1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/dmaengine.h>
23 #include <linux/spi/spi.h>
25 #define SUN6I_AUTOSUSPEND_TIMEOUT 2000
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_SDC BIT(11)
46 #define SUN6I_TFR_CTL_FBS BIT(12)
47 #define SUN6I_TFR_CTL_SDM BIT(13)
48 #define SUN6I_TFR_CTL_XCH BIT(31)
50 #define SUN6I_INT_CTL_REG 0x10
51 #define SUN6I_INT_CTL_RF_RDY BIT(0)
52 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
53 #define SUN6I_INT_CTL_RF_OVF BIT(8)
54 #define SUN6I_INT_CTL_TC BIT(12)
56 #define SUN6I_INT_STA_REG 0x14
58 #define SUN6I_FIFO_CTL_REG 0x18
59 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
60 #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
61 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
62 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
63 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
64 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
65 #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
66 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
68 #define SUN6I_FIFO_STA_REG 0x1c
69 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
70 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
72 #define SUN6I_CLK_CTL_REG 0x24
73 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
74 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
75 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
76 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
77 #define SUN6I_CLK_CTL_DRS BIT(12)
79 #define SUN6I_MAX_XFER_SIZE 0xffffff
81 #define SUN6I_BURST_CNT_REG 0x30
83 #define SUN6I_XMIT_CNT_REG 0x34
85 #define SUN6I_BURST_CTL_CNT_REG 0x38
87 #define SUN6I_TXDATA_REG 0x200
88 #define SUN6I_RXDATA_REG 0x300
90 struct sun6i_spi_cfg {
91 unsigned long fifo_depth;
96 struct spi_master *master;
97 void __iomem *base_addr;
98 dma_addr_t dma_addr_rx;
99 dma_addr_t dma_addr_tx;
102 struct reset_control *rstc;
104 struct completion done;
105 struct completion dma_rx_done;
110 const struct sun6i_spi_cfg *cfg;
113 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
115 return readl(sspi->base_addr + reg);
118 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
120 writel(value, sspi->base_addr + reg);
123 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
125 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
127 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
130 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
132 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
134 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
137 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
139 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
142 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
145 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
150 /* See how much data is available */
151 len = sun6i_spi_get_rx_fifo_count(sspi);
154 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
156 *sspi->rx_buf++ = byte;
160 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
166 /* See how much data we can fit */
167 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
169 len = min((int)cnt, sspi->len);
172 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
173 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
178 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
180 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
183 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
184 reg &= ~SUN6I_TFR_CTL_CS_MASK;
185 reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));
188 reg |= SUN6I_TFR_CTL_CS_LEVEL;
190 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
192 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
195 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
197 return SUN6I_MAX_XFER_SIZE - 1;
200 static void sun6i_spi_dma_rx_cb(void *param)
202 struct sun6i_spi *sspi = param;
204 complete(&sspi->dma_rx_done);
207 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
208 struct spi_transfer *tfr)
210 struct dma_async_tx_descriptor *rxdesc, *txdesc;
211 struct spi_master *master = sspi->master;
215 struct dma_slave_config rxconf = {
216 .direction = DMA_DEV_TO_MEM,
217 .src_addr = sspi->dma_addr_rx,
218 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
222 dmaengine_slave_config(master->dma_rx, &rxconf);
224 rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
231 rxdesc->callback_param = sspi;
232 rxdesc->callback = sun6i_spi_dma_rx_cb;
237 struct dma_slave_config txconf = {
238 .direction = DMA_MEM_TO_DEV,
239 .dst_addr = sspi->dma_addr_tx,
240 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
244 dmaengine_slave_config(master->dma_tx, &txconf);
246 txdesc = dmaengine_prep_slave_sg(master->dma_tx,
253 dmaengine_terminate_sync(master->dma_rx);
259 dmaengine_submit(rxdesc);
260 dma_async_issue_pending(master->dma_rx);
264 dmaengine_submit(txdesc);
265 dma_async_issue_pending(master->dma_tx);
271 static int sun6i_spi_transfer_one(struct spi_master *master,
272 struct spi_device *spi,
273 struct spi_transfer *tfr)
275 struct sun6i_spi *sspi = spi_master_get_devdata(master);
276 unsigned int div, div_cdr1, div_cdr2, timeout;
277 unsigned int start, end, tx_time;
278 unsigned int trig_level;
279 unsigned int tx_len = 0, rx_len = 0;
284 if (tfr->len > SUN6I_MAX_XFER_SIZE)
287 reinit_completion(&sspi->done);
288 reinit_completion(&sspi->dma_rx_done);
289 sspi->tx_buf = tfr->tx_buf;
290 sspi->rx_buf = tfr->rx_buf;
291 sspi->len = tfr->len;
292 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
294 /* Clear pending interrupts */
295 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
298 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
299 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
305 * Setup FIFO interrupt trigger level
306 * Here we choose 3/4 of the full fifo depth, as it's
307 * the hardcoded value used in old generation of Allwinner
308 * SPI controller. (See spi-sun4i.c)
310 trig_level = sspi->cfg->fifo_depth / 4 * 3;
313 * Setup FIFO DMA request trigger level
314 * We choose 1/2 of the full fifo depth, that value will
315 * be used as DMA burst length.
317 trig_level = sspi->cfg->fifo_depth / 2;
320 reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
322 reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
325 reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
326 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
328 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
331 * Setup the transfer control register: Chip Select,
334 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
336 if (spi->mode & SPI_CPOL)
337 reg |= SUN6I_TFR_CTL_CPOL;
339 reg &= ~SUN6I_TFR_CTL_CPOL;
341 if (spi->mode & SPI_CPHA)
342 reg |= SUN6I_TFR_CTL_CPHA;
344 reg &= ~SUN6I_TFR_CTL_CPHA;
346 if (spi->mode & SPI_LSB_FIRST)
347 reg |= SUN6I_TFR_CTL_FBS;
349 reg &= ~SUN6I_TFR_CTL_FBS;
352 * If it's a TX only transfer, we don't want to fill the RX
353 * FIFO with bogus data
356 reg &= ~SUN6I_TFR_CTL_DHB;
359 reg |= SUN6I_TFR_CTL_DHB;
362 /* We want to control the chip select manually */
363 reg |= SUN6I_TFR_CTL_CS_MANUAL;
365 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
367 if (sspi->cfg->has_clk_ctl) {
368 unsigned int mclk_rate = clk_get_rate(sspi->mclk);
370 /* Ensure that we have a parent clock fast enough */
371 if (mclk_rate < (2 * tfr->speed_hz)) {
372 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
373 mclk_rate = clk_get_rate(sspi->mclk);
377 * Setup clock divider.
379 * We have two choices there. Either we can use the clock
380 * divide rate 1, which is calculated thanks to this formula:
381 * SPI_CLK = MOD_CLK / (2 ^ cdr)
382 * Or we can use CDR2, which is calculated with the formula:
383 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
384 * Wether we use the former or the latter is set through the
387 * First try CDR2, and if we can't reach the expected
388 * frequency, fall back to CDR1.
390 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
391 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
392 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
393 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
394 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
396 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
397 reg = SUN6I_CLK_CTL_CDR1(div);
398 tfr->effective_speed_hz = mclk_rate / (1 << div);
401 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
403 clk_set_rate(sspi->mclk, tfr->speed_hz);
404 tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
407 * Configure work mode.
409 * There are three work modes depending on the controller clock
411 * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0
412 * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0
413 * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1
415 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
416 reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC);
418 if (tfr->effective_speed_hz <= 24000000)
419 reg |= SUN6I_TFR_CTL_SDM;
420 else if (tfr->effective_speed_hz >= 80000000)
421 reg |= SUN6I_TFR_CTL_SDC;
423 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
426 /* Finally enable the bus - doing so before might raise SCK to HIGH */
427 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
428 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
429 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
431 /* Setup the transfer now... */
435 /* Setup the counters */
436 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
437 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
438 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
441 /* Fill the TX FIFO */
442 sun6i_spi_fill_fifo(sspi);
444 ret = sun6i_spi_prepare_dma(sspi, tfr);
446 dev_warn(&master->dev,
447 "%s: prepare DMA failed, ret=%d",
448 dev_name(&spi->dev), ret);
453 /* Enable the interrupts */
454 reg = SUN6I_INT_CTL_TC;
457 if (rx_len > sspi->cfg->fifo_depth)
458 reg |= SUN6I_INT_CTL_RF_RDY;
459 if (tx_len > sspi->cfg->fifo_depth)
460 reg |= SUN6I_INT_CTL_TF_ERQ;
463 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
465 /* Start the transfer */
466 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
467 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
469 tx_time = spi_controller_xfer_timeout(master, tfr);
471 timeout = wait_for_completion_timeout(&sspi->done,
472 msecs_to_jiffies(tx_time));
475 sun6i_spi_drain_fifo(sspi);
477 if (timeout && rx_len) {
479 * Even though RX on the peripheral side has finished
480 * RX DMA might still be in flight
482 timeout = wait_for_completion_timeout(&sspi->dma_rx_done,
485 dev_warn(&master->dev, "RX DMA timeout\n");
491 dev_warn(&master->dev,
492 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
493 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
494 jiffies_to_msecs(end - start), tx_time);
498 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
500 if (ret && use_dma) {
501 dmaengine_terminate_sync(master->dma_rx);
502 dmaengine_terminate_sync(master->dma_tx);
508 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
510 struct sun6i_spi *sspi = dev_id;
511 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
513 /* Transfer complete */
514 if (status & SUN6I_INT_CTL_TC) {
515 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
516 complete(&sspi->done);
520 /* Receive FIFO 3/4 full */
521 if (status & SUN6I_INT_CTL_RF_RDY) {
522 sun6i_spi_drain_fifo(sspi);
523 /* Only clear the interrupt _after_ draining the FIFO */
524 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
528 /* Transmit FIFO 3/4 empty */
529 if (status & SUN6I_INT_CTL_TF_ERQ) {
530 sun6i_spi_fill_fifo(sspi);
533 /* nothing left to transmit */
534 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
536 /* Only clear the interrupt _after_ re-seeding the FIFO */
537 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
545 static int sun6i_spi_runtime_resume(struct device *dev)
547 struct spi_master *master = dev_get_drvdata(dev);
548 struct sun6i_spi *sspi = spi_master_get_devdata(master);
551 ret = clk_prepare_enable(sspi->hclk);
553 dev_err(dev, "Couldn't enable AHB clock\n");
557 ret = clk_prepare_enable(sspi->mclk);
559 dev_err(dev, "Couldn't enable module clock\n");
563 ret = reset_control_deassert(sspi->rstc);
565 dev_err(dev, "Couldn't deassert the device from reset\n");
569 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
570 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
575 clk_disable_unprepare(sspi->mclk);
577 clk_disable_unprepare(sspi->hclk);
582 static int sun6i_spi_runtime_suspend(struct device *dev)
584 struct spi_master *master = dev_get_drvdata(dev);
585 struct sun6i_spi *sspi = spi_master_get_devdata(master);
587 reset_control_assert(sspi->rstc);
588 clk_disable_unprepare(sspi->mclk);
589 clk_disable_unprepare(sspi->hclk);
594 static bool sun6i_spi_can_dma(struct spi_master *master,
595 struct spi_device *spi,
596 struct spi_transfer *xfer)
598 struct sun6i_spi *sspi = spi_master_get_devdata(master);
601 * If the number of spi words to transfer is less or equal than
602 * the fifo length we can just fill the fifo and wait for a single
603 * irq, so don't bother setting up dma
605 return xfer->len > sspi->cfg->fifo_depth;
608 static int sun6i_spi_probe(struct platform_device *pdev)
610 struct spi_master *master;
611 struct sun6i_spi *sspi;
612 struct resource *mem;
615 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
617 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
621 platform_set_drvdata(pdev, master);
622 sspi = spi_master_get_devdata(master);
624 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
625 if (IS_ERR(sspi->base_addr)) {
626 ret = PTR_ERR(sspi->base_addr);
627 goto err_free_master;
630 irq = platform_get_irq(pdev, 0);
633 goto err_free_master;
636 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
637 0, "sun6i-spi", sspi);
639 dev_err(&pdev->dev, "Cannot request IRQ\n");
640 goto err_free_master;
643 sspi->master = master;
644 sspi->cfg = of_device_get_match_data(&pdev->dev);
646 master->max_speed_hz = 100 * 1000 * 1000;
647 master->min_speed_hz = 3 * 1000;
648 master->use_gpio_descriptors = true;
649 master->set_cs = sun6i_spi_set_cs;
650 master->transfer_one = sun6i_spi_transfer_one;
651 master->num_chipselect = 4;
652 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
653 master->bits_per_word_mask = SPI_BPW_MASK(8);
654 master->dev.of_node = pdev->dev.of_node;
655 master->auto_runtime_pm = true;
656 master->max_transfer_size = sun6i_spi_max_transfer_size;
658 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
659 if (IS_ERR(sspi->hclk)) {
660 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
661 ret = PTR_ERR(sspi->hclk);
662 goto err_free_master;
665 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
666 if (IS_ERR(sspi->mclk)) {
667 dev_err(&pdev->dev, "Unable to acquire module clock\n");
668 ret = PTR_ERR(sspi->mclk);
669 goto err_free_master;
672 init_completion(&sspi->done);
673 init_completion(&sspi->dma_rx_done);
675 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
676 if (IS_ERR(sspi->rstc)) {
677 dev_err(&pdev->dev, "Couldn't get reset controller\n");
678 ret = PTR_ERR(sspi->rstc);
679 goto err_free_master;
682 master->dma_tx = dma_request_chan(&pdev->dev, "tx");
683 if (IS_ERR(master->dma_tx)) {
684 /* Check tx to see if we need defer probing driver */
685 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
687 goto err_free_master;
689 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
690 master->dma_tx = NULL;
693 master->dma_rx = dma_request_chan(&pdev->dev, "rx");
694 if (IS_ERR(master->dma_rx)) {
695 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
697 goto err_free_dma_tx;
699 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
700 master->dma_rx = NULL;
703 if (master->dma_tx && master->dma_rx) {
704 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
705 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
706 master->can_dma = sun6i_spi_can_dma;
710 * This wake-up/shutdown pattern is to be able to have the
711 * device woken up, even if runtime_pm is disabled
713 ret = sun6i_spi_runtime_resume(&pdev->dev);
715 dev_err(&pdev->dev, "Couldn't resume the device\n");
716 goto err_free_dma_rx;
719 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
720 pm_runtime_use_autosuspend(&pdev->dev);
721 pm_runtime_set_active(&pdev->dev);
722 pm_runtime_enable(&pdev->dev);
724 ret = devm_spi_register_master(&pdev->dev, master);
726 dev_err(&pdev->dev, "cannot register SPI master\n");
733 pm_runtime_disable(&pdev->dev);
734 sun6i_spi_runtime_suspend(&pdev->dev);
737 dma_release_channel(master->dma_rx);
740 dma_release_channel(master->dma_tx);
742 spi_master_put(master);
746 static void sun6i_spi_remove(struct platform_device *pdev)
748 struct spi_master *master = platform_get_drvdata(pdev);
750 pm_runtime_force_suspend(&pdev->dev);
753 dma_release_channel(master->dma_tx);
755 dma_release_channel(master->dma_rx);
758 static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = {
759 .fifo_depth = SUN6I_FIFO_DEPTH,
763 static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = {
764 .fifo_depth = SUN8I_FIFO_DEPTH,
768 static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
769 .fifo_depth = SUN8I_FIFO_DEPTH,
772 static const struct of_device_id sun6i_spi_match[] = {
773 { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
774 { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
776 .compatible = "allwinner,sun50i-r329-spi",
777 .data = &sun50i_r329_spi_cfg
781 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
783 static const struct dev_pm_ops sun6i_spi_pm_ops = {
784 .runtime_resume = sun6i_spi_runtime_resume,
785 .runtime_suspend = sun6i_spi_runtime_suspend,
788 static struct platform_driver sun6i_spi_driver = {
789 .probe = sun6i_spi_probe,
790 .remove_new = sun6i_spi_remove,
793 .of_match_table = sun6i_spi_match,
794 .pm = &sun6i_spi_pm_ops,
797 module_platform_driver(sun6i_spi_driver);
799 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
800 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
801 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
802 MODULE_LICENSE("GPL");