2 * Xilinx SPI controller driver (master mode only)
4 * Author: MontaVista Software, Inc.
7 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/spi/xilinx_spi.h>
25 #define XILINX_SPI_MAX_CS 32
27 #define XILINX_SPI_NAME "xilinx_spi"
29 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
30 * Product Specification", DS464
32 #define XSPI_CR_OFFSET 0x60 /* Control Register */
34 #define XSPI_CR_LOOP 0x01
35 #define XSPI_CR_ENABLE 0x02
36 #define XSPI_CR_MASTER_MODE 0x04
37 #define XSPI_CR_CPOL 0x08
38 #define XSPI_CR_CPHA 0x10
39 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
40 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
41 #define XSPI_CR_TXFIFO_RESET 0x20
42 #define XSPI_CR_RXFIFO_RESET 0x40
43 #define XSPI_CR_MANUAL_SSELECT 0x80
44 #define XSPI_CR_TRANS_INHIBIT 0x100
45 #define XSPI_CR_LSB_FIRST 0x200
47 #define XSPI_SR_OFFSET 0x64 /* Status Register */
49 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
50 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
51 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
52 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
53 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
55 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
56 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
58 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
60 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
61 * IPIF registers are 32 bit
63 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
64 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
66 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
67 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
69 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
70 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
72 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
73 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
74 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
75 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
76 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
78 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
79 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
82 /* bitbang has to be first */
83 struct spi_bitbang bitbang;
84 struct completion done;
85 void __iomem *regs; /* virt. address of the control registers */
89 u8 *rx_ptr; /* pointer in the Tx buffer */
90 const u8 *tx_ptr; /* pointer in the Rx buffer */
92 int buffer_size; /* buffer size in words */
93 u32 cs_inactive; /* Level of the CS pins when inactive*/
94 unsigned int (*read_fn)(void __iomem *);
95 void (*write_fn)(u32, void __iomem *);
98 static void xspi_write32(u32 val, void __iomem *addr)
100 iowrite32(val, addr);
103 static unsigned int xspi_read32(void __iomem *addr)
105 return ioread32(addr);
108 static void xspi_write32_be(u32 val, void __iomem *addr)
110 iowrite32be(val, addr);
113 static unsigned int xspi_read32_be(void __iomem *addr)
115 return ioread32be(addr);
118 static void xilinx_spi_tx(struct xilinx_spi *xspi)
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
124 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
125 xspi->tx_ptr += xspi->bytes_per_word;
128 static void xilinx_spi_rx(struct xilinx_spi *xspi)
130 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
135 switch (xspi->bytes_per_word) {
137 *(u8 *)(xspi->rx_ptr) = data;
140 *(u16 *)(xspi->rx_ptr) = data;
143 *(u32 *)(xspi->rx_ptr) = data;
147 xspi->rx_ptr += xspi->bytes_per_word;
150 static void xspi_init_hw(struct xilinx_spi *xspi)
152 void __iomem *regs_base = xspi->regs;
154 /* Reset the SPI device */
155 xspi->write_fn(XIPIF_V123B_RESET_MASK,
156 regs_base + XIPIF_V123B_RESETR_OFFSET);
157 /* Enable the transmit empty interrupt, which we use to determine
158 * progress on the transmission.
160 xspi->write_fn(XSPI_INTR_TX_EMPTY,
161 regs_base + XIPIF_V123B_IIER_OFFSET);
162 /* Disable the global IPIF interrupt */
163 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
164 /* Deselect the slave on the SPI bus */
165 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
166 /* Disable the transmitter, enable Manual Slave Select Assertion,
167 * put SPI controller into master mode, and enable it */
168 xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
169 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
170 regs_base + XSPI_CR_OFFSET);
173 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
175 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
179 if (is_on == BITBANG_CS_INACTIVE) {
180 /* Deselect the slave on the SPI bus */
181 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
185 /* Set the SPI clock phase and polarity */
186 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
187 if (spi->mode & SPI_CPHA)
189 if (spi->mode & SPI_CPOL)
191 if (spi->mode & SPI_LSB_FIRST)
192 cr |= XSPI_CR_LSB_FIRST;
193 if (spi->mode & SPI_LOOP)
195 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
197 /* We do not check spi->max_speed_hz here as the SPI clock
198 * frequency is not software programmable (the IP block design
202 cs = xspi->cs_inactive;
203 cs ^= BIT(spi->chip_select);
205 /* Activate the chip select */
206 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
209 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
210 * custom txrx_bufs().
212 static int xilinx_spi_setup_transfer(struct spi_device *spi,
213 struct spi_transfer *t)
215 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
217 if (spi->mode & SPI_CS_HIGH)
218 xspi->cs_inactive &= ~BIT(spi->chip_select);
220 xspi->cs_inactive |= BIT(spi->chip_select);
225 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
227 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
228 int remaining_words; /* the number of words left to transfer */
229 bool use_irq = false;
232 /* We get here with transmitter inhibited */
234 xspi->tx_ptr = t->tx_buf;
235 xspi->rx_ptr = t->rx_buf;
236 remaining_words = t->len / xspi->bytes_per_word;
237 reinit_completion(&xspi->done);
239 if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
241 xspi->write_fn(XSPI_INTR_TX_EMPTY,
242 xspi->regs + XIPIF_V123B_IISR_OFFSET);
243 /* Enable the global IPIF interrupt */
244 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
245 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
246 /* Inhibit irq to avoid spurious irqs on tx_empty*/
247 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
248 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
249 xspi->regs + XSPI_CR_OFFSET);
252 while (remaining_words) {
253 int n_words, tx_words, rx_words;
255 n_words = min(remaining_words, xspi->buffer_size);
261 /* Start the transfer by not inhibiting the transmitter any
266 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
267 wait_for_completion(&xspi->done);
269 while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) &
270 XSPI_SR_TX_EMPTY_MASK))
273 /* A transmit has just completed. Process received data and
274 * check for more data to transmit. Always inhibit the
275 * transmitter while the Isr refills the transmit register/FIFO,
276 * or make sure it is stopped if we're done.
279 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
280 xspi->regs + XSPI_CR_OFFSET);
282 /* Read out all the data from the Rx FIFO */
287 remaining_words -= n_words;
291 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
297 /* This driver supports single master mode only. Hence Tx FIFO Empty
298 * is the only interrupt we care about.
299 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
300 * Fault are not to happen.
302 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
304 struct xilinx_spi *xspi = dev_id;
307 /* Get the IPIF interrupts, and clear them immediately */
308 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
309 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
311 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
312 complete(&xspi->done);
318 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
324 * Before the buffer_size detection we reset the core
325 * to make sure we start with a clean state.
327 xspi->write_fn(XIPIF_V123B_RESET_MASK,
328 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
330 /* Fill the Tx FIFO with as many words as possible */
332 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
333 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
335 } while (!(sr & XSPI_SR_TX_FULL_MASK));
340 static const struct of_device_id xilinx_spi_of_match[] = {
341 { .compatible = "xlnx,xps-spi-2.00.a", },
342 { .compatible = "xlnx,xps-spi-2.00.b", },
345 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
347 static int xilinx_spi_probe(struct platform_device *pdev)
349 struct xilinx_spi *xspi;
350 struct xspi_platform_data *pdata;
351 struct resource *res;
352 int ret, num_cs = 0, bits_per_word = 8;
353 struct spi_master *master;
357 pdata = dev_get_platdata(&pdev->dev);
359 num_cs = pdata->num_chipselect;
360 bits_per_word = pdata->bits_per_word;
362 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
368 "Missing slave select configuration data\n");
372 if (num_cs > XILINX_SPI_MAX_CS) {
373 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
377 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
381 /* the spi->mode bits understood by this driver: */
382 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
385 xspi = spi_master_get_devdata(master);
386 xspi->cs_inactive = 0xffffffff;
387 xspi->bitbang.master = master;
388 xspi->bitbang.chipselect = xilinx_spi_chipselect;
389 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
390 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
391 init_completion(&xspi->done);
393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
394 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
395 if (IS_ERR(xspi->regs)) {
396 ret = PTR_ERR(xspi->regs);
400 master->bus_num = pdev->id;
401 master->num_chipselect = num_cs;
402 master->dev.of_node = pdev->dev.of_node;
405 * Detect endianess on the IP via loop bit in CR. Detection
406 * must be done before reset is sent because incorrect reset
407 * value generates error interrupt.
408 * Setup little endian helper functions first and try to use them
409 * and check if bit was correctly setup or not.
411 xspi->read_fn = xspi_read32;
412 xspi->write_fn = xspi_write32;
414 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
415 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
417 if (tmp != XSPI_CR_LOOP) {
418 xspi->read_fn = xspi_read32_be;
419 xspi->write_fn = xspi_write32_be;
422 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
423 xspi->bytes_per_word = bits_per_word / 8;
424 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
426 xspi->irq = platform_get_irq(pdev, 0);
427 if (xspi->irq >= 0) {
428 /* Register for SPI Interrupt */
429 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
430 dev_name(&pdev->dev), xspi);
435 /* SPI controller initializations */
438 ret = spi_bitbang_start(&xspi->bitbang);
440 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
444 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
445 (unsigned long long)res->start, xspi->regs, xspi->irq);
448 for (i = 0; i < pdata->num_devices; i++)
449 spi_new_device(master, pdata->devices + i);
452 platform_set_drvdata(pdev, master);
456 spi_master_put(master);
461 static int xilinx_spi_remove(struct platform_device *pdev)
463 struct spi_master *master = platform_get_drvdata(pdev);
464 struct xilinx_spi *xspi = spi_master_get_devdata(master);
465 void __iomem *regs_base = xspi->regs;
467 spi_bitbang_stop(&xspi->bitbang);
469 /* Disable all the interrupts just in case */
470 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
471 /* Disable the global IPIF interrupt */
472 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
474 spi_master_put(xspi->bitbang.master);
479 /* work with hotplug and coldplug */
480 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
482 static struct platform_driver xilinx_spi_driver = {
483 .probe = xilinx_spi_probe,
484 .remove = xilinx_spi_remove,
486 .name = XILINX_SPI_NAME,
487 .of_match_table = xilinx_spi_of_match,
490 module_platform_driver(xilinx_spi_driver);
492 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
493 MODULE_DESCRIPTION("Xilinx SPI driver");
494 MODULE_LICENSE("GPL");