drivers/staging/comedi/drivers/ni_65xx.c

   1 /*
   2     comedi/drivers/ni_6514.c
   3     driver for National Instruments PCI-6514
   4
   5     Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
   6     Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   7
   8     COMEDI - Linux Control and Measurement Device Interface
   9     Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
  10
  11     This program is free software; you can redistribute it and/or modify
  12     it under the terms of the GNU General Public License as published by
  13     the Free Software Foundation; either version 2 of the License, or
  14     (at your option) any later version.
  15
  16     This program is distributed in the hope that it will be useful,
  17     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19     GNU General Public License for more details.
  20 */
  21 /*
  22 Driver: ni_65xx
  23 Description: National Instruments 65xx static dio boards
  24 Author: Jon Grierson <jd@renko.co.uk>,
  25         Frank Mori Hess <fmhess@users.sourceforge.net>
  26 Status: testing
  27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
  28   PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
  29   PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
  30   PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
  31 Updated: Wed Oct 18 08:59:11 EDT 2006
  32
  33 Based on the PCI-6527 driver by ds.
  34 The interrupt subdevice (subdevice 3) is probably broken for all boards
  35 except maybe the 6514.
  36
  37 */
  38
  39 /*
  40    Manuals (available from ftp://ftp.natinst.com/support/manuals)
  41
  42         370106b.pdf     6514 Register Level Programmer Manual
  43
  44  */
  45
  46 #define DEBUG 1
  47 #define DEBUG_FLAGS
  48
  49 #include <linux/module.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52
  53 #include "../comedidev.h"
  54
  55 #include "comedi_fc.h"
  56 #include "mite.h"
  57
  58 #define NI6514_DIO_SIZE 4096
  59 #define NI6514_MITE_SIZE 4096
  60
  61 #define NI_65XX_MAX_NUM_PORTS 12
  62 static const unsigned ni_65xx_channels_per_port = 8;
  63 static const unsigned ni_65xx_port_offset = 0x10;
  64
  65 static inline unsigned Port_Data(unsigned port)
  66 {
  67         return 0x40 + port * ni_65xx_port_offset;
  68 }
  69
  70 static inline unsigned Port_Select(unsigned port)
  71 {
  72         return 0x41 + port * ni_65xx_port_offset;
  73 }
  74
  75 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
  76 {
  77         return 0x42 + port * ni_65xx_port_offset;
  78 }
  79
  80 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
  81 {
  82         return 0x43 + port * ni_65xx_port_offset;
  83 }
  84
  85 static inline unsigned Filter_Enable(unsigned port)
  86 {
  87         return 0x44 + port * ni_65xx_port_offset;
  88 }
  89
  90 #define ID_Register                             0x00
  91
  92 #define Clear_Register                          0x01
  93 #define ClrEdge                         0x08
  94 #define ClrOverflow                     0x04
  95
  96 #define Filter_Interval                 0x08
  97
  98 #define Change_Status                           0x02
  99 #define MasterInterruptStatus           0x04
 100 #define Overflow                        0x02
 101 #define EdgeStatus                      0x01
 102
 103 #define Master_Interrupt_Control                0x03
 104 #define FallingEdgeIntEnable            0x10
 105 #define RisingEdgeIntEnable             0x08
 106 #define MasterInterruptEnable           0x04
 107 #define OverflowIntEnable               0x02
 108 #define EdgeIntEnable                   0x01
 109
 110 enum ni_65xx_boardid {
 111         BOARD_PCI6509,
 112         BOARD_PXI6509,
 113         BOARD_PCI6510,
 114         BOARD_PCI6511,
 115         BOARD_PXI6511,
 116         BOARD_PCI6512,
 117         BOARD_PXI6512,
 118         BOARD_PCI6513,
 119         BOARD_PXI6513,
 120         BOARD_PCI6514,
 121         BOARD_PXI6514,
 122         BOARD_PCI6515,
 123         BOARD_PXI6515,
 124         BOARD_PCI6516,
 125         BOARD_PCI6517,
 126         BOARD_PCI6518,
 127         BOARD_PCI6519,
 128         BOARD_PCI6520,
 129         BOARD_PCI6521,
 130         BOARD_PXI6521,
 131         BOARD_PCI6528,
 132         BOARD_PXI6528,
 133 };
 134
 135 struct ni_65xx_board {
 136         const char *name;
 137         unsigned num_dio_ports;
 138         unsigned num_di_ports;
 139         unsigned num_do_ports;
 140         unsigned invert_outputs:1;
 141 };
 142
 143 static const struct ni_65xx_board ni_65xx_boards[] = {
 144         [BOARD_PCI6509] = {
 145                 .name           = "pci-6509",
 146                 .num_dio_ports  = 12,
 147         },
 148         [BOARD_PXI6509] = {
 149                 .name           = "pxi-6509",
 150                 .num_dio_ports  = 12,
 151         },
 152         [BOARD_PCI6510] = {
 153                 .name           = "pci-6510",
 154                 .num_di_ports   = 4,
 155         },
 156         [BOARD_PCI6511] = {
 157                 .name           = "pci-6511",
 158                 .num_di_ports   = 8,
 159         },
 160         [BOARD_PXI6511] = {
 161                 .name           = "pxi-6511",
 162                 .num_di_ports   = 8,
 163         },
 164         [BOARD_PCI6512] = {
 165                 .name           = "pci-6512",
 166                 .num_do_ports   = 8,
 167         },
 168         [BOARD_PXI6512] = {
 169                 .name           = "pxi-6512",
 170                 .num_do_ports   = 8,
 171         },
 172         [BOARD_PCI6513] = {
 173                 .name           = "pci-6513",
 174                 .num_do_ports   = 8,
 175                 .invert_outputs = 1,
 176         },
 177         [BOARD_PXI6513] = {
 178                 .name           = "pxi-6513",
 179                 .num_do_ports   = 8,
 180                 .invert_outputs = 1,
 181         },
 182         [BOARD_PCI6514] = {
 183                 .name           = "pci-6514",
 184                 .num_di_ports   = 4,
 185                 .num_do_ports   = 4,
 186                 .invert_outputs = 1,
 187         },
 188         [BOARD_PXI6514] = {
 189                 .name           = "pxi-6514",
 190                 .num_di_ports   = 4,
 191                 .num_do_ports   = 4,
 192                 .invert_outputs = 1,
 193         },
 194         [BOARD_PCI6515] = {
 195                 .name           = "pci-6515",
 196                 .num_di_ports   = 4,
 197                 .num_do_ports   = 4,
 198                 .invert_outputs = 1,
 199         },
 200         [BOARD_PXI6515] = {
 201                 .name           = "pxi-6515",
 202                 .num_di_ports   = 4,
 203                 .num_do_ports   = 4,
 204                 .invert_outputs = 1,
 205         },
 206         [BOARD_PCI6516] = {
 207                 .name           = "pci-6516",
 208                 .num_do_ports   = 4,
 209                 .invert_outputs = 1,
 210         },
 211         [BOARD_PCI6517] = {
 212                 .name           = "pci-6517",
 213                 .num_do_ports   = 4,
 214                 .invert_outputs = 1,
 215         },
 216         [BOARD_PCI6518] = {
 217                 .name           = "pci-6518",
 218                 .num_di_ports   = 2,
 219                 .num_do_ports   = 2,
 220                 .invert_outputs = 1,
 221         },
 222         [BOARD_PCI6519] = {
 223                 .name           = "pci-6519",
 224                 .num_di_ports   = 2,
 225                 .num_do_ports   = 2,
 226                 .invert_outputs = 1,
 227         },
 228         [BOARD_PCI6520] = {
 229                 .name           = "pci-6520",
 230                 .num_di_ports   = 1,
 231                 .num_do_ports   = 1,
 232         },
 233         [BOARD_PCI6521] = {
 234                 .name           = "pci-6521",
 235                 .num_di_ports   = 1,
 236                 .num_do_ports   = 1,
 237         },
 238         [BOARD_PXI6521] = {
 239                 .name           = "pxi-6521",
 240                 .num_di_ports   = 1,
 241                 .num_do_ports   = 1,
 242         },
 243         [BOARD_PCI6528] = {
 244                 .name           = "pci-6528",
 245                 .num_di_ports   = 3,
 246                 .num_do_ports   = 3,
 247         },
 248         [BOARD_PXI6528] = {
 249                 .name           = "pxi-6528",
 250                 .num_di_ports   = 3,
 251                 .num_do_ports   = 3,
 252         },
 253 };
 254
 255 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
 256 {
 257         return channel / ni_65xx_channels_per_port;
 258 }
 259
 260 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
 261                                                *board)
 262 {
 263         return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
 264 }
 265
 266 struct ni_65xx_private {
 267         struct mite_struct *mite;
 268         unsigned int filter_interval;
 269         unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
 270         unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
 271         unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
 272 };
 273
 274 struct ni_65xx_subdevice_private {
 275         unsigned base_port;
 276 };
 277
 278 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
 279                                                          *subdev)
 280 {
 281         return subdev->private;
 282 }
 283
 284 static int ni_65xx_config_filter(struct comedi_device *dev,
 285                                  struct comedi_subdevice *s,
 286                                  struct comedi_insn *insn, unsigned int *data)
 287 {
 288         struct ni_65xx_private *devpriv = dev->private;
 289         const unsigned chan = CR_CHAN(insn->chanspec);
 290         const unsigned port =
 291             sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
 292
 293         if (data[0] != INSN_CONFIG_FILTER)
 294                 return -EINVAL;
 295         if (data[1]) {
 296                 static const unsigned filter_resolution_ns = 200;
 297                 static const unsigned max_filter_interval = 0xfffff;
 298                 unsigned interval =
 299                     (data[1] +
 300                      (filter_resolution_ns / 2)) / filter_resolution_ns;
 301                 if (interval > max_filter_interval)
 302                         interval = max_filter_interval;
 303                 data[1] = interval * filter_resolution_ns;
 304
 305                 if (interval != devpriv->filter_interval) {
 306                         writeb(interval,
 307                                devpriv->mite->daq_io_addr +
 308                                Filter_Interval);
 309                         devpriv->filter_interval = interval;
 310                 }
 311
 312                 devpriv->filter_enable[port] |=
 313                     1 << (chan % ni_65xx_channels_per_port);
 314         } else {
 315                 devpriv->filter_enable[port] &=
 316                     ~(1 << (chan % ni_65xx_channels_per_port));
 317         }
 318
 319         writeb(devpriv->filter_enable[port],
 320                devpriv->mite->daq_io_addr + Filter_Enable(port));
 321
 322         return 2;
 323 }
 324
 325 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
 326                                    struct comedi_subdevice *s,
 327                                    struct comedi_insn *insn, unsigned int *data)
 328 {
 329         struct ni_65xx_private *devpriv = dev->private;
 330         unsigned port;
 331
 332         if (insn->n < 1)
 333                 return -EINVAL;
 334         port = sprivate(s)->base_port +
 335             ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
 336         switch (data[0]) {
 337         case INSN_CONFIG_FILTER:
 338                 return ni_65xx_config_filter(dev, s, insn, data);
 339                 break;
 340         case INSN_CONFIG_DIO_OUTPUT:
 341                 if (s->type != COMEDI_SUBD_DIO)
 342                         return -EINVAL;
 343                 devpriv->dio_direction[port] = COMEDI_OUTPUT;
 344                 writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
 345                 return 1;
 346                 break;
 347         case INSN_CONFIG_DIO_INPUT:
 348                 if (s->type != COMEDI_SUBD_DIO)
 349                         return -EINVAL;
 350                 devpriv->dio_direction[port] = COMEDI_INPUT;
 351                 writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
 352                 return 1;
 353                 break;
 354         case INSN_CONFIG_DIO_QUERY:
 355                 if (s->type != COMEDI_SUBD_DIO)
 356                         return -EINVAL;
 357                 data[1] = devpriv->dio_direction[port];
 358                 return insn->n;
 359                 break;
 360         default:
 361                 break;
 362         }
 363         return -EINVAL;
 364 }
 365
 366 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
 367                                  struct comedi_subdevice *s,
 368                                  struct comedi_insn *insn, unsigned int *data)
 369 {
 370         const struct ni_65xx_board *board = comedi_board(dev);
 371         struct ni_65xx_private *devpriv = dev->private;
 372         int base_bitfield_channel;
 373         unsigned read_bits = 0;
 374         int last_port_offset = ni_65xx_port_by_channel(s->n_chan - 1);
 375         int port_offset;
 376
 377         base_bitfield_channel = CR_CHAN(insn->chanspec);
 378         for (port_offset = ni_65xx_port_by_channel(base_bitfield_channel);
 379              port_offset <= last_port_offset; port_offset++) {
 380                 unsigned port = sprivate(s)->base_port + port_offset;
 381                 int base_port_channel = port_offset * ni_65xx_channels_per_port;
 382                 unsigned port_mask, port_data, port_read_bits;
 383                 int bitshift = base_port_channel - base_bitfield_channel;
 384
 385                 if (bitshift >= 32)
 386                         break;
 387                 port_mask = data[0];
 388                 port_data = data[1];
 389                 if (bitshift > 0) {
 390                         port_mask >>= bitshift;
 391                         port_data >>= bitshift;
 392                 } else {
 393                         port_mask <<= -bitshift;
 394                         port_data <<= -bitshift;
 395                 }
 396                 port_mask &= 0xff;
 397                 port_data &= 0xff;
 398                 if (port_mask) {
 399                         unsigned bits;
 400                         devpriv->output_bits[port] &= ~port_mask;
 401                         devpriv->output_bits[port] |=
 402                             port_data & port_mask;
 403                         bits = devpriv->output_bits[port];
 404                         if (board->invert_outputs)
 405                                 bits = ~bits;
 406                         writeb(bits,
 407                                devpriv->mite->daq_io_addr +
 408                                Port_Data(port));
 409                 }
 410                 port_read_bits =
 411                     readb(devpriv->mite->daq_io_addr + Port_Data(port));
 412                 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
 413                         /* Outputs inverted, so invert value read back from
 414                          * DO subdevice.  (Does not apply to boards with DIO
 415                          * subdevice.) */
 416                         port_read_bits ^= 0xFF;
 417                 }
 418                 if (bitshift > 0)
 419                         port_read_bits <<= bitshift;
 420                 else
 421                         port_read_bits >>= -bitshift;
 422
 423                 read_bits |= port_read_bits;
 424         }
 425         data[1] = read_bits;
 426         return insn->n;
 427 }
 428
 429 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
 430 {
 431         struct comedi_device *dev = d;
 432         struct ni_65xx_private *devpriv = dev->private;
 433         struct comedi_subdevice *s = &dev->subdevices[2];
 434         unsigned int status;
 435
 436         status = readb(devpriv->mite->daq_io_addr + Change_Status);
 437         if ((status & MasterInterruptStatus) == 0)
 438                 return IRQ_NONE;
 439         if ((status & EdgeStatus) == 0)
 440                 return IRQ_NONE;
 441
 442         writeb(ClrEdge | ClrOverflow,
 443                devpriv->mite->daq_io_addr + Clear_Register);
 444
 445         comedi_buf_put(s->async, 0);
 446         s->async->events |= COMEDI_CB_EOS;
 447         comedi_event(dev, s);
 448         return IRQ_HANDLED;
 449 }
 450
 451 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
 452                                 struct comedi_subdevice *s,
 453                                 struct comedi_cmd *cmd)
 454 {
 455         int err = 0;
 456
 457         /* Step 1 : check if triggers are trivially valid */
 458
 459         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
 460         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
 461         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 462         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 463         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
 464
 465         if (err)
 466                 return 1;
 467
 468         /* Step 2a : make sure trigger sources are unique */
 469         /* Step 2b : and mutually compatible */
 470
 471         if (err)
 472                 return 2;
 473
 474         /* Step 3: check if arguments are trivially valid */
 475
 476         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 477         err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 478         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 479         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
 480         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 481
 482         if (err)
 483                 return 3;
 484
 485         /* step 4: fix up any arguments */
 486
 487         if (err)
 488                 return 4;
 489
 490         return 0;
 491 }
 492
 493 static int ni_65xx_intr_cmd(struct comedi_device *dev,
 494                             struct comedi_subdevice *s)
 495 {
 496         struct ni_65xx_private *devpriv = dev->private;
 497         /* struct comedi_cmd *cmd = &s->async->cmd; */
 498
 499         writeb(ClrEdge | ClrOverflow,
 500                devpriv->mite->daq_io_addr + Clear_Register);
 501         writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
 502                MasterInterruptEnable | EdgeIntEnable,
 503                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 504
 505         return 0;
 506 }
 507
 508 static int ni_65xx_intr_cancel(struct comedi_device *dev,
 509                                struct comedi_subdevice *s)
 510 {
 511         struct ni_65xx_private *devpriv = dev->private;
 512
 513         writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 514
 515         return 0;
 516 }
 517
 518 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
 519                                   struct comedi_subdevice *s,
 520                                   struct comedi_insn *insn, unsigned int *data)
 521 {
 522         data[1] = 0;
 523         return insn->n;
 524 }
 525
 526 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
 527                                     struct comedi_subdevice *s,
 528                                     struct comedi_insn *insn,
 529                                     unsigned int *data)
 530 {
 531         struct ni_65xx_private *devpriv = dev->private;
 532
 533         if (insn->n < 1)
 534                 return -EINVAL;
 535         if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
 536                 return -EINVAL;
 537
 538         writeb(data[1],
 539                devpriv->mite->daq_io_addr +
 540                Rising_Edge_Detection_Enable(0));
 541         writeb(data[1] >> 8,
 542                devpriv->mite->daq_io_addr +
 543                Rising_Edge_Detection_Enable(0x10));
 544         writeb(data[1] >> 16,
 545                devpriv->mite->daq_io_addr +
 546                Rising_Edge_Detection_Enable(0x20));
 547         writeb(data[1] >> 24,
 548                devpriv->mite->daq_io_addr +
 549                Rising_Edge_Detection_Enable(0x30));
 550
 551         writeb(data[2],
 552                devpriv->mite->daq_io_addr +
 553                Falling_Edge_Detection_Enable(0));
 554         writeb(data[2] >> 8,
 555                devpriv->mite->daq_io_addr +
 556                Falling_Edge_Detection_Enable(0x10));
 557         writeb(data[2] >> 16,
 558                devpriv->mite->daq_io_addr +
 559                Falling_Edge_Detection_Enable(0x20));
 560         writeb(data[2] >> 24,
 561                devpriv->mite->daq_io_addr +
 562                Falling_Edge_Detection_Enable(0x30));
 563
 564         return 2;
 565 }
 566
 567 static int ni_65xx_auto_attach(struct comedi_device *dev,
 568                                unsigned long context)
 569 {
 570         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 571         const struct ni_65xx_board *board = NULL;
 572         struct ni_65xx_private *devpriv;
 573         struct ni_65xx_subdevice_private *spriv;
 574         struct comedi_subdevice *s;
 575         unsigned i;
 576         int ret;
 577
 578         if (context < ARRAY_SIZE(ni_65xx_boards))
 579                 board = &ni_65xx_boards[context];
 580         if (!board)
 581                 return -ENODEV;
 582         dev->board_ptr = board;
 583         dev->board_name = board->name;
 584
 585         ret = comedi_pci_enable(dev);
 586         if (ret)
 587                 return ret;
 588
 589         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 590         if (!devpriv)
 591                 return -ENOMEM;
 592
 593         devpriv->mite = mite_alloc(pcidev);
 594         if (!devpriv->mite)
 595                 return -ENOMEM;
 596
 597         ret = mite_setup(devpriv->mite);
 598         if (ret < 0) {
 599                 dev_warn(dev->class_dev, "error setting up mite\n");
 600                 return ret;
 601         }
 602
 603         dev->irq = mite_irq(devpriv->mite);
 604         dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
 605                readb(devpriv->mite->daq_io_addr + ID_Register));
 606
 607         ret = comedi_alloc_subdevices(dev, 4);
 608         if (ret)
 609                 return ret;
 610
 611         s = &dev->subdevices[0];
 612         if (board->num_di_ports) {
 613                 s->type = COMEDI_SUBD_DI;
 614                 s->subdev_flags = SDF_READABLE;
 615                 s->n_chan =
 616                     board->num_di_ports * ni_65xx_channels_per_port;
 617                 s->range_table = &range_digital;
 618                 s->maxdata = 1;
 619                 s->insn_config = ni_65xx_dio_insn_config;
 620                 s->insn_bits = ni_65xx_dio_insn_bits;
 621                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
 622                 if (!spriv)
 623                         return -ENOMEM;
 624                 spriv->base_port = 0;
 625         } else {
 626                 s->type = COMEDI_SUBD_UNUSED;
 627         }
 628
 629         s = &dev->subdevices[1];
 630         if (board->num_do_ports) {
 631                 s->type = COMEDI_SUBD_DO;
 632                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 633                 s->n_chan =
 634                     board->num_do_ports * ni_65xx_channels_per_port;
 635                 s->range_table = &range_digital;
 636                 s->maxdata = 1;
 637                 s->insn_bits = ni_65xx_dio_insn_bits;
 638                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
 639                 if (!spriv)
 640                         return -ENOMEM;
 641                 spriv->base_port = board->num_di_ports;
 642         } else {
 643                 s->type = COMEDI_SUBD_UNUSED;
 644         }
 645
 646         s = &dev->subdevices[2];
 647         if (board->num_dio_ports) {
 648                 s->type = COMEDI_SUBD_DIO;
 649                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
 650                 s->n_chan =
 651                     board->num_dio_ports * ni_65xx_channels_per_port;
 652                 s->range_table = &range_digital;
 653                 s->maxdata = 1;
 654                 s->insn_config = ni_65xx_dio_insn_config;
 655                 s->insn_bits = ni_65xx_dio_insn_bits;
 656                 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
 657                 if (!spriv)
 658                         return -ENOMEM;
 659                 spriv->base_port = 0;
 660                 for (i = 0; i < board->num_dio_ports; ++i) {
 661                         /*  configure all ports for input */
 662                         writeb(0x1,
 663                                devpriv->mite->daq_io_addr +
 664                                Port_Select(i));
 665                 }
 666         } else {
 667                 s->type = COMEDI_SUBD_UNUSED;
 668         }
 669
 670         s = &dev->subdevices[3];
 671         dev->read_subdev = s;
 672         s->type = COMEDI_SUBD_DI;
 673         s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 674         s->n_chan = 1;
 675         s->range_table = &range_unknown;
 676         s->maxdata = 1;
 677         s->do_cmdtest = ni_65xx_intr_cmdtest;
 678         s->do_cmd = ni_65xx_intr_cmd;
 679         s->cancel = ni_65xx_intr_cancel;
 680         s->insn_bits = ni_65xx_intr_insn_bits;
 681         s->insn_config = ni_65xx_intr_insn_config;
 682
 683         for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
 684                 writeb(0x00,
 685                        devpriv->mite->daq_io_addr + Filter_Enable(i));
 686                 if (board->invert_outputs)
 687                         writeb(0x01,
 688                                devpriv->mite->daq_io_addr + Port_Data(i));
 689                 else
 690                         writeb(0x00,
 691                                devpriv->mite->daq_io_addr + Port_Data(i));
 692         }
 693         writeb(ClrEdge | ClrOverflow,
 694                devpriv->mite->daq_io_addr + Clear_Register);
 695         writeb(0x00,
 696                devpriv->mite->daq_io_addr + Master_Interrupt_Control);
 697
 698         /* Set filter interval to 0  (32bit reg) */
 699         writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
 700
 701         ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
 702                           "ni_65xx", dev);
 703         if (ret < 0) {
 704                 dev->irq = 0;
 705                 dev_warn(dev->class_dev, "irq not available\n");
 706         }
 707
 708         return 0;
 709 }
 710
 711 static void ni_65xx_detach(struct comedi_device *dev)
 712 {
 713         struct ni_65xx_private *devpriv = dev->private;
 714
 715         if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
 716                 writeb(0x00,
 717                        devpriv->mite->daq_io_addr +
 718                        Master_Interrupt_Control);
 719         }
 720         if (dev->irq)
 721                 free_irq(dev->irq, dev);
 722         if (devpriv) {
 723                 if (devpriv->mite) {
 724                         mite_unsetup(devpriv->mite);
 725                         mite_free(devpriv->mite);
 726                 }
 727         }
 728         comedi_pci_disable(dev);
 729 }
 730
 731 static struct comedi_driver ni_65xx_driver = {
 732         .driver_name = "ni_65xx",
 733         .module = THIS_MODULE,
 734         .auto_attach = ni_65xx_auto_attach,
 735         .detach = ni_65xx_detach,
 736 };
 737
 738 static int ni_65xx_pci_probe(struct pci_dev *dev,
 739                              const struct pci_device_id *id)
 740 {
 741         return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
 742 }
 743
 744 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
 745         { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
 746         { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
 747         { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
 748         { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
 749         { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
 750         { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
 751         { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
 752         { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
 753         { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
 754         { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
 755         { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
 756         { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
 757         { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
 758         { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
 759         { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
 760         { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
 761         { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
 762         { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
 763         { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
 764         { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
 765         { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
 766         { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
 767         { 0 }
 768 };
 769 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
 770
 771 static struct pci_driver ni_65xx_pci_driver = {
 772         .name           = "ni_65xx",
 773         .id_table       = ni_65xx_pci_table,
 774         .probe          = ni_65xx_pci_probe,
 775         .remove         = comedi_pci_auto_unconfig,
 776 };
 777 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
 778
 779 MODULE_AUTHOR("Comedi http://www.comedi.org");
 780 MODULE_DESCRIPTION("Comedi low-level driver");
 781 MODULE_LICENSE("GPL");