2 comedi/drivers/ni_tio.c
3 Support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
20 Description: National Instruments general purpose counters
22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
23 Herman.Bruyninckx@mech.kuleuven.ac.be,
24 Wim.Meeussen@mech.kuleuven.ac.be,
25 Klaas.Gadeyne@mech.kuleuven.ac.be,
26 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Updated: Thu Nov 16 09:50:32 EST 2006
30 This module is not used directly by end-users. Rather, it
31 is used by other drivers (for example ni_660x and ni_pcimio)
32 to provide support for NI's general purpose counters. It was
33 originally based on the counter code from ni_660x.c and
37 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
38 DAQ 6601/6602 User Manual (NI 322137B-01)
39 340934b.pdf DAQ-STC reference manual
44 Support use of both banks X and Y
47 #include <linux/module.h>
48 #include <linux/slab.h>
50 #include "ni_tio_internal.h"
52 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
53 unsigned generic_clock_source);
54 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
56 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
57 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
58 MODULE_LICENSE("GPL");
60 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
65 case ni_gpct_variant_e_series:
68 case ni_gpct_variant_m_series:
69 return Gi_M_Series_Alternate_Sync_Bit;
71 case ni_gpct_variant_660x:
72 return Gi_660x_Alternate_Sync_Bit;
81 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
86 case ni_gpct_variant_e_series:
89 case ni_gpct_variant_m_series:
90 return Gi_M_Series_Prescale_X2_Bit;
92 case ni_gpct_variant_660x:
93 return Gi_660x_Prescale_X2_Bit;
102 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
107 case ni_gpct_variant_e_series:
110 case ni_gpct_variant_m_series:
111 return Gi_M_Series_Prescale_X8_Bit;
113 case ni_gpct_variant_660x:
114 return Gi_660x_Prescale_X8_Bit;
123 static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
128 case ni_gpct_variant_e_series:
131 case ni_gpct_variant_m_series:
132 return Gi_M_Series_HW_Arm_Select_Mask;
134 case ni_gpct_variant_660x:
135 return Gi_660x_HW_Arm_Select_Mask;
144 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
145 enum ni_660x_clock_source {
146 NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
147 NI_660x_Source_Pin_i_Clock = 0x1,
148 NI_660x_Next_Gate_Clock = 0xa,
149 NI_660x_Timebase_2_Clock = 0x12, /* 100KHz */
150 NI_660x_Next_TC_Clock = 0x13,
151 NI_660x_Timebase_3_Clock = 0x1e, /* 80MHz */
152 NI_660x_Logic_Low_Clock = 0x1f,
154 static const unsigned ni_660x_max_rtsi_channel = 6;
155 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
157 BUG_ON(n > ni_660x_max_rtsi_channel);
161 static const unsigned ni_660x_max_source_pin = 7;
162 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
164 BUG_ON(n > ni_660x_max_source_pin);
168 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
169 enum ni_m_series_clock_source {
170 NI_M_Series_Timebase_1_Clock = 0x0, /* 20MHz */
171 NI_M_Series_Timebase_2_Clock = 0x12, /* 100KHz */
172 NI_M_Series_Next_TC_Clock = 0x13,
173 NI_M_Series_Next_Gate_Clock = 0x14, /* when Gi_Src_SubSelect = 0 */
174 NI_M_Series_PXI_Star_Trigger_Clock = 0x14, /* when Gi_Src_SubSelect = 1 */
175 NI_M_Series_PXI10_Clock = 0x1d,
176 NI_M_Series_Timebase_3_Clock = 0x1e, /* 80MHz, when Gi_Src_SubSelect = 0 */
177 NI_M_Series_Analog_Trigger_Out_Clock = 0x1e, /* when Gi_Src_SubSelect = 1 */
178 NI_M_Series_Logic_Low_Clock = 0x1f,
180 static const unsigned ni_m_series_max_pfi_channel = 15;
181 static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
183 BUG_ON(n > ni_m_series_max_pfi_channel);
190 static const unsigned ni_m_series_max_rtsi_channel = 7;
191 static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
193 BUG_ON(n > ni_m_series_max_rtsi_channel);
200 enum ni_660x_gate_select {
201 NI_660x_Source_Pin_i_Gate_Select = 0x0,
202 NI_660x_Gate_Pin_i_Gate_Select = 0x1,
203 NI_660x_Next_SRC_Gate_Select = 0xa,
204 NI_660x_Next_Out_Gate_Select = 0x14,
205 NI_660x_Logic_Low_Gate_Select = 0x1f,
207 static const unsigned ni_660x_max_gate_pin = 7;
208 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
210 BUG_ON(n > ni_660x_max_gate_pin);
214 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
216 BUG_ON(n > ni_660x_max_rtsi_channel);
220 enum ni_m_series_gate_select {
221 NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
222 NI_M_Series_AI_START2_Gate_Select = 0x12,
223 NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
224 NI_M_Series_Next_Out_Gate_Select = 0x14,
225 NI_M_Series_AI_START1_Gate_Select = 0x1c,
226 NI_M_Series_Next_SRC_Gate_Select = 0x1d,
227 NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
228 NI_M_Series_Logic_Low_Gate_Select = 0x1f,
230 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
232 BUG_ON(n > ni_m_series_max_rtsi_channel);
238 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
240 BUG_ON(n > ni_m_series_max_pfi_channel);
246 static inline unsigned Gi_Source_Select_Bits(unsigned source)
248 return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
251 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
253 return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
256 enum ni_660x_second_gate_select {
257 NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
258 NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
259 NI_660x_Next_SRC_Second_Gate_Select = 0xa,
260 NI_660x_Next_Out_Second_Gate_Select = 0x14,
261 NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
262 NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
264 static const unsigned ni_660x_max_up_down_pin = 7;
265 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
267 BUG_ON(n > ni_660x_max_up_down_pin);
271 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
273 BUG_ON(n > ni_660x_max_rtsi_channel);
277 static const unsigned int counter_status_mask =
278 COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
280 static int __init ni_tio_init_module(void)
285 module_init(ni_tio_init_module);
287 static void __exit ni_tio_cleanup_module(void)
291 module_exit(ni_tio_cleanup_module);
293 struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device *dev,
294 void (*write_register) (struct
303 unsigned (*read_register)
304 (struct ni_gpct *counter,
305 enum ni_gpct_register reg),
306 enum ni_gpct_variant variant,
307 unsigned num_counters)
311 struct ni_gpct_device *counter_dev =
312 kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
313 if (counter_dev == NULL)
315 counter_dev->dev = dev;
316 counter_dev->write_register = write_register;
317 counter_dev->read_register = read_register;
318 counter_dev->variant = variant;
319 spin_lock_init(&counter_dev->regs_lock);
320 BUG_ON(num_counters == 0);
321 counter_dev->counters =
322 kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
323 if (counter_dev->counters == NULL) {
327 for (i = 0; i < num_counters; ++i) {
328 counter_dev->counters[i].counter_dev = counter_dev;
329 spin_lock_init(&counter_dev->counters[i].lock);
331 counter_dev->num_counters = num_counters;
334 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
336 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
338 if (counter_dev->counters == NULL)
340 kfree(counter_dev->counters);
343 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
345 static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
348 switch (counter_dev->variant) {
349 case ni_gpct_variant_e_series:
352 case ni_gpct_variant_m_series:
353 case ni_gpct_variant_660x:
363 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
365 write_register(counter, Gi_Reset_Bit(counter->counter_index),
366 NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
369 void ni_tio_init_counter(struct ni_gpct *counter)
371 struct ni_gpct_device *counter_dev = counter->counter_dev;
373 ni_tio_reset_count_and_disarm(counter);
374 /* initialize counter registers */
375 counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
377 write_register(counter,
379 regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
380 NITIO_Gi_Autoincrement_Reg(counter->counter_index));
381 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
382 ~0, Gi_Synchronize_Gate_Bit);
383 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
385 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
386 write_register(counter,
388 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
389 NITIO_Gi_LoadA_Reg(counter->counter_index));
390 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
391 write_register(counter,
393 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
394 NITIO_Gi_LoadB_Reg(counter->counter_index));
395 ni_tio_set_bits(counter,
396 NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
398 if (ni_tio_counting_mode_registers_present(counter_dev)) {
399 ni_tio_set_bits(counter,
400 NITIO_Gi_Counting_Mode_Reg(counter->
404 if (ni_tio_second_gate_registers_present(counter_dev)) {
406 regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
408 write_register(counter,
410 regs[NITIO_Gi_Second_Gate_Reg
411 (counter->counter_index)],
412 NITIO_Gi_Second_Gate_Reg(counter->
415 ni_tio_set_bits(counter,
416 NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
418 ni_tio_set_bits(counter,
419 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
422 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
424 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
426 unsigned int status = 0;
427 const unsigned bits = read_register(counter,
428 NITIO_Gxx_Status_Reg(counter->
430 if (bits & Gi_Armed_Bit(counter->counter_index)) {
431 status |= COMEDI_COUNTER_ARMED;
432 if (bits & Gi_Counting_Bit(counter->counter_index))
433 status |= COMEDI_COUNTER_COUNTING;
438 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
440 struct ni_gpct_device *counter_dev = counter->counter_dev;
441 const unsigned counting_mode_reg =
442 NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
443 static const uint64_t min_normal_sync_period_ps = 25000;
444 const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
445 ni_tio_generic_clock_src_select
448 if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
451 switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
452 case Gi_Counting_Mode_QuadratureX1_Bits:
453 case Gi_Counting_Mode_QuadratureX2_Bits:
454 case Gi_Counting_Mode_QuadratureX4_Bits:
455 case Gi_Counting_Mode_Sync_Source_Bits:
461 /* It's not clear what we should do if clock_period is unknown, so we are not
462 using the alt sync bit in that case, but allow the caller to decide by using the
463 force_alt_sync parameter. */
464 if (force_alt_sync ||
465 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
466 ni_tio_set_bits(counter, counting_mode_reg,
467 Gi_Alternate_Sync_Bit(counter_dev->variant),
468 Gi_Alternate_Sync_Bit(counter_dev->variant));
470 ni_tio_set_bits(counter, counting_mode_reg,
471 Gi_Alternate_Sync_Bit(counter_dev->variant),
476 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
478 struct ni_gpct_device *counter_dev = counter->counter_dev;
479 unsigned mode_reg_mask;
480 unsigned mode_reg_values;
481 unsigned input_select_bits = 0;
482 /* these bits map directly on to the mode register */
483 static const unsigned mode_reg_direct_mask =
484 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
485 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
486 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
487 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
489 mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
490 mode_reg_values = mode & mode_reg_direct_mask;
491 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
492 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
494 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
495 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
497 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
498 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
499 mode_reg_mask |= Gi_Gating_Mode_Mask;
500 mode_reg_values |= Gi_Level_Gating_Bits;
505 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
506 mode_reg_mask, mode_reg_values);
508 if (ni_tio_counting_mode_registers_present(counter_dev)) {
509 unsigned counting_mode_bits = 0;
510 counting_mode_bits |=
511 (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
512 Gi_Counting_Mode_Mask;
513 counting_mode_bits |=
514 ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
515 Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
516 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
517 counting_mode_bits |= Gi_Index_Mode_Bit;
518 ni_tio_set_bits(counter,
519 NITIO_Gi_Counting_Mode_Reg(counter->
521 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
522 Gi_Index_Mode_Bit, counting_mode_bits);
523 ni_tio_set_sync_mode(counter, 0);
526 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
528 (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
531 if (mode & NI_GPCT_OR_GATE_BIT)
532 input_select_bits |= Gi_Or_Gate_Bit;
533 if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
534 input_select_bits |= Gi_Output_Polarity_Bit;
535 ni_tio_set_bits(counter,
536 NITIO_Gi_Input_Select_Reg(counter->counter_index),
537 Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
538 Gi_Output_Polarity_Bit, input_select_bits);
543 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
545 struct ni_gpct_device *counter_dev = counter->counter_dev;
547 unsigned command_transient_bits = 0;
550 switch (start_trigger) {
551 case NI_GPCT_ARM_IMMEDIATE:
552 command_transient_bits |= Gi_Arm_Bit;
554 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
555 command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
560 if (ni_tio_counting_mode_registers_present(counter_dev)) {
561 unsigned counting_mode_bits = 0;
563 switch (start_trigger) {
564 case NI_GPCT_ARM_IMMEDIATE:
565 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
568 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
569 /* pass-through the least significant bits so we can figure out what select later */
570 unsigned hw_arm_select_bits =
572 Gi_HW_Arm_Select_Shift) &
573 Gi_HW_Arm_Select_Mask
574 (counter_dev->variant);
576 counting_mode_bits |=
577 Gi_HW_Arm_Enable_Bit |
584 ni_tio_set_bits(counter,
585 NITIO_Gi_Counting_Mode_Reg
586 (counter->counter_index),
587 Gi_HW_Arm_Select_Mask
588 (counter_dev->variant) |
589 Gi_HW_Arm_Enable_Bit,
593 command_transient_bits |= Gi_Disarm_Bit;
595 ni_tio_set_bits_transient(counter,
596 NITIO_Gi_Command_Reg(counter->counter_index),
597 0, 0, command_transient_bits);
600 EXPORT_SYMBOL_GPL(ni_tio_arm);
602 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
604 unsigned ni_660x_clock;
606 const unsigned clock_select_bits =
607 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
609 switch (clock_select_bits) {
610 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
611 ni_660x_clock = NI_660x_Timebase_1_Clock;
613 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
614 ni_660x_clock = NI_660x_Timebase_2_Clock;
616 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
617 ni_660x_clock = NI_660x_Timebase_3_Clock;
619 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
620 ni_660x_clock = NI_660x_Logic_Low_Clock;
622 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
623 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
625 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
626 ni_660x_clock = NI_660x_Next_Gate_Clock;
628 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
629 ni_660x_clock = NI_660x_Next_TC_Clock;
632 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
633 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
634 ni_660x_clock = NI_660x_RTSI_Clock(i);
638 if (i <= ni_660x_max_rtsi_channel)
640 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
641 if (clock_select_bits ==
642 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
643 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
647 if (i <= ni_660x_max_source_pin)
653 return Gi_Source_Select_Bits(ni_660x_clock);
656 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
658 unsigned ni_m_series_clock;
660 const unsigned clock_select_bits =
661 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
662 switch (clock_select_bits) {
663 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
664 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
666 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
667 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
669 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
670 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
672 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
673 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
675 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
676 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
678 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
679 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
681 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
682 ni_m_series_clock = NI_M_Series_PXI10_Clock;
684 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
685 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
687 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
688 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
691 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
692 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
693 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
697 if (i <= ni_m_series_max_rtsi_channel)
699 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
700 if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
701 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
705 if (i <= ni_m_series_max_pfi_channel)
707 printk(KERN_ERR "invalid clock source 0x%lx\n",
708 (unsigned long)clock_source);
710 ni_m_series_clock = 0;
713 return Gi_Source_Select_Bits(ni_m_series_clock);
716 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
717 unsigned int clock_source)
719 struct ni_gpct_device *counter_dev = counter->counter_dev;
720 const unsigned second_gate_reg =
721 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
723 if (counter_dev->variant != ni_gpct_variant_m_series)
725 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
726 /* Gi_Source_Subselect is zero */
727 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
728 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
729 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
731 /* Gi_Source_Subselect is one */
732 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
733 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
734 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
736 /* Gi_Source_Subselect doesn't matter */
741 write_register(counter, counter_dev->regs[second_gate_reg],
745 static int ni_tio_set_clock_src(struct ni_gpct *counter,
746 unsigned int clock_source,
747 unsigned int period_ns)
749 struct ni_gpct_device *counter_dev = counter->counter_dev;
750 unsigned input_select_bits = 0;
751 static const uint64_t pico_per_nano = 1000;
753 /*FIXME: validate clock source */
754 switch (counter_dev->variant) {
755 case ni_gpct_variant_660x:
756 input_select_bits |= ni_660x_source_select_bits(clock_source);
758 case ni_gpct_variant_e_series:
759 case ni_gpct_variant_m_series:
761 ni_m_series_source_select_bits(clock_source);
767 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
768 input_select_bits |= Gi_Source_Polarity_Bit;
769 ni_tio_set_bits(counter,
770 NITIO_Gi_Input_Select_Reg(counter->counter_index),
771 Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
773 ni_tio_set_source_subselect(counter, clock_source);
774 if (ni_tio_counting_mode_registers_present(counter_dev)) {
775 const unsigned prescaling_mode =
776 clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
777 unsigned counting_mode_bits = 0;
779 switch (prescaling_mode) {
780 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
782 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
783 counting_mode_bits |=
784 Gi_Prescale_X2_Bit(counter_dev->variant);
786 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
787 counting_mode_bits |=
788 Gi_Prescale_X8_Bit(counter_dev->variant);
794 ni_tio_set_bits(counter,
795 NITIO_Gi_Counting_Mode_Reg(counter->
797 Gi_Prescale_X2_Bit(counter_dev->variant) |
798 Gi_Prescale_X8_Bit(counter_dev->variant),
801 counter->clock_period_ps = pico_per_nano * period_ns;
802 ni_tio_set_sync_mode(counter, 0);
806 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
808 struct ni_gpct_device *counter_dev = counter->counter_dev;
809 const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter,
810 NITIO_Gi_Counting_Mode_Reg
815 if (ni_tio_get_soft_copy(counter,
816 NITIO_Gi_Input_Select_Reg
817 (counter->counter_index)) &
818 Gi_Source_Polarity_Bit)
819 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
820 if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
821 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
822 if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
823 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
827 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
829 struct ni_gpct_device *counter_dev = counter->counter_dev;
830 const unsigned second_gate_reg =
831 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
832 unsigned clock_source = 0;
834 const unsigned input_select = (ni_tio_get_soft_copy(counter,
835 NITIO_Gi_Input_Select_Reg
836 (counter->counter_index))
837 & Gi_Source_Select_Mask) >>
838 Gi_Source_Select_Shift;
840 switch (input_select) {
841 case NI_M_Series_Timebase_1_Clock:
842 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
844 case NI_M_Series_Timebase_2_Clock:
845 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
847 case NI_M_Series_Timebase_3_Clock:
848 if (counter_dev->regs[second_gate_reg] &
849 Gi_Source_Subselect_Bit)
851 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
853 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
855 case NI_M_Series_Logic_Low_Clock:
856 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
858 case NI_M_Series_Next_Gate_Clock:
859 if (counter_dev->regs[second_gate_reg] &
860 Gi_Source_Subselect_Bit)
861 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
863 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
865 case NI_M_Series_PXI10_Clock:
866 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
868 case NI_M_Series_Next_TC_Clock:
869 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
872 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
873 if (input_select == NI_M_Series_RTSI_Clock(i)) {
874 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
878 if (i <= ni_m_series_max_rtsi_channel)
880 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
881 if (input_select == NI_M_Series_PFI_Clock(i)) {
882 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
886 if (i <= ni_m_series_max_pfi_channel)
891 clock_source |= ni_tio_clock_src_modifiers(counter);
895 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
897 unsigned clock_source = 0;
899 const unsigned input_select = (ni_tio_get_soft_copy(counter,
900 NITIO_Gi_Input_Select_Reg
901 (counter->counter_index))
902 & Gi_Source_Select_Mask) >>
903 Gi_Source_Select_Shift;
905 switch (input_select) {
906 case NI_660x_Timebase_1_Clock:
907 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
909 case NI_660x_Timebase_2_Clock:
910 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
912 case NI_660x_Timebase_3_Clock:
913 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
915 case NI_660x_Logic_Low_Clock:
916 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
918 case NI_660x_Source_Pin_i_Clock:
919 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
921 case NI_660x_Next_Gate_Clock:
922 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
924 case NI_660x_Next_TC_Clock:
925 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
928 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
929 if (input_select == NI_660x_RTSI_Clock(i)) {
930 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
934 if (i <= ni_660x_max_rtsi_channel)
936 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
937 if (input_select == NI_660x_Source_Pin_Clock(i)) {
939 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
943 if (i <= ni_660x_max_source_pin)
948 clock_source |= ni_tio_clock_src_modifiers(counter);
952 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
954 switch (counter->counter_dev->variant) {
955 case ni_gpct_variant_e_series:
956 case ni_gpct_variant_m_series:
957 return ni_m_series_clock_src_select(counter);
959 case ni_gpct_variant_660x:
960 return ni_660x_clock_src_select(counter);
969 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
970 unsigned generic_clock_source)
972 uint64_t clock_period_ps;
974 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
975 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
976 clock_period_ps = 50000;
978 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
979 clock_period_ps = 10000000;
981 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
982 clock_period_ps = 12500;
984 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
985 clock_period_ps = 100000;
988 /* clock period is specified by user with prescaling already taken into account. */
989 return counter->clock_period_ps;
993 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
994 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
996 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
997 clock_period_ps *= 2;
999 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1000 clock_period_ps *= 8;
1006 return clock_period_ps;
1009 static void ni_tio_get_clock_src(struct ni_gpct *counter,
1010 unsigned int *clock_source,
1011 unsigned int *period_ns)
1013 static const unsigned pico_per_nano = 1000;
1015 *clock_source = ni_tio_generic_clock_src_select(counter);
1016 temp64 = ni_tio_clock_period_ps(counter, *clock_source);
1017 do_div(temp64, pico_per_nano);
1018 *period_ns = temp64;
1021 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
1022 unsigned int gate_source)
1024 const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
1025 unsigned mode_values = 0;
1027 if (gate_source & CR_INVERT)
1028 mode_values |= Gi_Gate_Polarity_Bit;
1029 if (gate_source & CR_EDGE)
1030 mode_values |= Gi_Rising_Edge_Gating_Bits;
1032 mode_values |= Gi_Level_Gating_Bits;
1033 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
1034 mode_mask, mode_values);
1037 static int ni_660x_set_first_gate(struct ni_gpct *counter,
1038 unsigned int gate_source)
1040 const unsigned selected_gate = CR_CHAN(gate_source);
1041 /* bits of selected_gate that may be meaningful to input select register */
1042 const unsigned selected_gate_mask = 0x1f;
1043 unsigned ni_660x_gate_select;
1046 switch (selected_gate) {
1047 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1048 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1050 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1051 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1052 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1053 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1054 ni_660x_gate_select = selected_gate & selected_gate_mask;
1057 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1058 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1059 ni_660x_gate_select =
1060 selected_gate & selected_gate_mask;
1064 if (i <= ni_660x_max_rtsi_channel)
1066 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1067 if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
1068 ni_660x_gate_select =
1069 selected_gate & selected_gate_mask;
1073 if (i <= ni_660x_max_gate_pin)
1078 ni_tio_set_bits(counter,
1079 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1080 Gi_Gate_Select_Mask,
1081 Gi_Gate_Select_Bits(ni_660x_gate_select));
1085 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
1086 unsigned int gate_source)
1088 const unsigned selected_gate = CR_CHAN(gate_source);
1089 /* bits of selected_gate that may be meaningful to input select register */
1090 const unsigned selected_gate_mask = 0x1f;
1091 unsigned ni_m_series_gate_select;
1094 switch (selected_gate) {
1095 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1096 case NI_GPCT_AI_START2_GATE_SELECT:
1097 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1098 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1099 case NI_GPCT_AI_START1_GATE_SELECT:
1100 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1101 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1102 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1103 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1106 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1107 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1108 ni_m_series_gate_select =
1109 selected_gate & selected_gate_mask;
1113 if (i <= ni_m_series_max_rtsi_channel)
1115 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1116 if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
1117 ni_m_series_gate_select =
1118 selected_gate & selected_gate_mask;
1122 if (i <= ni_m_series_max_pfi_channel)
1127 ni_tio_set_bits(counter,
1128 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1129 Gi_Gate_Select_Mask,
1130 Gi_Gate_Select_Bits(ni_m_series_gate_select));
1134 static int ni_660x_set_second_gate(struct ni_gpct *counter,
1135 unsigned int gate_source)
1137 struct ni_gpct_device *counter_dev = counter->counter_dev;
1138 const unsigned second_gate_reg =
1139 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1140 const unsigned selected_second_gate = CR_CHAN(gate_source);
1141 /* bits of second_gate that may be meaningful to second gate register */
1142 static const unsigned selected_second_gate_mask = 0x1f;
1143 unsigned ni_660x_second_gate_select;
1146 switch (selected_second_gate) {
1147 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1148 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1149 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1150 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1151 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1152 ni_660x_second_gate_select =
1153 selected_second_gate & selected_second_gate_mask;
1155 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1156 ni_660x_second_gate_select =
1157 NI_660x_Next_SRC_Second_Gate_Select;
1160 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1161 if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1162 ni_660x_second_gate_select =
1163 selected_second_gate &
1164 selected_second_gate_mask;
1168 if (i <= ni_660x_max_rtsi_channel)
1170 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1171 if (selected_second_gate ==
1172 NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1173 ni_660x_second_gate_select =
1174 selected_second_gate &
1175 selected_second_gate_mask;
1179 if (i <= ni_660x_max_up_down_pin)
1184 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1185 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1186 counter_dev->regs[second_gate_reg] |=
1187 Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
1188 write_register(counter, counter_dev->regs[second_gate_reg],
1193 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
1194 unsigned int gate_source)
1196 struct ni_gpct_device *counter_dev = counter->counter_dev;
1197 const unsigned second_gate_reg =
1198 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1199 const unsigned selected_second_gate = CR_CHAN(gate_source);
1200 /* bits of second_gate that may be meaningful to second gate register */
1201 static const unsigned selected_second_gate_mask = 0x1f;
1202 unsigned ni_m_series_second_gate_select;
1204 /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1205 the bits through for now. */
1206 switch (selected_second_gate) {
1208 ni_m_series_second_gate_select =
1209 selected_second_gate & selected_second_gate_mask;
1212 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1213 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1214 counter_dev->regs[second_gate_reg] |=
1215 Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1216 write_register(counter, counter_dev->regs[second_gate_reg],
1221 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
1222 unsigned int gate_source)
1224 struct ni_gpct_device *counter_dev = counter->counter_dev;
1225 const unsigned second_gate_reg =
1226 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1228 switch (gate_index) {
1230 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1231 ni_tio_set_bits(counter,
1232 NITIO_Gi_Mode_Reg(counter->
1234 Gi_Gating_Mode_Mask,
1235 Gi_Gating_Disabled_Bits);
1238 ni_tio_set_first_gate_modifiers(counter, gate_source);
1239 switch (counter_dev->variant) {
1240 case ni_gpct_variant_e_series:
1241 case ni_gpct_variant_m_series:
1242 return ni_m_series_set_first_gate(counter, gate_source);
1244 case ni_gpct_variant_660x:
1245 return ni_660x_set_first_gate(counter, gate_source);
1253 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1255 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1256 counter_dev->regs[second_gate_reg] &=
1257 ~Gi_Second_Gate_Mode_Bit;
1258 write_register(counter,
1259 counter_dev->regs[second_gate_reg],
1263 if (gate_source & CR_INVERT) {
1264 counter_dev->regs[second_gate_reg] |=
1265 Gi_Second_Gate_Polarity_Bit;
1267 counter_dev->regs[second_gate_reg] &=
1268 ~Gi_Second_Gate_Polarity_Bit;
1270 switch (counter_dev->variant) {
1271 case ni_gpct_variant_m_series:
1272 return ni_m_series_set_second_gate(counter,
1275 case ni_gpct_variant_660x:
1276 return ni_660x_set_second_gate(counter, gate_source);
1289 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1291 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1292 unsigned int source)
1294 struct ni_gpct_device *counter_dev = counter->counter_dev;
1296 if (counter_dev->variant == ni_gpct_variant_m_series) {
1297 unsigned int abz_reg, shift, mask;
1299 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1301 case NI_GPCT_SOURCE_ENCODER_A:
1304 case NI_GPCT_SOURCE_ENCODER_B:
1307 case NI_GPCT_SOURCE_ENCODER_Z:
1314 mask = 0x1f << shift;
1315 if (source > 0x1f) {
1319 counter_dev->regs[abz_reg] &= ~mask;
1320 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1321 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1322 /* printk("%s %x %d %d\n", __func__, counter_dev->regs[abz_reg], index, source); */
1328 static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
1329 ni_660x_gate_select)
1333 switch (ni_660x_gate_select) {
1334 case NI_660x_Source_Pin_i_Gate_Select:
1335 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1337 case NI_660x_Gate_Pin_i_Gate_Select:
1338 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1340 case NI_660x_Next_SRC_Gate_Select:
1341 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1343 case NI_660x_Next_Out_Gate_Select:
1344 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1346 case NI_660x_Logic_Low_Gate_Select:
1347 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1350 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1351 if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
1352 return NI_GPCT_RTSI_GATE_SELECT(i);
1356 if (i <= ni_660x_max_rtsi_channel)
1358 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1359 if (ni_660x_gate_select ==
1360 NI_660x_Gate_Pin_Gate_Select(i)) {
1361 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1365 if (i <= ni_660x_max_gate_pin)
1373 static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
1374 ni_m_series_gate_select)
1378 switch (ni_m_series_gate_select) {
1379 case NI_M_Series_Timestamp_Mux_Gate_Select:
1380 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1382 case NI_M_Series_AI_START2_Gate_Select:
1383 return NI_GPCT_AI_START2_GATE_SELECT;
1385 case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1386 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1388 case NI_M_Series_Next_Out_Gate_Select:
1389 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1391 case NI_M_Series_AI_START1_Gate_Select:
1392 return NI_GPCT_AI_START1_GATE_SELECT;
1394 case NI_M_Series_Next_SRC_Gate_Select:
1395 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1397 case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1398 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1400 case NI_M_Series_Logic_Low_Gate_Select:
1401 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1404 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1405 if (ni_m_series_gate_select ==
1406 NI_M_Series_RTSI_Gate_Select(i)) {
1407 return NI_GPCT_RTSI_GATE_SELECT(i);
1411 if (i <= ni_m_series_max_rtsi_channel)
1413 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1414 if (ni_m_series_gate_select ==
1415 NI_M_Series_PFI_Gate_Select(i)) {
1416 return NI_GPCT_PFI_GATE_SELECT(i);
1420 if (i <= ni_m_series_max_pfi_channel)
1428 static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
1429 ni_660x_gate_select)
1433 switch (ni_660x_gate_select) {
1434 case NI_660x_Source_Pin_i_Second_Gate_Select:
1435 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1437 case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1438 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1440 case NI_660x_Next_SRC_Second_Gate_Select:
1441 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1443 case NI_660x_Next_Out_Second_Gate_Select:
1444 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1446 case NI_660x_Selected_Gate_Second_Gate_Select:
1447 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1449 case NI_660x_Logic_Low_Second_Gate_Select:
1450 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1453 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1454 if (ni_660x_gate_select ==
1455 NI_660x_RTSI_Second_Gate_Select(i)) {
1456 return NI_GPCT_RTSI_GATE_SELECT(i);
1460 if (i <= ni_660x_max_rtsi_channel)
1462 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1463 if (ni_660x_gate_select ==
1464 NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
1465 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1469 if (i <= ni_660x_max_up_down_pin)
1477 static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
1478 ni_m_series_gate_select)
1480 /*FIXME: the second gate sources for the m series are undocumented, so we just return
1481 * the raw bits for now. */
1482 switch (ni_m_series_gate_select) {
1484 return ni_m_series_gate_select;
1490 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1491 unsigned int *gate_source)
1493 struct ni_gpct_device *counter_dev = counter->counter_dev;
1494 const unsigned mode_bits = ni_tio_get_soft_copy(counter,
1498 const unsigned second_gate_reg =
1499 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1500 unsigned gate_select_bits;
1502 switch (gate_index) {
1504 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1505 Gi_Gating_Disabled_Bits) {
1506 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1510 (ni_tio_get_soft_copy(counter,
1511 NITIO_Gi_Input_Select_Reg
1512 (counter->counter_index)) &
1513 Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1515 switch (counter_dev->variant) {
1516 case ni_gpct_variant_e_series:
1517 case ni_gpct_variant_m_series:
1519 ni_m_series_first_gate_to_generic_gate_source
1522 case ni_gpct_variant_660x:
1524 ni_660x_first_gate_to_generic_gate_source
1531 if (mode_bits & Gi_Gate_Polarity_Bit)
1532 *gate_source |= CR_INVERT;
1533 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1534 *gate_source |= CR_EDGE;
1537 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1538 || (counter_dev->regs[second_gate_reg] &
1539 Gi_Second_Gate_Mode_Bit)
1541 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1545 (counter_dev->regs[second_gate_reg] &
1546 Gi_Second_Gate_Select_Mask) >>
1547 Gi_Second_Gate_Select_Shift;
1549 switch (counter_dev->variant) {
1550 case ni_gpct_variant_e_series:
1551 case ni_gpct_variant_m_series:
1553 ni_m_series_second_gate_to_generic_gate_source
1556 case ni_gpct_variant_660x:
1558 ni_660x_second_gate_to_generic_gate_source
1565 if (counter_dev->regs[second_gate_reg] &
1566 Gi_Second_Gate_Polarity_Bit) {
1567 *gate_source |= CR_INVERT;
1569 /* second gate can't have edge/level mode set independently */
1570 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1571 *gate_source |= CR_EDGE;
1580 int ni_tio_insn_config(struct ni_gpct *counter,
1581 struct comedi_insn *insn, unsigned int *data)
1584 case INSN_CONFIG_SET_COUNTER_MODE:
1585 return ni_tio_set_counter_mode(counter, data[1]);
1587 case INSN_CONFIG_ARM:
1588 return ni_tio_arm(counter, 1, data[1]);
1590 case INSN_CONFIG_DISARM:
1591 ni_tio_arm(counter, 0, 0);
1594 case INSN_CONFIG_GET_COUNTER_STATUS:
1595 data[1] = ni_tio_counter_status(counter);
1596 data[2] = counter_status_mask;
1599 case INSN_CONFIG_SET_CLOCK_SRC:
1600 return ni_tio_set_clock_src(counter, data[1], data[2]);
1602 case INSN_CONFIG_GET_CLOCK_SRC:
1603 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1606 case INSN_CONFIG_SET_GATE_SRC:
1607 return ni_tio_set_gate_src(counter, data[1], data[2]);
1609 case INSN_CONFIG_GET_GATE_SRC:
1610 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1612 case INSN_CONFIG_SET_OTHER_SRC:
1613 return ni_tio_set_other_src(counter, data[1], data[2]);
1615 case INSN_CONFIG_RESET:
1616 ni_tio_reset_count_and_disarm(counter);
1624 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1626 int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
1629 struct ni_gpct_device *counter_dev = counter->counter_dev;
1630 const unsigned channel = CR_CHAN(insn->chanspec);
1631 unsigned first_read;
1632 unsigned second_read;
1633 unsigned correct_read;
1639 ni_tio_set_bits(counter,
1640 NITIO_Gi_Command_Reg(counter->counter_index),
1641 Gi_Save_Trace_Bit, 0);
1642 ni_tio_set_bits(counter,
1643 NITIO_Gi_Command_Reg(counter->counter_index),
1644 Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1645 /* The count doesn't get latched until the next clock edge, so it is possible the count
1646 may change (once) while we are reading. Since the read of the SW_Save_Reg isn't
1647 atomic (apparently even when it's a 32 bit register according to 660x docs),
1648 we need to read twice and make sure the reading hasn't changed. If it has,
1649 a third read will be correct since the count value will definitely have latched by then. */
1651 read_register(counter,
1652 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1654 read_register(counter,
1655 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1656 if (first_read != second_read)
1658 read_register(counter,
1659 NITIO_Gi_SW_Save_Reg(counter->
1662 correct_read = first_read;
1663 data[0] = correct_read;
1669 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
1674 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
1679 EXPORT_SYMBOL_GPL(ni_tio_rinsn);
1681 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1683 const unsigned bits = read_register(counter,
1684 NITIO_Gxx_Status_Reg(counter->
1687 if (bits & Gi_Next_Load_Source_Bit(counter->counter_index))
1688 return NITIO_Gi_LoadB_Reg(counter->counter_index);
1690 return NITIO_Gi_LoadA_Reg(counter->counter_index);
1693 int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
1696 struct ni_gpct_device *counter_dev = counter->counter_dev;
1697 const unsigned channel = CR_CHAN(insn->chanspec);
1704 /* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */
1705 /* Don't disturb load source select, just use whichever load register is already selected. */
1706 load_reg = ni_tio_next_load_register(counter);
1707 write_register(counter, data[0], load_reg);
1708 ni_tio_set_bits_transient(counter,
1709 NITIO_Gi_Command_Reg(counter->
1712 /* restore state of load reg to whatever the user set last set it to */
1713 write_register(counter, counter_dev->regs[load_reg], load_reg);
1716 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
1718 write_register(counter, data[0],
1719 NITIO_Gi_LoadA_Reg(counter->counter_index));
1722 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
1724 write_register(counter, data[0],
1725 NITIO_Gi_LoadB_Reg(counter->counter_index));
1733 EXPORT_SYMBOL_GPL(ni_tio_winsn);