drivers/staging/media/sunxi/cedrus/cedrus_hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cedrus VPU driver
   4  *
   5  * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
   6  * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
   7  * Copyright (C) 2018 Bootlin
   8  *
   9  * Based on the vim2m driver, that is:
  10  *
  11  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  12  * Pawel Osciak, <pawel@osciak.com>
  13  * Marek Szyprowski, <m.szyprowski@samsung.com>
  14  */
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/of_reserved_mem.h>
  18 #include <linux/of_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/clk.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset.h>
  24 #include <linux/soc/sunxi/sunxi_sram.h>
  25
  26 #include <media/videobuf2-core.h>
  27 #include <media/v4l2-mem2mem.h>
  28
  29 #include "cedrus.h"
  30 #include "cedrus_hw.h"
  31 #include "cedrus_regs.h"
  32
  33 int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec)
  34 {
  35         u32 reg = 0;
  36
  37         /*
  38          * FIXME: This is only valid on 32-bits DDR's, we should test
  39          * it on the A13/A33.
  40          */
  41         reg |= VE_MODE_REC_WR_MODE_2MB;
  42         reg |= VE_MODE_DDR_MODE_BW_128;
  43
  44         switch (codec) {
  45         case CEDRUS_CODEC_MPEG2:
  46                 reg |= VE_MODE_DEC_MPEG;
  47                 break;
  48
  49         default:
  50                 return -EINVAL;
  51         }
  52
  53         cedrus_write(dev, VE_MODE, reg);
  54
  55         return 0;
  56 }
  57
  58 void cedrus_engine_disable(struct cedrus_dev *dev)
  59 {
  60         cedrus_write(dev, VE_MODE, VE_MODE_DISABLED);
  61 }
  62
  63 void cedrus_dst_format_set(struct cedrus_dev *dev,
  64                            struct v4l2_pix_format *fmt)
  65 {
  66         unsigned int width = fmt->width;
  67         unsigned int height = fmt->height;
  68         u32 chroma_size;
  69         u32 reg;
  70
  71         switch (fmt->pixelformat) {
  72         case V4L2_PIX_FMT_NV12:
  73                 chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2;
  74
  75                 reg = VE_PRIMARY_OUT_FMT_NV12;
  76                 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
  77
  78                 reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2);
  79                 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
  80
  81                 reg = chroma_size / 2;
  82                 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg);
  83
  84                 reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) |
  85                       VE_PRIMARY_FB_LINE_STRIDE_CHROMA(ALIGN(width, 16) / 2);
  86                 cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg);
  87
  88                 break;
  89         case V4L2_PIX_FMT_SUNXI_TILED_NV12:
  90         default:
  91                 reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12;
  92                 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
  93
  94                 reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12;
  95                 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg);
  96
  97                 break;
  98         }
  99 }
 100
 101 static irqreturn_t cedrus_bh(int irq, void *data)
 102 {
 103         struct cedrus_dev *dev = data;
 104         struct cedrus_ctx *ctx;
 105
 106         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
 107         if (!ctx) {
 108                 v4l2_err(&dev->v4l2_dev,
 109                          "Instance released before the end of transaction\n");
 110                 return IRQ_HANDLED;
 111         }
 112
 113         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
 114
 115         return IRQ_HANDLED;
 116 }
 117
 118 static irqreturn_t cedrus_irq(int irq, void *data)
 119 {
 120         struct cedrus_dev *dev = data;
 121         struct cedrus_ctx *ctx;
 122         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 123         enum vb2_buffer_state state;
 124         enum cedrus_irq_status status;
 125         unsigned long flags;
 126
 127         spin_lock_irqsave(&dev->irq_lock, flags);
 128
 129         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
 130         if (!ctx) {
 131                 v4l2_err(&dev->v4l2_dev,
 132                          "Instance released before the end of transaction\n");
 133                 spin_unlock_irqrestore(&dev->irq_lock, flags);
 134
 135                 return IRQ_NONE;
 136         }
 137
 138         status = dev->dec_ops[ctx->current_codec]->irq_status(ctx);
 139         if (status == CEDRUS_IRQ_NONE) {
 140                 spin_unlock_irqrestore(&dev->irq_lock, flags);
 141                 return IRQ_NONE;
 142         }
 143
 144         dev->dec_ops[ctx->current_codec]->irq_disable(ctx);
 145         dev->dec_ops[ctx->current_codec]->irq_clear(ctx);
 146
 147         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 148         dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
 149
 150         if (!src_buf || !dst_buf) {
 151                 v4l2_err(&dev->v4l2_dev,
 152                          "Missing source and/or destination buffers\n");
 153                 spin_unlock_irqrestore(&dev->irq_lock, flags);
 154
 155                 return IRQ_HANDLED;
 156         }
 157
 158         if (status == CEDRUS_IRQ_ERROR)
 159                 state = VB2_BUF_STATE_ERROR;
 160         else
 161                 state = VB2_BUF_STATE_DONE;
 162
 163         v4l2_m2m_buf_done(src_buf, state);
 164         v4l2_m2m_buf_done(dst_buf, state);
 165
 166         spin_unlock_irqrestore(&dev->irq_lock, flags);
 167
 168         return IRQ_WAKE_THREAD;
 169 }
 170
 171 int cedrus_hw_probe(struct cedrus_dev *dev)
 172 {
 173         const struct cedrus_variant *variant;
 174         struct resource *res;
 175         int irq_dec;
 176         int ret;
 177
 178         variant = of_device_get_match_data(dev->dev);
 179         if (!variant)
 180                 return -EINVAL;
 181
 182         dev->capabilities = variant->capabilities;
 183
 184         irq_dec = platform_get_irq(dev->pdev, 0);
 185         if (irq_dec <= 0) {
 186                 v4l2_err(&dev->v4l2_dev, "Failed to get IRQ\n");
 187
 188                 return irq_dec;
 189         }
 190         ret = devm_request_threaded_irq(dev->dev, irq_dec, cedrus_irq,
 191                                         cedrus_bh, 0, dev_name(dev->dev),
 192                                         dev);
 193         if (ret) {
 194                 v4l2_err(&dev->v4l2_dev, "Failed to request IRQ\n");
 195
 196                 return ret;
 197         }
 198
 199         /*
 200          * The VPU is only able to handle bus addresses so we have to subtract
 201          * the RAM offset to the physcal addresses.
 202          *
 203          * This information will eventually be obtained from device-tree.
 204          */
 205
 206 #ifdef PHYS_PFN_OFFSET
 207         dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET;
 208 #endif
 209
 210         ret = of_reserved_mem_device_init(dev->dev);
 211         if (ret && ret != -ENODEV) {
 212                 v4l2_err(&dev->v4l2_dev, "Failed to reserve memory\n");
 213
 214                 return ret;
 215         }
 216
 217         ret = sunxi_sram_claim(dev->dev);
 218         if (ret) {
 219                 v4l2_err(&dev->v4l2_dev, "Failed to claim SRAM\n");
 220
 221                 goto err_mem;
 222         }
 223
 224         dev->ahb_clk = devm_clk_get(dev->dev, "ahb");
 225         if (IS_ERR(dev->ahb_clk)) {
 226                 v4l2_err(&dev->v4l2_dev, "Failed to get AHB clock\n");
 227
 228                 ret = PTR_ERR(dev->ahb_clk);
 229                 goto err_sram;
 230         }
 231
 232         dev->mod_clk = devm_clk_get(dev->dev, "mod");
 233         if (IS_ERR(dev->mod_clk)) {
 234                 v4l2_err(&dev->v4l2_dev, "Failed to get MOD clock\n");
 235
 236                 ret = PTR_ERR(dev->mod_clk);
 237                 goto err_sram;
 238         }
 239
 240         dev->ram_clk = devm_clk_get(dev->dev, "ram");
 241         if (IS_ERR(dev->ram_clk)) {
 242                 v4l2_err(&dev->v4l2_dev, "Failed to get RAM clock\n");
 243
 244                 ret = PTR_ERR(dev->ram_clk);
 245                 goto err_sram;
 246         }
 247
 248         dev->rstc = devm_reset_control_get(dev->dev, NULL);
 249         if (IS_ERR(dev->rstc)) {
 250                 v4l2_err(&dev->v4l2_dev, "Failed to get reset control\n");
 251
 252                 ret = PTR_ERR(dev->rstc);
 253                 goto err_sram;
 254         }
 255
 256         res = platform_get_resource(dev->pdev, IORESOURCE_MEM, 0);
 257         dev->base = devm_ioremap_resource(dev->dev, res);
 258         if (IS_ERR(dev->base)) {
 259                 v4l2_err(&dev->v4l2_dev, "Failed to map registers\n");
 260
 261                 ret = PTR_ERR(dev->base);
 262                 goto err_sram;
 263         }
 264
 265         ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT);
 266         if (ret) {
 267                 v4l2_err(&dev->v4l2_dev, "Failed to set clock rate\n");
 268
 269                 goto err_sram;
 270         }
 271
 272         ret = clk_prepare_enable(dev->ahb_clk);
 273         if (ret) {
 274                 v4l2_err(&dev->v4l2_dev, "Failed to enable AHB clock\n");
 275
 276                 goto err_sram;
 277         }
 278
 279         ret = clk_prepare_enable(dev->mod_clk);
 280         if (ret) {
 281                 v4l2_err(&dev->v4l2_dev, "Failed to enable MOD clock\n");
 282
 283                 goto err_ahb_clk;
 284         }
 285
 286         ret = clk_prepare_enable(dev->ram_clk);
 287         if (ret) {
 288                 v4l2_err(&dev->v4l2_dev, "Failed to enable RAM clock\n");
 289
 290                 goto err_mod_clk;
 291         }
 292
 293         ret = reset_control_reset(dev->rstc);
 294         if (ret) {
 295                 v4l2_err(&dev->v4l2_dev, "Failed to apply reset\n");
 296
 297                 goto err_ram_clk;
 298         }
 299
 300         return 0;
 301
 302 err_ram_clk:
 303         clk_disable_unprepare(dev->ram_clk);
 304 err_mod_clk:
 305         clk_disable_unprepare(dev->mod_clk);
 306 err_ahb_clk:
 307         clk_disable_unprepare(dev->ahb_clk);
 308 err_sram:
 309         sunxi_sram_release(dev->dev);
 310 err_mem:
 311         of_reserved_mem_device_release(dev->dev);
 312
 313         return ret;
 314 }
 315
 316 void cedrus_hw_remove(struct cedrus_dev *dev)
 317 {
 318         reset_control_assert(dev->rstc);
 319
 320         clk_disable_unprepare(dev->ram_clk);
 321         clk_disable_unprepare(dev->mod_clk);
 322         clk_disable_unprepare(dev->ahb_clk);
 323
 324         sunxi_sram_release(dev->dev);
 325
 326         of_reserved_mem_device_release(dev->dev);
 327 }