1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Anson Huang <Anson.Huang@nxp.com>
8 #include <linux/bitfield.h>
10 #include <linux/err.h>
12 #include <linux/module.h>
13 #include <linux/nvmem-consumer.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/thermal.h>
20 #include "thermal_hwmon.h"
22 #define TER 0x0 /* TMU enable */
24 #define TRITSR 0x20 /* TMU immediate temp */
25 /* TMU calibration data registers */
27 #define TASR_BUF_SLOPE_MASK GENMASK(19, 16)
28 #define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */
29 #define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */
30 #define TCALIV(n) (0x30 + ((n) * 4))
31 #define TCALIV_EN BIT(31)
32 #define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */
33 #define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */
34 #define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */
35 #define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */
37 #define TRIM_BJT_CUR_MASK GENMASK(23, 20)
38 #define TRIM_BGR_MASK GENMASK(31, 28)
39 #define TRIM_VLSB_MASK GENMASK(15, 12)
40 #define TRIM_EN_CH BIT(7)
42 #define TER_ADC_PD BIT(30)
43 #define TER_EN BIT(31)
44 #define TRITSR_TEMP0_VAL_MASK GENMASK(7, 0)
45 #define TRITSR_TEMP1_VAL_MASK GENMASK(23, 16)
47 #define PROBE_SEL_ALL GENMASK(31, 30)
49 #define probe_status_offset(x) (30 + x)
50 #define SIGN_BIT BIT(7)
51 #define TEMP_VAL_MASK GENMASK(6, 0)
53 /* TMU OCOTP calibration data bitfields */
54 #define ANA0_EN BIT(25)
55 #define ANA0_BUF_VREF_MASK GENMASK(24, 20)
56 #define ANA0_BUF_SLOPE_MASK GENMASK(19, 16)
57 #define ANA0_HR_MASK GENMASK(15, 8)
58 #define ANA0_RT_MASK GENMASK(7, 0)
59 #define TRIM2_VLSB_MASK GENMASK(23, 20)
60 #define TRIM2_BGR_MASK GENMASK(19, 16)
61 #define TRIM2_BJT_CUR_MASK GENMASK(15, 12)
62 #define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8)
63 #define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6)
64 #define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28)
65 #define TRIM3_TCA40_0_MASK GENMASK(27, 16)
66 #define TRIM4_TCA40_1_MASK GENMASK(31, 20)
67 #define TRIM4_TCA105_0_MASK GENMASK(19, 8)
68 #define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0)
69 #define TRIM5_TCA105_1_MASK GENMASK(23, 12)
70 #define TRIM5_TCA25_1_MASK GENMASK(11, 0)
72 #define VER1_TEMP_LOW_LIMIT 10000
73 #define VER2_TEMP_LOW_LIMIT -40000
74 #define VER2_TEMP_HIGH_LIMIT 125000
79 struct thermal_soc_data {
82 int (*get_temp)(void *, int *);
86 struct imx8mm_tmu *priv;
88 struct thermal_zone_device *tzd;
94 const struct thermal_soc_data *socdata;
95 struct tmu_sensor sensors[];
98 static int imx8mm_tmu_get_temp(void *data, int *temp)
100 struct tmu_sensor *sensor = data;
101 struct imx8mm_tmu *tmu = sensor->priv;
104 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;
107 * Do not validate against the V bit (bit 31) due to errata
108 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid
112 if (*temp < VER1_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
118 static int imx8mp_tmu_get_temp(void *data, int *temp)
120 struct tmu_sensor *sensor = data;
121 struct imx8mm_tmu *tmu = sensor->priv;
125 val = readl_relaxed(tmu->base + TRITSR);
126 ready = test_bit(probe_status_offset(sensor->hw_id), &val);
130 val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) :
131 FIELD_GET(TRITSR_TEMP0_VAL_MASK, val);
132 if (val & SIGN_BIT) /* negative */
133 val = (~(val & TEMP_VAL_MASK) + 1);
136 if (*temp < VER2_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT)
142 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
144 struct tmu_sensor *sensor = tz->devdata;
145 struct imx8mm_tmu *tmu = sensor->priv;
147 return tmu->socdata->get_temp(sensor, temp);
150 static const struct thermal_zone_device_ops tmu_tz_ops = {
151 .get_temp = tmu_get_temp,
154 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
158 val = readl_relaxed(tmu->base + TER);
159 val = enable ? (val | TER_EN) : (val & ~TER_EN);
160 if (tmu->socdata->version == TMU_VER2)
161 val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD);
162 writel_relaxed(val, tmu->base + TER);
165 static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
169 val = readl_relaxed(tmu->base + TPS);
170 val |= PROBE_SEL_ALL;
171 writel_relaxed(val, tmu->base + TPS);
174 static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev,
175 struct imx8mm_tmu *tmu)
177 struct device *dev = &pdev->dev;
181 ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0);
183 dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret);
187 writel(FIELD_PREP(TASR_BUF_VREF_MASK,
188 FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) |
189 FIELD_PREP(TASR_BUF_SLOPE_MASK,
190 FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)),
193 writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) |
194 FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) |
195 ((ana0 & ANA0_EN) ? TCALIV_EN : 0),
196 tmu->base + TCALIV(0));
201 static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev,
202 struct imx8mm_tmu *tmu)
204 struct device *dev = &pdev->dev;
205 struct nvmem_cell *cell;
210 cell = nvmem_cell_get(dev, "calib");
212 return PTR_ERR(cell);
214 buf = nvmem_cell_read(cell, &len);
215 nvmem_cell_put(cell);
220 memcpy(trim, buf, min(len, sizeof(trim)));
225 "OCOTP nvmem cell length is %zu, must be 16.\n", len);
229 /* Blank sample hardware */
230 if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) {
231 /* Use a default 25C binary codes */
232 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
233 tmu->base + TCALIV(0));
234 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
235 tmu->base + TCALIV(1));
239 writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
240 FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) |
241 FIELD_PREP(TASR_BUF_SLOPE_MASK,
242 FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])),
245 writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
246 FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) |
247 FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) |
248 FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) |
252 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
253 FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) |
254 (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) |
255 FIELD_PREP(TCALIV_SNSR105C_MASK,
256 FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])),
257 tmu->base + TCALIV(0));
259 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
260 FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) |
261 FIELD_PREP(TCALIV_SNSR105C_MASK,
262 FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])),
263 tmu->base + TCALIV(1));
265 writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
266 FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) |
267 FIELD_PREP(TCALIV_SNSR105C_MASK,
268 FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])),
269 tmu->base + TCALIV(2));
274 static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev,
275 struct imx8mm_tmu *tmu)
277 struct device *dev = &pdev->dev;
280 * Lack of calibration data OCOTP reference is not considered
281 * fatal to retain compatibility with old DTs. It is however
282 * strongly recommended to update such old DTs to get correct
283 * temperature compensation values for each SoC.
285 if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) {
287 "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n");
291 if (tmu->socdata->version == TMU_VER1)
292 return imx8mm_tmu_probe_set_calib_v1(pdev, tmu);
294 return imx8mm_tmu_probe_set_calib_v2(pdev, tmu);
297 static int imx8mm_tmu_probe(struct platform_device *pdev)
299 const struct thermal_soc_data *data;
300 struct imx8mm_tmu *tmu;
304 data = of_device_get_match_data(&pdev->dev);
306 tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,
307 data->num_sensors), GFP_KERNEL);
313 tmu->base = devm_platform_ioremap_resource(pdev, 0);
314 if (IS_ERR(tmu->base))
315 return PTR_ERR(tmu->base);
317 tmu->clk = devm_clk_get(&pdev->dev, NULL);
318 if (IS_ERR(tmu->clk))
319 return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),
320 "failed to get tmu clock\n");
322 ret = clk_prepare_enable(tmu->clk);
324 dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);
328 /* disable the monitor during initialization */
329 imx8mm_tmu_enable(tmu, false);
331 for (i = 0; i < data->num_sensors; i++) {
332 tmu->sensors[i].priv = tmu;
333 tmu->sensors[i].tzd =
334 devm_thermal_of_zone_register(&pdev->dev, i,
337 if (IS_ERR(tmu->sensors[i].tzd)) {
338 ret = PTR_ERR(tmu->sensors[i].tzd);
340 "failed to register thermal zone sensor[%d]: %d\n",
344 tmu->sensors[i].hw_id = i;
346 if (devm_thermal_add_hwmon_sysfs(tmu->sensors[i].tzd))
347 dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
350 platform_set_drvdata(pdev, tmu);
352 ret = imx8mm_tmu_probe_set_calib(pdev, tmu);
356 /* enable all the probes for V2 TMU */
357 if (tmu->socdata->version == TMU_VER2)
358 imx8mm_tmu_probe_sel_all(tmu);
360 /* enable the monitor */
361 imx8mm_tmu_enable(tmu, true);
366 clk_disable_unprepare(tmu->clk);
370 static int imx8mm_tmu_remove(struct platform_device *pdev)
372 struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);
375 imx8mm_tmu_enable(tmu, false);
377 clk_disable_unprepare(tmu->clk);
378 platform_set_drvdata(pdev, NULL);
383 static struct thermal_soc_data imx8mm_tmu_data = {
386 .get_temp = imx8mm_tmu_get_temp,
389 static struct thermal_soc_data imx8mp_tmu_data = {
392 .get_temp = imx8mp_tmu_get_temp,
395 static const struct of_device_id imx8mm_tmu_table[] = {
396 { .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
397 { .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },
400 MODULE_DEVICE_TABLE(of, imx8mm_tmu_table);
402 static struct platform_driver imx8mm_tmu = {
404 .name = "i.mx8mm_thermal",
405 .of_match_table = imx8mm_tmu_table,
407 .probe = imx8mm_tmu_probe,
408 .remove = imx8mm_tmu_remove,
410 module_platform_driver(imx8mm_tmu);
412 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
413 MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver");
414 MODULE_LICENSE("GPL v2");