1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
22 #include <asm/byteorder.h>
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
33 struct pci_serial_quirk {
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
46 #define PCI_NUM_BAR_RESOURCES 6
48 struct serial_private {
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
56 static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
59 static void moan_device(const char *str, struct pci_dev *dev)
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
72 setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
75 struct pci_dev *dev = priv->dev;
77 if (bar >= PCI_NUM_BAR_RESOURCES)
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
100 * ADDI-DATA GmbH communication cards <info@addi-data.com>
102 static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
119 offset += ((idx - 6) * board->uart_offset);
122 return setup_port(priv, port, bar, offset, board->reg_shift);
126 * AFAVLAB uses a different mixture of BARs and offsets
127 * Not that ugly ;) -- HW
130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
133 unsigned int bar, offset = board->first_offset;
135 bar = FL_GET_BASE(board->flags);
140 offset += (idx - 4) * board->uart_offset;
143 return setup_port(priv, port, bar, offset, board->reg_shift);
147 * HP's Remote Management Console. The Diva chip came in several
148 * different versions. N-class, L2000 and A500 have two Diva chips, each
149 * with 3 UARTs (the third UART on the second chip is unused). Superdome
150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
151 * one Diva chip, but it has been expanded to 5 UARTs.
153 static int pci_hp_diva_init(struct pci_dev *dev)
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
180 * HP's Diva chip puts the 4th/5th serial port further out, and
181 * some serial ports are supposed to be hidden on certain models.
184 pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 offset += idx * board->uart_offset;
208 return setup_port(priv, port, bar, offset, board->reg_shift);
212 * Added for EKF Intel i960 serial boards
214 static int pci_inteli960ni_init(struct pci_dev *dev)
218 if (!(dev->subsystem_device & 0x1000))
221 /* is firmware started? */
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) { /* RESET value */
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
231 * Some PCI serial cards using the PLX 9050 PCI interface chip require
232 * that the card interrupt be explicitly enabled or disabled. This
233 * seems to be mainly needed on card using the PLX which also use I/O
236 static int pci_plx9050_init(struct pci_dev *dev)
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
254 * As the megawolf cards have the int pins active
255 * high, and have 2 UART chips, both ints must be
256 * enabled on the 9050. Also, the UARTS are set in
257 * 16450 mode by default, so we have to enable the
258 * 16C950 'enhanced' mode so that we can use the
263 * enable/disable interrupts
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
268 writel(irq_config, p + 0x4c);
271 * Read the register back to ensure that it took effect.
279 static void pci_plx9050_exit(struct pci_dev *dev)
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
294 * Read the register back to ensure that it took effect.
301 #define NI8420_INT_ENABLE_REG 0x38
302 #define NI8420_INT_ENABLE_BIT 0x2000
304 static void pci_ni8420_exit(struct pci_dev *dev)
307 unsigned int bar = 0;
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
314 p = pci_ioremap_bar(dev, bar);
318 /* Disable the CPU Interrupt */
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
326 #define MITE_IOWBSR1 0xc4
327 #define MITE_IOWCR1 0xf4
328 #define MITE_LCIMR1 0x08
329 #define MITE_LCIMR2 0x10
331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
333 static void pci_ni8430_exit(struct pci_dev *dev)
336 unsigned int bar = 0;
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
343 p = pci_ioremap_bar(dev, bar);
347 /* Disable the CPU Interrupt */
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
357 unsigned int bar, offset = board->first_offset;
362 /* first four channels map to 0, 0x100, 0x200, 0x300 */
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
366 offset += idx * board->uart_offset + 0xC00;
367 } else /* we have only 8 ports on PMC-OCTALPRO */
370 return setup_port(priv, port, bar, offset, board->reg_shift);
374 * This does initialization for PMC OCTALPRO cards:
375 * maps the device memory, resets the UARTs (needed, bc
376 * if the module is removed and inserted again, the card
377 * is in the sleep mode) and enables global interrupt.
380 /* global control register offset for SBS PMC-OctalPro */
381 #define OCT_REG_CR_OFF 0x500
383 static int sbs_init(struct pci_dev *dev)
387 p = pci_ioremap_bar(dev, 0);
391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
392 writeb(0x10, p + OCT_REG_CR_OFF);
394 writeb(0x0, p + OCT_REG_CR_OFF);
396 /* Set bit-2 (INTENABLE) of Control Register */
397 writeb(0x4, p + OCT_REG_CR_OFF);
404 * Disables the global interrupt of PMC-OctalPro
407 static void sbs_exit(struct pci_dev *dev)
411 p = pci_ioremap_bar(dev, 0);
412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
414 writeb(0, p + OCT_REG_CR_OFF);
419 * SIIG serial cards have an PCI interface chip which also controls
420 * the UART clocking frequency. Each UART can be clocked independently
421 * (except cards equipped with 4 UARTs) and initial clocking settings
422 * are stored in the EEPROM chip. It can cause problems because this
423 * version of serial driver doesn't support differently clocked UART's
424 * on single PCI card. To prevent this, initialization functions set
425 * high frequency clocking for all UART's on given card. It is safe (I
426 * hope) because it doesn't touch EEPROM settings to prevent conflicts
427 * with other OSes (like M$ DOS).
429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
431 * There is two family of SIIG serial cards with different PCI
432 * interface chip and different configuration methods:
433 * - 10x cards have control registers in IO and/or memory space;
434 * - 20x cards have control registers in standard PCI configuration space.
436 * Note: all 10x cards have PCI device ids 0x10..
437 * all 20x cards have PCI device ids 0x20..
439 * There are also Quartet Serial cards which use Oxford Semiconductor
440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
442 * Note: some SIIG cards are probed by the parport_serial object.
445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
448 static int pci_siig10x_init(struct pci_dev *dev)
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
460 default: /* 1S1P, 4S */
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
469 writew(readw(p + 0x28) & data, p + 0x28);
475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
478 static int pci_siig20x_init(struct pci_dev *dev)
482 /* Change clock frequency for the first UART. */
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
486 /* If this card has 2 UART, we have to do the same with second UART. */
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
495 static int pci_siig_init(struct pci_dev *dev)
497 unsigned int type = dev->device & 0xff00;
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
504 moan_device("Unknown SIIG card", dev);
508 static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
516 offset = (idx - 4) * 8;
519 return setup_port(priv, port, bar, offset, 0);
523 * Timedia has an explosion of boards, and to avoid the PCI table from
524 * growing *huge*, we use this function to collapse some 70 entries
525 * in the PCI table into one, for sanity's and compactness's sake.
527 static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
531 static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
539 static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
546 static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
551 static const struct timedia_struct {
553 const unsigned short *ids;
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
563 * listing them individually, this driver merely grabs them all with
564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
565 * and should be left free to be claimed by parport_serial instead.
567 static int pci_timedia_probe(struct pci_dev *dev)
570 * Check the third digit of the subdevice ID
571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
583 static int pci_timedia_init(struct pci_dev *dev)
585 const unsigned short *ids;
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
598 * Timedia/SUNIX uses a mixture of BARs and offsets
599 * Ugh, this is ugly as all hell --- TYT
602 pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
606 unsigned int bar = 0, offset = board->first_offset;
613 offset = board->uart_offset;
620 offset = board->uart_offset;
629 return setup_port(priv, port, bar, offset, board->reg_shift);
633 * Some Titan cards are also a little weird
636 titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
640 unsigned int bar, offset = board->first_offset;
651 offset = (idx - 2) * board->uart_offset;
654 return setup_port(priv, port, bar, offset, board->reg_shift);
657 static int pci_xircom_init(struct pci_dev *dev)
663 static int pci_ni8420_init(struct pci_dev *dev)
666 unsigned int bar = 0;
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
673 p = pci_ioremap_bar(dev, bar);
677 /* Enable CPU Interrupt */
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
685 #define MITE_IOWBSR1_WSIZE 0xa
686 #define MITE_IOWBSR1_WIN_OFFSET 0x800
687 #define MITE_IOWBSR1_WENAB (1 << 7)
688 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
692 static int pci_ni8430_init(struct pci_dev *dev)
695 struct pci_bus_region region;
697 unsigned int bar = 0;
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
704 p = pci_ioremap_bar(dev, bar);
709 * Set device window address and size in BAR0, while acknowledging that
710 * the resource structure may contain a translated address that differs
711 * from the address the device responds to.
713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
718 /* Set window access to go to RAMSEL IO address space */
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
722 /* Enable IO Bus Interrupt 0 */
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
725 /* Enable CPU Interrupt */
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
732 /* UART Port Control Register */
733 #define NI8430_PORTCON 0x0f
734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
737 pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
741 struct pci_dev *dev = priv->dev;
743 unsigned int bar, offset = board->first_offset;
745 if (idx >= board->num_ports)
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
751 p = pci_ioremap_bar(dev, bar);
755 /* enable the transceiver */
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
761 return setup_port(priv, port, bar, offset, board->reg_shift);
764 static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772 /* netmos apparently orders BARs by datasheet layout, so serial
773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
777 return setup_port(priv, port, bar, 0, board->reg_shift);
779 return pci_default_setup(priv, board, port, idx);
783 /* the 99xx series comes with a range of device IDs and a variety
786 * 9900 has varying capabilities and can cascade to sub-controllers
787 * (cascading should be purely internal)
788 * 9904 is hardwired with 4 serial ports
789 * 9912 and 9922 are hardwired with 2 serial ports
791 static int pci_netmos_9900_numports(struct pci_dev *dev)
793 unsigned int c = dev->class;
795 unsigned short sub_serports;
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803 /* two possibilities: 0x30ps encodes number of parallel and
804 * serial ports, or 0x1000 indicates *something*. This is not
805 * immediately obvious, since the 2s1p+4s configuration seems
806 * to offer all functionality on functions 0..2, while still
807 * advertising the same function 3 as the 4s+2s1p config.
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
818 moan_device("unknown NetMos/Mostech program interface", dev);
822 static int pci_netmos_init(struct pci_dev *dev)
824 /* subdevice 0x00PS means <P> parallel, <S> serial */
825 unsigned int num_serial = dev->subsystem_device & 0xf;
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
835 switch (dev->device) { /* FALLTHROUGH on all */
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
856 * These chips are available with optionally one parallel port and up to
857 * two serial ports. Unfortunately they all have the same product id.
859 * Basic configuration is done over a region of 32 I/O ports. The base
860 * ioport is called INTA or INTC, depending on docs/other drivers.
862 * The region of the 32 I/O ports is configured in POSIO0R...
866 #define ITE_887x_MISCR 0x9c
867 #define ITE_887x_INTCBAR 0x78
868 #define ITE_887x_UARTBAR 0x7c
869 #define ITE_887x_PS0BAR 0x10
870 #define ITE_887x_POSIO0 0x60
873 #define ITE_887x_IOSIZE 32
874 /* I/O space size (bits 26-24; 8 bytes = 011b) */
875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876 /* I/O space size (bits 26-24; 32 bytes = 101b) */
877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
879 #define ITE_887x_POSIO_SPEED (3 << 29)
880 /* enable IO_Space bit */
881 #define ITE_887x_POSIO_ENABLE (1 << 31)
883 static int pci_ite887x_init(struct pci_dev *dev)
885 /* inta_addr are the configuration addresses of the ITE */
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
892 /* search for the base-ioport */
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
897 if (iobase != NULL) {
898 /* write POSIO0R - speed | size | ioport */
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902 /* write INTCBAR - ioport */
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
905 ret = inb(inta_addr[i]);
907 /* ioport connected */
910 release_region(iobase->start, ITE_887x_IOSIZE);
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
921 /* start of undocumented type checking (see parport_pc.c) */
922 type = inb(iobase->start + 0x18) & 0x0f;
925 case 0x2: /* ITE8871 (1P) */
926 case 0xa: /* ITE8875 (1P) */
929 case 0xe: /* ITE8872 (2S1P) */
932 case 0x6: /* ITE8873 (1S) */
935 case 0x8: /* ITE8874 (2S) */
939 moan_device("Unknown ITE887x", dev);
943 /* configure all serial ports */
944 for (i = 0; i < ret; i++) {
945 /* read the I/O port from the device */
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
948 ioport &= 0x0000FF00; /* the actual base address */
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
953 /* write the ioport to the UARTBAR */
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
956 uartbar |= (ioport << (16 * i)); /* set the ioport */
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
959 /* get current config */
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961 /* disable interrupts (UARTx_Routing[3:0]) */
962 miscr &= ~(0xf << (12 - 4 * i));
963 /* activate the UART (UARTx_En) */
964 miscr |= 1 << (23 - i);
965 /* write new config with activated UART */
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
970 /* the device has no UARTs if we get here */
971 release_region(iobase->start, ITE_887x_IOSIZE);
977 static void pci_ite887x_exit(struct pci_dev *dev)
980 /* the ioport is bit 0-15 in POSIO0R */
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
983 release_region(ioport, ITE_887x_IOSIZE);
987 * EndRun Technologies.
988 * Determine the number of ports available on the device.
990 #define PCI_VENDOR_ID_ENDRUN 0x7401
991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
993 static int pci_endrun_init(struct pci_dev *dev)
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
999 /* EndRun device is all 0xexxx */
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1004 p = pci_iomap(dev, 0, 5);
1008 deviceID = ioread32(p);
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1013 "%d ports detected on EndRun PCI Express device\n",
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1021 * Oxford Semiconductor Inc.
1022 * Check that device is part of the Tornado range of devices, then determine
1023 * the number of ports available on the device.
1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1031 /* OxSemi Tornado devices are all 0xCxxx */
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1036 p = pci_iomap(dev, 0, 5);
1040 deviceID = ioread32(p);
1041 /* Tornado device */
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1045 "%d ports detected on Oxford PCI Express device\n",
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1052 static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1060 /* Quatech devices have their own extra interface features */
1062 struct quatech_feature {
1067 #define QPCR_TEST_FOR1 0x3F
1068 #define QPCR_TEST_GET1 0x00
1069 #define QPCR_TEST_FOR2 0x40
1070 #define QPCR_TEST_GET2 0x40
1071 #define QPCR_TEST_FOR3 0x80
1072 #define QPCR_TEST_GET3 0x40
1073 #define QPCR_TEST_FOR4 0xC0
1074 #define QPCR_TEST_GET4 0x80
1076 #define QOPR_CLOCK_X1 0x0000
1077 #define QOPR_CLOCK_X2 0x0001
1078 #define QOPR_CLOCK_X4 0x0002
1079 #define QOPR_CLOCK_X8 0x0003
1080 #define QOPR_CLOCK_RATE_MASK 0x0003
1083 static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1106 static int pci_quatech_amcc(u16 devid)
1108 struct quatech_feature *qf = &quatech_cards[0];
1110 if (qf->devid == devid)
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1118 static int pci_quatech_rqopr(struct uart_8250_port *port)
1120 unsigned long base = port->port.iobase;
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1132 unsigned long base = port->port.iobase;
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1142 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1144 unsigned long base = port->port.iobase;
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1160 unsigned long base = port->port.iobase;
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1174 unsigned long base = port->port.iobase;
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1190 static int pci_quatech_test(struct uart_8250_port *port)
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1212 pci_quatech_wqopr(port, qopr);
1216 static int pci_quatech_clock(struct uart_8250_port *port)
1219 unsigned long clock;
1221 if (pci_quatech_test(port) < 0)
1224 qopr = pci_quatech_rqopr(port);
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1247 set = QOPR_CLOCK_X8;
1250 set = QOPR_CLOCK_X1;
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1256 pci_quatech_wqopr(port, qopr);
1260 static int pci_quatech_rs422(struct uart_8250_port *port)
1265 if (!pci_quatech_has_qmcr(port))
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1271 pci_quatech_wqmcr(port, qmcr);
1275 static int pci_quatech_init(struct pci_dev *dev)
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1291 static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1295 /* Needed by pci_quatech calls below */
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297 /* Set up the clocking */
1298 port->port.uartclk = pci_quatech_clock(port);
1299 /* For now just warn about RS422 */
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1305 static void pci_quatech_exit(struct pci_dev *dev)
1309 static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1313 unsigned int bar, offset = board->first_offset, maxnr;
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1319 offset += idx * board->uart_offset;
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1330 static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1334 unsigned int bar, offset = board->first_offset, maxnr;
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1340 offset += idx * board->uart_offset;
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1355 ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1371 pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1375 return setup_port(priv, port, 2, idx * 8, 0);
1379 pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1383 int ret = pci_default_setup(priv, board, port, idx);
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1390 /* RTS will control by MCR if this bit is 0 */
1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1393 #define FINTEK_RTS_INVERT BIT(5)
1395 /* We should do proper H/W transceiver setting before change to RS485 mode */
1396 static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1401 u8 *index = (u8 *) port->private_data;
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1410 memset(rs485, 0, sizeof(*rs485));
1412 /* F81504/508/512 not support RTS delay before or after send */
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416 /* Enable RTS H/W control mode */
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420 /* RTS driving high on TX */
1421 setting &= ~FINTEK_RTS_INVERT;
1423 /* RTS driving low on TX */
1424 setting |= FINTEK_RTS_INVERT;
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1430 /* Disable RTS H/W control mode */
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1442 static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1446 struct pci_dev *pdev = priv->dev;
1451 config_base = 0x40 + 0x08 * idx;
1453 /* Get the io address from configuration space */
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1466 /* preserve index in PCI configuration space */
1468 port->port.private_data = data;
1473 static int pci_fintek_init(struct pci_dev *dev)
1475 unsigned long iobase;
1477 resource_size_t bar_data[3];
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1487 switch (dev->device) {
1488 case 0x1104: /* 4 ports */
1489 case 0x1108: /* 8 ports */
1490 max_port = dev->device & 0xff;
1492 case 0x1112: /* 12 ports */
1499 /* Get the io address dispatch from the BIOS */
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1504 for (i = 0; i < max_port; ++i) {
1505 /* UART0 configuration offset start from 0x40 */
1506 config_base = 0x40 + 0x08 * i;
1508 /* Calculate Real IO Port */
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1511 /* Enable UART I/O port */
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1514 /* Select 128-byte FIFO and 8x FIFO threshold */
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1528 /* re-apply RS232/485 mode when
1529 * pciserial_resume_ports()
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1534 /* First init without port data
1535 * force init to RS232 Mode
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1544 static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1554 return pci_default_setup(priv, board, port, idx);
1557 static void kt_handle_break(struct uart_port *p)
1559 struct uart_8250_port *up = up_to_u8250p(p);
1561 * On receipt of a BI, serial device in Intel ME (Intel
1562 * management engine) needs to have its fifos cleared for sane
1563 * SOL (Serial Over Lan) output.
1565 serial8250_clear_and_reinit_fifos(up);
1568 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1570 struct uart_8250_port *up = up_to_u8250p(p);
1574 * When the Intel ME (management engine) gets reset its serial
1575 * port registers could return 0 momentarily. Functions like
1576 * serial8250_console_write, read and save the IER, perform
1577 * some operation and then restore it. In order to avoid
1578 * setting IER register inadvertently to 0, if the value read
1579 * is 0, double check with ier value in uart_8250_port and use
1580 * that instead. up->ier should be the same value as what is
1581 * currently configured.
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1591 static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1601 static int pci_eg20t_init(struct pci_dev *dev)
1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1611 pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1621 pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1631 pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1640 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642 #define PCI_DEVICE_ID_OCTPRO 0x0001
1643 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1644 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1645 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1646 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1647 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1648 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1651 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1654 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1655 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1656 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1657 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1658 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1659 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1660 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1661 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1662 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1663 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1664 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1665 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1666 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1667 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1668 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1669 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1670 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1671 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1672 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1673 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1674 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1675 #define PCI_VENDOR_ID_WCH 0x4348
1676 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1677 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1678 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1679 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1680 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1681 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1682 #define PCI_VENDOR_ID_AGESTAR 0x5372
1683 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1684 #define PCI_VENDOR_ID_ASIX 0x9710
1685 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1686 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1688 #define PCIE_VENDOR_ID_WCH 0x1c00
1689 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1690 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1691 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1693 #define PCI_VENDOR_ID_PERICOM 0x12D8
1694 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1695 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1696 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1697 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1699 #define PCI_VENDOR_ID_ACCESIO 0x494f
1700 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1701 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1702 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1703 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1704 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1705 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1706 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1708 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1710 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1712 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1716 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1717 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1718 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1719 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1720 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1721 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1722 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1728 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1736 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1737 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1738 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1741 * Master list of serial port init/setup/exit quirks.
1742 * This does not describe the general nature of the port.
1743 * (ie, baud base, number and location of ports, etc)
1745 * This list is ordered alphabetically by vendor then device.
1746 * Specific entries must come before more generic entries.
1748 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1750 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1753 .vendor = PCI_VENDOR_ID_AMCC,
1754 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1755 .subvendor = PCI_ANY_ID,
1756 .subdevice = PCI_ANY_ID,
1757 .setup = addidata_apci7800_setup,
1760 * AFAVLAB cards - these may be called via parport_serial
1761 * It is not clear whether this applies to all products.
1764 .vendor = PCI_VENDOR_ID_AFAVLAB,
1765 .device = PCI_ANY_ID,
1766 .subvendor = PCI_ANY_ID,
1767 .subdevice = PCI_ANY_ID,
1768 .setup = afavlab_setup,
1774 .vendor = PCI_VENDOR_ID_HP,
1775 .device = PCI_DEVICE_ID_HP_DIVA,
1776 .subvendor = PCI_ANY_ID,
1777 .subdevice = PCI_ANY_ID,
1778 .init = pci_hp_diva_init,
1779 .setup = pci_hp_diva_setup,
1785 .vendor = PCI_VENDOR_ID_INTEL,
1786 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1787 .subvendor = 0xe4bf,
1788 .subdevice = PCI_ANY_ID,
1789 .init = pci_inteli960ni_init,
1790 .setup = pci_default_setup,
1793 .vendor = PCI_VENDOR_ID_INTEL,
1794 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1795 .subvendor = PCI_ANY_ID,
1796 .subdevice = PCI_ANY_ID,
1797 .setup = skip_tx_en_setup,
1800 .vendor = PCI_VENDOR_ID_INTEL,
1801 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 .setup = skip_tx_en_setup,
1807 .vendor = PCI_VENDOR_ID_INTEL,
1808 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1809 .subvendor = PCI_ANY_ID,
1810 .subdevice = PCI_ANY_ID,
1811 .setup = skip_tx_en_setup,
1814 .vendor = PCI_VENDOR_ID_INTEL,
1815 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1816 .subvendor = PCI_ANY_ID,
1817 .subdevice = PCI_ANY_ID,
1818 .setup = ce4100_serial_setup,
1821 .vendor = PCI_VENDOR_ID_INTEL,
1822 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .setup = kt_serial_setup,
1831 .vendor = PCI_VENDOR_ID_ITE,
1832 .device = PCI_DEVICE_ID_ITE_8872,
1833 .subvendor = PCI_ANY_ID,
1834 .subdevice = PCI_ANY_ID,
1835 .init = pci_ite887x_init,
1836 .setup = pci_default_setup,
1837 .exit = pci_ite887x_exit,
1840 * National Instruments
1843 .vendor = PCI_VENDOR_ID_NI,
1844 .device = PCI_DEVICE_ID_NI_PCI23216,
1845 .subvendor = PCI_ANY_ID,
1846 .subdevice = PCI_ANY_ID,
1847 .init = pci_ni8420_init,
1848 .setup = pci_default_setup,
1849 .exit = pci_ni8420_exit,
1852 .vendor = PCI_VENDOR_ID_NI,
1853 .device = PCI_DEVICE_ID_NI_PCI2328,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .init = pci_ni8420_init,
1857 .setup = pci_default_setup,
1858 .exit = pci_ni8420_exit,
1861 .vendor = PCI_VENDOR_ID_NI,
1862 .device = PCI_DEVICE_ID_NI_PCI2324,
1863 .subvendor = PCI_ANY_ID,
1864 .subdevice = PCI_ANY_ID,
1865 .init = pci_ni8420_init,
1866 .setup = pci_default_setup,
1867 .exit = pci_ni8420_exit,
1870 .vendor = PCI_VENDOR_ID_NI,
1871 .device = PCI_DEVICE_ID_NI_PCI2322,
1872 .subvendor = PCI_ANY_ID,
1873 .subdevice = PCI_ANY_ID,
1874 .init = pci_ni8420_init,
1875 .setup = pci_default_setup,
1876 .exit = pci_ni8420_exit,
1879 .vendor = PCI_VENDOR_ID_NI,
1880 .device = PCI_DEVICE_ID_NI_PCI2324I,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_ni8420_init,
1884 .setup = pci_default_setup,
1885 .exit = pci_ni8420_exit,
1888 .vendor = PCI_VENDOR_ID_NI,
1889 .device = PCI_DEVICE_ID_NI_PCI2322I,
1890 .subvendor = PCI_ANY_ID,
1891 .subdevice = PCI_ANY_ID,
1892 .init = pci_ni8420_init,
1893 .setup = pci_default_setup,
1894 .exit = pci_ni8420_exit,
1897 .vendor = PCI_VENDOR_ID_NI,
1898 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .init = pci_ni8420_init,
1902 .setup = pci_default_setup,
1903 .exit = pci_ni8420_exit,
1906 .vendor = PCI_VENDOR_ID_NI,
1907 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1908 .subvendor = PCI_ANY_ID,
1909 .subdevice = PCI_ANY_ID,
1910 .init = pci_ni8420_init,
1911 .setup = pci_default_setup,
1912 .exit = pci_ni8420_exit,
1915 .vendor = PCI_VENDOR_ID_NI,
1916 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .init = pci_ni8420_init,
1920 .setup = pci_default_setup,
1921 .exit = pci_ni8420_exit,
1924 .vendor = PCI_VENDOR_ID_NI,
1925 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1926 .subvendor = PCI_ANY_ID,
1927 .subdevice = PCI_ANY_ID,
1928 .init = pci_ni8420_init,
1929 .setup = pci_default_setup,
1930 .exit = pci_ni8420_exit,
1933 .vendor = PCI_VENDOR_ID_NI,
1934 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .init = pci_ni8420_init,
1938 .setup = pci_default_setup,
1939 .exit = pci_ni8420_exit,
1942 .vendor = PCI_VENDOR_ID_NI,
1943 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .init = pci_ni8420_init,
1947 .setup = pci_default_setup,
1948 .exit = pci_ni8420_exit,
1951 .vendor = PCI_VENDOR_ID_NI,
1952 .device = PCI_ANY_ID,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .init = pci_ni8430_init,
1956 .setup = pci_ni8430_setup,
1957 .exit = pci_ni8430_exit,
1961 .vendor = PCI_VENDOR_ID_QUATECH,
1962 .device = PCI_ANY_ID,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_quatech_init,
1966 .setup = pci_quatech_setup,
1967 .exit = pci_quatech_exit,
1973 .vendor = PCI_VENDOR_ID_PANACOM,
1974 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .init = pci_plx9050_init,
1978 .setup = pci_default_setup,
1979 .exit = pci_plx9050_exit,
1982 .vendor = PCI_VENDOR_ID_PANACOM,
1983 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .init = pci_plx9050_init,
1987 .setup = pci_default_setup,
1988 .exit = pci_plx9050_exit,
1991 * Pericom (Only 7954 - It have a offset jump for port 4)
1994 .vendor = PCI_VENDOR_ID_PERICOM,
1995 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = pci_pericom_setup,
2004 .vendor = PCI_VENDOR_ID_PLX,
2005 .device = PCI_DEVICE_ID_PLX_9050,
2006 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2007 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2008 .init = pci_plx9050_init,
2009 .setup = pci_default_setup,
2010 .exit = pci_plx9050_exit,
2013 .vendor = PCI_VENDOR_ID_PLX,
2014 .device = PCI_DEVICE_ID_PLX_9050,
2015 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2016 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2017 .init = pci_plx9050_init,
2018 .setup = pci_default_setup,
2019 .exit = pci_plx9050_exit,
2022 .vendor = PCI_VENDOR_ID_PLX,
2023 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2024 .subvendor = PCI_VENDOR_ID_PLX,
2025 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2026 .init = pci_plx9050_init,
2027 .setup = pci_default_setup,
2028 .exit = pci_plx9050_exit,
2031 * SBS Technologies, Inc., PMC-OCTALPRO 232
2034 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2035 .device = PCI_DEVICE_ID_OCTPRO,
2036 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2037 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2043 * SBS Technologies, Inc., PMC-OCTALPRO 422
2046 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2047 .device = PCI_DEVICE_ID_OCTPRO,
2048 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2049 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2055 * SBS Technologies, Inc., P-Octal 232
2058 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2059 .device = PCI_DEVICE_ID_OCTPRO,
2060 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2061 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2067 * SBS Technologies, Inc., P-Octal 422
2070 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2071 .device = PCI_DEVICE_ID_OCTPRO,
2072 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2073 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2079 * SIIG cards - these may be called via parport_serial
2082 .vendor = PCI_VENDOR_ID_SIIG,
2083 .device = PCI_ANY_ID,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .init = pci_siig_init,
2087 .setup = pci_siig_setup,
2093 .vendor = PCI_VENDOR_ID_TITAN,
2094 .device = PCI_DEVICE_ID_TITAN_400L,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = titan_400l_800l_setup,
2100 .vendor = PCI_VENDOR_ID_TITAN,
2101 .device = PCI_DEVICE_ID_TITAN_800L,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = titan_400l_800l_setup,
2110 .vendor = PCI_VENDOR_ID_TIMEDIA,
2111 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2112 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2113 .subdevice = PCI_ANY_ID,
2114 .probe = pci_timedia_probe,
2115 .init = pci_timedia_init,
2116 .setup = pci_timedia_setup,
2119 .vendor = PCI_VENDOR_ID_TIMEDIA,
2120 .device = PCI_ANY_ID,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = pci_timedia_setup,
2126 * SUNIX (Timedia) cards
2127 * Do not "probe" for these cards as there is at least one combination
2128 * card that should be handled by parport_pc that doesn't match the
2129 * rule in pci_timedia_probe.
2130 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2131 * There are some boards with part number SER5037AL that report
2132 * subdevice ID 0x0002.
2135 .vendor = PCI_VENDOR_ID_SUNIX,
2136 .device = PCI_DEVICE_ID_SUNIX_1999,
2137 .subvendor = PCI_VENDOR_ID_SUNIX,
2138 .subdevice = PCI_ANY_ID,
2139 .init = pci_timedia_init,
2140 .setup = pci_timedia_setup,
2146 .vendor = PCI_VENDOR_ID_XIRCOM,
2147 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2148 .subvendor = PCI_ANY_ID,
2149 .subdevice = PCI_ANY_ID,
2150 .init = pci_xircom_init,
2151 .setup = pci_default_setup,
2154 * Netmos cards - these may be called via parport_serial
2157 .vendor = PCI_VENDOR_ID_NETMOS,
2158 .device = PCI_ANY_ID,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .init = pci_netmos_init,
2162 .setup = pci_netmos_9900_setup,
2165 * EndRun Technologies
2168 .vendor = PCI_VENDOR_ID_ENDRUN,
2169 .device = PCI_ANY_ID,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .init = pci_endrun_init,
2173 .setup = pci_default_setup,
2176 * For Oxford Semiconductor Tornado based devices
2179 .vendor = PCI_VENDOR_ID_OXSEMI,
2180 .device = PCI_ANY_ID,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .init = pci_oxsemi_tornado_init,
2184 .setup = pci_default_setup,
2187 .vendor = PCI_VENDOR_ID_MAINPINE,
2188 .device = PCI_ANY_ID,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .init = pci_oxsemi_tornado_init,
2192 .setup = pci_default_setup,
2195 .vendor = PCI_VENDOR_ID_DIGI,
2196 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2197 .subvendor = PCI_SUBVENDOR_ID_IBM,
2198 .subdevice = PCI_ANY_ID,
2199 .init = pci_oxsemi_tornado_init,
2200 .setup = pci_default_setup,
2203 .vendor = PCI_VENDOR_ID_INTEL,
2205 .subvendor = PCI_ANY_ID,
2206 .subdevice = PCI_ANY_ID,
2207 .init = pci_eg20t_init,
2208 .setup = pci_default_setup,
2211 .vendor = PCI_VENDOR_ID_INTEL,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .init = pci_eg20t_init,
2216 .setup = pci_default_setup,
2219 .vendor = PCI_VENDOR_ID_INTEL,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_eg20t_init,
2224 .setup = pci_default_setup,
2227 .vendor = PCI_VENDOR_ID_INTEL,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .init = pci_eg20t_init,
2232 .setup = pci_default_setup,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .init = pci_eg20t_init,
2240 .setup = pci_default_setup,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .init = pci_eg20t_init,
2248 .setup = pci_default_setup,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .init = pci_eg20t_init,
2256 .setup = pci_default_setup,
2261 .subvendor = PCI_ANY_ID,
2262 .subdevice = PCI_ANY_ID,
2263 .init = pci_eg20t_init,
2264 .setup = pci_default_setup,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .init = pci_eg20t_init,
2272 .setup = pci_default_setup,
2275 * Cronyx Omega PCI (PLX-chip based)
2278 .vendor = PCI_VENDOR_ID_PLX,
2279 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .setup = pci_omegapci_setup,
2284 /* WCH CH353 1S1P card (16550 clone) */
2286 .vendor = PCI_VENDOR_ID_WCH,
2287 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .setup = pci_wch_ch353_setup,
2292 /* WCH CH353 2S1P card (16550 clone) */
2294 .vendor = PCI_VENDOR_ID_WCH,
2295 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .setup = pci_wch_ch353_setup,
2300 /* WCH CH353 4S card (16550 clone) */
2302 .vendor = PCI_VENDOR_ID_WCH,
2303 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_wch_ch353_setup,
2308 /* WCH CH353 2S1PF card (16550 clone) */
2310 .vendor = PCI_VENDOR_ID_WCH,
2311 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .setup = pci_wch_ch353_setup,
2316 /* WCH CH352 2S card (16550 clone) */
2318 .vendor = PCI_VENDOR_ID_WCH,
2319 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .setup = pci_wch_ch353_setup,
2324 /* WCH CH355 4S card (16550 clone) */
2326 .vendor = PCI_VENDOR_ID_WCH,
2327 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .setup = pci_wch_ch355_setup,
2332 /* WCH CH382 2S card (16850 clone) */
2334 .vendor = PCIE_VENDOR_ID_WCH,
2335 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .setup = pci_wch_ch38x_setup,
2340 /* WCH CH382 2S1P card (16850 clone) */
2342 .vendor = PCIE_VENDOR_ID_WCH,
2343 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
2346 .setup = pci_wch_ch38x_setup,
2348 /* WCH CH384 4S card (16850 clone) */
2350 .vendor = PCIE_VENDOR_ID_WCH,
2351 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .setup = pci_wch_ch38x_setup,
2357 * ASIX devices with FIFO bug
2360 .vendor = PCI_VENDOR_ID_ASIX,
2361 .device = PCI_ANY_ID,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .setup = pci_asix_setup,
2367 * Broadcom TruManage (NetXtreme)
2370 .vendor = PCI_VENDOR_ID_BROADCOM,
2371 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
2374 .setup = pci_brcm_trumanage_setup,
2379 .subvendor = PCI_ANY_ID,
2380 .subdevice = PCI_ANY_ID,
2381 .setup = pci_fintek_setup,
2382 .init = pci_fintek_init,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .setup = pci_fintek_setup,
2390 .init = pci_fintek_init,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_fintek_setup,
2398 .init = pci_fintek_init,
2402 * Default "match everything" terminator entry
2405 .vendor = PCI_ANY_ID,
2406 .device = PCI_ANY_ID,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_default_setup,
2413 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2415 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2418 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2420 struct pci_serial_quirk *quirk;
2422 for (quirk = pci_serial_quirks; ; quirk++)
2423 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2424 quirk_id_matches(quirk->device, dev->device) &&
2425 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2426 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2431 static inline int get_pci_irq(struct pci_dev *dev,
2432 const struct pciserial_board *board)
2434 if (board->flags & FL_NOIRQ)
2441 * This is the configuration table for all of the PCI serial boards
2442 * which we support. It is directly indexed by the pci_board_num_t enum
2443 * value, which is encoded in the pci_device_id PCI probe table's
2444 * driver_data member.
2446 * The makeup of these names are:
2447 * pbn_bn{_bt}_n_baud{_offsetinhex}
2449 * bn = PCI BAR number
2450 * bt = Index using PCI BARs
2451 * n = number of serial ports
2453 * offsetinhex = offset for each sequential port (in hex)
2455 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2457 * Please note: in theory if n = 1, _bt infix should make no difference.
2458 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2460 enum pci_board_num_t {
2554 * Board-specific versions.
2560 pbn_endrun_2_4000000,
2562 pbn_oxsemi_1_4000000,
2563 pbn_oxsemi_2_4000000,
2564 pbn_oxsemi_4_4000000,
2565 pbn_oxsemi_8_4000000,
2577 pbn_ADDIDATA_PCIe_1_3906250,
2578 pbn_ADDIDATA_PCIe_2_3906250,
2579 pbn_ADDIDATA_PCIe_4_3906250,
2580 pbn_ADDIDATA_PCIe_8_3906250,
2581 pbn_ce4100_1_115200,
2583 pbn_NETMOS9900_2s_115200,
2590 pbn_pericom_PI7C9X7951,
2591 pbn_pericom_PI7C9X7952,
2592 pbn_pericom_PI7C9X7954,
2593 pbn_pericom_PI7C9X7958,
2597 * uart_offset - the space between channels
2598 * reg_shift - describes how the UART registers are mapped
2599 * to PCI memory by the card.
2600 * For example IER register on SBS, Inc. PMC-OctPro is located at
2601 * offset 0x10 from the UART base, while UART_IER is defined as 1
2602 * in include/linux/serial_reg.h,
2603 * see first lines of serial_in() and serial_out() in 8250.c
2606 static struct pciserial_board pci_boards[] = {
2610 .base_baud = 115200,
2613 [pbn_b0_1_115200] = {
2616 .base_baud = 115200,
2619 [pbn_b0_2_115200] = {
2622 .base_baud = 115200,
2625 [pbn_b0_4_115200] = {
2628 .base_baud = 115200,
2631 [pbn_b0_5_115200] = {
2634 .base_baud = 115200,
2637 [pbn_b0_8_115200] = {
2640 .base_baud = 115200,
2643 [pbn_b0_1_921600] = {
2646 .base_baud = 921600,
2649 [pbn_b0_2_921600] = {
2652 .base_baud = 921600,
2655 [pbn_b0_4_921600] = {
2658 .base_baud = 921600,
2662 [pbn_b0_2_1130000] = {
2665 .base_baud = 1130000,
2669 [pbn_b0_4_1152000] = {
2672 .base_baud = 1152000,
2676 [pbn_b0_4_1250000] = {
2679 .base_baud = 1250000,
2683 [pbn_b0_2_1843200] = {
2686 .base_baud = 1843200,
2689 [pbn_b0_4_1843200] = {
2692 .base_baud = 1843200,
2696 [pbn_b0_1_4000000] = {
2699 .base_baud = 4000000,
2703 [pbn_b0_bt_1_115200] = {
2704 .flags = FL_BASE0|FL_BASE_BARS,
2706 .base_baud = 115200,
2709 [pbn_b0_bt_2_115200] = {
2710 .flags = FL_BASE0|FL_BASE_BARS,
2712 .base_baud = 115200,
2715 [pbn_b0_bt_4_115200] = {
2716 .flags = FL_BASE0|FL_BASE_BARS,
2718 .base_baud = 115200,
2721 [pbn_b0_bt_8_115200] = {
2722 .flags = FL_BASE0|FL_BASE_BARS,
2724 .base_baud = 115200,
2728 [pbn_b0_bt_1_460800] = {
2729 .flags = FL_BASE0|FL_BASE_BARS,
2731 .base_baud = 460800,
2734 [pbn_b0_bt_2_460800] = {
2735 .flags = FL_BASE0|FL_BASE_BARS,
2737 .base_baud = 460800,
2740 [pbn_b0_bt_4_460800] = {
2741 .flags = FL_BASE0|FL_BASE_BARS,
2743 .base_baud = 460800,
2747 [pbn_b0_bt_1_921600] = {
2748 .flags = FL_BASE0|FL_BASE_BARS,
2750 .base_baud = 921600,
2753 [pbn_b0_bt_2_921600] = {
2754 .flags = FL_BASE0|FL_BASE_BARS,
2756 .base_baud = 921600,
2759 [pbn_b0_bt_4_921600] = {
2760 .flags = FL_BASE0|FL_BASE_BARS,
2762 .base_baud = 921600,
2765 [pbn_b0_bt_8_921600] = {
2766 .flags = FL_BASE0|FL_BASE_BARS,
2768 .base_baud = 921600,
2772 [pbn_b1_1_115200] = {
2775 .base_baud = 115200,
2778 [pbn_b1_2_115200] = {
2781 .base_baud = 115200,
2784 [pbn_b1_4_115200] = {
2787 .base_baud = 115200,
2790 [pbn_b1_8_115200] = {
2793 .base_baud = 115200,
2796 [pbn_b1_16_115200] = {
2799 .base_baud = 115200,
2803 [pbn_b1_1_921600] = {
2806 .base_baud = 921600,
2809 [pbn_b1_2_921600] = {
2812 .base_baud = 921600,
2815 [pbn_b1_4_921600] = {
2818 .base_baud = 921600,
2821 [pbn_b1_8_921600] = {
2824 .base_baud = 921600,
2827 [pbn_b1_2_1250000] = {
2830 .base_baud = 1250000,
2834 [pbn_b1_bt_1_115200] = {
2835 .flags = FL_BASE1|FL_BASE_BARS,
2837 .base_baud = 115200,
2840 [pbn_b1_bt_2_115200] = {
2841 .flags = FL_BASE1|FL_BASE_BARS,
2843 .base_baud = 115200,
2846 [pbn_b1_bt_4_115200] = {
2847 .flags = FL_BASE1|FL_BASE_BARS,
2849 .base_baud = 115200,
2853 [pbn_b1_bt_2_921600] = {
2854 .flags = FL_BASE1|FL_BASE_BARS,
2856 .base_baud = 921600,
2860 [pbn_b1_1_1382400] = {
2863 .base_baud = 1382400,
2866 [pbn_b1_2_1382400] = {
2869 .base_baud = 1382400,
2872 [pbn_b1_4_1382400] = {
2875 .base_baud = 1382400,
2878 [pbn_b1_8_1382400] = {
2881 .base_baud = 1382400,
2885 [pbn_b2_1_115200] = {
2888 .base_baud = 115200,
2891 [pbn_b2_2_115200] = {
2894 .base_baud = 115200,
2897 [pbn_b2_4_115200] = {
2900 .base_baud = 115200,
2903 [pbn_b2_8_115200] = {
2906 .base_baud = 115200,
2910 [pbn_b2_1_460800] = {
2913 .base_baud = 460800,
2916 [pbn_b2_4_460800] = {
2919 .base_baud = 460800,
2922 [pbn_b2_8_460800] = {
2925 .base_baud = 460800,
2928 [pbn_b2_16_460800] = {
2931 .base_baud = 460800,
2935 [pbn_b2_1_921600] = {
2938 .base_baud = 921600,
2941 [pbn_b2_4_921600] = {
2944 .base_baud = 921600,
2947 [pbn_b2_8_921600] = {
2950 .base_baud = 921600,
2954 [pbn_b2_8_1152000] = {
2957 .base_baud = 1152000,
2961 [pbn_b2_bt_1_115200] = {
2962 .flags = FL_BASE2|FL_BASE_BARS,
2964 .base_baud = 115200,
2967 [pbn_b2_bt_2_115200] = {
2968 .flags = FL_BASE2|FL_BASE_BARS,
2970 .base_baud = 115200,
2973 [pbn_b2_bt_4_115200] = {
2974 .flags = FL_BASE2|FL_BASE_BARS,
2976 .base_baud = 115200,
2980 [pbn_b2_bt_2_921600] = {
2981 .flags = FL_BASE2|FL_BASE_BARS,
2983 .base_baud = 921600,
2986 [pbn_b2_bt_4_921600] = {
2987 .flags = FL_BASE2|FL_BASE_BARS,
2989 .base_baud = 921600,
2993 [pbn_b3_2_115200] = {
2996 .base_baud = 115200,
2999 [pbn_b3_4_115200] = {
3002 .base_baud = 115200,
3005 [pbn_b3_8_115200] = {
3008 .base_baud = 115200,
3012 [pbn_b4_bt_2_921600] = {
3015 .base_baud = 921600,
3018 [pbn_b4_bt_4_921600] = {
3021 .base_baud = 921600,
3024 [pbn_b4_bt_8_921600] = {
3027 .base_baud = 921600,
3032 * Entries following this are board-specific.
3041 .base_baud = 921600,
3042 .uart_offset = 0x400,
3046 .flags = FL_BASE2|FL_BASE_BARS,
3048 .base_baud = 921600,
3049 .uart_offset = 0x400,
3053 .flags = FL_BASE2|FL_BASE_BARS,
3055 .base_baud = 921600,
3056 .uart_offset = 0x400,
3060 /* I think this entry is broken - the first_offset looks wrong --rmk */
3061 [pbn_plx_romulus] = {
3064 .base_baud = 921600,
3065 .uart_offset = 8 << 2,
3067 .first_offset = 0x03,
3071 * EndRun Technologies
3072 * Uses the size of PCI Base region 0 to
3073 * signal now many ports are available
3074 * 2 port 952 Uart support
3076 [pbn_endrun_2_4000000] = {
3079 .base_baud = 4000000,
3080 .uart_offset = 0x200,
3081 .first_offset = 0x1000,
3085 * This board uses the size of PCI Base region 0 to
3086 * signal now many ports are available
3089 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3091 .base_baud = 115200,
3094 [pbn_oxsemi_1_4000000] = {
3097 .base_baud = 4000000,
3098 .uart_offset = 0x200,
3099 .first_offset = 0x1000,
3101 [pbn_oxsemi_2_4000000] = {
3104 .base_baud = 4000000,
3105 .uart_offset = 0x200,
3106 .first_offset = 0x1000,
3108 [pbn_oxsemi_4_4000000] = {
3111 .base_baud = 4000000,
3112 .uart_offset = 0x200,
3113 .first_offset = 0x1000,
3115 [pbn_oxsemi_8_4000000] = {
3118 .base_baud = 4000000,
3119 .uart_offset = 0x200,
3120 .first_offset = 0x1000,
3125 * EKF addition for i960 Boards form EKF with serial port.
3128 [pbn_intel_i960] = {
3131 .base_baud = 921600,
3132 .uart_offset = 8 << 2,
3134 .first_offset = 0x10000,
3137 .flags = FL_BASE0|FL_NOIRQ,
3139 .base_baud = 458333,
3142 .first_offset = 0x20178,
3146 * Computone - uses IOMEM.
3148 [pbn_computone_4] = {
3151 .base_baud = 921600,
3152 .uart_offset = 0x40,
3154 .first_offset = 0x200,
3156 [pbn_computone_6] = {
3159 .base_baud = 921600,
3160 .uart_offset = 0x40,
3162 .first_offset = 0x200,
3164 [pbn_computone_8] = {
3167 .base_baud = 921600,
3168 .uart_offset = 0x40,
3170 .first_offset = 0x200,
3175 .base_baud = 460800,
3180 * PA Semi PWRficient PA6T-1682M on-chip UART
3182 [pbn_pasemi_1682M] = {
3185 .base_baud = 8333333,
3188 * National Instruments 843x
3193 .base_baud = 3686400,
3194 .uart_offset = 0x10,
3195 .first_offset = 0x800,
3200 .base_baud = 3686400,
3201 .uart_offset = 0x10,
3202 .first_offset = 0x800,
3207 .base_baud = 3686400,
3208 .uart_offset = 0x10,
3209 .first_offset = 0x800,
3214 .base_baud = 3686400,
3215 .uart_offset = 0x10,
3216 .first_offset = 0x800,
3219 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3221 [pbn_ADDIDATA_PCIe_1_3906250] = {
3224 .base_baud = 3906250,
3225 .uart_offset = 0x200,
3226 .first_offset = 0x1000,
3228 [pbn_ADDIDATA_PCIe_2_3906250] = {
3231 .base_baud = 3906250,
3232 .uart_offset = 0x200,
3233 .first_offset = 0x1000,
3235 [pbn_ADDIDATA_PCIe_4_3906250] = {
3238 .base_baud = 3906250,
3239 .uart_offset = 0x200,
3240 .first_offset = 0x1000,
3242 [pbn_ADDIDATA_PCIe_8_3906250] = {
3245 .base_baud = 3906250,
3246 .uart_offset = 0x200,
3247 .first_offset = 0x1000,
3249 [pbn_ce4100_1_115200] = {
3250 .flags = FL_BASE_BARS,
3252 .base_baud = 921600,
3258 .base_baud = 115200,
3259 .uart_offset = 0x200,
3261 [pbn_NETMOS9900_2s_115200] = {
3264 .base_baud = 115200,
3266 [pbn_brcm_trumanage] = {
3270 .base_baud = 115200,
3275 .base_baud = 115200,
3276 .first_offset = 0x40,
3281 .base_baud = 115200,
3282 .first_offset = 0x40,
3287 .base_baud = 115200,
3288 .first_offset = 0x40,
3293 .base_baud = 115200,
3295 .first_offset = 0xC0,
3300 .base_baud = 115200,
3302 .first_offset = 0xC0,
3305 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3307 [pbn_pericom_PI7C9X7951] = {
3310 .base_baud = 921600,
3313 [pbn_pericom_PI7C9X7952] = {
3316 .base_baud = 921600,
3319 [pbn_pericom_PI7C9X7954] = {
3322 .base_baud = 921600,
3325 [pbn_pericom_PI7C9X7958] = {
3328 .base_baud = 921600,
3333 static const struct pci_device_id blacklist[] = {
3335 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3336 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3337 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3339 /* multi-io cards handled by parport_serial */
3340 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3341 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3342 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3344 /* Moxa Smartio MUE boards handled by 8250_moxa */
3345 { PCI_VDEVICE(MOXA, 0x1024), },
3346 { PCI_VDEVICE(MOXA, 0x1025), },
3347 { PCI_VDEVICE(MOXA, 0x1045), },
3348 { PCI_VDEVICE(MOXA, 0x1144), },
3349 { PCI_VDEVICE(MOXA, 0x1160), },
3350 { PCI_VDEVICE(MOXA, 0x1161), },
3351 { PCI_VDEVICE(MOXA, 0x1182), },
3352 { PCI_VDEVICE(MOXA, 0x1183), },
3353 { PCI_VDEVICE(MOXA, 0x1322), },
3354 { PCI_VDEVICE(MOXA, 0x1342), },
3355 { PCI_VDEVICE(MOXA, 0x1381), },
3356 { PCI_VDEVICE(MOXA, 0x1683), },
3358 /* Intel platforms with MID UART */
3359 { PCI_VDEVICE(INTEL, 0x081b), },
3360 { PCI_VDEVICE(INTEL, 0x081c), },
3361 { PCI_VDEVICE(INTEL, 0x081d), },
3362 { PCI_VDEVICE(INTEL, 0x1191), },
3363 { PCI_VDEVICE(INTEL, 0x18d8), },
3364 { PCI_VDEVICE(INTEL, 0x19d8), },
3366 /* Intel platforms with DesignWare UART */
3367 { PCI_VDEVICE(INTEL, 0x0936), },
3368 { PCI_VDEVICE(INTEL, 0x0f0a), },
3369 { PCI_VDEVICE(INTEL, 0x0f0c), },
3370 { PCI_VDEVICE(INTEL, 0x228a), },
3371 { PCI_VDEVICE(INTEL, 0x228c), },
3372 { PCI_VDEVICE(INTEL, 0x9ce3), },
3373 { PCI_VDEVICE(INTEL, 0x9ce4), },
3376 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3377 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3380 static int serial_pci_is_class_communication(struct pci_dev *dev)
3383 * If it is not a communications device or the programming
3384 * interface is greater than 6, give up.
3386 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3387 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3388 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3389 (dev->class & 0xff) > 6)
3395 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3397 const struct pci_device_id *bldev;
3400 * Do not access blacklisted devices that are known not to
3401 * feature serial ports or are handled by other modules.
3403 for (bldev = blacklist;
3404 bldev < blacklist + ARRAY_SIZE(blacklist);
3406 if (dev->vendor == bldev->vendor &&
3407 dev->device == bldev->device)
3415 * Given a complete unknown PCI device, try to use some heuristics to
3416 * guess what the configuration might be, based on the pitiful PCI
3417 * serial specs. Returns 0 on success, -ENODEV on failure.
3420 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3422 int num_iomem, num_port, first_port = -1, i;
3425 * Should we try to make guesses for multiport serial devices later?
3427 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3430 num_iomem = num_port = 0;
3431 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3432 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3434 if (first_port == -1)
3437 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3442 * If there is 1 or 0 iomem regions, and exactly one port,
3443 * use it. We guess the number of ports based on the IO
3446 if (num_iomem <= 1 && num_port == 1) {
3447 board->flags = first_port;
3448 board->num_ports = pci_resource_len(dev, first_port) / 8;
3453 * Now guess if we've got a board which indexes by BARs.
3454 * Each IO BAR should be 8 bytes, and they should follow
3459 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3460 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3461 pci_resource_len(dev, i) == 8 &&
3462 (first_port == -1 || (first_port + num_port) == i)) {
3464 if (first_port == -1)
3470 board->flags = first_port | FL_BASE_BARS;
3471 board->num_ports = num_port;
3479 serial_pci_matches(const struct pciserial_board *board,
3480 const struct pciserial_board *guessed)
3483 board->num_ports == guessed->num_ports &&
3484 board->base_baud == guessed->base_baud &&
3485 board->uart_offset == guessed->uart_offset &&
3486 board->reg_shift == guessed->reg_shift &&
3487 board->first_offset == guessed->first_offset;
3490 struct serial_private *
3491 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3493 struct uart_8250_port uart;
3494 struct serial_private *priv;
3495 struct pci_serial_quirk *quirk;
3496 int rc, nr_ports, i;
3498 nr_ports = board->num_ports;
3501 * Find an init and setup quirks.
3503 quirk = find_quirk(dev);
3506 * Run the new-style initialization function.
3507 * The initialization function returns:
3509 * 0 - use board->num_ports
3510 * >0 - number of ports
3513 rc = quirk->init(dev);
3522 priv = kzalloc(sizeof(struct serial_private) +
3523 sizeof(unsigned int) * nr_ports,
3526 priv = ERR_PTR(-ENOMEM);
3531 priv->quirk = quirk;
3533 memset(&uart, 0, sizeof(uart));
3534 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3535 uart.port.uartclk = board->base_baud * 16;
3536 uart.port.irq = get_pci_irq(dev, board);
3537 uart.port.dev = &dev->dev;
3539 for (i = 0; i < nr_ports; i++) {
3540 if (quirk->setup(priv, board, &uart, i))
3543 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3544 uart.port.iobase, uart.port.irq, uart.port.iotype);
3546 priv->line[i] = serial8250_register_8250_port(&uart);
3547 if (priv->line[i] < 0) {
3549 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3550 uart.port.iobase, uart.port.irq,
3551 uart.port.iotype, priv->line[i]);
3556 priv->board = board;
3565 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3567 static void pciserial_detach_ports(struct serial_private *priv)
3569 struct pci_serial_quirk *quirk;
3572 for (i = 0; i < priv->nr; i++)
3573 serial8250_unregister_port(priv->line[i]);
3576 * Find the exit quirks.
3578 quirk = find_quirk(priv->dev);
3580 quirk->exit(priv->dev);
3583 void pciserial_remove_ports(struct serial_private *priv)
3585 pciserial_detach_ports(priv);
3588 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3590 void pciserial_suspend_ports(struct serial_private *priv)
3594 for (i = 0; i < priv->nr; i++)
3595 if (priv->line[i] >= 0)
3596 serial8250_suspend_port(priv->line[i]);
3599 * Ensure that every init quirk is properly torn down
3601 if (priv->quirk->exit)
3602 priv->quirk->exit(priv->dev);
3604 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3606 void pciserial_resume_ports(struct serial_private *priv)
3611 * Ensure that the board is correctly configured.
3613 if (priv->quirk->init)
3614 priv->quirk->init(priv->dev);
3616 for (i = 0; i < priv->nr; i++)
3617 if (priv->line[i] >= 0)
3618 serial8250_resume_port(priv->line[i]);
3620 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3623 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3624 * to the arrangement of serial ports on a PCI card.
3627 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3629 struct pci_serial_quirk *quirk;
3630 struct serial_private *priv;
3631 const struct pciserial_board *board;
3632 struct pciserial_board tmp;
3635 quirk = find_quirk(dev);
3637 rc = quirk->probe(dev);
3642 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3643 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3648 board = &pci_boards[ent->driver_data];
3650 rc = serial_pci_is_class_communication(dev);
3654 rc = serial_pci_is_blacklisted(dev);
3658 rc = pcim_enable_device(dev);
3659 pci_save_state(dev);
3663 if (ent->driver_data == pbn_default) {
3665 * Use a copy of the pci_board entry for this;
3666 * avoid changing entries in the table.
3668 memcpy(&tmp, board, sizeof(struct pciserial_board));
3672 * We matched one of our class entries. Try to
3673 * determine the parameters of this board.
3675 rc = serial_pci_guess_board(dev, &tmp);
3680 * We matched an explicit entry. If we are able to
3681 * detect this boards settings with our heuristic,
3682 * then we no longer need this entry.
3684 memcpy(&tmp, &pci_boards[pbn_default],
3685 sizeof(struct pciserial_board));
3686 rc = serial_pci_guess_board(dev, &tmp);
3687 if (rc == 0 && serial_pci_matches(board, &tmp))
3688 moan_device("Redundant entry in serial pci_table.",
3692 priv = pciserial_init_ports(dev, board);
3694 return PTR_ERR(priv);
3696 pci_set_drvdata(dev, priv);
3700 static void pciserial_remove_one(struct pci_dev *dev)
3702 struct serial_private *priv = pci_get_drvdata(dev);
3704 pciserial_remove_ports(priv);
3707 #ifdef CONFIG_PM_SLEEP
3708 static int pciserial_suspend_one(struct device *dev)
3710 struct pci_dev *pdev = to_pci_dev(dev);
3711 struct serial_private *priv = pci_get_drvdata(pdev);
3714 pciserial_suspend_ports(priv);
3719 static int pciserial_resume_one(struct device *dev)
3721 struct pci_dev *pdev = to_pci_dev(dev);
3722 struct serial_private *priv = pci_get_drvdata(pdev);
3727 * The device may have been disabled. Re-enable it.
3729 err = pci_enable_device(pdev);
3730 /* FIXME: We cannot simply error out here */
3732 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3733 pciserial_resume_ports(priv);
3739 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3740 pciserial_resume_one);
3742 static const struct pci_device_id serial_pci_tbl[] = {
3743 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3744 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3745 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3747 /* Advantech also use 0x3618 and 0xf618 */
3748 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3749 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3751 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3752 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3754 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3755 PCI_SUBVENDOR_ID_CONNECT_TECH,
3756 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3758 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3759 PCI_SUBVENDOR_ID_CONNECT_TECH,
3760 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3762 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3763 PCI_SUBVENDOR_ID_CONNECT_TECH,
3764 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3766 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3767 PCI_SUBVENDOR_ID_CONNECT_TECH,
3768 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3770 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3771 PCI_SUBVENDOR_ID_CONNECT_TECH,
3772 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3774 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3775 PCI_SUBVENDOR_ID_CONNECT_TECH,
3776 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3778 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3779 PCI_SUBVENDOR_ID_CONNECT_TECH,
3780 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3782 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3783 PCI_SUBVENDOR_ID_CONNECT_TECH,
3784 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3786 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3787 PCI_SUBVENDOR_ID_CONNECT_TECH,
3788 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3790 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3791 PCI_SUBVENDOR_ID_CONNECT_TECH,
3792 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3794 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3795 PCI_SUBVENDOR_ID_CONNECT_TECH,
3796 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3798 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3799 PCI_SUBVENDOR_ID_CONNECT_TECH,
3800 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3802 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3803 PCI_SUBVENDOR_ID_CONNECT_TECH,
3804 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3806 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3807 PCI_SUBVENDOR_ID_CONNECT_TECH,
3808 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3810 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3811 PCI_SUBVENDOR_ID_CONNECT_TECH,
3812 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3814 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3815 PCI_SUBVENDOR_ID_CONNECT_TECH,
3816 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3818 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3819 PCI_SUBVENDOR_ID_CONNECT_TECH,
3820 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3822 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3823 PCI_VENDOR_ID_AFAVLAB,
3824 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3826 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b2_bt_1_115200 },
3829 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 pbn_b2_bt_2_115200 },
3832 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 pbn_b2_bt_4_115200 },
3835 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 pbn_b2_bt_2_115200 },
3838 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_b2_bt_4_115200 },
3841 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3844 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3847 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3853 pbn_b2_bt_2_115200 },
3854 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 pbn_b2_bt_2_921600 },
3858 * VScom SPCOM800, from sl@s.pl
3860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3866 /* Unknown card - subdevice 0x1584 */
3867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3869 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3871 /* Unknown card - subdevice 0x1588 */
3872 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3874 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3876 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3877 PCI_SUBVENDOR_ID_KEYSPAN,
3878 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3880 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3883 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3886 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3887 PCI_VENDOR_ID_ESDGMBH,
3888 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3890 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3891 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3892 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3894 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3895 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3896 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3898 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3899 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3900 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3902 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3903 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3904 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3906 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3907 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3908 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3910 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3911 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3912 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3914 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3915 PCI_SUBVENDOR_ID_EXSYS,
3916 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3919 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3922 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3923 0x10b5, 0x106a, 0, 0,
3926 * EndRun Technologies. PCI express device range.
3927 * EndRun PTP/1588 has 2 Native UARTs.
3929 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_endrun_2_4000000 },
3933 * Quatech cards. These actually have configurable clocks but for
3934 * now we just use the default.
3936 * 100 series are RS232, 200 series RS422,
3938 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3997 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4000 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4001 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4004 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006 pbn_b0_bt_2_921600 },
4009 * The below card is a little controversial since it is the
4010 * subject of a PCI vendor/device ID clash. (See
4011 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4012 * For now just used the hex ID 0x950a.
4014 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4015 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4016 0, 0, pbn_b0_2_115200 },
4017 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4018 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4019 0, 0, pbn_b0_2_115200 },
4020 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4024 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4026 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4029 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_b0_bt_2_921600 },
4032 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037 * Oxford Semiconductor Inc. Tornado PCI express device range.
4039 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4042 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4045 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047 pbn_oxsemi_1_4000000 },
4048 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050 pbn_oxsemi_1_4000000 },
4051 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4054 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4057 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059 pbn_oxsemi_1_4000000 },
4060 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4062 pbn_oxsemi_1_4000000 },
4063 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4066 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4069 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4072 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4075 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 pbn_oxsemi_2_4000000 },
4078 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 pbn_oxsemi_2_4000000 },
4081 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 pbn_oxsemi_4_4000000 },
4084 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 pbn_oxsemi_4_4000000 },
4087 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089 pbn_oxsemi_8_4000000 },
4090 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092 pbn_oxsemi_8_4000000 },
4093 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095 pbn_oxsemi_1_4000000 },
4096 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4098 pbn_oxsemi_1_4000000 },
4099 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101 pbn_oxsemi_1_4000000 },
4102 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104 pbn_oxsemi_1_4000000 },
4105 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 pbn_oxsemi_1_4000000 },
4108 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110 pbn_oxsemi_1_4000000 },
4111 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113 pbn_oxsemi_1_4000000 },
4114 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 pbn_oxsemi_1_4000000 },
4117 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119 pbn_oxsemi_1_4000000 },
4120 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_oxsemi_1_4000000 },
4123 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 pbn_oxsemi_1_4000000 },
4126 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_oxsemi_1_4000000 },
4129 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_oxsemi_1_4000000 },
4132 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_oxsemi_1_4000000 },
4135 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_oxsemi_1_4000000 },
4138 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_oxsemi_1_4000000 },
4141 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_oxsemi_1_4000000 },
4144 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_oxsemi_1_4000000 },
4147 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_oxsemi_1_4000000 },
4150 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_oxsemi_1_4000000 },
4153 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_oxsemi_1_4000000 },
4156 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_oxsemi_1_4000000 },
4159 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_oxsemi_1_4000000 },
4162 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_oxsemi_1_4000000 },
4165 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_oxsemi_1_4000000 },
4168 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_oxsemi_1_4000000 },
4172 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4174 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4175 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4176 pbn_oxsemi_1_4000000 },
4177 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4178 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4179 pbn_oxsemi_2_4000000 },
4180 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4181 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4182 pbn_oxsemi_4_4000000 },
4183 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4184 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4185 pbn_oxsemi_8_4000000 },
4188 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4190 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4191 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_2_4000000 },
4195 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4196 * from skokodyn@yahoo.com
4198 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4199 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4201 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4202 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4204 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4205 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4207 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4208 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4212 * Digitan DS560-558, from jimd@esoft.com
4214 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 * Titan Electronic cards
4220 * The 400L and 800L have a custom setup quirk.
4222 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_b1_bt_2_921600 },
4240 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 pbn_b0_bt_4_921600 },
4243 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_b0_bt_8_921600 },
4246 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_b4_bt_2_921600 },
4249 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_b4_bt_4_921600 },
4252 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_b4_bt_8_921600 },
4255 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_oxsemi_1_4000000 },
4267 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_oxsemi_2_4000000 },
4270 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_oxsemi_4_4000000 },
4273 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_oxsemi_8_4000000 },
4276 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_oxsemi_2_4000000 },
4279 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_oxsemi_2_4000000 },
4282 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b0_bt_2_921600 },
4285 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_b2_bt_2_921600 },
4310 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_bt_2_921600 },
4313 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_b2_bt_2_921600 },
4316 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_b2_bt_4_921600 },
4319 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_b2_bt_4_921600 },
4322 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_b2_bt_4_921600 },
4325 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b0_bt_2_921600 },
4337 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b0_bt_2_921600 },
4340 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_bt_2_921600 },
4343 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b0_bt_4_921600 },
4346 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b0_bt_4_921600 },
4349 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b0_bt_4_921600 },
4352 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b0_bt_8_921600 },
4355 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_bt_8_921600 },
4358 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_bt_8_921600 },
4363 * Computone devices submitted by Doug McNash dmcnash@computone.com
4365 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4366 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4367 0, 0, pbn_computone_4 },
4368 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4369 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4370 0, 0, pbn_computone_8 },
4371 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4372 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4373 0, 0, pbn_computone_6 },
4375 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4379 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4380 pbn_b0_bt_1_921600 },
4385 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4386 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4387 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4388 pbn_b0_bt_1_921600 },
4390 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4391 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4392 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4393 pbn_b0_bt_1_921600 },
4396 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4398 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b0_bt_8_115200 },
4401 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b0_bt_8_115200 },
4405 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b0_bt_2_115200 },
4408 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b0_bt_2_115200 },
4411 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b0_bt_2_115200 },
4414 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b0_bt_2_115200 },
4417 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b0_bt_2_115200 },
4420 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b0_bt_4_460800 },
4423 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_b0_bt_4_460800 },
4426 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_b0_bt_2_460800 },
4429 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_b0_bt_2_460800 },
4432 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_b0_bt_2_460800 },
4435 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_b0_bt_1_115200 },
4438 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b0_bt_1_460800 },
4443 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4444 * Cards are identified by their subsystem vendor IDs, which
4445 * (in hex) match the model number.
4447 * Note that JC140x are RS422/485 cards which require ox950
4448 * ACR = 0x10, and as such are not currently fully supported.
4450 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4451 0x1204, 0x0004, 0, 0,
4453 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4454 0x1208, 0x0004, 0, 0,
4456 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4457 0x1402, 0x0002, 0, 0,
4458 pbn_b0_2_921600 }, */
4459 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4460 0x1404, 0x0004, 0, 0,
4461 pbn_b0_4_921600 }, */
4462 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4463 0x1208, 0x0004, 0, 0,
4466 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4467 0x1204, 0x0004, 0, 0,
4469 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4470 0x1208, 0x0004, 0, 0,
4472 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4473 0x1208, 0x0004, 0, 0,
4476 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4478 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4485 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 * RAStel 2 port modem, gerg@moreton.com.au
4492 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_2_115200 },
4497 * EKF addition for i960 Boards form EKF with serial port
4499 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4500 0xE4BF, PCI_ANY_ID, 0, 0,
4504 * Xircom Cardbus/Ethernet combos
4506 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4512 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 * Untested PCI modems, sent in from various folks...
4521 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4523 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4524 0x1048, 0x1500, 0, 0,
4527 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4534 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4535 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4537 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4556 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4557 PCI_ANY_ID, PCI_ANY_ID,
4559 0, pbn_pericom_PI7C9X7951 },
4560 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4561 PCI_ANY_ID, PCI_ANY_ID,
4563 0, pbn_pericom_PI7C9X7952 },
4564 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4565 PCI_ANY_ID, PCI_ANY_ID,
4567 0, pbn_pericom_PI7C9X7954 },
4568 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4569 PCI_ANY_ID, PCI_ANY_ID,
4571 0, pbn_pericom_PI7C9X7958 },
4573 * ACCES I/O Products quad
4575 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_pericom_PI7C9X7954 },
4578 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_pericom_PI7C9X7954 },
4581 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_pericom_PI7C9X7954 },
4584 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_pericom_PI7C9X7954 },
4587 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_pericom_PI7C9X7954 },
4590 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_pericom_PI7C9X7954 },
4593 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_pericom_PI7C9X7954 },
4596 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_pericom_PI7C9X7954 },
4599 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_pericom_PI7C9X7954 },
4602 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_pericom_PI7C9X7954 },
4605 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_pericom_PI7C9X7954 },
4608 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_pericom_PI7C9X7954 },
4611 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_pericom_PI7C9X7954 },
4614 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_pericom_PI7C9X7954 },
4617 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_pericom_PI7C9X7954 },
4620 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_pericom_PI7C9X7954 },
4623 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_pericom_PI7C9X7954 },
4626 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_pericom_PI7C9X7954 },
4629 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_pericom_PI7C9X7954 },
4632 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_pericom_PI7C9X7954 },
4635 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_pericom_PI7C9X7954 },
4638 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_pericom_PI7C9X7954 },
4641 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_pericom_PI7C9X7954 },
4644 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_pericom_PI7C9X7954 },
4647 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_pericom_PI7C9X7958 },
4650 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_pericom_PI7C9X7958 },
4653 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_pericom_PI7C9X7958 },
4656 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_pericom_PI7C9X7958 },
4659 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_pericom_PI7C9X7958 },
4662 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_pericom_PI7C9X7958 },
4665 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_pericom_PI7C9X7958 },
4668 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_pericom_PI7C9X7958 },
4671 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_pericom_PI7C9X7958 },
4675 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4677 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4684 PCI_ANY_ID, PCI_ANY_ID,
4686 pbn_b1_bt_1_115200 },
4691 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4697 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4703 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4704 PCI_ANY_ID, PCI_ANY_ID,
4705 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4707 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4708 PCI_ANY_ID, PCI_ANY_ID,
4709 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4712 * Perle PCI-RAS cards
4714 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4715 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4716 0, 0, pbn_b2_4_921600 },
4717 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4718 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4719 0, 0, pbn_b2_8_921600 },
4722 * Mainpine series cards: Fairly standard layout but fools
4723 * parts of the autodetect in some cases and uses otherwise
4724 * unmatched communications subclasses in the PCI Express case
4727 { /* RockForceDUO */
4728 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4729 PCI_VENDOR_ID_MAINPINE, 0x0200,
4730 0, 0, pbn_b0_2_115200 },
4731 { /* RockForceQUATRO */
4732 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4733 PCI_VENDOR_ID_MAINPINE, 0x0300,
4734 0, 0, pbn_b0_4_115200 },
4735 { /* RockForceDUO+ */
4736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4737 PCI_VENDOR_ID_MAINPINE, 0x0400,
4738 0, 0, pbn_b0_2_115200 },
4739 { /* RockForceQUATRO+ */
4740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4741 PCI_VENDOR_ID_MAINPINE, 0x0500,
4742 0, 0, pbn_b0_4_115200 },
4744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4745 PCI_VENDOR_ID_MAINPINE, 0x0600,
4746 0, 0, pbn_b0_2_115200 },
4748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4749 PCI_VENDOR_ID_MAINPINE, 0x0700,
4750 0, 0, pbn_b0_4_115200 },
4751 { /* RockForceOCTO+ */
4752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4753 PCI_VENDOR_ID_MAINPINE, 0x0800,
4754 0, 0, pbn_b0_8_115200 },
4755 { /* RockForceDUO+ */
4756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4757 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4758 0, 0, pbn_b0_2_115200 },
4759 { /* RockForceQUARTRO+ */
4760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4761 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4762 0, 0, pbn_b0_4_115200 },
4763 { /* RockForceOCTO+ */
4764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4765 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4766 0, 0, pbn_b0_8_115200 },
4768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4769 PCI_VENDOR_ID_MAINPINE, 0x2000,
4770 0, 0, pbn_b0_1_115200 },
4772 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4773 PCI_VENDOR_ID_MAINPINE, 0x2100,
4774 0, 0, pbn_b0_1_115200 },
4776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4777 PCI_VENDOR_ID_MAINPINE, 0x2200,
4778 0, 0, pbn_b0_2_115200 },
4780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4781 PCI_VENDOR_ID_MAINPINE, 0x2300,
4782 0, 0, pbn_b0_2_115200 },
4784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4785 PCI_VENDOR_ID_MAINPINE, 0x2400,
4786 0, 0, pbn_b0_4_115200 },
4788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4789 PCI_VENDOR_ID_MAINPINE, 0x2500,
4790 0, 0, pbn_b0_4_115200 },
4792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4793 PCI_VENDOR_ID_MAINPINE, 0x2600,
4794 0, 0, pbn_b0_8_115200 },
4796 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4797 PCI_VENDOR_ID_MAINPINE, 0x2700,
4798 0, 0, pbn_b0_8_115200 },
4799 { /* IQ Express D1 */
4800 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4801 PCI_VENDOR_ID_MAINPINE, 0x3000,
4802 0, 0, pbn_b0_1_115200 },
4803 { /* IQ Express F1 */
4804 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4805 PCI_VENDOR_ID_MAINPINE, 0x3100,
4806 0, 0, pbn_b0_1_115200 },
4807 { /* IQ Express D2 */
4808 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4809 PCI_VENDOR_ID_MAINPINE, 0x3200,
4810 0, 0, pbn_b0_2_115200 },
4811 { /* IQ Express F2 */
4812 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4813 PCI_VENDOR_ID_MAINPINE, 0x3300,
4814 0, 0, pbn_b0_2_115200 },
4815 { /* IQ Express D4 */
4816 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4817 PCI_VENDOR_ID_MAINPINE, 0x3400,
4818 0, 0, pbn_b0_4_115200 },
4819 { /* IQ Express F4 */
4820 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4821 PCI_VENDOR_ID_MAINPINE, 0x3500,
4822 0, 0, pbn_b0_4_115200 },
4823 { /* IQ Express D8 */
4824 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4825 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4826 0, 0, pbn_b0_8_115200 },
4827 { /* IQ Express F8 */
4828 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4829 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4830 0, 0, pbn_b0_8_115200 },
4834 * PA Semi PA6T-1682M on-chip UART
4836 { PCI_VENDOR_ID_PASEMI, 0xa004,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 * National Instruments
4843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b1_bt_4_115200 },
4852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b1_bt_2_115200 },
4855 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b1_bt_4_115200 },
4858 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b1_bt_2_115200 },
4861 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b1_bt_4_115200 },
4870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b1_bt_2_115200 },
4873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b1_bt_4_115200 },
4876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_b1_bt_2_115200 },
4879 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4919 { PCI_VENDOR_ID_ADDIDATA,
4920 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4927 { PCI_VENDOR_ID_ADDIDATA,
4928 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4935 { PCI_VENDOR_ID_ADDIDATA,
4936 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4943 { PCI_VENDOR_ID_AMCC,
4944 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4951 { PCI_VENDOR_ID_ADDIDATA,
4952 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4959 { PCI_VENDOR_ID_ADDIDATA,
4960 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4967 { PCI_VENDOR_ID_ADDIDATA,
4968 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4975 { PCI_VENDOR_ID_ADDIDATA,
4976 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4983 { PCI_VENDOR_ID_ADDIDATA,
4984 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4991 { PCI_VENDOR_ID_ADDIDATA,
4992 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4999 { PCI_VENDOR_ID_ADDIDATA,
5000 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5007 { PCI_VENDOR_ID_ADDIDATA,
5008 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5013 pbn_ADDIDATA_PCIe_4_3906250 },
5015 { PCI_VENDOR_ID_ADDIDATA,
5016 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5021 pbn_ADDIDATA_PCIe_2_3906250 },
5023 { PCI_VENDOR_ID_ADDIDATA,
5024 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5029 pbn_ADDIDATA_PCIe_1_3906250 },
5031 { PCI_VENDOR_ID_ADDIDATA,
5032 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5037 pbn_ADDIDATA_PCIe_8_3906250 },
5039 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5040 PCI_VENDOR_ID_IBM, 0x0299,
5041 0, 0, pbn_b0_bt_2_115200 },
5044 * other NetMos 9835 devices are most likely handled by the
5045 * parport_serial driver, check drivers/parport/parport_serial.c
5046 * before adding them here.
5049 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5051 0, 0, pbn_b0_1_115200 },
5053 /* the 9901 is a rebranded 9912 */
5054 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5056 0, 0, pbn_b0_1_115200 },
5058 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5060 0, 0, pbn_b0_1_115200 },
5062 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5064 0, 0, pbn_b0_1_115200 },
5066 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5068 0, 0, pbn_b0_1_115200 },
5070 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5072 0, 0, pbn_NETMOS9900_2s_115200 },
5075 * Best Connectivity and Rosewill PCI Multi I/O cards
5078 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5080 0, 0, pbn_b0_1_115200 },
5082 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5084 0, 0, pbn_b0_bt_2_115200 },
5086 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5088 0, 0, pbn_b0_bt_4_115200 },
5090 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_ce4100_1_115200 },
5097 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102 * Broadcom TruManage
5104 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_brcm_trumanage },
5109 * AgeStar as-prs2-009
5111 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5112 PCI_ANY_ID, PCI_ANY_ID,
5113 0, 0, pbn_b0_bt_2_115200 },
5116 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5117 * so not listed here.
5119 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5120 PCI_ANY_ID, PCI_ANY_ID,
5121 0, 0, pbn_b0_bt_4_115200 },
5123 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5124 PCI_ANY_ID, PCI_ANY_ID,
5125 0, 0, pbn_b0_bt_2_115200 },
5127 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5128 PCI_ANY_ID, PCI_ANY_ID,
5129 0, 0, pbn_b0_bt_4_115200 },
5131 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5132 PCI_ANY_ID, PCI_ANY_ID,
5133 0, 0, pbn_wch382_2 },
5135 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5136 PCI_ANY_ID, PCI_ANY_ID,
5137 0, 0, pbn_wch384_4 },
5139 /* Fintek PCI serial cards */
5140 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5141 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5142 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5144 /* MKS Tenta SCOM-080x serial cards */
5145 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5146 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5148 /* Amazon PCI serial device */
5149 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5152 * These entries match devices with class COMMUNICATION_SERIAL,
5153 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5155 { PCI_ANY_ID, PCI_ANY_ID,
5156 PCI_ANY_ID, PCI_ANY_ID,
5157 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5158 0xffff00, pbn_default },
5159 { PCI_ANY_ID, PCI_ANY_ID,
5160 PCI_ANY_ID, PCI_ANY_ID,
5161 PCI_CLASS_COMMUNICATION_MODEM << 8,
5162 0xffff00, pbn_default },
5163 { PCI_ANY_ID, PCI_ANY_ID,
5164 PCI_ANY_ID, PCI_ANY_ID,
5165 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5166 0xffff00, pbn_default },
5170 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5171 pci_channel_state_t state)
5173 struct serial_private *priv = pci_get_drvdata(dev);
5175 if (state == pci_channel_io_perm_failure)
5176 return PCI_ERS_RESULT_DISCONNECT;
5179 pciserial_detach_ports(priv);
5181 pci_disable_device(dev);
5183 return PCI_ERS_RESULT_NEED_RESET;
5186 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5190 rc = pci_enable_device(dev);
5193 return PCI_ERS_RESULT_DISCONNECT;
5195 pci_restore_state(dev);
5196 pci_save_state(dev);
5198 return PCI_ERS_RESULT_RECOVERED;
5201 static void serial8250_io_resume(struct pci_dev *dev)
5203 struct serial_private *priv = pci_get_drvdata(dev);
5204 struct serial_private *new;
5209 new = pciserial_init_ports(dev, priv->board);
5211 pci_set_drvdata(dev, new);
5216 static const struct pci_error_handlers serial8250_err_handler = {
5217 .error_detected = serial8250_io_error_detected,
5218 .slot_reset = serial8250_io_slot_reset,
5219 .resume = serial8250_io_resume,
5222 static struct pci_driver serial_pci_driver = {
5224 .probe = pciserial_init_one,
5225 .remove = pciserial_remove_one,
5227 .pm = &pciserial_pm_ops,
5229 .id_table = serial_pci_tbl,
5230 .err_handler = &serial8250_err_handler,
5233 module_pci_driver(serial_pci_driver);
5235 MODULE_LICENSE("GPL");
5236 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5237 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);