drivers/tty/serial/imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Motorola/Freescale IMX serial ports
   4  *
   5  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6  *
   7  * Author: Sascha Hauer <sascha@saschahauer.de>
   8  * Copyright (C) 2004 Pengutronix
   9  */
  10
  11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/module.h>
  16 #include <linux/ioport.h>
  17 #include <linux/init.h>
  18 #include <linux/console.h>
  19 #include <linux/sysrq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/serial.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/rational.h>
  28 #include <linux/slab.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/io.h>
  32 #include <linux/dma-mapping.h>
  33
  34 #include <asm/irq.h>
  35 #include <linux/platform_data/serial-imx.h>
  36 #include <linux/platform_data/dma-imx.h>
  37
  38 #include "serial_mctrl_gpio.h"
  39
  40 /* Register definitions */
  41 #define URXD0 0x0  /* Receiver Register */
  42 #define URTX0 0x40 /* Transmitter Register */
  43 #define UCR1  0x80 /* Control Register 1 */
  44 #define UCR2  0x84 /* Control Register 2 */
  45 #define UCR3  0x88 /* Control Register 3 */
  46 #define UCR4  0x8c /* Control Register 4 */
  47 #define UFCR  0x90 /* FIFO Control Register */
  48 #define USR1  0x94 /* Status Register 1 */
  49 #define USR2  0x98 /* Status Register 2 */
  50 #define UESC  0x9c /* Escape Character Register */
  51 #define UTIM  0xa0 /* Escape Timer Register */
  52 #define UBIR  0xa4 /* BRM Incremental Register */
  53 #define UBMR  0xa8 /* BRM Modulator Register */
  54 #define UBRC  0xac /* Baud Rate Count Register */
  55 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  56 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  57 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  58
  59 /* UART Control Register Bit Fields.*/
  60 #define URXD_DUMMY_READ (1<<16)
  61 #define URXD_CHARRDY    (1<<15)
  62 #define URXD_ERR        (1<<14)
  63 #define URXD_OVRRUN     (1<<13)
  64 #define URXD_FRMERR     (1<<12)
  65 #define URXD_BRK        (1<<11)
  66 #define URXD_PRERR      (1<<10)
  67 #define URXD_RX_DATA    (0xFF<<0)
  68 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  69 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  70 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  71 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  72 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  73 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  74 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  75 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  76 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  77 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  78 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  79 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  80 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  81 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  82 #define UCR1_DOZE       (1<<1)  /* Doze */
  83 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  84 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  85 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  86 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  87 #define UCR2_CTS        (1<<12) /* Clear to send */
  88 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  89 #define UCR2_PREN       (1<<8)  /* Parity enable */
  90 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
  91 #define UCR2_STPB       (1<<6)  /* Stop */
  92 #define UCR2_WS         (1<<5)  /* Word size */
  93 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  94 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
  95 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  96 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
  97 #define UCR2_SRST       (1<<0)  /* SW reset */
  98 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
  99 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 100 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 101 #define UCR3_DSR        (1<<10) /* Data set ready */
 102 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 103 #define UCR3_RI         (1<<8)  /* Ring indicator */
 104 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 105 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 106 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 107 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 108 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 109 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 110 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 111 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 112 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 113 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 114 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 115 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 116 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 117 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 118 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 119 #define UCR4_IRSC       (1<<5)  /* IR special case */
 120 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 121 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 122 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 123 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 124 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 125 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 126 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 127 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 128 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 129 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 130 #define USR1_RTSS       (1<<14) /* RTS pin status */
 131 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 132 #define USR1_RTSD       (1<<12) /* RTS delta */
 133 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 134 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 135 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 136 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 137 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 138 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 139 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 140 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 141 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 142 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 143 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 144 #define USR2_IDLE        (1<<12) /* Idle condition */
 145 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 146 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 147 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 148 #define USR2_WAKE        (1<<7)  /* Wake */
 149 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 150 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 151 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 152 #define USR2_BRCD        (1<<2)  /* Break condition */
 153 #define USR2_ORE        (1<<1)   /* Overrun error */
 154 #define USR2_RDR        (1<<0)   /* Recv data ready */
 155 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 156 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 157 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 158 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 159 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 160 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 161 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 162
 163 /* We've been assigned a range on the "Low-density serial ports" major */
 164 #define SERIAL_IMX_MAJOR        207
 165 #define MINOR_START             16
 166 #define DEV_NAME                "ttymxc"
 167
 168 /*
 169  * This determines how often we check the modem status signals
 170  * for any change.  They generally aren't connected to an IRQ
 171  * so we have to poll them.  We also check immediately before
 172  * filling the TX fifo incase CTS has been dropped.
 173  */
 174 #define MCTRL_TIMEOUT   (250*HZ/1000)
 175
 176 #define DRIVER_NAME "IMX-uart"
 177
 178 #define UART_NR 8
 179
 180 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 181 enum imx_uart_type {
 182         IMX1_UART,
 183         IMX21_UART,
 184         IMX53_UART,
 185         IMX6Q_UART,
 186 };
 187
 188 /* device type dependent stuff */
 189 struct imx_uart_data {
 190         unsigned uts_reg;
 191         enum imx_uart_type devtype;
 192 };
 193
 194 struct imx_port {
 195         struct uart_port        port;
 196         struct timer_list       timer;
 197         unsigned int            old_status;
 198         unsigned int            have_rtscts:1;
 199         unsigned int            have_rtsgpio:1;
 200         unsigned int            dte_mode:1;
 201         struct clk              *clk_ipg;
 202         struct clk              *clk_per;
 203         const struct imx_uart_data *devdata;
 204
 205         struct mctrl_gpios *gpios;
 206
 207         /* DMA fields */
 208         unsigned int            dma_is_inited:1;
 209         unsigned int            dma_is_enabled:1;
 210         unsigned int            dma_is_rxing:1;
 211         unsigned int            dma_is_txing:1;
 212         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 213         struct scatterlist      rx_sgl, tx_sgl[2];
 214         void                    *rx_buf;
 215         struct circ_buf         rx_ring;
 216         unsigned int            rx_periods;
 217         dma_cookie_t            rx_cookie;
 218         unsigned int            tx_bytes;
 219         unsigned int            dma_tx_nents;
 220         unsigned int            saved_reg[10];
 221         bool                    context_saved;
 222 };
 223
 224 struct imx_port_ucrs {
 225         unsigned int    ucr1;
 226         unsigned int    ucr2;
 227         unsigned int    ucr3;
 228 };
 229
 230 static struct imx_uart_data imx_uart_devdata[] = {
 231         [IMX1_UART] = {
 232                 .uts_reg = IMX1_UTS,
 233                 .devtype = IMX1_UART,
 234         },
 235         [IMX21_UART] = {
 236                 .uts_reg = IMX21_UTS,
 237                 .devtype = IMX21_UART,
 238         },
 239         [IMX53_UART] = {
 240                 .uts_reg = IMX21_UTS,
 241                 .devtype = IMX53_UART,
 242         },
 243         [IMX6Q_UART] = {
 244                 .uts_reg = IMX21_UTS,
 245                 .devtype = IMX6Q_UART,
 246         },
 247 };
 248
 249 static const struct platform_device_id imx_uart_devtype[] = {
 250         {
 251                 .name = "imx1-uart",
 252                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 253         }, {
 254                 .name = "imx21-uart",
 255                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 256         }, {
 257                 .name = "imx53-uart",
 258                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 259         }, {
 260                 .name = "imx6q-uart",
 261                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 262         }, {
 263                 /* sentinel */
 264         }
 265 };
 266 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 267
 268 static const struct of_device_id imx_uart_dt_ids[] = {
 269         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 270         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 271         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 272         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 273         { /* sentinel */ }
 274 };
 275 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 276
 277 static inline unsigned uts_reg(struct imx_port *sport)
 278 {
 279         return sport->devdata->uts_reg;
 280 }
 281
 282 static inline int is_imx1_uart(struct imx_port *sport)
 283 {
 284         return sport->devdata->devtype == IMX1_UART;
 285 }
 286
 287 static inline int is_imx21_uart(struct imx_port *sport)
 288 {
 289         return sport->devdata->devtype == IMX21_UART;
 290 }
 291
 292 static inline int is_imx53_uart(struct imx_port *sport)
 293 {
 294         return sport->devdata->devtype == IMX53_UART;
 295 }
 296
 297 static inline int is_imx6q_uart(struct imx_port *sport)
 298 {
 299         return sport->devdata->devtype == IMX6Q_UART;
 300 }
 301 /*
 302  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 303  */
 304 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 305 static void imx_port_ucrs_save(struct uart_port *port,
 306                                struct imx_port_ucrs *ucr)
 307 {
 308         /* save control registers */
 309         ucr->ucr1 = readl(port->membase + UCR1);
 310         ucr->ucr2 = readl(port->membase + UCR2);
 311         ucr->ucr3 = readl(port->membase + UCR3);
 312 }
 313
 314 static void imx_port_ucrs_restore(struct uart_port *port,
 315                                   struct imx_port_ucrs *ucr)
 316 {
 317         /* restore control registers */
 318         writel(ucr->ucr1, port->membase + UCR1);
 319         writel(ucr->ucr2, port->membase + UCR2);
 320         writel(ucr->ucr3, port->membase + UCR3);
 321 }
 322 #endif
 323
 324 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 325 {
 326         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 327
 328         sport->port.mctrl |= TIOCM_RTS;
 329         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 330 }
 331
 332 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 333 {
 334         *ucr2 &= ~UCR2_CTSC;
 335         *ucr2 |= UCR2_CTS;
 336
 337         sport->port.mctrl &= ~TIOCM_RTS;
 338         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 339 }
 340
 341 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 342 {
 343         *ucr2 |= UCR2_CTSC;
 344 }
 345
 346 /*
 347  * interrupts disabled on entry
 348  */
 349 static void imx_stop_tx(struct uart_port *port)
 350 {
 351         struct imx_port *sport = (struct imx_port *)port;
 352         unsigned long temp;
 353
 354         /*
 355          * We are maybe in the SMP context, so if the DMA TX thread is running
 356          * on other cpu, we have to wait for it to finish.
 357          */
 358         if (sport->dma_is_enabled && sport->dma_is_txing)
 359                 return;
 360
 361         temp = readl(port->membase + UCR1);
 362         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 363
 364         /* in rs485 mode disable transmitter if shifter is empty */
 365         if (port->rs485.flags & SER_RS485_ENABLED &&
 366             readl(port->membase + USR2) & USR2_TXDC) {
 367                 temp = readl(port->membase + UCR2);
 368                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 369                         imx_port_rts_active(sport, &temp);
 370                 else
 371                         imx_port_rts_inactive(sport, &temp);
 372                 temp |= UCR2_RXEN;
 373                 writel(temp, port->membase + UCR2);
 374
 375                 temp = readl(port->membase + UCR4);
 376                 temp &= ~UCR4_TCEN;
 377                 writel(temp, port->membase + UCR4);
 378         }
 379 }
 380
 381 /*
 382  * interrupts disabled on entry
 383  */
 384 static void imx_stop_rx(struct uart_port *port)
 385 {
 386         struct imx_port *sport = (struct imx_port *)port;
 387         unsigned long temp;
 388
 389         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 390                 if (sport->port.suspended) {
 391                         dmaengine_terminate_all(sport->dma_chan_rx);
 392                         sport->dma_is_rxing = 0;
 393                 } else {
 394                         return;
 395                 }
 396         }
 397
 398         temp = readl(sport->port.membase + UCR2);
 399         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 400
 401         /* disable the `Receiver Ready Interrrupt` */
 402         temp = readl(sport->port.membase + UCR1);
 403         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 404 }
 405
 406 /*
 407  * Set the modem control timer to fire immediately.
 408  */
 409 static void imx_enable_ms(struct uart_port *port)
 410 {
 411         struct imx_port *sport = (struct imx_port *)port;
 412
 413         mod_timer(&sport->timer, jiffies);
 414
 415         mctrl_gpio_enable_ms(sport->gpios);
 416 }
 417
 418 static void imx_dma_tx(struct imx_port *sport);
 419 static inline void imx_transmit_buffer(struct imx_port *sport)
 420 {
 421         struct circ_buf *xmit = &sport->port.state->xmit;
 422         unsigned long temp;
 423
 424         if (sport->port.x_char) {
 425                 /* Send next char */
 426                 writel(sport->port.x_char, sport->port.membase + URTX0);
 427                 sport->port.icount.tx++;
 428                 sport->port.x_char = 0;
 429                 return;
 430         }
 431
 432         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 433                 imx_stop_tx(&sport->port);
 434                 return;
 435         }
 436
 437         if (sport->dma_is_enabled) {
 438                 /*
 439                  * We've just sent a X-char Ensure the TX DMA is enabled
 440                  * and the TX IRQ is disabled.
 441                  **/
 442                 temp = readl(sport->port.membase + UCR1);
 443                 temp &= ~UCR1_TXMPTYEN;
 444                 if (sport->dma_is_txing) {
 445                         temp |= UCR1_TDMAEN;
 446                         writel(temp, sport->port.membase + UCR1);
 447                 } else {
 448                         writel(temp, sport->port.membase + UCR1);
 449                         imx_dma_tx(sport);
 450                 }
 451         }
 452
 453         if (sport->dma_is_txing)
 454                 return;
 455
 456         while (!uart_circ_empty(xmit) &&
 457                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 458                 /* send xmit->buf[xmit->tail]
 459                  * out the port here */
 460                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 461                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 462                 sport->port.icount.tx++;
 463         }
 464
 465         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 466                 uart_write_wakeup(&sport->port);
 467
 468         if (uart_circ_empty(xmit))
 469                 imx_stop_tx(&sport->port);
 470 }
 471
 472 static void dma_tx_callback(void *data)
 473 {
 474         struct imx_port *sport = data;
 475         struct scatterlist *sgl = &sport->tx_sgl[0];
 476         struct circ_buf *xmit = &sport->port.state->xmit;
 477         unsigned long flags;
 478         unsigned long temp;
 479
 480         spin_lock_irqsave(&sport->port.lock, flags);
 481
 482         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 483
 484         temp = readl(sport->port.membase + UCR1);
 485         temp &= ~UCR1_TDMAEN;
 486         writel(temp, sport->port.membase + UCR1);
 487
 488         /* update the stat */
 489         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 490         sport->port.icount.tx += sport->tx_bytes;
 491
 492         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 493
 494         sport->dma_is_txing = 0;
 495
 496         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 497                 uart_write_wakeup(&sport->port);
 498
 499         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 500                 imx_dma_tx(sport);
 501
 502         spin_unlock_irqrestore(&sport->port.lock, flags);
 503 }
 504
 505 static void imx_dma_tx(struct imx_port *sport)
 506 {
 507         struct circ_buf *xmit = &sport->port.state->xmit;
 508         struct scatterlist *sgl = sport->tx_sgl;
 509         struct dma_async_tx_descriptor *desc;
 510         struct dma_chan *chan = sport->dma_chan_tx;
 511         struct device *dev = sport->port.dev;
 512         unsigned long temp;
 513         int ret;
 514
 515         if (sport->dma_is_txing)
 516                 return;
 517
 518         sport->tx_bytes = uart_circ_chars_pending(xmit);
 519
 520         if (xmit->tail < xmit->head) {
 521                 sport->dma_tx_nents = 1;
 522                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 523         } else {
 524                 sport->dma_tx_nents = 2;
 525                 sg_init_table(sgl, 2);
 526                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 527                                 UART_XMIT_SIZE - xmit->tail);
 528                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 529         }
 530
 531         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 532         if (ret == 0) {
 533                 dev_err(dev, "DMA mapping error for TX.\n");
 534                 return;
 535         }
 536         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 537                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 538         if (!desc) {
 539                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 540                              DMA_TO_DEVICE);
 541                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 542                 return;
 543         }
 544         desc->callback = dma_tx_callback;
 545         desc->callback_param = sport;
 546
 547         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 548                         uart_circ_chars_pending(xmit));
 549
 550         temp = readl(sport->port.membase + UCR1);
 551         temp |= UCR1_TDMAEN;
 552         writel(temp, sport->port.membase + UCR1);
 553
 554         /* fire it */
 555         sport->dma_is_txing = 1;
 556         dmaengine_submit(desc);
 557         dma_async_issue_pending(chan);
 558         return;
 559 }
 560
 561 /*
 562  * interrupts disabled on entry
 563  */
 564 static void imx_start_tx(struct uart_port *port)
 565 {
 566         struct imx_port *sport = (struct imx_port *)port;
 567         unsigned long temp;
 568
 569         if (port->rs485.flags & SER_RS485_ENABLED) {
 570                 temp = readl(port->membase + UCR2);
 571                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 572                         imx_port_rts_active(sport, &temp);
 573                 else
 574                         imx_port_rts_inactive(sport, &temp);
 575                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 576                         temp &= ~UCR2_RXEN;
 577                 writel(temp, port->membase + UCR2);
 578
 579                 /* enable transmitter and shifter empty irq */
 580                 temp = readl(port->membase + UCR4);
 581                 temp |= UCR4_TCEN;
 582                 writel(temp, port->membase + UCR4);
 583         }
 584
 585         if (!sport->dma_is_enabled) {
 586                 temp = readl(sport->port.membase + UCR1);
 587                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 588         }
 589
 590         if (sport->dma_is_enabled) {
 591                 if (sport->port.x_char) {
 592                         /* We have X-char to send, so enable TX IRQ and
 593                          * disable TX DMA to let TX interrupt to send X-char */
 594                         temp = readl(sport->port.membase + UCR1);
 595                         temp &= ~UCR1_TDMAEN;
 596                         temp |= UCR1_TXMPTYEN;
 597                         writel(temp, sport->port.membase + UCR1);
 598                         return;
 599                 }
 600
 601                 if (!uart_circ_empty(&port->state->xmit) &&
 602                     !uart_tx_stopped(port))
 603                         imx_dma_tx(sport);
 604                 return;
 605         }
 606 }
 607
 608 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 609 {
 610         struct imx_port *sport = dev_id;
 611         unsigned int val;
 612         unsigned long flags;
 613
 614         spin_lock_irqsave(&sport->port.lock, flags);
 615
 616         writel(USR1_RTSD, sport->port.membase + USR1);
 617         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 618         uart_handle_cts_change(&sport->port, !!val);
 619         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 620
 621         spin_unlock_irqrestore(&sport->port.lock, flags);
 622         return IRQ_HANDLED;
 623 }
 624
 625 static irqreturn_t imx_txint(int irq, void *dev_id)
 626 {
 627         struct imx_port *sport = dev_id;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&sport->port.lock, flags);
 631         imx_transmit_buffer(sport);
 632         spin_unlock_irqrestore(&sport->port.lock, flags);
 633         return IRQ_HANDLED;
 634 }
 635
 636 static irqreturn_t imx_rxint(int irq, void *dev_id)
 637 {
 638         struct imx_port *sport = dev_id;
 639         unsigned int rx, flg, ignored = 0;
 640         struct tty_port *port = &sport->port.state->port;
 641         unsigned long flags, temp;
 642
 643         spin_lock_irqsave(&sport->port.lock, flags);
 644
 645         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 646                 flg = TTY_NORMAL;
 647                 sport->port.icount.rx++;
 648
 649                 rx = readl(sport->port.membase + URXD0);
 650
 651                 temp = readl(sport->port.membase + USR2);
 652                 if (temp & USR2_BRCD) {
 653                         writel(USR2_BRCD, sport->port.membase + USR2);
 654                         if (uart_handle_break(&sport->port))
 655                                 continue;
 656                 }
 657
 658                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 659                         continue;
 660
 661                 if (unlikely(rx & URXD_ERR)) {
 662                         if (rx & URXD_BRK)
 663                                 sport->port.icount.brk++;
 664                         else if (rx & URXD_PRERR)
 665                                 sport->port.icount.parity++;
 666                         else if (rx & URXD_FRMERR)
 667                                 sport->port.icount.frame++;
 668                         if (rx & URXD_OVRRUN)
 669                                 sport->port.icount.overrun++;
 670
 671                         if (rx & sport->port.ignore_status_mask) {
 672                                 if (++ignored > 100)
 673                                         goto out;
 674                                 continue;
 675                         }
 676
 677                         rx &= (sport->port.read_status_mask | 0xFF);
 678
 679                         if (rx & URXD_BRK)
 680                                 flg = TTY_BREAK;
 681                         else if (rx & URXD_PRERR)
 682                                 flg = TTY_PARITY;
 683                         else if (rx & URXD_FRMERR)
 684                                 flg = TTY_FRAME;
 685                         if (rx & URXD_OVRRUN)
 686                                 flg = TTY_OVERRUN;
 687
 688 #ifdef SUPPORT_SYSRQ
 689                         sport->port.sysrq = 0;
 690 #endif
 691                 }
 692
 693                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 694                         goto out;
 695
 696                 if (tty_insert_flip_char(port, rx, flg) == 0)
 697                         sport->port.icount.buf_overrun++;
 698         }
 699
 700 out:
 701         spin_unlock_irqrestore(&sport->port.lock, flags);
 702         tty_flip_buffer_push(port);
 703         return IRQ_HANDLED;
 704 }
 705
 706 static void clear_rx_errors(struct imx_port *sport);
 707
 708 /*
 709  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 710  */
 711 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 712 {
 713         unsigned int tmp = TIOCM_DSR;
 714         unsigned usr1 = readl(sport->port.membase + USR1);
 715         unsigned usr2 = readl(sport->port.membase + USR2);
 716
 717         if (usr1 & USR1_RTSS)
 718                 tmp |= TIOCM_CTS;
 719
 720         /* in DCE mode DCDIN is always 0 */
 721         if (!(usr2 & USR2_DCDIN))
 722                 tmp |= TIOCM_CAR;
 723
 724         if (sport->dte_mode)
 725                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 726                         tmp |= TIOCM_RI;
 727
 728         return tmp;
 729 }
 730
 731 /*
 732  * Handle any change of modem status signal since we were last called.
 733  */
 734 static void imx_mctrl_check(struct imx_port *sport)
 735 {
 736         unsigned int status, changed;
 737
 738         status = imx_get_hwmctrl(sport);
 739         changed = status ^ sport->old_status;
 740
 741         if (changed == 0)
 742                 return;
 743
 744         sport->old_status = status;
 745
 746         if (changed & TIOCM_RI && status & TIOCM_RI)
 747                 sport->port.icount.rng++;
 748         if (changed & TIOCM_DSR)
 749                 sport->port.icount.dsr++;
 750         if (changed & TIOCM_CAR)
 751                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 752         if (changed & TIOCM_CTS)
 753                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 754
 755         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 756 }
 757
 758 static irqreturn_t imx_int(int irq, void *dev_id)
 759 {
 760         struct imx_port *sport = dev_id;
 761         unsigned int sts;
 762         unsigned int sts2;
 763         irqreturn_t ret = IRQ_NONE;
 764
 765         sts = readl(sport->port.membase + USR1);
 766         sts2 = readl(sport->port.membase + USR2);
 767
 768         if (!sport->dma_is_enabled && (sts & (USR1_RRDY | USR1_AGTIM))) {
 769                 imx_rxint(irq, dev_id);
 770                 ret = IRQ_HANDLED;
 771         }
 772
 773         if ((sts & USR1_TRDY &&
 774              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 775             (sts2 & USR2_TXDC &&
 776              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
 777                 imx_txint(irq, dev_id);
 778                 ret = IRQ_HANDLED;
 779         }
 780
 781         if (sts & USR1_DTRD) {
 782                 unsigned long flags;
 783
 784                 if (sts & USR1_DTRD)
 785                         writel(USR1_DTRD, sport->port.membase + USR1);
 786
 787                 spin_lock_irqsave(&sport->port.lock, flags);
 788                 imx_mctrl_check(sport);
 789                 spin_unlock_irqrestore(&sport->port.lock, flags);
 790
 791                 ret = IRQ_HANDLED;
 792         }
 793
 794         if (sts & USR1_RTSD) {
 795                 imx_rtsint(irq, dev_id);
 796                 ret = IRQ_HANDLED;
 797         }
 798
 799         if (sts & USR1_AWAKE) {
 800                 writel(USR1_AWAKE, sport->port.membase + USR1);
 801                 ret = IRQ_HANDLED;
 802         }
 803
 804         if (sts2 & USR2_ORE) {
 805                 sport->port.icount.overrun++;
 806                 writel(USR2_ORE, sport->port.membase + USR2);
 807                 ret = IRQ_HANDLED;
 808         }
 809
 810         return ret;
 811 }
 812
 813 /*
 814  * Return TIOCSER_TEMT when transmitter is not busy.
 815  */
 816 static unsigned int imx_tx_empty(struct uart_port *port)
 817 {
 818         struct imx_port *sport = (struct imx_port *)port;
 819         unsigned int ret;
 820
 821         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 822
 823         /* If the TX DMA is working, return 0. */
 824         if (sport->dma_is_enabled && sport->dma_is_txing)
 825                 ret = 0;
 826
 827         return ret;
 828 }
 829
 830 static unsigned int imx_get_mctrl(struct uart_port *port)
 831 {
 832         struct imx_port *sport = (struct imx_port *)port;
 833         unsigned int ret = imx_get_hwmctrl(sport);
 834
 835         mctrl_gpio_get(sport->gpios, &ret);
 836
 837         return ret;
 838 }
 839
 840 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 841 {
 842         struct imx_port *sport = (struct imx_port *)port;
 843         unsigned long temp;
 844
 845         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 846                 temp = readl(sport->port.membase + UCR2);
 847                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 848                 if (mctrl & TIOCM_RTS)
 849                         temp |= UCR2_CTS | UCR2_CTSC;
 850                 writel(temp, sport->port.membase + UCR2);
 851         }
 852
 853         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 854         if (!(mctrl & TIOCM_DTR))
 855                 temp |= UCR3_DSR;
 856         writel(temp, sport->port.membase + UCR3);
 857
 858         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 859         if (mctrl & TIOCM_LOOP)
 860                 temp |= UTS_LOOP;
 861         writel(temp, sport->port.membase + uts_reg(sport));
 862
 863         mctrl_gpio_set(sport->gpios, mctrl);
 864 }
 865
 866 /*
 867  * Interrupts always disabled.
 868  */
 869 static void imx_break_ctl(struct uart_port *port, int break_state)
 870 {
 871         struct imx_port *sport = (struct imx_port *)port;
 872         unsigned long flags, temp;
 873
 874         spin_lock_irqsave(&sport->port.lock, flags);
 875
 876         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 877
 878         if (break_state != 0)
 879                 temp |= UCR1_SNDBRK;
 880
 881         writel(temp, sport->port.membase + UCR1);
 882
 883         spin_unlock_irqrestore(&sport->port.lock, flags);
 884 }
 885
 886 /*
 887  * This is our per-port timeout handler, for checking the
 888  * modem status signals.
 889  */
 890 static void imx_timeout(struct timer_list *t)
 891 {
 892         struct imx_port *sport = from_timer(sport, t, timer);
 893         unsigned long flags;
 894
 895         if (sport->port.state) {
 896                 spin_lock_irqsave(&sport->port.lock, flags);
 897                 imx_mctrl_check(sport);
 898                 spin_unlock_irqrestore(&sport->port.lock, flags);
 899
 900                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 901         }
 902 }
 903
 904 #define RX_BUF_SIZE     (PAGE_SIZE)
 905
 906 /*
 907  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 908  *   [1] the RX DMA buffer is full.
 909  *   [2] the aging timer expires
 910  *
 911  * Condition [2] is triggered when a character has been sitting in the FIFO
 912  * for at least 8 byte durations.
 913  */
 914 static void dma_rx_callback(void *data)
 915 {
 916         struct imx_port *sport = data;
 917         struct dma_chan *chan = sport->dma_chan_rx;
 918         struct scatterlist *sgl = &sport->rx_sgl;
 919         struct tty_port *port = &sport->port.state->port;
 920         struct dma_tx_state state;
 921         struct circ_buf *rx_ring = &sport->rx_ring;
 922         enum dma_status status;
 923         unsigned int w_bytes = 0;
 924         unsigned int r_bytes;
 925         unsigned int bd_size;
 926
 927         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 928
 929         if (status == DMA_ERROR) {
 930                 dev_err(sport->port.dev, "DMA transaction error.\n");
 931                 clear_rx_errors(sport);
 932                 return;
 933         }
 934
 935         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 936
 937                 /*
 938                  * The state-residue variable represents the empty space
 939                  * relative to the entire buffer. Taking this in consideration
 940                  * the head is always calculated base on the buffer total
 941                  * length - DMA transaction residue. The UART script from the
 942                  * SDMA firmware will jump to the next buffer descriptor,
 943                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
 944                  * Taking this in consideration the tail is always at the
 945                  * beginning of the buffer descriptor that contains the head.
 946                  */
 947
 948                 /* Calculate the head */
 949                 rx_ring->head = sg_dma_len(sgl) - state.residue;
 950
 951                 /* Calculate the tail. */
 952                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
 953                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
 954
 955                 if (rx_ring->head <= sg_dma_len(sgl) &&
 956                     rx_ring->head > rx_ring->tail) {
 957
 958                         /* Move data from tail to head */
 959                         r_bytes = rx_ring->head - rx_ring->tail;
 960
 961                         /* CPU claims ownership of RX DMA buffer */
 962                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
 963                                 DMA_FROM_DEVICE);
 964
 965                         w_bytes = tty_insert_flip_string(port,
 966                                 sport->rx_buf + rx_ring->tail, r_bytes);
 967
 968                         /* UART retrieves ownership of RX DMA buffer */
 969                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
 970                                 DMA_FROM_DEVICE);
 971
 972                         if (w_bytes != r_bytes)
 973                                 sport->port.icount.buf_overrun++;
 974
 975                         sport->port.icount.rx += w_bytes;
 976                 } else  {
 977                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
 978                         WARN_ON(rx_ring->head <= rx_ring->tail);
 979                 }
 980         }
 981
 982         if (w_bytes) {
 983                 tty_flip_buffer_push(port);
 984                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
 985         }
 986 }
 987
 988 /* RX DMA buffer periods */
 989 #define RX_DMA_PERIODS 4
 990
 991 static int start_rx_dma(struct imx_port *sport)
 992 {
 993         struct scatterlist *sgl = &sport->rx_sgl;
 994         struct dma_chan *chan = sport->dma_chan_rx;
 995         struct device *dev = sport->port.dev;
 996         struct dma_async_tx_descriptor *desc;
 997         int ret;
 998
 999         sport->rx_ring.head = 0;
1000         sport->rx_ring.tail = 0;
1001         sport->rx_periods = RX_DMA_PERIODS;
1002
1003         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1004         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1005         if (ret == 0) {
1006                 dev_err(dev, "DMA mapping error for RX.\n");
1007                 return -EINVAL;
1008         }
1009
1010         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1011                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1012                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1013
1014         if (!desc) {
1015                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1016                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1017                 return -EINVAL;
1018         }
1019         desc->callback = dma_rx_callback;
1020         desc->callback_param = sport;
1021
1022         dev_dbg(dev, "RX: prepare for the DMA.\n");
1023         sport->dma_is_rxing = 1;
1024         sport->rx_cookie = dmaengine_submit(desc);
1025         dma_async_issue_pending(chan);
1026         return 0;
1027 }
1028
1029 static void clear_rx_errors(struct imx_port *sport)
1030 {
1031         unsigned int status_usr1, status_usr2;
1032
1033         status_usr1 = readl(sport->port.membase + USR1);
1034         status_usr2 = readl(sport->port.membase + USR2);
1035
1036         if (status_usr2 & USR2_BRCD) {
1037                 sport->port.icount.brk++;
1038                 writel(USR2_BRCD, sport->port.membase + USR2);
1039         } else if (status_usr1 & USR1_FRAMERR) {
1040                 sport->port.icount.frame++;
1041                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1042         } else if (status_usr1 & USR1_PARITYERR) {
1043                 sport->port.icount.parity++;
1044                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1045         }
1046
1047         if (status_usr2 & USR2_ORE) {
1048                 sport->port.icount.overrun++;
1049                 writel(USR2_ORE, sport->port.membase + USR2);
1050         }
1051
1052 }
1053
1054 #define TXTL_DEFAULT 2 /* reset default */
1055 #define RXTL_DEFAULT 1 /* reset default */
1056 #define TXTL_DMA 8 /* DMA burst setting */
1057 #define RXTL_DMA 9 /* DMA burst setting */
1058
1059 static void imx_setup_ufcr(struct imx_port *sport,
1060                           unsigned char txwl, unsigned char rxwl)
1061 {
1062         unsigned int val;
1063
1064         /* set receiver / transmitter trigger level */
1065         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1066         val |= txwl << UFCR_TXTL_SHF | rxwl;
1067         writel(val, sport->port.membase + UFCR);
1068 }
1069
1070 static void imx_uart_dma_exit(struct imx_port *sport)
1071 {
1072         if (sport->dma_chan_rx) {
1073                 dmaengine_terminate_sync(sport->dma_chan_rx);
1074                 dma_release_channel(sport->dma_chan_rx);
1075                 sport->dma_chan_rx = NULL;
1076                 sport->rx_cookie = -EINVAL;
1077                 kfree(sport->rx_buf);
1078                 sport->rx_buf = NULL;
1079         }
1080
1081         if (sport->dma_chan_tx) {
1082                 dmaengine_terminate_sync(sport->dma_chan_tx);
1083                 dma_release_channel(sport->dma_chan_tx);
1084                 sport->dma_chan_tx = NULL;
1085         }
1086
1087         sport->dma_is_inited = 0;
1088 }
1089
1090 static int imx_uart_dma_init(struct imx_port *sport)
1091 {
1092         struct dma_slave_config slave_config = {};
1093         struct device *dev = sport->port.dev;
1094         int ret;
1095
1096         /* Prepare for RX : */
1097         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1098         if (!sport->dma_chan_rx) {
1099                 dev_dbg(dev, "cannot get the DMA channel.\n");
1100                 ret = -EINVAL;
1101                 goto err;
1102         }
1103
1104         slave_config.direction = DMA_DEV_TO_MEM;
1105         slave_config.src_addr = sport->port.mapbase + URXD0;
1106         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1107         /* one byte less than the watermark level to enable the aging timer */
1108         slave_config.src_maxburst = RXTL_DMA - 1;
1109         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1110         if (ret) {
1111                 dev_err(dev, "error in RX dma configuration.\n");
1112                 goto err;
1113         }
1114
1115         sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1116         if (!sport->rx_buf) {
1117                 ret = -ENOMEM;
1118                 goto err;
1119         }
1120         sport->rx_ring.buf = sport->rx_buf;
1121
1122         /* Prepare for TX : */
1123         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1124         if (!sport->dma_chan_tx) {
1125                 dev_err(dev, "cannot get the TX DMA channel!\n");
1126                 ret = -EINVAL;
1127                 goto err;
1128         }
1129
1130         slave_config.direction = DMA_MEM_TO_DEV;
1131         slave_config.dst_addr = sport->port.mapbase + URTX0;
1132         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1133         slave_config.dst_maxburst = TXTL_DMA;
1134         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1135         if (ret) {
1136                 dev_err(dev, "error in TX dma configuration.");
1137                 goto err;
1138         }
1139
1140         sport->dma_is_inited = 1;
1141
1142         return 0;
1143 err:
1144         imx_uart_dma_exit(sport);
1145         return ret;
1146 }
1147
1148 static void imx_enable_dma(struct imx_port *sport)
1149 {
1150         unsigned long temp;
1151
1152         /* set UCR1 */
1153         temp = readl(sport->port.membase + UCR1);
1154         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1155         writel(temp, sport->port.membase + UCR1);
1156
1157         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1158
1159         sport->dma_is_enabled = 1;
1160 }
1161
1162 static void imx_disable_dma(struct imx_port *sport)
1163 {
1164         unsigned long temp;
1165
1166         /* clear UCR1 */
1167         temp = readl(sport->port.membase + UCR1);
1168         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1169         writel(temp, sport->port.membase + UCR1);
1170
1171         /* clear UCR2 */
1172         temp = readl(sport->port.membase + UCR2);
1173         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1174         writel(temp, sport->port.membase + UCR2);
1175
1176         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1177
1178         sport->dma_is_enabled = 0;
1179 }
1180
1181 /* half the RX buffer size */
1182 #define CTSTL 16
1183
1184 static int imx_startup(struct uart_port *port)
1185 {
1186         struct imx_port *sport = (struct imx_port *)port;
1187         int retval, i;
1188         unsigned long flags, temp;
1189
1190         retval = clk_prepare_enable(sport->clk_per);
1191         if (retval)
1192                 return retval;
1193         retval = clk_prepare_enable(sport->clk_ipg);
1194         if (retval) {
1195                 clk_disable_unprepare(sport->clk_per);
1196                 return retval;
1197         }
1198
1199         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1200
1201         /* disable the DREN bit (Data Ready interrupt enable) before
1202          * requesting IRQs
1203          */
1204         temp = readl(sport->port.membase + UCR4);
1205
1206         /* set the trigger level for CTS */
1207         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1208         temp |= CTSTL << UCR4_CTSTL_SHF;
1209
1210         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1211
1212         /* Can we enable the DMA support? */
1213         if (!uart_console(port) && !sport->dma_is_inited)
1214                 imx_uart_dma_init(sport);
1215
1216         spin_lock_irqsave(&sport->port.lock, flags);
1217         /* Reset fifo's and state machines */
1218         i = 100;
1219
1220         temp = readl(sport->port.membase + UCR2);
1221         temp &= ~UCR2_SRST;
1222         writel(temp, sport->port.membase + UCR2);
1223
1224         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1225                 udelay(1);
1226
1227         /*
1228          * Finally, clear and enable interrupts
1229          */
1230         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1231         writel(USR2_ORE, sport->port.membase + USR2);
1232
1233         if (sport->dma_is_inited && !sport->dma_is_enabled)
1234                 imx_enable_dma(sport);
1235
1236         temp = readl(sport->port.membase + UCR1) & ~UCR1_RRDYEN;
1237         if (!sport->dma_is_enabled)
1238                 temp |= UCR1_RRDYEN;
1239         temp |= UCR1_UARTEN;
1240         if (sport->have_rtscts)
1241                         temp |= UCR1_RTSDEN;
1242
1243         writel(temp, sport->port.membase + UCR1);
1244
1245         temp = readl(sport->port.membase + UCR4) & ~UCR4_OREN;
1246         if (!sport->dma_is_enabled)
1247                 temp |= UCR4_OREN;
1248         writel(temp, sport->port.membase + UCR4);
1249
1250         temp = readl(sport->port.membase + UCR2) & ~UCR2_ATEN;
1251         temp |= (UCR2_RXEN | UCR2_TXEN);
1252         if (!sport->have_rtscts)
1253                 temp |= UCR2_IRTS;
1254         /*
1255          * make sure the edge sensitive RTS-irq is disabled,
1256          * we're using RTSD instead.
1257          */
1258         if (!is_imx1_uart(sport))
1259                 temp &= ~UCR2_RTSEN;
1260         writel(temp, sport->port.membase + UCR2);
1261
1262         if (!is_imx1_uart(sport)) {
1263                 temp = readl(sport->port.membase + UCR3);
1264
1265                 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1266
1267                 if (sport->dte_mode)
1268                         /* disable broken interrupts */
1269                         temp &= ~(UCR3_RI | UCR3_DCD);
1270
1271                 writel(temp, sport->port.membase + UCR3);
1272         }
1273
1274         /*
1275          * Enable modem status interrupts
1276          */
1277         imx_enable_ms(&sport->port);
1278
1279         /*
1280          * Start RX DMA immediately instead of waiting for RX FIFO interrupts.
1281          * In our iMX53 the average delay for the first reception dropped from
1282          * approximately 35000 microseconds to 1000 microseconds.
1283          */
1284         if (sport->dma_is_enabled)
1285                 start_rx_dma(sport);
1286
1287         spin_unlock_irqrestore(&sport->port.lock, flags);
1288
1289         return 0;
1290 }
1291
1292 static void imx_shutdown(struct uart_port *port)
1293 {
1294         struct imx_port *sport = (struct imx_port *)port;
1295         unsigned long temp;
1296         unsigned long flags;
1297
1298         if (sport->dma_is_enabled) {
1299                 sport->dma_is_rxing = 0;
1300                 sport->dma_is_txing = 0;
1301                 dmaengine_terminate_sync(sport->dma_chan_tx);
1302                 dmaengine_terminate_sync(sport->dma_chan_rx);
1303
1304                 spin_lock_irqsave(&sport->port.lock, flags);
1305                 imx_stop_tx(port);
1306                 imx_stop_rx(port);
1307                 imx_disable_dma(sport);
1308                 spin_unlock_irqrestore(&sport->port.lock, flags);
1309                 imx_uart_dma_exit(sport);
1310         }
1311
1312         mctrl_gpio_disable_ms(sport->gpios);
1313
1314         spin_lock_irqsave(&sport->port.lock, flags);
1315         temp = readl(sport->port.membase + UCR2);
1316         temp &= ~(UCR2_TXEN);
1317         writel(temp, sport->port.membase + UCR2);
1318         spin_unlock_irqrestore(&sport->port.lock, flags);
1319
1320         /*
1321          * Stop our timer.
1322          */
1323         del_timer_sync(&sport->timer);
1324
1325         /*
1326          * Disable all interrupts, port and break condition.
1327          */
1328
1329         spin_lock_irqsave(&sport->port.lock, flags);
1330         temp = readl(sport->port.membase + UCR1);
1331         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1332
1333         writel(temp, sport->port.membase + UCR1);
1334         spin_unlock_irqrestore(&sport->port.lock, flags);
1335
1336         clk_disable_unprepare(sport->clk_per);
1337         clk_disable_unprepare(sport->clk_ipg);
1338 }
1339
1340 static void imx_flush_buffer(struct uart_port *port)
1341 {
1342         struct imx_port *sport = (struct imx_port *)port;
1343         struct scatterlist *sgl = &sport->tx_sgl[0];
1344         unsigned long temp;
1345         int i = 100, ubir, ubmr, uts;
1346
1347         if (!sport->dma_chan_tx)
1348                 return;
1349
1350         sport->tx_bytes = 0;
1351         dmaengine_terminate_all(sport->dma_chan_tx);
1352         if (sport->dma_is_txing) {
1353                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1354                              DMA_TO_DEVICE);
1355                 temp = readl(sport->port.membase + UCR1);
1356                 temp &= ~UCR1_TDMAEN;
1357                 writel(temp, sport->port.membase + UCR1);
1358                 sport->dma_is_txing = 0;
1359         }
1360
1361         /*
1362          * According to the Reference Manual description of the UART SRST bit:
1363          *
1364          * "Reset the transmit and receive state machines,
1365          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1366          * and UTS[6-3]".
1367          *
1368          * We don't need to restore the old values from USR1, USR2, URXD and
1369          * UTXD. UBRC is read only, so only save/restore the other three
1370          * registers.
1371          */
1372         ubir = readl(sport->port.membase + UBIR);
1373         ubmr = readl(sport->port.membase + UBMR);
1374         uts = readl(sport->port.membase + IMX21_UTS);
1375
1376         temp = readl(sport->port.membase + UCR2);
1377         temp &= ~UCR2_SRST;
1378         writel(temp, sport->port.membase + UCR2);
1379
1380         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1381                 udelay(1);
1382
1383         /* Restore the registers */
1384         writel(ubir, sport->port.membase + UBIR);
1385         writel(ubmr, sport->port.membase + UBMR);
1386         writel(uts, sport->port.membase + IMX21_UTS);
1387 }
1388
1389 static void
1390 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1391                    struct ktermios *old)
1392 {
1393         struct imx_port *sport = (struct imx_port *)port;
1394         unsigned long flags;
1395         unsigned long ucr2, old_ucr1, old_ucr2;
1396         unsigned int baud, quot;
1397         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1398         unsigned long div, ufcr;
1399         unsigned long num, denom;
1400         uint64_t tdiv64;
1401
1402         /*
1403          * We only support CS7 and CS8.
1404          */
1405         while ((termios->c_cflag & CSIZE) != CS7 &&
1406                (termios->c_cflag & CSIZE) != CS8) {
1407                 termios->c_cflag &= ~CSIZE;
1408                 termios->c_cflag |= old_csize;
1409                 old_csize = CS8;
1410         }
1411
1412         if ((termios->c_cflag & CSIZE) == CS8)
1413                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1414         else
1415                 ucr2 = UCR2_SRST | UCR2_IRTS;
1416
1417         if (termios->c_cflag & CRTSCTS) {
1418                 if (sport->have_rtscts) {
1419                         ucr2 &= ~UCR2_IRTS;
1420
1421                         if (port->rs485.flags & SER_RS485_ENABLED) {
1422                                 /*
1423                                  * RTS is mandatory for rs485 operation, so keep
1424                                  * it under manual control and keep transmitter
1425                                  * disabled.
1426                                  */
1427                                 if (port->rs485.flags &
1428                                     SER_RS485_RTS_AFTER_SEND)
1429                                         imx_port_rts_active(sport, &ucr2);
1430                                 else
1431                                         imx_port_rts_inactive(sport, &ucr2);
1432                         } else {
1433                                 imx_port_rts_auto(sport, &ucr2);
1434                         }
1435                 } else {
1436                         termios->c_cflag &= ~CRTSCTS;
1437                 }
1438         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1439                 /* disable transmitter */
1440                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1441                         imx_port_rts_active(sport, &ucr2);
1442                 else
1443                         imx_port_rts_inactive(sport, &ucr2);
1444         }
1445
1446
1447         if (termios->c_cflag & CSTOPB)
1448                 ucr2 |= UCR2_STPB;
1449         if (termios->c_cflag & PARENB) {
1450                 ucr2 |= UCR2_PREN;
1451                 if (termios->c_cflag & PARODD)
1452                         ucr2 |= UCR2_PROE;
1453         }
1454
1455         del_timer_sync(&sport->timer);
1456
1457         /*
1458          * Ask the core to calculate the divisor for us.
1459          */
1460         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1461         quot = uart_get_divisor(port, baud);
1462
1463         spin_lock_irqsave(&sport->port.lock, flags);
1464
1465         sport->port.read_status_mask = 0;
1466         if (termios->c_iflag & INPCK)
1467                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1468         if (termios->c_iflag & (BRKINT | PARMRK))
1469                 sport->port.read_status_mask |= URXD_BRK;
1470
1471         /*
1472          * Characters to ignore
1473          */
1474         sport->port.ignore_status_mask = 0;
1475         if (termios->c_iflag & IGNPAR)
1476                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1477         if (termios->c_iflag & IGNBRK) {
1478                 sport->port.ignore_status_mask |= URXD_BRK;
1479                 /*
1480                  * If we're ignoring parity and break indicators,
1481                  * ignore overruns too (for real raw support).
1482                  */
1483                 if (termios->c_iflag & IGNPAR)
1484                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1485         }
1486
1487         if ((termios->c_cflag & CREAD) == 0)
1488                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1489
1490         /*
1491          * Update the per-port timeout.
1492          */
1493         uart_update_timeout(port, termios->c_cflag, baud);
1494
1495         /*
1496          * disable interrupts and drain transmitter
1497          */
1498         old_ucr1 = readl(sport->port.membase + UCR1);
1499         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1500                         sport->port.membase + UCR1);
1501
1502         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1503                 barrier();
1504
1505         /* then, disable everything */
1506         old_ucr2 = readl(sport->port.membase + UCR2);
1507         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1508                         sport->port.membase + UCR2);
1509         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1510
1511         /* custom-baudrate handling */
1512         div = sport->port.uartclk / (baud * 16);
1513         if (baud == 38400 && quot != div)
1514                 baud = sport->port.uartclk / (quot * 16);
1515
1516         div = sport->port.uartclk / (baud * 16);
1517         if (div > 7)
1518                 div = 7;
1519         if (!div)
1520                 div = 1;
1521
1522         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1523                 1 << 16, 1 << 16, &num, &denom);
1524
1525         tdiv64 = sport->port.uartclk;
1526         tdiv64 *= num;
1527         do_div(tdiv64, denom * 16 * div);
1528         tty_termios_encode_baud_rate(termios,
1529                                 (speed_t)tdiv64, (speed_t)tdiv64);
1530
1531         num -= 1;
1532         denom -= 1;
1533
1534         ufcr = readl(sport->port.membase + UFCR);
1535         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1536         writel(ufcr, sport->port.membase + UFCR);
1537
1538         writel(num, sport->port.membase + UBIR);
1539         writel(denom, sport->port.membase + UBMR);
1540
1541         if (!is_imx1_uart(sport))
1542                 writel(sport->port.uartclk / div / 1000,
1543                                 sport->port.membase + IMX21_ONEMS);
1544
1545         writel(old_ucr1, sport->port.membase + UCR1);
1546
1547         /* set the parity, stop bits and data size */
1548         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1549
1550         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1551                 imx_enable_ms(&sport->port);
1552
1553         spin_unlock_irqrestore(&sport->port.lock, flags);
1554 }
1555
1556 static const char *imx_type(struct uart_port *port)
1557 {
1558         struct imx_port *sport = (struct imx_port *)port;
1559
1560         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1561 }
1562
1563 /*
1564  * Configure/autoconfigure the port.
1565  */
1566 static void imx_config_port(struct uart_port *port, int flags)
1567 {
1568         struct imx_port *sport = (struct imx_port *)port;
1569
1570         if (flags & UART_CONFIG_TYPE)
1571                 sport->port.type = PORT_IMX;
1572 }
1573
1574 /*
1575  * Verify the new serial_struct (for TIOCSSERIAL).
1576  * The only change we allow are to the flags and type, and
1577  * even then only between PORT_IMX and PORT_UNKNOWN
1578  */
1579 static int
1580 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1581 {
1582         struct imx_port *sport = (struct imx_port *)port;
1583         int ret = 0;
1584
1585         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1586                 ret = -EINVAL;
1587         if (sport->port.irq != ser->irq)
1588                 ret = -EINVAL;
1589         if (ser->io_type != UPIO_MEM)
1590                 ret = -EINVAL;
1591         if (sport->port.uartclk / 16 != ser->baud_base)
1592                 ret = -EINVAL;
1593         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1594                 ret = -EINVAL;
1595         if (sport->port.iobase != ser->port)
1596                 ret = -EINVAL;
1597         if (ser->hub6 != 0)
1598                 ret = -EINVAL;
1599         return ret;
1600 }
1601
1602 #if defined(CONFIG_CONSOLE_POLL)
1603
1604 static int imx_poll_init(struct uart_port *port)
1605 {
1606         struct imx_port *sport = (struct imx_port *)port;
1607         unsigned long flags;
1608         unsigned long temp;
1609         int retval;
1610
1611         retval = clk_prepare_enable(sport->clk_ipg);
1612         if (retval)
1613                 return retval;
1614         retval = clk_prepare_enable(sport->clk_per);
1615         if (retval)
1616                 clk_disable_unprepare(sport->clk_ipg);
1617
1618         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1619
1620         spin_lock_irqsave(&sport->port.lock, flags);
1621
1622         temp = readl(sport->port.membase + UCR1);
1623         if (is_imx1_uart(sport))
1624                 temp |= IMX1_UCR1_UARTCLKEN;
1625         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1626         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1627         writel(temp, sport->port.membase + UCR1);
1628
1629         temp = readl(sport->port.membase + UCR2);
1630         temp |= UCR2_RXEN;
1631         writel(temp, sport->port.membase + UCR2);
1632
1633         spin_unlock_irqrestore(&sport->port.lock, flags);
1634
1635         return 0;
1636 }
1637
1638 static int imx_poll_get_char(struct uart_port *port)
1639 {
1640         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1641                 return NO_POLL_CHAR;
1642
1643         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1644 }
1645
1646 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1647 {
1648         unsigned int status;
1649
1650         /* drain */
1651         do {
1652                 status = readl_relaxed(port->membase + USR1);
1653         } while (~status & USR1_TRDY);
1654
1655         /* write */
1656         writel_relaxed(c, port->membase + URTX0);
1657
1658         /* flush */
1659         do {
1660                 status = readl_relaxed(port->membase + USR2);
1661         } while (~status & USR2_TXDC);
1662 }
1663 #endif
1664
1665 static int imx_rs485_config(struct uart_port *port,
1666                             struct serial_rs485 *rs485conf)
1667 {
1668         struct imx_port *sport = (struct imx_port *)port;
1669         unsigned long temp;
1670
1671         /* unimplemented */
1672         rs485conf->delay_rts_before_send = 0;
1673         rs485conf->delay_rts_after_send = 0;
1674
1675         /* RTS is required to control the transmitter */
1676         if (!sport->have_rtscts && !sport->have_rtsgpio)
1677                 rs485conf->flags &= ~SER_RS485_ENABLED;
1678
1679         if (rs485conf->flags & SER_RS485_ENABLED) {
1680                 /* disable transmitter */
1681                 temp = readl(sport->port.membase + UCR2);
1682                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1683                         imx_port_rts_active(sport, &temp);
1684                 else
1685                         imx_port_rts_inactive(sport, &temp);
1686                 writel(temp, sport->port.membase + UCR2);
1687         }
1688
1689         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1690         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1691             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1692                 temp = readl(sport->port.membase + UCR2);
1693                 temp |= UCR2_RXEN;
1694                 writel(temp, sport->port.membase + UCR2);
1695         }
1696
1697         port->rs485 = *rs485conf;
1698
1699         return 0;
1700 }
1701
1702 static const struct uart_ops imx_pops = {
1703         .tx_empty       = imx_tx_empty,
1704         .set_mctrl      = imx_set_mctrl,
1705         .get_mctrl      = imx_get_mctrl,
1706         .stop_tx        = imx_stop_tx,
1707         .start_tx       = imx_start_tx,
1708         .stop_rx        = imx_stop_rx,
1709         .enable_ms      = imx_enable_ms,
1710         .break_ctl      = imx_break_ctl,
1711         .startup        = imx_startup,
1712         .shutdown       = imx_shutdown,
1713         .flush_buffer   = imx_flush_buffer,
1714         .set_termios    = imx_set_termios,
1715         .type           = imx_type,
1716         .config_port    = imx_config_port,
1717         .verify_port    = imx_verify_port,
1718 #if defined(CONFIG_CONSOLE_POLL)
1719         .poll_init      = imx_poll_init,
1720         .poll_get_char  = imx_poll_get_char,
1721         .poll_put_char  = imx_poll_put_char,
1722 #endif
1723 };
1724
1725 static struct imx_port *imx_ports[UART_NR];
1726
1727 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1728 static void imx_console_putchar(struct uart_port *port, int ch)
1729 {
1730         struct imx_port *sport = (struct imx_port *)port;
1731
1732         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1733                 barrier();
1734
1735         writel(ch, sport->port.membase + URTX0);
1736 }
1737
1738 /*
1739  * Interrupts are disabled on entering
1740  */
1741 static void
1742 imx_console_write(struct console *co, const char *s, unsigned int count)
1743 {
1744         struct imx_port *sport = imx_ports[co->index];
1745         struct imx_port_ucrs old_ucr;
1746         unsigned int ucr1;
1747         unsigned long flags = 0;
1748         int locked = 1;
1749         int retval;
1750
1751         retval = clk_enable(sport->clk_per);
1752         if (retval)
1753                 return;
1754         retval = clk_enable(sport->clk_ipg);
1755         if (retval) {
1756                 clk_disable(sport->clk_per);
1757                 return;
1758         }
1759
1760         if (sport->port.sysrq)
1761                 locked = 0;
1762         else if (oops_in_progress)
1763                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1764         else
1765                 spin_lock_irqsave(&sport->port.lock, flags);
1766
1767         /*
1768          *      First, save UCR1/2/3 and then disable interrupts
1769          */
1770         imx_port_ucrs_save(&sport->port, &old_ucr);
1771         ucr1 = old_ucr.ucr1;
1772
1773         if (is_imx1_uart(sport))
1774                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1775         ucr1 |= UCR1_UARTEN;
1776         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1777
1778         writel(ucr1, sport->port.membase + UCR1);
1779
1780         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1781
1782         uart_console_write(&sport->port, s, count, imx_console_putchar);
1783
1784         /*
1785          *      Finally, wait for transmitter to become empty
1786          *      and restore UCR1/2/3
1787          */
1788         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1789
1790         imx_port_ucrs_restore(&sport->port, &old_ucr);
1791
1792         if (locked)
1793                 spin_unlock_irqrestore(&sport->port.lock, flags);
1794
1795         clk_disable(sport->clk_ipg);
1796         clk_disable(sport->clk_per);
1797 }
1798
1799 /*
1800  * If the port was already initialised (eg, by a boot loader),
1801  * try to determine the current setup.
1802  */
1803 static void __init
1804 imx_console_get_options(struct imx_port *sport, int *baud,
1805                            int *parity, int *bits)
1806 {
1807
1808         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1809                 /* ok, the port was enabled */
1810                 unsigned int ucr2, ubir, ubmr, uartclk;
1811                 unsigned int baud_raw;
1812                 unsigned int ucfr_rfdiv;
1813
1814                 ucr2 = readl(sport->port.membase + UCR2);
1815
1816                 *parity = 'n';
1817                 if (ucr2 & UCR2_PREN) {
1818                         if (ucr2 & UCR2_PROE)
1819                                 *parity = 'o';
1820                         else
1821                                 *parity = 'e';
1822                 }
1823
1824                 if (ucr2 & UCR2_WS)
1825                         *bits = 8;
1826                 else
1827                         *bits = 7;
1828
1829                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1830                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1831
1832                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1833                 if (ucfr_rfdiv == 6)
1834                         ucfr_rfdiv = 7;
1835                 else
1836                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1837
1838                 uartclk = clk_get_rate(sport->clk_per);
1839                 uartclk /= ucfr_rfdiv;
1840
1841                 {       /*
1842                          * The next code provides exact computation of
1843                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1844                          * without need of float support or long long division,
1845                          * which would be required to prevent 32bit arithmetic overflow
1846                          */
1847                         unsigned int mul = ubir + 1;
1848                         unsigned int div = 16 * (ubmr + 1);
1849                         unsigned int rem = uartclk % div;
1850
1851                         baud_raw = (uartclk / div) * mul;
1852                         baud_raw += (rem * mul + div / 2) / div;
1853                         *baud = (baud_raw + 50) / 100 * 100;
1854                 }
1855
1856                 if (*baud != baud_raw)
1857                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1858                                 baud_raw, *baud);
1859         }
1860 }
1861
1862 static int __init
1863 imx_console_setup(struct console *co, char *options)
1864 {
1865         struct imx_port *sport;
1866         int baud = 9600;
1867         int bits = 8;
1868         int parity = 'n';
1869         int flow = 'n';
1870         int retval;
1871
1872         /*
1873          * Check whether an invalid uart number has been specified, and
1874          * if so, search for the first available port that does have
1875          * console support.
1876          */
1877         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1878                 co->index = 0;
1879         sport = imx_ports[co->index];
1880         if (sport == NULL)
1881                 return -ENODEV;
1882
1883         /* For setting the registers, we only need to enable the ipg clock. */
1884         retval = clk_prepare_enable(sport->clk_ipg);
1885         if (retval)
1886                 goto error_console;
1887
1888         if (options)
1889                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1890         else
1891                 imx_console_get_options(sport, &baud, &parity, &bits);
1892
1893         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1894
1895         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1896
1897         clk_disable(sport->clk_ipg);
1898         if (retval) {
1899                 clk_unprepare(sport->clk_ipg);
1900                 goto error_console;
1901         }
1902
1903         retval = clk_prepare(sport->clk_per);
1904         if (retval)
1905                 clk_disable_unprepare(sport->clk_ipg);
1906
1907 error_console:
1908         return retval;
1909 }
1910
1911 static struct uart_driver imx_reg;
1912 static struct console imx_console = {
1913         .name           = DEV_NAME,
1914         .write          = imx_console_write,
1915         .device         = uart_console_device,
1916         .setup          = imx_console_setup,
1917         .flags          = CON_PRINTBUFFER,
1918         .index          = -1,
1919         .data           = &imx_reg,
1920 };
1921
1922 #define IMX_CONSOLE     &imx_console
1923
1924 #ifdef CONFIG_OF
1925 static void imx_console_early_putchar(struct uart_port *port, int ch)
1926 {
1927         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1928                 cpu_relax();
1929
1930         writel_relaxed(ch, port->membase + URTX0);
1931 }
1932
1933 static void imx_console_early_write(struct console *con, const char *s,
1934                                     unsigned count)
1935 {
1936         struct earlycon_device *dev = con->data;
1937
1938         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1939 }
1940
1941 static int __init
1942 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1943 {
1944         if (!dev->port.membase)
1945                 return -ENODEV;
1946
1947         dev->con->write = imx_console_early_write;
1948
1949         return 0;
1950 }
1951 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1952 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1953 #endif
1954
1955 #else
1956 #define IMX_CONSOLE     NULL
1957 #endif
1958
1959 static struct uart_driver imx_reg = {
1960         .owner          = THIS_MODULE,
1961         .driver_name    = DRIVER_NAME,
1962         .dev_name       = DEV_NAME,
1963         .major          = SERIAL_IMX_MAJOR,
1964         .minor          = MINOR_START,
1965         .nr             = ARRAY_SIZE(imx_ports),
1966         .cons           = IMX_CONSOLE,
1967 };
1968
1969 #ifdef CONFIG_OF
1970 /*
1971  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1972  * could successfully get all information from dt or a negative errno.
1973  */
1974 static int serial_imx_probe_dt(struct imx_port *sport,
1975                 struct platform_device *pdev)
1976 {
1977         struct device_node *np = pdev->dev.of_node;
1978         int ret;
1979
1980         sport->devdata = of_device_get_match_data(&pdev->dev);
1981         if (!sport->devdata)
1982                 /* no device tree device */
1983                 return 1;
1984
1985         ret = of_alias_get_id(np, "serial");
1986         if (ret < 0) {
1987                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1988                 return ret;
1989         }
1990         sport->port.line = ret;
1991
1992         if (of_get_property(np, "uart-has-rtscts", NULL) ||
1993             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1994                 sport->have_rtscts = 1;
1995
1996         if (of_get_property(np, "fsl,dte-mode", NULL))
1997                 sport->dte_mode = 1;
1998
1999         if (of_get_property(np, "rts-gpios", NULL))
2000                 sport->have_rtsgpio = 1;
2001
2002         return 0;
2003 }
2004 #else
2005 static inline int serial_imx_probe_dt(struct imx_port *sport,
2006                 struct platform_device *pdev)
2007 {
2008         return 1;
2009 }
2010 #endif
2011
2012 static void serial_imx_probe_pdata(struct imx_port *sport,
2013                 struct platform_device *pdev)
2014 {
2015         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2016
2017         sport->port.line = pdev->id;
2018         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2019
2020         if (!pdata)
2021                 return;
2022
2023         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2024                 sport->have_rtscts = 1;
2025 }
2026
2027 static int serial_imx_probe(struct platform_device *pdev)
2028 {
2029         struct imx_port *sport;
2030         void __iomem *base;
2031         int ret = 0, reg;
2032         struct resource *res;
2033         int txirq, rxirq, rtsirq;
2034
2035         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2036         if (!sport)
2037                 return -ENOMEM;
2038
2039         ret = serial_imx_probe_dt(sport, pdev);
2040         if (ret > 0)
2041                 serial_imx_probe_pdata(sport, pdev);
2042         else if (ret < 0)
2043                 return ret;
2044
2045         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2046         base = devm_ioremap_resource(&pdev->dev, res);
2047         if (IS_ERR(base))
2048                 return PTR_ERR(base);
2049
2050         rxirq = platform_get_irq(pdev, 0);
2051         txirq = platform_get_irq(pdev, 1);
2052         rtsirq = platform_get_irq(pdev, 2);
2053
2054         sport->port.dev = &pdev->dev;
2055         sport->port.mapbase = res->start;
2056         sport->port.membase = base;
2057         sport->port.type = PORT_IMX,
2058         sport->port.iotype = UPIO_MEM;
2059         sport->port.irq = rxirq;
2060         sport->port.fifosize = 32;
2061         sport->port.ops = &imx_pops;
2062         sport->port.rs485_config = imx_rs485_config;
2063         sport->port.flags = UPF_BOOT_AUTOCONF;
2064         timer_setup(&sport->timer, imx_timeout, 0);
2065
2066         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2067         if (IS_ERR(sport->gpios))
2068                 return PTR_ERR(sport->gpios);
2069
2070         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2071         if (IS_ERR(sport->clk_ipg)) {
2072                 ret = PTR_ERR(sport->clk_ipg);
2073                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2074                 return ret;
2075         }
2076
2077         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2078         if (IS_ERR(sport->clk_per)) {
2079                 ret = PTR_ERR(sport->clk_per);
2080                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2081                 return ret;
2082         }
2083
2084         sport->port.uartclk = clk_get_rate(sport->clk_per);
2085
2086         /* For register access, we only need to enable the ipg clock. */
2087         ret = clk_prepare_enable(sport->clk_ipg);
2088         if (ret) {
2089                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2090                 return ret;
2091         }
2092
2093         uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2094
2095         if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2096             (!sport->have_rtscts && !sport->have_rtsgpio))
2097                 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2098
2099         imx_rs485_config(&sport->port, &sport->port.rs485);
2100
2101         /* Disable interrupts before requesting them */
2102         reg = readl_relaxed(sport->port.membase + UCR1);
2103         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2104                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2105         writel_relaxed(reg, sport->port.membase + UCR1);
2106
2107         if (!is_imx1_uart(sport) && sport->dte_mode) {
2108                 /*
2109                  * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2110                  * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2111                  * and DCD (when they are outputs) or enables the respective
2112                  * irqs. So set this bit early, i.e. before requesting irqs.
2113                  */
2114                 reg = readl(sport->port.membase + UFCR);
2115                 if (!(reg & UFCR_DCEDTE))
2116                         writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
2117
2118                 /*
2119                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2120                  * enabled later because they cannot be cleared
2121                  * (confirmed on i.MX25) which makes them unusable.
2122                  */
2123                 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2124                        sport->port.membase + UCR3);
2125
2126         } else {
2127                 unsigned long ucr3 = UCR3_DSR;
2128
2129                 reg = readl(sport->port.membase + UFCR);
2130                 if (reg & UFCR_DCEDTE)
2131                         writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
2132
2133                 if (!is_imx1_uart(sport))
2134                         ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2135                 writel(ucr3, sport->port.membase + UCR3);
2136         }
2137
2138         clk_disable_unprepare(sport->clk_ipg);
2139
2140         /*
2141          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2142          * chips only have one interrupt.
2143          */
2144         if (txirq > 0) {
2145                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2146                                        dev_name(&pdev->dev), sport);
2147                 if (ret) {
2148                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2149                                 ret);
2150                         return ret;
2151                 }
2152
2153                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2154                                        dev_name(&pdev->dev), sport);
2155                 if (ret) {
2156                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2157                                 ret);
2158                         return ret;
2159                 }
2160         } else {
2161                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2162                                        dev_name(&pdev->dev), sport);
2163                 if (ret) {
2164                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2165                         return ret;
2166                 }
2167         }
2168
2169         imx_ports[sport->port.line] = sport;
2170
2171         platform_set_drvdata(pdev, sport);
2172
2173         return uart_add_one_port(&imx_reg, &sport->port);
2174 }
2175
2176 static int serial_imx_remove(struct platform_device *pdev)
2177 {
2178         struct imx_port *sport = platform_get_drvdata(pdev);
2179
2180         return uart_remove_one_port(&imx_reg, &sport->port);
2181 }
2182
2183 static void serial_imx_restore_context(struct imx_port *sport)
2184 {
2185         if (!sport->context_saved)
2186                 return;
2187
2188         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2189         writel(sport->saved_reg[5], sport->port.membase + UESC);
2190         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2191         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2192         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2193         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2194         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2195         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2196         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2197         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2198         sport->context_saved = false;
2199 }
2200
2201 static void serial_imx_save_context(struct imx_port *sport)
2202 {
2203         /* Save necessary regs */
2204         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2205         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2206         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2207         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2208         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2209         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2210         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2211         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2212         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2213         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2214         sport->context_saved = true;
2215 }
2216
2217 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2218 {
2219         unsigned int val;
2220
2221         val = readl(sport->port.membase + UCR3);
2222         if (on) {
2223                 writel(USR1_AWAKE, sport->port.membase + USR1);
2224                 val |= UCR3_AWAKEN;
2225         }
2226         else
2227                 val &= ~UCR3_AWAKEN;
2228         writel(val, sport->port.membase + UCR3);
2229
2230         if (sport->have_rtscts) {
2231                 val = readl(sport->port.membase + UCR1);
2232                 if (on)
2233                         val |= UCR1_RTSDEN;
2234                 else
2235                         val &= ~UCR1_RTSDEN;
2236                 writel(val, sport->port.membase + UCR1);
2237         }
2238 }
2239
2240 static int imx_serial_port_suspend_noirq(struct device *dev)
2241 {
2242         struct platform_device *pdev = to_platform_device(dev);
2243         struct imx_port *sport = platform_get_drvdata(pdev);
2244
2245         serial_imx_save_context(sport);
2246
2247         clk_disable(sport->clk_ipg);
2248
2249         return 0;
2250 }
2251
2252 static int imx_serial_port_resume_noirq(struct device *dev)
2253 {
2254         struct platform_device *pdev = to_platform_device(dev);
2255         struct imx_port *sport = platform_get_drvdata(pdev);
2256         int ret;
2257
2258         ret = clk_enable(sport->clk_ipg);
2259         if (ret)
2260                 return ret;
2261
2262         serial_imx_restore_context(sport);
2263
2264         return 0;
2265 }
2266
2267 static int imx_serial_port_suspend(struct device *dev)
2268 {
2269         struct platform_device *pdev = to_platform_device(dev);
2270         struct imx_port *sport = platform_get_drvdata(pdev);
2271         int ret;
2272
2273         uart_suspend_port(&imx_reg, &sport->port);
2274         disable_irq(sport->port.irq);
2275
2276         ret = clk_prepare_enable(sport->clk_ipg);
2277         if (ret)
2278                 return ret;
2279
2280         /* enable wakeup from i.MX UART */
2281         serial_imx_enable_wakeup(sport, true);
2282
2283         return 0;
2284 }
2285
2286 static int imx_serial_port_resume(struct device *dev)
2287 {
2288         struct platform_device *pdev = to_platform_device(dev);
2289         struct imx_port *sport = platform_get_drvdata(pdev);
2290
2291         /* disable wakeup from i.MX UART */
2292         serial_imx_enable_wakeup(sport, false);
2293
2294         uart_resume_port(&imx_reg, &sport->port);
2295         enable_irq(sport->port.irq);
2296
2297         clk_disable_unprepare(sport->clk_ipg);
2298
2299         return 0;
2300 }
2301
2302 static int imx_serial_port_freeze(struct device *dev)
2303 {
2304         struct platform_device *pdev = to_platform_device(dev);
2305         struct imx_port *sport = platform_get_drvdata(pdev);
2306
2307         uart_suspend_port(&imx_reg, &sport->port);
2308
2309         return clk_prepare_enable(sport->clk_ipg);
2310 }
2311
2312 static int imx_serial_port_thaw(struct device *dev)
2313 {
2314         struct platform_device *pdev = to_platform_device(dev);
2315         struct imx_port *sport = platform_get_drvdata(pdev);
2316
2317         uart_resume_port(&imx_reg, &sport->port);
2318
2319         clk_disable_unprepare(sport->clk_ipg);
2320
2321         return 0;
2322 }
2323
2324 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2325         .suspend_noirq = imx_serial_port_suspend_noirq,
2326         .resume_noirq = imx_serial_port_resume_noirq,
2327         .freeze_noirq = imx_serial_port_suspend_noirq,
2328         .restore_noirq = imx_serial_port_resume_noirq,
2329         .suspend = imx_serial_port_suspend,
2330         .resume = imx_serial_port_resume,
2331         .freeze = imx_serial_port_freeze,
2332         .thaw = imx_serial_port_thaw,
2333         .restore = imx_serial_port_thaw,
2334 };
2335
2336 static struct platform_driver serial_imx_driver = {
2337         .probe          = serial_imx_probe,
2338         .remove         = serial_imx_remove,
2339
2340         .id_table       = imx_uart_devtype,
2341         .driver         = {
2342                 .name   = "imx-uart",
2343                 .of_match_table = imx_uart_dt_ids,
2344                 .pm     = &imx_serial_port_pm_ops,
2345         },
2346 };
2347
2348 static int __init imx_serial_init(void)
2349 {
2350         int ret = uart_register_driver(&imx_reg);
2351
2352         if (ret)
2353                 return ret;
2354
2355         ret = platform_driver_register(&serial_imx_driver);
2356         if (ret != 0)
2357                 uart_unregister_driver(&imx_reg);
2358
2359         return ret;
2360 }
2361
2362 static void __exit imx_serial_exit(void)
2363 {
2364         platform_driver_unregister(&serial_imx_driver);
2365         uart_unregister_driver(&imx_reg);
2366 }
2367
2368 module_init(imx_serial_init);
2369 module_exit(imx_serial_exit);
2370
2371 MODULE_AUTHOR("Sascha Hauer");
2372 MODULE_DESCRIPTION("IMX generic serial port driver");
2373 MODULE_LICENSE("GPL");
2374 MODULE_ALIAS("platform:imx-uart");