drivers/tty/serial/lantiq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   4  *
   5  * Copyright (C) 2004 Infineon IFAP DC COM CPE
   6  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   7  * Copyright (C) 2007 John Crispin <john@phrozen.org>
   8  * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/console.h>
  13 #include <linux/device.h>
  14 #include <linux/gpio.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/lantiq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/serial.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/slab.h>
  25 #include <linux/sysrq.h>
  26 #include <linux/tty.h>
  27 #include <linux/tty_flip.h>
  28
  29 #define PORT_LTQ_ASC            111
  30 #define MAXPORTS                2
  31 #define UART_DUMMY_UER_RX       1
  32 #define DRVNAME                 "lantiq,asc"
  33 #ifdef __BIG_ENDIAN
  34 #define LTQ_ASC_TBUF            (0x0020 + 3)
  35 #define LTQ_ASC_RBUF            (0x0024 + 3)
  36 #else
  37 #define LTQ_ASC_TBUF            0x0020
  38 #define LTQ_ASC_RBUF            0x0024
  39 #endif
  40 #define LTQ_ASC_FSTAT           0x0048
  41 #define LTQ_ASC_WHBSTATE        0x0018
  42 #define LTQ_ASC_STATE           0x0014
  43 #define LTQ_ASC_IRNCR           0x00F8
  44 #define LTQ_ASC_CLC             0x0000
  45 #define LTQ_ASC_ID              0x0008
  46 #define LTQ_ASC_PISEL           0x0004
  47 #define LTQ_ASC_TXFCON          0x0044
  48 #define LTQ_ASC_RXFCON          0x0040
  49 #define LTQ_ASC_CON             0x0010
  50 #define LTQ_ASC_BG              0x0050
  51 #define LTQ_ASC_IRNREN          0x00F4
  52
  53 #define ASC_IRNREN_TX           0x1
  54 #define ASC_IRNREN_RX           0x2
  55 #define ASC_IRNREN_ERR          0x4
  56 #define ASC_IRNREN_TX_BUF       0x8
  57 #define ASC_IRNCR_TIR           0x1
  58 #define ASC_IRNCR_RIR           0x2
  59 #define ASC_IRNCR_EIR           0x4
  60
  61 #define ASCOPT_CSIZE            0x3
  62 #define TXFIFO_FL               1
  63 #define RXFIFO_FL               1
  64 #define ASCCLC_DISS             0x2
  65 #define ASCCLC_RMCMASK          0x0000FF00
  66 #define ASCCLC_RMCOFFSET        8
  67 #define ASCCON_M_8ASYNC         0x0
  68 #define ASCCON_M_7ASYNC         0x2
  69 #define ASCCON_ODD              0x00000020
  70 #define ASCCON_STP              0x00000080
  71 #define ASCCON_BRS              0x00000100
  72 #define ASCCON_FDE              0x00000200
  73 #define ASCCON_R                0x00008000
  74 #define ASCCON_FEN              0x00020000
  75 #define ASCCON_ROEN             0x00080000
  76 #define ASCCON_TOEN             0x00100000
  77 #define ASCSTATE_PE             0x00010000
  78 #define ASCSTATE_FE             0x00020000
  79 #define ASCSTATE_ROE            0x00080000
  80 #define ASCSTATE_ANY            (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
  81 #define ASCWHBSTATE_CLRREN      0x00000001
  82 #define ASCWHBSTATE_SETREN      0x00000002
  83 #define ASCWHBSTATE_CLRPE       0x00000004
  84 #define ASCWHBSTATE_CLRFE       0x00000008
  85 #define ASCWHBSTATE_CLRROE      0x00000020
  86 #define ASCTXFCON_TXFEN         0x0001
  87 #define ASCTXFCON_TXFFLU        0x0002
  88 #define ASCTXFCON_TXFITLMASK    0x3F00
  89 #define ASCTXFCON_TXFITLOFF     8
  90 #define ASCRXFCON_RXFEN         0x0001
  91 #define ASCRXFCON_RXFFLU        0x0002
  92 #define ASCRXFCON_RXFITLMASK    0x3F00
  93 #define ASCRXFCON_RXFITLOFF     8
  94 #define ASCFSTAT_RXFFLMASK      0x003F
  95 #define ASCFSTAT_TXFFLMASK      0x3F00
  96 #define ASCFSTAT_TXFREEMASK     0x3F000000
  97 #define ASCFSTAT_TXFREEOFF      24
  98
  99 static void lqasc_tx_chars(struct uart_port *port);
 100 static struct ltq_uart_port *lqasc_port[MAXPORTS];
 101 static struct uart_driver lqasc_reg;
 102 static DEFINE_SPINLOCK(ltq_asc_lock);
 103
 104 struct ltq_uart_port {
 105         struct uart_port        port;
 106         /* clock used to derive divider */
 107         struct clk              *freqclk;
 108         /* clock gating of the ASC core */
 109         struct clk              *clk;
 110         unsigned int            tx_irq;
 111         unsigned int            rx_irq;
 112         unsigned int            err_irq;
 113 };
 114
 115 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
 116 {
 117         u32 tmp = readl(reg);
 118
 119         writel((tmp & ~clear) | set, reg);
 120 }
 121
 122 static inline struct
 123 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
 124 {
 125         return container_of(port, struct ltq_uart_port, port);
 126 }
 127
 128 static void
 129 lqasc_stop_tx(struct uart_port *port)
 130 {
 131         return;
 132 }
 133
 134 static void
 135 lqasc_start_tx(struct uart_port *port)
 136 {
 137         unsigned long flags;
 138         spin_lock_irqsave(&ltq_asc_lock, flags);
 139         lqasc_tx_chars(port);
 140         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 141         return;
 142 }
 143
 144 static void
 145 lqasc_stop_rx(struct uart_port *port)
 146 {
 147         writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
 148 }
 149
 150 static int
 151 lqasc_rx_chars(struct uart_port *port)
 152 {
 153         struct tty_port *tport = &port->state->port;
 154         unsigned int ch = 0, rsr = 0, fifocnt;
 155
 156         fifocnt = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
 157         while (fifocnt--) {
 158                 u8 flag = TTY_NORMAL;
 159                 ch = readb(port->membase + LTQ_ASC_RBUF);
 160                 rsr = (readl(port->membase + LTQ_ASC_STATE)
 161                         & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
 162                 tty_flip_buffer_push(tport);
 163                 port->icount.rx++;
 164
 165                 /*
 166                  * Note that the error handling code is
 167                  * out of the main execution path
 168                  */
 169                 if (rsr & ASCSTATE_ANY) {
 170                         if (rsr & ASCSTATE_PE) {
 171                                 port->icount.parity++;
 172                                 asc_update_bits(0, ASCWHBSTATE_CLRPE,
 173                                         port->membase + LTQ_ASC_WHBSTATE);
 174                         } else if (rsr & ASCSTATE_FE) {
 175                                 port->icount.frame++;
 176                                 asc_update_bits(0, ASCWHBSTATE_CLRFE,
 177                                         port->membase + LTQ_ASC_WHBSTATE);
 178                         }
 179                         if (rsr & ASCSTATE_ROE) {
 180                                 port->icount.overrun++;
 181                                 asc_update_bits(0, ASCWHBSTATE_CLRROE,
 182                                         port->membase + LTQ_ASC_WHBSTATE);
 183                         }
 184
 185                         rsr &= port->read_status_mask;
 186
 187                         if (rsr & ASCSTATE_PE)
 188                                 flag = TTY_PARITY;
 189                         else if (rsr & ASCSTATE_FE)
 190                                 flag = TTY_FRAME;
 191                 }
 192
 193                 if ((rsr & port->ignore_status_mask) == 0)
 194                         tty_insert_flip_char(tport, ch, flag);
 195
 196                 if (rsr & ASCSTATE_ROE)
 197                         /*
 198                          * Overrun is special, since it's reported
 199                          * immediately, and doesn't affect the current
 200                          * character
 201                          */
 202                         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 203         }
 204
 205         if (ch != 0)
 206                 tty_flip_buffer_push(tport);
 207
 208         return 0;
 209 }
 210
 211 static void
 212 lqasc_tx_chars(struct uart_port *port)
 213 {
 214         struct circ_buf *xmit = &port->state->xmit;
 215         if (uart_tx_stopped(port)) {
 216                 lqasc_stop_tx(port);
 217                 return;
 218         }
 219
 220         while (((readl(port->membase + LTQ_ASC_FSTAT) &
 221                 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
 222                 if (port->x_char) {
 223                         writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
 224                         port->icount.tx++;
 225                         port->x_char = 0;
 226                         continue;
 227                 }
 228
 229                 if (uart_circ_empty(xmit))
 230                         break;
 231
 232                 writeb(port->state->xmit.buf[port->state->xmit.tail],
 233                         port->membase + LTQ_ASC_TBUF);
 234                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 235                 port->icount.tx++;
 236         }
 237
 238         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 239                 uart_write_wakeup(port);
 240 }
 241
 242 static irqreturn_t
 243 lqasc_tx_int(int irq, void *_port)
 244 {
 245         unsigned long flags;
 246         struct uart_port *port = (struct uart_port *)_port;
 247         spin_lock_irqsave(&ltq_asc_lock, flags);
 248         writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
 249         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 250         lqasc_start_tx(port);
 251         return IRQ_HANDLED;
 252 }
 253
 254 static irqreturn_t
 255 lqasc_err_int(int irq, void *_port)
 256 {
 257         unsigned long flags;
 258         struct uart_port *port = (struct uart_port *)_port;
 259         spin_lock_irqsave(&ltq_asc_lock, flags);
 260         /* clear any pending interrupts */
 261         asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
 262                 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
 263         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 264         return IRQ_HANDLED;
 265 }
 266
 267 static irqreturn_t
 268 lqasc_rx_int(int irq, void *_port)
 269 {
 270         unsigned long flags;
 271         struct uart_port *port = (struct uart_port *)_port;
 272         spin_lock_irqsave(&ltq_asc_lock, flags);
 273         writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
 274         lqasc_rx_chars(port);
 275         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 276         return IRQ_HANDLED;
 277 }
 278
 279 static unsigned int
 280 lqasc_tx_empty(struct uart_port *port)
 281 {
 282         int status;
 283         status = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
 284         return status ? 0 : TIOCSER_TEMT;
 285 }
 286
 287 static unsigned int
 288 lqasc_get_mctrl(struct uart_port *port)
 289 {
 290         return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
 291 }
 292
 293 static void
 294 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
 295 {
 296 }
 297
 298 static void
 299 lqasc_break_ctl(struct uart_port *port, int break_state)
 300 {
 301 }
 302
 303 static int
 304 lqasc_startup(struct uart_port *port)
 305 {
 306         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 307         int retval;
 308
 309         if (!IS_ERR(ltq_port->clk))
 310                 clk_prepare_enable(ltq_port->clk);
 311         port->uartclk = clk_get_rate(ltq_port->freqclk);
 312
 313         asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
 314                 port->membase + LTQ_ASC_CLC);
 315
 316         writel(0, port->membase + LTQ_ASC_PISEL);
 317         writel(
 318                 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
 319                 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
 320                 port->membase + LTQ_ASC_TXFCON);
 321         writel(
 322                 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
 323                 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
 324                 port->membase + LTQ_ASC_RXFCON);
 325         /* make sure other settings are written to hardware before
 326          * setting enable bits
 327          */
 328         wmb();
 329         asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
 330                 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
 331
 332         retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
 333                 0, "asc_tx", port);
 334         if (retval) {
 335                 pr_err("failed to request lqasc_tx_int\n");
 336                 return retval;
 337         }
 338
 339         retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
 340                 0, "asc_rx", port);
 341         if (retval) {
 342                 pr_err("failed to request lqasc_rx_int\n");
 343                 goto err1;
 344         }
 345
 346         retval = request_irq(ltq_port->err_irq, lqasc_err_int,
 347                 0, "asc_err", port);
 348         if (retval) {
 349                 pr_err("failed to request lqasc_err_int\n");
 350                 goto err2;
 351         }
 352
 353         writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
 354                 port->membase + LTQ_ASC_IRNREN);
 355         return 0;
 356
 357 err2:
 358         free_irq(ltq_port->rx_irq, port);
 359 err1:
 360         free_irq(ltq_port->tx_irq, port);
 361         return retval;
 362 }
 363
 364 static void
 365 lqasc_shutdown(struct uart_port *port)
 366 {
 367         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 368         free_irq(ltq_port->tx_irq, port);
 369         free_irq(ltq_port->rx_irq, port);
 370         free_irq(ltq_port->err_irq, port);
 371
 372         writel(0, port->membase + LTQ_ASC_CON);
 373         asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
 374                 port->membase + LTQ_ASC_RXFCON);
 375         asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
 376                 port->membase + LTQ_ASC_TXFCON);
 377         if (!IS_ERR(ltq_port->clk))
 378                 clk_disable_unprepare(ltq_port->clk);
 379 }
 380
 381 static void
 382 lqasc_set_termios(struct uart_port *port,
 383         struct ktermios *new, struct ktermios *old)
 384 {
 385         unsigned int cflag;
 386         unsigned int iflag;
 387         unsigned int divisor;
 388         unsigned int baud;
 389         unsigned int con = 0;
 390         unsigned long flags;
 391
 392         cflag = new->c_cflag;
 393         iflag = new->c_iflag;
 394
 395         switch (cflag & CSIZE) {
 396         case CS7:
 397                 con = ASCCON_M_7ASYNC;
 398                 break;
 399
 400         case CS5:
 401         case CS6:
 402         default:
 403                 new->c_cflag &= ~ CSIZE;
 404                 new->c_cflag |= CS8;
 405                 con = ASCCON_M_8ASYNC;
 406                 break;
 407         }
 408
 409         cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
 410
 411         if (cflag & CSTOPB)
 412                 con |= ASCCON_STP;
 413
 414         if (cflag & PARENB) {
 415                 if (!(cflag & PARODD))
 416                         con &= ~ASCCON_ODD;
 417                 else
 418                         con |= ASCCON_ODD;
 419         }
 420
 421         port->read_status_mask = ASCSTATE_ROE;
 422         if (iflag & INPCK)
 423                 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 424
 425         port->ignore_status_mask = 0;
 426         if (iflag & IGNPAR)
 427                 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 428
 429         if (iflag & IGNBRK) {
 430                 /*
 431                  * If we're ignoring parity and break indicators,
 432                  * ignore overruns too (for real raw support).
 433                  */
 434                 if (iflag & IGNPAR)
 435                         port->ignore_status_mask |= ASCSTATE_ROE;
 436         }
 437
 438         if ((cflag & CREAD) == 0)
 439                 port->ignore_status_mask |= UART_DUMMY_UER_RX;
 440
 441         /* set error signals  - framing, parity  and overrun, enable receiver */
 442         con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
 443
 444         spin_lock_irqsave(&ltq_asc_lock, flags);
 445
 446         /* set up CON */
 447         asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
 448
 449         /* Set baud rate - take a divider of 2 into account */
 450         baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
 451         divisor = uart_get_divisor(port, baud);
 452         divisor = divisor / 2 - 1;
 453
 454         /* disable the baudrate generator */
 455         asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
 456
 457         /* make sure the fractional divider is off */
 458         asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
 459
 460         /* set up to use divisor of 2 */
 461         asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
 462
 463         /* now we can write the new baudrate into the register */
 464         writel(divisor, port->membase + LTQ_ASC_BG);
 465
 466         /* turn the baudrate generator back on */
 467         asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
 468
 469         /* enable rx */
 470         writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
 471
 472         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 473
 474         /* Don't rewrite B0 */
 475         if (tty_termios_baud_rate(new))
 476                 tty_termios_encode_baud_rate(new, baud, baud);
 477
 478         uart_update_timeout(port, cflag, baud);
 479 }
 480
 481 static const char*
 482 lqasc_type(struct uart_port *port)
 483 {
 484         if (port->type == PORT_LTQ_ASC)
 485                 return DRVNAME;
 486         else
 487                 return NULL;
 488 }
 489
 490 static void
 491 lqasc_release_port(struct uart_port *port)
 492 {
 493         struct platform_device *pdev = to_platform_device(port->dev);
 494
 495         if (port->flags & UPF_IOREMAP) {
 496                 devm_iounmap(&pdev->dev, port->membase);
 497                 port->membase = NULL;
 498         }
 499 }
 500
 501 static int
 502 lqasc_request_port(struct uart_port *port)
 503 {
 504         struct platform_device *pdev = to_platform_device(port->dev);
 505         struct resource *res;
 506         int size;
 507
 508         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 509         if (!res) {
 510                 dev_err(&pdev->dev, "cannot obtain I/O memory region");
 511                 return -ENODEV;
 512         }
 513         size = resource_size(res);
 514
 515         res = devm_request_mem_region(&pdev->dev, res->start,
 516                 size, dev_name(&pdev->dev));
 517         if (!res) {
 518                 dev_err(&pdev->dev, "cannot request I/O memory region");
 519                 return -EBUSY;
 520         }
 521
 522         if (port->flags & UPF_IOREMAP) {
 523                 port->membase = devm_ioremap_nocache(&pdev->dev,
 524                         port->mapbase, size);
 525                 if (port->membase == NULL)
 526                         return -ENOMEM;
 527         }
 528         return 0;
 529 }
 530
 531 static void
 532 lqasc_config_port(struct uart_port *port, int flags)
 533 {
 534         if (flags & UART_CONFIG_TYPE) {
 535                 port->type = PORT_LTQ_ASC;
 536                 lqasc_request_port(port);
 537         }
 538 }
 539
 540 static int
 541 lqasc_verify_port(struct uart_port *port,
 542         struct serial_struct *ser)
 543 {
 544         int ret = 0;
 545         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
 546                 ret = -EINVAL;
 547         if (ser->irq < 0 || ser->irq >= NR_IRQS)
 548                 ret = -EINVAL;
 549         if (ser->baud_base < 9600)
 550                 ret = -EINVAL;
 551         return ret;
 552 }
 553
 554 static const struct uart_ops lqasc_pops = {
 555         .tx_empty =     lqasc_tx_empty,
 556         .set_mctrl =    lqasc_set_mctrl,
 557         .get_mctrl =    lqasc_get_mctrl,
 558         .stop_tx =      lqasc_stop_tx,
 559         .start_tx =     lqasc_start_tx,
 560         .stop_rx =      lqasc_stop_rx,
 561         .break_ctl =    lqasc_break_ctl,
 562         .startup =      lqasc_startup,
 563         .shutdown =     lqasc_shutdown,
 564         .set_termios =  lqasc_set_termios,
 565         .type =         lqasc_type,
 566         .release_port = lqasc_release_port,
 567         .request_port = lqasc_request_port,
 568         .config_port =  lqasc_config_port,
 569         .verify_port =  lqasc_verify_port,
 570 };
 571
 572 static void
 573 lqasc_console_putchar(struct uart_port *port, int ch)
 574 {
 575         int fifofree;
 576
 577         if (!port->membase)
 578                 return;
 579
 580         do {
 581                 fifofree = (readl(port->membase + LTQ_ASC_FSTAT)
 582                         & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
 583         } while (fifofree == 0);
 584         writeb(ch, port->membase + LTQ_ASC_TBUF);
 585 }
 586
 587 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
 588                                     u_int count)
 589 {
 590         unsigned long flags;
 591
 592         spin_lock_irqsave(&ltq_asc_lock, flags);
 593         uart_console_write(port, s, count, lqasc_console_putchar);
 594         spin_unlock_irqrestore(&ltq_asc_lock, flags);
 595 }
 596
 597 static void
 598 lqasc_console_write(struct console *co, const char *s, u_int count)
 599 {
 600         struct ltq_uart_port *ltq_port;
 601
 602         if (co->index >= MAXPORTS)
 603                 return;
 604
 605         ltq_port = lqasc_port[co->index];
 606         if (!ltq_port)
 607                 return;
 608
 609         lqasc_serial_port_write(&ltq_port->port, s, count);
 610 }
 611
 612 static int __init
 613 lqasc_console_setup(struct console *co, char *options)
 614 {
 615         struct ltq_uart_port *ltq_port;
 616         struct uart_port *port;
 617         int baud = 115200;
 618         int bits = 8;
 619         int parity = 'n';
 620         int flow = 'n';
 621
 622         if (co->index >= MAXPORTS)
 623                 return -ENODEV;
 624
 625         ltq_port = lqasc_port[co->index];
 626         if (!ltq_port)
 627                 return -ENODEV;
 628
 629         port = &ltq_port->port;
 630
 631         if (!IS_ERR(ltq_port->clk))
 632                 clk_prepare_enable(ltq_port->clk);
 633
 634         port->uartclk = clk_get_rate(ltq_port->freqclk);
 635
 636         if (options)
 637                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 638         return uart_set_options(port, co, baud, parity, bits, flow);
 639 }
 640
 641 static struct console lqasc_console = {
 642         .name =         "ttyLTQ",
 643         .write =        lqasc_console_write,
 644         .device =       uart_console_device,
 645         .setup =        lqasc_console_setup,
 646         .flags =        CON_PRINTBUFFER,
 647         .index =        -1,
 648         .data =         &lqasc_reg,
 649 };
 650
 651 static int __init
 652 lqasc_console_init(void)
 653 {
 654         register_console(&lqasc_console);
 655         return 0;
 656 }
 657 console_initcall(lqasc_console_init);
 658
 659 static void lqasc_serial_early_console_write(struct console *co,
 660                                              const char *s,
 661                                              u_int count)
 662 {
 663         struct earlycon_device *dev = co->data;
 664
 665         lqasc_serial_port_write(&dev->port, s, count);
 666 }
 667
 668 static int __init
 669 lqasc_serial_early_console_setup(struct earlycon_device *device,
 670                                  const char *opt)
 671 {
 672         if (!device->port.membase)
 673                 return -ENODEV;
 674
 675         device->con->write = lqasc_serial_early_console_write;
 676         return 0;
 677 }
 678 OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
 679
 680 static struct uart_driver lqasc_reg = {
 681         .owner =        THIS_MODULE,
 682         .driver_name =  DRVNAME,
 683         .dev_name =     "ttyLTQ",
 684         .major =        0,
 685         .minor =        0,
 686         .nr =           MAXPORTS,
 687         .cons =         &lqasc_console,
 688 };
 689
 690 static int __init
 691 lqasc_probe(struct platform_device *pdev)
 692 {
 693         struct device_node *node = pdev->dev.of_node;
 694         struct ltq_uart_port *ltq_port;
 695         struct uart_port *port;
 696         struct resource *mmres, irqres[3];
 697         int line;
 698         int ret;
 699
 700         mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 701         ret = of_irq_to_resource_table(node, irqres, 3);
 702         if (!mmres || (ret != 3)) {
 703                 dev_err(&pdev->dev,
 704                         "failed to get memory/irq for serial port\n");
 705                 return -ENODEV;
 706         }
 707
 708         /* get serial id */
 709         line = of_alias_get_id(node, "serial");
 710         if (line < 0) {
 711                 if (IS_ENABLED(CONFIG_LANTIQ)) {
 712                         if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
 713                                 line = 0;
 714                         else
 715                                 line = 1;
 716                 } else {
 717                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
 718                                 line);
 719                         return line;
 720                 }
 721         }
 722
 723         if (lqasc_port[line]) {
 724                 dev_err(&pdev->dev, "port %d already allocated\n", line);
 725                 return -EBUSY;
 726         }
 727
 728         ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
 729                         GFP_KERNEL);
 730         if (!ltq_port)
 731                 return -ENOMEM;
 732
 733         port = &ltq_port->port;
 734
 735         port->iotype    = SERIAL_IO_MEM;
 736         port->flags     = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
 737         port->ops       = &lqasc_pops;
 738         port->fifosize  = 16;
 739         port->type      = PORT_LTQ_ASC,
 740         port->line      = line;
 741         port->dev       = &pdev->dev;
 742         /* unused, just to be backward-compatible */
 743         port->irq       = irqres[0].start;
 744         port->mapbase   = mmres->start;
 745
 746         if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
 747                 ltq_port->freqclk = clk_get_fpi();
 748         else
 749                 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
 750
 751
 752         if (IS_ERR(ltq_port->freqclk)) {
 753                 pr_err("failed to get fpi clk\n");
 754                 return -ENOENT;
 755         }
 756
 757         /* not all asc ports have clock gates, lets ignore the return code */
 758         if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
 759                 ltq_port->clk = clk_get(&pdev->dev, NULL);
 760         else
 761                 ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
 762
 763         ltq_port->tx_irq = irqres[0].start;
 764         ltq_port->rx_irq = irqres[1].start;
 765         ltq_port->err_irq = irqres[2].start;
 766
 767         lqasc_port[line] = ltq_port;
 768         platform_set_drvdata(pdev, ltq_port);
 769
 770         ret = uart_add_one_port(&lqasc_reg, port);
 771
 772         return ret;
 773 }
 774
 775 static const struct of_device_id ltq_asc_match[] = {
 776         { .compatible = DRVNAME },
 777         {},
 778 };
 779
 780 static struct platform_driver lqasc_driver = {
 781         .driver         = {
 782                 .name   = DRVNAME,
 783                 .of_match_table = ltq_asc_match,
 784         },
 785 };
 786
 787 static int __init
 788 init_lqasc(void)
 789 {
 790         int ret;
 791
 792         ret = uart_register_driver(&lqasc_reg);
 793         if (ret != 0)
 794                 return ret;
 795
 796         ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
 797         if (ret != 0)
 798                 uart_unregister_driver(&lqasc_reg);
 799
 800         return ret;
 801 }
 802 device_initcall(init_lqasc);