drivers/tty/serial/msm_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for msm7k serial device and console
   4  *
   5  * Copyright (C) 2007 Google, Inc.
   6  * Author: Robert Love <rlove@google.com>
   7  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/atomic.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/module.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/console.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/wait.h>
  30
  31 #define UART_MR1                        0x0000
  32
  33 #define UART_MR1_AUTO_RFR_LEVEL0        0x3F
  34 #define UART_MR1_AUTO_RFR_LEVEL1        0x3FF00
  35 #define UART_DM_MR1_AUTO_RFR_LEVEL1     0xFFFFFF00
  36 #define UART_MR1_RX_RDY_CTL             BIT(7)
  37 #define UART_MR1_CTS_CTL                BIT(6)
  38
  39 #define UART_MR2                        0x0004
  40 #define UART_MR2_ERROR_MODE             BIT(6)
  41 #define UART_MR2_BITS_PER_CHAR          0x30
  42 #define UART_MR2_BITS_PER_CHAR_5        (0x0 << 4)
  43 #define UART_MR2_BITS_PER_CHAR_6        (0x1 << 4)
  44 #define UART_MR2_BITS_PER_CHAR_7        (0x2 << 4)
  45 #define UART_MR2_BITS_PER_CHAR_8        (0x3 << 4)
  46 #define UART_MR2_STOP_BIT_LEN_ONE       (0x1 << 2)
  47 #define UART_MR2_STOP_BIT_LEN_TWO       (0x3 << 2)
  48 #define UART_MR2_PARITY_MODE_NONE       0x0
  49 #define UART_MR2_PARITY_MODE_ODD        0x1
  50 #define UART_MR2_PARITY_MODE_EVEN       0x2
  51 #define UART_MR2_PARITY_MODE_SPACE      0x3
  52 #define UART_MR2_PARITY_MODE            0x3
  53
  54 #define UART_CSR                        0x0008
  55
  56 #define UART_TF                         0x000C
  57 #define UARTDM_TF                       0x0070
  58
  59 #define UART_CR                         0x0010
  60 #define UART_CR_CMD_NULL                (0 << 4)
  61 #define UART_CR_CMD_RESET_RX            (1 << 4)
  62 #define UART_CR_CMD_RESET_TX            (2 << 4)
  63 #define UART_CR_CMD_RESET_ERR           (3 << 4)
  64 #define UART_CR_CMD_RESET_BREAK_INT     (4 << 4)
  65 #define UART_CR_CMD_START_BREAK         (5 << 4)
  66 #define UART_CR_CMD_STOP_BREAK          (6 << 4)
  67 #define UART_CR_CMD_RESET_CTS           (7 << 4)
  68 #define UART_CR_CMD_RESET_STALE_INT     (8 << 4)
  69 #define UART_CR_CMD_PACKET_MODE         (9 << 4)
  70 #define UART_CR_CMD_MODE_RESET          (12 << 4)
  71 #define UART_CR_CMD_SET_RFR             (13 << 4)
  72 #define UART_CR_CMD_RESET_RFR           (14 << 4)
  73 #define UART_CR_CMD_PROTECTION_EN       (16 << 4)
  74 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
  75 #define UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
  76 #define UART_CR_CMD_FORCE_STALE         (4 << 8)
  77 #define UART_CR_CMD_RESET_TX_READY      (3 << 8)
  78 #define UART_CR_TX_DISABLE              BIT(3)
  79 #define UART_CR_TX_ENABLE               BIT(2)
  80 #define UART_CR_RX_DISABLE              BIT(1)
  81 #define UART_CR_RX_ENABLE               BIT(0)
  82 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
  83
  84 #define UART_IMR                        0x0014
  85 #define UART_IMR_TXLEV                  BIT(0)
  86 #define UART_IMR_RXSTALE                BIT(3)
  87 #define UART_IMR_RXLEV                  BIT(4)
  88 #define UART_IMR_DELTA_CTS              BIT(5)
  89 #define UART_IMR_CURRENT_CTS            BIT(6)
  90 #define UART_IMR_RXBREAK_START          BIT(10)
  91
  92 #define UART_IPR_RXSTALE_LAST           0x20
  93 #define UART_IPR_STALE_LSB              0x1F
  94 #define UART_IPR_STALE_TIMEOUT_MSB      0x3FF80
  95 #define UART_DM_IPR_STALE_TIMEOUT_MSB   0xFFFFFF80
  96
  97 #define UART_IPR                        0x0018
  98 #define UART_TFWR                       0x001C
  99 #define UART_RFWR                       0x0020
 100 #define UART_HCR                        0x0024
 101
 102 #define UART_MREG                       0x0028
 103 #define UART_NREG                       0x002C
 104 #define UART_DREG                       0x0030
 105 #define UART_MNDREG                     0x0034
 106 #define UART_IRDA                       0x0038
 107 #define UART_MISR_MODE                  0x0040
 108 #define UART_MISR_RESET                 0x0044
 109 #define UART_MISR_EXPORT                0x0048
 110 #define UART_MISR_VAL                   0x004C
 111 #define UART_TEST_CTRL                  0x0050
 112
 113 #define UART_SR                         0x0008
 114 #define UART_SR_HUNT_CHAR               BIT(7)
 115 #define UART_SR_RX_BREAK                BIT(6)
 116 #define UART_SR_PAR_FRAME_ERR           BIT(5)
 117 #define UART_SR_OVERRUN                 BIT(4)
 118 #define UART_SR_TX_EMPTY                BIT(3)
 119 #define UART_SR_TX_READY                BIT(2)
 120 #define UART_SR_RX_FULL                 BIT(1)
 121 #define UART_SR_RX_READY                BIT(0)
 122
 123 #define UART_RF                         0x000C
 124 #define UARTDM_RF                       0x0070
 125 #define UART_MISR                       0x0010
 126 #define UART_ISR                        0x0014
 127 #define UART_ISR_TX_READY               BIT(7)
 128
 129 #define UARTDM_RXFS                     0x50
 130 #define UARTDM_RXFS_BUF_SHIFT           0x7
 131 #define UARTDM_RXFS_BUF_MASK            0x7
 132
 133 #define UARTDM_DMEN                     0x3C
 134 #define UARTDM_DMEN_RX_SC_ENABLE        BIT(5)
 135 #define UARTDM_DMEN_TX_SC_ENABLE        BIT(4)
 136
 137 #define UARTDM_DMEN_TX_BAM_ENABLE       BIT(2)  /* UARTDM_1P4 */
 138 #define UARTDM_DMEN_TX_DM_ENABLE        BIT(0)  /* < UARTDM_1P4 */
 139
 140 #define UARTDM_DMEN_RX_BAM_ENABLE       BIT(3)  /* UARTDM_1P4 */
 141 #define UARTDM_DMEN_RX_DM_ENABLE        BIT(1)  /* < UARTDM_1P4 */
 142
 143 #define UARTDM_DMRX                     0x34
 144 #define UARTDM_NCF_TX                   0x40
 145 #define UARTDM_RX_TOTAL_SNAP            0x38
 146
 147 #define UARTDM_BURST_SIZE               16   /* in bytes */
 148 #define UARTDM_TX_AIGN(x)               ((x) & ~0x3) /* valid for > 1p3 */
 149 #define UARTDM_TX_MAX                   256   /* in bytes, valid for <= 1p3 */
 150 #define UARTDM_RX_SIZE                  (UART_XMIT_SIZE / 4)
 151
 152 enum {
 153         UARTDM_1P1 = 1,
 154         UARTDM_1P2,
 155         UARTDM_1P3,
 156         UARTDM_1P4,
 157 };
 158
 159 struct msm_dma {
 160         struct dma_chan         *chan;
 161         enum dma_data_direction dir;
 162         dma_addr_t              phys;
 163         unsigned char           *virt;
 164         dma_cookie_t            cookie;
 165         u32                     enable_bit;
 166         unsigned int            count;
 167         struct dma_async_tx_descriptor  *desc;
 168 };
 169
 170 struct msm_port {
 171         struct uart_port        uart;
 172         char                    name[16];
 173         struct clk              *clk;
 174         struct clk              *pclk;
 175         unsigned int            imr;
 176         int                     is_uartdm;
 177         unsigned int            old_snap_state;
 178         bool                    break_detected;
 179         struct msm_dma          tx_dma;
 180         struct msm_dma          rx_dma;
 181 };
 182
 183 #define UART_TO_MSM(uart_port)  container_of(uart_port, struct msm_port, uart)
 184
 185 static
 186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
 187 {
 188         writel_relaxed(val, port->membase + off);
 189 }
 190
 191 static
 192 unsigned int msm_read(struct uart_port *port, unsigned int off)
 193 {
 194         return readl_relaxed(port->membase + off);
 195 }
 196
 197 /*
 198  * Setup the MND registers to use the TCXO clock.
 199  */
 200 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
 201 {
 202         msm_write(port, 0x06, UART_MREG);
 203         msm_write(port, 0xF1, UART_NREG);
 204         msm_write(port, 0x0F, UART_DREG);
 205         msm_write(port, 0x1A, UART_MNDREG);
 206         port->uartclk = 1843200;
 207 }
 208
 209 /*
 210  * Setup the MND registers to use the TCXO clock divided by 4.
 211  */
 212 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
 213 {
 214         msm_write(port, 0x18, UART_MREG);
 215         msm_write(port, 0xF6, UART_NREG);
 216         msm_write(port, 0x0F, UART_DREG);
 217         msm_write(port, 0x0A, UART_MNDREG);
 218         port->uartclk = 1843200;
 219 }
 220
 221 static void msm_serial_set_mnd_regs(struct uart_port *port)
 222 {
 223         struct msm_port *msm_port = UART_TO_MSM(port);
 224
 225         /*
 226          * These registers don't exist so we change the clk input rate
 227          * on uartdm hardware instead
 228          */
 229         if (msm_port->is_uartdm)
 230                 return;
 231
 232         if (port->uartclk == 19200000)
 233                 msm_serial_set_mnd_regs_tcxo(port);
 234         else if (port->uartclk == 4800000)
 235                 msm_serial_set_mnd_regs_tcxoby4(port);
 236 }
 237
 238 static void msm_handle_tx(struct uart_port *port);
 239 static void msm_start_rx_dma(struct msm_port *msm_port);
 240
 241 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 242 {
 243         struct device *dev = port->dev;
 244         unsigned int mapped;
 245         u32 val;
 246
 247         mapped = dma->count;
 248         dma->count = 0;
 249
 250         dmaengine_terminate_all(dma->chan);
 251
 252         /*
 253          * DMA Stall happens if enqueue and flush command happens concurrently.
 254          * For example before changing the baud rate/protocol configuration and
 255          * sending flush command to ADM, disable the channel of UARTDM.
 256          * Note: should not reset the receiver here immediately as it is not
 257          * suggested to do disable/reset or reset/disable at the same time.
 258          */
 259         val = msm_read(port, UARTDM_DMEN);
 260         val &= ~dma->enable_bit;
 261         msm_write(port, val, UARTDM_DMEN);
 262
 263         if (mapped)
 264                 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
 265 }
 266
 267 static void msm_release_dma(struct msm_port *msm_port)
 268 {
 269         struct msm_dma *dma;
 270
 271         dma = &msm_port->tx_dma;
 272         if (dma->chan) {
 273                 msm_stop_dma(&msm_port->uart, dma);
 274                 dma_release_channel(dma->chan);
 275         }
 276
 277         memset(dma, 0, sizeof(*dma));
 278
 279         dma = &msm_port->rx_dma;
 280         if (dma->chan) {
 281                 msm_stop_dma(&msm_port->uart, dma);
 282                 dma_release_channel(dma->chan);
 283                 kfree(dma->virt);
 284         }
 285
 286         memset(dma, 0, sizeof(*dma));
 287 }
 288
 289 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
 290 {
 291         struct device *dev = msm_port->uart.dev;
 292         struct dma_slave_config conf;
 293         struct msm_dma *dma;
 294         u32 crci = 0;
 295         int ret;
 296
 297         dma = &msm_port->tx_dma;
 298
 299         /* allocate DMA resources, if available */
 300         dma->chan = dma_request_chan(dev, "tx");
 301         if (IS_ERR(dma->chan))
 302                 goto no_tx;
 303
 304         of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
 305
 306         memset(&conf, 0, sizeof(conf));
 307         conf.direction = DMA_MEM_TO_DEV;
 308         conf.device_fc = true;
 309         conf.dst_addr = base + UARTDM_TF;
 310         conf.dst_maxburst = UARTDM_BURST_SIZE;
 311         conf.slave_id = crci;
 312
 313         ret = dmaengine_slave_config(dma->chan, &conf);
 314         if (ret)
 315                 goto rel_tx;
 316
 317         dma->dir = DMA_TO_DEVICE;
 318
 319         if (msm_port->is_uartdm < UARTDM_1P4)
 320                 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
 321         else
 322                 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
 323
 324         return;
 325
 326 rel_tx:
 327         dma_release_channel(dma->chan);
 328 no_tx:
 329         memset(dma, 0, sizeof(*dma));
 330 }
 331
 332 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
 333 {
 334         struct device *dev = msm_port->uart.dev;
 335         struct dma_slave_config conf;
 336         struct msm_dma *dma;
 337         u32 crci = 0;
 338         int ret;
 339
 340         dma = &msm_port->rx_dma;
 341
 342         /* allocate DMA resources, if available */
 343         dma->chan = dma_request_chan(dev, "rx");
 344         if (IS_ERR(dma->chan))
 345                 goto no_rx;
 346
 347         of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
 348
 349         dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
 350         if (!dma->virt)
 351                 goto rel_rx;
 352
 353         memset(&conf, 0, sizeof(conf));
 354         conf.direction = DMA_DEV_TO_MEM;
 355         conf.device_fc = true;
 356         conf.src_addr = base + UARTDM_RF;
 357         conf.src_maxburst = UARTDM_BURST_SIZE;
 358         conf.slave_id = crci;
 359
 360         ret = dmaengine_slave_config(dma->chan, &conf);
 361         if (ret)
 362                 goto err;
 363
 364         dma->dir = DMA_FROM_DEVICE;
 365
 366         if (msm_port->is_uartdm < UARTDM_1P4)
 367                 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
 368         else
 369                 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
 370
 371         return;
 372 err:
 373         kfree(dma->virt);
 374 rel_rx:
 375         dma_release_channel(dma->chan);
 376 no_rx:
 377         memset(dma, 0, sizeof(*dma));
 378 }
 379
 380 static inline void msm_wait_for_xmitr(struct uart_port *port)
 381 {
 382         unsigned int timeout = 500000;
 383
 384         while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
 385                 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
 386                         break;
 387                 udelay(1);
 388                 if (!timeout--)
 389                         break;
 390         }
 391         msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
 392 }
 393
 394 static void msm_stop_tx(struct uart_port *port)
 395 {
 396         struct msm_port *msm_port = UART_TO_MSM(port);
 397
 398         msm_port->imr &= ~UART_IMR_TXLEV;
 399         msm_write(port, msm_port->imr, UART_IMR);
 400 }
 401
 402 static void msm_start_tx(struct uart_port *port)
 403 {
 404         struct msm_port *msm_port = UART_TO_MSM(port);
 405         struct msm_dma *dma = &msm_port->tx_dma;
 406
 407         /* Already started in DMA mode */
 408         if (dma->count)
 409                 return;
 410
 411         msm_port->imr |= UART_IMR_TXLEV;
 412         msm_write(port, msm_port->imr, UART_IMR);
 413 }
 414
 415 static void msm_reset_dm_count(struct uart_port *port, int count)
 416 {
 417         msm_wait_for_xmitr(port);
 418         msm_write(port, count, UARTDM_NCF_TX);
 419         msm_read(port, UARTDM_NCF_TX);
 420 }
 421
 422 static void msm_complete_tx_dma(void *args)
 423 {
 424         struct msm_port *msm_port = args;
 425         struct uart_port *port = &msm_port->uart;
 426         struct circ_buf *xmit = &port->state->xmit;
 427         struct msm_dma *dma = &msm_port->tx_dma;
 428         struct dma_tx_state state;
 429         enum dma_status status;
 430         unsigned long flags;
 431         unsigned int count;
 432         u32 val;
 433
 434         spin_lock_irqsave(&port->lock, flags);
 435
 436         /* Already stopped */
 437         if (!dma->count)
 438                 goto done;
 439
 440         status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
 441
 442         dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
 443
 444         val = msm_read(port, UARTDM_DMEN);
 445         val &= ~dma->enable_bit;
 446         msm_write(port, val, UARTDM_DMEN);
 447
 448         if (msm_port->is_uartdm > UARTDM_1P3) {
 449                 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
 450                 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
 451         }
 452
 453         count = dma->count - state.residue;
 454         port->icount.tx += count;
 455         dma->count = 0;
 456
 457         xmit->tail += count;
 458         xmit->tail &= UART_XMIT_SIZE - 1;
 459
 460         /* Restore "Tx FIFO below watermark" interrupt */
 461         msm_port->imr |= UART_IMR_TXLEV;
 462         msm_write(port, msm_port->imr, UART_IMR);
 463
 464         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 465                 uart_write_wakeup(port);
 466
 467         msm_handle_tx(port);
 468 done:
 469         spin_unlock_irqrestore(&port->lock, flags);
 470 }
 471
 472 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
 473 {
 474         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 475         struct uart_port *port = &msm_port->uart;
 476         struct msm_dma *dma = &msm_port->tx_dma;
 477         void *cpu_addr;
 478         int ret;
 479         u32 val;
 480
 481         cpu_addr = &xmit->buf[xmit->tail];
 482
 483         dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
 484         ret = dma_mapping_error(port->dev, dma->phys);
 485         if (ret)
 486                 return ret;
 487
 488         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 489                                                 count, DMA_MEM_TO_DEV,
 490                                                 DMA_PREP_INTERRUPT |
 491                                                 DMA_PREP_FENCE);
 492         if (!dma->desc) {
 493                 ret = -EIO;
 494                 goto unmap;
 495         }
 496
 497         dma->desc->callback = msm_complete_tx_dma;
 498         dma->desc->callback_param = msm_port;
 499
 500         dma->cookie = dmaengine_submit(dma->desc);
 501         ret = dma_submit_error(dma->cookie);
 502         if (ret)
 503                 goto unmap;
 504
 505         /*
 506          * Using DMA complete for Tx FIFO reload, no need for
 507          * "Tx FIFO below watermark" one, disable it
 508          */
 509         msm_port->imr &= ~UART_IMR_TXLEV;
 510         msm_write(port, msm_port->imr, UART_IMR);
 511
 512         dma->count = count;
 513
 514         val = msm_read(port, UARTDM_DMEN);
 515         val |= dma->enable_bit;
 516
 517         if (msm_port->is_uartdm < UARTDM_1P4)
 518                 msm_write(port, val, UARTDM_DMEN);
 519
 520         msm_reset_dm_count(port, count);
 521
 522         if (msm_port->is_uartdm > UARTDM_1P3)
 523                 msm_write(port, val, UARTDM_DMEN);
 524
 525         dma_async_issue_pending(dma->chan);
 526         return 0;
 527 unmap:
 528         dma_unmap_single(port->dev, dma->phys, count, dma->dir);
 529         return ret;
 530 }
 531
 532 static void msm_complete_rx_dma(void *args)
 533 {
 534         struct msm_port *msm_port = args;
 535         struct uart_port *port = &msm_port->uart;
 536         struct tty_port *tport = &port->state->port;
 537         struct msm_dma *dma = &msm_port->rx_dma;
 538         int count = 0, i, sysrq;
 539         unsigned long flags;
 540         u32 val;
 541
 542         spin_lock_irqsave(&port->lock, flags);
 543
 544         /* Already stopped */
 545         if (!dma->count)
 546                 goto done;
 547
 548         val = msm_read(port, UARTDM_DMEN);
 549         val &= ~dma->enable_bit;
 550         msm_write(port, val, UARTDM_DMEN);
 551
 552         if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
 553                 port->icount.overrun++;
 554                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 555                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 556         }
 557
 558         count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
 559
 560         port->icount.rx += count;
 561
 562         dma->count = 0;
 563
 564         dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 565
 566         for (i = 0; i < count; i++) {
 567                 char flag = TTY_NORMAL;
 568
 569                 if (msm_port->break_detected && dma->virt[i] == 0) {
 570                         port->icount.brk++;
 571                         flag = TTY_BREAK;
 572                         msm_port->break_detected = false;
 573                         if (uart_handle_break(port))
 574                                 continue;
 575                 }
 576
 577                 if (!(port->read_status_mask & UART_SR_RX_BREAK))
 578                         flag = TTY_NORMAL;
 579
 580                 spin_unlock_irqrestore(&port->lock, flags);
 581                 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
 582                 spin_lock_irqsave(&port->lock, flags);
 583                 if (!sysrq)
 584                         tty_insert_flip_char(tport, dma->virt[i], flag);
 585         }
 586
 587         msm_start_rx_dma(msm_port);
 588 done:
 589         spin_unlock_irqrestore(&port->lock, flags);
 590
 591         if (count)
 592                 tty_flip_buffer_push(tport);
 593 }
 594
 595 static void msm_start_rx_dma(struct msm_port *msm_port)
 596 {
 597         struct msm_dma *dma = &msm_port->rx_dma;
 598         struct uart_port *uart = &msm_port->uart;
 599         u32 val;
 600         int ret;
 601
 602         if (!dma->chan)
 603                 return;
 604
 605         dma->phys = dma_map_single(uart->dev, dma->virt,
 606                                    UARTDM_RX_SIZE, dma->dir);
 607         ret = dma_mapping_error(uart->dev, dma->phys);
 608         if (ret)
 609                 return;
 610
 611         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 612                                                 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
 613                                                 DMA_PREP_INTERRUPT);
 614         if (!dma->desc)
 615                 goto unmap;
 616
 617         dma->desc->callback = msm_complete_rx_dma;
 618         dma->desc->callback_param = msm_port;
 619
 620         dma->cookie = dmaengine_submit(dma->desc);
 621         ret = dma_submit_error(dma->cookie);
 622         if (ret)
 623                 goto unmap;
 624         /*
 625          * Using DMA for FIFO off-load, no need for "Rx FIFO over
 626          * watermark" or "stale" interrupts, disable them
 627          */
 628         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 629
 630         /*
 631          * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
 632          * we need RXSTALE to flush input DMA fifo to memory
 633          */
 634         if (msm_port->is_uartdm < UARTDM_1P4)
 635                 msm_port->imr |= UART_IMR_RXSTALE;
 636
 637         msm_write(uart, msm_port->imr, UART_IMR);
 638
 639         dma->count = UARTDM_RX_SIZE;
 640
 641         dma_async_issue_pending(dma->chan);
 642
 643         msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 644         msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 645
 646         val = msm_read(uart, UARTDM_DMEN);
 647         val |= dma->enable_bit;
 648
 649         if (msm_port->is_uartdm < UARTDM_1P4)
 650                 msm_write(uart, val, UARTDM_DMEN);
 651
 652         msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
 653
 654         if (msm_port->is_uartdm > UARTDM_1P3)
 655                 msm_write(uart, val, UARTDM_DMEN);
 656
 657         return;
 658 unmap:
 659         dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 660 }
 661
 662 static void msm_stop_rx(struct uart_port *port)
 663 {
 664         struct msm_port *msm_port = UART_TO_MSM(port);
 665         struct msm_dma *dma = &msm_port->rx_dma;
 666
 667         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 668         msm_write(port, msm_port->imr, UART_IMR);
 669
 670         if (dma->chan)
 671                 msm_stop_dma(port, dma);
 672 }
 673
 674 static void msm_enable_ms(struct uart_port *port)
 675 {
 676         struct msm_port *msm_port = UART_TO_MSM(port);
 677
 678         msm_port->imr |= UART_IMR_DELTA_CTS;
 679         msm_write(port, msm_port->imr, UART_IMR);
 680 }
 681
 682 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 683 {
 684         struct tty_port *tport = &port->state->port;
 685         unsigned int sr;
 686         int count = 0;
 687         struct msm_port *msm_port = UART_TO_MSM(port);
 688
 689         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 690                 port->icount.overrun++;
 691                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 692                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 693         }
 694
 695         if (misr & UART_IMR_RXSTALE) {
 696                 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
 697                         msm_port->old_snap_state;
 698                 msm_port->old_snap_state = 0;
 699         } else {
 700                 count = 4 * (msm_read(port, UART_RFWR));
 701                 msm_port->old_snap_state += count;
 702         }
 703
 704         /* TODO: Precise error reporting */
 705
 706         port->icount.rx += count;
 707
 708         while (count > 0) {
 709                 unsigned char buf[4];
 710                 int sysrq, r_count, i;
 711
 712                 sr = msm_read(port, UART_SR);
 713                 if ((sr & UART_SR_RX_READY) == 0) {
 714                         msm_port->old_snap_state -= count;
 715                         break;
 716                 }
 717
 718                 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
 719                 r_count = min_t(int, count, sizeof(buf));
 720
 721                 for (i = 0; i < r_count; i++) {
 722                         char flag = TTY_NORMAL;
 723
 724                         if (msm_port->break_detected && buf[i] == 0) {
 725                                 port->icount.brk++;
 726                                 flag = TTY_BREAK;
 727                                 msm_port->break_detected = false;
 728                                 if (uart_handle_break(port))
 729                                         continue;
 730                         }
 731
 732                         if (!(port->read_status_mask & UART_SR_RX_BREAK))
 733                                 flag = TTY_NORMAL;
 734
 735                         spin_unlock(&port->lock);
 736                         sysrq = uart_handle_sysrq_char(port, buf[i]);
 737                         spin_lock(&port->lock);
 738                         if (!sysrq)
 739                                 tty_insert_flip_char(tport, buf[i], flag);
 740                 }
 741                 count -= r_count;
 742         }
 743
 744         spin_unlock(&port->lock);
 745         tty_flip_buffer_push(tport);
 746         spin_lock(&port->lock);
 747
 748         if (misr & (UART_IMR_RXSTALE))
 749                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 750         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
 751         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 752
 753         /* Try to use DMA */
 754         msm_start_rx_dma(msm_port);
 755 }
 756
 757 static void msm_handle_rx(struct uart_port *port)
 758 {
 759         struct tty_port *tport = &port->state->port;
 760         unsigned int sr;
 761
 762         /*
 763          * Handle overrun. My understanding of the hardware is that overrun
 764          * is not tied to the RX buffer, so we handle the case out of band.
 765          */
 766         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 767                 port->icount.overrun++;
 768                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 769                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 770         }
 771
 772         /* and now the main RX loop */
 773         while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
 774                 unsigned int c;
 775                 char flag = TTY_NORMAL;
 776                 int sysrq;
 777
 778                 c = msm_read(port, UART_RF);
 779
 780                 if (sr & UART_SR_RX_BREAK) {
 781                         port->icount.brk++;
 782                         if (uart_handle_break(port))
 783                                 continue;
 784                 } else if (sr & UART_SR_PAR_FRAME_ERR) {
 785                         port->icount.frame++;
 786                 } else {
 787                         port->icount.rx++;
 788                 }
 789
 790                 /* Mask conditions we're ignorning. */
 791                 sr &= port->read_status_mask;
 792
 793                 if (sr & UART_SR_RX_BREAK)
 794                         flag = TTY_BREAK;
 795                 else if (sr & UART_SR_PAR_FRAME_ERR)
 796                         flag = TTY_FRAME;
 797
 798                 spin_unlock(&port->lock);
 799                 sysrq = uart_handle_sysrq_char(port, c);
 800                 spin_lock(&port->lock);
 801                 if (!sysrq)
 802                         tty_insert_flip_char(tport, c, flag);
 803         }
 804
 805         spin_unlock(&port->lock);
 806         tty_flip_buffer_push(tport);
 807         spin_lock(&port->lock);
 808 }
 809
 810 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
 811 {
 812         struct circ_buf *xmit = &port->state->xmit;
 813         struct msm_port *msm_port = UART_TO_MSM(port);
 814         unsigned int num_chars;
 815         unsigned int tf_pointer = 0;
 816         void __iomem *tf;
 817
 818         if (msm_port->is_uartdm)
 819                 tf = port->membase + UARTDM_TF;
 820         else
 821                 tf = port->membase + UART_TF;
 822
 823         if (tx_count && msm_port->is_uartdm)
 824                 msm_reset_dm_count(port, tx_count);
 825
 826         while (tf_pointer < tx_count) {
 827                 int i;
 828                 char buf[4] = { 0 };
 829
 830                 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
 831                         break;
 832
 833                 if (msm_port->is_uartdm)
 834                         num_chars = min(tx_count - tf_pointer,
 835                                         (unsigned int)sizeof(buf));
 836                 else
 837                         num_chars = 1;
 838
 839                 for (i = 0; i < num_chars; i++) {
 840                         buf[i] = xmit->buf[xmit->tail + i];
 841                         port->icount.tx++;
 842                 }
 843
 844                 iowrite32_rep(tf, buf, 1);
 845                 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
 846                 tf_pointer += num_chars;
 847         }
 848
 849         /* disable tx interrupts if nothing more to send */
 850         if (uart_circ_empty(xmit))
 851                 msm_stop_tx(port);
 852
 853         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 854                 uart_write_wakeup(port);
 855 }
 856
 857 static void msm_handle_tx(struct uart_port *port)
 858 {
 859         struct msm_port *msm_port = UART_TO_MSM(port);
 860         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 861         struct msm_dma *dma = &msm_port->tx_dma;
 862         unsigned int pio_count, dma_count, dma_min;
 863         char buf[4] = { 0 };
 864         void __iomem *tf;
 865         int err = 0;
 866
 867         if (port->x_char) {
 868                 if (msm_port->is_uartdm)
 869                         tf = port->membase + UARTDM_TF;
 870                 else
 871                         tf = port->membase + UART_TF;
 872
 873                 buf[0] = port->x_char;
 874
 875                 if (msm_port->is_uartdm)
 876                         msm_reset_dm_count(port, 1);
 877
 878                 iowrite32_rep(tf, buf, 1);
 879                 port->icount.tx++;
 880                 port->x_char = 0;
 881                 return;
 882         }
 883
 884         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 885                 msm_stop_tx(port);
 886                 return;
 887         }
 888
 889         pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 890         dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 891
 892         dma_min = 1;    /* Always DMA */
 893         if (msm_port->is_uartdm > UARTDM_1P3) {
 894                 dma_count = UARTDM_TX_AIGN(dma_count);
 895                 dma_min = UARTDM_BURST_SIZE;
 896         } else {
 897                 if (dma_count > UARTDM_TX_MAX)
 898                         dma_count = UARTDM_TX_MAX;
 899         }
 900
 901         if (pio_count > port->fifosize)
 902                 pio_count = port->fifosize;
 903
 904         if (!dma->chan || dma_count < dma_min)
 905                 msm_handle_tx_pio(port, pio_count);
 906         else
 907                 err = msm_handle_tx_dma(msm_port, dma_count);
 908
 909         if (err)        /* fall back to PIO mode */
 910                 msm_handle_tx_pio(port, pio_count);
 911 }
 912
 913 static void msm_handle_delta_cts(struct uart_port *port)
 914 {
 915         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
 916         port->icount.cts++;
 917         wake_up_interruptible(&port->state->port.delta_msr_wait);
 918 }
 919
 920 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
 921 {
 922         struct uart_port *port = dev_id;
 923         struct msm_port *msm_port = UART_TO_MSM(port);
 924         struct msm_dma *dma = &msm_port->rx_dma;
 925         unsigned long flags;
 926         unsigned int misr;
 927         u32 val;
 928
 929         spin_lock_irqsave(&port->lock, flags);
 930         misr = msm_read(port, UART_MISR);
 931         msm_write(port, 0, UART_IMR); /* disable interrupt */
 932
 933         if (misr & UART_IMR_RXBREAK_START) {
 934                 msm_port->break_detected = true;
 935                 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
 936         }
 937
 938         if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
 939                 if (dma->count) {
 940                         val = UART_CR_CMD_STALE_EVENT_DISABLE;
 941                         msm_write(port, val, UART_CR);
 942                         val = UART_CR_CMD_RESET_STALE_INT;
 943                         msm_write(port, val, UART_CR);
 944                         /*
 945                          * Flush DMA input fifo to memory, this will also
 946                          * trigger DMA RX completion
 947                          */
 948                         dmaengine_terminate_all(dma->chan);
 949                 } else if (msm_port->is_uartdm) {
 950                         msm_handle_rx_dm(port, misr);
 951                 } else {
 952                         msm_handle_rx(port);
 953                 }
 954         }
 955         if (misr & UART_IMR_TXLEV)
 956                 msm_handle_tx(port);
 957         if (misr & UART_IMR_DELTA_CTS)
 958                 msm_handle_delta_cts(port);
 959
 960         msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
 961         spin_unlock_irqrestore(&port->lock, flags);
 962
 963         return IRQ_HANDLED;
 964 }
 965
 966 static unsigned int msm_tx_empty(struct uart_port *port)
 967 {
 968         return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
 969 }
 970
 971 static unsigned int msm_get_mctrl(struct uart_port *port)
 972 {
 973         return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
 974 }
 975
 976 static void msm_reset(struct uart_port *port)
 977 {
 978         struct msm_port *msm_port = UART_TO_MSM(port);
 979         unsigned int mr;
 980
 981         /* reset everything */
 982         msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
 983         msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
 984         msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 985         msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
 986         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
 987         msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
 988         mr = msm_read(port, UART_MR1);
 989         mr &= ~UART_MR1_RX_RDY_CTL;
 990         msm_write(port, mr, UART_MR1);
 991
 992         /* Disable DM modes */
 993         if (msm_port->is_uartdm)
 994                 msm_write(port, 0, UARTDM_DMEN);
 995 }
 996
 997 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
 998 {
 999         unsigned int mr;
1000
1001         mr = msm_read(port, UART_MR1);
1002
1003         if (!(mctrl & TIOCM_RTS)) {
1004                 mr &= ~UART_MR1_RX_RDY_CTL;
1005                 msm_write(port, mr, UART_MR1);
1006                 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1007         } else {
1008                 mr |= UART_MR1_RX_RDY_CTL;
1009                 msm_write(port, mr, UART_MR1);
1010         }
1011 }
1012
1013 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1014 {
1015         if (break_ctl)
1016                 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1017         else
1018                 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1019 }
1020
1021 struct msm_baud_map {
1022         u16     divisor;
1023         u8      code;
1024         u8      rxstale;
1025 };
1026
1027 static const struct msm_baud_map *
1028 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1029                    unsigned long *rate)
1030 {
1031         struct msm_port *msm_port = UART_TO_MSM(port);
1032         unsigned int divisor, result;
1033         unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1034         const struct msm_baud_map *entry, *end, *best;
1035         static const struct msm_baud_map table[] = {
1036                 {    1, 0xff, 31 },
1037                 {    2, 0xee, 16 },
1038                 {    3, 0xdd,  8 },
1039                 {    4, 0xcc,  6 },
1040                 {    6, 0xbb,  6 },
1041                 {    8, 0xaa,  6 },
1042                 {   12, 0x99,  6 },
1043                 {   16, 0x88,  1 },
1044                 {   24, 0x77,  1 },
1045                 {   32, 0x66,  1 },
1046                 {   48, 0x55,  1 },
1047                 {   96, 0x44,  1 },
1048                 {  192, 0x33,  1 },
1049                 {  384, 0x22,  1 },
1050                 {  768, 0x11,  1 },
1051                 { 1536, 0x00,  1 },
1052         };
1053
1054         best = table; /* Default to smallest divider */
1055         target = clk_round_rate(msm_port->clk, 16 * baud);
1056         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1057
1058         end = table + ARRAY_SIZE(table);
1059         entry = table;
1060         while (entry < end) {
1061                 if (entry->divisor <= divisor) {
1062                         result = target / entry->divisor / 16;
1063                         diff = abs(result - baud);
1064
1065                         /* Keep track of best entry */
1066                         if (diff < best_diff) {
1067                                 best_diff = diff;
1068                                 best = entry;
1069                                 best_rate = target;
1070                         }
1071
1072                         if (result == baud)
1073                                 break;
1074                 } else if (entry->divisor > divisor) {
1075                         old = target;
1076                         target = clk_round_rate(msm_port->clk, old + 1);
1077                         /*
1078                          * The rate didn't get any faster so we can't do
1079                          * better at dividing it down
1080                          */
1081                         if (target == old)
1082                                 break;
1083
1084                         /* Start the divisor search over at this new rate */
1085                         entry = table;
1086                         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1087                         continue;
1088                 }
1089                 entry++;
1090         }
1091
1092         *rate = best_rate;
1093         return best;
1094 }
1095
1096 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1097                              unsigned long *saved_flags)
1098 {
1099         unsigned int rxstale, watermark, mask;
1100         struct msm_port *msm_port = UART_TO_MSM(port);
1101         const struct msm_baud_map *entry;
1102         unsigned long flags, rate;
1103
1104         flags = *saved_flags;
1105         spin_unlock_irqrestore(&port->lock, flags);
1106
1107         entry = msm_find_best_baud(port, baud, &rate);
1108         clk_set_rate(msm_port->clk, rate);
1109         baud = rate / 16 / entry->divisor;
1110
1111         spin_lock_irqsave(&port->lock, flags);
1112         *saved_flags = flags;
1113         port->uartclk = rate;
1114
1115         msm_write(port, entry->code, UART_CSR);
1116
1117         /* RX stale watermark */
1118         rxstale = entry->rxstale;
1119         watermark = UART_IPR_STALE_LSB & rxstale;
1120         if (msm_port->is_uartdm) {
1121                 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1122         } else {
1123                 watermark |= UART_IPR_RXSTALE_LAST;
1124                 mask = UART_IPR_STALE_TIMEOUT_MSB;
1125         }
1126
1127         watermark |= mask & (rxstale << 2);
1128
1129         msm_write(port, watermark, UART_IPR);
1130
1131         /* set RX watermark */
1132         watermark = (port->fifosize * 3) / 4;
1133         msm_write(port, watermark, UART_RFWR);
1134
1135         /* set TX watermark */
1136         msm_write(port, 10, UART_TFWR);
1137
1138         msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1139         msm_reset(port);
1140
1141         /* Enable RX and TX */
1142         msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1143
1144         /* turn on RX and CTS interrupts */
1145         msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1146                         UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1147
1148         msm_write(port, msm_port->imr, UART_IMR);
1149
1150         if (msm_port->is_uartdm) {
1151                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1152                 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1153                 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1154         }
1155
1156         return baud;
1157 }
1158
1159 static void msm_init_clock(struct uart_port *port)
1160 {
1161         struct msm_port *msm_port = UART_TO_MSM(port);
1162
1163         clk_prepare_enable(msm_port->clk);
1164         clk_prepare_enable(msm_port->pclk);
1165         msm_serial_set_mnd_regs(port);
1166 }
1167
1168 static int msm_startup(struct uart_port *port)
1169 {
1170         struct msm_port *msm_port = UART_TO_MSM(port);
1171         unsigned int data, rfr_level, mask;
1172         int ret;
1173
1174         snprintf(msm_port->name, sizeof(msm_port->name),
1175                  "msm_serial%d", port->line);
1176
1177         msm_init_clock(port);
1178
1179         if (likely(port->fifosize > 12))
1180                 rfr_level = port->fifosize - 12;
1181         else
1182                 rfr_level = port->fifosize;
1183
1184         /* set automatic RFR level */
1185         data = msm_read(port, UART_MR1);
1186
1187         if (msm_port->is_uartdm)
1188                 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1189         else
1190                 mask = UART_MR1_AUTO_RFR_LEVEL1;
1191
1192         data &= ~mask;
1193         data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1194         data |= mask & (rfr_level << 2);
1195         data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1196         msm_write(port, data, UART_MR1);
1197
1198         if (msm_port->is_uartdm) {
1199                 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1200                 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1201         }
1202
1203         ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1204                           msm_port->name, port);
1205         if (unlikely(ret))
1206                 goto err_irq;
1207
1208         return 0;
1209
1210 err_irq:
1211         if (msm_port->is_uartdm)
1212                 msm_release_dma(msm_port);
1213
1214         clk_disable_unprepare(msm_port->pclk);
1215         clk_disable_unprepare(msm_port->clk);
1216
1217         return ret;
1218 }
1219
1220 static void msm_shutdown(struct uart_port *port)
1221 {
1222         struct msm_port *msm_port = UART_TO_MSM(port);
1223
1224         msm_port->imr = 0;
1225         msm_write(port, 0, UART_IMR); /* disable interrupts */
1226
1227         if (msm_port->is_uartdm)
1228                 msm_release_dma(msm_port);
1229
1230         clk_disable_unprepare(msm_port->clk);
1231
1232         free_irq(port->irq, port);
1233 }
1234
1235 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1236                             struct ktermios *old)
1237 {
1238         struct msm_port *msm_port = UART_TO_MSM(port);
1239         struct msm_dma *dma = &msm_port->rx_dma;
1240         unsigned long flags;
1241         unsigned int baud, mr;
1242
1243         spin_lock_irqsave(&port->lock, flags);
1244
1245         if (dma->chan) /* Terminate if any */
1246                 msm_stop_dma(port, dma);
1247
1248         /* calculate and set baud rate */
1249         baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1250         baud = msm_set_baud_rate(port, baud, &flags);
1251         if (tty_termios_baud_rate(termios))
1252                 tty_termios_encode_baud_rate(termios, baud, baud);
1253
1254         /* calculate parity */
1255         mr = msm_read(port, UART_MR2);
1256         mr &= ~UART_MR2_PARITY_MODE;
1257         if (termios->c_cflag & PARENB) {
1258                 if (termios->c_cflag & PARODD)
1259                         mr |= UART_MR2_PARITY_MODE_ODD;
1260                 else if (termios->c_cflag & CMSPAR)
1261                         mr |= UART_MR2_PARITY_MODE_SPACE;
1262                 else
1263                         mr |= UART_MR2_PARITY_MODE_EVEN;
1264         }
1265
1266         /* calculate bits per char */
1267         mr &= ~UART_MR2_BITS_PER_CHAR;
1268         switch (termios->c_cflag & CSIZE) {
1269         case CS5:
1270                 mr |= UART_MR2_BITS_PER_CHAR_5;
1271                 break;
1272         case CS6:
1273                 mr |= UART_MR2_BITS_PER_CHAR_6;
1274                 break;
1275         case CS7:
1276                 mr |= UART_MR2_BITS_PER_CHAR_7;
1277                 break;
1278         case CS8:
1279         default:
1280                 mr |= UART_MR2_BITS_PER_CHAR_8;
1281                 break;
1282         }
1283
1284         /* calculate stop bits */
1285         mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1286         if (termios->c_cflag & CSTOPB)
1287                 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1288         else
1289                 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1290
1291         /* set parity, bits per char, and stop bit */
1292         msm_write(port, mr, UART_MR2);
1293
1294         /* calculate and set hardware flow control */
1295         mr = msm_read(port, UART_MR1);
1296         mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1297         if (termios->c_cflag & CRTSCTS) {
1298                 mr |= UART_MR1_CTS_CTL;
1299                 mr |= UART_MR1_RX_RDY_CTL;
1300         }
1301         msm_write(port, mr, UART_MR1);
1302
1303         /* Configure status bits to ignore based on termio flags. */
1304         port->read_status_mask = 0;
1305         if (termios->c_iflag & INPCK)
1306                 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1307         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1308                 port->read_status_mask |= UART_SR_RX_BREAK;
1309
1310         uart_update_timeout(port, termios->c_cflag, baud);
1311
1312         /* Try to use DMA */
1313         msm_start_rx_dma(msm_port);
1314
1315         spin_unlock_irqrestore(&port->lock, flags);
1316 }
1317
1318 static const char *msm_type(struct uart_port *port)
1319 {
1320         return "MSM";
1321 }
1322
1323 static void msm_release_port(struct uart_port *port)
1324 {
1325         struct platform_device *pdev = to_platform_device(port->dev);
1326         struct resource *uart_resource;
1327         resource_size_t size;
1328
1329         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1330         if (unlikely(!uart_resource))
1331                 return;
1332         size = resource_size(uart_resource);
1333
1334         release_mem_region(port->mapbase, size);
1335         iounmap(port->membase);
1336         port->membase = NULL;
1337 }
1338
1339 static int msm_request_port(struct uart_port *port)
1340 {
1341         struct platform_device *pdev = to_platform_device(port->dev);
1342         struct resource *uart_resource;
1343         resource_size_t size;
1344         int ret;
1345
1346         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347         if (unlikely(!uart_resource))
1348                 return -ENXIO;
1349
1350         size = resource_size(uart_resource);
1351
1352         if (!request_mem_region(port->mapbase, size, "msm_serial"))
1353                 return -EBUSY;
1354
1355         port->membase = ioremap(port->mapbase, size);
1356         if (!port->membase) {
1357                 ret = -EBUSY;
1358                 goto fail_release_port;
1359         }
1360
1361         return 0;
1362
1363 fail_release_port:
1364         release_mem_region(port->mapbase, size);
1365         return ret;
1366 }
1367
1368 static void msm_config_port(struct uart_port *port, int flags)
1369 {
1370         int ret;
1371
1372         if (flags & UART_CONFIG_TYPE) {
1373                 port->type = PORT_MSM;
1374                 ret = msm_request_port(port);
1375                 if (ret)
1376                         return;
1377         }
1378 }
1379
1380 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1381 {
1382         if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1383                 return -EINVAL;
1384         if (unlikely(port->irq != ser->irq))
1385                 return -EINVAL;
1386         return 0;
1387 }
1388
1389 static void msm_power(struct uart_port *port, unsigned int state,
1390                       unsigned int oldstate)
1391 {
1392         struct msm_port *msm_port = UART_TO_MSM(port);
1393
1394         switch (state) {
1395         case 0:
1396                 clk_prepare_enable(msm_port->clk);
1397                 clk_prepare_enable(msm_port->pclk);
1398                 break;
1399         case 3:
1400                 clk_disable_unprepare(msm_port->clk);
1401                 clk_disable_unprepare(msm_port->pclk);
1402                 break;
1403         default:
1404                 pr_err("msm_serial: Unknown PM state %d\n", state);
1405         }
1406 }
1407
1408 #ifdef CONFIG_CONSOLE_POLL
1409 static int msm_poll_get_char_single(struct uart_port *port)
1410 {
1411         struct msm_port *msm_port = UART_TO_MSM(port);
1412         unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1413
1414         if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1415                 return NO_POLL_CHAR;
1416
1417         return msm_read(port, rf_reg) & 0xff;
1418 }
1419
1420 static int msm_poll_get_char_dm(struct uart_port *port)
1421 {
1422         int c;
1423         static u32 slop;
1424         static int count;
1425         unsigned char *sp = (unsigned char *)&slop;
1426
1427         /* Check if a previous read had more than one char */
1428         if (count) {
1429                 c = sp[sizeof(slop) - count];
1430                 count--;
1431         /* Or if FIFO is empty */
1432         } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1433                 /*
1434                  * If RX packing buffer has less than a word, force stale to
1435                  * push contents into RX FIFO
1436                  */
1437                 count = msm_read(port, UARTDM_RXFS);
1438                 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1439                 if (count) {
1440                         msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1441                         slop = msm_read(port, UARTDM_RF);
1442                         c = sp[0];
1443                         count--;
1444                         msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1445                         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1446                         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1447                                   UART_CR);
1448                 } else {
1449                         c = NO_POLL_CHAR;
1450                 }
1451         /* FIFO has a word */
1452         } else {
1453                 slop = msm_read(port, UARTDM_RF);
1454                 c = sp[0];
1455                 count = sizeof(slop) - 1;
1456         }
1457
1458         return c;
1459 }
1460
1461 static int msm_poll_get_char(struct uart_port *port)
1462 {
1463         u32 imr;
1464         int c;
1465         struct msm_port *msm_port = UART_TO_MSM(port);
1466
1467         /* Disable all interrupts */
1468         imr = msm_read(port, UART_IMR);
1469         msm_write(port, 0, UART_IMR);
1470
1471         if (msm_port->is_uartdm)
1472                 c = msm_poll_get_char_dm(port);
1473         else
1474                 c = msm_poll_get_char_single(port);
1475
1476         /* Enable interrupts */
1477         msm_write(port, imr, UART_IMR);
1478
1479         return c;
1480 }
1481
1482 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1483 {
1484         u32 imr;
1485         struct msm_port *msm_port = UART_TO_MSM(port);
1486
1487         /* Disable all interrupts */
1488         imr = msm_read(port, UART_IMR);
1489         msm_write(port, 0, UART_IMR);
1490
1491         if (msm_port->is_uartdm)
1492                 msm_reset_dm_count(port, 1);
1493
1494         /* Wait until FIFO is empty */
1495         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1496                 cpu_relax();
1497
1498         /* Write a character */
1499         msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1500
1501         /* Wait until FIFO is empty */
1502         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1503                 cpu_relax();
1504
1505         /* Enable interrupts */
1506         msm_write(port, imr, UART_IMR);
1507 }
1508 #endif
1509
1510 static struct uart_ops msm_uart_pops = {
1511         .tx_empty = msm_tx_empty,
1512         .set_mctrl = msm_set_mctrl,
1513         .get_mctrl = msm_get_mctrl,
1514         .stop_tx = msm_stop_tx,
1515         .start_tx = msm_start_tx,
1516         .stop_rx = msm_stop_rx,
1517         .enable_ms = msm_enable_ms,
1518         .break_ctl = msm_break_ctl,
1519         .startup = msm_startup,
1520         .shutdown = msm_shutdown,
1521         .set_termios = msm_set_termios,
1522         .type = msm_type,
1523         .release_port = msm_release_port,
1524         .request_port = msm_request_port,
1525         .config_port = msm_config_port,
1526         .verify_port = msm_verify_port,
1527         .pm = msm_power,
1528 #ifdef CONFIG_CONSOLE_POLL
1529         .poll_get_char  = msm_poll_get_char,
1530         .poll_put_char  = msm_poll_put_char,
1531 #endif
1532 };
1533
1534 static struct msm_port msm_uart_ports[] = {
1535         {
1536                 .uart = {
1537                         .iotype = UPIO_MEM,
1538                         .ops = &msm_uart_pops,
1539                         .flags = UPF_BOOT_AUTOCONF,
1540                         .fifosize = 64,
1541                         .line = 0,
1542                 },
1543         },
1544         {
1545                 .uart = {
1546                         .iotype = UPIO_MEM,
1547                         .ops = &msm_uart_pops,
1548                         .flags = UPF_BOOT_AUTOCONF,
1549                         .fifosize = 64,
1550                         .line = 1,
1551                 },
1552         },
1553         {
1554                 .uart = {
1555                         .iotype = UPIO_MEM,
1556                         .ops = &msm_uart_pops,
1557                         .flags = UPF_BOOT_AUTOCONF,
1558                         .fifosize = 64,
1559                         .line = 2,
1560                 },
1561         },
1562 };
1563
1564 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1565
1566 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1567 {
1568         return &msm_uart_ports[line].uart;
1569 }
1570
1571 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1572 static void __msm_console_write(struct uart_port *port, const char *s,
1573                                 unsigned int count, bool is_uartdm)
1574 {
1575         int i;
1576         int num_newlines = 0;
1577         bool replaced = false;
1578         void __iomem *tf;
1579         int locked = 1;
1580
1581         if (is_uartdm)
1582                 tf = port->membase + UARTDM_TF;
1583         else
1584                 tf = port->membase + UART_TF;
1585
1586         /* Account for newlines that will get a carriage return added */
1587         for (i = 0; i < count; i++)
1588                 if (s[i] == '\n')
1589                         num_newlines++;
1590         count += num_newlines;
1591
1592         if (port->sysrq)
1593                 locked = 0;
1594         else if (oops_in_progress)
1595                 locked = spin_trylock(&port->lock);
1596         else
1597                 spin_lock(&port->lock);
1598
1599         if (is_uartdm)
1600                 msm_reset_dm_count(port, count);
1601
1602         i = 0;
1603         while (i < count) {
1604                 int j;
1605                 unsigned int num_chars;
1606                 char buf[4] = { 0 };
1607
1608                 if (is_uartdm)
1609                         num_chars = min(count - i, (unsigned int)sizeof(buf));
1610                 else
1611                         num_chars = 1;
1612
1613                 for (j = 0; j < num_chars; j++) {
1614                         char c = *s;
1615
1616                         if (c == '\n' && !replaced) {
1617                                 buf[j] = '\r';
1618                                 j++;
1619                                 replaced = true;
1620                         }
1621                         if (j < num_chars) {
1622                                 buf[j] = c;
1623                                 s++;
1624                                 replaced = false;
1625                         }
1626                 }
1627
1628                 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1629                         cpu_relax();
1630
1631                 iowrite32_rep(tf, buf, 1);
1632                 i += num_chars;
1633         }
1634
1635         if (locked)
1636                 spin_unlock(&port->lock);
1637 }
1638
1639 static void msm_console_write(struct console *co, const char *s,
1640                               unsigned int count)
1641 {
1642         struct uart_port *port;
1643         struct msm_port *msm_port;
1644
1645         BUG_ON(co->index < 0 || co->index >= UART_NR);
1646
1647         port = msm_get_port_from_line(co->index);
1648         msm_port = UART_TO_MSM(port);
1649
1650         __msm_console_write(port, s, count, msm_port->is_uartdm);
1651 }
1652
1653 static int msm_console_setup(struct console *co, char *options)
1654 {
1655         struct uart_port *port;
1656         int baud = 115200;
1657         int bits = 8;
1658         int parity = 'n';
1659         int flow = 'n';
1660
1661         if (unlikely(co->index >= UART_NR || co->index < 0))
1662                 return -ENXIO;
1663
1664         port = msm_get_port_from_line(co->index);
1665
1666         if (unlikely(!port->membase))
1667                 return -ENXIO;
1668
1669         msm_init_clock(port);
1670
1671         if (options)
1672                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1673
1674         pr_info("msm_serial: console setup on port #%d\n", port->line);
1675
1676         return uart_set_options(port, co, baud, parity, bits, flow);
1677 }
1678
1679 static void
1680 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1681 {
1682         struct earlycon_device *dev = con->data;
1683
1684         __msm_console_write(&dev->port, s, n, false);
1685 }
1686
1687 static int __init
1688 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1689 {
1690         if (!device->port.membase)
1691                 return -ENODEV;
1692
1693         device->con->write = msm_serial_early_write;
1694         return 0;
1695 }
1696 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1697                     msm_serial_early_console_setup);
1698
1699 static void
1700 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1701 {
1702         struct earlycon_device *dev = con->data;
1703
1704         __msm_console_write(&dev->port, s, n, true);
1705 }
1706
1707 static int __init
1708 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1709                                   const char *opt)
1710 {
1711         if (!device->port.membase)
1712                 return -ENODEV;
1713
1714         device->con->write = msm_serial_early_write_dm;
1715         return 0;
1716 }
1717 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1718                     msm_serial_early_console_setup_dm);
1719
1720 static struct uart_driver msm_uart_driver;
1721
1722 static struct console msm_console = {
1723         .name = "ttyMSM",
1724         .write = msm_console_write,
1725         .device = uart_console_device,
1726         .setup = msm_console_setup,
1727         .flags = CON_PRINTBUFFER,
1728         .index = -1,
1729         .data = &msm_uart_driver,
1730 };
1731
1732 #define MSM_CONSOLE     (&msm_console)
1733
1734 #else
1735 #define MSM_CONSOLE     NULL
1736 #endif
1737
1738 static struct uart_driver msm_uart_driver = {
1739         .owner = THIS_MODULE,
1740         .driver_name = "msm_serial",
1741         .dev_name = "ttyMSM",
1742         .nr = UART_NR,
1743         .cons = MSM_CONSOLE,
1744 };
1745
1746 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1747
1748 static const struct of_device_id msm_uartdm_table[] = {
1749         { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1750         { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1751         { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1752         { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1753         { }
1754 };
1755
1756 static int msm_serial_probe(struct platform_device *pdev)
1757 {
1758         struct msm_port *msm_port;
1759         struct resource *resource;
1760         struct uart_port *port;
1761         const struct of_device_id *id;
1762         int irq, line;
1763
1764         if (pdev->dev.of_node)
1765                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1766         else
1767                 line = pdev->id;
1768
1769         if (line < 0)
1770                 line = atomic_inc_return(&msm_uart_next_id) - 1;
1771
1772         if (unlikely(line < 0 || line >= UART_NR))
1773                 return -ENXIO;
1774
1775         dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1776
1777         port = msm_get_port_from_line(line);
1778         port->dev = &pdev->dev;
1779         msm_port = UART_TO_MSM(port);
1780
1781         id = of_match_device(msm_uartdm_table, &pdev->dev);
1782         if (id)
1783                 msm_port->is_uartdm = (unsigned long)id->data;
1784         else
1785                 msm_port->is_uartdm = 0;
1786
1787         msm_port->clk = devm_clk_get(&pdev->dev, "core");
1788         if (IS_ERR(msm_port->clk))
1789                 return PTR_ERR(msm_port->clk);
1790
1791         if (msm_port->is_uartdm) {
1792                 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1793                 if (IS_ERR(msm_port->pclk))
1794                         return PTR_ERR(msm_port->pclk);
1795         }
1796
1797         port->uartclk = clk_get_rate(msm_port->clk);
1798         dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1799
1800         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1801         if (unlikely(!resource))
1802                 return -ENXIO;
1803         port->mapbase = resource->start;
1804
1805         irq = platform_get_irq(pdev, 0);
1806         if (unlikely(irq < 0))
1807                 return -ENXIO;
1808         port->irq = irq;
1809         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1810
1811         platform_set_drvdata(pdev, port);
1812
1813         return uart_add_one_port(&msm_uart_driver, port);
1814 }
1815
1816 static int msm_serial_remove(struct platform_device *pdev)
1817 {
1818         struct uart_port *port = platform_get_drvdata(pdev);
1819
1820         uart_remove_one_port(&msm_uart_driver, port);
1821
1822         return 0;
1823 }
1824
1825 static const struct of_device_id msm_match_table[] = {
1826         { .compatible = "qcom,msm-uart" },
1827         { .compatible = "qcom,msm-uartdm" },
1828         {}
1829 };
1830 MODULE_DEVICE_TABLE(of, msm_match_table);
1831
1832 static int __maybe_unused msm_serial_suspend(struct device *dev)
1833 {
1834         struct msm_port *port = dev_get_drvdata(dev);
1835
1836         uart_suspend_port(&msm_uart_driver, &port->uart);
1837
1838         return 0;
1839 }
1840
1841 static int __maybe_unused msm_serial_resume(struct device *dev)
1842 {
1843         struct msm_port *port = dev_get_drvdata(dev);
1844
1845         uart_resume_port(&msm_uart_driver, &port->uart);
1846
1847         return 0;
1848 }
1849
1850 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1851         SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1852 };
1853
1854 static struct platform_driver msm_platform_driver = {
1855         .remove = msm_serial_remove,
1856         .probe = msm_serial_probe,
1857         .driver = {
1858                 .name = "msm_serial",
1859                 .pm = &msm_serial_dev_pm_ops,
1860                 .of_match_table = msm_match_table,
1861         },
1862 };
1863
1864 static int __init msm_serial_init(void)
1865 {
1866         int ret;
1867
1868         ret = uart_register_driver(&msm_uart_driver);
1869         if (unlikely(ret))
1870                 return ret;
1871
1872         ret = platform_driver_register(&msm_platform_driver);
1873         if (unlikely(ret))
1874                 uart_unregister_driver(&msm_uart_driver);
1875
1876         pr_info("msm_serial: driver initialized\n");
1877
1878         return ret;
1879 }
1880
1881 static void __exit msm_serial_exit(void)
1882 {
1883         platform_driver_unregister(&msm_platform_driver);
1884         uart_unregister_driver(&msm_uart_driver);
1885 }
1886
1887 module_init(msm_serial_init);
1888 module_exit(msm_serial_exit);
1889
1890 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1891 MODULE_DESCRIPTION("Driver for msm7x serial device");
1892 MODULE_LICENSE("GPL");