drivers/tty/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/io.h>
  77 #include <asm/irq.h>
  78 #include <asm/dma.h>
  79 #include <asm/types.h>
  80 #include <asm/uaccess.h>
  81
  82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  83 #define SYNCLINK_GENERIC_HDLC 1
  84 #else
  85 #define SYNCLINK_GENERIC_HDLC 0
  86 #endif
  87
  88 /*
  89  * module identification
  90  */
  91 static char *driver_name     = "SyncLink GT";
  92 static char *tty_driver_name = "synclink_gt";
  93 static char *tty_dev_prefix  = "ttySLG";
  94 MODULE_LICENSE("GPL");
  95 #define MGSL_MAGIC 0x5401
  96 #define MAX_DEVICES 32
  97
  98 static struct pci_device_id pci_table[] = {
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {0,}, /* terminate list */
 104 };
 105 MODULE_DEVICE_TABLE(pci, pci_table);
 106
 107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 108 static void remove_one(struct pci_dev *dev);
 109 static struct pci_driver pci_driver = {
 110         .name           = "synclink_gt",
 111         .id_table       = pci_table,
 112         .probe          = init_one,
 113         .remove         = remove_one,
 114 };
 115
 116 static bool pci_registered;
 117
 118 /*
 119  * module configuration and status
 120  */
 121 static struct slgt_info *slgt_device_list;
 122 static int slgt_device_count;
 123
 124 static int ttymajor;
 125 static int debug_level;
 126 static int maxframe[MAX_DEVICES];
 127
 128 module_param(ttymajor, int, 0);
 129 module_param(debug_level, int, 0);
 130 module_param_array(maxframe, int, NULL, 0);
 131
 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 135
 136 /*
 137  * tty support and callbacks
 138  */
 139 static struct tty_driver *serial_driver;
 140
 141 static int  open(struct tty_struct *tty, struct file * filp);
 142 static void close(struct tty_struct *tty, struct file * filp);
 143 static void hangup(struct tty_struct *tty);
 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 145
 146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 147 static int put_char(struct tty_struct *tty, unsigned char ch);
 148 static void send_xchar(struct tty_struct *tty, char ch);
 149 static void wait_until_sent(struct tty_struct *tty, int timeout);
 150 static int  write_room(struct tty_struct *tty);
 151 static void flush_chars(struct tty_struct *tty);
 152 static void flush_buffer(struct tty_struct *tty);
 153 static void tx_hold(struct tty_struct *tty);
 154 static void tx_release(struct tty_struct *tty);
 155
 156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 157 static int  chars_in_buffer(struct tty_struct *tty);
 158 static void throttle(struct tty_struct * tty);
 159 static void unthrottle(struct tty_struct * tty);
 160 static int set_break(struct tty_struct *tty, int break_state);
 161
 162 /*
 163  * generic HDLC support and callbacks
 164  */
 165 #if SYNCLINK_GENERIC_HDLC
 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 167 static void hdlcdev_tx_done(struct slgt_info *info);
 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 169 static int  hdlcdev_init(struct slgt_info *info);
 170 static void hdlcdev_exit(struct slgt_info *info);
 171 #endif
 172
 173
 174 /*
 175  * device specific structures, macros and functions
 176  */
 177
 178 #define SLGT_MAX_PORTS 4
 179 #define SLGT_REG_SIZE  256
 180
 181 /*
 182  * conditional wait facility
 183  */
 184 struct cond_wait {
 185         struct cond_wait *next;
 186         wait_queue_head_t q;
 187         wait_queue_t wait;
 188         unsigned int data;
 189 };
 190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void flush_cond_wait(struct cond_wait **head);
 194
 195 /*
 196  * DMA buffer descriptor and access macros
 197  */
 198 struct slgt_desc
 199 {
 200         __le16 count;
 201         __le16 status;
 202         __le32 pbuf;  /* physical address of data buffer */
 203         __le32 next;  /* physical address of next descriptor */
 204
 205         /* driver book keeping */
 206         char *buf;          /* virtual  address of data buffer */
 207         unsigned int pdesc; /* physical address of this descriptor */
 208         dma_addr_t buf_dma_addr;
 209         unsigned short buf_count;
 210 };
 211
 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 217 #define desc_count(a)      (le16_to_cpu((a).count))
 218 #define desc_status(a)     (le16_to_cpu((a).status))
 219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 224
 225 struct _input_signal_events {
 226         int ri_up;
 227         int ri_down;
 228         int dsr_up;
 229         int dsr_down;
 230         int dcd_up;
 231         int dcd_down;
 232         int cts_up;
 233         int cts_down;
 234 };
 235
 236 /*
 237  * device instance data structure
 238  */
 239 struct slgt_info {
 240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 241         struct tty_port port;
 242
 243         struct slgt_info *next_device;  /* device list link */
 244
 245         int magic;
 246
 247         char device_name[25];
 248         struct pci_dev *pdev;
 249
 250         int port_count;  /* count of ports on adapter */
 251         int adapter_num; /* adapter instance number */
 252         int port_num;    /* port instance number */
 253
 254         /* array of pointers to port contexts on this adapter */
 255         struct slgt_info *port_array[SLGT_MAX_PORTS];
 256
 257         int                     line;           /* tty line instance number */
 258
 259         struct mgsl_icount      icount;
 260
 261         int                     timeout;
 262         int                     x_char;         /* xon/xoff character */
 263         unsigned int            read_status_mask;
 264         unsigned int            ignore_status_mask;
 265
 266         wait_queue_head_t       status_event_wait_q;
 267         wait_queue_head_t       event_wait_q;
 268         struct timer_list       tx_timer;
 269         struct timer_list       rx_timer;
 270
 271         unsigned int            gpio_present;
 272         struct cond_wait        *gpio_wait_q;
 273
 274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 275
 276         struct work_struct task;
 277         u32 pending_bh;
 278         bool bh_requested;
 279         bool bh_running;
 280
 281         int isr_overflow;
 282         bool irq_requested;     /* true if IRQ requested */
 283         bool irq_occurred;      /* for diagnostics use */
 284
 285         /* device configuration */
 286
 287         unsigned int bus_type;
 288         unsigned int irq_level;
 289         unsigned long irq_flags;
 290
 291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 292         u32 phys_reg_addr;
 293         bool reg_addr_requested;
 294
 295         MGSL_PARAMS params;       /* communications parameters */
 296         u32 idle_mode;
 297         u32 max_frame_size;       /* as set by device config */
 298
 299         unsigned int rbuf_fill_level;
 300         unsigned int rx_pio;
 301         unsigned int if_mode;
 302         unsigned int base_clock;
 303         unsigned int xsync;
 304         unsigned int xctrl;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char *flag_buf;
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408 #define XSR   0x40 /* extended sync pattern */
 409 #define XCR   0x44 /* extended control */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static unsigned int tbuf_bytes(struct slgt_info *info);
 470 static void reset_tbufs(struct slgt_info *info);
 471 static void tdma_reset(struct slgt_info *info);
 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty);
 514 static int  tiocmset(struct tty_struct *tty,
 515                                 unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 523 static int  set_xsync(struct slgt_info *info, int if_mode);
 524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 525 static int  set_xctrl(struct slgt_info *info, int if_mode);
 526
 527 /*
 528  * driver functions
 529  */
 530 static void add_device(struct slgt_info *info);
 531 static void device_init(int adapter_num, struct pci_dev *pdev);
 532 static int  claim_resources(struct slgt_info *info);
 533 static void release_resources(struct slgt_info *info);
 534
 535 /*
 536  * DEBUG OUTPUT CODE
 537  */
 538 #ifndef DBGINFO
 539 #define DBGINFO(fmt)
 540 #endif
 541 #ifndef DBGERR
 542 #define DBGERR(fmt)
 543 #endif
 544 #ifndef DBGBH
 545 #define DBGBH(fmt)
 546 #endif
 547 #ifndef DBGISR
 548 #define DBGISR(fmt)
 549 #endif
 550
 551 #ifdef DBGDATA
 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 553 {
 554         int i;
 555         int linecount;
 556         printk("%s %s data:\n",info->device_name, label);
 557         while(count) {
 558                 linecount = (count > 16) ? 16 : count;
 559                 for(i=0; i < linecount; i++)
 560                         printk("%02X ",(unsigned char)data[i]);
 561                 for(;i<17;i++)
 562                         printk("   ");
 563                 for(i=0;i<linecount;i++) {
 564                         if (data[i]>=040 && data[i]<=0176)
 565                                 printk("%c",data[i]);
 566                         else
 567                                 printk(".");
 568                 }
 569                 printk("\n");
 570                 data  += linecount;
 571                 count -= linecount;
 572         }
 573 }
 574 #else
 575 #define DBGDATA(info, buf, size, label)
 576 #endif
 577
 578 #ifdef DBGTBUF
 579 static void dump_tbufs(struct slgt_info *info)
 580 {
 581         int i;
 582         printk("tbuf_current=%d\n", info->tbuf_current);
 583         for (i=0 ; i < info->tbuf_count ; i++) {
 584                 printk("%d: count=%04X status=%04X\n",
 585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 586         }
 587 }
 588 #else
 589 #define DBGTBUF(info)
 590 #endif
 591
 592 #ifdef DBGRBUF
 593 static void dump_rbufs(struct slgt_info *info)
 594 {
 595         int i;
 596         printk("rbuf_current=%d\n", info->rbuf_current);
 597         for (i=0 ; i < info->rbuf_count ; i++) {
 598                 printk("%d: count=%04X status=%04X\n",
 599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 600         }
 601 }
 602 #else
 603 #define DBGRBUF(info)
 604 #endif
 605
 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 607 {
 608 #ifdef SANITY_CHECK
 609         if (!info) {
 610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613         if (info->magic != MGSL_MAGIC) {
 614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617 #else
 618         if (!info)
 619                 return 1;
 620 #endif
 621         return 0;
 622 }
 623
 624 /**
 625  * line discipline callback wrappers
 626  *
 627  * The wrappers maintain line discipline references
 628  * while calling into the line discipline.
 629  *
 630  * ldisc_receive_buf  - pass receive data to line discipline
 631  */
 632 static void ldisc_receive_buf(struct tty_struct *tty,
 633                               const __u8 *data, char *flags, int count)
 634 {
 635         struct tty_ldisc *ld;
 636         if (!tty)
 637                 return;
 638         ld = tty_ldisc_ref(tty);
 639         if (ld) {
 640                 if (ld->ops->receive_buf)
 641                         ld->ops->receive_buf(tty, data, flags, count);
 642                 tty_ldisc_deref(ld);
 643         }
 644 }
 645
 646 /* tty callbacks */
 647
 648 static int open(struct tty_struct *tty, struct file *filp)
 649 {
 650         struct slgt_info *info;
 651         int retval, line;
 652         unsigned long flags;
 653
 654         line = tty->index;
 655         if (line >= slgt_device_count) {
 656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 657                 return -ENODEV;
 658         }
 659
 660         info = slgt_device_list;
 661         while(info && info->line != line)
 662                 info = info->next_device;
 663         if (sanity_check(info, tty->name, "open"))
 664                 return -ENODEV;
 665         if (info->init_error) {
 666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 667                 return -ENODEV;
 668         }
 669
 670         tty->driver_data = info;
 671         info->port.tty = tty;
 672
 673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 674
 675         mutex_lock(&info->port.mutex);
 676         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 677
 678         spin_lock_irqsave(&info->netlock, flags);
 679         if (info->netcount) {
 680                 retval = -EBUSY;
 681                 spin_unlock_irqrestore(&info->netlock, flags);
 682                 mutex_unlock(&info->port.mutex);
 683                 goto cleanup;
 684         }
 685         info->port.count++;
 686         spin_unlock_irqrestore(&info->netlock, flags);
 687
 688         if (info->port.count == 1) {
 689                 /* 1st open on this device, init hardware */
 690                 retval = startup(info);
 691                 if (retval < 0) {
 692                         mutex_unlock(&info->port.mutex);
 693                         goto cleanup;
 694                 }
 695         }
 696         mutex_unlock(&info->port.mutex);
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         mutex_lock(&info->port.mutex);
 729         if (info->port.flags & ASYNC_INITIALIZED)
 730                 wait_until_sent(tty, info->timeout);
 731         flush_buffer(tty);
 732         tty_ldisc_flush(tty);
 733
 734         shutdown(info);
 735         mutex_unlock(&info->port.mutex);
 736
 737         tty_port_close_end(&info->port, tty);
 738         info->port.tty = NULL;
 739 cleanup:
 740         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 741 }
 742
 743 static void hangup(struct tty_struct *tty)
 744 {
 745         struct slgt_info *info = tty->driver_data;
 746         unsigned long flags;
 747
 748         if (sanity_check(info, tty->name, "hangup"))
 749                 return;
 750         DBGINFO(("%s hangup\n", info->device_name));
 751
 752         flush_buffer(tty);
 753
 754         mutex_lock(&info->port.mutex);
 755         shutdown(info);
 756
 757         spin_lock_irqsave(&info->port.lock, flags);
 758         info->port.count = 0;
 759         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 760         info->port.tty = NULL;
 761         spin_unlock_irqrestore(&info->port.lock, flags);
 762         mutex_unlock(&info->port.mutex);
 763
 764         wake_up_interruptible(&info->port.open_wait);
 765 }
 766
 767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 768 {
 769         struct slgt_info *info = tty->driver_data;
 770         unsigned long flags;
 771
 772         DBGINFO(("%s set_termios\n", tty->driver->name));
 773
 774         change_params(info);
 775
 776         /* Handle transition to B0 status */
 777         if (old_termios->c_cflag & CBAUD &&
 778             !(tty->termios.c_cflag & CBAUD)) {
 779                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 780                 spin_lock_irqsave(&info->lock,flags);
 781                 set_signals(info);
 782                 spin_unlock_irqrestore(&info->lock,flags);
 783         }
 784
 785         /* Handle transition away from B0 status */
 786         if (!(old_termios->c_cflag & CBAUD) &&
 787             tty->termios.c_cflag & CBAUD) {
 788                 info->signals |= SerialSignal_DTR;
 789                 if (!(tty->termios.c_cflag & CRTSCTS) ||
 790                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 791                         info->signals |= SerialSignal_RTS;
 792                 }
 793                 spin_lock_irqsave(&info->lock,flags);
 794                 set_signals(info);
 795                 spin_unlock_irqrestore(&info->lock,flags);
 796         }
 797
 798         /* Handle turning off CRTSCTS */
 799         if (old_termios->c_cflag & CRTSCTS &&
 800             !(tty->termios.c_cflag & CRTSCTS)) {
 801                 tty->hw_stopped = 0;
 802                 tx_release(tty);
 803         }
 804 }
 805
 806 static void update_tx_timer(struct slgt_info *info)
 807 {
 808         /*
 809          * use worst case speed of 1200bps to calculate transmit timeout
 810          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 811          */
 812         if (info->params.mode == MGSL_MODE_HDLC) {
 813                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 814                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 815         }
 816 }
 817
 818 static int write(struct tty_struct *tty,
 819                  const unsigned char *buf, int count)
 820 {
 821         int ret = 0;
 822         struct slgt_info *info = tty->driver_data;
 823         unsigned long flags;
 824
 825         if (sanity_check(info, tty->name, "write"))
 826                 return -EIO;
 827
 828         DBGINFO(("%s write count=%d\n", info->device_name, count));
 829
 830         if (!info->tx_buf || (count > info->max_frame_size))
 831                 return -EIO;
 832
 833         if (!count || tty->stopped || tty->hw_stopped)
 834                 return 0;
 835
 836         spin_lock_irqsave(&info->lock, flags);
 837
 838         if (info->tx_count) {
 839                 /* send accumulated data from send_char() */
 840                 if (!tx_load(info, info->tx_buf, info->tx_count))
 841                         goto cleanup;
 842                 info->tx_count = 0;
 843         }
 844
 845         if (tx_load(info, buf, count))
 846                 ret = count;
 847
 848 cleanup:
 849         spin_unlock_irqrestore(&info->lock, flags);
 850         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 851         return ret;
 852 }
 853
 854 static int put_char(struct tty_struct *tty, unsigned char ch)
 855 {
 856         struct slgt_info *info = tty->driver_data;
 857         unsigned long flags;
 858         int ret = 0;
 859
 860         if (sanity_check(info, tty->name, "put_char"))
 861                 return 0;
 862         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 863         if (!info->tx_buf)
 864                 return 0;
 865         spin_lock_irqsave(&info->lock,flags);
 866         if (info->tx_count < info->max_frame_size) {
 867                 info->tx_buf[info->tx_count++] = ch;
 868                 ret = 1;
 869         }
 870         spin_unlock_irqrestore(&info->lock,flags);
 871         return ret;
 872 }
 873
 874 static void send_xchar(struct tty_struct *tty, char ch)
 875 {
 876         struct slgt_info *info = tty->driver_data;
 877         unsigned long flags;
 878
 879         if (sanity_check(info, tty->name, "send_xchar"))
 880                 return;
 881         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 882         info->x_char = ch;
 883         if (ch) {
 884                 spin_lock_irqsave(&info->lock,flags);
 885                 if (!info->tx_enabled)
 886                         tx_start(info);
 887                 spin_unlock_irqrestore(&info->lock,flags);
 888         }
 889 }
 890
 891 static void wait_until_sent(struct tty_struct *tty, int timeout)
 892 {
 893         struct slgt_info *info = tty->driver_data;
 894         unsigned long orig_jiffies, char_time;
 895
 896         if (!info )
 897                 return;
 898         if (sanity_check(info, tty->name, "wait_until_sent"))
 899                 return;
 900         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 901         if (!(info->port.flags & ASYNC_INITIALIZED))
 902                 goto exit;
 903
 904         orig_jiffies = jiffies;
 905
 906         /* Set check interval to 1/5 of estimated time to
 907          * send a character, and make it at least 1. The check
 908          * interval should also be less than the timeout.
 909          * Note: use tight timings here to satisfy the NIST-PCTS.
 910          */
 911
 912         if (info->params.data_rate) {
 913                 char_time = info->timeout/(32 * 5);
 914                 if (!char_time)
 915                         char_time++;
 916         } else
 917                 char_time = 1;
 918
 919         if (timeout)
 920                 char_time = min_t(unsigned long, char_time, timeout);
 921
 922         while (info->tx_active) {
 923                 msleep_interruptible(jiffies_to_msecs(char_time));
 924                 if (signal_pending(current))
 925                         break;
 926                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 927                         break;
 928         }
 929 exit:
 930         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 931 }
 932
 933 static int write_room(struct tty_struct *tty)
 934 {
 935         struct slgt_info *info = tty->driver_data;
 936         int ret;
 937
 938         if (sanity_check(info, tty->name, "write_room"))
 939                 return 0;
 940         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 941         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 942         return ret;
 943 }
 944
 945 static void flush_chars(struct tty_struct *tty)
 946 {
 947         struct slgt_info *info = tty->driver_data;
 948         unsigned long flags;
 949
 950         if (sanity_check(info, tty->name, "flush_chars"))
 951                 return;
 952         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 953
 954         if (info->tx_count <= 0 || tty->stopped ||
 955             tty->hw_stopped || !info->tx_buf)
 956                 return;
 957
 958         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 959
 960         spin_lock_irqsave(&info->lock,flags);
 961         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 962                 info->tx_count = 0;
 963         spin_unlock_irqrestore(&info->lock,flags);
 964 }
 965
 966 static void flush_buffer(struct tty_struct *tty)
 967 {
 968         struct slgt_info *info = tty->driver_data;
 969         unsigned long flags;
 970
 971         if (sanity_check(info, tty->name, "flush_buffer"))
 972                 return;
 973         DBGINFO(("%s flush_buffer\n", info->device_name));
 974
 975         spin_lock_irqsave(&info->lock, flags);
 976         info->tx_count = 0;
 977         spin_unlock_irqrestore(&info->lock, flags);
 978
 979         tty_wakeup(tty);
 980 }
 981
 982 /*
 983  * throttle (stop) transmitter
 984  */
 985 static void tx_hold(struct tty_struct *tty)
 986 {
 987         struct slgt_info *info = tty->driver_data;
 988         unsigned long flags;
 989
 990         if (sanity_check(info, tty->name, "tx_hold"))
 991                 return;
 992         DBGINFO(("%s tx_hold\n", info->device_name));
 993         spin_lock_irqsave(&info->lock,flags);
 994         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 995                 tx_stop(info);
 996         spin_unlock_irqrestore(&info->lock,flags);
 997 }
 998
 999 /*
1000  * release (start) transmitter
1001  */
1002 static void tx_release(struct tty_struct *tty)
1003 {
1004         struct slgt_info *info = tty->driver_data;
1005         unsigned long flags;
1006
1007         if (sanity_check(info, tty->name, "tx_release"))
1008                 return;
1009         DBGINFO(("%s tx_release\n", info->device_name));
1010         spin_lock_irqsave(&info->lock, flags);
1011         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1012                 info->tx_count = 0;
1013         spin_unlock_irqrestore(&info->lock, flags);
1014 }
1015
1016 /*
1017  * Service an IOCTL request
1018  *
1019  * Arguments
1020  *
1021  *      tty     pointer to tty instance data
1022  *      cmd     IOCTL command code
1023  *      arg     command argument/context
1024  *
1025  * Return 0 if success, otherwise error code
1026  */
1027 static int ioctl(struct tty_struct *tty,
1028                  unsigned int cmd, unsigned long arg)
1029 {
1030         struct slgt_info *info = tty->driver_data;
1031         void __user *argp = (void __user *)arg;
1032         int ret;
1033
1034         if (sanity_check(info, tty->name, "ioctl"))
1035                 return -ENODEV;
1036         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1037
1038         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1039             (cmd != TIOCMIWAIT)) {
1040                 if (tty->flags & (1 << TTY_IO_ERROR))
1041                     return -EIO;
1042         }
1043
1044         switch (cmd) {
1045         case MGSL_IOCWAITEVENT:
1046                 return wait_mgsl_event(info, argp);
1047         case TIOCMIWAIT:
1048                 return modem_input_wait(info,(int)arg);
1049         case MGSL_IOCSGPIO:
1050                 return set_gpio(info, argp);
1051         case MGSL_IOCGGPIO:
1052                 return get_gpio(info, argp);
1053         case MGSL_IOCWAITGPIO:
1054                 return wait_gpio(info, argp);
1055         case MGSL_IOCGXSYNC:
1056                 return get_xsync(info, argp);
1057         case MGSL_IOCSXSYNC:
1058                 return set_xsync(info, (int)arg);
1059         case MGSL_IOCGXCTRL:
1060                 return get_xctrl(info, argp);
1061         case MGSL_IOCSXCTRL:
1062                 return set_xctrl(info, (int)arg);
1063         }
1064         mutex_lock(&info->port.mutex);
1065         switch (cmd) {
1066         case MGSL_IOCGPARAMS:
1067                 ret = get_params(info, argp);
1068                 break;
1069         case MGSL_IOCSPARAMS:
1070                 ret = set_params(info, argp);
1071                 break;
1072         case MGSL_IOCGTXIDLE:
1073                 ret = get_txidle(info, argp);
1074                 break;
1075         case MGSL_IOCSTXIDLE:
1076                 ret = set_txidle(info, (int)arg);
1077                 break;
1078         case MGSL_IOCTXENABLE:
1079                 ret = tx_enable(info, (int)arg);
1080                 break;
1081         case MGSL_IOCRXENABLE:
1082                 ret = rx_enable(info, (int)arg);
1083                 break;
1084         case MGSL_IOCTXABORT:
1085                 ret = tx_abort(info);
1086                 break;
1087         case MGSL_IOCGSTATS:
1088                 ret = get_stats(info, argp);
1089                 break;
1090         case MGSL_IOCGIF:
1091                 ret = get_interface(info, argp);
1092                 break;
1093         case MGSL_IOCSIF:
1094                 ret = set_interface(info,(int)arg);
1095                 break;
1096         default:
1097                 ret = -ENOIOCTLCMD;
1098         }
1099         mutex_unlock(&info->port.mutex);
1100         return ret;
1101 }
1102
1103 static int get_icount(struct tty_struct *tty,
1104                                 struct serial_icounter_struct *icount)
1105
1106 {
1107         struct slgt_info *info = tty->driver_data;
1108         struct mgsl_icount cnow;        /* kernel counter temps */
1109         unsigned long flags;
1110
1111         spin_lock_irqsave(&info->lock,flags);
1112         cnow = info->icount;
1113         spin_unlock_irqrestore(&info->lock,flags);
1114
1115         icount->cts = cnow.cts;
1116         icount->dsr = cnow.dsr;
1117         icount->rng = cnow.rng;
1118         icount->dcd = cnow.dcd;
1119         icount->rx = cnow.rx;
1120         icount->tx = cnow.tx;
1121         icount->frame = cnow.frame;
1122         icount->overrun = cnow.overrun;
1123         icount->parity = cnow.parity;
1124         icount->brk = cnow.brk;
1125         icount->buf_overrun = cnow.buf_overrun;
1126
1127         return 0;
1128 }
1129
1130 /*
1131  * support for 32 bit ioctl calls on 64 bit systems
1132  */
1133 #ifdef CONFIG_COMPAT
1134 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1135 {
1136         struct MGSL_PARAMS32 tmp_params;
1137
1138         DBGINFO(("%s get_params32\n", info->device_name));
1139         memset(&tmp_params, 0, sizeof(tmp_params));
1140         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1141         tmp_params.loopback        = info->params.loopback;
1142         tmp_params.flags           = info->params.flags;
1143         tmp_params.encoding        = info->params.encoding;
1144         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1145         tmp_params.addr_filter     = info->params.addr_filter;
1146         tmp_params.crc_type        = info->params.crc_type;
1147         tmp_params.preamble_length = info->params.preamble_length;
1148         tmp_params.preamble        = info->params.preamble;
1149         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1150         tmp_params.data_bits       = info->params.data_bits;
1151         tmp_params.stop_bits       = info->params.stop_bits;
1152         tmp_params.parity          = info->params.parity;
1153         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1154                 return -EFAULT;
1155         return 0;
1156 }
1157
1158 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1159 {
1160         struct MGSL_PARAMS32 tmp_params;
1161
1162         DBGINFO(("%s set_params32\n", info->device_name));
1163         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1164                 return -EFAULT;
1165
1166         spin_lock(&info->lock);
1167         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1168                 info->base_clock = tmp_params.clock_speed;
1169         } else {
1170                 info->params.mode            = tmp_params.mode;
1171                 info->params.loopback        = tmp_params.loopback;
1172                 info->params.flags           = tmp_params.flags;
1173                 info->params.encoding        = tmp_params.encoding;
1174                 info->params.clock_speed     = tmp_params.clock_speed;
1175                 info->params.addr_filter     = tmp_params.addr_filter;
1176                 info->params.crc_type        = tmp_params.crc_type;
1177                 info->params.preamble_length = tmp_params.preamble_length;
1178                 info->params.preamble        = tmp_params.preamble;
1179                 info->params.data_rate       = tmp_params.data_rate;
1180                 info->params.data_bits       = tmp_params.data_bits;
1181                 info->params.stop_bits       = tmp_params.stop_bits;
1182                 info->params.parity          = tmp_params.parity;
1183         }
1184         spin_unlock(&info->lock);
1185
1186         program_hw(info);
1187
1188         return 0;
1189 }
1190
1191 static long slgt_compat_ioctl(struct tty_struct *tty,
1192                          unsigned int cmd, unsigned long arg)
1193 {
1194         struct slgt_info *info = tty->driver_data;
1195         int rc;
1196
1197         if (sanity_check(info, tty->name, "compat_ioctl"))
1198                 return -ENODEV;
1199         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1200
1201         switch (cmd) {
1202         case MGSL_IOCSPARAMS32:
1203                 rc = set_params32(info, compat_ptr(arg));
1204                 break;
1205
1206         case MGSL_IOCGPARAMS32:
1207                 rc = get_params32(info, compat_ptr(arg));
1208                 break;
1209
1210         case MGSL_IOCGPARAMS:
1211         case MGSL_IOCSPARAMS:
1212         case MGSL_IOCGTXIDLE:
1213         case MGSL_IOCGSTATS:
1214         case MGSL_IOCWAITEVENT:
1215         case MGSL_IOCGIF:
1216         case MGSL_IOCSGPIO:
1217         case MGSL_IOCGGPIO:
1218         case MGSL_IOCWAITGPIO:
1219         case MGSL_IOCGXSYNC:
1220         case MGSL_IOCGXCTRL:
1221                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1222                 break;
1223         default:
1224                 rc = ioctl(tty, cmd, arg);
1225         }
1226         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1227         return rc;
1228 }
1229 #else
1230 #define slgt_compat_ioctl NULL
1231 #endif /* ifdef CONFIG_COMPAT */
1232
1233 /*
1234  * proc fs support
1235  */
1236 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1237 {
1238         char stat_buf[30];
1239         unsigned long flags;
1240
1241         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1242                       info->device_name, info->phys_reg_addr,
1243                       info->irq_level, info->max_frame_size);
1244
1245         /* output current serial signal states */
1246         spin_lock_irqsave(&info->lock,flags);
1247         get_signals(info);
1248         spin_unlock_irqrestore(&info->lock,flags);
1249
1250         stat_buf[0] = 0;
1251         stat_buf[1] = 0;
1252         if (info->signals & SerialSignal_RTS)
1253                 strcat(stat_buf, "|RTS");
1254         if (info->signals & SerialSignal_CTS)
1255                 strcat(stat_buf, "|CTS");
1256         if (info->signals & SerialSignal_DTR)
1257                 strcat(stat_buf, "|DTR");
1258         if (info->signals & SerialSignal_DSR)
1259                 strcat(stat_buf, "|DSR");
1260         if (info->signals & SerialSignal_DCD)
1261                 strcat(stat_buf, "|CD");
1262         if (info->signals & SerialSignal_RI)
1263                 strcat(stat_buf, "|RI");
1264
1265         if (info->params.mode != MGSL_MODE_ASYNC) {
1266                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1267                                info->icount.txok, info->icount.rxok);
1268                 if (info->icount.txunder)
1269                         seq_printf(m, " txunder:%d", info->icount.txunder);
1270                 if (info->icount.txabort)
1271                         seq_printf(m, " txabort:%d", info->icount.txabort);
1272                 if (info->icount.rxshort)
1273                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1274                 if (info->icount.rxlong)
1275                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1276                 if (info->icount.rxover)
1277                         seq_printf(m, " rxover:%d", info->icount.rxover);
1278                 if (info->icount.rxcrc)
1279                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1280         } else {
1281                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1282                                info->icount.tx, info->icount.rx);
1283                 if (info->icount.frame)
1284                         seq_printf(m, " fe:%d", info->icount.frame);
1285                 if (info->icount.parity)
1286                         seq_printf(m, " pe:%d", info->icount.parity);
1287                 if (info->icount.brk)
1288                         seq_printf(m, " brk:%d", info->icount.brk);
1289                 if (info->icount.overrun)
1290                         seq_printf(m, " oe:%d", info->icount.overrun);
1291         }
1292
1293         /* Append serial signal status to end */
1294         seq_printf(m, " %s\n", stat_buf+1);
1295
1296         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1297                        info->tx_active,info->bh_requested,info->bh_running,
1298                        info->pending_bh);
1299 }
1300
1301 /* Called to print information about devices
1302  */
1303 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1304 {
1305         struct slgt_info *info;
1306
1307         seq_puts(m, "synclink_gt driver\n");
1308
1309         info = slgt_device_list;
1310         while( info ) {
1311                 line_info(m, info);
1312                 info = info->next_device;
1313         }
1314         return 0;
1315 }
1316
1317 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1318 {
1319         return single_open(file, synclink_gt_proc_show, NULL);
1320 }
1321
1322 static const struct file_operations synclink_gt_proc_fops = {
1323         .owner          = THIS_MODULE,
1324         .open           = synclink_gt_proc_open,
1325         .read           = seq_read,
1326         .llseek         = seq_lseek,
1327         .release        = single_release,
1328 };
1329
1330 /*
1331  * return count of bytes in transmit buffer
1332  */
1333 static int chars_in_buffer(struct tty_struct *tty)
1334 {
1335         struct slgt_info *info = tty->driver_data;
1336         int count;
1337         if (sanity_check(info, tty->name, "chars_in_buffer"))
1338                 return 0;
1339         count = tbuf_bytes(info);
1340         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1341         return count;
1342 }
1343
1344 /*
1345  * signal remote device to throttle send data (our receive data)
1346  */
1347 static void throttle(struct tty_struct * tty)
1348 {
1349         struct slgt_info *info = tty->driver_data;
1350         unsigned long flags;
1351
1352         if (sanity_check(info, tty->name, "throttle"))
1353                 return;
1354         DBGINFO(("%s throttle\n", info->device_name));
1355         if (I_IXOFF(tty))
1356                 send_xchar(tty, STOP_CHAR(tty));
1357         if (tty->termios.c_cflag & CRTSCTS) {
1358                 spin_lock_irqsave(&info->lock,flags);
1359                 info->signals &= ~SerialSignal_RTS;
1360                 set_signals(info);
1361                 spin_unlock_irqrestore(&info->lock,flags);
1362         }
1363 }
1364
1365 /*
1366  * signal remote device to stop throttling send data (our receive data)
1367  */
1368 static void unthrottle(struct tty_struct * tty)
1369 {
1370         struct slgt_info *info = tty->driver_data;
1371         unsigned long flags;
1372
1373         if (sanity_check(info, tty->name, "unthrottle"))
1374                 return;
1375         DBGINFO(("%s unthrottle\n", info->device_name));
1376         if (I_IXOFF(tty)) {
1377                 if (info->x_char)
1378                         info->x_char = 0;
1379                 else
1380                         send_xchar(tty, START_CHAR(tty));
1381         }
1382         if (tty->termios.c_cflag & CRTSCTS) {
1383                 spin_lock_irqsave(&info->lock,flags);
1384                 info->signals |= SerialSignal_RTS;
1385                 set_signals(info);
1386                 spin_unlock_irqrestore(&info->lock,flags);
1387         }
1388 }
1389
1390 /*
1391  * set or clear transmit break condition
1392  * break_state  -1=set break condition, 0=clear
1393  */
1394 static int set_break(struct tty_struct *tty, int break_state)
1395 {
1396         struct slgt_info *info = tty->driver_data;
1397         unsigned short value;
1398         unsigned long flags;
1399
1400         if (sanity_check(info, tty->name, "set_break"))
1401                 return -EINVAL;
1402         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1403
1404         spin_lock_irqsave(&info->lock,flags);
1405         value = rd_reg16(info, TCR);
1406         if (break_state == -1)
1407                 value |= BIT6;
1408         else
1409                 value &= ~BIT6;
1410         wr_reg16(info, TCR, value);
1411         spin_unlock_irqrestore(&info->lock,flags);
1412         return 0;
1413 }
1414
1415 #if SYNCLINK_GENERIC_HDLC
1416
1417 /**
1418  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1419  * set encoding and frame check sequence (FCS) options
1420  *
1421  * dev       pointer to network device structure
1422  * encoding  serial encoding setting
1423  * parity    FCS setting
1424  *
1425  * returns 0 if success, otherwise error code
1426  */
1427 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1428                           unsigned short parity)
1429 {
1430         struct slgt_info *info = dev_to_port(dev);
1431         unsigned char  new_encoding;
1432         unsigned short new_crctype;
1433
1434         /* return error if TTY interface open */
1435         if (info->port.count)
1436                 return -EBUSY;
1437
1438         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1439
1440         switch (encoding)
1441         {
1442         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1443         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1444         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1445         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1446         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1447         default: return -EINVAL;
1448         }
1449
1450         switch (parity)
1451         {
1452         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1453         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1454         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1455         default: return -EINVAL;
1456         }
1457
1458         info->params.encoding = new_encoding;
1459         info->params.crc_type = new_crctype;
1460
1461         /* if network interface up, reprogram hardware */
1462         if (info->netcount)
1463                 program_hw(info);
1464
1465         return 0;
1466 }
1467
1468 /**
1469  * called by generic HDLC layer to send frame
1470  *
1471  * skb  socket buffer containing HDLC frame
1472  * dev  pointer to network device structure
1473  */
1474 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1475                                       struct net_device *dev)
1476 {
1477         struct slgt_info *info = dev_to_port(dev);
1478         unsigned long flags;
1479
1480         DBGINFO(("%s hdlc_xmit\n", dev->name));
1481
1482         if (!skb->len)
1483                 return NETDEV_TX_OK;
1484
1485         /* stop sending until this frame completes */
1486         netif_stop_queue(dev);
1487
1488         /* update network statistics */
1489         dev->stats.tx_packets++;
1490         dev->stats.tx_bytes += skb->len;
1491
1492         /* save start time for transmit timeout detection */
1493         dev->trans_start = jiffies;
1494
1495         spin_lock_irqsave(&info->lock, flags);
1496         tx_load(info, skb->data, skb->len);
1497         spin_unlock_irqrestore(&info->lock, flags);
1498
1499         /* done with socket buffer, so free it */
1500         dev_kfree_skb(skb);
1501
1502         return NETDEV_TX_OK;
1503 }
1504
1505 /**
1506  * called by network layer when interface enabled
1507  * claim resources and initialize hardware
1508  *
1509  * dev  pointer to network device structure
1510  *
1511  * returns 0 if success, otherwise error code
1512  */
1513 static int hdlcdev_open(struct net_device *dev)
1514 {
1515         struct slgt_info *info = dev_to_port(dev);
1516         int rc;
1517         unsigned long flags;
1518
1519         if (!try_module_get(THIS_MODULE))
1520                 return -EBUSY;
1521
1522         DBGINFO(("%s hdlcdev_open\n", dev->name));
1523
1524         /* generic HDLC layer open processing */
1525         rc = hdlc_open(dev);
1526         if (rc)
1527                 return rc;
1528
1529         /* arbitrate between network and tty opens */
1530         spin_lock_irqsave(&info->netlock, flags);
1531         if (info->port.count != 0 || info->netcount != 0) {
1532                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1533                 spin_unlock_irqrestore(&info->netlock, flags);
1534                 return -EBUSY;
1535         }
1536         info->netcount=1;
1537         spin_unlock_irqrestore(&info->netlock, flags);
1538
1539         /* claim resources and init adapter */
1540         if ((rc = startup(info)) != 0) {
1541                 spin_lock_irqsave(&info->netlock, flags);
1542                 info->netcount=0;
1543                 spin_unlock_irqrestore(&info->netlock, flags);
1544                 return rc;
1545         }
1546
1547         /* assert RTS and DTR, apply hardware settings */
1548         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1549         program_hw(info);
1550
1551         /* enable network layer transmit */
1552         dev->trans_start = jiffies;
1553         netif_start_queue(dev);
1554
1555         /* inform generic HDLC layer of current DCD status */
1556         spin_lock_irqsave(&info->lock, flags);
1557         get_signals(info);
1558         spin_unlock_irqrestore(&info->lock, flags);
1559         if (info->signals & SerialSignal_DCD)
1560                 netif_carrier_on(dev);
1561         else
1562                 netif_carrier_off(dev);
1563         return 0;
1564 }
1565
1566 /**
1567  * called by network layer when interface is disabled
1568  * shutdown hardware and release resources
1569  *
1570  * dev  pointer to network device structure
1571  *
1572  * returns 0 if success, otherwise error code
1573  */
1574 static int hdlcdev_close(struct net_device *dev)
1575 {
1576         struct slgt_info *info = dev_to_port(dev);
1577         unsigned long flags;
1578
1579         DBGINFO(("%s hdlcdev_close\n", dev->name));
1580
1581         netif_stop_queue(dev);
1582
1583         /* shutdown adapter and release resources */
1584         shutdown(info);
1585
1586         hdlc_close(dev);
1587
1588         spin_lock_irqsave(&info->netlock, flags);
1589         info->netcount=0;
1590         spin_unlock_irqrestore(&info->netlock, flags);
1591
1592         module_put(THIS_MODULE);
1593         return 0;
1594 }
1595
1596 /**
1597  * called by network layer to process IOCTL call to network device
1598  *
1599  * dev  pointer to network device structure
1600  * ifr  pointer to network interface request structure
1601  * cmd  IOCTL command code
1602  *
1603  * returns 0 if success, otherwise error code
1604  */
1605 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1606 {
1607         const size_t size = sizeof(sync_serial_settings);
1608         sync_serial_settings new_line;
1609         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1610         struct slgt_info *info = dev_to_port(dev);
1611         unsigned int flags;
1612
1613         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1614
1615         /* return error if TTY interface open */
1616         if (info->port.count)
1617                 return -EBUSY;
1618
1619         if (cmd != SIOCWANDEV)
1620                 return hdlc_ioctl(dev, ifr, cmd);
1621
1622         memset(&new_line, 0, sizeof(new_line));
1623
1624         switch(ifr->ifr_settings.type) {
1625         case IF_GET_IFACE: /* return current sync_serial_settings */
1626
1627                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1628                 if (ifr->ifr_settings.size < size) {
1629                         ifr->ifr_settings.size = size; /* data size wanted */
1630                         return -ENOBUFS;
1631                 }
1632
1633                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1634                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1635                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1636                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1637
1638                 switch (flags){
1639                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1640                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1641                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1642                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1643                 default: new_line.clock_type = CLOCK_DEFAULT;
1644                 }
1645
1646                 new_line.clock_rate = info->params.clock_speed;
1647                 new_line.loopback   = info->params.loopback ? 1:0;
1648
1649                 if (copy_to_user(line, &new_line, size))
1650                         return -EFAULT;
1651                 return 0;
1652
1653         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1654
1655                 if(!capable(CAP_NET_ADMIN))
1656                         return -EPERM;
1657                 if (copy_from_user(&new_line, line, size))
1658                         return -EFAULT;
1659
1660                 switch (new_line.clock_type)
1661                 {
1662                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1663                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1664                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1665                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1666                 case CLOCK_DEFAULT:  flags = info->params.flags &
1667                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1668                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1669                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1670                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1671                 default: return -EINVAL;
1672                 }
1673
1674                 if (new_line.loopback != 0 && new_line.loopback != 1)
1675                         return -EINVAL;
1676
1677                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1678                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1679                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1680                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1681                 info->params.flags |= flags;
1682
1683                 info->params.loopback = new_line.loopback;
1684
1685                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1686                         info->params.clock_speed = new_line.clock_rate;
1687                 else
1688                         info->params.clock_speed = 0;
1689
1690                 /* if network interface up, reprogram hardware */
1691                 if (info->netcount)
1692                         program_hw(info);
1693                 return 0;
1694
1695         default:
1696                 return hdlc_ioctl(dev, ifr, cmd);
1697         }
1698 }
1699
1700 /**
1701  * called by network layer when transmit timeout is detected
1702  *
1703  * dev  pointer to network device structure
1704  */
1705 static void hdlcdev_tx_timeout(struct net_device *dev)
1706 {
1707         struct slgt_info *info = dev_to_port(dev);
1708         unsigned long flags;
1709
1710         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1711
1712         dev->stats.tx_errors++;
1713         dev->stats.tx_aborted_errors++;
1714
1715         spin_lock_irqsave(&info->lock,flags);
1716         tx_stop(info);
1717         spin_unlock_irqrestore(&info->lock,flags);
1718
1719         netif_wake_queue(dev);
1720 }
1721
1722 /**
1723  * called by device driver when transmit completes
1724  * reenable network layer transmit if stopped
1725  *
1726  * info  pointer to device instance information
1727  */
1728 static void hdlcdev_tx_done(struct slgt_info *info)
1729 {
1730         if (netif_queue_stopped(info->netdev))
1731                 netif_wake_queue(info->netdev);
1732 }
1733
1734 /**
1735  * called by device driver when frame received
1736  * pass frame to network layer
1737  *
1738  * info  pointer to device instance information
1739  * buf   pointer to buffer contianing frame data
1740  * size  count of data bytes in buf
1741  */
1742 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1743 {
1744         struct sk_buff *skb = dev_alloc_skb(size);
1745         struct net_device *dev = info->netdev;
1746
1747         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1748
1749         if (skb == NULL) {
1750                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1751                 dev->stats.rx_dropped++;
1752                 return;
1753         }
1754
1755         memcpy(skb_put(skb, size), buf, size);
1756
1757         skb->protocol = hdlc_type_trans(skb, dev);
1758
1759         dev->stats.rx_packets++;
1760         dev->stats.rx_bytes += size;
1761
1762         netif_rx(skb);
1763 }
1764
1765 static const struct net_device_ops hdlcdev_ops = {
1766         .ndo_open       = hdlcdev_open,
1767         .ndo_stop       = hdlcdev_close,
1768         .ndo_change_mtu = hdlc_change_mtu,
1769         .ndo_start_xmit = hdlc_start_xmit,
1770         .ndo_do_ioctl   = hdlcdev_ioctl,
1771         .ndo_tx_timeout = hdlcdev_tx_timeout,
1772 };
1773
1774 /**
1775  * called by device driver when adding device instance
1776  * do generic HDLC initialization
1777  *
1778  * info  pointer to device instance information
1779  *
1780  * returns 0 if success, otherwise error code
1781  */
1782 static int hdlcdev_init(struct slgt_info *info)
1783 {
1784         int rc;
1785         struct net_device *dev;
1786         hdlc_device *hdlc;
1787
1788         /* allocate and initialize network and HDLC layer objects */
1789
1790         dev = alloc_hdlcdev(info);
1791         if (!dev) {
1792                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1793                 return -ENOMEM;
1794         }
1795
1796         /* for network layer reporting purposes only */
1797         dev->mem_start = info->phys_reg_addr;
1798         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1799         dev->irq       = info->irq_level;
1800
1801         /* network layer callbacks and settings */
1802         dev->netdev_ops     = &hdlcdev_ops;
1803         dev->watchdog_timeo = 10 * HZ;
1804         dev->tx_queue_len   = 50;
1805
1806         /* generic HDLC layer callbacks and settings */
1807         hdlc         = dev_to_hdlc(dev);
1808         hdlc->attach = hdlcdev_attach;
1809         hdlc->xmit   = hdlcdev_xmit;
1810
1811         /* register objects with HDLC layer */
1812         rc = register_hdlc_device(dev);
1813         if (rc) {
1814                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1815                 free_netdev(dev);
1816                 return rc;
1817         }
1818
1819         info->netdev = dev;
1820         return 0;
1821 }
1822
1823 /**
1824  * called by device driver when removing device instance
1825  * do generic HDLC cleanup
1826  *
1827  * info  pointer to device instance information
1828  */
1829 static void hdlcdev_exit(struct slgt_info *info)
1830 {
1831         unregister_hdlc_device(info->netdev);
1832         free_netdev(info->netdev);
1833         info->netdev = NULL;
1834 }
1835
1836 #endif /* ifdef CONFIG_HDLC */
1837
1838 /*
1839  * get async data from rx DMA buffers
1840  */
1841 static void rx_async(struct slgt_info *info)
1842 {
1843         struct mgsl_icount *icount = &info->icount;
1844         unsigned int start, end;
1845         unsigned char *p;
1846         unsigned char status;
1847         struct slgt_desc *bufs = info->rbufs;
1848         int i, count;
1849         int chars = 0;
1850         int stat;
1851         unsigned char ch;
1852
1853         start = end = info->rbuf_current;
1854
1855         while(desc_complete(bufs[end])) {
1856                 count = desc_count(bufs[end]) - info->rbuf_index;
1857                 p     = bufs[end].buf + info->rbuf_index;
1858
1859                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1860                 DBGDATA(info, p, count, "rx");
1861
1862                 for(i=0 ; i < count; i+=2, p+=2) {
1863                         ch = *p;
1864                         icount->rx++;
1865
1866                         stat = 0;
1867
1868                         status = *(p + 1) & (BIT1 + BIT0);
1869                         if (status) {
1870                                 if (status & BIT1)
1871                                         icount->parity++;
1872                                 else if (status & BIT0)
1873                                         icount->frame++;
1874                                 /* discard char if tty control flags say so */
1875                                 if (status & info->ignore_status_mask)
1876                                         continue;
1877                                 if (status & BIT1)
1878                                         stat = TTY_PARITY;
1879                                 else if (status & BIT0)
1880                                         stat = TTY_FRAME;
1881                         }
1882                         tty_insert_flip_char(&info->port, ch, stat);
1883                         chars++;
1884                 }
1885
1886                 if (i < count) {
1887                         /* receive buffer not completed */
1888                         info->rbuf_index += i;
1889                         mod_timer(&info->rx_timer, jiffies + 1);
1890                         break;
1891                 }
1892
1893                 info->rbuf_index = 0;
1894                 free_rbufs(info, end, end);
1895
1896                 if (++end == info->rbuf_count)
1897                         end = 0;
1898
1899                 /* if entire list searched then no frame available */
1900                 if (end == start)
1901                         break;
1902         }
1903
1904         if (chars)
1905                 tty_flip_buffer_push(&info->port);
1906 }
1907
1908 /*
1909  * return next bottom half action to perform
1910  */
1911 static int bh_action(struct slgt_info *info)
1912 {
1913         unsigned long flags;
1914         int rc;
1915
1916         spin_lock_irqsave(&info->lock,flags);
1917
1918         if (info->pending_bh & BH_RECEIVE) {
1919                 info->pending_bh &= ~BH_RECEIVE;
1920                 rc = BH_RECEIVE;
1921         } else if (info->pending_bh & BH_TRANSMIT) {
1922                 info->pending_bh &= ~BH_TRANSMIT;
1923                 rc = BH_TRANSMIT;
1924         } else if (info->pending_bh & BH_STATUS) {
1925                 info->pending_bh &= ~BH_STATUS;
1926                 rc = BH_STATUS;
1927         } else {
1928                 /* Mark BH routine as complete */
1929                 info->bh_running = false;
1930                 info->bh_requested = false;
1931                 rc = 0;
1932         }
1933
1934         spin_unlock_irqrestore(&info->lock,flags);
1935
1936         return rc;
1937 }
1938
1939 /*
1940  * perform bottom half processing
1941  */
1942 static void bh_handler(struct work_struct *work)
1943 {
1944         struct slgt_info *info = container_of(work, struct slgt_info, task);
1945         int action;
1946
1947         info->bh_running = true;
1948
1949         while((action = bh_action(info))) {
1950                 switch (action) {
1951                 case BH_RECEIVE:
1952                         DBGBH(("%s bh receive\n", info->device_name));
1953                         switch(info->params.mode) {
1954                         case MGSL_MODE_ASYNC:
1955                                 rx_async(info);
1956                                 break;
1957                         case MGSL_MODE_HDLC:
1958                                 while(rx_get_frame(info));
1959                                 break;
1960                         case MGSL_MODE_RAW:
1961                         case MGSL_MODE_MONOSYNC:
1962                         case MGSL_MODE_BISYNC:
1963                         case MGSL_MODE_XSYNC:
1964                                 while(rx_get_buf(info));
1965                                 break;
1966                         }
1967                         /* restart receiver if rx DMA buffers exhausted */
1968                         if (info->rx_restart)
1969                                 rx_start(info);
1970                         break;
1971                 case BH_TRANSMIT:
1972                         bh_transmit(info);
1973                         break;
1974                 case BH_STATUS:
1975                         DBGBH(("%s bh status\n", info->device_name));
1976                         info->ri_chkcount = 0;
1977                         info->dsr_chkcount = 0;
1978                         info->dcd_chkcount = 0;
1979                         info->cts_chkcount = 0;
1980                         break;
1981                 default:
1982                         DBGBH(("%s unknown action\n", info->device_name));
1983                         break;
1984                 }
1985         }
1986         DBGBH(("%s bh_handler exit\n", info->device_name));
1987 }
1988
1989 static void bh_transmit(struct slgt_info *info)
1990 {
1991         struct tty_struct *tty = info->port.tty;
1992
1993         DBGBH(("%s bh_transmit\n", info->device_name));
1994         if (tty)
1995                 tty_wakeup(tty);
1996 }
1997
1998 static void dsr_change(struct slgt_info *info, unsigned short status)
1999 {
2000         if (status & BIT3) {
2001                 info->signals |= SerialSignal_DSR;
2002                 info->input_signal_events.dsr_up++;
2003         } else {
2004                 info->signals &= ~SerialSignal_DSR;
2005                 info->input_signal_events.dsr_down++;
2006         }
2007         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2008         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2009                 slgt_irq_off(info, IRQ_DSR);
2010                 return;
2011         }
2012         info->icount.dsr++;
2013         wake_up_interruptible(&info->status_event_wait_q);
2014         wake_up_interruptible(&info->event_wait_q);
2015         info->pending_bh |= BH_STATUS;
2016 }
2017
2018 static void cts_change(struct slgt_info *info, unsigned short status)
2019 {
2020         if (status & BIT2) {
2021                 info->signals |= SerialSignal_CTS;
2022                 info->input_signal_events.cts_up++;
2023         } else {
2024                 info->signals &= ~SerialSignal_CTS;
2025                 info->input_signal_events.cts_down++;
2026         }
2027         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2028         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2029                 slgt_irq_off(info, IRQ_CTS);
2030                 return;
2031         }
2032         info->icount.cts++;
2033         wake_up_interruptible(&info->status_event_wait_q);
2034         wake_up_interruptible(&info->event_wait_q);
2035         info->pending_bh |= BH_STATUS;
2036
2037         if (tty_port_cts_enabled(&info->port)) {
2038                 if (info->port.tty) {
2039                         if (info->port.tty->hw_stopped) {
2040                                 if (info->signals & SerialSignal_CTS) {
2041                                         info->port.tty->hw_stopped = 0;
2042                                         info->pending_bh |= BH_TRANSMIT;
2043                                         return;
2044                                 }
2045                         } else {
2046                                 if (!(info->signals & SerialSignal_CTS))
2047                                         info->port.tty->hw_stopped = 1;
2048                         }
2049                 }
2050         }
2051 }
2052
2053 static void dcd_change(struct slgt_info *info, unsigned short status)
2054 {
2055         if (status & BIT1) {
2056                 info->signals |= SerialSignal_DCD;
2057                 info->input_signal_events.dcd_up++;
2058         } else {
2059                 info->signals &= ~SerialSignal_DCD;
2060                 info->input_signal_events.dcd_down++;
2061         }
2062         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2063         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2064                 slgt_irq_off(info, IRQ_DCD);
2065                 return;
2066         }
2067         info->icount.dcd++;
2068 #if SYNCLINK_GENERIC_HDLC
2069         if (info->netcount) {
2070                 if (info->signals & SerialSignal_DCD)
2071                         netif_carrier_on(info->netdev);
2072                 else
2073                         netif_carrier_off(info->netdev);
2074         }
2075 #endif
2076         wake_up_interruptible(&info->status_event_wait_q);
2077         wake_up_interruptible(&info->event_wait_q);
2078         info->pending_bh |= BH_STATUS;
2079
2080         if (info->port.flags & ASYNC_CHECK_CD) {
2081                 if (info->signals & SerialSignal_DCD)
2082                         wake_up_interruptible(&info->port.open_wait);
2083                 else {
2084                         if (info->port.tty)
2085                                 tty_hangup(info->port.tty);
2086                 }
2087         }
2088 }
2089
2090 static void ri_change(struct slgt_info *info, unsigned short status)
2091 {
2092         if (status & BIT0) {
2093                 info->signals |= SerialSignal_RI;
2094                 info->input_signal_events.ri_up++;
2095         } else {
2096                 info->signals &= ~SerialSignal_RI;
2097                 info->input_signal_events.ri_down++;
2098         }
2099         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2100         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2101                 slgt_irq_off(info, IRQ_RI);
2102                 return;
2103         }
2104         info->icount.rng++;
2105         wake_up_interruptible(&info->status_event_wait_q);
2106         wake_up_interruptible(&info->event_wait_q);
2107         info->pending_bh |= BH_STATUS;
2108 }
2109
2110 static void isr_rxdata(struct slgt_info *info)
2111 {
2112         unsigned int count = info->rbuf_fill_count;
2113         unsigned int i = info->rbuf_fill_index;
2114         unsigned short reg;
2115
2116         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2117                 reg = rd_reg16(info, RDR);
2118                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2119                 if (desc_complete(info->rbufs[i])) {
2120                         /* all buffers full */
2121                         rx_stop(info);
2122                         info->rx_restart = 1;
2123                         continue;
2124                 }
2125                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2126                 /* async mode saves status byte to buffer for each data byte */
2127                 if (info->params.mode == MGSL_MODE_ASYNC)
2128                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2129                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2130                         /* buffer full or end of frame */
2131                         set_desc_count(info->rbufs[i], count);
2132                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2133                         info->rbuf_fill_count = count = 0;
2134                         if (++i == info->rbuf_count)
2135                                 i = 0;
2136                         info->pending_bh |= BH_RECEIVE;
2137                 }
2138         }
2139
2140         info->rbuf_fill_index = i;
2141         info->rbuf_fill_count = count;
2142 }
2143
2144 static void isr_serial(struct slgt_info *info)
2145 {
2146         unsigned short status = rd_reg16(info, SSR);
2147
2148         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2149
2150         wr_reg16(info, SSR, status); /* clear pending */
2151
2152         info->irq_occurred = true;
2153
2154         if (info->params.mode == MGSL_MODE_ASYNC) {
2155                 if (status & IRQ_TXIDLE) {
2156                         if (info->tx_active)
2157                                 isr_txeom(info, status);
2158                 }
2159                 if (info->rx_pio && (status & IRQ_RXDATA))
2160                         isr_rxdata(info);
2161                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2162                         info->icount.brk++;
2163                         /* process break detection if tty control allows */
2164                         if (info->port.tty) {
2165                                 if (!(status & info->ignore_status_mask)) {
2166                                         if (info->read_status_mask & MASK_BREAK) {
2167                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2168                                                 if (info->port.flags & ASYNC_SAK)
2169                                                         do_SAK(info->port.tty);
2170                                         }
2171                                 }
2172                         }
2173                 }
2174         } else {
2175                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2176                         isr_txeom(info, status);
2177                 if (info->rx_pio && (status & IRQ_RXDATA))
2178                         isr_rxdata(info);
2179                 if (status & IRQ_RXIDLE) {
2180                         if (status & RXIDLE)
2181                                 info->icount.rxidle++;
2182                         else
2183                                 info->icount.exithunt++;
2184                         wake_up_interruptible(&info->event_wait_q);
2185                 }
2186
2187                 if (status & IRQ_RXOVER)
2188                         rx_start(info);
2189         }
2190
2191         if (status & IRQ_DSR)
2192                 dsr_change(info, status);
2193         if (status & IRQ_CTS)
2194                 cts_change(info, status);
2195         if (status & IRQ_DCD)
2196                 dcd_change(info, status);
2197         if (status & IRQ_RI)
2198                 ri_change(info, status);
2199 }
2200
2201 static void isr_rdma(struct slgt_info *info)
2202 {
2203         unsigned int status = rd_reg32(info, RDCSR);
2204
2205         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2206
2207         /* RDCSR (rx DMA control/status)
2208          *
2209          * 31..07  reserved
2210          * 06      save status byte to DMA buffer
2211          * 05      error
2212          * 04      eol (end of list)
2213          * 03      eob (end of buffer)
2214          * 02      IRQ enable
2215          * 01      reset
2216          * 00      enable
2217          */
2218         wr_reg32(info, RDCSR, status);  /* clear pending */
2219
2220         if (status & (BIT5 + BIT4)) {
2221                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2222                 info->rx_restart = true;
2223         }
2224         info->pending_bh |= BH_RECEIVE;
2225 }
2226
2227 static void isr_tdma(struct slgt_info *info)
2228 {
2229         unsigned int status = rd_reg32(info, TDCSR);
2230
2231         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2232
2233         /* TDCSR (tx DMA control/status)
2234          *
2235          * 31..06  reserved
2236          * 05      error
2237          * 04      eol (end of list)
2238          * 03      eob (end of buffer)
2239          * 02      IRQ enable
2240          * 01      reset
2241          * 00      enable
2242          */
2243         wr_reg32(info, TDCSR, status);  /* clear pending */
2244
2245         if (status & (BIT5 + BIT4 + BIT3)) {
2246                 // another transmit buffer has completed
2247                 // run bottom half to get more send data from user
2248                 info->pending_bh |= BH_TRANSMIT;
2249         }
2250 }
2251
2252 /*
2253  * return true if there are unsent tx DMA buffers, otherwise false
2254  *
2255  * if there are unsent buffers then info->tbuf_start
2256  * is set to index of first unsent buffer
2257  */
2258 static bool unsent_tbufs(struct slgt_info *info)
2259 {
2260         unsigned int i = info->tbuf_current;
2261         bool rc = false;
2262
2263         /*
2264          * search backwards from last loaded buffer (precedes tbuf_current)
2265          * for first unsent buffer (desc_count > 0)
2266          */
2267
2268         do {
2269                 if (i)
2270                         i--;
2271                 else
2272                         i = info->tbuf_count - 1;
2273                 if (!desc_count(info->tbufs[i]))
2274                         break;
2275                 info->tbuf_start = i;
2276                 rc = true;
2277         } while (i != info->tbuf_current);
2278
2279         return rc;
2280 }
2281
2282 static void isr_txeom(struct slgt_info *info, unsigned short status)
2283 {
2284         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2285
2286         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2287         tdma_reset(info);
2288         if (status & IRQ_TXUNDER) {
2289                 unsigned short val = rd_reg16(info, TCR);
2290                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2291                 wr_reg16(info, TCR, val); /* clear reset bit */
2292         }
2293
2294         if (info->tx_active) {
2295                 if (info->params.mode != MGSL_MODE_ASYNC) {
2296                         if (status & IRQ_TXUNDER)
2297                                 info->icount.txunder++;
2298                         else if (status & IRQ_TXIDLE)
2299                                 info->icount.txok++;
2300                 }
2301
2302                 if (unsent_tbufs(info)) {
2303                         tx_start(info);
2304                         update_tx_timer(info);
2305                         return;
2306                 }
2307                 info->tx_active = false;
2308
2309                 del_timer(&info->tx_timer);
2310
2311                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2312                         info->signals &= ~SerialSignal_RTS;
2313                         info->drop_rts_on_tx_done = false;
2314                         set_signals(info);
2315                 }
2316
2317 #if SYNCLINK_GENERIC_HDLC
2318                 if (info->netcount)
2319                         hdlcdev_tx_done(info);
2320                 else
2321 #endif
2322                 {
2323                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2324                                 tx_stop(info);
2325                                 return;
2326                         }
2327                         info->pending_bh |= BH_TRANSMIT;
2328                 }
2329         }
2330 }
2331
2332 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2333 {
2334         struct cond_wait *w, *prev;
2335
2336         /* wake processes waiting for specific transitions */
2337         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2338                 if (w->data & changed) {
2339                         w->data = state;
2340                         wake_up_interruptible(&w->q);
2341                         if (prev != NULL)
2342                                 prev->next = w->next;
2343                         else
2344                                 info->gpio_wait_q = w->next;
2345                 } else
2346                         prev = w;
2347         }
2348 }
2349
2350 /* interrupt service routine
2351  *
2352  *      irq     interrupt number
2353  *      dev_id  device ID supplied during interrupt registration
2354  */
2355 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2356 {
2357         struct slgt_info *info = dev_id;
2358         unsigned int gsr;
2359         unsigned int i;
2360
2361         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2362
2363         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2364                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2365                 info->irq_occurred = true;
2366                 for(i=0; i < info->port_count ; i++) {
2367                         if (info->port_array[i] == NULL)
2368                                 continue;
2369                         spin_lock(&info->port_array[i]->lock);
2370                         if (gsr & (BIT8 << i))
2371                                 isr_serial(info->port_array[i]);
2372                         if (gsr & (BIT16 << (i*2)))
2373                                 isr_rdma(info->port_array[i]);
2374                         if (gsr & (BIT17 << (i*2)))
2375                                 isr_tdma(info->port_array[i]);
2376                         spin_unlock(&info->port_array[i]->lock);
2377                 }
2378         }
2379
2380         if (info->gpio_present) {
2381                 unsigned int state;
2382                 unsigned int changed;
2383                 spin_lock(&info->lock);
2384                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2385                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2386                         /* read latched state of GPIO signals */
2387                         state = rd_reg32(info, IOVR);
2388                         /* clear pending GPIO interrupt bits */
2389                         wr_reg32(info, IOSR, changed);
2390                         for (i=0 ; i < info->port_count ; i++) {
2391                                 if (info->port_array[i] != NULL)
2392                                         isr_gpio(info->port_array[i], changed, state);
2393                         }
2394                 }
2395                 spin_unlock(&info->lock);
2396         }
2397
2398         for(i=0; i < info->port_count ; i++) {
2399                 struct slgt_info *port = info->port_array[i];
2400                 if (port == NULL)
2401                         continue;
2402                 spin_lock(&port->lock);
2403                 if ((port->port.count || port->netcount) &&
2404                     port->pending_bh && !port->bh_running &&
2405                     !port->bh_requested) {
2406                         DBGISR(("%s bh queued\n", port->device_name));
2407                         schedule_work(&port->task);
2408                         port->bh_requested = true;
2409                 }
2410                 spin_unlock(&port->lock);
2411         }
2412
2413         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2414         return IRQ_HANDLED;
2415 }
2416
2417 static int startup(struct slgt_info *info)
2418 {
2419         DBGINFO(("%s startup\n", info->device_name));
2420
2421         if (info->port.flags & ASYNC_INITIALIZED)
2422                 return 0;
2423
2424         if (!info->tx_buf) {
2425                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2426                 if (!info->tx_buf) {
2427                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2428                         return -ENOMEM;
2429                 }
2430         }
2431
2432         info->pending_bh = 0;
2433
2434         memset(&info->icount, 0, sizeof(info->icount));
2435
2436         /* program hardware for current parameters */
2437         change_params(info);
2438
2439         if (info->port.tty)
2440                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2441
2442         info->port.flags |= ASYNC_INITIALIZED;
2443
2444         return 0;
2445 }
2446
2447 /*
2448  *  called by close() and hangup() to shutdown hardware
2449  */
2450 static void shutdown(struct slgt_info *info)
2451 {
2452         unsigned long flags;
2453
2454         if (!(info->port.flags & ASYNC_INITIALIZED))
2455                 return;
2456
2457         DBGINFO(("%s shutdown\n", info->device_name));
2458
2459         /* clear status wait queue because status changes */
2460         /* can't happen after shutting down the hardware */
2461         wake_up_interruptible(&info->status_event_wait_q);
2462         wake_up_interruptible(&info->event_wait_q);
2463
2464         del_timer_sync(&info->tx_timer);
2465         del_timer_sync(&info->rx_timer);
2466
2467         kfree(info->tx_buf);
2468         info->tx_buf = NULL;
2469
2470         spin_lock_irqsave(&info->lock,flags);
2471
2472         tx_stop(info);
2473         rx_stop(info);
2474
2475         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2476
2477         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2478                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2479                 set_signals(info);
2480         }
2481
2482         flush_cond_wait(&info->gpio_wait_q);
2483
2484         spin_unlock_irqrestore(&info->lock,flags);
2485
2486         if (info->port.tty)
2487                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2488
2489         info->port.flags &= ~ASYNC_INITIALIZED;
2490 }
2491
2492 static void program_hw(struct slgt_info *info)
2493 {
2494         unsigned long flags;
2495
2496         spin_lock_irqsave(&info->lock,flags);
2497
2498         rx_stop(info);
2499         tx_stop(info);
2500
2501         if (info->params.mode != MGSL_MODE_ASYNC ||
2502             info->netcount)
2503                 sync_mode(info);
2504         else
2505                 async_mode(info);
2506
2507         set_signals(info);
2508
2509         info->dcd_chkcount = 0;
2510         info->cts_chkcount = 0;
2511         info->ri_chkcount = 0;
2512         info->dsr_chkcount = 0;
2513
2514         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2515         get_signals(info);
2516
2517         if (info->netcount ||
2518             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2519                 rx_start(info);
2520
2521         spin_unlock_irqrestore(&info->lock,flags);
2522 }
2523
2524 /*
2525  * reconfigure adapter based on new parameters
2526  */
2527 static void change_params(struct slgt_info *info)
2528 {
2529         unsigned cflag;
2530         int bits_per_char;
2531
2532         if (!info->port.tty)
2533                 return;
2534         DBGINFO(("%s change_params\n", info->device_name));
2535
2536         cflag = info->port.tty->termios.c_cflag;
2537
2538         /* if B0 rate (hangup) specified then negate RTS and DTR */
2539         /* otherwise assert RTS and DTR */
2540         if (cflag & CBAUD)
2541                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2542         else
2543                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2544
2545         /* byte size and parity */
2546
2547         switch (cflag & CSIZE) {
2548         case CS5: info->params.data_bits = 5; break;
2549         case CS6: info->params.data_bits = 6; break;
2550         case CS7: info->params.data_bits = 7; break;
2551         case CS8: info->params.data_bits = 8; break;
2552         default:  info->params.data_bits = 7; break;
2553         }
2554
2555         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2556
2557         if (cflag & PARENB)
2558                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2559         else
2560                 info->params.parity = ASYNC_PARITY_NONE;
2561
2562         /* calculate number of jiffies to transmit a full
2563          * FIFO (32 bytes) at specified data rate
2564          */
2565         bits_per_char = info->params.data_bits +
2566                         info->params.stop_bits + 1;
2567
2568         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2569
2570         if (info->params.data_rate) {
2571                 info->timeout = (32*HZ*bits_per_char) /
2572                                 info->params.data_rate;
2573         }
2574         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2575
2576         if (cflag & CRTSCTS)
2577                 info->port.flags |= ASYNC_CTS_FLOW;
2578         else
2579                 info->port.flags &= ~ASYNC_CTS_FLOW;
2580
2581         if (cflag & CLOCAL)
2582                 info->port.flags &= ~ASYNC_CHECK_CD;
2583         else
2584                 info->port.flags |= ASYNC_CHECK_CD;
2585
2586         /* process tty input control flags */
2587
2588         info->read_status_mask = IRQ_RXOVER;
2589         if (I_INPCK(info->port.tty))
2590                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2591         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2592                 info->read_status_mask |= MASK_BREAK;
2593         if (I_IGNPAR(info->port.tty))
2594                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2595         if (I_IGNBRK(info->port.tty)) {
2596                 info->ignore_status_mask |= MASK_BREAK;
2597                 /* If ignoring parity and break indicators, ignore
2598                  * overruns too.  (For real raw support).
2599                  */
2600                 if (I_IGNPAR(info->port.tty))
2601                         info->ignore_status_mask |= MASK_OVERRUN;
2602         }
2603
2604         program_hw(info);
2605 }
2606
2607 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2608 {
2609         DBGINFO(("%s get_stats\n",  info->device_name));
2610         if (!user_icount) {
2611                 memset(&info->icount, 0, sizeof(info->icount));
2612         } else {
2613                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2614                         return -EFAULT;
2615         }
2616         return 0;
2617 }
2618
2619 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2620 {
2621         DBGINFO(("%s get_params\n", info->device_name));
2622         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2623                 return -EFAULT;
2624         return 0;
2625 }
2626
2627 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2628 {
2629         unsigned long flags;
2630         MGSL_PARAMS tmp_params;
2631
2632         DBGINFO(("%s set_params\n", info->device_name));
2633         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2634                 return -EFAULT;
2635
2636         spin_lock_irqsave(&info->lock, flags);
2637         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2638                 info->base_clock = tmp_params.clock_speed;
2639         else
2640                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2641         spin_unlock_irqrestore(&info->lock, flags);
2642
2643         program_hw(info);
2644
2645         return 0;
2646 }
2647
2648 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2649 {
2650         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2651         if (put_user(info->idle_mode, idle_mode))
2652                 return -EFAULT;
2653         return 0;
2654 }
2655
2656 static int set_txidle(struct slgt_info *info, int idle_mode)
2657 {
2658         unsigned long flags;
2659         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2660         spin_lock_irqsave(&info->lock,flags);
2661         info->idle_mode = idle_mode;
2662         if (info->params.mode != MGSL_MODE_ASYNC)
2663                 tx_set_idle(info);
2664         spin_unlock_irqrestore(&info->lock,flags);
2665         return 0;
2666 }
2667
2668 static int tx_enable(struct slgt_info *info, int enable)
2669 {
2670         unsigned long flags;
2671         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2672         spin_lock_irqsave(&info->lock,flags);
2673         if (enable) {
2674                 if (!info->tx_enabled)
2675                         tx_start(info);
2676         } else {
2677                 if (info->tx_enabled)
2678                         tx_stop(info);
2679         }
2680         spin_unlock_irqrestore(&info->lock,flags);
2681         return 0;
2682 }
2683
2684 /*
2685  * abort transmit HDLC frame
2686  */
2687 static int tx_abort(struct slgt_info *info)
2688 {
2689         unsigned long flags;
2690         DBGINFO(("%s tx_abort\n", info->device_name));
2691         spin_lock_irqsave(&info->lock,flags);
2692         tdma_reset(info);
2693         spin_unlock_irqrestore(&info->lock,flags);
2694         return 0;
2695 }
2696
2697 static int rx_enable(struct slgt_info *info, int enable)
2698 {
2699         unsigned long flags;
2700         unsigned int rbuf_fill_level;
2701         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2702         spin_lock_irqsave(&info->lock,flags);
2703         /*
2704          * enable[31..16] = receive DMA buffer fill level
2705          * 0 = noop (leave fill level unchanged)
2706          * fill level must be multiple of 4 and <= buffer size
2707          */
2708         rbuf_fill_level = ((unsigned int)enable) >> 16;
2709         if (rbuf_fill_level) {
2710                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2711                         spin_unlock_irqrestore(&info->lock, flags);
2712                         return -EINVAL;
2713                 }
2714                 info->rbuf_fill_level = rbuf_fill_level;
2715                 if (rbuf_fill_level < 128)
2716                         info->rx_pio = 1; /* PIO mode */
2717                 else
2718                         info->rx_pio = 0; /* DMA mode */
2719                 rx_stop(info); /* restart receiver to use new fill level */
2720         }
2721
2722         /*
2723          * enable[1..0] = receiver enable command
2724          * 0 = disable
2725          * 1 = enable
2726          * 2 = enable or force hunt mode if already enabled
2727          */
2728         enable &= 3;
2729         if (enable) {
2730                 if (!info->rx_enabled)
2731                         rx_start(info);
2732                 else if (enable == 2) {
2733                         /* force hunt mode (write 1 to RCR[3]) */
2734                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2735                 }
2736         } else {
2737                 if (info->rx_enabled)
2738                         rx_stop(info);
2739         }
2740         spin_unlock_irqrestore(&info->lock,flags);
2741         return 0;
2742 }
2743
2744 /*
2745  *  wait for specified event to occur
2746  */
2747 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2748 {
2749         unsigned long flags;
2750         int s;
2751         int rc=0;
2752         struct mgsl_icount cprev, cnow;
2753         int events;
2754         int mask;
2755         struct  _input_signal_events oldsigs, newsigs;
2756         DECLARE_WAITQUEUE(wait, current);
2757
2758         if (get_user(mask, mask_ptr))
2759                 return -EFAULT;
2760
2761         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2762
2763         spin_lock_irqsave(&info->lock,flags);
2764
2765         /* return immediately if state matches requested events */
2766         get_signals(info);
2767         s = info->signals;
2768
2769         events = mask &
2770                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2771                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2772                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2773                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2774         if (events) {
2775                 spin_unlock_irqrestore(&info->lock,flags);
2776                 goto exit;
2777         }
2778
2779         /* save current irq counts */
2780         cprev = info->icount;
2781         oldsigs = info->input_signal_events;
2782
2783         /* enable hunt and idle irqs if needed */
2784         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2785                 unsigned short val = rd_reg16(info, SCR);
2786                 if (!(val & IRQ_RXIDLE))
2787                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2788         }
2789
2790         set_current_state(TASK_INTERRUPTIBLE);
2791         add_wait_queue(&info->event_wait_q, &wait);
2792
2793         spin_unlock_irqrestore(&info->lock,flags);
2794
2795         for(;;) {
2796                 schedule();
2797                 if (signal_pending(current)) {
2798                         rc = -ERESTARTSYS;
2799                         break;
2800                 }
2801
2802                 /* get current irq counts */
2803                 spin_lock_irqsave(&info->lock,flags);
2804                 cnow = info->icount;
2805                 newsigs = info->input_signal_events;
2806                 set_current_state(TASK_INTERRUPTIBLE);
2807                 spin_unlock_irqrestore(&info->lock,flags);
2808
2809                 /* if no change, wait aborted for some reason */
2810                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2811                     newsigs.dsr_down == oldsigs.dsr_down &&
2812                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2813                     newsigs.dcd_down == oldsigs.dcd_down &&
2814                     newsigs.cts_up   == oldsigs.cts_up   &&
2815                     newsigs.cts_down == oldsigs.cts_down &&
2816                     newsigs.ri_up    == oldsigs.ri_up    &&
2817                     newsigs.ri_down  == oldsigs.ri_down  &&
2818                     cnow.exithunt    == cprev.exithunt   &&
2819                     cnow.rxidle      == cprev.rxidle) {
2820                         rc = -EIO;
2821                         break;
2822                 }
2823
2824                 events = mask &
2825                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2826                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2827                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2828                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2829                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2830                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2831                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2832                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2833                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2834                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2835                 if (events)
2836                         break;
2837
2838                 cprev = cnow;
2839                 oldsigs = newsigs;
2840         }
2841
2842         remove_wait_queue(&info->event_wait_q, &wait);
2843         set_current_state(TASK_RUNNING);
2844
2845
2846         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2847                 spin_lock_irqsave(&info->lock,flags);
2848                 if (!waitqueue_active(&info->event_wait_q)) {
2849                         /* disable enable exit hunt mode/idle rcvd IRQs */
2850                         wr_reg16(info, SCR,
2851                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2852                 }
2853                 spin_unlock_irqrestore(&info->lock,flags);
2854         }
2855 exit:
2856         if (rc == 0)
2857                 rc = put_user(events, mask_ptr);
2858         return rc;
2859 }
2860
2861 static int get_interface(struct slgt_info *info, int __user *if_mode)
2862 {
2863         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2864         if (put_user(info->if_mode, if_mode))
2865                 return -EFAULT;
2866         return 0;
2867 }
2868
2869 static int set_interface(struct slgt_info *info, int if_mode)
2870 {
2871         unsigned long flags;
2872         unsigned short val;
2873
2874         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2875         spin_lock_irqsave(&info->lock,flags);
2876         info->if_mode = if_mode;
2877
2878         msc_set_vcr(info);
2879
2880         /* TCR (tx control) 07  1=RTS driver control */
2881         val = rd_reg16(info, TCR);
2882         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2883                 val |= BIT7;
2884         else
2885                 val &= ~BIT7;
2886         wr_reg16(info, TCR, val);
2887
2888         spin_unlock_irqrestore(&info->lock,flags);
2889         return 0;
2890 }
2891
2892 static int get_xsync(struct slgt_info *info, int __user *xsync)
2893 {
2894         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2895         if (put_user(info->xsync, xsync))
2896                 return -EFAULT;
2897         return 0;
2898 }
2899
2900 /*
2901  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2902  *
2903  * sync pattern is contained in least significant bytes of value
2904  * most significant byte of sync pattern is oldest (1st sent/detected)
2905  */
2906 static int set_xsync(struct slgt_info *info, int xsync)
2907 {
2908         unsigned long flags;
2909
2910         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2911         spin_lock_irqsave(&info->lock, flags);
2912         info->xsync = xsync;
2913         wr_reg32(info, XSR, xsync);
2914         spin_unlock_irqrestore(&info->lock, flags);
2915         return 0;
2916 }
2917
2918 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2919 {
2920         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2921         if (put_user(info->xctrl, xctrl))
2922                 return -EFAULT;
2923         return 0;
2924 }
2925
2926 /*
2927  * set extended control options
2928  *
2929  * xctrl[31:19] reserved, must be zero
2930  * xctrl[18:17] extended sync pattern length in bytes
2931  *              00 = 1 byte  in xsr[7:0]
2932  *              01 = 2 bytes in xsr[15:0]
2933  *              10 = 3 bytes in xsr[23:0]
2934  *              11 = 4 bytes in xsr[31:0]
2935  * xctrl[16]    1 = enable terminal count, 0=disabled
2936  * xctrl[15:0]  receive terminal count for fixed length packets
2937  *              value is count minus one (0 = 1 byte packet)
2938  *              when terminal count is reached, receiver
2939  *              automatically returns to hunt mode and receive
2940  *              FIFO contents are flushed to DMA buffers with
2941  *              end of frame (EOF) status
2942  */
2943 static int set_xctrl(struct slgt_info *info, int xctrl)
2944 {
2945         unsigned long flags;
2946
2947         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2948         spin_lock_irqsave(&info->lock, flags);
2949         info->xctrl = xctrl;
2950         wr_reg32(info, XCR, xctrl);
2951         spin_unlock_irqrestore(&info->lock, flags);
2952         return 0;
2953 }
2954
2955 /*
2956  * set general purpose IO pin state and direction
2957  *
2958  * user_gpio fields:
2959  * state   each bit indicates a pin state
2960  * smask   set bit indicates pin state to set
2961  * dir     each bit indicates a pin direction (0=input, 1=output)
2962  * dmask   set bit indicates pin direction to set
2963  */
2964 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2965 {
2966         unsigned long flags;
2967         struct gpio_desc gpio;
2968         __u32 data;
2969
2970         if (!info->gpio_present)
2971                 return -EINVAL;
2972         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2973                 return -EFAULT;
2974         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2975                  info->device_name, gpio.state, gpio.smask,
2976                  gpio.dir, gpio.dmask));
2977
2978         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2979         if (gpio.dmask) {
2980                 data = rd_reg32(info, IODR);
2981                 data |= gpio.dmask & gpio.dir;
2982                 data &= ~(gpio.dmask & ~gpio.dir);
2983                 wr_reg32(info, IODR, data);
2984         }
2985         if (gpio.smask) {
2986                 data = rd_reg32(info, IOVR);
2987                 data |= gpio.smask & gpio.state;
2988                 data &= ~(gpio.smask & ~gpio.state);
2989                 wr_reg32(info, IOVR, data);
2990         }
2991         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2992
2993         return 0;
2994 }
2995
2996 /*
2997  * get general purpose IO pin state and direction
2998  */
2999 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3000 {
3001         struct gpio_desc gpio;
3002         if (!info->gpio_present)
3003                 return -EINVAL;
3004         gpio.state = rd_reg32(info, IOVR);
3005         gpio.smask = 0xffffffff;
3006         gpio.dir   = rd_reg32(info, IODR);
3007         gpio.dmask = 0xffffffff;
3008         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3009                 return -EFAULT;
3010         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3011                  info->device_name, gpio.state, gpio.dir));
3012         return 0;
3013 }
3014
3015 /*
3016  * conditional wait facility
3017  */
3018 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3019 {
3020         init_waitqueue_head(&w->q);
3021         init_waitqueue_entry(&w->wait, current);
3022         w->data = data;
3023 }
3024
3025 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3026 {
3027         set_current_state(TASK_INTERRUPTIBLE);
3028         add_wait_queue(&w->q, &w->wait);
3029         w->next = *head;
3030         *head = w;
3031 }
3032
3033 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3034 {
3035         struct cond_wait *w, *prev;
3036         remove_wait_queue(&cw->q, &cw->wait);
3037         set_current_state(TASK_RUNNING);
3038         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3039                 if (w == cw) {
3040                         if (prev != NULL)
3041                                 prev->next = w->next;
3042                         else
3043                                 *head = w->next;
3044                         break;
3045                 }
3046         }
3047 }
3048
3049 static void flush_cond_wait(struct cond_wait **head)
3050 {
3051         while (*head != NULL) {
3052                 wake_up_interruptible(&(*head)->q);
3053                 *head = (*head)->next;
3054         }
3055 }
3056
3057 /*
3058  * wait for general purpose I/O pin(s) to enter specified state
3059  *
3060  * user_gpio fields:
3061  * state - bit indicates target pin state
3062  * smask - set bit indicates watched pin
3063  *
3064  * The wait ends when at least one watched pin enters the specified
3065  * state. When 0 (no error) is returned, user_gpio->state is set to the
3066  * state of all GPIO pins when the wait ends.
3067  *
3068  * Note: Each pin may be a dedicated input, dedicated output, or
3069  * configurable input/output. The number and configuration of pins
3070  * varies with the specific adapter model. Only input pins (dedicated
3071  * or configured) can be monitored with this function.
3072  */
3073 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3074 {
3075         unsigned long flags;
3076         int rc = 0;
3077         struct gpio_desc gpio;
3078         struct cond_wait wait;
3079         u32 state;
3080
3081         if (!info->gpio_present)
3082                 return -EINVAL;
3083         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3084                 return -EFAULT;
3085         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3086                  info->device_name, gpio.state, gpio.smask));
3087         /* ignore output pins identified by set IODR bit */
3088         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3089                 return -EINVAL;
3090         init_cond_wait(&wait, gpio.smask);
3091
3092         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3093         /* enable interrupts for watched pins */
3094         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3095         /* get current pin states */
3096         state = rd_reg32(info, IOVR);
3097
3098         if (gpio.smask & ~(state ^ gpio.state)) {
3099                 /* already in target state */
3100                 gpio.state = state;
3101         } else {
3102                 /* wait for target state */
3103                 add_cond_wait(&info->gpio_wait_q, &wait);
3104                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3105                 schedule();
3106                 if (signal_pending(current))
3107                         rc = -ERESTARTSYS;
3108                 else
3109                         gpio.state = wait.data;
3110                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3111                 remove_cond_wait(&info->gpio_wait_q, &wait);
3112         }
3113
3114         /* disable all GPIO interrupts if no waiting processes */
3115         if (info->gpio_wait_q == NULL)
3116                 wr_reg32(info, IOER, 0);
3117         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3118
3119         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3120                 rc = -EFAULT;
3121         return rc;
3122 }
3123
3124 static int modem_input_wait(struct slgt_info *info,int arg)
3125 {
3126         unsigned long flags;
3127         int rc;
3128         struct mgsl_icount cprev, cnow;
3129         DECLARE_WAITQUEUE(wait, current);
3130
3131         /* save current irq counts */
3132         spin_lock_irqsave(&info->lock,flags);
3133         cprev = info->icount;
3134         add_wait_queue(&info->status_event_wait_q, &wait);
3135         set_current_state(TASK_INTERRUPTIBLE);
3136         spin_unlock_irqrestore(&info->lock,flags);
3137
3138         for(;;) {
3139                 schedule();
3140                 if (signal_pending(current)) {
3141                         rc = -ERESTARTSYS;
3142                         break;
3143                 }
3144
3145                 /* get new irq counts */
3146                 spin_lock_irqsave(&info->lock,flags);
3147                 cnow = info->icount;
3148                 set_current_state(TASK_INTERRUPTIBLE);
3149                 spin_unlock_irqrestore(&info->lock,flags);
3150
3151                 /* if no change, wait aborted for some reason */
3152                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3153                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3154                         rc = -EIO;
3155                         break;
3156                 }
3157
3158                 /* check for change in caller specified modem input */
3159                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3160                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3161                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3162                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3163                         rc = 0;
3164                         break;
3165                 }
3166
3167                 cprev = cnow;
3168         }
3169         remove_wait_queue(&info->status_event_wait_q, &wait);
3170         set_current_state(TASK_RUNNING);
3171         return rc;
3172 }
3173
3174 /*
3175  *  return state of serial control and status signals
3176  */
3177 static int tiocmget(struct tty_struct *tty)
3178 {
3179         struct slgt_info *info = tty->driver_data;
3180         unsigned int result;
3181         unsigned long flags;
3182
3183         spin_lock_irqsave(&info->lock,flags);
3184         get_signals(info);
3185         spin_unlock_irqrestore(&info->lock,flags);
3186
3187         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3188                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3189                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3190                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3191                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3192                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3193
3194         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3195         return result;
3196 }
3197
3198 /*
3199  * set modem control signals (DTR/RTS)
3200  *
3201  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3202  *              TIOCMSET = set/clear signal values
3203  *      value   bit mask for command
3204  */
3205 static int tiocmset(struct tty_struct *tty,
3206                     unsigned int set, unsigned int clear)
3207 {
3208         struct slgt_info *info = tty->driver_data;
3209         unsigned long flags;
3210
3211         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3212
3213         if (set & TIOCM_RTS)
3214                 info->signals |= SerialSignal_RTS;
3215         if (set & TIOCM_DTR)
3216                 info->signals |= SerialSignal_DTR;
3217         if (clear & TIOCM_RTS)
3218                 info->signals &= ~SerialSignal_RTS;
3219         if (clear & TIOCM_DTR)
3220                 info->signals &= ~SerialSignal_DTR;
3221
3222         spin_lock_irqsave(&info->lock,flags);
3223         set_signals(info);
3224         spin_unlock_irqrestore(&info->lock,flags);
3225         return 0;
3226 }
3227
3228 static int carrier_raised(struct tty_port *port)
3229 {
3230         unsigned long flags;
3231         struct slgt_info *info = container_of(port, struct slgt_info, port);
3232
3233         spin_lock_irqsave(&info->lock,flags);
3234         get_signals(info);
3235         spin_unlock_irqrestore(&info->lock,flags);
3236         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3237 }
3238
3239 static void dtr_rts(struct tty_port *port, int on)
3240 {
3241         unsigned long flags;
3242         struct slgt_info *info = container_of(port, struct slgt_info, port);
3243
3244         spin_lock_irqsave(&info->lock,flags);
3245         if (on)
3246                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3247         else
3248                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3249         set_signals(info);
3250         spin_unlock_irqrestore(&info->lock,flags);
3251 }
3252
3253
3254 /*
3255  *  block current process until the device is ready to open
3256  */
3257 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3258                            struct slgt_info *info)
3259 {
3260         DECLARE_WAITQUEUE(wait, current);
3261         int             retval;
3262         bool            do_clocal = false;
3263         unsigned long   flags;
3264         int             cd;
3265         struct tty_port *port = &info->port;
3266
3267         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3268
3269         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3270                 /* nonblock mode is set or port is not enabled */
3271                 port->flags |= ASYNC_NORMAL_ACTIVE;
3272                 return 0;
3273         }
3274
3275         if (tty->termios.c_cflag & CLOCAL)
3276                 do_clocal = true;
3277
3278         /* Wait for carrier detect and the line to become
3279          * free (i.e., not in use by the callout).  While we are in
3280          * this loop, port->count is dropped by one, so that
3281          * close() knows when to free things.  We restore it upon
3282          * exit, either normal or abnormal.
3283          */
3284
3285         retval = 0;
3286         add_wait_queue(&port->open_wait, &wait);
3287
3288         spin_lock_irqsave(&info->lock, flags);
3289         port->count--;
3290         spin_unlock_irqrestore(&info->lock, flags);
3291         port->blocked_open++;
3292
3293         while (1) {
3294                 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3295                         tty_port_raise_dtr_rts(port);
3296
3297                 set_current_state(TASK_INTERRUPTIBLE);
3298
3299                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3300                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3301                                         -EAGAIN : -ERESTARTSYS;
3302                         break;
3303                 }
3304
3305                 cd = tty_port_carrier_raised(port);
3306                 if (do_clocal || cd)
3307                         break;
3308
3309                 if (signal_pending(current)) {
3310                         retval = -ERESTARTSYS;
3311                         break;
3312                 }
3313
3314                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3315                 tty_unlock(tty);
3316                 schedule();
3317                 tty_lock(tty);
3318         }
3319
3320         set_current_state(TASK_RUNNING);
3321         remove_wait_queue(&port->open_wait, &wait);
3322
3323         if (!tty_hung_up_p(filp))
3324                 port->count++;
3325         port->blocked_open--;
3326
3327         if (!retval)
3328                 port->flags |= ASYNC_NORMAL_ACTIVE;
3329
3330         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3331         return retval;
3332 }
3333
3334 /*
3335  * allocate buffers used for calling line discipline receive_buf
3336  * directly in synchronous mode
3337  * note: add 5 bytes to max frame size to allow appending
3338  * 32-bit CRC and status byte when configured to do so
3339  */
3340 static int alloc_tmp_rbuf(struct slgt_info *info)
3341 {
3342         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3343         if (info->tmp_rbuf == NULL)
3344                 return -ENOMEM;
3345         /* unused flag buffer to satisfy receive_buf calling interface */
3346         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3347         if (!info->flag_buf) {
3348                 kfree(info->tmp_rbuf);
3349                 info->tmp_rbuf = NULL;
3350                 return -ENOMEM;
3351         }
3352         return 0;
3353 }
3354
3355 static void free_tmp_rbuf(struct slgt_info *info)
3356 {
3357         kfree(info->tmp_rbuf);
3358         info->tmp_rbuf = NULL;
3359         kfree(info->flag_buf);
3360         info->flag_buf = NULL;
3361 }
3362
3363 /*
3364  * allocate DMA descriptor lists.
3365  */
3366 static int alloc_desc(struct slgt_info *info)
3367 {
3368         unsigned int i;
3369         unsigned int pbufs;
3370
3371         /* allocate memory to hold descriptor lists */
3372         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3373                                            &info->bufs_dma_addr);
3374         if (info->bufs == NULL)
3375                 return -ENOMEM;
3376
3377         info->rbufs = (struct slgt_desc*)info->bufs;
3378         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3379
3380         pbufs = (unsigned int)info->bufs_dma_addr;
3381
3382         /*
3383          * Build circular lists of descriptors
3384          */
3385
3386         for (i=0; i < info->rbuf_count; i++) {
3387                 /* physical address of this descriptor */
3388                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3389
3390                 /* physical address of next descriptor */
3391                 if (i == info->rbuf_count - 1)
3392                         info->rbufs[i].next = cpu_to_le32(pbufs);
3393                 else
3394                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3395                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3396         }
3397
3398         for (i=0; i < info->tbuf_count; i++) {
3399                 /* physical address of this descriptor */
3400                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3401
3402                 /* physical address of next descriptor */
3403                 if (i == info->tbuf_count - 1)
3404                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3405                 else
3406                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3407         }
3408
3409         return 0;
3410 }
3411
3412 static void free_desc(struct slgt_info *info)
3413 {
3414         if (info->bufs != NULL) {
3415                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3416                 info->bufs  = NULL;
3417                 info->rbufs = NULL;
3418                 info->tbufs = NULL;
3419         }
3420 }
3421
3422 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3423 {
3424         int i;
3425         for (i=0; i < count; i++) {
3426                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3427                         return -ENOMEM;
3428                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3429         }
3430         return 0;
3431 }
3432
3433 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3434 {
3435         int i;
3436         for (i=0; i < count; i++) {
3437                 if (bufs[i].buf == NULL)
3438                         continue;
3439                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3440                 bufs[i].buf = NULL;
3441         }
3442 }
3443
3444 static int alloc_dma_bufs(struct slgt_info *info)
3445 {
3446         info->rbuf_count = 32;
3447         info->tbuf_count = 32;
3448
3449         if (alloc_desc(info) < 0 ||
3450             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3451             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3452             alloc_tmp_rbuf(info) < 0) {
3453                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3454                 return -ENOMEM;
3455         }
3456         reset_rbufs(info);
3457         return 0;
3458 }
3459
3460 static void free_dma_bufs(struct slgt_info *info)
3461 {
3462         if (info->bufs) {
3463                 free_bufs(info, info->rbufs, info->rbuf_count);
3464                 free_bufs(info, info->tbufs, info->tbuf_count);
3465                 free_desc(info);
3466         }
3467         free_tmp_rbuf(info);
3468 }
3469
3470 static int claim_resources(struct slgt_info *info)
3471 {
3472         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3473                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3474                         info->device_name, info->phys_reg_addr));
3475                 info->init_error = DiagStatus_AddressConflict;
3476                 goto errout;
3477         }
3478         else
3479                 info->reg_addr_requested = true;
3480
3481         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3482         if (!info->reg_addr) {
3483                 DBGERR(("%s can't map device registers, addr=%08X\n",
3484                         info->device_name, info->phys_reg_addr));
3485                 info->init_error = DiagStatus_CantAssignPciResources;
3486                 goto errout;
3487         }
3488         return 0;
3489
3490 errout:
3491         release_resources(info);
3492         return -ENODEV;
3493 }
3494
3495 static void release_resources(struct slgt_info *info)
3496 {
3497         if (info->irq_requested) {
3498                 free_irq(info->irq_level, info);
3499                 info->irq_requested = false;
3500         }
3501
3502         if (info->reg_addr_requested) {
3503                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3504                 info->reg_addr_requested = false;
3505         }
3506
3507         if (info->reg_addr) {
3508                 iounmap(info->reg_addr);
3509                 info->reg_addr = NULL;
3510         }
3511 }
3512
3513 /* Add the specified device instance data structure to the
3514  * global linked list of devices and increment the device count.
3515  */
3516 static void add_device(struct slgt_info *info)
3517 {
3518         char *devstr;
3519
3520         info->next_device = NULL;
3521         info->line = slgt_device_count;
3522         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3523
3524         if (info->line < MAX_DEVICES) {
3525                 if (maxframe[info->line])
3526                         info->max_frame_size = maxframe[info->line];
3527         }
3528
3529         slgt_device_count++;
3530
3531         if (!slgt_device_list)
3532                 slgt_device_list = info;
3533         else {
3534                 struct slgt_info *current_dev = slgt_device_list;
3535                 while(current_dev->next_device)
3536                         current_dev = current_dev->next_device;
3537                 current_dev->next_device = info;
3538         }
3539
3540         if (info->max_frame_size < 4096)
3541                 info->max_frame_size = 4096;
3542         else if (info->max_frame_size > 65535)
3543                 info->max_frame_size = 65535;
3544
3545         switch(info->pdev->device) {
3546         case SYNCLINK_GT_DEVICE_ID:
3547                 devstr = "GT";
3548                 break;
3549         case SYNCLINK_GT2_DEVICE_ID:
3550                 devstr = "GT2";
3551                 break;
3552         case SYNCLINK_GT4_DEVICE_ID:
3553                 devstr = "GT4";
3554                 break;
3555         case SYNCLINK_AC_DEVICE_ID:
3556                 devstr = "AC";
3557                 info->params.mode = MGSL_MODE_ASYNC;
3558                 break;
3559         default:
3560                 devstr = "(unknown model)";
3561         }
3562         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3563                 devstr, info->device_name, info->phys_reg_addr,
3564                 info->irq_level, info->max_frame_size);
3565
3566 #if SYNCLINK_GENERIC_HDLC
3567         hdlcdev_init(info);
3568 #endif
3569 }
3570
3571 static const struct tty_port_operations slgt_port_ops = {
3572         .carrier_raised = carrier_raised,
3573         .dtr_rts = dtr_rts,
3574 };
3575
3576 /*
3577  *  allocate device instance structure, return NULL on failure
3578  */
3579 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3580 {
3581         struct slgt_info *info;
3582
3583         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3584
3585         if (!info) {
3586                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3587                         driver_name, adapter_num, port_num));
3588         } else {
3589                 tty_port_init(&info->port);
3590                 info->port.ops = &slgt_port_ops;
3591                 info->magic = MGSL_MAGIC;
3592                 INIT_WORK(&info->task, bh_handler);
3593                 info->max_frame_size = 4096;
3594                 info->base_clock = 14745600;
3595                 info->rbuf_fill_level = DMABUFSIZE;
3596                 info->port.close_delay = 5*HZ/10;
3597                 info->port.closing_wait = 30*HZ;
3598                 init_waitqueue_head(&info->status_event_wait_q);
3599                 init_waitqueue_head(&info->event_wait_q);
3600                 spin_lock_init(&info->netlock);
3601                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3602                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3603                 info->adapter_num = adapter_num;
3604                 info->port_num = port_num;
3605
3606                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3607                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3608
3609                 /* Copy configuration info to device instance data */
3610                 info->pdev = pdev;
3611                 info->irq_level = pdev->irq;
3612                 info->phys_reg_addr = pci_resource_start(pdev,0);
3613
3614                 info->bus_type = MGSL_BUS_TYPE_PCI;
3615                 info->irq_flags = IRQF_SHARED;
3616
3617                 info->init_error = -1; /* assume error, set to 0 on successful init */
3618         }
3619
3620         return info;
3621 }
3622
3623 static void device_init(int adapter_num, struct pci_dev *pdev)
3624 {
3625         struct slgt_info *port_array[SLGT_MAX_PORTS];
3626         int i;
3627         int port_count = 1;
3628
3629         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3630                 port_count = 2;
3631         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3632                 port_count = 4;
3633
3634         /* allocate device instances for all ports */
3635         for (i=0; i < port_count; ++i) {
3636                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3637                 if (port_array[i] == NULL) {
3638                         for (--i; i >= 0; --i) {
3639                                 tty_port_destroy(&port_array[i]->port);
3640                                 kfree(port_array[i]);
3641                         }
3642                         return;
3643                 }
3644         }
3645
3646         /* give copy of port_array to all ports and add to device list  */
3647         for (i=0; i < port_count; ++i) {
3648                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3649                 add_device(port_array[i]);
3650                 port_array[i]->port_count = port_count;
3651                 spin_lock_init(&port_array[i]->lock);
3652         }
3653
3654         /* Allocate and claim adapter resources */
3655         if (!claim_resources(port_array[0])) {
3656
3657                 alloc_dma_bufs(port_array[0]);
3658
3659                 /* copy resource information from first port to others */
3660                 for (i = 1; i < port_count; ++i) {
3661                         port_array[i]->irq_level = port_array[0]->irq_level;
3662                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3663                         alloc_dma_bufs(port_array[i]);
3664                 }
3665
3666                 if (request_irq(port_array[0]->irq_level,
3667                                         slgt_interrupt,
3668                                         port_array[0]->irq_flags,
3669                                         port_array[0]->device_name,
3670                                         port_array[0]) < 0) {
3671                         DBGERR(("%s request_irq failed IRQ=%d\n",
3672                                 port_array[0]->device_name,
3673                                 port_array[0]->irq_level));
3674                 } else {
3675                         port_array[0]->irq_requested = true;
3676                         adapter_test(port_array[0]);
3677                         for (i=1 ; i < port_count ; i++) {
3678                                 port_array[i]->init_error = port_array[0]->init_error;
3679                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3680                         }
3681                 }
3682         }
3683
3684         for (i = 0; i < port_count; ++i) {
3685                 struct slgt_info *info = port_array[i];
3686                 tty_port_register_device(&info->port, serial_driver, info->line,
3687                                 &info->pdev->dev);
3688         }
3689 }
3690
3691 static int init_one(struct pci_dev *dev,
3692                               const struct pci_device_id *ent)
3693 {
3694         if (pci_enable_device(dev)) {
3695                 printk("error enabling pci device %p\n", dev);
3696                 return -EIO;
3697         }
3698         pci_set_master(dev);
3699         device_init(slgt_device_count, dev);
3700         return 0;
3701 }
3702
3703 static void remove_one(struct pci_dev *dev)
3704 {
3705 }
3706
3707 static const struct tty_operations ops = {
3708         .open = open,
3709         .close = close,
3710         .write = write,
3711         .put_char = put_char,
3712         .flush_chars = flush_chars,
3713         .write_room = write_room,
3714         .chars_in_buffer = chars_in_buffer,
3715         .flush_buffer = flush_buffer,
3716         .ioctl = ioctl,
3717         .compat_ioctl = slgt_compat_ioctl,
3718         .throttle = throttle,
3719         .unthrottle = unthrottle,
3720         .send_xchar = send_xchar,
3721         .break_ctl = set_break,
3722         .wait_until_sent = wait_until_sent,
3723         .set_termios = set_termios,
3724         .stop = tx_hold,
3725         .start = tx_release,
3726         .hangup = hangup,
3727         .tiocmget = tiocmget,
3728         .tiocmset = tiocmset,
3729         .get_icount = get_icount,
3730         .proc_fops = &synclink_gt_proc_fops,
3731 };
3732
3733 static void slgt_cleanup(void)
3734 {
3735         int rc;
3736         struct slgt_info *info;
3737         struct slgt_info *tmp;
3738
3739         printk(KERN_INFO "unload %s\n", driver_name);
3740
3741         if (serial_driver) {
3742                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3743                         tty_unregister_device(serial_driver, info->line);
3744                 rc = tty_unregister_driver(serial_driver);
3745                 if (rc)
3746                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3747                 put_tty_driver(serial_driver);
3748         }
3749
3750         /* reset devices */
3751         info = slgt_device_list;
3752         while(info) {
3753                 reset_port(info);
3754                 info = info->next_device;
3755         }
3756
3757         /* release devices */
3758         info = slgt_device_list;
3759         while(info) {
3760 #if SYNCLINK_GENERIC_HDLC
3761                 hdlcdev_exit(info);
3762 #endif
3763                 free_dma_bufs(info);
3764                 free_tmp_rbuf(info);
3765                 if (info->port_num == 0)
3766                         release_resources(info);
3767                 tmp = info;
3768                 info = info->next_device;
3769                 tty_port_destroy(&tmp->port);
3770                 kfree(tmp);
3771         }
3772
3773         if (pci_registered)
3774                 pci_unregister_driver(&pci_driver);
3775 }
3776
3777 /*
3778  *  Driver initialization entry point.
3779  */
3780 static int __init slgt_init(void)
3781 {
3782         int rc;
3783
3784         printk(KERN_INFO "%s\n", driver_name);
3785
3786         serial_driver = alloc_tty_driver(MAX_DEVICES);
3787         if (!serial_driver) {
3788                 printk("%s can't allocate tty driver\n", driver_name);
3789                 return -ENOMEM;
3790         }
3791
3792         /* Initialize the tty_driver structure */
3793
3794         serial_driver->driver_name = tty_driver_name;
3795         serial_driver->name = tty_dev_prefix;
3796         serial_driver->major = ttymajor;
3797         serial_driver->minor_start = 64;
3798         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3799         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3800         serial_driver->init_termios = tty_std_termios;
3801         serial_driver->init_termios.c_cflag =
3802                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3803         serial_driver->init_termios.c_ispeed = 9600;
3804         serial_driver->init_termios.c_ospeed = 9600;
3805         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3806         tty_set_operations(serial_driver, &ops);
3807         if ((rc = tty_register_driver(serial_driver)) < 0) {
3808                 DBGERR(("%s can't register serial driver\n", driver_name));
3809                 put_tty_driver(serial_driver);
3810                 serial_driver = NULL;
3811                 goto error;
3812         }
3813
3814         printk(KERN_INFO "%s, tty major#%d\n",
3815                driver_name, serial_driver->major);
3816
3817         slgt_device_count = 0;
3818         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3819                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3820                 goto error;
3821         }
3822         pci_registered = true;
3823
3824         if (!slgt_device_list)
3825                 printk("%s no devices found\n",driver_name);
3826
3827         return 0;
3828
3829 error:
3830         slgt_cleanup();
3831         return rc;
3832 }
3833
3834 static void __exit slgt_exit(void)
3835 {
3836         slgt_cleanup();
3837 }
3838
3839 module_init(slgt_init);
3840 module_exit(slgt_exit);
3841
3842 /*
3843  * register access routines
3844  */
3845
3846 #define CALC_REGADDR() \
3847         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3848         if (addr >= 0x80) \
3849                 reg_addr += (info->port_num) * 32; \
3850         else if (addr >= 0x40)  \
3851                 reg_addr += (info->port_num) * 16;
3852
3853 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3854 {
3855         CALC_REGADDR();
3856         return readb((void __iomem *)reg_addr);
3857 }
3858
3859 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3860 {
3861         CALC_REGADDR();
3862         writeb(value, (void __iomem *)reg_addr);
3863 }
3864
3865 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3866 {
3867         CALC_REGADDR();
3868         return readw((void __iomem *)reg_addr);
3869 }
3870
3871 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3872 {
3873         CALC_REGADDR();
3874         writew(value, (void __iomem *)reg_addr);
3875 }
3876
3877 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3878 {
3879         CALC_REGADDR();
3880         return readl((void __iomem *)reg_addr);
3881 }
3882
3883 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3884 {
3885         CALC_REGADDR();
3886         writel(value, (void __iomem *)reg_addr);
3887 }
3888
3889 static void rdma_reset(struct slgt_info *info)
3890 {
3891         unsigned int i;
3892
3893         /* set reset bit */
3894         wr_reg32(info, RDCSR, BIT1);
3895
3896         /* wait for enable bit cleared */
3897         for(i=0 ; i < 1000 ; i++)
3898                 if (!(rd_reg32(info, RDCSR) & BIT0))
3899                         break;
3900 }
3901
3902 static void tdma_reset(struct slgt_info *info)
3903 {
3904         unsigned int i;
3905
3906         /* set reset bit */
3907         wr_reg32(info, TDCSR, BIT1);
3908
3909         /* wait for enable bit cleared */
3910         for(i=0 ; i < 1000 ; i++)
3911                 if (!(rd_reg32(info, TDCSR) & BIT0))
3912                         break;
3913 }
3914
3915 /*
3916  * enable internal loopback
3917  * TxCLK and RxCLK are generated from BRG
3918  * and TxD is looped back to RxD internally.
3919  */
3920 static void enable_loopback(struct slgt_info *info)
3921 {
3922         /* SCR (serial control) BIT2=loopback enable */
3923         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3924
3925         if (info->params.mode != MGSL_MODE_ASYNC) {
3926                 /* CCR (clock control)
3927                  * 07..05  tx clock source (010 = BRG)
3928                  * 04..02  rx clock source (010 = BRG)
3929                  * 01      auxclk enable   (0 = disable)
3930                  * 00      BRG enable      (1 = enable)
3931                  *
3932                  * 0100 1001
3933                  */
3934                 wr_reg8(info, CCR, 0x49);
3935
3936                 /* set speed if available, otherwise use default */
3937                 if (info->params.clock_speed)
3938                         set_rate(info, info->params.clock_speed);
3939                 else
3940                         set_rate(info, 3686400);
3941         }
3942 }
3943
3944 /*
3945  *  set baud rate generator to specified rate
3946  */
3947 static void set_rate(struct slgt_info *info, u32 rate)
3948 {
3949         unsigned int div;
3950         unsigned int osc = info->base_clock;
3951
3952         /* div = osc/rate - 1
3953          *
3954          * Round div up if osc/rate is not integer to
3955          * force to next slowest rate.
3956          */
3957
3958         if (rate) {
3959                 div = osc/rate;
3960                 if (!(osc % rate) && div)
3961                         div--;
3962                 wr_reg16(info, BDR, (unsigned short)div);
3963         }
3964 }
3965
3966 static void rx_stop(struct slgt_info *info)
3967 {
3968         unsigned short val;
3969
3970         /* disable and reset receiver */
3971         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3972         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3973         wr_reg16(info, RCR, val);                  /* clear reset bit */
3974
3975         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3976
3977         /* clear pending rx interrupts */
3978         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3979
3980         rdma_reset(info);
3981
3982         info->rx_enabled = false;
3983         info->rx_restart = false;
3984 }
3985
3986 static void rx_start(struct slgt_info *info)
3987 {
3988         unsigned short val;
3989
3990         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3991
3992         /* clear pending rx overrun IRQ */
3993         wr_reg16(info, SSR, IRQ_RXOVER);
3994
3995         /* reset and disable receiver */
3996         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3997         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3998         wr_reg16(info, RCR, val);                  /* clear reset bit */
3999
4000         rdma_reset(info);
4001         reset_rbufs(info);
4002
4003         if (info->rx_pio) {
4004                 /* rx request when rx FIFO not empty */
4005                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4006                 slgt_irq_on(info, IRQ_RXDATA);
4007                 if (info->params.mode == MGSL_MODE_ASYNC) {
4008                         /* enable saving of rx status */
4009                         wr_reg32(info, RDCSR, BIT6);
4010                 }
4011         } else {
4012                 /* rx request when rx FIFO half full */
4013                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4014                 /* set 1st descriptor address */
4015                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4016
4017                 if (info->params.mode != MGSL_MODE_ASYNC) {
4018                         /* enable rx DMA and DMA interrupt */
4019                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4020                 } else {
4021                         /* enable saving of rx status, rx DMA and DMA interrupt */
4022                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4023                 }
4024         }
4025
4026         slgt_irq_on(info, IRQ_RXOVER);
4027
4028         /* enable receiver */
4029         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4030
4031         info->rx_restart = false;
4032         info->rx_enabled = true;
4033 }
4034
4035 static void tx_start(struct slgt_info *info)
4036 {
4037         if (!info->tx_enabled) {
4038                 wr_reg16(info, TCR,
4039                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4040                 info->tx_enabled = true;
4041         }
4042
4043         if (desc_count(info->tbufs[info->tbuf_start])) {
4044                 info->drop_rts_on_tx_done = false;
4045
4046                 if (info->params.mode != MGSL_MODE_ASYNC) {
4047                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4048                                 get_signals(info);
4049                                 if (!(info->signals & SerialSignal_RTS)) {
4050                                         info->signals |= SerialSignal_RTS;
4051                                         set_signals(info);
4052                                         info->drop_rts_on_tx_done = true;
4053                                 }
4054                         }
4055
4056                         slgt_irq_off(info, IRQ_TXDATA);
4057                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4058                         /* clear tx idle and underrun status bits */
4059                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4060                 } else {
4061                         slgt_irq_off(info, IRQ_TXDATA);
4062                         slgt_irq_on(info, IRQ_TXIDLE);
4063                         /* clear tx idle status bit */
4064                         wr_reg16(info, SSR, IRQ_TXIDLE);
4065                 }
4066                 /* set 1st descriptor address and start DMA */
4067                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4068                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4069                 info->tx_active = true;
4070         }
4071 }
4072
4073 static void tx_stop(struct slgt_info *info)
4074 {
4075         unsigned short val;
4076
4077         del_timer(&info->tx_timer);
4078
4079         tdma_reset(info);
4080
4081         /* reset and disable transmitter */
4082         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4083         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4084
4085         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4086
4087         /* clear tx idle and underrun status bit */
4088         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4089
4090         reset_tbufs(info);
4091
4092         info->tx_enabled = false;
4093         info->tx_active = false;
4094 }
4095
4096 static void reset_port(struct slgt_info *info)
4097 {
4098         if (!info->reg_addr)
4099                 return;
4100
4101         tx_stop(info);
4102         rx_stop(info);
4103
4104         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4105         set_signals(info);
4106
4107         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4108 }
4109
4110 static void reset_adapter(struct slgt_info *info)
4111 {
4112         int i;
4113         for (i=0; i < info->port_count; ++i) {
4114                 if (info->port_array[i])
4115                         reset_port(info->port_array[i]);
4116         }
4117 }
4118
4119 static void async_mode(struct slgt_info *info)
4120 {
4121         unsigned short val;
4122
4123         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4124         tx_stop(info);
4125         rx_stop(info);
4126
4127         /* TCR (tx control)
4128          *
4129          * 15..13  mode, 010=async
4130          * 12..10  encoding, 000=NRZ
4131          * 09      parity enable
4132          * 08      1=odd parity, 0=even parity
4133          * 07      1=RTS driver control
4134          * 06      1=break enable
4135          * 05..04  character length
4136          *         00=5 bits
4137          *         01=6 bits
4138          *         10=7 bits
4139          *         11=8 bits
4140          * 03      0=1 stop bit, 1=2 stop bits
4141          * 02      reset
4142          * 01      enable
4143          * 00      auto-CTS enable
4144          */
4145         val = 0x4000;
4146
4147         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4148                 val |= BIT7;
4149
4150         if (info->params.parity != ASYNC_PARITY_NONE) {
4151                 val |= BIT9;
4152                 if (info->params.parity == ASYNC_PARITY_ODD)
4153                         val |= BIT8;
4154         }
4155
4156         switch (info->params.data_bits)
4157         {
4158         case 6: val |= BIT4; break;
4159         case 7: val |= BIT5; break;
4160         case 8: val |= BIT5 + BIT4; break;
4161         }
4162
4163         if (info->params.stop_bits != 1)
4164                 val |= BIT3;
4165
4166         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4167                 val |= BIT0;
4168
4169         wr_reg16(info, TCR, val);
4170
4171         /* RCR (rx control)
4172          *
4173          * 15..13  mode, 010=async
4174          * 12..10  encoding, 000=NRZ
4175          * 09      parity enable
4176          * 08      1=odd parity, 0=even parity
4177          * 07..06  reserved, must be 0
4178          * 05..04  character length
4179          *         00=5 bits
4180          *         01=6 bits
4181          *         10=7 bits
4182          *         11=8 bits
4183          * 03      reserved, must be zero
4184          * 02      reset
4185          * 01      enable
4186          * 00      auto-DCD enable
4187          */
4188         val = 0x4000;
4189
4190         if (info->params.parity != ASYNC_PARITY_NONE) {
4191                 val |= BIT9;
4192                 if (info->params.parity == ASYNC_PARITY_ODD)
4193                         val |= BIT8;
4194         }
4195
4196         switch (info->params.data_bits)
4197         {
4198         case 6: val |= BIT4; break;
4199         case 7: val |= BIT5; break;
4200         case 8: val |= BIT5 + BIT4; break;
4201         }
4202
4203         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4204                 val |= BIT0;
4205
4206         wr_reg16(info, RCR, val);
4207
4208         /* CCR (clock control)
4209          *
4210          * 07..05  011 = tx clock source is BRG/16
4211          * 04..02  010 = rx clock source is BRG
4212          * 01      0 = auxclk disabled
4213          * 00      1 = BRG enabled
4214          *
4215          * 0110 1001
4216          */
4217         wr_reg8(info, CCR, 0x69);
4218
4219         msc_set_vcr(info);
4220
4221         /* SCR (serial control)
4222          *
4223          * 15  1=tx req on FIFO half empty
4224          * 14  1=rx req on FIFO half full
4225          * 13  tx data  IRQ enable
4226          * 12  tx idle  IRQ enable
4227          * 11  rx break on IRQ enable
4228          * 10  rx data  IRQ enable
4229          * 09  rx break off IRQ enable
4230          * 08  overrun  IRQ enable
4231          * 07  DSR      IRQ enable
4232          * 06  CTS      IRQ enable
4233          * 05  DCD      IRQ enable
4234          * 04  RI       IRQ enable
4235          * 03  0=16x sampling, 1=8x sampling
4236          * 02  1=txd->rxd internal loopback enable
4237          * 01  reserved, must be zero
4238          * 00  1=master IRQ enable
4239          */
4240         val = BIT15 + BIT14 + BIT0;
4241         /* JCR[8] : 1 = x8 async mode feature available */
4242         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4243             ((info->base_clock < (info->params.data_rate * 16)) ||
4244              (info->base_clock % (info->params.data_rate * 16)))) {
4245                 /* use 8x sampling */
4246                 val |= BIT3;
4247                 set_rate(info, info->params.data_rate * 8);
4248         } else {
4249                 /* use 16x sampling */
4250                 set_rate(info, info->params.data_rate * 16);
4251         }
4252         wr_reg16(info, SCR, val);
4253
4254         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4255
4256         if (info->params.loopback)
4257                 enable_loopback(info);
4258 }
4259
4260 static void sync_mode(struct slgt_info *info)
4261 {
4262         unsigned short val;
4263
4264         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4265         tx_stop(info);
4266         rx_stop(info);
4267
4268         /* TCR (tx control)
4269          *
4270          * 15..13  mode
4271          *         000=HDLC/SDLC
4272          *         001=raw bit synchronous
4273          *         010=asynchronous/isochronous
4274          *         011=monosync byte synchronous
4275          *         100=bisync byte synchronous
4276          *         101=xsync byte synchronous
4277          * 12..10  encoding
4278          * 09      CRC enable
4279          * 08      CRC32
4280          * 07      1=RTS driver control
4281          * 06      preamble enable
4282          * 05..04  preamble length
4283          * 03      share open/close flag
4284          * 02      reset
4285          * 01      enable
4286          * 00      auto-CTS enable
4287          */
4288         val = BIT2;
4289
4290         switch(info->params.mode) {
4291         case MGSL_MODE_XSYNC:
4292                 val |= BIT15 + BIT13;
4293                 break;
4294         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4295         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4296         case MGSL_MODE_RAW:      val |= BIT13; break;
4297         }
4298         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4299                 val |= BIT7;
4300
4301         switch(info->params.encoding)
4302         {
4303         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4304         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4305         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4306         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4307         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4308         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4309         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4310         }
4311
4312         switch (info->params.crc_type & HDLC_CRC_MASK)
4313         {
4314         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4315         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4316         }
4317
4318         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4319                 val |= BIT6;
4320
4321         switch (info->params.preamble_length)
4322         {
4323         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4324         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4325         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4326         }
4327
4328         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4329                 val |= BIT0;
4330
4331         wr_reg16(info, TCR, val);
4332
4333         /* TPR (transmit preamble) */
4334
4335         switch (info->params.preamble)
4336         {
4337         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4338         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4339         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4340         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4341         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4342         default:                          val = 0x7e; break;
4343         }
4344         wr_reg8(info, TPR, (unsigned char)val);
4345
4346         /* RCR (rx control)
4347          *
4348          * 15..13  mode
4349          *         000=HDLC/SDLC
4350          *         001=raw bit synchronous
4351          *         010=asynchronous/isochronous
4352          *         011=monosync byte synchronous
4353          *         100=bisync byte synchronous
4354          *         101=xsync byte synchronous
4355          * 12..10  encoding
4356          * 09      CRC enable
4357          * 08      CRC32
4358          * 07..03  reserved, must be 0
4359          * 02      reset
4360          * 01      enable
4361          * 00      auto-DCD enable
4362          */
4363         val = 0;
4364
4365         switch(info->params.mode) {
4366         case MGSL_MODE_XSYNC:
4367                 val |= BIT15 + BIT13;
4368                 break;
4369         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4370         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4371         case MGSL_MODE_RAW:      val |= BIT13; break;
4372         }
4373
4374         switch(info->params.encoding)
4375         {
4376         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4377         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4378         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4379         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4380         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4381         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4382         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4383         }
4384
4385         switch (info->params.crc_type & HDLC_CRC_MASK)
4386         {
4387         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4388         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4389         }
4390
4391         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4392                 val |= BIT0;
4393
4394         wr_reg16(info, RCR, val);
4395
4396         /* CCR (clock control)
4397          *
4398          * 07..05  tx clock source
4399          * 04..02  rx clock source
4400          * 01      auxclk enable
4401          * 00      BRG enable
4402          */
4403         val = 0;
4404
4405         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4406         {
4407                 // when RxC source is DPLL, BRG generates 16X DPLL
4408                 // reference clock, so take TxC from BRG/16 to get
4409                 // transmit clock at actual data rate
4410                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4411                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4412                 else
4413                         val |= BIT6;    /* 010, txclk = BRG */
4414         }
4415         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4416                 val |= BIT7;    /* 100, txclk = DPLL Input */
4417         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4418                 val |= BIT5;    /* 001, txclk = RXC Input */
4419
4420         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4421                 val |= BIT3;    /* 010, rxclk = BRG */
4422         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4423                 val |= BIT4;    /* 100, rxclk = DPLL */
4424         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4425                 val |= BIT2;    /* 001, rxclk = TXC Input */
4426
4427         if (info->params.clock_speed)
4428                 val |= BIT1 + BIT0;
4429
4430         wr_reg8(info, CCR, (unsigned char)val);
4431
4432         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4433         {
4434                 // program DPLL mode
4435                 switch(info->params.encoding)
4436                 {
4437                 case HDLC_ENCODING_BIPHASE_MARK:
4438                 case HDLC_ENCODING_BIPHASE_SPACE:
4439                         val = BIT7; break;
4440                 case HDLC_ENCODING_BIPHASE_LEVEL:
4441                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4442                         val = BIT7 + BIT6; break;
4443                 default: val = BIT6;    // NRZ encodings
4444                 }
4445                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4446
4447                 // DPLL requires a 16X reference clock from BRG
4448                 set_rate(info, info->params.clock_speed * 16);
4449         }
4450         else
4451                 set_rate(info, info->params.clock_speed);
4452
4453         tx_set_idle(info);
4454
4455         msc_set_vcr(info);
4456
4457         /* SCR (serial control)
4458          *
4459          * 15  1=tx req on FIFO half empty
4460          * 14  1=rx req on FIFO half full
4461          * 13  tx data  IRQ enable
4462          * 12  tx idle  IRQ enable
4463          * 11  underrun IRQ enable
4464          * 10  rx data  IRQ enable
4465          * 09  rx idle  IRQ enable
4466          * 08  overrun  IRQ enable
4467          * 07  DSR      IRQ enable
4468          * 06  CTS      IRQ enable
4469          * 05  DCD      IRQ enable
4470          * 04  RI       IRQ enable
4471          * 03  reserved, must be zero
4472          * 02  1=txd->rxd internal loopback enable
4473          * 01  reserved, must be zero
4474          * 00  1=master IRQ enable
4475          */
4476         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4477
4478         if (info->params.loopback)
4479                 enable_loopback(info);
4480 }
4481
4482 /*
4483  *  set transmit idle mode
4484  */
4485 static void tx_set_idle(struct slgt_info *info)
4486 {
4487         unsigned char val;
4488         unsigned short tcr;
4489
4490         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4491          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4492          */
4493         tcr = rd_reg16(info, TCR);
4494         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4495                 /* disable preamble, set idle size to 16 bits */
4496                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4497                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4498                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4499         } else if (!(tcr & BIT6)) {
4500                 /* preamble is disabled, set idle size to 8 bits */
4501                 tcr &= ~(BIT5 + BIT4);
4502         }
4503         wr_reg16(info, TCR, tcr);
4504
4505         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4506                 /* LSB of custom tx idle specified in tx idle register */
4507                 val = (unsigned char)(info->idle_mode & 0xff);
4508         } else {
4509                 /* standard 8 bit idle patterns */
4510                 switch(info->idle_mode)
4511                 {
4512                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4513                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4514                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4515                 case HDLC_TXIDLE_ZEROS:
4516                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4517                 default:                         val = 0xff;
4518                 }
4519         }
4520
4521         wr_reg8(info, TIR, val);
4522 }
4523
4524 /*
4525  * get state of V24 status (input) signals
4526  */
4527 static void get_signals(struct slgt_info *info)
4528 {
4529         unsigned short status = rd_reg16(info, SSR);
4530
4531         /* clear all serial signals except RTS and DTR */
4532         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4533
4534         if (status & BIT3)
4535                 info->signals |= SerialSignal_DSR;
4536         if (status & BIT2)
4537                 info->signals |= SerialSignal_CTS;
4538         if (status & BIT1)
4539                 info->signals |= SerialSignal_DCD;
4540         if (status & BIT0)
4541                 info->signals |= SerialSignal_RI;
4542 }
4543
4544 /*
4545  * set V.24 Control Register based on current configuration
4546  */
4547 static void msc_set_vcr(struct slgt_info *info)
4548 {
4549         unsigned char val = 0;
4550
4551         /* VCR (V.24 control)
4552          *
4553          * 07..04  serial IF select
4554          * 03      DTR
4555          * 02      RTS
4556          * 01      LL
4557          * 00      RL
4558          */
4559
4560         switch(info->if_mode & MGSL_INTERFACE_MASK)
4561         {
4562         case MGSL_INTERFACE_RS232:
4563                 val |= BIT5; /* 0010 */
4564                 break;
4565         case MGSL_INTERFACE_V35:
4566                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4567                 break;
4568         case MGSL_INTERFACE_RS422:
4569                 val |= BIT6; /* 0100 */
4570                 break;
4571         }
4572
4573         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4574                 val |= BIT4;
4575         if (info->signals & SerialSignal_DTR)
4576                 val |= BIT3;
4577         if (info->signals & SerialSignal_RTS)
4578                 val |= BIT2;
4579         if (info->if_mode & MGSL_INTERFACE_LL)
4580                 val |= BIT1;
4581         if (info->if_mode & MGSL_INTERFACE_RL)
4582                 val |= BIT0;
4583         wr_reg8(info, VCR, val);
4584 }
4585
4586 /*
4587  * set state of V24 control (output) signals
4588  */
4589 static void set_signals(struct slgt_info *info)
4590 {
4591         unsigned char val = rd_reg8(info, VCR);
4592         if (info->signals & SerialSignal_DTR)
4593                 val |= BIT3;
4594         else
4595                 val &= ~BIT3;
4596         if (info->signals & SerialSignal_RTS)
4597                 val |= BIT2;
4598         else
4599                 val &= ~BIT2;
4600         wr_reg8(info, VCR, val);
4601 }
4602
4603 /*
4604  * free range of receive DMA buffers (i to last)
4605  */
4606 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4607 {
4608         int done = 0;
4609
4610         while(!done) {
4611                 /* reset current buffer for reuse */
4612                 info->rbufs[i].status = 0;
4613                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4614                 if (i == last)
4615                         done = 1;
4616                 if (++i == info->rbuf_count)
4617                         i = 0;
4618         }
4619         info->rbuf_current = i;
4620 }
4621
4622 /*
4623  * mark all receive DMA buffers as free
4624  */
4625 static void reset_rbufs(struct slgt_info *info)
4626 {
4627         free_rbufs(info, 0, info->rbuf_count - 1);
4628         info->rbuf_fill_index = 0;
4629         info->rbuf_fill_count = 0;
4630 }
4631
4632 /*
4633  * pass receive HDLC frame to upper layer
4634  *
4635  * return true if frame available, otherwise false
4636  */
4637 static bool rx_get_frame(struct slgt_info *info)
4638 {
4639         unsigned int start, end;
4640         unsigned short status;
4641         unsigned int framesize = 0;
4642         unsigned long flags;
4643         struct tty_struct *tty = info->port.tty;
4644         unsigned char addr_field = 0xff;
4645         unsigned int crc_size = 0;
4646
4647         switch (info->params.crc_type & HDLC_CRC_MASK) {
4648         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4649         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4650         }
4651
4652 check_again:
4653
4654         framesize = 0;
4655         addr_field = 0xff;
4656         start = end = info->rbuf_current;
4657
4658         for (;;) {
4659                 if (!desc_complete(info->rbufs[end]))
4660                         goto cleanup;
4661
4662                 if (framesize == 0 && info->params.addr_filter != 0xff)
4663                         addr_field = info->rbufs[end].buf[0];
4664
4665                 framesize += desc_count(info->rbufs[end]);
4666
4667                 if (desc_eof(info->rbufs[end]))
4668                         break;
4669
4670                 if (++end == info->rbuf_count)
4671                         end = 0;
4672
4673                 if (end == info->rbuf_current) {
4674                         if (info->rx_enabled){
4675                                 spin_lock_irqsave(&info->lock,flags);
4676                                 rx_start(info);
4677                                 spin_unlock_irqrestore(&info->lock,flags);
4678                         }
4679                         goto cleanup;
4680                 }
4681         }
4682
4683         /* status
4684          *
4685          * 15      buffer complete
4686          * 14..06  reserved
4687          * 05..04  residue
4688          * 02      eof (end of frame)
4689          * 01      CRC error
4690          * 00      abort
4691          */
4692         status = desc_status(info->rbufs[end]);
4693
4694         /* ignore CRC bit if not using CRC (bit is undefined) */
4695         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4696                 status &= ~BIT1;
4697
4698         if (framesize == 0 ||
4699                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4700                 free_rbufs(info, start, end);
4701                 goto check_again;
4702         }
4703
4704         if (framesize < (2 + crc_size) || status & BIT0) {
4705                 info->icount.rxshort++;
4706                 framesize = 0;
4707         } else if (status & BIT1) {
4708                 info->icount.rxcrc++;
4709                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4710                         framesize = 0;
4711         }
4712
4713 #if SYNCLINK_GENERIC_HDLC
4714         if (framesize == 0) {
4715                 info->netdev->stats.rx_errors++;
4716                 info->netdev->stats.rx_frame_errors++;
4717         }
4718 #endif
4719
4720         DBGBH(("%s rx frame status=%04X size=%d\n",
4721                 info->device_name, status, framesize));
4722         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4723
4724         if (framesize) {
4725                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4726                         framesize -= crc_size;
4727                         crc_size = 0;
4728                 }
4729
4730                 if (framesize > info->max_frame_size + crc_size)
4731                         info->icount.rxlong++;
4732                 else {
4733                         /* copy dma buffer(s) to contiguous temp buffer */
4734                         int copy_count = framesize;
4735                         int i = start;
4736                         unsigned char *p = info->tmp_rbuf;
4737                         info->tmp_rbuf_count = framesize;
4738
4739                         info->icount.rxok++;
4740
4741                         while(copy_count) {
4742                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4743                                 memcpy(p, info->rbufs[i].buf, partial_count);
4744                                 p += partial_count;
4745                                 copy_count -= partial_count;
4746                                 if (++i == info->rbuf_count)
4747                                         i = 0;
4748                         }
4749
4750                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4751                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4752                                 framesize++;
4753                         }
4754
4755 #if SYNCLINK_GENERIC_HDLC
4756                         if (info->netcount)
4757                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4758                         else
4759 #endif
4760                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4761                 }
4762         }
4763         free_rbufs(info, start, end);
4764         return true;
4765
4766 cleanup:
4767         return false;
4768 }
4769
4770 /*
4771  * pass receive buffer (RAW synchronous mode) to tty layer
4772  * return true if buffer available, otherwise false
4773  */
4774 static bool rx_get_buf(struct slgt_info *info)
4775 {
4776         unsigned int i = info->rbuf_current;
4777         unsigned int count;
4778
4779         if (!desc_complete(info->rbufs[i]))
4780                 return false;
4781         count = desc_count(info->rbufs[i]);
4782         switch(info->params.mode) {
4783         case MGSL_MODE_MONOSYNC:
4784         case MGSL_MODE_BISYNC:
4785         case MGSL_MODE_XSYNC:
4786                 /* ignore residue in byte synchronous modes */
4787                 if (desc_residue(info->rbufs[i]))
4788                         count--;
4789                 break;
4790         }
4791         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4792         DBGINFO(("rx_get_buf size=%d\n", count));
4793         if (count)
4794                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4795                                   info->flag_buf, count);
4796         free_rbufs(info, i, i);
4797         return true;
4798 }
4799
4800 static void reset_tbufs(struct slgt_info *info)
4801 {
4802         unsigned int i;
4803         info->tbuf_current = 0;
4804         for (i=0 ; i < info->tbuf_count ; i++) {
4805                 info->tbufs[i].status = 0;
4806                 info->tbufs[i].count  = 0;
4807         }
4808 }
4809
4810 /*
4811  * return number of free transmit DMA buffers
4812  */
4813 static unsigned int free_tbuf_count(struct slgt_info *info)
4814 {
4815         unsigned int count = 0;
4816         unsigned int i = info->tbuf_current;
4817
4818         do
4819         {
4820                 if (desc_count(info->tbufs[i]))
4821                         break; /* buffer in use */
4822                 ++count;
4823                 if (++i == info->tbuf_count)
4824                         i=0;
4825         } while (i != info->tbuf_current);
4826
4827         /* if tx DMA active, last zero count buffer is in use */
4828         if (count && (rd_reg32(info, TDCSR) & BIT0))
4829                 --count;
4830
4831         return count;
4832 }
4833
4834 /*
4835  * return number of bytes in unsent transmit DMA buffers
4836  * and the serial controller tx FIFO
4837  */
4838 static unsigned int tbuf_bytes(struct slgt_info *info)
4839 {
4840         unsigned int total_count = 0;
4841         unsigned int i = info->tbuf_current;
4842         unsigned int reg_value;
4843         unsigned int count;
4844         unsigned int active_buf_count = 0;
4845
4846         /*
4847          * Add descriptor counts for all tx DMA buffers.
4848          * If count is zero (cleared by DMA controller after read),
4849          * the buffer is complete or is actively being read from.
4850          *
4851          * Record buf_count of last buffer with zero count starting
4852          * from current ring position. buf_count is mirror
4853          * copy of count and is not cleared by serial controller.
4854          * If DMA controller is active, that buffer is actively
4855          * being read so add to total.
4856          */
4857         do {
4858                 count = desc_count(info->tbufs[i]);
4859                 if (count)
4860                         total_count += count;
4861                 else if (!total_count)
4862                         active_buf_count = info->tbufs[i].buf_count;
4863                 if (++i == info->tbuf_count)
4864                         i = 0;
4865         } while (i != info->tbuf_current);
4866
4867         /* read tx DMA status register */
4868         reg_value = rd_reg32(info, TDCSR);
4869
4870         /* if tx DMA active, last zero count buffer is in use */
4871         if (reg_value & BIT0)
4872                 total_count += active_buf_count;
4873
4874         /* add tx FIFO count = reg_value[15..8] */
4875         total_count += (reg_value >> 8) & 0xff;
4876
4877         /* if transmitter active add one byte for shift register */
4878         if (info->tx_active)
4879                 total_count++;
4880
4881         return total_count;
4882 }
4883
4884 /*
4885  * load data into transmit DMA buffer ring and start transmitter if needed
4886  * return true if data accepted, otherwise false (buffers full)
4887  */
4888 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4889 {
4890         unsigned short count;
4891         unsigned int i;
4892         struct slgt_desc *d;
4893
4894         /* check required buffer space */
4895         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4896                 return false;
4897
4898         DBGDATA(info, buf, size, "tx");
4899
4900         /*
4901          * copy data to one or more DMA buffers in circular ring
4902          * tbuf_start   = first buffer for this data
4903          * tbuf_current = next free buffer
4904          *
4905          * Copy all data before making data visible to DMA controller by
4906          * setting descriptor count of the first buffer.
4907          * This prevents an active DMA controller from reading the first DMA
4908          * buffers of a frame and stopping before the final buffers are filled.
4909          */
4910
4911         info->tbuf_start = i = info->tbuf_current;
4912
4913         while (size) {
4914                 d = &info->tbufs[i];
4915
4916                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4917                 memcpy(d->buf, buf, count);
4918
4919                 size -= count;
4920                 buf  += count;
4921
4922                 /*
4923                  * set EOF bit for last buffer of HDLC frame or
4924                  * for every buffer in raw mode
4925                  */
4926                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4927                     info->params.mode == MGSL_MODE_RAW)
4928                         set_desc_eof(*d, 1);
4929                 else
4930                         set_desc_eof(*d, 0);
4931
4932                 /* set descriptor count for all but first buffer */
4933                 if (i != info->tbuf_start)
4934                         set_desc_count(*d, count);
4935                 d->buf_count = count;
4936
4937                 if (++i == info->tbuf_count)
4938                         i = 0;
4939         }
4940
4941         info->tbuf_current = i;
4942
4943         /* set first buffer count to make new data visible to DMA controller */
4944         d = &info->tbufs[info->tbuf_start];
4945         set_desc_count(*d, d->buf_count);
4946
4947         /* start transmitter if needed and update transmit timeout */
4948         if (!info->tx_active)
4949                 tx_start(info);
4950         update_tx_timer(info);
4951
4952         return true;
4953 }
4954
4955 static int register_test(struct slgt_info *info)
4956 {
4957         static unsigned short patterns[] =
4958                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4959         static unsigned int count = ARRAY_SIZE(patterns);
4960         unsigned int i;
4961         int rc = 0;
4962
4963         for (i=0 ; i < count ; i++) {
4964                 wr_reg16(info, TIR, patterns[i]);
4965                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4966                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4967                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4968                         rc = -ENODEV;
4969                         break;
4970                 }
4971         }
4972         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4973         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4974         return rc;
4975 }
4976
4977 static int irq_test(struct slgt_info *info)
4978 {
4979         unsigned long timeout;
4980         unsigned long flags;
4981         struct tty_struct *oldtty = info->port.tty;
4982         u32 speed = info->params.data_rate;
4983
4984         info->params.data_rate = 921600;
4985         info->port.tty = NULL;
4986
4987         spin_lock_irqsave(&info->lock, flags);
4988         async_mode(info);
4989         slgt_irq_on(info, IRQ_TXIDLE);
4990
4991         /* enable transmitter */
4992         wr_reg16(info, TCR,
4993                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4994
4995         /* write one byte and wait for tx idle */
4996         wr_reg16(info, TDR, 0);
4997
4998         /* assume failure */
4999         info->init_error = DiagStatus_IrqFailure;
5000         info->irq_occurred = false;
5001
5002         spin_unlock_irqrestore(&info->lock, flags);
5003
5004         timeout=100;
5005         while(timeout-- && !info->irq_occurred)
5006                 msleep_interruptible(10);
5007
5008         spin_lock_irqsave(&info->lock,flags);
5009         reset_port(info);
5010         spin_unlock_irqrestore(&info->lock,flags);
5011
5012         info->params.data_rate = speed;
5013         info->port.tty = oldtty;
5014
5015         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5016         return info->irq_occurred ? 0 : -ENODEV;
5017 }
5018
5019 static int loopback_test_rx(struct slgt_info *info)
5020 {
5021         unsigned char *src, *dest;
5022         int count;
5023
5024         if (desc_complete(info->rbufs[0])) {
5025                 count = desc_count(info->rbufs[0]);
5026                 src   = info->rbufs[0].buf;
5027                 dest  = info->tmp_rbuf;
5028
5029                 for( ; count ; count-=2, src+=2) {
5030                         /* src=data byte (src+1)=status byte */
5031                         if (!(*(src+1) & (BIT9 + BIT8))) {
5032                                 *dest = *src;
5033                                 dest++;
5034                                 info->tmp_rbuf_count++;
5035                         }
5036                 }
5037                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5038                 return 1;
5039         }
5040         return 0;
5041 }
5042
5043 static int loopback_test(struct slgt_info *info)
5044 {
5045 #define TESTFRAMESIZE 20
5046
5047         unsigned long timeout;
5048         u16 count = TESTFRAMESIZE;
5049         unsigned char buf[TESTFRAMESIZE];
5050         int rc = -ENODEV;
5051         unsigned long flags;
5052
5053         struct tty_struct *oldtty = info->port.tty;
5054         MGSL_PARAMS params;
5055
5056         memcpy(&params, &info->params, sizeof(params));
5057
5058         info->params.mode = MGSL_MODE_ASYNC;
5059         info->params.data_rate = 921600;
5060         info->params.loopback = 1;
5061         info->port.tty = NULL;
5062
5063         /* build and send transmit frame */
5064         for (count = 0; count < TESTFRAMESIZE; ++count)
5065                 buf[count] = (unsigned char)count;
5066
5067         info->tmp_rbuf_count = 0;
5068         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5069
5070         /* program hardware for HDLC and enabled receiver */
5071         spin_lock_irqsave(&info->lock,flags);
5072         async_mode(info);
5073         rx_start(info);
5074         tx_load(info, buf, count);
5075         spin_unlock_irqrestore(&info->lock, flags);
5076
5077         /* wait for receive complete */
5078         for (timeout = 100; timeout; --timeout) {
5079                 msleep_interruptible(10);
5080                 if (loopback_test_rx(info)) {
5081                         rc = 0;
5082                         break;
5083                 }
5084         }
5085
5086         /* verify received frame length and contents */
5087         if (!rc && (info->tmp_rbuf_count != count ||
5088                   memcmp(buf, info->tmp_rbuf, count))) {
5089                 rc = -ENODEV;
5090         }
5091
5092         spin_lock_irqsave(&info->lock,flags);
5093         reset_adapter(info);
5094         spin_unlock_irqrestore(&info->lock,flags);
5095
5096         memcpy(&info->params, &params, sizeof(info->params));
5097         info->port.tty = oldtty;
5098
5099         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5100         return rc;
5101 }
5102
5103 static int adapter_test(struct slgt_info *info)
5104 {
5105         DBGINFO(("testing %s\n", info->device_name));
5106         if (register_test(info) < 0) {
5107                 printk("register test failure %s addr=%08X\n",
5108                         info->device_name, info->phys_reg_addr);
5109         } else if (irq_test(info) < 0) {
5110                 printk("IRQ test failure %s IRQ=%d\n",
5111                         info->device_name, info->irq_level);
5112         } else if (loopback_test(info) < 0) {
5113                 printk("loopback test failure %s\n", info->device_name);
5114         }
5115         return info->init_error;
5116 }
5117
5118 /*
5119  * transmit timeout handler
5120  */
5121 static void tx_timeout(unsigned long context)
5122 {
5123         struct slgt_info *info = (struct slgt_info*)context;
5124         unsigned long flags;
5125
5126         DBGINFO(("%s tx_timeout\n", info->device_name));
5127         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5128                 info->icount.txtimeout++;
5129         }
5130         spin_lock_irqsave(&info->lock,flags);
5131         tx_stop(info);
5132         spin_unlock_irqrestore(&info->lock,flags);
5133
5134 #if SYNCLINK_GENERIC_HDLC
5135         if (info->netcount)
5136                 hdlcdev_tx_done(info);
5137         else
5138 #endif
5139                 bh_transmit(info);
5140 }
5141
5142 /*
5143  * receive buffer polling timer
5144  */
5145 static void rx_timeout(unsigned long context)
5146 {
5147         struct slgt_info *info = (struct slgt_info*)context;
5148         unsigned long flags;
5149
5150         DBGINFO(("%s rx_timeout\n", info->device_name));
5151         spin_lock_irqsave(&info->lock, flags);
5152         info->pending_bh |= BH_RECEIVE;
5153         spin_unlock_irqrestore(&info->lock, flags);
5154         bh_handler(&info->task);
5155 }
5156