2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/mutex.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/clk.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
42 /* conversion functions */
43 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
45 return container_of(req, struct s3c_hsotg_req, req);
48 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
50 return container_of(ep, struct s3c_hsotg_ep, ep);
53 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
55 return container_of(gadget, struct dwc2_hsotg, gadget);
58 static inline void __orr32(void __iomem *ptr, u32 val)
60 writel(readl(ptr) | val, ptr);
63 static inline void __bic32(void __iomem *ptr, u32 val)
65 writel(readl(ptr) & ~val, ptr);
68 static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
69 u32 ep_index, u32 dir_in)
72 return hsotg->eps_in[ep_index];
74 return hsotg->eps_out[ep_index];
77 /* forward declaration of functions */
78 static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg);
81 * using_dma - return the DMA status of the driver.
82 * @hsotg: The driver state.
84 * Return true if we're using DMA.
86 * Currently, we have the DMA support code worked into everywhere
87 * that needs it, but the AMBA DMA implementation in the hardware can
88 * only DMA from 32bit aligned addresses. This means that gadgets such
89 * as the CDC Ethernet cannot work as they often pass packets which are
92 * Unfortunately the choice to use DMA or not is global to the controller
93 * and seems to be only settable when the controller is being put through
94 * a core reset. This means we either need to fix the gadgets to take
95 * account of DMA alignment, or add bounce buffers (yuerk).
97 * g_using_dma is set depending on dts flag.
99 static inline bool using_dma(struct dwc2_hsotg *hsotg)
101 return hsotg->g_using_dma;
105 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
106 * @hsotg: The device state
107 * @ints: A bitmask of the interrupts to enable
109 static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
111 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
114 new_gsintmsk = gsintmsk | ints;
116 if (new_gsintmsk != gsintmsk) {
117 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
118 writel(new_gsintmsk, hsotg->regs + GINTMSK);
123 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
124 * @hsotg: The device state
125 * @ints: A bitmask of the interrupts to enable
127 static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
129 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
132 new_gsintmsk = gsintmsk & ~ints;
134 if (new_gsintmsk != gsintmsk)
135 writel(new_gsintmsk, hsotg->regs + GINTMSK);
139 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
140 * @hsotg: The device state
141 * @ep: The endpoint index
142 * @dir_in: True if direction is in.
143 * @en: The enable value, true to enable
145 * Set or clear the mask for an individual endpoint's interrupt
148 static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
149 unsigned int ep, unsigned int dir_in,
159 local_irq_save(flags);
160 daint = readl(hsotg->regs + DAINTMSK);
165 writel(daint, hsotg->regs + DAINTMSK);
166 local_irq_restore(flags);
170 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
171 * @hsotg: The device instance.
173 static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
180 /* Reset fifo map if not correctly cleared during previous session */
181 WARN_ON(hsotg->fifo_map);
184 /* set RX/NPTX FIFO sizes */
185 writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
186 writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
187 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
188 hsotg->regs + GNPTXFSIZ);
191 * arange all the rest of the TX FIFOs, as some versions of this
192 * block have overlapping default addresses. This also ensures
193 * that if the settings have been changed, then they are set to
197 /* start at the end of the GNPTXFSIZ, rounded up */
198 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
201 * Configure fifos sizes from provided configuration and assign
202 * them to endpoints dynamically according to maxpacket size value of
205 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
206 if (!hsotg->g_tx_fifo_sz[ep])
209 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
210 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
211 "insufficient fifo memory");
212 addr += hsotg->g_tx_fifo_sz[ep];
214 writel(val, hsotg->regs + DPTXFSIZN(ep));
218 * according to p428 of the design guide, we need to ensure that
219 * all fifos are flushed before continuing
222 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
223 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
225 /* wait until the fifos are both flushed */
228 val = readl(hsotg->regs + GRSTCTL);
230 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
233 if (--timeout == 0) {
235 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
243 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
247 * @ep: USB endpoint to allocate request for.
248 * @flags: Allocation flags
250 * Allocate a new USB request structure appropriate for the specified endpoint
252 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
255 struct s3c_hsotg_req *req;
257 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
261 INIT_LIST_HEAD(&req->queue);
267 * is_ep_periodic - return true if the endpoint is in periodic mode.
268 * @hs_ep: The endpoint to query.
270 * Returns true if the endpoint is in periodic mode, meaning it is being
271 * used for an Interrupt or ISO transfer.
273 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
275 return hs_ep->periodic;
279 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
280 * @hsotg: The device state.
281 * @hs_ep: The endpoint for the request
282 * @hs_req: The request being processed.
284 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
285 * of a request to ensure the buffer is ready for access by the caller.
287 static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
288 struct s3c_hsotg_ep *hs_ep,
289 struct s3c_hsotg_req *hs_req)
291 struct usb_request *req = &hs_req->req;
293 /* ignore this if we're not moving any data */
294 if (hs_req->req.length == 0)
297 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
301 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
302 * @hsotg: The controller state.
303 * @hs_ep: The endpoint we're going to write for.
304 * @hs_req: The request to write data for.
306 * This is called when the TxFIFO has some space in it to hold a new
307 * transmission and we have something to give it. The actual setup of
308 * the data size is done elsewhere, so all we have to do is to actually
311 * The return value is zero if there is more space (or nothing was done)
312 * otherwise -ENOSPC is returned if the FIFO space was used up.
314 * This routine is only needed for PIO
316 static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
317 struct s3c_hsotg_ep *hs_ep,
318 struct s3c_hsotg_req *hs_req)
320 bool periodic = is_ep_periodic(hs_ep);
321 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
322 int buf_pos = hs_req->req.actual;
323 int to_write = hs_ep->size_loaded;
329 to_write -= (buf_pos - hs_ep->last_load);
331 /* if there's nothing to write, get out early */
335 if (periodic && !hsotg->dedicated_fifos) {
336 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
341 * work out how much data was loaded so we can calculate
342 * how much data is left in the fifo.
345 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
348 * if shared fifo, we cannot write anything until the
349 * previous data has been completely sent.
351 if (hs_ep->fifo_load != 0) {
352 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
356 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
358 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
360 /* how much of the data has moved */
361 size_done = hs_ep->size_loaded - size_left;
363 /* how much data is left in the fifo */
364 can_write = hs_ep->fifo_load - size_done;
365 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
366 __func__, can_write);
368 can_write = hs_ep->fifo_size - can_write;
369 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
370 __func__, can_write);
372 if (can_write <= 0) {
373 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
376 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
377 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
382 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
384 "%s: no queue slots available (0x%08x)\n",
387 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
391 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
392 can_write *= 4; /* fifo size is in 32bit quantities. */
395 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
397 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
398 __func__, gnptxsts, can_write, to_write, max_transfer);
401 * limit to 512 bytes of data, it seems at least on the non-periodic
402 * FIFO, requests of >512 cause the endpoint to get stuck with a
403 * fragment of the end of the transfer in it.
405 if (can_write > 512 && !periodic)
409 * limit the write to one max-packet size worth of data, but allow
410 * the transfer to return that it did not run out of fifo space
413 if (to_write > max_transfer) {
414 to_write = max_transfer;
416 /* it's needed only when we do not use dedicated fifos */
417 if (!hsotg->dedicated_fifos)
418 s3c_hsotg_en_gsint(hsotg,
419 periodic ? GINTSTS_PTXFEMP :
423 /* see if we can write data */
425 if (to_write > can_write) {
426 to_write = can_write;
427 pkt_round = to_write % max_transfer;
430 * Round the write down to an
431 * exact number of packets.
433 * Note, we do not currently check to see if we can ever
434 * write a full packet or not to the FIFO.
438 to_write -= pkt_round;
441 * enable correct FIFO interrupt to alert us when there
445 /* it's needed only when we do not use dedicated fifos */
446 if (!hsotg->dedicated_fifos)
447 s3c_hsotg_en_gsint(hsotg,
448 periodic ? GINTSTS_PTXFEMP :
452 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
453 to_write, hs_req->req.length, can_write, buf_pos);
458 hs_req->req.actual = buf_pos + to_write;
459 hs_ep->total_data += to_write;
462 hs_ep->fifo_load += to_write;
464 to_write = DIV_ROUND_UP(to_write, 4);
465 data = hs_req->req.buf + buf_pos;
467 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
469 return (to_write >= can_write) ? -ENOSPC : 0;
473 * get_ep_limit - get the maximum data legnth for this endpoint
474 * @hs_ep: The endpoint
476 * Return the maximum data that can be queued in one go on a given endpoint
477 * so that transfers that are too long can be split.
479 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
481 int index = hs_ep->index;
486 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
487 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
491 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
496 /* we made the constant loading easier above by using +1 */
501 * constrain by packet count if maxpkts*pktsize is greater
502 * than the length register size.
505 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
506 maxsize = maxpkt * hs_ep->ep.maxpacket;
512 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
513 * @hsotg: The controller state.
514 * @hs_ep: The endpoint to process a request for
515 * @hs_req: The request to start.
516 * @continuing: True if we are doing more for the current request.
518 * Start the given request running by setting the endpoint registers
519 * appropriately, and writing any data to the FIFOs.
521 static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg,
522 struct s3c_hsotg_ep *hs_ep,
523 struct s3c_hsotg_req *hs_req,
526 struct usb_request *ureq = &hs_req->req;
527 int index = hs_ep->index;
528 int dir_in = hs_ep->dir_in;
538 if (hs_ep->req && !continuing) {
539 dev_err(hsotg->dev, "%s: active request\n", __func__);
542 } else if (hs_ep->req != hs_req && continuing) {
544 "%s: continue different req\n", __func__);
550 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
551 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
553 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
554 __func__, readl(hsotg->regs + epctrl_reg), index,
555 hs_ep->dir_in ? "in" : "out");
557 /* If endpoint is stalled, we will restart request later */
558 ctrl = readl(hsotg->regs + epctrl_reg);
560 if (ctrl & DXEPCTL_STALL) {
561 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
565 length = ureq->length - ureq->actual;
566 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
567 ureq->length, ureq->actual);
570 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
571 ureq->buf, length, &ureq->dma,
572 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
574 maxreq = get_ep_limit(hs_ep);
575 if (length > maxreq) {
576 int round = maxreq % hs_ep->ep.maxpacket;
578 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
579 __func__, length, maxreq, round);
581 /* round down to multiple of packets */
589 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
591 packets = 1; /* send one packet if length is zero. */
593 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
594 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
598 if (dir_in && index != 0)
599 if (hs_ep->isochronous)
600 epsize = DXEPTSIZ_MC(packets);
602 epsize = DXEPTSIZ_MC(1);
607 * zero length packet should be programmed on its own and should not
608 * be counted in DIEPTSIZ.PktCnt with other packets.
610 if (dir_in && ureq->zero && !continuing) {
611 /* Test if zlp is actually required. */
612 if ((ureq->length >= hs_ep->ep.maxpacket) &&
613 !(ureq->length % hs_ep->ep.maxpacket))
617 epsize |= DXEPTSIZ_PKTCNT(packets);
618 epsize |= DXEPTSIZ_XFERSIZE(length);
620 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
621 __func__, packets, length, ureq->length, epsize, epsize_reg);
623 /* store the request as the current one we're doing */
626 /* write size / packets */
627 writel(epsize, hsotg->regs + epsize_reg);
629 if (using_dma(hsotg) && !continuing) {
630 unsigned int dma_reg;
633 * write DMA address to control register, buffer already
634 * synced by s3c_hsotg_ep_queue().
637 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
638 writel(ureq->dma, hsotg->regs + dma_reg);
640 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
641 __func__, &ureq->dma, dma_reg);
644 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
645 ctrl |= DXEPCTL_USBACTEP;
647 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
649 /* For Setup request do not clear NAK */
650 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
651 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
653 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
654 writel(ctrl, hsotg->regs + epctrl_reg);
657 * set these, it seems that DMA support increments past the end
658 * of the packet buffer so we need to calculate the length from
661 hs_ep->size_loaded = length;
662 hs_ep->last_load = ureq->actual;
664 if (dir_in && !using_dma(hsotg)) {
665 /* set these anyway, we may need them for non-periodic in */
666 hs_ep->fifo_load = 0;
668 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
672 * clear the INTknTXFEmpMsk when we start request, more as a aide
673 * to debugging to see what is going on.
676 writel(DIEPMSK_INTKNTXFEMPMSK,
677 hsotg->regs + DIEPINT(index));
680 * Note, trying to clear the NAK here causes problems with transmit
681 * on the S3C6400 ending up with the TXFIFO becoming full.
684 /* check ep is enabled */
685 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
687 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
688 index, readl(hsotg->regs + epctrl_reg));
690 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
691 __func__, readl(hsotg->regs + epctrl_reg));
693 /* enable ep interrupts */
694 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
698 * s3c_hsotg_map_dma - map the DMA memory being used for the request
699 * @hsotg: The device state.
700 * @hs_ep: The endpoint the request is on.
701 * @req: The request being processed.
703 * We've been asked to queue a request, so ensure that the memory buffer
704 * is correctly setup for DMA. If we've been passed an extant DMA address
705 * then ensure the buffer has been synced to memory. If our buffer has no
706 * DMA memory, then we map the memory and mark our request to allow us to
707 * cleanup on completion.
709 static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg,
710 struct s3c_hsotg_ep *hs_ep,
711 struct usb_request *req)
713 struct s3c_hsotg_req *hs_req = our_req(req);
716 /* if the length is zero, ignore the DMA data */
717 if (hs_req->req.length == 0)
720 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
727 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
728 __func__, req->buf, req->length);
733 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
736 struct s3c_hsotg_req *hs_req = our_req(req);
737 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
738 struct dwc2_hsotg *hs = hs_ep->parent;
741 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
742 ep->name, req, req->length, req->buf, req->no_interrupt,
743 req->zero, req->short_not_ok);
745 /* initialise status of the request */
746 INIT_LIST_HEAD(&hs_req->queue);
748 req->status = -EINPROGRESS;
750 /* if we're using DMA, sync the buffers as necessary */
752 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
757 first = list_empty(&hs_ep->queue);
758 list_add_tail(&hs_req->queue, &hs_ep->queue);
761 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
766 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
769 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
770 struct dwc2_hsotg *hs = hs_ep->parent;
771 unsigned long flags = 0;
774 spin_lock_irqsave(&hs->lock, flags);
775 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
776 spin_unlock_irqrestore(&hs->lock, flags);
781 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
782 struct usb_request *req)
784 struct s3c_hsotg_req *hs_req = our_req(req);
790 * s3c_hsotg_complete_oursetup - setup completion callback
791 * @ep: The endpoint the request was on.
792 * @req: The request completed.
794 * Called on completion of any requests the driver itself
795 * submitted that need cleaning up.
797 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
798 struct usb_request *req)
800 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
801 struct dwc2_hsotg *hsotg = hs_ep->parent;
803 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
805 s3c_hsotg_ep_free_request(ep, req);
809 * ep_from_windex - convert control wIndex value to endpoint
810 * @hsotg: The driver state.
811 * @windex: The control request wIndex field (in host order).
813 * Convert the given wIndex into a pointer to an driver endpoint
814 * structure, or return NULL if it is not a valid endpoint.
816 static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
819 struct s3c_hsotg_ep *ep;
820 int dir = (windex & USB_DIR_IN) ? 1 : 0;
821 int idx = windex & 0x7F;
826 if (idx > hsotg->num_of_eps)
829 ep = index_to_ep(hsotg, idx, dir);
831 if (idx && ep->dir_in != dir)
838 * s3c_hsotg_send_reply - send reply to control request
839 * @hsotg: The device state
841 * @buff: Buffer for request
842 * @length: Length of reply.
844 * Create a request and queue it on the given endpoint. This is useful as
845 * an internal method of sending replies to certain control requests, etc.
847 static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg,
848 struct s3c_hsotg_ep *ep,
852 struct usb_request *req;
855 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
857 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
858 hsotg->ep0_reply = req;
860 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
864 req->buf = hsotg->ep0_buff;
865 req->length = length;
867 * zero flag is for sending zlp in DATA IN stage. It has no impact on
871 req->complete = s3c_hsotg_complete_oursetup;
874 memcpy(req->buf, buff, length);
876 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
878 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
886 * s3c_hsotg_process_req_status - process request GET_STATUS
887 * @hsotg: The device state
888 * @ctrl: USB control request
890 static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
891 struct usb_ctrlrequest *ctrl)
893 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
894 struct s3c_hsotg_ep *ep;
898 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
901 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
905 switch (ctrl->bRequestType & USB_RECIP_MASK) {
906 case USB_RECIP_DEVICE:
907 reply = cpu_to_le16(0); /* bit 0 => self powered,
908 * bit 1 => remote wakeup */
911 case USB_RECIP_INTERFACE:
912 /* currently, the data result should be zero */
913 reply = cpu_to_le16(0);
916 case USB_RECIP_ENDPOINT:
917 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
921 reply = cpu_to_le16(ep->halted ? 1 : 0);
928 if (le16_to_cpu(ctrl->wLength) != 2)
931 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
933 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
940 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
943 * get_ep_head - return the first request on the endpoint
944 * @hs_ep: The controller endpoint to get
946 * Get the first request on the endpoint.
948 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
950 if (list_empty(&hs_ep->queue))
953 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
957 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
958 * @hsotg: The device state
959 * @ctrl: USB control request
961 static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
962 struct usb_ctrlrequest *ctrl)
964 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
965 struct s3c_hsotg_req *hs_req;
967 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
968 struct s3c_hsotg_ep *ep;
972 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
973 __func__, set ? "SET" : "CLEAR");
975 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
976 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
978 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
979 __func__, le16_to_cpu(ctrl->wIndex));
983 switch (le16_to_cpu(ctrl->wValue)) {
984 case USB_ENDPOINT_HALT:
987 s3c_hsotg_ep_sethalt(&ep->ep, set);
989 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
992 "%s: failed to send reply\n", __func__);
997 * we have to complete all requests for ep if it was
998 * halted, and the halt was cleared by CLEAR_FEATURE
1001 if (!set && halted) {
1003 * If we have request in progress,
1009 list_del_init(&hs_req->queue);
1010 usb_gadget_giveback_request(&ep->ep,
1014 /* If we have pending request, then start it */
1015 restart = !list_empty(&ep->queue);
1017 hs_req = get_ep_head(ep);
1018 s3c_hsotg_start_req(hsotg, ep,
1029 return -ENOENT; /* currently only deal with endpoint */
1034 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1037 * s3c_hsotg_stall_ep0 - stall ep0
1038 * @hsotg: The device state
1040 * Set stall for ep0 as response for setup request.
1042 static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1044 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
1048 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1049 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1052 * DxEPCTL_Stall will be cleared by EP once it has
1053 * taken effect, so no need to clear later.
1056 ctrl = readl(hsotg->regs + reg);
1057 ctrl |= DXEPCTL_STALL;
1058 ctrl |= DXEPCTL_CNAK;
1059 writel(ctrl, hsotg->regs + reg);
1062 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1063 ctrl, reg, readl(hsotg->regs + reg));
1066 * complete won't be called, so we enqueue
1067 * setup request here
1069 s3c_hsotg_enqueue_setup(hsotg);
1073 * s3c_hsotg_process_control - process a control request
1074 * @hsotg: The device state
1075 * @ctrl: The control request received
1077 * The controller has received the SETUP phase of a control request, and
1078 * needs to work out what to do next (and whether to pass it on to the
1081 static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg,
1082 struct usb_ctrlrequest *ctrl)
1084 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
1088 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1089 ctrl->bRequest, ctrl->bRequestType,
1090 ctrl->wValue, ctrl->wLength);
1092 if (ctrl->wLength == 0) {
1094 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1095 } else if (ctrl->bRequestType & USB_DIR_IN) {
1097 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1100 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1103 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1104 switch (ctrl->bRequest) {
1105 case USB_REQ_SET_ADDRESS:
1106 hsotg->connected = 1;
1107 dcfg = readl(hsotg->regs + DCFG);
1108 dcfg &= ~DCFG_DEVADDR_MASK;
1109 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1110 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1111 writel(dcfg, hsotg->regs + DCFG);
1113 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1115 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1118 case USB_REQ_GET_STATUS:
1119 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1122 case USB_REQ_CLEAR_FEATURE:
1123 case USB_REQ_SET_FEATURE:
1124 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1129 /* as a fallback, try delivering it to the driver to deal with */
1131 if (ret == 0 && hsotg->driver) {
1132 spin_unlock(&hsotg->lock);
1133 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1134 spin_lock(&hsotg->lock);
1136 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1140 * the request is either unhandlable, or is not formatted correctly
1141 * so respond with a STALL for the status stage to indicate failure.
1145 s3c_hsotg_stall_ep0(hsotg);
1149 * s3c_hsotg_complete_setup - completion of a setup transfer
1150 * @ep: The endpoint the request was on.
1151 * @req: The request completed.
1153 * Called on completion of any requests the driver itself submitted for
1156 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1157 struct usb_request *req)
1159 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1160 struct dwc2_hsotg *hsotg = hs_ep->parent;
1162 if (req->status < 0) {
1163 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1167 spin_lock(&hsotg->lock);
1168 if (req->actual == 0)
1169 s3c_hsotg_enqueue_setup(hsotg);
1171 s3c_hsotg_process_control(hsotg, req->buf);
1172 spin_unlock(&hsotg->lock);
1176 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1177 * @hsotg: The device state.
1179 * Enqueue a request on EP0 if necessary to received any SETUP packets
1180 * received from the host.
1182 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1184 struct usb_request *req = hsotg->ctrl_req;
1185 struct s3c_hsotg_req *hs_req = our_req(req);
1188 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1192 req->buf = hsotg->ctrl_buff;
1193 req->complete = s3c_hsotg_complete_setup;
1195 if (!list_empty(&hs_req->queue)) {
1196 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1200 hsotg->eps_out[0]->dir_in = 0;
1201 hsotg->eps_out[0]->send_zlp = 0;
1202 hsotg->ep0_state = DWC2_EP0_SETUP;
1204 ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1206 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1208 * Don't think there's much we can do other than watch the
1214 static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1215 struct s3c_hsotg_ep *hs_ep)
1218 u8 index = hs_ep->index;
1219 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1220 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1222 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index);
1224 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1225 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1228 ctrl = readl(hsotg->regs + epctl_reg);
1229 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1230 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1231 ctrl |= DXEPCTL_USBACTEP;
1232 writel(ctrl, hsotg->regs + epctl_reg);
1236 * s3c_hsotg_complete_request - complete a request given to us
1237 * @hsotg: The device state.
1238 * @hs_ep: The endpoint the request was on.
1239 * @hs_req: The request to complete.
1240 * @result: The result code (0 => Ok, otherwise errno)
1242 * The given request has finished, so call the necessary completion
1243 * if it has one and then look to see if we can start a new request
1246 * Note, expects the ep to already be locked as appropriate.
1248 static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1249 struct s3c_hsotg_ep *hs_ep,
1250 struct s3c_hsotg_req *hs_req,
1256 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1260 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1261 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1264 * only replace the status if we've not already set an error
1265 * from a previous transaction
1268 if (hs_req->req.status == -EINPROGRESS)
1269 hs_req->req.status = result;
1272 list_del_init(&hs_req->queue);
1274 if (using_dma(hsotg))
1275 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1278 * call the complete request with the locks off, just in case the
1279 * request tries to queue more work for this endpoint.
1282 if (hs_req->req.complete) {
1283 spin_unlock(&hsotg->lock);
1284 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1285 spin_lock(&hsotg->lock);
1289 * Look to see if there is anything else to do. Note, the completion
1290 * of the previous request may have caused a new request to be started
1291 * so be careful when doing this.
1294 if (!hs_ep->req && result >= 0) {
1295 restart = !list_empty(&hs_ep->queue);
1297 hs_req = get_ep_head(hs_ep);
1298 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1304 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1305 * @hsotg: The device state.
1306 * @ep_idx: The endpoint index for the data
1307 * @size: The size of data in the fifo, in bytes
1309 * The FIFO status shows there is data to read from the FIFO for a given
1310 * endpoint, so sort out whether we need to read the data into a request
1311 * that has been made for that endpoint.
1313 static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1315 struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1316 struct s3c_hsotg_req *hs_req = hs_ep->req;
1317 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1324 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1328 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1329 __func__, size, ep_idx, epctl);
1331 /* dump the data from the FIFO, we've nothing we can do */
1332 for (ptr = 0; ptr < size; ptr += 4)
1339 read_ptr = hs_req->req.actual;
1340 max_req = hs_req->req.length - read_ptr;
1342 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1343 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1345 if (to_read > max_req) {
1347 * more data appeared than we where willing
1348 * to deal with in this request.
1351 /* currently we don't deal this */
1355 hs_ep->total_data += to_read;
1356 hs_req->req.actual += to_read;
1357 to_read = DIV_ROUND_UP(to_read, 4);
1360 * note, we might over-write the buffer end by 3 bytes depending on
1361 * alignment of the data.
1363 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1367 * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1368 * @hsotg: The device instance
1369 * @dir_in: If IN zlp
1371 * Generate a zero-length IN packet request for terminating a SETUP
1374 * Note, since we don't write any data to the TxFIFO, then it is
1375 * currently believed that we do not need to wait for any space in
1378 static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1380 /* eps_out[0] is used in both directions */
1381 hsotg->eps_out[0]->dir_in = dir_in;
1382 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1384 s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1388 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1389 * @hsotg: The device instance
1390 * @epnum: The endpoint received from
1392 * The RXFIFO has delivered an OutDone event, which means that the data
1393 * transfer for an OUT endpoint has been completed, either by a short
1394 * packet or by the finish of a transfer.
1396 static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1398 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1399 struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1400 struct s3c_hsotg_req *hs_req = hs_ep->req;
1401 struct usb_request *req = &hs_req->req;
1402 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1406 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1410 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1411 dev_dbg(hsotg->dev, "zlp packet received\n");
1412 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1413 s3c_hsotg_enqueue_setup(hsotg);
1417 if (using_dma(hsotg)) {
1421 * Calculate the size of the transfer by checking how much
1422 * is left in the endpoint size register and then working it
1423 * out from the amount we loaded for the transfer.
1425 * We need to do this as DMA pointers are always 32bit aligned
1426 * so may overshoot/undershoot the transfer.
1429 size_done = hs_ep->size_loaded - size_left;
1430 size_done += hs_ep->last_load;
1432 req->actual = size_done;
1435 /* if there is more request to do, schedule new transfer */
1436 if (req->actual < req->length && size_left == 0) {
1437 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1441 if (req->actual < req->length && req->short_not_ok) {
1442 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1443 __func__, req->actual, req->length);
1446 * todo - what should we return here? there's no one else
1447 * even bothering to check the status.
1451 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1452 /* Move to STATUS IN */
1453 s3c_hsotg_ep0_zlp(hsotg, true);
1457 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1461 * s3c_hsotg_read_frameno - read current frame number
1462 * @hsotg: The device instance
1464 * Return the current frame number
1466 static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1470 dsts = readl(hsotg->regs + DSTS);
1471 dsts &= DSTS_SOFFN_MASK;
1472 dsts >>= DSTS_SOFFN_SHIFT;
1478 * s3c_hsotg_handle_rx - RX FIFO has data
1479 * @hsotg: The device instance
1481 * The IRQ handler has detected that the RX FIFO has some data in it
1482 * that requires processing, so find out what is in there and do the
1485 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1486 * chunks, so if you have x packets received on an endpoint you'll get x
1487 * FIFO events delivered, each with a packet's worth of data in it.
1489 * When using DMA, we should not be processing events from the RXFIFO
1490 * as the actual data should be sent to the memory directly and we turn
1491 * on the completion interrupts to get notifications of transfer completion.
1493 static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1495 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1496 u32 epnum, status, size;
1498 WARN_ON(using_dma(hsotg));
1500 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1501 status = grxstsr & GRXSTS_PKTSTS_MASK;
1503 size = grxstsr & GRXSTS_BYTECNT_MASK;
1504 size >>= GRXSTS_BYTECNT_SHIFT;
1507 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1508 __func__, grxstsr, size, epnum);
1510 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1511 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1512 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1515 case GRXSTS_PKTSTS_OUTDONE:
1516 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1517 s3c_hsotg_read_frameno(hsotg));
1519 if (!using_dma(hsotg))
1520 s3c_hsotg_handle_outdone(hsotg, epnum);
1523 case GRXSTS_PKTSTS_SETUPDONE:
1525 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1526 s3c_hsotg_read_frameno(hsotg),
1527 readl(hsotg->regs + DOEPCTL(0)));
1529 * Call s3c_hsotg_handle_outdone here if it was not called from
1530 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1531 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1533 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1534 s3c_hsotg_handle_outdone(hsotg, epnum);
1537 case GRXSTS_PKTSTS_OUTRX:
1538 s3c_hsotg_rx_data(hsotg, epnum, size);
1541 case GRXSTS_PKTSTS_SETUPRX:
1543 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1544 s3c_hsotg_read_frameno(hsotg),
1545 readl(hsotg->regs + DOEPCTL(0)));
1547 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1549 s3c_hsotg_rx_data(hsotg, epnum, size);
1553 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1556 s3c_hsotg_dump(hsotg);
1562 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1563 * @mps: The maximum packet size in bytes.
1565 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1569 return D0EPCTL_MPS_64;
1571 return D0EPCTL_MPS_32;
1573 return D0EPCTL_MPS_16;
1575 return D0EPCTL_MPS_8;
1578 /* bad max packet size, warn and return invalid result */
1584 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1585 * @hsotg: The driver state.
1586 * @ep: The index number of the endpoint
1587 * @mps: The maximum packet size in bytes
1589 * Configure the maximum packet size for the given endpoint, updating
1590 * the hardware control registers to reflect this.
1592 static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1593 unsigned int ep, unsigned int mps, unsigned int dir_in)
1595 struct s3c_hsotg_ep *hs_ep;
1596 void __iomem *regs = hsotg->regs;
1601 hs_ep = index_to_ep(hsotg, ep, dir_in);
1606 /* EP0 is a special case */
1607 mpsval = s3c_hsotg_ep0_mps(mps);
1610 hs_ep->ep.maxpacket = mps;
1613 mpsval = mps & DXEPCTL_MPS_MASK;
1616 mcval = ((mps >> 11) & 0x3) + 1;
1620 hs_ep->ep.maxpacket = mpsval;
1624 reg = readl(regs + DIEPCTL(ep));
1625 reg &= ~DXEPCTL_MPS_MASK;
1627 writel(reg, regs + DIEPCTL(ep));
1629 reg = readl(regs + DOEPCTL(ep));
1630 reg &= ~DXEPCTL_MPS_MASK;
1632 writel(reg, regs + DOEPCTL(ep));
1638 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1642 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1643 * @hsotg: The driver state
1644 * @idx: The index for the endpoint (0..15)
1646 static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1651 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1652 hsotg->regs + GRSTCTL);
1654 /* wait until the fifo is flushed */
1658 val = readl(hsotg->regs + GRSTCTL);
1660 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1663 if (--timeout == 0) {
1665 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1675 * s3c_hsotg_trytx - check to see if anything needs transmitting
1676 * @hsotg: The driver state
1677 * @hs_ep: The driver endpoint to check.
1679 * Check to see if there is a request that has data to send, and if so
1680 * make an attempt to write data into the FIFO.
1682 static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg,
1683 struct s3c_hsotg_ep *hs_ep)
1685 struct s3c_hsotg_req *hs_req = hs_ep->req;
1687 if (!hs_ep->dir_in || !hs_req) {
1689 * if request is not enqueued, we disable interrupts
1690 * for endpoints, excepting ep0
1692 if (hs_ep->index != 0)
1693 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1698 if (hs_req->req.actual < hs_req->req.length) {
1699 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1701 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1708 * s3c_hsotg_complete_in - complete IN transfer
1709 * @hsotg: The device state.
1710 * @hs_ep: The endpoint that has just completed.
1712 * An IN transfer has been completed, update the transfer's state and then
1713 * call the relevant completion routines.
1715 static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1716 struct s3c_hsotg_ep *hs_ep)
1718 struct s3c_hsotg_req *hs_req = hs_ep->req;
1719 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1720 int size_left, size_done;
1723 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1727 /* Finish ZLP handling for IN EP0 transactions */
1728 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1729 dev_dbg(hsotg->dev, "zlp packet sent\n");
1730 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1731 s3c_hsotg_enqueue_setup(hsotg);
1736 * Calculate the size of the transfer by checking how much is left
1737 * in the endpoint size register and then working it out from
1738 * the amount we loaded for the transfer.
1740 * We do this even for DMA, as the transfer may have incremented
1741 * past the end of the buffer (DMA transfers are always 32bit
1745 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1747 size_done = hs_ep->size_loaded - size_left;
1748 size_done += hs_ep->last_load;
1750 if (hs_req->req.actual != size_done)
1751 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1752 __func__, hs_req->req.actual, size_done);
1754 hs_req->req.actual = size_done;
1755 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1756 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1758 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1759 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1760 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1764 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1765 if (hs_ep->send_zlp) {
1766 s3c_hsotg_program_zlp(hsotg, hs_ep);
1767 hs_ep->send_zlp = 0;
1768 /* transfer will be completed on next complete interrupt */
1772 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1773 /* Move to STATUS OUT */
1774 s3c_hsotg_ep0_zlp(hsotg, false);
1778 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1782 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1783 * @hsotg: The driver state
1784 * @idx: The index for the endpoint (0..15)
1785 * @dir_in: Set if this is an IN endpoint
1787 * Process and clear any interrupt pending for an individual endpoint
1789 static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1792 struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1793 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1794 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1795 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1799 ints = readl(hsotg->regs + epint_reg);
1800 ctrl = readl(hsotg->regs + epctl_reg);
1802 /* Clear endpoint interrupts */
1803 writel(ints, hsotg->regs + epint_reg);
1806 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1807 __func__, idx, dir_in ? "in" : "out");
1811 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1812 __func__, idx, dir_in ? "in" : "out", ints);
1814 /* Don't process XferCompl interrupt if it is a setup packet */
1815 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1816 ints &= ~DXEPINT_XFERCOMPL;
1818 if (ints & DXEPINT_XFERCOMPL) {
1819 if (hs_ep->isochronous && hs_ep->interval == 1) {
1820 if (ctrl & DXEPCTL_EOFRNUM)
1821 ctrl |= DXEPCTL_SETEVENFR;
1823 ctrl |= DXEPCTL_SETODDFR;
1824 writel(ctrl, hsotg->regs + epctl_reg);
1828 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1829 __func__, readl(hsotg->regs + epctl_reg),
1830 readl(hsotg->regs + epsiz_reg));
1833 * we get OutDone from the FIFO, so we only need to look
1834 * at completing IN requests here
1837 s3c_hsotg_complete_in(hsotg, hs_ep);
1839 if (idx == 0 && !hs_ep->req)
1840 s3c_hsotg_enqueue_setup(hsotg);
1841 } else if (using_dma(hsotg)) {
1843 * We're using DMA, we need to fire an OutDone here
1844 * as we ignore the RXFIFO.
1847 s3c_hsotg_handle_outdone(hsotg, idx);
1851 if (ints & DXEPINT_EPDISBLD) {
1852 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1855 int epctl = readl(hsotg->regs + epctl_reg);
1857 s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1859 if ((epctl & DXEPCTL_STALL) &&
1860 (epctl & DXEPCTL_EPTYPE_BULK)) {
1861 int dctl = readl(hsotg->regs + DCTL);
1863 dctl |= DCTL_CGNPINNAK;
1864 writel(dctl, hsotg->regs + DCTL);
1869 if (ints & DXEPINT_AHBERR)
1870 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1872 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
1873 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1875 if (using_dma(hsotg) && idx == 0) {
1877 * this is the notification we've received a
1878 * setup packet. In non-DMA mode we'd get this
1879 * from the RXFIFO, instead we need to process
1886 s3c_hsotg_handle_outdone(hsotg, 0);
1890 if (ints & DXEPINT_BACK2BACKSETUP)
1891 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1893 if (dir_in && !hs_ep->isochronous) {
1894 /* not sure if this is important, but we'll clear it anyway */
1895 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
1896 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1900 /* this probably means something bad is happening */
1901 if (ints & DIEPMSK_INTKNEPMISMSK) {
1902 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1906 /* FIFO has space or is empty (see GAHBCFG) */
1907 if (hsotg->dedicated_fifos &&
1908 ints & DIEPMSK_TXFIFOEMPTY) {
1909 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1911 if (!using_dma(hsotg))
1912 s3c_hsotg_trytx(hsotg, hs_ep);
1918 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1919 * @hsotg: The device state.
1921 * Handle updating the device settings after the enumeration phase has
1924 static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
1926 u32 dsts = readl(hsotg->regs + DSTS);
1927 int ep0_mps = 0, ep_mps = 8;
1930 * This should signal the finish of the enumeration phase
1931 * of the USB handshaking, so we should now know what rate
1935 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1938 * note, since we're limited by the size of transfer on EP0, and
1939 * it seems IN transfers must be a even number of packets we do
1940 * not advertise a 64byte MPS on EP0.
1943 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1944 switch (dsts & DSTS_ENUMSPD_MASK) {
1945 case DSTS_ENUMSPD_FS:
1946 case DSTS_ENUMSPD_FS48:
1947 hsotg->gadget.speed = USB_SPEED_FULL;
1948 ep0_mps = EP0_MPS_LIMIT;
1952 case DSTS_ENUMSPD_HS:
1953 hsotg->gadget.speed = USB_SPEED_HIGH;
1954 ep0_mps = EP0_MPS_LIMIT;
1958 case DSTS_ENUMSPD_LS:
1959 hsotg->gadget.speed = USB_SPEED_LOW;
1961 * note, we don't actually support LS in this driver at the
1962 * moment, and the documentation seems to imply that it isn't
1963 * supported by the PHYs on some of the devices.
1967 dev_info(hsotg->dev, "new device is %s\n",
1968 usb_speed_string(hsotg->gadget.speed));
1971 * we should now know the maximum packet size for an
1972 * endpoint, so set the endpoints to a default value.
1977 /* Initialize ep0 for both in and out directions */
1978 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
1979 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
1980 for (i = 1; i < hsotg->num_of_eps; i++) {
1981 if (hsotg->eps_in[i])
1982 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
1983 if (hsotg->eps_out[i])
1984 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
1988 /* ensure after enumeration our EP0 is active */
1990 s3c_hsotg_enqueue_setup(hsotg);
1992 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1993 readl(hsotg->regs + DIEPCTL0),
1994 readl(hsotg->regs + DOEPCTL0));
1998 * kill_all_requests - remove all requests from the endpoint's queue
1999 * @hsotg: The device state.
2000 * @ep: The endpoint the requests may be on.
2001 * @result: The result code to use.
2003 * Go through the requests on the given endpoint and mark them
2004 * completed with the given result code.
2006 static void kill_all_requests(struct dwc2_hsotg *hsotg,
2007 struct s3c_hsotg_ep *ep,
2010 struct s3c_hsotg_req *req, *treq;
2015 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2016 s3c_hsotg_complete_request(hsotg, ep, req,
2019 if (!hsotg->dedicated_fifos)
2021 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2022 if (size < ep->fifo_size)
2023 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2027 * s3c_hsotg_disconnect - disconnect service
2028 * @hsotg: The device state.
2030 * The device has been disconnected. Remove all current
2031 * transactions and signal the gadget driver that this
2034 void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2038 if (!hsotg->connected)
2041 hsotg->connected = 0;
2043 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2044 if (hsotg->eps_in[ep])
2045 kill_all_requests(hsotg, hsotg->eps_in[ep],
2047 if (hsotg->eps_out[ep])
2048 kill_all_requests(hsotg, hsotg->eps_out[ep],
2052 call_gadget(hsotg, disconnect);
2054 EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect);
2057 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2058 * @hsotg: The device state:
2059 * @periodic: True if this is a periodic FIFO interrupt
2061 static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2063 struct s3c_hsotg_ep *ep;
2066 /* look through for any more data to transmit */
2067 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2068 ep = index_to_ep(hsotg, epno, 1);
2076 if ((periodic && !ep->periodic) ||
2077 (!periodic && ep->periodic))
2080 ret = s3c_hsotg_trytx(hsotg, ep);
2086 /* IRQ flags which will trigger a retry around the IRQ loop */
2087 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2092 * s3c_hsotg_corereset - issue softreset to the core
2093 * @hsotg: The device state
2095 * Issue a soft reset to the core, and await the core finishing it.
2097 static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg)
2102 dev_dbg(hsotg->dev, "resetting core\n");
2104 /* issue soft reset */
2105 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2109 grstctl = readl(hsotg->regs + GRSTCTL);
2110 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2112 if (grstctl & GRSTCTL_CSFTRST) {
2113 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2120 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2122 if (timeout-- < 0) {
2123 dev_info(hsotg->dev,
2124 "%s: reset failed, GRSTCTL=%08x\n",
2129 if (!(grstctl & GRSTCTL_AHBIDLE))
2132 break; /* reset done */
2135 dev_dbg(hsotg->dev, "reset successful\n");
2140 * s3c_hsotg_core_init - issue softreset to the core
2141 * @hsotg: The device state
2143 * Issue a soft reset to the core, and await the core finishing it.
2145 void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg)
2147 s3c_hsotg_corereset(hsotg);
2150 * we must now enable ep0 ready for host detection and then
2151 * set configuration.
2154 /* set the PLL on, remove the HNP/SRP and set the PHY */
2155 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2156 (0x5 << 10), hsotg->regs + GUSBCFG);
2158 s3c_hsotg_init_fifo(hsotg);
2160 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2162 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2164 /* Clear any pending OTG interrupts */
2165 writel(0xffffffff, hsotg->regs + GOTGINT);
2167 /* Clear any pending interrupts */
2168 writel(0xffffffff, hsotg->regs + GINTSTS);
2170 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2171 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2172 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2173 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2174 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2175 hsotg->regs + GINTMSK);
2177 if (using_dma(hsotg))
2178 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2179 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2180 hsotg->regs + GAHBCFG);
2182 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2183 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2184 GAHBCFG_GLBL_INTR_EN,
2185 hsotg->regs + GAHBCFG);
2188 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2189 * when we have no data to transfer. Otherwise we get being flooded by
2193 writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2194 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2195 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2196 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2197 DIEPMSK_INTKNEPMISMSK,
2198 hsotg->regs + DIEPMSK);
2201 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2202 * DMA mode we may need this.
2204 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2205 DIEPMSK_TIMEOUTMSK) : 0) |
2206 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2208 hsotg->regs + DOEPMSK);
2210 writel(0, hsotg->regs + DAINTMSK);
2212 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2213 readl(hsotg->regs + DIEPCTL0),
2214 readl(hsotg->regs + DOEPCTL0));
2216 /* enable in and out endpoint interrupts */
2217 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2220 * Enable the RXFIFO when in slave mode, as this is how we collect
2221 * the data. In DMA mode, we get events from the FIFO but also
2222 * things we cannot process, so do not use it.
2224 if (!using_dma(hsotg))
2225 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2227 /* Enable interrupts for EP0 in and out */
2228 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2229 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2231 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2232 udelay(10); /* see openiboot */
2233 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2235 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2238 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2239 * writing to the EPCTL register..
2242 /* set to read 1 8byte packet */
2243 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2244 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2246 writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2247 DXEPCTL_CNAK | DXEPCTL_EPENA |
2249 hsotg->regs + DOEPCTL0);
2251 /* enable, but don't activate EP0in */
2252 writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2253 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2255 s3c_hsotg_enqueue_setup(hsotg);
2257 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2258 readl(hsotg->regs + DIEPCTL0),
2259 readl(hsotg->regs + DOEPCTL0));
2261 /* clear global NAKs */
2262 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON,
2263 hsotg->regs + DCTL);
2265 /* must be at-least 3ms to allow bus to see disconnect */
2268 hsotg->last_rst = jiffies;
2271 static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2273 /* set the soft-disconnect bit */
2274 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2277 void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2279 /* remove the soft-disconnect and let's go */
2280 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2284 * s3c_hsotg_irq - handle device interrupt
2285 * @irq: The IRQ number triggered
2286 * @pw: The pw value when registered the handler.
2288 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2290 struct dwc2_hsotg *hsotg = pw;
2291 int retry_count = 8;
2295 spin_lock(&hsotg->lock);
2297 gintsts = readl(hsotg->regs + GINTSTS);
2298 gintmsk = readl(hsotg->regs + GINTMSK);
2300 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2301 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2305 if (gintsts & GINTSTS_ENUMDONE) {
2306 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2308 s3c_hsotg_irq_enumdone(hsotg);
2311 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2312 u32 daint = readl(hsotg->regs + DAINT);
2313 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2314 u32 daint_out, daint_in;
2318 daint_out = daint >> DAINT_OUTEP_SHIFT;
2319 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2321 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2323 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2324 ep++, daint_out >>= 1) {
2326 s3c_hsotg_epint(hsotg, ep, 0);
2329 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2330 ep++, daint_in >>= 1) {
2332 s3c_hsotg_epint(hsotg, ep, 1);
2336 if (gintsts & GINTSTS_USBRST) {
2338 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2340 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2341 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2342 readl(hsotg->regs + GNPTXSTS));
2344 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2346 /* Report disconnection if it is not already done. */
2347 s3c_hsotg_disconnect(hsotg);
2349 if (usb_status & GOTGCTL_BSESVLD) {
2350 if (time_after(jiffies, hsotg->last_rst +
2351 msecs_to_jiffies(200))) {
2353 kill_all_requests(hsotg, hsotg->eps_out[0],
2356 s3c_hsotg_core_init_disconnected(hsotg);
2357 s3c_hsotg_core_connect(hsotg);
2362 /* check both FIFOs */
2364 if (gintsts & GINTSTS_NPTXFEMP) {
2365 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2368 * Disable the interrupt to stop it happening again
2369 * unless one of these endpoint routines decides that
2370 * it needs re-enabling
2373 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2374 s3c_hsotg_irq_fifoempty(hsotg, false);
2377 if (gintsts & GINTSTS_PTXFEMP) {
2378 dev_dbg(hsotg->dev, "PTxFEmp\n");
2380 /* See note in GINTSTS_NPTxFEmp */
2382 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2383 s3c_hsotg_irq_fifoempty(hsotg, true);
2386 if (gintsts & GINTSTS_RXFLVL) {
2388 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2389 * we need to retry s3c_hsotg_handle_rx if this is still
2393 s3c_hsotg_handle_rx(hsotg);
2396 if (gintsts & GINTSTS_ERLYSUSP) {
2397 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2398 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2402 * these next two seem to crop-up occasionally causing the core
2403 * to shutdown the USB transfer, so try clearing them and logging
2407 if (gintsts & GINTSTS_GOUTNAKEFF) {
2408 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2410 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2412 s3c_hsotg_dump(hsotg);
2415 if (gintsts & GINTSTS_GINNAKEFF) {
2416 dev_info(hsotg->dev, "GINNakEff triggered\n");
2418 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2420 s3c_hsotg_dump(hsotg);
2424 * if we've had fifo events, we should try and go around the
2425 * loop again to see if there's any point in returning yet.
2428 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2431 spin_unlock(&hsotg->lock);
2437 * s3c_hsotg_ep_enable - enable the given endpoint
2438 * @ep: The USB endpint to configure
2439 * @desc: The USB endpoint descriptor to configure with.
2441 * This is called from the USB gadget code's usb_ep_enable().
2443 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2444 const struct usb_endpoint_descriptor *desc)
2446 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2447 struct dwc2_hsotg *hsotg = hs_ep->parent;
2448 unsigned long flags;
2449 unsigned int index = hs_ep->index;
2453 unsigned int dir_in;
2454 unsigned int i, val, size;
2458 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2459 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2460 desc->wMaxPacketSize, desc->bInterval);
2462 /* not to be called for EP0 */
2463 WARN_ON(index == 0);
2465 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2466 if (dir_in != hs_ep->dir_in) {
2467 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2471 mps = usb_endpoint_maxp(desc);
2473 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2475 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2476 epctrl = readl(hsotg->regs + epctrl_reg);
2478 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2479 __func__, epctrl, epctrl_reg);
2481 spin_lock_irqsave(&hsotg->lock, flags);
2483 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2484 epctrl |= DXEPCTL_MPS(mps);
2487 * mark the endpoint as active, otherwise the core may ignore
2488 * transactions entirely for this endpoint
2490 epctrl |= DXEPCTL_USBACTEP;
2493 * set the NAK status on the endpoint, otherwise we might try and
2494 * do something with data that we've yet got a request to process
2495 * since the RXFIFO will take data for an endpoint even if the
2496 * size register hasn't been set.
2499 epctrl |= DXEPCTL_SNAK;
2501 /* update the endpoint state */
2502 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2504 /* default, set to non-periodic */
2505 hs_ep->isochronous = 0;
2506 hs_ep->periodic = 0;
2508 hs_ep->interval = desc->bInterval;
2510 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2511 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2513 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2514 case USB_ENDPOINT_XFER_ISOC:
2515 epctrl |= DXEPCTL_EPTYPE_ISO;
2516 epctrl |= DXEPCTL_SETEVENFR;
2517 hs_ep->isochronous = 1;
2519 hs_ep->periodic = 1;
2522 case USB_ENDPOINT_XFER_BULK:
2523 epctrl |= DXEPCTL_EPTYPE_BULK;
2526 case USB_ENDPOINT_XFER_INT:
2528 hs_ep->periodic = 1;
2530 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2533 case USB_ENDPOINT_XFER_CONTROL:
2534 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2538 /* If fifo is already allocated for this ep */
2539 if (hs_ep->fifo_index) {
2540 size = hs_ep->ep.maxpacket * hs_ep->mc;
2541 /* If bigger fifo is required deallocate current one */
2542 if (size > hs_ep->fifo_size) {
2543 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2544 hs_ep->fifo_index = 0;
2545 hs_ep->fifo_size = 0;
2550 * if the hardware has dedicated fifos, we must give each IN EP
2551 * a unique tx-fifo even if it is non-periodic.
2553 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2555 u32 fifo_size = UINT_MAX;
2556 size = hs_ep->ep.maxpacket*hs_ep->mc;
2557 for (i = 1; i < hsotg->num_of_eps; ++i) {
2558 if (hsotg->fifo_map & (1<<i))
2560 val = readl(hsotg->regs + DPTXFSIZN(i));
2561 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2564 /* Search for smallest acceptable fifo */
2565 if (val < fifo_size) {
2572 "%s: No suitable fifo found\n", __func__);
2576 hsotg->fifo_map |= 1 << fifo_index;
2577 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2578 hs_ep->fifo_index = fifo_index;
2579 hs_ep->fifo_size = fifo_size;
2582 /* for non control endpoints, set PID to D0 */
2584 epctrl |= DXEPCTL_SETD0PID;
2586 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2589 writel(epctrl, hsotg->regs + epctrl_reg);
2590 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2591 __func__, readl(hsotg->regs + epctrl_reg));
2593 /* enable the endpoint interrupt */
2594 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2597 spin_unlock_irqrestore(&hsotg->lock, flags);
2602 * s3c_hsotg_ep_disable - disable given endpoint
2603 * @ep: The endpoint to disable.
2605 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2607 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2608 struct dwc2_hsotg *hsotg = hs_ep->parent;
2609 int dir_in = hs_ep->dir_in;
2610 int index = hs_ep->index;
2611 unsigned long flags;
2615 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2617 if (ep == &hsotg->eps_out[0]->ep) {
2618 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2622 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2624 spin_lock_irqsave(&hsotg->lock, flags);
2626 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2627 hs_ep->fifo_index = 0;
2628 hs_ep->fifo_size = 0;
2630 ctrl = readl(hsotg->regs + epctrl_reg);
2631 ctrl &= ~DXEPCTL_EPENA;
2632 ctrl &= ~DXEPCTL_USBACTEP;
2633 ctrl |= DXEPCTL_SNAK;
2635 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2636 writel(ctrl, hsotg->regs + epctrl_reg);
2638 /* disable endpoint interrupts */
2639 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2641 /* terminate all requests with shutdown */
2642 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2644 spin_unlock_irqrestore(&hsotg->lock, flags);
2649 * on_list - check request is on the given endpoint
2650 * @ep: The endpoint to check.
2651 * @test: The request to test if it is on the endpoint.
2653 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2655 struct s3c_hsotg_req *req, *treq;
2657 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2666 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2667 * @ep: The endpoint to dequeue.
2668 * @req: The request to be removed from a queue.
2670 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2672 struct s3c_hsotg_req *hs_req = our_req(req);
2673 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2674 struct dwc2_hsotg *hs = hs_ep->parent;
2675 unsigned long flags;
2677 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2679 spin_lock_irqsave(&hs->lock, flags);
2681 if (!on_list(hs_ep, hs_req)) {
2682 spin_unlock_irqrestore(&hs->lock, flags);
2686 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2687 spin_unlock_irqrestore(&hs->lock, flags);
2693 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2694 * @ep: The endpoint to set halt.
2695 * @value: Set or unset the halt.
2697 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2699 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2700 struct dwc2_hsotg *hs = hs_ep->parent;
2701 int index = hs_ep->index;
2706 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2710 s3c_hsotg_stall_ep0(hs);
2713 "%s: can't clear halt on ep0\n", __func__);
2717 if (hs_ep->dir_in) {
2718 epreg = DIEPCTL(index);
2719 epctl = readl(hs->regs + epreg);
2722 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2723 if (epctl & DXEPCTL_EPENA)
2724 epctl |= DXEPCTL_EPDIS;
2726 epctl &= ~DXEPCTL_STALL;
2727 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2728 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2729 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2730 epctl |= DXEPCTL_SETD0PID;
2732 writel(epctl, hs->regs + epreg);
2735 epreg = DOEPCTL(index);
2736 epctl = readl(hs->regs + epreg);
2739 epctl |= DXEPCTL_STALL;
2741 epctl &= ~DXEPCTL_STALL;
2742 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2743 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2744 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2745 epctl |= DXEPCTL_SETD0PID;
2747 writel(epctl, hs->regs + epreg);
2750 hs_ep->halted = value;
2756 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2757 * @ep: The endpoint to set halt.
2758 * @value: Set or unset the halt.
2760 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2762 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2763 struct dwc2_hsotg *hs = hs_ep->parent;
2764 unsigned long flags = 0;
2767 spin_lock_irqsave(&hs->lock, flags);
2768 ret = s3c_hsotg_ep_sethalt(ep, value);
2769 spin_unlock_irqrestore(&hs->lock, flags);
2774 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2775 .enable = s3c_hsotg_ep_enable,
2776 .disable = s3c_hsotg_ep_disable,
2777 .alloc_request = s3c_hsotg_ep_alloc_request,
2778 .free_request = s3c_hsotg_ep_free_request,
2779 .queue = s3c_hsotg_ep_queue_lock,
2780 .dequeue = s3c_hsotg_ep_dequeue,
2781 .set_halt = s3c_hsotg_ep_sethalt_lock,
2782 /* note, don't believe we have any call for the fifo routines */
2786 * s3c_hsotg_phy_enable - enable platform phy dev
2787 * @hsotg: The driver state
2789 * A wrapper for platform code responsible for controlling
2790 * low-level USB code
2792 static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg)
2794 struct platform_device *pdev = to_platform_device(hsotg->dev);
2796 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2799 usb_phy_init(hsotg->uphy);
2800 else if (hsotg->plat && hsotg->plat->phy_init)
2801 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2803 phy_init(hsotg->phy);
2804 phy_power_on(hsotg->phy);
2809 * s3c_hsotg_phy_disable - disable platform phy dev
2810 * @hsotg: The driver state
2812 * A wrapper for platform code responsible for controlling
2813 * low-level USB code
2815 static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg)
2817 struct platform_device *pdev = to_platform_device(hsotg->dev);
2820 usb_phy_shutdown(hsotg->uphy);
2821 else if (hsotg->plat && hsotg->plat->phy_exit)
2822 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2824 phy_power_off(hsotg->phy);
2825 phy_exit(hsotg->phy);
2830 * s3c_hsotg_init - initalize the usb core
2831 * @hsotg: The driver state
2833 static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
2835 /* unmask subset of endpoint interrupts */
2837 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2838 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2839 hsotg->regs + DIEPMSK);
2841 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2842 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2843 hsotg->regs + DOEPMSK);
2845 writel(0, hsotg->regs + DAINTMSK);
2847 /* Be in disconnected state until gadget is registered */
2848 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2851 /* post global nak until we're ready */
2852 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2853 hsotg->regs + DCTL);
2858 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2859 readl(hsotg->regs + GRXFSIZ),
2860 readl(hsotg->regs + GNPTXFSIZ));
2862 s3c_hsotg_init_fifo(hsotg);
2864 /* set the PLL on, remove the HNP/SRP and set the PHY */
2865 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2866 hsotg->regs + GUSBCFG);
2868 if (using_dma(hsotg))
2869 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
2873 * s3c_hsotg_udc_start - prepare the udc for work
2874 * @gadget: The usb gadget state
2875 * @driver: The usb gadget driver
2877 * Perform initialization to prepare udc device and driver
2880 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2881 struct usb_gadget_driver *driver)
2883 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2884 unsigned long flags;
2888 pr_err("%s: called with no device\n", __func__);
2893 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2897 if (driver->max_speed < USB_SPEED_FULL)
2898 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2900 if (!driver->setup) {
2901 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2905 mutex_lock(&hsotg->init_mutex);
2906 WARN_ON(hsotg->driver);
2908 driver->driver.bus = NULL;
2909 hsotg->driver = driver;
2910 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2911 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2913 clk_enable(hsotg->clk);
2915 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2918 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2922 s3c_hsotg_phy_enable(hsotg);
2923 if (!IS_ERR_OR_NULL(hsotg->uphy))
2924 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
2926 spin_lock_irqsave(&hsotg->lock, flags);
2927 s3c_hsotg_init(hsotg);
2928 s3c_hsotg_core_init_disconnected(hsotg);
2930 spin_unlock_irqrestore(&hsotg->lock, flags);
2932 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2934 mutex_unlock(&hsotg->init_mutex);
2939 mutex_unlock(&hsotg->init_mutex);
2940 hsotg->driver = NULL;
2945 * s3c_hsotg_udc_stop - stop the udc
2946 * @gadget: The usb gadget state
2947 * @driver: The usb gadget driver
2949 * Stop udc hw block and stay tunned for future transmissions
2951 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget)
2953 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2954 unsigned long flags = 0;
2960 mutex_lock(&hsotg->init_mutex);
2962 /* all endpoints should be shutdown */
2963 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
2964 if (hsotg->eps_in[ep])
2965 s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
2966 if (hsotg->eps_out[ep])
2967 s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
2970 spin_lock_irqsave(&hsotg->lock, flags);
2972 hsotg->driver = NULL;
2973 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2976 spin_unlock_irqrestore(&hsotg->lock, flags);
2978 if (!IS_ERR_OR_NULL(hsotg->uphy))
2979 otg_set_peripheral(hsotg->uphy->otg, NULL);
2980 s3c_hsotg_phy_disable(hsotg);
2982 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2984 clk_disable(hsotg->clk);
2986 mutex_unlock(&hsotg->init_mutex);
2992 * s3c_hsotg_gadget_getframe - read the frame number
2993 * @gadget: The usb gadget state
2995 * Read the {micro} frame number
2997 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2999 return s3c_hsotg_read_frameno(to_hsotg(gadget));
3003 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3004 * @gadget: The usb gadget state
3005 * @is_on: Current state of the USB PHY
3007 * Connect/Disconnect the USB PHY pullup
3009 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3011 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3012 unsigned long flags = 0;
3014 dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
3016 mutex_lock(&hsotg->init_mutex);
3017 spin_lock_irqsave(&hsotg->lock, flags);
3019 clk_enable(hsotg->clk);
3021 s3c_hsotg_core_connect(hsotg);
3023 s3c_hsotg_core_disconnect(hsotg);
3024 s3c_hsotg_disconnect(hsotg);
3026 clk_disable(hsotg->clk);
3029 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3030 spin_unlock_irqrestore(&hsotg->lock, flags);
3031 mutex_unlock(&hsotg->init_mutex);
3036 static int s3c_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3038 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3039 unsigned long flags;
3041 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3042 spin_lock_irqsave(&hsotg->lock, flags);
3045 /* Kill any ep0 requests as controller will be reinitialized */
3046 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3047 s3c_hsotg_core_init_disconnected(hsotg);
3049 s3c_hsotg_core_connect(hsotg);
3051 s3c_hsotg_core_disconnect(hsotg);
3052 s3c_hsotg_disconnect(hsotg);
3055 spin_unlock_irqrestore(&hsotg->lock, flags);
3060 * s3c_hsotg_vbus_draw - report bMaxPower field
3061 * @gadget: The usb gadget state
3062 * @mA: Amount of current
3064 * Report how much power the device may consume to the phy.
3066 static int s3c_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3068 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3070 if (IS_ERR_OR_NULL(hsotg->uphy))
3072 return usb_phy_set_power(hsotg->uphy, mA);
3075 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3076 .get_frame = s3c_hsotg_gadget_getframe,
3077 .udc_start = s3c_hsotg_udc_start,
3078 .udc_stop = s3c_hsotg_udc_stop,
3079 .pullup = s3c_hsotg_pullup,
3080 .vbus_session = s3c_hsotg_vbus_session,
3081 .vbus_draw = s3c_hsotg_vbus_draw,
3085 * s3c_hsotg_initep - initialise a single endpoint
3086 * @hsotg: The device state.
3087 * @hs_ep: The endpoint to be initialised.
3088 * @epnum: The endpoint number
3090 * Initialise the given endpoint (as part of the probe and device state
3091 * creation) to give to the gadget driver. Setup the endpoint name, any
3092 * direction information and other state that may be required.
3094 static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg,
3095 struct s3c_hsotg_ep *hs_ep,
3108 hs_ep->dir_in = dir_in;
3109 hs_ep->index = epnum;
3111 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3113 INIT_LIST_HEAD(&hs_ep->queue);
3114 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3116 /* add to the list of endpoints known by the gadget driver */
3118 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3120 hs_ep->parent = hsotg;
3121 hs_ep->ep.name = hs_ep->name;
3122 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3123 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3126 * if we're using dma, we need to set the next-endpoint pointer
3127 * to be something valid.
3130 if (using_dma(hsotg)) {
3131 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3133 writel(next, hsotg->regs + DIEPCTL(epnum));
3135 writel(next, hsotg->regs + DOEPCTL(epnum));
3140 * s3c_hsotg_hw_cfg - read HW configuration registers
3141 * @param: The device state
3143 * Read the USB core HW configuration registers
3145 static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3151 /* check hardware configuration */
3153 cfg = readl(hsotg->regs + GHWCFG2);
3154 hsotg->num_of_eps = (cfg >> 10) & 0xF;
3156 hsotg->num_of_eps++;
3158 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep),
3160 if (!hsotg->eps_in[0])
3162 /* Same s3c_hsotg_ep is used in both directions for ep0 */
3163 hsotg->eps_out[0] = hsotg->eps_in[0];
3165 cfg = readl(hsotg->regs + GHWCFG1);
3166 for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3168 /* Direction in or both */
3169 if (!(ep_type & 2)) {
3170 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3171 sizeof(struct s3c_hsotg_ep), GFP_KERNEL);
3172 if (!hsotg->eps_in[i])
3175 /* Direction out or both */
3176 if (!(ep_type & 1)) {
3177 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3178 sizeof(struct s3c_hsotg_ep), GFP_KERNEL);
3179 if (!hsotg->eps_out[i])
3184 cfg = readl(hsotg->regs + GHWCFG3);
3185 hsotg->fifo_mem = (cfg >> 16);
3187 cfg = readl(hsotg->regs + GHWCFG4);
3188 hsotg->dedicated_fifos = (cfg >> 25) & 1;
3190 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3192 hsotg->dedicated_fifos ? "dedicated" : "shared",
3198 * s3c_hsotg_dump - dump state of the udc
3199 * @param: The device state
3201 static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg)
3204 struct device *dev = hsotg->dev;
3205 void __iomem *regs = hsotg->regs;
3209 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3210 readl(regs + DCFG), readl(regs + DCTL),
3211 readl(regs + DIEPMSK));
3213 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3214 readl(regs + GAHBCFG), readl(regs + 0x44));
3216 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3217 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3219 /* show periodic fifo settings */
3221 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3222 val = readl(regs + DPTXFSIZN(idx));
3223 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3224 val >> FIFOSIZE_DEPTH_SHIFT,
3225 val & FIFOSIZE_STARTADDR_MASK);
3228 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3230 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3231 readl(regs + DIEPCTL(idx)),
3232 readl(regs + DIEPTSIZ(idx)),
3233 readl(regs + DIEPDMA(idx)));
3235 val = readl(regs + DOEPCTL(idx));
3237 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3238 idx, readl(regs + DOEPCTL(idx)),
3239 readl(regs + DOEPTSIZ(idx)),
3240 readl(regs + DOEPDMA(idx)));
3244 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3245 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3250 * state_show - debugfs: show overall driver and device state.
3251 * @seq: The seq file to write to.
3252 * @v: Unused parameter.
3254 * This debugfs entry shows the overall state of the hardware and
3255 * some general information about each of the endpoints available
3258 static int state_show(struct seq_file *seq, void *v)
3260 struct dwc2_hsotg *hsotg = seq->private;
3261 void __iomem *regs = hsotg->regs;
3264 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3267 readl(regs + DSTS));
3269 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3270 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3272 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3273 readl(regs + GINTMSK),
3274 readl(regs + GINTSTS));
3276 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3277 readl(regs + DAINTMSK),
3278 readl(regs + DAINT));
3280 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3281 readl(regs + GNPTXSTS),
3282 readl(regs + GRXSTSR));
3284 seq_puts(seq, "\nEndpoint status:\n");
3286 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3289 in = readl(regs + DIEPCTL(idx));
3290 out = readl(regs + DOEPCTL(idx));
3292 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3295 in = readl(regs + DIEPTSIZ(idx));
3296 out = readl(regs + DOEPTSIZ(idx));
3298 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3301 seq_puts(seq, "\n");
3307 static int state_open(struct inode *inode, struct file *file)
3309 return single_open(file, state_show, inode->i_private);
3312 static const struct file_operations state_fops = {
3313 .owner = THIS_MODULE,
3316 .llseek = seq_lseek,
3317 .release = single_release,
3321 * fifo_show - debugfs: show the fifo information
3322 * @seq: The seq_file to write data to.
3323 * @v: Unused parameter.
3325 * Show the FIFO information for the overall fifo and all the
3326 * periodic transmission FIFOs.
3328 static int fifo_show(struct seq_file *seq, void *v)
3330 struct dwc2_hsotg *hsotg = seq->private;
3331 void __iomem *regs = hsotg->regs;
3335 seq_puts(seq, "Non-periodic FIFOs:\n");
3336 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3338 val = readl(regs + GNPTXFSIZ);
3339 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3340 val >> FIFOSIZE_DEPTH_SHIFT,
3341 val & FIFOSIZE_DEPTH_MASK);
3343 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3345 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3346 val = readl(regs + DPTXFSIZN(idx));
3348 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3349 val >> FIFOSIZE_DEPTH_SHIFT,
3350 val & FIFOSIZE_STARTADDR_MASK);
3356 static int fifo_open(struct inode *inode, struct file *file)
3358 return single_open(file, fifo_show, inode->i_private);
3361 static const struct file_operations fifo_fops = {
3362 .owner = THIS_MODULE,
3365 .llseek = seq_lseek,
3366 .release = single_release,
3370 static const char *decode_direction(int is_in)
3372 return is_in ? "in" : "out";
3376 * ep_show - debugfs: show the state of an endpoint.
3377 * @seq: The seq_file to write data to.
3378 * @v: Unused parameter.
3380 * This debugfs entry shows the state of the given endpoint (one is
3381 * registered for each available).
3383 static int ep_show(struct seq_file *seq, void *v)
3385 struct s3c_hsotg_ep *ep = seq->private;
3386 struct dwc2_hsotg *hsotg = ep->parent;
3387 struct s3c_hsotg_req *req;
3388 void __iomem *regs = hsotg->regs;
3389 int index = ep->index;
3390 int show_limit = 15;
3391 unsigned long flags;
3393 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3394 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3396 /* first show the register state */
3398 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3399 readl(regs + DIEPCTL(index)),
3400 readl(regs + DOEPCTL(index)));
3402 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3403 readl(regs + DIEPDMA(index)),
3404 readl(regs + DOEPDMA(index)));
3406 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3407 readl(regs + DIEPINT(index)),
3408 readl(regs + DOEPINT(index)));
3410 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3411 readl(regs + DIEPTSIZ(index)),
3412 readl(regs + DOEPTSIZ(index)));
3414 seq_puts(seq, "\n");
3415 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3416 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3418 seq_printf(seq, "request list (%p,%p):\n",
3419 ep->queue.next, ep->queue.prev);
3421 spin_lock_irqsave(&hsotg->lock, flags);
3423 list_for_each_entry(req, &ep->queue, queue) {
3424 if (--show_limit < 0) {
3425 seq_puts(seq, "not showing more requests...\n");
3429 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3430 req == ep->req ? '*' : ' ',
3431 req, req->req.length, req->req.buf);
3432 seq_printf(seq, "%d done, res %d\n",
3433 req->req.actual, req->req.status);
3436 spin_unlock_irqrestore(&hsotg->lock, flags);
3441 static int ep_open(struct inode *inode, struct file *file)
3443 return single_open(file, ep_show, inode->i_private);
3446 static const struct file_operations ep_fops = {
3447 .owner = THIS_MODULE,
3450 .llseek = seq_lseek,
3451 .release = single_release,
3455 * s3c_hsotg_create_debug - create debugfs directory and files
3456 * @hsotg: The driver state
3458 * Create the debugfs files to allow the user to get information
3459 * about the state of the system. The directory name is created
3460 * with the same name as the device itself, in case we end up
3461 * with multiple blocks in future systems.
3463 static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg)
3465 struct dentry *root;
3468 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3469 hsotg->debug_root = root;
3471 dev_err(hsotg->dev, "cannot create debug root\n");
3475 /* create general state file */
3477 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3478 hsotg, &state_fops);
3480 if (IS_ERR(hsotg->debug_file))
3481 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3483 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3486 if (IS_ERR(hsotg->debug_fifo))
3487 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3489 /* Create one file for each out endpoint */
3490 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3491 struct s3c_hsotg_ep *ep;
3493 ep = hsotg->eps_out[epidx];
3495 ep->debugfs = debugfs_create_file(ep->name, 0444,
3496 root, ep, &ep_fops);
3498 if (IS_ERR(ep->debugfs))
3499 dev_err(hsotg->dev, "failed to create %s debug file\n",
3503 /* Create one file for each in endpoint. EP0 is handled with out eps */
3504 for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) {
3505 struct s3c_hsotg_ep *ep;
3507 ep = hsotg->eps_in[epidx];
3509 ep->debugfs = debugfs_create_file(ep->name, 0444,
3510 root, ep, &ep_fops);
3512 if (IS_ERR(ep->debugfs))
3513 dev_err(hsotg->dev, "failed to create %s debug file\n",
3520 * s3c_hsotg_delete_debug - cleanup debugfs entries
3521 * @hsotg: The driver state
3523 * Cleanup (remove) the debugfs files for use on module exit.
3525 static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg)
3529 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3530 if (hsotg->eps_in[epidx])
3531 debugfs_remove(hsotg->eps_in[epidx]->debugfs);
3532 if (hsotg->eps_out[epidx])
3533 debugfs_remove(hsotg->eps_out[epidx]->debugfs);
3536 debugfs_remove(hsotg->debug_file);
3537 debugfs_remove(hsotg->debug_fifo);
3538 debugfs_remove(hsotg->debug_root);
3542 static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3544 struct device_node *np = hsotg->dev->of_node;
3548 /* Enable dma if requested in device tree */
3549 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3552 * Register TX periodic fifo size per endpoint.
3553 * EP0 is excluded since it has no fifo configuration.
3555 if (!of_find_property(np, "g-tx-fifo-size", &len))
3560 /* Read tx fifo sizes other than ep0 */
3561 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3562 &hsotg->g_tx_fifo_sz[1], len))
3568 /* Make remaining TX fifos unavailable */
3569 if (len < MAX_EPS_CHANNELS) {
3570 for (i = len; i < MAX_EPS_CHANNELS; i++)
3571 hsotg->g_tx_fifo_sz[i] = 0;
3575 /* Register RX fifo size */
3576 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3578 /* Register NPTX fifo size */
3579 of_property_read_u32(np, "g-np-tx-fifo-size",
3580 &hsotg->g_np_g_tx_fifo_sz);
3583 static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3587 * dwc2_gadget_init - init function for gadget
3588 * @dwc2: The data structure for the DWC2 driver.
3589 * @irq: The IRQ number for the controller.
3591 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3593 struct device *dev = hsotg->dev;
3594 struct s3c_hsotg_plat *plat = dev->platform_data;
3598 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3600 /* Set default UTMI width */
3601 hsotg->phyif = GUSBCFG_PHYIF16;
3603 s3c_hsotg_of_probe(hsotg);
3605 /* Initialize to legacy fifo configuration values */
3606 hsotg->g_rx_fifo_sz = 2048;
3607 hsotg->g_np_g_tx_fifo_sz = 1024;
3608 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3609 /* Device tree specific probe */
3610 s3c_hsotg_of_probe(hsotg);
3611 /* Dump fifo information */
3612 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3613 hsotg->g_np_g_tx_fifo_sz);
3614 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3615 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3616 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3617 hsotg->g_tx_fifo_sz[i]);
3619 * If platform probe couldn't find a generic PHY or an old style
3620 * USB PHY, fall back to pdata
3622 if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
3623 plat = dev_get_platdata(dev);
3626 "no platform data or transceiver defined\n");
3627 return -EPROBE_DEFER;
3630 } else if (hsotg->phy) {
3632 * If using the generic PHY framework, check if the PHY bus
3633 * width is 8-bit and set the phyif appropriately.
3635 if (phy_get_bus_width(hsotg->phy) == 8)
3636 hsotg->phyif = GUSBCFG_PHYIF8;
3639 hsotg->clk = devm_clk_get(dev, "otg");
3640 if (IS_ERR(hsotg->clk)) {
3642 dev_dbg(dev, "cannot get otg clock\n");
3645 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3646 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3647 hsotg->gadget.name = dev_name(dev);
3649 /* reset the system */
3651 ret = clk_prepare_enable(hsotg->clk);
3653 dev_err(dev, "failed to enable otg clk\n");
3660 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3661 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3663 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3666 dev_err(dev, "failed to request supplies: %d\n", ret);
3670 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3674 dev_err(dev, "failed to enable supplies: %d\n", ret);
3678 /* usb phy enable */
3679 s3c_hsotg_phy_enable(hsotg);
3682 * Force Device mode before initialization.
3683 * This allows correctly configuring fifo for device mode.
3685 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE);
3686 __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3689 * According to Synopsys databook, this sleep is needed for the force
3690 * device mode to take effect.
3694 s3c_hsotg_corereset(hsotg);
3695 ret = s3c_hsotg_hw_cfg(hsotg);
3697 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3701 s3c_hsotg_init(hsotg);
3703 /* Switch back to default configuration */
3704 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3706 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3707 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3708 if (!hsotg->ctrl_buff) {
3709 dev_err(dev, "failed to allocate ctrl request buff\n");
3714 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3715 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3716 if (!hsotg->ep0_buff) {
3717 dev_err(dev, "failed to allocate ctrl reply buff\n");
3722 ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED,
3723 dev_name(hsotg->dev), hsotg);
3725 s3c_hsotg_phy_disable(hsotg);
3726 clk_disable_unprepare(hsotg->clk);
3727 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3729 dev_err(dev, "cannot claim IRQ for gadget\n");
3733 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3735 if (hsotg->num_of_eps == 0) {
3736 dev_err(dev, "wrong number of EPs (zero)\n");
3741 /* setup endpoint information */
3743 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3744 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3746 /* allocate EP0 request */
3748 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3750 if (!hsotg->ctrl_req) {
3751 dev_err(dev, "failed to allocate ctrl req\n");
3756 /* initialise the endpoints now the core has been initialised */
3757 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3758 if (hsotg->eps_in[epnum])
3759 s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3761 if (hsotg->eps_out[epnum])
3762 s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3766 /* disable power and clock */
3767 s3c_hsotg_phy_disable(hsotg);
3769 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3772 dev_err(dev, "failed to disable supplies: %d\n", ret);
3776 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3780 s3c_hsotg_create_debug(hsotg);
3782 s3c_hsotg_dump(hsotg);
3787 s3c_hsotg_phy_disable(hsotg);
3789 clk_disable_unprepare(hsotg->clk);
3793 EXPORT_SYMBOL_GPL(dwc2_gadget_init);
3796 * s3c_hsotg_remove - remove function for hsotg driver
3797 * @pdev: The platform information for the driver
3799 int s3c_hsotg_remove(struct dwc2_hsotg *hsotg)
3801 usb_del_gadget_udc(&hsotg->gadget);
3802 s3c_hsotg_delete_debug(hsotg);
3803 clk_disable_unprepare(hsotg->clk);
3807 EXPORT_SYMBOL_GPL(s3c_hsotg_remove);
3809 int s3c_hsotg_suspend(struct dwc2_hsotg *hsotg)
3811 unsigned long flags;
3814 mutex_lock(&hsotg->init_mutex);
3816 if (hsotg->driver) {
3819 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3820 hsotg->driver->driver.name);
3822 spin_lock_irqsave(&hsotg->lock, flags);
3824 s3c_hsotg_core_disconnect(hsotg);
3825 s3c_hsotg_disconnect(hsotg);
3826 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3827 spin_unlock_irqrestore(&hsotg->lock, flags);
3829 s3c_hsotg_phy_disable(hsotg);
3831 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3832 if (hsotg->eps_in[ep])
3833 s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3834 if (hsotg->eps_out[ep])
3835 s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3838 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3840 clk_disable(hsotg->clk);
3843 mutex_unlock(&hsotg->init_mutex);
3847 EXPORT_SYMBOL_GPL(s3c_hsotg_suspend);
3849 int s3c_hsotg_resume(struct dwc2_hsotg *hsotg)
3851 unsigned long flags;
3854 mutex_lock(&hsotg->init_mutex);
3856 if (hsotg->driver) {
3857 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3858 hsotg->driver->driver.name);
3860 clk_enable(hsotg->clk);
3861 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3864 s3c_hsotg_phy_enable(hsotg);
3866 spin_lock_irqsave(&hsotg->lock, flags);
3867 s3c_hsotg_core_init_disconnected(hsotg);
3869 s3c_hsotg_core_connect(hsotg);
3870 spin_unlock_irqrestore(&hsotg->lock, flags);
3872 mutex_unlock(&hsotg->init_mutex);
3876 EXPORT_SYMBOL_GPL(s3c_hsotg_resume);