1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
189 trace_dwc3_gadget_giveback(req);
192 pm_runtime_put(dwc->dev);
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
208 struct dwc3 *dwc = dep->dwc;
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
212 spin_unlock(&dwc->lock);
213 usb_gadget_giveback_request(&dep->endpoint, &req->request);
214 spin_lock(&dwc->lock);
218 * dwc3_send_gadget_generic_command - issue a generic command for the controller
219 * @dwc: pointer to the controller context
220 * @cmd: the command to be issued
221 * @param: command parameter
223 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
224 * and wait for its completion.
226 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
233 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
234 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
237 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
238 if (!(reg & DWC3_DGCMD_CMDACT)) {
239 status = DWC3_DGCMD_STATUS(reg);
251 trace_dwc3_gadget_generic_cmd(cmd, param, status);
256 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
259 * dwc3_send_gadget_ep_cmd - issue an endpoint command
260 * @dep: the endpoint to which the command is going to be issued
261 * @cmd: the command to be issued
262 * @params: parameters to the command
264 * Caller should handle locking. This function will issue @cmd with given
265 * @params to @dep and wait for its completion.
267 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
268 struct dwc3_gadget_ep_cmd_params *params)
270 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
271 struct dwc3 *dwc = dep->dwc;
273 u32 saved_config = 0;
280 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
281 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
284 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
285 * settings. Restore them after the command is completed.
287 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
290 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
291 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
292 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
293 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
296 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
297 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
298 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
302 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
305 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
308 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
309 dwc->link_state == DWC3_LINK_STATE_U2 ||
310 dwc->link_state == DWC3_LINK_STATE_U3);
312 if (unlikely(needs_wakeup)) {
313 ret = __dwc3_gadget_wakeup(dwc);
314 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
319 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
324 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
325 * not relying on XferNotReady, we can make use of a special "No
326 * Response Update Transfer" command where we should clear both CmdAct
329 * With this, we don't need to wait for command completion and can
330 * straight away issue further commands to the endpoint.
332 * NOTICE: We're making an assumption that control endpoints will never
333 * make use of Update Transfer command. This is a safe assumption
334 * because we can never have more than one request at a time with
335 * Control Endpoints. If anybody changes that assumption, this chunk
336 * needs to be updated accordingly.
338 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
339 !usb_endpoint_xfer_isoc(desc))
340 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 cmd |= DWC3_DEPCMD_CMDACT;
344 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
347 if (!(reg & DWC3_DEPCMD_CMDACT)) {
348 cmd_status = DWC3_DEPCMD_STATUS(reg);
350 switch (cmd_status) {
354 case DEPEVT_TRANSFER_NO_RESOURCE:
357 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 * SW issues START TRANSFER command to
360 * isochronous ep with future frame interval. If
361 * future interval time has already passed when
362 * core receives the command, it will respond
363 * with an error status of 'Bus Expiry'.
365 * Instead of always returning -EINVAL, let's
366 * give a hint to the gadget driver that this is
367 * the case by returning -EAGAIN.
372 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
381 cmd_status = -ETIMEDOUT;
384 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
387 switch (DWC3_DEPCMD_CMD(cmd)) {
388 case DWC3_DEPCMD_STARTTRANSFER:
389 dep->flags |= DWC3_EP_TRANSFER_STARTED;
390 dwc3_gadget_ep_get_transfer_index(dep);
392 case DWC3_DEPCMD_ENDTRANSFER:
393 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
402 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
404 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
410 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
412 struct dwc3 *dwc = dep->dwc;
413 struct dwc3_gadget_ep_cmd_params params;
414 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
417 * As of core revision 2.60a the recommended programming model
418 * is to set the ClearPendIN bit when issuing a Clear Stall EP
419 * command for IN endpoints. This is to prevent an issue where
420 * some (non-compliant) hosts may not send ACK TPs for pending
421 * IN transfers due to a mishandled error condition. Synopsys
424 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
425 (dwc->gadget.speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
428 memset(¶ms, 0, sizeof(params));
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
438 return dep->trb_pool_dma + offset;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
443 struct dwc3 *dwc = dep->dwc;
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
475 memset(¶ms, 0x00, sizeof(params));
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
541 ret = dwc3_gadget_set_xfer_resource(dep);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
559 memset(¶ms, 0x00, sizeof(params));
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
567 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
570 params.param0 |= action;
571 if (action == DWC3_DEPCFG_ACTION_RESTORE)
572 params.param2 |= dep->saved_state;
574 if (usb_endpoint_xfer_control(desc))
575 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
577 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
580 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
581 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
582 | DWC3_DEPCFG_STREAM_EVENT_EN;
583 dep->stream_capable = true;
586 if (!usb_endpoint_xfer_control(desc))
587 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
590 * We are doing 1:1 mapping for endpoints, meaning
591 * Physical Endpoints 2 maps to Logical Endpoint 2 and
592 * so on. We consider the direction bit as part of the physical
593 * endpoint number. So USB endpoint 0x81 is 0x03.
595 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
598 * We must use the lower 16 TX FIFOs even though
602 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
604 if (desc->bInterval) {
605 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
606 dep->interval = 1 << (desc->bInterval - 1);
609 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
613 * __dwc3_gadget_ep_enable - initializes a hw endpoint
614 * @dep: endpoint to be initialized
615 * @action: one of INIT, MODIFY or RESTORE
617 * Caller should take care of locking. Execute all necessary commands to
618 * initialize a HW endpoint so it can be used by a gadget driver.
620 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
622 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
623 struct dwc3 *dwc = dep->dwc;
628 if (!(dep->flags & DWC3_EP_ENABLED)) {
629 ret = dwc3_gadget_start_config(dep);
634 ret = dwc3_gadget_set_ep_config(dep, action);
638 if (!(dep->flags & DWC3_EP_ENABLED)) {
639 struct dwc3_trb *trb_st_hw;
640 struct dwc3_trb *trb_link;
642 dep->type = usb_endpoint_type(desc);
643 dep->flags |= DWC3_EP_ENABLED;
644 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
646 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
647 reg |= DWC3_DALEPENA_EP(dep->number);
648 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
650 if (usb_endpoint_xfer_control(desc))
653 /* Initialize the TRB ring */
654 dep->trb_dequeue = 0;
655 dep->trb_enqueue = 0;
656 memset(dep->trb_pool, 0,
657 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
659 /* Link TRB. The HWO bit is never reset */
660 trb_st_hw = &dep->trb_pool[0];
662 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
663 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
664 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
665 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
666 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
670 * Issue StartTransfer here with no-op TRB so we can always rely on No
671 * Response Update Transfer command.
673 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
674 usb_endpoint_xfer_int(desc)) {
675 struct dwc3_gadget_ep_cmd_params params;
676 struct dwc3_trb *trb;
680 memset(¶ms, 0, sizeof(params));
681 trb = &dep->trb_pool[0];
682 trb_dma = dwc3_trb_dma_offset(dep, trb);
684 params.param0 = upper_32_bits(trb_dma);
685 params.param1 = lower_32_bits(trb_dma);
687 cmd = DWC3_DEPCMD_STARTTRANSFER;
689 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
695 trace_dwc3_gadget_ep_enable(dep);
700 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
701 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
703 struct dwc3_request *req;
705 dwc3_stop_active_transfer(dep, true);
707 /* - giveback all requests to gadget driver */
708 while (!list_empty(&dep->started_list)) {
709 req = next_request(&dep->started_list);
711 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
714 while (!list_empty(&dep->pending_list)) {
715 req = next_request(&dep->pending_list);
717 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
722 * __dwc3_gadget_ep_disable - disables a hw endpoint
723 * @dep: the endpoint to disable
725 * This function undoes what __dwc3_gadget_ep_enable did and also removes
726 * requests which are currently being processed by the hardware and those which
727 * are not yet scheduled.
729 * Caller should take care of locking.
731 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
733 struct dwc3 *dwc = dep->dwc;
736 trace_dwc3_gadget_ep_disable(dep);
738 dwc3_remove_requests(dwc, dep);
740 /* make sure HW endpoint isn't stalled */
741 if (dep->flags & DWC3_EP_STALL)
742 __dwc3_gadget_ep_set_halt(dep, 0, false);
744 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
745 reg &= ~DWC3_DALEPENA_EP(dep->number);
746 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
748 dep->stream_capable = false;
750 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
752 /* Clear out the ep descriptors for non-ep0 */
753 if (dep->number > 1) {
754 dep->endpoint.comp_desc = NULL;
755 dep->endpoint.desc = NULL;
761 /* -------------------------------------------------------------------------- */
763 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
764 const struct usb_endpoint_descriptor *desc)
769 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
774 /* -------------------------------------------------------------------------- */
776 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
777 const struct usb_endpoint_descriptor *desc)
784 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
785 pr_debug("dwc3: invalid parameters\n");
789 if (!desc->wMaxPacketSize) {
790 pr_debug("dwc3: missing wMaxPacketSize\n");
794 dep = to_dwc3_ep(ep);
797 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
798 "%s is already enabled\n",
802 spin_lock_irqsave(&dwc->lock, flags);
803 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
804 spin_unlock_irqrestore(&dwc->lock, flags);
809 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
817 pr_debug("dwc3: invalid parameters\n");
821 dep = to_dwc3_ep(ep);
824 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
825 "%s is already disabled\n",
829 spin_lock_irqsave(&dwc->lock, flags);
830 ret = __dwc3_gadget_ep_disable(dep);
831 spin_unlock_irqrestore(&dwc->lock, flags);
836 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
839 struct dwc3_request *req;
840 struct dwc3_ep *dep = to_dwc3_ep(ep);
842 req = kzalloc(sizeof(*req), gfp_flags);
846 req->direction = dep->direction;
847 req->epnum = dep->number;
850 trace_dwc3_alloc_request(req);
852 return &req->request;
855 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
856 struct usb_request *request)
858 struct dwc3_request *req = to_dwc3_request(request);
860 trace_dwc3_free_request(req);
865 * dwc3_ep_prev_trb - returns the previous TRB in the ring
866 * @dep: The endpoint with the TRB ring
867 * @index: The index of the current TRB in the ring
869 * Returns the TRB prior to the one pointed to by the index. If the
870 * index is 0, we will wrap backwards, skip the link TRB, and return
871 * the one just before that.
873 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
878 tmp = DWC3_TRB_NUM - 1;
880 return &dep->trb_pool[tmp - 1];
883 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
885 struct dwc3_trb *tmp;
889 * If enqueue & dequeue are equal than it is either full or empty.
891 * One way to know for sure is if the TRB right before us has HWO bit
892 * set or not. If it has, then we're definitely full and can't fit any
893 * more transfers in our ring.
895 if (dep->trb_enqueue == dep->trb_dequeue) {
896 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
897 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
900 return DWC3_TRB_NUM - 1;
903 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
904 trbs_left &= (DWC3_TRB_NUM - 1);
906 if (dep->trb_dequeue < dep->trb_enqueue)
912 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
913 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
914 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
916 struct dwc3 *dwc = dep->dwc;
917 struct usb_gadget *gadget = &dwc->gadget;
918 enum usb_device_speed speed = gadget->speed;
920 trb->size = DWC3_TRB_SIZE_LENGTH(length);
921 trb->bpl = lower_32_bits(dma);
922 trb->bph = upper_32_bits(dma);
924 switch (usb_endpoint_type(dep->endpoint.desc)) {
925 case USB_ENDPOINT_XFER_CONTROL:
926 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
929 case USB_ENDPOINT_XFER_ISOC:
931 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
934 * USB Specification 2.0 Section 5.9.2 states that: "If
935 * there is only a single transaction in the microframe,
936 * only a DATA0 data packet PID is used. If there are
937 * two transactions per microframe, DATA1 is used for
938 * the first transaction data packet and DATA0 is used
939 * for the second transaction data packet. If there are
940 * three transactions per microframe, DATA2 is used for
941 * the first transaction data packet, DATA1 is used for
942 * the second, and DATA0 is used for the third."
944 * IOW, we should satisfy the following cases:
946 * 1) length <= maxpacket
949 * 2) maxpacket < length <= (2 * maxpacket)
952 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
953 * - DATA2, DATA1, DATA0
955 if (speed == USB_SPEED_HIGH) {
956 struct usb_ep *ep = &dep->endpoint;
957 unsigned int mult = 2;
958 unsigned int maxp = usb_endpoint_maxp(ep->desc);
960 if (length <= (2 * maxp))
966 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
969 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
972 /* always enable Interrupt on Missed ISOC */
973 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
976 case USB_ENDPOINT_XFER_BULK:
977 case USB_ENDPOINT_XFER_INT:
978 trb->ctrl = DWC3_TRBCTL_NORMAL;
982 * This is only possible with faulty memory because we
983 * checked it already :)
985 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
986 usb_endpoint_type(dep->endpoint.desc));
990 * Enable Continue on Short Packet
991 * when endpoint is not a stream capable
993 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
994 if (!dep->stream_capable)
995 trb->ctrl |= DWC3_TRB_CTRL_CSP;
998 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1001 if ((!no_interrupt && !chain) ||
1002 (dwc3_calc_trbs_left(dep) == 1))
1003 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1006 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1008 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1009 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1011 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1013 dwc3_ep_inc_enq(dep);
1015 trace_dwc3_prepare_trb(dep, trb);
1019 * dwc3_prepare_one_trb - setup one TRB from one request
1020 * @dep: endpoint for which this request is prepared
1021 * @req: dwc3_request pointer
1022 * @chain: should this TRB be chained to the next?
1023 * @node: only for isochronous endpoints. First TRB needs different type.
1025 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1026 struct dwc3_request *req, unsigned chain, unsigned node)
1028 struct dwc3_trb *trb;
1029 unsigned int length;
1031 unsigned stream_id = req->request.stream_id;
1032 unsigned short_not_ok = req->request.short_not_ok;
1033 unsigned no_interrupt = req->request.no_interrupt;
1035 if (req->request.num_sgs > 0) {
1036 length = sg_dma_len(req->start_sg);
1037 dma = sg_dma_address(req->start_sg);
1039 length = req->request.length;
1040 dma = req->request.dma;
1043 trb = &dep->trb_pool[dep->trb_enqueue];
1046 dwc3_gadget_move_started_request(req);
1048 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1053 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1054 stream_id, short_not_ok, no_interrupt);
1057 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1058 struct dwc3_request *req)
1060 struct scatterlist *sg = req->start_sg;
1061 struct scatterlist *s;
1064 unsigned int remaining = req->request.num_mapped_sgs
1065 - req->num_queued_sgs;
1067 for_each_sg(sg, s, remaining, i) {
1068 unsigned int length = req->request.length;
1069 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1070 unsigned int rem = length % maxp;
1071 unsigned chain = true;
1076 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1077 struct dwc3 *dwc = dep->dwc;
1078 struct dwc3_trb *trb;
1080 req->needs_extra_trb = true;
1082 /* prepare normal TRB */
1083 dwc3_prepare_one_trb(dep, req, true, i);
1085 /* Now prepare one extra TRB to align transfer size */
1086 trb = &dep->trb_pool[dep->trb_enqueue];
1088 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1089 maxp - rem, false, 1,
1090 req->request.stream_id,
1091 req->request.short_not_ok,
1092 req->request.no_interrupt);
1094 dwc3_prepare_one_trb(dep, req, chain, i);
1098 * There can be a situation where all sgs in sglist are not
1099 * queued because of insufficient trb number. To handle this
1100 * case, update start_sg to next sg to be queued, so that
1101 * we have free trbs we can continue queuing from where we
1102 * previously stopped
1105 req->start_sg = sg_next(s);
1107 req->num_queued_sgs++;
1109 if (!dwc3_calc_trbs_left(dep))
1114 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1115 struct dwc3_request *req)
1117 unsigned int length = req->request.length;
1118 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1119 unsigned int rem = length % maxp;
1121 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1122 struct dwc3 *dwc = dep->dwc;
1123 struct dwc3_trb *trb;
1125 req->needs_extra_trb = true;
1127 /* prepare normal TRB */
1128 dwc3_prepare_one_trb(dep, req, true, 0);
1130 /* Now prepare one extra TRB to align transfer size */
1131 trb = &dep->trb_pool[dep->trb_enqueue];
1133 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1134 false, 1, req->request.stream_id,
1135 req->request.short_not_ok,
1136 req->request.no_interrupt);
1137 } else if (req->request.zero && req->request.length &&
1138 (IS_ALIGNED(req->request.length, maxp))) {
1139 struct dwc3 *dwc = dep->dwc;
1140 struct dwc3_trb *trb;
1142 req->needs_extra_trb = true;
1144 /* prepare normal TRB */
1145 dwc3_prepare_one_trb(dep, req, true, 0);
1147 /* Now prepare one extra TRB to handle ZLP */
1148 trb = &dep->trb_pool[dep->trb_enqueue];
1150 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1151 false, 1, req->request.stream_id,
1152 req->request.short_not_ok,
1153 req->request.no_interrupt);
1155 dwc3_prepare_one_trb(dep, req, false, 0);
1160 * dwc3_prepare_trbs - setup TRBs from requests
1161 * @dep: endpoint for which requests are being prepared
1163 * The function goes through the requests list and sets up TRBs for the
1164 * transfers. The function returns once there are no more TRBs available or
1165 * it runs out of requests.
1167 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1169 struct dwc3_request *req, *n;
1171 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1174 * We can get in a situation where there's a request in the started list
1175 * but there weren't enough TRBs to fully kick it in the first time
1176 * around, so it has been waiting for more TRBs to be freed up.
1178 * In that case, we should check if we have a request with pending_sgs
1179 * in the started list and prepare TRBs for that request first,
1180 * otherwise we will prepare TRBs completely out of order and that will
1183 list_for_each_entry(req, &dep->started_list, list) {
1184 if (req->num_pending_sgs > 0)
1185 dwc3_prepare_one_trb_sg(dep, req);
1187 if (!dwc3_calc_trbs_left(dep))
1191 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1192 struct dwc3 *dwc = dep->dwc;
1195 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1200 req->sg = req->request.sg;
1201 req->start_sg = req->sg;
1202 req->num_queued_sgs = 0;
1203 req->num_pending_sgs = req->request.num_mapped_sgs;
1205 if (req->num_pending_sgs > 0)
1206 dwc3_prepare_one_trb_sg(dep, req);
1208 dwc3_prepare_one_trb_linear(dep, req);
1210 if (!dwc3_calc_trbs_left(dep))
1215 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1217 struct dwc3_gadget_ep_cmd_params params;
1218 struct dwc3_request *req;
1223 if (!dwc3_calc_trbs_left(dep))
1226 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1228 dwc3_prepare_trbs(dep);
1229 req = next_request(&dep->started_list);
1231 dep->flags |= DWC3_EP_PENDING_REQUEST;
1235 memset(¶ms, 0, sizeof(params));
1238 params.param0 = upper_32_bits(req->trb_dma);
1239 params.param1 = lower_32_bits(req->trb_dma);
1240 cmd = DWC3_DEPCMD_STARTTRANSFER;
1242 if (dep->stream_capable)
1243 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1245 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1246 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1248 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1249 DWC3_DEPCMD_PARAM(dep->resource_index);
1252 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1255 * FIXME we need to iterate over the list of requests
1256 * here and stop, unmap, free and del each of the linked
1257 * requests instead of what we do now.
1260 memset(req->trb, 0, sizeof(struct dwc3_trb));
1261 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1268 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1272 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1273 return DWC3_DSTS_SOFFN(reg);
1277 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1278 * @dep: isoc endpoint
1280 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1281 * microframe number reported by the XferNotReady event for the future frame
1282 * number to start the isoc transfer.
1284 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1285 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1286 * XferNotReady event are invalid. The driver uses this number to schedule the
1287 * isochronous transfer and passes it to the START TRANSFER command. Because
1288 * this number is invalid, the command may fail. If BIT[15:14] matches the
1289 * internal 16-bit microframe, the START TRANSFER command will pass and the
1290 * transfer will start at the scheduled time, if it is off by 1, the command
1291 * will still pass, but the transfer will start 2 seconds in the future. For all
1292 * other conditions, the START TRANSFER command will fail with bus-expiry.
1294 * In order to workaround this issue, we can test for the correct combination of
1295 * BIT[15:14] by sending START TRANSFER commands with different values of
1296 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1297 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1298 * As the result, within the 4 possible combinations for BIT[15:14], there will
1299 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1300 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1301 * value is the correct combination.
1303 * Since there are only 4 outcomes and the results are ordered, we can simply
1304 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1305 * deduce the smaller successful combination.
1307 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1308 * of BIT[15:14]. The correct combination is as follow:
1310 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1311 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1312 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1313 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1315 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1318 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1324 while (dep->combo_num < 2) {
1325 struct dwc3_gadget_ep_cmd_params params;
1326 u32 test_frame_number;
1330 * Check if we can start isoc transfer on the next interval or
1331 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1333 test_frame_number = dep->frame_number & 0x3fff;
1334 test_frame_number |= dep->combo_num << 14;
1335 test_frame_number += max_t(u32, 4, dep->interval);
1337 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1338 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1340 cmd = DWC3_DEPCMD_STARTTRANSFER;
1341 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1342 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1344 /* Redo if some other failure beside bus-expiry is received */
1345 if (cmd_status && cmd_status != -EAGAIN) {
1346 dep->start_cmd_status = 0;
1351 /* Store the first test status */
1352 if (dep->combo_num == 0)
1353 dep->start_cmd_status = cmd_status;
1358 * End the transfer if the START_TRANSFER command is successful
1359 * to wait for the next XferNotReady to test the command again
1361 if (cmd_status == 0) {
1362 dwc3_stop_active_transfer(dep, true);
1367 /* test0 and test1 are both completed at this point */
1368 test0 = (dep->start_cmd_status == 0);
1369 test1 = (cmd_status == 0);
1371 if (!test0 && test1)
1373 else if (!test0 && !test1)
1375 else if (test0 && !test1)
1377 else if (test0 && test1)
1380 dep->frame_number &= 0x3fff;
1381 dep->frame_number |= dep->combo_num << 14;
1382 dep->frame_number += max_t(u32, 4, dep->interval);
1384 /* Reinitialize test variables */
1385 dep->start_cmd_status = 0;
1388 return __dwc3_gadget_kick_transfer(dep);
1391 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1393 struct dwc3 *dwc = dep->dwc;
1397 if (list_empty(&dep->pending_list)) {
1398 dep->flags |= DWC3_EP_PENDING_REQUEST;
1402 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1403 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1404 (dwc->revision == DWC3_USB31_REVISION_170A &&
1405 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1406 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1408 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1409 return dwc3_gadget_start_isoc_quirk(dep);
1412 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1413 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1415 ret = __dwc3_gadget_kick_transfer(dep);
1423 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1425 struct dwc3 *dwc = dep->dwc;
1427 if (!dep->endpoint.desc) {
1428 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1433 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1434 &req->request, req->dep->name))
1437 pm_runtime_get(dwc->dev);
1439 req->request.actual = 0;
1440 req->request.status = -EINPROGRESS;
1442 trace_dwc3_ep_queue(req);
1444 list_add_tail(&req->list, &dep->pending_list);
1447 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1448 * wait for a XferNotReady event so we will know what's the current
1449 * (micro-)frame number.
1451 * Without this trick, we are very, very likely gonna get Bus Expiry
1452 * errors which will force us issue EndTransfer command.
1454 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1455 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1456 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1459 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1460 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1461 return __dwc3_gadget_start_isoc(dep);
1466 return __dwc3_gadget_kick_transfer(dep);
1469 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1472 struct dwc3_request *req = to_dwc3_request(request);
1473 struct dwc3_ep *dep = to_dwc3_ep(ep);
1474 struct dwc3 *dwc = dep->dwc;
1476 unsigned long flags;
1480 spin_lock_irqsave(&dwc->lock, flags);
1481 ret = __dwc3_gadget_ep_queue(dep, req);
1482 spin_unlock_irqrestore(&dwc->lock, flags);
1487 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492 * If request was already started, this means we had to
1493 * stop the transfer. With that we also need to ignore
1494 * all TRBs used by the request, however TRBs can only
1495 * be modified after completion of END_TRANSFER
1496 * command. So what we do here is that we wait for
1497 * END_TRANSFER completion and only after that, we jump
1498 * over TRBs by clearing HWO and incrementing dequeue
1501 for (i = 0; i < req->num_trbs; i++) {
1502 struct dwc3_trb *trb;
1505 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1506 dwc3_ep_inc_deq(dep);
1510 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1512 struct dwc3_request *req;
1513 struct dwc3_request *tmp;
1515 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1516 dwc3_gadget_ep_skip_trbs(dep, req);
1517 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1521 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1522 struct usb_request *request)
1524 struct dwc3_request *req = to_dwc3_request(request);
1525 struct dwc3_request *r = NULL;
1527 struct dwc3_ep *dep = to_dwc3_ep(ep);
1528 struct dwc3 *dwc = dep->dwc;
1530 unsigned long flags;
1533 trace_dwc3_ep_dequeue(req);
1535 spin_lock_irqsave(&dwc->lock, flags);
1537 list_for_each_entry(r, &dep->pending_list, list) {
1543 list_for_each_entry(r, &dep->started_list, list) {
1548 /* wait until it is processed */
1549 dwc3_stop_active_transfer(dep, true);
1554 dwc3_gadget_move_cancelled_request(req);
1557 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1563 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1566 spin_unlock_irqrestore(&dwc->lock, flags);
1571 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1573 struct dwc3_gadget_ep_cmd_params params;
1574 struct dwc3 *dwc = dep->dwc;
1577 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1578 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1582 memset(¶ms, 0x00, sizeof(params));
1585 struct dwc3_trb *trb;
1587 unsigned transfer_in_flight;
1590 if (dep->number > 1)
1591 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1593 trb = &dwc->ep0_trb[dep->trb_enqueue];
1595 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1596 started = !list_empty(&dep->started_list);
1598 if (!protocol && ((dep->direction && transfer_in_flight) ||
1599 (!dep->direction && started))) {
1603 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1606 dev_err(dwc->dev, "failed to set STALL on %s\n",
1609 dep->flags |= DWC3_EP_STALL;
1612 ret = dwc3_send_clear_stall_ep_cmd(dep);
1614 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1617 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1623 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1625 struct dwc3_ep *dep = to_dwc3_ep(ep);
1626 struct dwc3 *dwc = dep->dwc;
1628 unsigned long flags;
1632 spin_lock_irqsave(&dwc->lock, flags);
1633 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1634 spin_unlock_irqrestore(&dwc->lock, flags);
1639 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1641 struct dwc3_ep *dep = to_dwc3_ep(ep);
1642 struct dwc3 *dwc = dep->dwc;
1643 unsigned long flags;
1646 spin_lock_irqsave(&dwc->lock, flags);
1647 dep->flags |= DWC3_EP_WEDGE;
1649 if (dep->number == 0 || dep->number == 1)
1650 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1652 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1653 spin_unlock_irqrestore(&dwc->lock, flags);
1658 /* -------------------------------------------------------------------------- */
1660 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1661 .bLength = USB_DT_ENDPOINT_SIZE,
1662 .bDescriptorType = USB_DT_ENDPOINT,
1663 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1666 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1667 .enable = dwc3_gadget_ep0_enable,
1668 .disable = dwc3_gadget_ep0_disable,
1669 .alloc_request = dwc3_gadget_ep_alloc_request,
1670 .free_request = dwc3_gadget_ep_free_request,
1671 .queue = dwc3_gadget_ep0_queue,
1672 .dequeue = dwc3_gadget_ep_dequeue,
1673 .set_halt = dwc3_gadget_ep0_set_halt,
1674 .set_wedge = dwc3_gadget_ep_set_wedge,
1677 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1678 .enable = dwc3_gadget_ep_enable,
1679 .disable = dwc3_gadget_ep_disable,
1680 .alloc_request = dwc3_gadget_ep_alloc_request,
1681 .free_request = dwc3_gadget_ep_free_request,
1682 .queue = dwc3_gadget_ep_queue,
1683 .dequeue = dwc3_gadget_ep_dequeue,
1684 .set_halt = dwc3_gadget_ep_set_halt,
1685 .set_wedge = dwc3_gadget_ep_set_wedge,
1688 /* -------------------------------------------------------------------------- */
1690 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1692 struct dwc3 *dwc = gadget_to_dwc(g);
1694 return __dwc3_gadget_get_frame(dwc);
1697 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708 * According to the Databook Remote wakeup request should
1709 * be issued only when the device is in early suspend state.
1711 * We can check that via USB Link State bits in DSTS register.
1713 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1715 speed = reg & DWC3_DSTS_CONNECTSPD;
1716 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1717 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1720 link_state = DWC3_DSTS_USBLNKST(reg);
1722 switch (link_state) {
1723 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1724 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1730 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1732 dev_err(dwc->dev, "failed to put link in Recovery\n");
1736 /* Recent versions do this automatically */
1737 if (dwc->revision < DWC3_REVISION_194A) {
1738 /* write zeroes to Link Change Request */
1739 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1740 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1741 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1744 /* poll until Link State changes to ON */
1748 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1750 /* in HS, means ON */
1751 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1755 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1756 dev_err(dwc->dev, "failed to send remote wakeup\n");
1763 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1765 struct dwc3 *dwc = gadget_to_dwc(g);
1766 unsigned long flags;
1769 spin_lock_irqsave(&dwc->lock, flags);
1770 ret = __dwc3_gadget_wakeup(dwc);
1771 spin_unlock_irqrestore(&dwc->lock, flags);
1776 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1779 struct dwc3 *dwc = gadget_to_dwc(g);
1780 unsigned long flags;
1782 spin_lock_irqsave(&dwc->lock, flags);
1783 g->is_selfpowered = !!is_selfpowered;
1784 spin_unlock_irqrestore(&dwc->lock, flags);
1789 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1794 if (pm_runtime_suspended(dwc->dev))
1797 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1799 if (dwc->revision <= DWC3_REVISION_187A) {
1800 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1801 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1804 if (dwc->revision >= DWC3_REVISION_194A)
1805 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1806 reg |= DWC3_DCTL_RUN_STOP;
1808 if (dwc->has_hibernation)
1809 reg |= DWC3_DCTL_KEEP_CONNECT;
1811 dwc->pullups_connected = true;
1813 reg &= ~DWC3_DCTL_RUN_STOP;
1815 if (dwc->has_hibernation && !suspend)
1816 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1818 dwc->pullups_connected = false;
1821 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1824 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1825 reg &= DWC3_DSTS_DEVCTRLHLT;
1826 } while (--timeout && !(!is_on ^ !reg));
1834 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1836 struct dwc3 *dwc = gadget_to_dwc(g);
1837 unsigned long flags;
1843 * Per databook, when we want to stop the gadget, if a control transfer
1844 * is still in process, complete it and get the core into setup phase.
1846 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1847 reinit_completion(&dwc->ep0_in_setup);
1849 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1850 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1852 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1857 spin_lock_irqsave(&dwc->lock, flags);
1858 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1859 spin_unlock_irqrestore(&dwc->lock, flags);
1864 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1868 /* Enable all but Start and End of Frame IRQs */
1869 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1870 DWC3_DEVTEN_EVNTOVERFLOWEN |
1871 DWC3_DEVTEN_CMDCMPLTEN |
1872 DWC3_DEVTEN_ERRTICERREN |
1873 DWC3_DEVTEN_WKUPEVTEN |
1874 DWC3_DEVTEN_CONNECTDONEEN |
1875 DWC3_DEVTEN_USBRSTEN |
1876 DWC3_DEVTEN_DISCONNEVTEN);
1878 if (dwc->revision < DWC3_REVISION_250A)
1879 reg |= DWC3_DEVTEN_ULSTCNGEN;
1881 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1884 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1886 /* mask all interrupts */
1887 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1890 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1891 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1894 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1895 * @dwc: pointer to our context structure
1897 * The following looks like complex but it's actually very simple. In order to
1898 * calculate the number of packets we can burst at once on OUT transfers, we're
1899 * gonna use RxFIFO size.
1901 * To calculate RxFIFO size we need two numbers:
1902 * MDWIDTH = size, in bits, of the internal memory bus
1903 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1905 * Given these two numbers, the formula is simple:
1907 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1909 * 24 bytes is for 3x SETUP packets
1910 * 16 bytes is a clock domain crossing tolerance
1912 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1914 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1921 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1922 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1924 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1925 nump = min_t(u32, nump, 16);
1928 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1929 reg &= ~DWC3_DCFG_NUMP_MASK;
1930 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1931 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1934 static int __dwc3_gadget_start(struct dwc3 *dwc)
1936 struct dwc3_ep *dep;
1941 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1942 * the core supports IMOD, disable it.
1944 if (dwc->imod_interval) {
1945 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1946 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1947 } else if (dwc3_has_imod(dwc)) {
1948 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1952 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1953 * field instead of letting dwc3 itself calculate that automatically.
1955 * This way, we maximize the chances that we'll be able to get several
1956 * bursts of data without going through any sort of endpoint throttling.
1958 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1959 if (dwc3_is_usb31(dwc))
1960 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1962 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1964 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1966 dwc3_gadget_setup_nump(dwc);
1968 /* Start with SuperSpeed Default */
1969 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1972 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1974 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1979 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1981 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 /* begin to receive SETUP packets */
1986 dwc->ep0state = EP0_SETUP_PHASE;
1987 dwc3_ep0_out_start(dwc);
1989 dwc3_gadget_enable_irq(dwc);
1994 __dwc3_gadget_ep_disable(dwc->eps[0]);
2000 static int dwc3_gadget_start(struct usb_gadget *g,
2001 struct usb_gadget_driver *driver)
2003 struct dwc3 *dwc = gadget_to_dwc(g);
2004 unsigned long flags;
2008 irq = dwc->irq_gadget;
2009 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2010 IRQF_SHARED, "dwc3", dwc->ev_buf);
2012 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2017 spin_lock_irqsave(&dwc->lock, flags);
2018 if (dwc->gadget_driver) {
2019 dev_err(dwc->dev, "%s is already bound to %s\n",
2021 dwc->gadget_driver->driver.name);
2026 dwc->gadget_driver = driver;
2028 if (pm_runtime_active(dwc->dev))
2029 __dwc3_gadget_start(dwc);
2031 spin_unlock_irqrestore(&dwc->lock, flags);
2036 spin_unlock_irqrestore(&dwc->lock, flags);
2043 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2045 dwc3_gadget_disable_irq(dwc);
2046 __dwc3_gadget_ep_disable(dwc->eps[0]);
2047 __dwc3_gadget_ep_disable(dwc->eps[1]);
2050 static int dwc3_gadget_stop(struct usb_gadget *g)
2052 struct dwc3 *dwc = gadget_to_dwc(g);
2053 unsigned long flags;
2055 spin_lock_irqsave(&dwc->lock, flags);
2057 if (pm_runtime_suspended(dwc->dev))
2060 __dwc3_gadget_stop(dwc);
2063 dwc->gadget_driver = NULL;
2064 spin_unlock_irqrestore(&dwc->lock, flags);
2066 free_irq(dwc->irq_gadget, dwc->ev_buf);
2071 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2072 enum usb_device_speed speed)
2074 struct dwc3 *dwc = gadget_to_dwc(g);
2075 unsigned long flags;
2078 spin_lock_irqsave(&dwc->lock, flags);
2079 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2080 reg &= ~(DWC3_DCFG_SPEED_MASK);
2083 * WORKAROUND: DWC3 revision < 2.20a have an issue
2084 * which would cause metastability state on Run/Stop
2085 * bit if we try to force the IP to USB2-only mode.
2087 * Because of that, we cannot configure the IP to any
2088 * speed other than the SuperSpeed
2092 * STAR#9000525659: Clock Domain Crossing on DCTL in
2095 if (dwc->revision < DWC3_REVISION_220A &&
2096 !dwc->dis_metastability_quirk) {
2097 reg |= DWC3_DCFG_SUPERSPEED;
2101 reg |= DWC3_DCFG_LOWSPEED;
2103 case USB_SPEED_FULL:
2104 reg |= DWC3_DCFG_FULLSPEED;
2106 case USB_SPEED_HIGH:
2107 reg |= DWC3_DCFG_HIGHSPEED;
2109 case USB_SPEED_SUPER:
2110 reg |= DWC3_DCFG_SUPERSPEED;
2112 case USB_SPEED_SUPER_PLUS:
2113 if (dwc3_is_usb31(dwc))
2114 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2116 reg |= DWC3_DCFG_SUPERSPEED;
2119 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2121 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2122 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2124 reg |= DWC3_DCFG_SUPERSPEED;
2127 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2129 spin_unlock_irqrestore(&dwc->lock, flags);
2132 static const struct usb_gadget_ops dwc3_gadget_ops = {
2133 .get_frame = dwc3_gadget_get_frame,
2134 .wakeup = dwc3_gadget_wakeup,
2135 .set_selfpowered = dwc3_gadget_set_selfpowered,
2136 .pullup = dwc3_gadget_pullup,
2137 .udc_start = dwc3_gadget_start,
2138 .udc_stop = dwc3_gadget_stop,
2139 .udc_set_speed = dwc3_gadget_set_speed,
2142 /* -------------------------------------------------------------------------- */
2144 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2146 struct dwc3 *dwc = dep->dwc;
2148 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2149 dep->endpoint.maxburst = 1;
2150 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2151 if (!dep->direction)
2152 dwc->gadget.ep0 = &dep->endpoint;
2154 dep->endpoint.caps.type_control = true;
2159 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2161 struct dwc3 *dwc = dep->dwc;
2166 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2167 /* MDWIDTH is represented in bits, we need it in bytes */
2170 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2171 if (dwc3_is_usb31(dwc))
2172 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2174 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2176 /* FIFO Depth is in MDWDITH bytes. Multiply */
2179 kbytes = size / 1024;
2184 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2185 * internal overhead. We don't really know how these are used,
2186 * but documentation say it exists.
2188 size -= mdwidth * (kbytes + 1);
2191 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2193 dep->endpoint.max_streams = 15;
2194 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2195 list_add_tail(&dep->endpoint.ep_list,
2196 &dwc->gadget.ep_list);
2197 dep->endpoint.caps.type_iso = true;
2198 dep->endpoint.caps.type_bulk = true;
2199 dep->endpoint.caps.type_int = true;
2201 return dwc3_alloc_trb_pool(dep);
2204 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2206 struct dwc3 *dwc = dep->dwc;
2208 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2209 dep->endpoint.max_streams = 15;
2210 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2211 list_add_tail(&dep->endpoint.ep_list,
2212 &dwc->gadget.ep_list);
2213 dep->endpoint.caps.type_iso = true;
2214 dep->endpoint.caps.type_bulk = true;
2215 dep->endpoint.caps.type_int = true;
2217 return dwc3_alloc_trb_pool(dep);
2220 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2222 struct dwc3_ep *dep;
2223 bool direction = epnum & 1;
2225 u8 num = epnum >> 1;
2227 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2232 dep->number = epnum;
2233 dep->direction = direction;
2234 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2235 dwc->eps[epnum] = dep;
2237 dep->start_cmd_status = 0;
2239 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2240 direction ? "in" : "out");
2242 dep->endpoint.name = dep->name;
2244 if (!(dep->number > 1)) {
2245 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2246 dep->endpoint.comp_desc = NULL;
2249 spin_lock_init(&dep->lock);
2252 ret = dwc3_gadget_init_control_endpoint(dep);
2254 ret = dwc3_gadget_init_in_endpoint(dep);
2256 ret = dwc3_gadget_init_out_endpoint(dep);
2261 dep->endpoint.caps.dir_in = direction;
2262 dep->endpoint.caps.dir_out = !direction;
2264 INIT_LIST_HEAD(&dep->pending_list);
2265 INIT_LIST_HEAD(&dep->started_list);
2266 INIT_LIST_HEAD(&dep->cancelled_list);
2271 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2275 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2277 for (epnum = 0; epnum < total; epnum++) {
2280 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2288 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2290 struct dwc3_ep *dep;
2293 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2294 dep = dwc->eps[epnum];
2298 * Physical endpoints 0 and 1 are special; they form the
2299 * bi-directional USB endpoint 0.
2301 * For those two physical endpoints, we don't allocate a TRB
2302 * pool nor do we add them the endpoints list. Due to that, we
2303 * shouldn't do these two operations otherwise we would end up
2304 * with all sorts of bugs when removing dwc3.ko.
2306 if (epnum != 0 && epnum != 1) {
2307 dwc3_free_trb_pool(dep);
2308 list_del(&dep->endpoint.ep_list);
2315 /* -------------------------------------------------------------------------- */
2317 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2318 struct dwc3_request *req, struct dwc3_trb *trb,
2319 const struct dwc3_event_depevt *event, int status, int chain)
2323 dwc3_ep_inc_deq(dep);
2325 trace_dwc3_complete_trb(dep, trb);
2329 * If we're in the middle of series of chained TRBs and we
2330 * receive a short transfer along the way, DWC3 will skip
2331 * through all TRBs including the last TRB in the chain (the
2332 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2333 * bit and SW has to do it manually.
2335 * We're going to do that here to avoid problems of HW trying
2336 * to use bogus TRBs for transfers.
2338 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2339 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2342 * For isochronous transfers, the first TRB in a service interval must
2343 * have the Isoc-First type. Track and report its interval frame number.
2345 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2346 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2347 unsigned int frame_number;
2349 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2350 frame_number &= ~(dep->interval - 1);
2351 req->request.frame_number = frame_number;
2355 * If we're dealing with unaligned size OUT transfer, we will be left
2356 * with one TRB pending in the ring. We need to manually clear HWO bit
2360 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2361 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2365 count = trb->size & DWC3_TRB_SIZE_MASK;
2366 req->remaining += count;
2368 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2371 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2374 if (event->status & DEPEVT_STATUS_IOC)
2380 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2381 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2384 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2385 struct scatterlist *sg = req->sg;
2386 struct scatterlist *s;
2387 unsigned int pending = req->num_pending_sgs;
2391 for_each_sg(sg, s, pending, i) {
2392 trb = &dep->trb_pool[dep->trb_dequeue];
2394 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2397 req->sg = sg_next(s);
2398 req->num_pending_sgs--;
2400 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2401 trb, event, status, true);
2409 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2410 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2413 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2415 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2416 event, status, false);
2419 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2421 return req->request.actual == req->request.length;
2424 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2425 const struct dwc3_event_depevt *event,
2426 struct dwc3_request *req, int status)
2430 if (req->num_pending_sgs)
2431 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2434 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2437 if (req->needs_extra_trb) {
2438 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2440 req->needs_extra_trb = false;
2443 req->request.actual = req->request.length - req->remaining;
2445 if (!dwc3_gadget_ep_request_completed(req) &&
2446 req->num_pending_sgs) {
2447 __dwc3_gadget_kick_transfer(dep);
2451 dwc3_gadget_giveback(dep, req, status);
2457 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2458 const struct dwc3_event_depevt *event, int status)
2460 struct dwc3_request *req;
2461 struct dwc3_request *tmp;
2463 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2466 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2473 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event)
2476 dep->frame_number = event->parameters;
2479 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2480 const struct dwc3_event_depevt *event)
2482 struct dwc3 *dwc = dep->dwc;
2483 unsigned status = 0;
2486 dwc3_gadget_endpoint_frame_from_event(dep, event);
2488 if (event->status & DEPEVT_STATUS_BUSERR)
2489 status = -ECONNRESET;
2491 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2494 if (list_empty(&dep->started_list))
2498 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2501 dwc3_stop_active_transfer(dep, true);
2502 dep->flags = DWC3_EP_ENABLED;
2506 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2507 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2509 if (dwc->revision < DWC3_REVISION_183A) {
2513 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2516 if (!(dep->flags & DWC3_EP_ENABLED))
2519 if (!list_empty(&dep->started_list))
2523 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2525 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2531 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2532 const struct dwc3_event_depevt *event)
2534 dwc3_gadget_endpoint_frame_from_event(dep, event);
2535 (void) __dwc3_gadget_start_isoc(dep);
2538 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2539 const struct dwc3_event_depevt *event)
2541 struct dwc3_ep *dep;
2542 u8 epnum = event->endpoint_number;
2545 dep = dwc->eps[epnum];
2547 if (!(dep->flags & DWC3_EP_ENABLED)) {
2548 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2551 /* Handle only EPCMDCMPLT when EP disabled */
2552 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2556 if (epnum == 0 || epnum == 1) {
2557 dwc3_ep0_interrupt(dwc, event);
2561 switch (event->endpoint_event) {
2562 case DWC3_DEPEVT_XFERINPROGRESS:
2563 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2565 case DWC3_DEPEVT_XFERNOTREADY:
2566 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2568 case DWC3_DEPEVT_EPCMDCMPLT:
2569 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2571 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2572 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2573 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2576 case DWC3_DEPEVT_STREAMEVT:
2577 case DWC3_DEPEVT_XFERCOMPLETE:
2578 case DWC3_DEPEVT_RXTXFIFOEVT:
2583 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2585 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2586 spin_unlock(&dwc->lock);
2587 dwc->gadget_driver->disconnect(&dwc->gadget);
2588 spin_lock(&dwc->lock);
2592 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2594 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2595 spin_unlock(&dwc->lock);
2596 dwc->gadget_driver->suspend(&dwc->gadget);
2597 spin_lock(&dwc->lock);
2601 static void dwc3_resume_gadget(struct dwc3 *dwc)
2603 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2604 spin_unlock(&dwc->lock);
2605 dwc->gadget_driver->resume(&dwc->gadget);
2606 spin_lock(&dwc->lock);
2610 static void dwc3_reset_gadget(struct dwc3 *dwc)
2612 if (!dwc->gadget_driver)
2615 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2616 spin_unlock(&dwc->lock);
2617 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2618 spin_lock(&dwc->lock);
2622 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2624 struct dwc3 *dwc = dep->dwc;
2625 struct dwc3_gadget_ep_cmd_params params;
2629 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2630 !dep->resource_index)
2634 * NOTICE: We are violating what the Databook says about the
2635 * EndTransfer command. Ideally we would _always_ wait for the
2636 * EndTransfer Command Completion IRQ, but that's causing too
2637 * much trouble synchronizing between us and gadget driver.
2639 * We have discussed this with the IP Provider and it was
2640 * suggested to giveback all requests here, but give HW some
2641 * extra time to synchronize with the interconnect. We're using
2642 * an arbitrary 100us delay for that.
2644 * Note also that a similar handling was tested by Synopsys
2645 * (thanks a lot Paul) and nothing bad has come out of it.
2646 * In short, what we're doing is:
2648 * - Issue EndTransfer WITH CMDIOC bit set
2651 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2652 * supports a mode to work around the above limitation. The
2653 * software can poll the CMDACT bit in the DEPCMD register
2654 * after issuing a EndTransfer command. This mode is enabled
2655 * by writing GUCTL2[14]. This polling is already done in the
2656 * dwc3_send_gadget_ep_cmd() function so if the mode is
2657 * enabled, the EndTransfer command will have completed upon
2658 * returning from this function and we don't need to delay for
2661 * This mode is NOT available on the DWC_usb31 IP.
2664 cmd = DWC3_DEPCMD_ENDTRANSFER;
2665 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2666 cmd |= DWC3_DEPCMD_CMDIOC;
2667 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2668 memset(¶ms, 0, sizeof(params));
2669 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2671 dep->resource_index = 0;
2673 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2674 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2679 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2683 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2684 struct dwc3_ep *dep;
2687 dep = dwc->eps[epnum];
2691 if (!(dep->flags & DWC3_EP_STALL))
2694 dep->flags &= ~DWC3_EP_STALL;
2696 ret = dwc3_send_clear_stall_ep_cmd(dep);
2701 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2705 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2706 reg &= ~DWC3_DCTL_INITU1ENA;
2707 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2709 reg &= ~DWC3_DCTL_INITU2ENA;
2710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2712 dwc3_disconnect_gadget(dwc);
2714 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2715 dwc->setup_packet_pending = false;
2716 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2718 dwc->connected = false;
2721 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2725 dwc->connected = true;
2728 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2729 * would cause a missing Disconnect Event if there's a
2730 * pending Setup Packet in the FIFO.
2732 * There's no suggested workaround on the official Bug
2733 * report, which states that "unless the driver/application
2734 * is doing any special handling of a disconnect event,
2735 * there is no functional issue".
2737 * Unfortunately, it turns out that we _do_ some special
2738 * handling of a disconnect event, namely complete all
2739 * pending transfers, notify gadget driver of the
2740 * disconnection, and so on.
2742 * Our suggested workaround is to follow the Disconnect
2743 * Event steps here, instead, based on a setup_packet_pending
2744 * flag. Such flag gets set whenever we have a SETUP_PENDING
2745 * status for EP0 TRBs and gets cleared on XferComplete for the
2750 * STAR#9000466709: RTL: Device : Disconnect event not
2751 * generated if setup packet pending in FIFO
2753 if (dwc->revision < DWC3_REVISION_188A) {
2754 if (dwc->setup_packet_pending)
2755 dwc3_gadget_disconnect_interrupt(dwc);
2758 dwc3_reset_gadget(dwc);
2760 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2761 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2762 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2763 dwc->test_mode = false;
2764 dwc3_clear_stall_all_ep(dwc);
2766 /* Reset device address to zero */
2767 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2768 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2769 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2772 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2774 struct dwc3_ep *dep;
2779 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2780 speed = reg & DWC3_DSTS_CONNECTSPD;
2784 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2785 * each time on Connect Done.
2787 * Currently we always use the reset value. If any platform
2788 * wants to set this to a different value, we need to add a
2789 * setting and update GCTL.RAMCLKSEL here.
2793 case DWC3_DSTS_SUPERSPEED_PLUS:
2794 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2795 dwc->gadget.ep0->maxpacket = 512;
2796 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2798 case DWC3_DSTS_SUPERSPEED:
2800 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2801 * would cause a missing USB3 Reset event.
2803 * In such situations, we should force a USB3 Reset
2804 * event by calling our dwc3_gadget_reset_interrupt()
2809 * STAR#9000483510: RTL: SS : USB3 reset event may
2810 * not be generated always when the link enters poll
2812 if (dwc->revision < DWC3_REVISION_190A)
2813 dwc3_gadget_reset_interrupt(dwc);
2815 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2816 dwc->gadget.ep0->maxpacket = 512;
2817 dwc->gadget.speed = USB_SPEED_SUPER;
2819 case DWC3_DSTS_HIGHSPEED:
2820 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2821 dwc->gadget.ep0->maxpacket = 64;
2822 dwc->gadget.speed = USB_SPEED_HIGH;
2824 case DWC3_DSTS_FULLSPEED:
2825 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2826 dwc->gadget.ep0->maxpacket = 64;
2827 dwc->gadget.speed = USB_SPEED_FULL;
2829 case DWC3_DSTS_LOWSPEED:
2830 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2831 dwc->gadget.ep0->maxpacket = 8;
2832 dwc->gadget.speed = USB_SPEED_LOW;
2836 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2838 /* Enable USB2 LPM Capability */
2840 if ((dwc->revision > DWC3_REVISION_194A) &&
2841 (speed != DWC3_DSTS_SUPERSPEED) &&
2842 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2843 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2844 reg |= DWC3_DCFG_LPM_CAP;
2845 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2847 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2848 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2850 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2853 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2854 * DCFG.LPMCap is set, core responses with an ACK and the
2855 * BESL value in the LPM token is less than or equal to LPM
2858 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2859 && dwc->has_lpm_erratum,
2860 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2862 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2863 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2865 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2867 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2868 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2869 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2873 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2875 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2880 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2882 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2887 * Configure PHY via GUSB3PIPECTLn if required.
2889 * Update GTXFIFOSIZn
2891 * In both cases reset values should be sufficient.
2895 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2898 * TODO take core out of low power mode when that's
2902 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2903 spin_unlock(&dwc->lock);
2904 dwc->gadget_driver->resume(&dwc->gadget);
2905 spin_lock(&dwc->lock);
2909 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2910 unsigned int evtinfo)
2912 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2913 unsigned int pwropt;
2916 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2917 * Hibernation mode enabled which would show up when device detects
2918 * host-initiated U3 exit.
2920 * In that case, device will generate a Link State Change Interrupt
2921 * from U3 to RESUME which is only necessary if Hibernation is
2924 * There are no functional changes due to such spurious event and we
2925 * just need to ignore it.
2929 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2932 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2933 if ((dwc->revision < DWC3_REVISION_250A) &&
2934 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2935 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2936 (next == DWC3_LINK_STATE_RESUME)) {
2942 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2943 * on the link partner, the USB session might do multiple entry/exit
2944 * of low power states before a transfer takes place.
2946 * Due to this problem, we might experience lower throughput. The
2947 * suggested workaround is to disable DCTL[12:9] bits if we're
2948 * transitioning from U1/U2 to U0 and enable those bits again
2949 * after a transfer completes and there are no pending transfers
2950 * on any of the enabled endpoints.
2952 * This is the first half of that workaround.
2956 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2957 * core send LGO_Ux entering U0
2959 if (dwc->revision < DWC3_REVISION_183A) {
2960 if (next == DWC3_LINK_STATE_U0) {
2964 switch (dwc->link_state) {
2965 case DWC3_LINK_STATE_U1:
2966 case DWC3_LINK_STATE_U2:
2967 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2968 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2969 | DWC3_DCTL_ACCEPTU2ENA
2970 | DWC3_DCTL_INITU1ENA
2971 | DWC3_DCTL_ACCEPTU1ENA);
2974 dwc->u1u2 = reg & u1u2;
2978 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2988 case DWC3_LINK_STATE_U1:
2989 if (dwc->speed == USB_SPEED_SUPER)
2990 dwc3_suspend_gadget(dwc);
2992 case DWC3_LINK_STATE_U2:
2993 case DWC3_LINK_STATE_U3:
2994 dwc3_suspend_gadget(dwc);
2996 case DWC3_LINK_STATE_RESUME:
2997 dwc3_resume_gadget(dwc);
3004 dwc->link_state = next;
3007 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3008 unsigned int evtinfo)
3010 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3012 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3013 dwc3_suspend_gadget(dwc);
3015 dwc->link_state = next;
3018 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3019 unsigned int evtinfo)
3021 unsigned int is_ss = evtinfo & BIT(4);
3024 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3025 * have a known issue which can cause USB CV TD.9.23 to fail
3028 * Because of this issue, core could generate bogus hibernation
3029 * events which SW needs to ignore.
3033 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3034 * Device Fallback from SuperSpeed
3036 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3039 /* enter hibernation here */
3042 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3043 const struct dwc3_event_devt *event)
3045 switch (event->type) {
3046 case DWC3_DEVICE_EVENT_DISCONNECT:
3047 dwc3_gadget_disconnect_interrupt(dwc);
3049 case DWC3_DEVICE_EVENT_RESET:
3050 dwc3_gadget_reset_interrupt(dwc);
3052 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3053 dwc3_gadget_conndone_interrupt(dwc);
3055 case DWC3_DEVICE_EVENT_WAKEUP:
3056 dwc3_gadget_wakeup_interrupt(dwc);
3058 case DWC3_DEVICE_EVENT_HIBER_REQ:
3059 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3060 "unexpected hibernation event\n"))
3063 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3065 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3066 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3068 case DWC3_DEVICE_EVENT_EOPF:
3069 /* It changed to be suspend event for version 2.30a and above */
3070 if (dwc->revision >= DWC3_REVISION_230A) {
3072 * Ignore suspend event until the gadget enters into
3073 * USB_STATE_CONFIGURED state.
3075 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3076 dwc3_gadget_suspend_interrupt(dwc,
3080 case DWC3_DEVICE_EVENT_SOF:
3081 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3082 case DWC3_DEVICE_EVENT_CMD_CMPL:
3083 case DWC3_DEVICE_EVENT_OVERFLOW:
3086 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3090 static void dwc3_process_event_entry(struct dwc3 *dwc,
3091 const union dwc3_event *event)
3093 trace_dwc3_event(event->raw, dwc);
3095 if (!event->type.is_devspec)
3096 dwc3_endpoint_interrupt(dwc, &event->depevt);
3097 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3098 dwc3_gadget_interrupt(dwc, &event->devt);
3100 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3103 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3105 struct dwc3 *dwc = evt->dwc;
3106 irqreturn_t ret = IRQ_NONE;
3112 if (!(evt->flags & DWC3_EVENT_PENDING))
3116 union dwc3_event event;
3118 event.raw = *(u32 *) (evt->cache + evt->lpos);
3120 dwc3_process_event_entry(dwc, &event);
3123 * FIXME we wrap around correctly to the next entry as
3124 * almost all entries are 4 bytes in size. There is one
3125 * entry which has 12 bytes which is a regular entry
3126 * followed by 8 bytes data. ATM I don't know how
3127 * things are organized if we get next to the a
3128 * boundary so I worry about that once we try to handle
3131 evt->lpos = (evt->lpos + 4) % evt->length;
3136 evt->flags &= ~DWC3_EVENT_PENDING;
3139 /* Unmask interrupt */
3140 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3141 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3142 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3144 if (dwc->imod_interval) {
3145 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3146 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3152 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3154 struct dwc3_event_buffer *evt = _evt;
3155 struct dwc3 *dwc = evt->dwc;
3156 unsigned long flags;
3157 irqreturn_t ret = IRQ_NONE;
3159 spin_lock_irqsave(&dwc->lock, flags);
3160 ret = dwc3_process_event_buf(evt);
3161 spin_unlock_irqrestore(&dwc->lock, flags);
3166 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3168 struct dwc3 *dwc = evt->dwc;
3173 if (pm_runtime_suspended(dwc->dev)) {
3174 pm_runtime_get(dwc->dev);
3175 disable_irq_nosync(dwc->irq_gadget);
3176 dwc->pending_events = true;
3181 * With PCIe legacy interrupt, test shows that top-half irq handler can
3182 * be called again after HW interrupt deassertion. Check if bottom-half
3183 * irq event handler completes before caching new event to prevent
3186 if (evt->flags & DWC3_EVENT_PENDING)
3189 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3190 count &= DWC3_GEVNTCOUNT_MASK;
3195 evt->flags |= DWC3_EVENT_PENDING;
3197 /* Mask interrupt */
3198 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3199 reg |= DWC3_GEVNTSIZ_INTMASK;
3200 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3202 amount = min(count, evt->length - evt->lpos);
3203 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3206 memcpy(evt->cache, evt->buf, count - amount);
3208 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3210 return IRQ_WAKE_THREAD;
3213 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3215 struct dwc3_event_buffer *evt = _evt;
3217 return dwc3_check_event_buf(evt);
3220 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3222 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3225 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3229 if (irq == -EPROBE_DEFER)
3232 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3236 if (irq == -EPROBE_DEFER)
3239 irq = platform_get_irq(dwc3_pdev, 0);
3243 if (irq != -EPROBE_DEFER)
3244 dev_err(dwc->dev, "missing peripheral IRQ\n");
3254 * dwc3_gadget_init - initializes gadget related registers
3255 * @dwc: pointer to our controller context structure
3257 * Returns 0 on success otherwise negative errno.
3259 int dwc3_gadget_init(struct dwc3 *dwc)
3264 irq = dwc3_gadget_get_irq(dwc);
3270 dwc->irq_gadget = irq;
3272 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3273 sizeof(*dwc->ep0_trb) * 2,
3274 &dwc->ep0_trb_addr, GFP_KERNEL);
3275 if (!dwc->ep0_trb) {
3276 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3281 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3282 if (!dwc->setup_buf) {
3287 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3288 &dwc->bounce_addr, GFP_KERNEL);
3294 init_completion(&dwc->ep0_in_setup);
3296 dwc->gadget.ops = &dwc3_gadget_ops;
3297 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3298 dwc->gadget.sg_supported = true;
3299 dwc->gadget.name = "dwc3-gadget";
3300 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3303 * FIXME We might be setting max_speed to <SUPER, however versions
3304 * <2.20a of dwc3 have an issue with metastability (documented
3305 * elsewhere in this driver) which tells us we can't set max speed to
3306 * anything lower than SUPER.
3308 * Because gadget.max_speed is only used by composite.c and function
3309 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3310 * to happen so we avoid sending SuperSpeed Capability descriptor
3311 * together with our BOS descriptor as that could confuse host into
3312 * thinking we can handle super speed.
3314 * Note that, in fact, we won't even support GetBOS requests when speed
3315 * is less than super speed because we don't have means, yet, to tell
3316 * composite.c that we are USB 2.0 + LPM ECN.
3318 if (dwc->revision < DWC3_REVISION_220A &&
3319 !dwc->dis_metastability_quirk)
3320 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3323 dwc->gadget.max_speed = dwc->maximum_speed;
3326 * REVISIT: Here we should clear all pending IRQs to be
3327 * sure we're starting from a well known location.
3330 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3334 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3336 dev_err(dwc->dev, "failed to register udc\n");
3343 dwc3_gadget_free_endpoints(dwc);
3346 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3350 kfree(dwc->setup_buf);
3353 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3354 dwc->ep0_trb, dwc->ep0_trb_addr);
3360 /* -------------------------------------------------------------------------- */
3362 void dwc3_gadget_exit(struct dwc3 *dwc)
3364 usb_del_gadget_udc(&dwc->gadget);
3365 dwc3_gadget_free_endpoints(dwc);
3366 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3368 kfree(dwc->setup_buf);
3369 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3370 dwc->ep0_trb, dwc->ep0_trb_addr);
3373 int dwc3_gadget_suspend(struct dwc3 *dwc)
3375 if (!dwc->gadget_driver)
3378 dwc3_gadget_run_stop(dwc, false, false);
3379 dwc3_disconnect_gadget(dwc);
3380 __dwc3_gadget_stop(dwc);
3385 int dwc3_gadget_resume(struct dwc3 *dwc)
3389 if (!dwc->gadget_driver)
3392 ret = __dwc3_gadget_start(dwc);
3396 ret = dwc3_gadget_run_stop(dwc, true, false);
3403 __dwc3_gadget_stop(dwc);
3409 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3411 if (dwc->pending_events) {
3412 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3413 dwc->pending_events = false;
3414 enable_irq(dwc->irq_gadget);