drivers/usb/host/ehci-sched.c

   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 #ifdef CONFIG_PCI
  40
  41 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
  42 {
  43         unsigned uf;
  44
  45         /*
  46          * The MosChip MCS9990 controller updates its microframe counter
  47          * a little before the frame counter, and occasionally we will read
  48          * the invalid intermediate value.  Avoid problems by checking the
  49          * microframe number (the low-order 3 bits); if they are 0 then
  50          * re-read the register to get the correct value.
  51          */
  52         uf = ehci_readl(ehci, &ehci->regs->frame_index);
  53         if (unlikely(ehci->frame_index_bug && ((uf & 7) == 0)))
  54                 uf = ehci_readl(ehci, &ehci->regs->frame_index);
  55         return uf;
  56 }
  57
  58 #endif
  59
  60 /*-------------------------------------------------------------------------*/
  61
  62 /*
  63  * periodic_next_shadow - return "next" pointer on shadow list
  64  * @periodic: host pointer to qh/itd/sitd
  65  * @tag: hardware tag for type of this record
  66  */
  67 static union ehci_shadow *
  68 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  69                 __hc32 tag)
  70 {
  71         switch (hc32_to_cpu(ehci, tag)) {
  72         case Q_TYPE_QH:
  73                 return &periodic->qh->qh_next;
  74         case Q_TYPE_FSTN:
  75                 return &periodic->fstn->fstn_next;
  76         case Q_TYPE_ITD:
  77                 return &periodic->itd->itd_next;
  78         // case Q_TYPE_SITD:
  79         default:
  80                 return &periodic->sitd->sitd_next;
  81         }
  82 }
  83
  84 static __hc32 *
  85 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  86                 __hc32 tag)
  87 {
  88         switch (hc32_to_cpu(ehci, tag)) {
  89         /* our ehci_shadow.qh is actually software part */
  90         case Q_TYPE_QH:
  91                 return &periodic->qh->hw->hw_next;
  92         /* others are hw parts */
  93         default:
  94                 return periodic->hw_next;
  95         }
  96 }
  97
  98 /* caller must hold ehci->lock */
  99 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
 100 {
 101         union ehci_shadow       *prev_p = &ehci->pshadow[frame];
 102         __hc32                  *hw_p = &ehci->periodic[frame];
 103         union ehci_shadow       here = *prev_p;
 104
 105         /* find predecessor of "ptr"; hw and shadow lists are in sync */
 106         while (here.ptr && here.ptr != ptr) {
 107                 prev_p = periodic_next_shadow(ehci, prev_p,
 108                                 Q_NEXT_TYPE(ehci, *hw_p));
 109                 hw_p = shadow_next_periodic(ehci, &here,
 110                                 Q_NEXT_TYPE(ehci, *hw_p));
 111                 here = *prev_p;
 112         }
 113         /* an interrupt entry (at list end) could have been shared */
 114         if (!here.ptr)
 115                 return;
 116
 117         /* update shadow and hardware lists ... the old "next" pointers
 118          * from ptr may still be in use, the caller updates them.
 119          */
 120         *prev_p = *periodic_next_shadow(ehci, &here,
 121                         Q_NEXT_TYPE(ehci, *hw_p));
 122
 123         if (!ehci->use_dummy_qh ||
 124             *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
 125                         != EHCI_LIST_END(ehci))
 126                 *hw_p = *shadow_next_periodic(ehci, &here,
 127                                 Q_NEXT_TYPE(ehci, *hw_p));
 128         else
 129                 *hw_p = ehci->dummy->qh_dma;
 130 }
 131
 132 /* how many of the uframe's 125 usecs are allocated? */
 133 static unsigned short
 134 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
 135 {
 136         __hc32                  *hw_p = &ehci->periodic [frame];
 137         union ehci_shadow       *q = &ehci->pshadow [frame];
 138         unsigned                usecs = 0;
 139         struct ehci_qh_hw       *hw;
 140
 141         while (q->ptr) {
 142                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 143                 case Q_TYPE_QH:
 144                         hw = q->qh->hw;
 145                         /* is it in the S-mask? */
 146                         if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
 147                                 usecs += q->qh->usecs;
 148                         /* ... or C-mask? */
 149                         if (hw->hw_info2 & cpu_to_hc32(ehci,
 150                                         1 << (8 + uframe)))
 151                                 usecs += q->qh->c_usecs;
 152                         hw_p = &hw->hw_next;
 153                         q = &q->qh->qh_next;
 154                         break;
 155                 // case Q_TYPE_FSTN:
 156                 default:
 157                         /* for "save place" FSTNs, count the relevant INTR
 158                          * bandwidth from the previous frame
 159                          */
 160                         if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
 161                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 162                         }
 163                         hw_p = &q->fstn->hw_next;
 164                         q = &q->fstn->fstn_next;
 165                         break;
 166                 case Q_TYPE_ITD:
 167                         if (q->itd->hw_transaction[uframe])
 168                                 usecs += q->itd->stream->usecs;
 169                         hw_p = &q->itd->hw_next;
 170                         q = &q->itd->itd_next;
 171                         break;
 172                 case Q_TYPE_SITD:
 173                         /* is it in the S-mask?  (count SPLIT, DATA) */
 174                         if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
 175                                         1 << uframe)) {
 176                                 if (q->sitd->hw_fullspeed_ep &
 177                                                 cpu_to_hc32(ehci, 1<<31))
 178                                         usecs += q->sitd->stream->usecs;
 179                                 else    /* worst case for OUT start-split */
 180                                         usecs += HS_USECS_ISO (188);
 181                         }
 182
 183                         /* ... C-mask?  (count CSPLIT, DATA) */
 184                         if (q->sitd->hw_uframe &
 185                                         cpu_to_hc32(ehci, 1 << (8 + uframe))) {
 186                                 /* worst case for IN complete-split */
 187                                 usecs += q->sitd->stream->c_usecs;
 188                         }
 189
 190                         hw_p = &q->sitd->hw_next;
 191                         q = &q->sitd->sitd_next;
 192                         break;
 193                 }
 194         }
 195 #ifdef  DEBUG
 196         if (usecs > 100)
 197                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 198                         frame * 8 + uframe, usecs);
 199 #endif
 200         return usecs;
 201 }
 202
 203 /*-------------------------------------------------------------------------*/
 204
 205 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 206 {
 207         if (!dev1->tt || !dev2->tt)
 208                 return 0;
 209         if (dev1->tt != dev2->tt)
 210                 return 0;
 211         if (dev1->tt->multi)
 212                 return dev1->ttport == dev2->ttport;
 213         else
 214                 return 1;
 215 }
 216
 217 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 218
 219 /* Which uframe does the low/fullspeed transfer start in?
 220  *
 221  * The parameter is the mask of ssplits in "H-frame" terms
 222  * and this returns the transfer start uframe in "B-frame" terms,
 223  * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
 224  * will cause a transfer in "B-frame" uframe 0.  "B-frames" lag
 225  * "H-frames" by 1 uframe.  See the EHCI spec sec 4.5 and figure 4.7.
 226  */
 227 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 228 {
 229         unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
 230         if (!smask) {
 231                 ehci_err(ehci, "invalid empty smask!\n");
 232                 /* uframe 7 can't have bw so this will indicate failure */
 233                 return 7;
 234         }
 235         return ffs(smask) - 1;
 236 }
 237
 238 static const unsigned char
 239 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 240
 241 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 242 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
 243 {
 244         int i;
 245         for (i=0; i<7; i++) {
 246                 if (max_tt_usecs[i] < tt_usecs[i]) {
 247                         tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
 248                         tt_usecs[i] = max_tt_usecs[i];
 249                 }
 250         }
 251 }
 252
 253 /* How many of the tt's periodic downstream 1000 usecs are allocated?
 254  *
 255  * While this measures the bandwidth in terms of usecs/uframe,
 256  * the low/fullspeed bus has no notion of uframes, so any particular
 257  * low/fullspeed transfer can "carry over" from one uframe to the next,
 258  * since the TT just performs downstream transfers in sequence.
 259  *
 260  * For example two separate 100 usec transfers can start in the same uframe,
 261  * and the second one would "carry over" 75 usecs into the next uframe.
 262  */
 263 static void
 264 periodic_tt_usecs (
 265         struct ehci_hcd *ehci,
 266         struct usb_device *dev,
 267         unsigned frame,
 268         unsigned short tt_usecs[8]
 269 )
 270 {
 271         __hc32                  *hw_p = &ehci->periodic [frame];
 272         union ehci_shadow       *q = &ehci->pshadow [frame];
 273         unsigned char           uf;
 274
 275         memset(tt_usecs, 0, 16);
 276
 277         while (q->ptr) {
 278                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 279                 case Q_TYPE_ITD:
 280                         hw_p = &q->itd->hw_next;
 281                         q = &q->itd->itd_next;
 282                         continue;
 283                 case Q_TYPE_QH:
 284                         if (same_tt(dev, q->qh->dev)) {
 285                                 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
 286                                 tt_usecs[uf] += q->qh->tt_usecs;
 287                         }
 288                         hw_p = &q->qh->hw->hw_next;
 289                         q = &q->qh->qh_next;
 290                         continue;
 291                 case Q_TYPE_SITD:
 292                         if (same_tt(dev, q->sitd->urb->dev)) {
 293                                 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
 294                                 tt_usecs[uf] += q->sitd->stream->tt_usecs;
 295                         }
 296                         hw_p = &q->sitd->hw_next;
 297                         q = &q->sitd->sitd_next;
 298                         continue;
 299                 // case Q_TYPE_FSTN:
 300                 default:
 301                         ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
 302                                         frame);
 303                         hw_p = &q->fstn->hw_next;
 304                         q = &q->fstn->fstn_next;
 305                 }
 306         }
 307
 308         carryover_tt_bandwidth(tt_usecs);
 309
 310         if (max_tt_usecs[7] < tt_usecs[7])
 311                 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
 312                         frame, tt_usecs[7] - max_tt_usecs[7]);
 313 }
 314
 315 /*
 316  * Return true if the device's tt's downstream bus is available for a
 317  * periodic transfer of the specified length (usecs), starting at the
 318  * specified frame/uframe.  Note that (as summarized in section 11.19
 319  * of the usb 2.0 spec) TTs can buffer multiple transactions for each
 320  * uframe.
 321  *
 322  * The uframe parameter is when the fullspeed/lowspeed transfer
 323  * should be executed in "B-frame" terms, which is the same as the
 324  * highspeed ssplit's uframe (which is in "H-frame" terms).  For example
 325  * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
 326  * See the EHCI spec sec 4.5 and fig 4.7.
 327  *
 328  * This checks if the full/lowspeed bus, at the specified starting uframe,
 329  * has the specified bandwidth available, according to rules listed
 330  * in USB 2.0 spec section 11.18.1 fig 11-60.
 331  *
 332  * This does not check if the transfer would exceed the max ssplit
 333  * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
 334  * since proper scheduling limits ssplits to less than 16 per uframe.
 335  */
 336 static int tt_available (
 337         struct ehci_hcd         *ehci,
 338         unsigned                period,
 339         struct usb_device       *dev,
 340         unsigned                frame,
 341         unsigned                uframe,
 342         u16                     usecs
 343 )
 344 {
 345         if ((period == 0) || (uframe >= 7))     /* error */
 346                 return 0;
 347
 348         for (; frame < ehci->periodic_size; frame += period) {
 349                 unsigned short tt_usecs[8];
 350
 351                 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
 352
 353                 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
 354                         " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
 355                         frame, usecs, uframe,
 356                         tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
 357                         tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
 358
 359                 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
 360                         ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
 361                                 frame, uframe);
 362                         return 0;
 363                 }
 364
 365                 /* special case for isoc transfers larger than 125us:
 366                  * the first and each subsequent fully used uframe
 367                  * must be empty, so as to not illegally delay
 368                  * already scheduled transactions
 369                  */
 370                 if (125 < usecs) {
 371                         int ufs = (usecs / 125);
 372                         int i;
 373                         for (i = uframe; i < (uframe + ufs) && i < 8; i++)
 374                                 if (0 < tt_usecs[i]) {
 375                                         ehci_vdbg(ehci,
 376                                                 "multi-uframe xfer can't fit "
 377                                                 "in frame %d uframe %d\n",
 378                                                 frame, i);
 379                                         return 0;
 380                                 }
 381                 }
 382
 383                 tt_usecs[uframe] += usecs;
 384
 385                 carryover_tt_bandwidth(tt_usecs);
 386
 387                 /* fail if the carryover pushed bw past the last uframe's limit */
 388                 if (max_tt_usecs[7] < tt_usecs[7]) {
 389                         ehci_vdbg(ehci,
 390                                 "tt unavailable usecs %d frame %d uframe %d\n",
 391                                 usecs, frame, uframe);
 392                         return 0;
 393                 }
 394         }
 395
 396         return 1;
 397 }
 398
 399 #else
 400
 401 /* return true iff the device's transaction translator is available
 402  * for a periodic transfer starting at the specified frame, using
 403  * all the uframes in the mask.
 404  */
 405 static int tt_no_collision (
 406         struct ehci_hcd         *ehci,
 407         unsigned                period,
 408         struct usb_device       *dev,
 409         unsigned                frame,
 410         u32                     uf_mask
 411 )
 412 {
 413         if (period == 0)        /* error */
 414                 return 0;
 415
 416         /* note bandwidth wastage:  split never follows csplit
 417          * (different dev or endpoint) until the next uframe.
 418          * calling convention doesn't make that distinction.
 419          */
 420         for (; frame < ehci->periodic_size; frame += period) {
 421                 union ehci_shadow       here;
 422                 __hc32                  type;
 423                 struct ehci_qh_hw       *hw;
 424
 425                 here = ehci->pshadow [frame];
 426                 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
 427                 while (here.ptr) {
 428                         switch (hc32_to_cpu(ehci, type)) {
 429                         case Q_TYPE_ITD:
 430                                 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
 431                                 here = here.itd->itd_next;
 432                                 continue;
 433                         case Q_TYPE_QH:
 434                                 hw = here.qh->hw;
 435                                 if (same_tt (dev, here.qh->dev)) {
 436                                         u32             mask;
 437
 438                                         mask = hc32_to_cpu(ehci,
 439                                                         hw->hw_info2);
 440                                         /* "knows" no gap is needed */
 441                                         mask |= mask >> 8;
 442                                         if (mask & uf_mask)
 443                                                 break;
 444                                 }
 445                                 type = Q_NEXT_TYPE(ehci, hw->hw_next);
 446                                 here = here.qh->qh_next;
 447                                 continue;
 448                         case Q_TYPE_SITD:
 449                                 if (same_tt (dev, here.sitd->urb->dev)) {
 450                                         u16             mask;
 451
 452                                         mask = hc32_to_cpu(ehci, here.sitd
 453                                                                 ->hw_uframe);
 454                                         /* FIXME assumes no gap for IN! */
 455                                         mask |= mask >> 8;
 456                                         if (mask & uf_mask)
 457                                                 break;
 458                                 }
 459                                 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
 460                                 here = here.sitd->sitd_next;
 461                                 continue;
 462                         // case Q_TYPE_FSTN:
 463                         default:
 464                                 ehci_dbg (ehci,
 465                                         "periodic frame %d bogus type %d\n",
 466                                         frame, type);
 467                         }
 468
 469                         /* collision or error */
 470                         return 0;
 471                 }
 472         }
 473
 474         /* no collision */
 475         return 1;
 476 }
 477
 478 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
 479
 480 /*-------------------------------------------------------------------------*/
 481
 482 static int enable_periodic (struct ehci_hcd *ehci)
 483 {
 484         u32     cmd;
 485         int     status;
 486
 487         if (ehci->periodic_sched++)
 488                 return 0;
 489
 490         /* did clearing PSE did take effect yet?
 491          * takes effect only at frame boundaries...
 492          */
 493         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 494                                              STS_PSS, 0, 9 * 125);
 495         if (status) {
 496                 usb_hc_died(ehci_to_hcd(ehci));
 497                 return status;
 498         }
 499
 500         cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
 501         ehci_writel(ehci, cmd, &ehci->regs->command);
 502         /* posted write ... PSS happens later */
 503         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
 504
 505         /* make sure ehci_work scans these */
 506         ehci->next_uframe = ehci_read_frame_index(ehci)
 507                 % (ehci->periodic_size << 3);
 508         if (unlikely(ehci->broken_periodic))
 509                 ehci->last_periodic_enable = ktime_get_real();
 510         return 0;
 511 }
 512
 513 static int disable_periodic (struct ehci_hcd *ehci)
 514 {
 515         u32     cmd;
 516         int     status;
 517
 518         if (--ehci->periodic_sched)
 519                 return 0;
 520
 521         if (unlikely(ehci->broken_periodic)) {
 522                 /* delay experimentally determined */
 523                 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
 524                 ktime_t now = ktime_get_real();
 525                 s64 delay = ktime_us_delta(safe, now);
 526
 527                 if (unlikely(delay > 0))
 528                         udelay(delay);
 529         }
 530
 531         /* did setting PSE not take effect yet?
 532          * takes effect only at frame boundaries...
 533          */
 534         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 535                                              STS_PSS, STS_PSS, 9 * 125);
 536         if (status) {
 537                 usb_hc_died(ehci_to_hcd(ehci));
 538                 return status;
 539         }
 540
 541         cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
 542         ehci_writel(ehci, cmd, &ehci->regs->command);
 543         /* posted write ... */
 544
 545         free_cached_lists(ehci);
 546
 547         ehci->next_uframe = -1;
 548         return 0;
 549 }
 550
 551 /*-------------------------------------------------------------------------*/
 552
 553 /* periodic schedule slots have iso tds (normal or split) first, then a
 554  * sparse tree for active interrupt transfers.
 555  *
 556  * this just links in a qh; caller guarantees uframe masks are set right.
 557  * no FSTN support (yet; ehci 0.96+)
 558  */
 559 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 560 {
 561         unsigned        i;
 562         unsigned        period = qh->period;
 563
 564         dev_dbg (&qh->dev->dev,
 565                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 566                 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
 567                         & (QH_CMASK | QH_SMASK),
 568                 qh, qh->start, qh->usecs, qh->c_usecs);
 569
 570         /* high bandwidth, or otherwise every microframe */
 571         if (period == 0)
 572                 period = 1;
 573
 574         for (i = qh->start; i < ehci->periodic_size; i += period) {
 575                 union ehci_shadow       *prev = &ehci->pshadow[i];
 576                 __hc32                  *hw_p = &ehci->periodic[i];
 577                 union ehci_shadow       here = *prev;
 578                 __hc32                  type = 0;
 579
 580                 /* skip the iso nodes at list head */
 581                 while (here.ptr) {
 582                         type = Q_NEXT_TYPE(ehci, *hw_p);
 583                         if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
 584                                 break;
 585                         prev = periodic_next_shadow(ehci, prev, type);
 586                         hw_p = shadow_next_periodic(ehci, &here, type);
 587                         here = *prev;
 588                 }
 589
 590                 /* sorting each branch by period (slow-->fast)
 591                  * enables sharing interior tree nodes
 592                  */
 593                 while (here.ptr && qh != here.qh) {
 594                         if (qh->period > here.qh->period)
 595                                 break;
 596                         prev = &here.qh->qh_next;
 597                         hw_p = &here.qh->hw->hw_next;
 598                         here = *prev;
 599                 }
 600                 /* link in this qh, unless some earlier pass did that */
 601                 if (qh != here.qh) {
 602                         qh->qh_next = here;
 603                         if (here.qh)
 604                                 qh->hw->hw_next = *hw_p;
 605                         wmb ();
 606                         prev->qh = qh;
 607                         *hw_p = QH_NEXT (ehci, qh->qh_dma);
 608                 }
 609         }
 610         qh->qh_state = QH_STATE_LINKED;
 611         qh->xacterrs = 0;
 612         qh_get (qh);
 613
 614         /* update per-qh bandwidth for usbfs */
 615         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 616                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 617                 : (qh->usecs * 8);
 618
 619         /* maybe enable periodic schedule processing */
 620         return enable_periodic(ehci);
 621 }
 622
 623 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
 624 {
 625         unsigned        i;
 626         unsigned        period;
 627
 628         // FIXME:
 629         // IF this isn't high speed
 630         //   and this qh is active in the current uframe
 631         //   (and overlay token SplitXstate is false?)
 632         // THEN
 633         //   qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
 634
 635         /* high bandwidth, or otherwise part of every microframe */
 636         if ((period = qh->period) == 0)
 637                 period = 1;
 638
 639         for (i = qh->start; i < ehci->periodic_size; i += period)
 640                 periodic_unlink (ehci, i, qh);
 641
 642         /* update per-qh bandwidth for usbfs */
 643         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 644                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 645                 : (qh->usecs * 8);
 646
 647         dev_dbg (&qh->dev->dev,
 648                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 649                 qh->period,
 650                 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
 651                 qh, qh->start, qh->usecs, qh->c_usecs);
 652
 653         /* qh->qh_next still "live" to HC */
 654         qh->qh_state = QH_STATE_UNLINK;
 655         qh->qh_next.ptr = NULL;
 656         qh_put (qh);
 657
 658         /* maybe turn off periodic schedule */
 659         return disable_periodic(ehci);
 660 }
 661
 662 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 663 {
 664         unsigned                wait;
 665         struct ehci_qh_hw       *hw = qh->hw;
 666         int                     rc;
 667
 668         /* If the QH isn't linked then there's nothing we can do
 669          * unless we were called during a giveback, in which case
 670          * qh_completions() has to deal with it.
 671          */
 672         if (qh->qh_state != QH_STATE_LINKED) {
 673                 if (qh->qh_state == QH_STATE_COMPLETING)
 674                         qh->needs_rescan = 1;
 675                 return;
 676         }
 677
 678         qh_unlink_periodic (ehci, qh);
 679
 680         /* simple/paranoid:  always delay, expecting the HC needs to read
 681          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 682          * expect khubd to clean up after any CSPLITs we won't issue.
 683          * active high speed queues may need bigger delays...
 684          */
 685         if (list_empty (&qh->qtd_list)
 686                         || (cpu_to_hc32(ehci, QH_CMASK)
 687                                         & hw->hw_info2) != 0)
 688                 wait = 2;
 689         else
 690                 wait = 55;      /* worst case: 3 * 1024 */
 691
 692         udelay (wait);
 693         qh->qh_state = QH_STATE_IDLE;
 694         hw->hw_next = EHCI_LIST_END(ehci);
 695         wmb ();
 696
 697         qh_completions(ehci, qh);
 698
 699         /* reschedule QH iff another request is queued */
 700         if (!list_empty(&qh->qtd_list) &&
 701                         HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
 702                 rc = qh_schedule(ehci, qh);
 703
 704                 /* An error here likely indicates handshake failure
 705                  * or no space left in the schedule.  Neither fault
 706                  * should happen often ...
 707                  *
 708                  * FIXME kill the now-dysfunctional queued urbs
 709                  */
 710                 if (rc != 0)
 711                         ehci_err(ehci, "can't reschedule qh %p, err %d\n",
 712                                         qh, rc);
 713         }
 714 }
 715
 716 /*-------------------------------------------------------------------------*/
 717
 718 static int check_period (
 719         struct ehci_hcd *ehci,
 720         unsigned        frame,
 721         unsigned        uframe,
 722         unsigned        period,
 723         unsigned        usecs
 724 ) {
 725         int             claimed;
 726
 727         /* complete split running into next frame?
 728          * given FSTN support, we could sometimes check...
 729          */
 730         if (uframe >= 8)
 731                 return 0;
 732
 733         /*
 734          * 80% periodic == 100 usec/uframe available
 735          * convert "usecs we need" to "max already claimed"
 736          */
 737         usecs = 100 - usecs;
 738
 739         /* we "know" 2 and 4 uframe intervals were rejected; so
 740          * for period 0, check _every_ microframe in the schedule.
 741          */
 742         if (unlikely (period == 0)) {
 743                 do {
 744                         for (uframe = 0; uframe < 7; uframe++) {
 745                                 claimed = periodic_usecs (ehci, frame, uframe);
 746                                 if (claimed > usecs)
 747                                         return 0;
 748                         }
 749                 } while ((frame += 1) < ehci->periodic_size);
 750
 751         /* just check the specified uframe, at that period */
 752         } else {
 753                 do {
 754                         claimed = periodic_usecs (ehci, frame, uframe);
 755                         if (claimed > usecs)
 756                                 return 0;
 757                 } while ((frame += period) < ehci->periodic_size);
 758         }
 759
 760         // success!
 761         return 1;
 762 }
 763
 764 static int check_intr_schedule (
 765         struct ehci_hcd         *ehci,
 766         unsigned                frame,
 767         unsigned                uframe,
 768         const struct ehci_qh    *qh,
 769         __hc32                  *c_maskp
 770 )
 771 {
 772         int             retval = -ENOSPC;
 773         u8              mask = 0;
 774
 775         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 776                 goto done;
 777
 778         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 779                 goto done;
 780         if (!qh->c_usecs) {
 781                 retval = 0;
 782                 *c_maskp = 0;
 783                 goto done;
 784         }
 785
 786 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 787         if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
 788                                 qh->tt_usecs)) {
 789                 unsigned i;
 790
 791                 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
 792                 for (i=uframe+1; i<8 && i<uframe+4; i++)
 793                         if (!check_period (ehci, frame, i,
 794                                                 qh->period, qh->c_usecs))
 795                                 goto done;
 796                         else
 797                                 mask |= 1 << i;
 798
 799                 retval = 0;
 800
 801                 *c_maskp = cpu_to_hc32(ehci, mask << 8);
 802         }
 803 #else
 804         /* Make sure this tt's buffer is also available for CSPLITs.
 805          * We pessimize a bit; probably the typical full speed case
 806          * doesn't need the second CSPLIT.
 807          *
 808          * NOTE:  both SPLIT and CSPLIT could be checked in just
 809          * one smart pass...
 810          */
 811         mask = 0x03 << (uframe + qh->gap_uf);
 812         *c_maskp = cpu_to_hc32(ehci, mask << 8);
 813
 814         mask |= 1 << uframe;
 815         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 816                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 817                                         qh->period, qh->c_usecs))
 818                         goto done;
 819                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 820                                         qh->period, qh->c_usecs))
 821                         goto done;
 822                 retval = 0;
 823         }
 824 #endif
 825 done:
 826         return retval;
 827 }
 828
 829 /* "first fit" scheduling policy used the first time through,
 830  * or when the previous schedule slot can't be re-used.
 831  */
 832 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
 833 {
 834         int             status;
 835         unsigned        uframe;
 836         __hc32          c_mask;
 837         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 838         struct ehci_qh_hw       *hw = qh->hw;
 839
 840         qh_refresh(ehci, qh);
 841         hw->hw_next = EHCI_LIST_END(ehci);
 842         frame = qh->start;
 843
 844         /* reuse the previous schedule slots, if we can */
 845         if (frame < qh->period) {
 846                 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
 847                 status = check_intr_schedule (ehci, frame, --uframe,
 848                                 qh, &c_mask);
 849         } else {
 850                 uframe = 0;
 851                 c_mask = 0;
 852                 status = -ENOSPC;
 853         }
 854
 855         /* else scan the schedule to find a group of slots such that all
 856          * uframes have enough periodic bandwidth available.
 857          */
 858         if (status) {
 859                 /* "normal" case, uframing flexible except with splits */
 860                 if (qh->period) {
 861                         int             i;
 862
 863                         for (i = qh->period; status && i > 0; --i) {
 864                                 frame = ++ehci->random_frame % qh->period;
 865                                 for (uframe = 0; uframe < 8; uframe++) {
 866                                         status = check_intr_schedule (ehci,
 867                                                         frame, uframe, qh,
 868                                                         &c_mask);
 869                                         if (status == 0)
 870                                                 break;
 871                                 }
 872                         }
 873
 874                 /* qh->period == 0 means every uframe */
 875                 } else {
 876                         frame = 0;
 877                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 878                 }
 879                 if (status)
 880                         goto done;
 881                 qh->start = frame;
 882
 883                 /* reset S-frame and (maybe) C-frame masks */
 884                 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
 885                 hw->hw_info2 |= qh->period
 886                         ? cpu_to_hc32(ehci, 1 << uframe)
 887                         : cpu_to_hc32(ehci, QH_SMASK);
 888                 hw->hw_info2 |= c_mask;
 889         } else
 890                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 891
 892         /* stuff into the periodic schedule */
 893         status = qh_link_periodic (ehci, qh);
 894 done:
 895         return status;
 896 }
 897
 898 static int intr_submit (
 899         struct ehci_hcd         *ehci,
 900         struct urb              *urb,
 901         struct list_head        *qtd_list,
 902         gfp_t                   mem_flags
 903 ) {
 904         unsigned                epnum;
 905         unsigned long           flags;
 906         struct ehci_qh          *qh;
 907         int                     status;
 908         struct list_head        empty;
 909
 910         /* get endpoint and transfer/schedule data */
 911         epnum = urb->ep->desc.bEndpointAddress;
 912
 913         spin_lock_irqsave (&ehci->lock, flags);
 914
 915         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
 916                 status = -ESHUTDOWN;
 917                 goto done_not_linked;
 918         }
 919         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
 920         if (unlikely(status))
 921                 goto done_not_linked;
 922
 923         /* get qh and force any scheduling errors */
 924         INIT_LIST_HEAD (&empty);
 925         qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
 926         if (qh == NULL) {
 927                 status = -ENOMEM;
 928                 goto done;
 929         }
 930         if (qh->qh_state == QH_STATE_IDLE) {
 931                 if ((status = qh_schedule (ehci, qh)) != 0)
 932                         goto done;
 933         }
 934
 935         /* then queue the urb's tds to the qh */
 936         qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
 937         BUG_ON (qh == NULL);
 938
 939         /* ... update usbfs periodic stats */
 940         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 941
 942 done:
 943         if (unlikely(status))
 944                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
 945 done_not_linked:
 946         spin_unlock_irqrestore (&ehci->lock, flags);
 947         if (status)
 948                 qtd_list_free (ehci, urb, qtd_list);
 949
 950         return status;
 951 }
 952
 953 /*-------------------------------------------------------------------------*/
 954
 955 /* ehci_iso_stream ops work with both ITD and SITD */
 956
 957 static struct ehci_iso_stream *
 958 iso_stream_alloc (gfp_t mem_flags)
 959 {
 960         struct ehci_iso_stream *stream;
 961
 962         stream = kzalloc(sizeof *stream, mem_flags);
 963         if (likely (stream != NULL)) {
 964                 INIT_LIST_HEAD(&stream->td_list);
 965                 INIT_LIST_HEAD(&stream->free_list);
 966                 stream->next_uframe = -1;
 967                 stream->refcount = 1;
 968         }
 969         return stream;
 970 }
 971
 972 static void
 973 iso_stream_init (
 974         struct ehci_hcd         *ehci,
 975         struct ehci_iso_stream  *stream,
 976         struct usb_device       *dev,
 977         int                     pipe,
 978         unsigned                interval
 979 )
 980 {
 981         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 982
 983         u32                     buf1;
 984         unsigned                epnum, maxp;
 985         int                     is_input;
 986         long                    bandwidth;
 987
 988         /*
 989          * this might be a "high bandwidth" highspeed endpoint,
 990          * as encoded in the ep descriptor's wMaxPacket field
 991          */
 992         epnum = usb_pipeendpoint (pipe);
 993         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 994         maxp = usb_maxpacket(dev, pipe, !is_input);
 995         if (is_input) {
 996                 buf1 = (1 << 11);
 997         } else {
 998                 buf1 = 0;
 999         }
1000
1001         /* knows about ITD vs SITD */
1002         if (dev->speed == USB_SPEED_HIGH) {
1003                 unsigned multi = hb_mult(maxp);
1004
1005                 stream->highspeed = 1;
1006
1007                 maxp = max_packet(maxp);
1008                 buf1 |= maxp;
1009                 maxp *= multi;
1010
1011                 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
1012                 stream->buf1 = cpu_to_hc32(ehci, buf1);
1013                 stream->buf2 = cpu_to_hc32(ehci, multi);
1014
1015                 /* usbfs wants to report the average usecs per frame tied up
1016                  * when transfers on this endpoint are scheduled ...
1017                  */
1018                 stream->usecs = HS_USECS_ISO (maxp);
1019                 bandwidth = stream->usecs * 8;
1020                 bandwidth /= interval;
1021
1022         } else {
1023                 u32             addr;
1024                 int             think_time;
1025                 int             hs_transfers;
1026
1027                 addr = dev->ttport << 24;
1028                 if (!ehci_is_TDI(ehci)
1029                                 || (dev->tt->hub !=
1030                                         ehci_to_hcd(ehci)->self.root_hub))
1031                         addr |= dev->tt->hub->devnum << 16;
1032                 addr |= epnum << 8;
1033                 addr |= dev->devnum;
1034                 stream->usecs = HS_USECS_ISO (maxp);
1035                 think_time = dev->tt ? dev->tt->think_time : 0;
1036                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1037                                 dev->speed, is_input, 1, maxp));
1038                 hs_transfers = max (1u, (maxp + 187) / 188);
1039                 if (is_input) {
1040                         u32     tmp;
1041
1042                         addr |= 1 << 31;
1043                         stream->c_usecs = stream->usecs;
1044                         stream->usecs = HS_USECS_ISO (1);
1045                         stream->raw_mask = 1;
1046
1047                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
1048                         tmp = (1 << (hs_transfers + 2)) - 1;
1049                         stream->raw_mask |= tmp << (8 + 2);
1050                 } else
1051                         stream->raw_mask = smask_out [hs_transfers - 1];
1052                 bandwidth = stream->usecs + stream->c_usecs;
1053                 bandwidth /= interval << 3;
1054
1055                 /* stream->splits gets created from raw_mask later */
1056                 stream->address = cpu_to_hc32(ehci, addr);
1057         }
1058         stream->bandwidth = bandwidth;
1059
1060         stream->udev = dev;
1061
1062         stream->bEndpointAddress = is_input | epnum;
1063         stream->interval = interval;
1064         stream->maxp = maxp;
1065 }
1066
1067 static void
1068 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1069 {
1070         stream->refcount--;
1071
1072         /* free whenever just a dev->ep reference remains.
1073          * not like a QH -- no persistent state (toggle, halt)
1074          */
1075         if (stream->refcount == 1) {
1076                 // BUG_ON (!list_empty(&stream->td_list));
1077
1078                 while (!list_empty (&stream->free_list)) {
1079                         struct list_head        *entry;
1080
1081                         entry = stream->free_list.next;
1082                         list_del (entry);
1083
1084                         /* knows about ITD vs SITD */
1085                         if (stream->highspeed) {
1086                                 struct ehci_itd         *itd;
1087
1088                                 itd = list_entry (entry, struct ehci_itd,
1089                                                 itd_list);
1090                                 dma_pool_free (ehci->itd_pool, itd,
1091                                                 itd->itd_dma);
1092                         } else {
1093                                 struct ehci_sitd        *sitd;
1094
1095                                 sitd = list_entry (entry, struct ehci_sitd,
1096                                                 sitd_list);
1097                                 dma_pool_free (ehci->sitd_pool, sitd,
1098                                                 sitd->sitd_dma);
1099                         }
1100                 }
1101
1102                 stream->bEndpointAddress &= 0x0f;
1103                 if (stream->ep)
1104                         stream->ep->hcpriv = NULL;
1105
1106                 kfree(stream);
1107         }
1108 }
1109
1110 static inline struct ehci_iso_stream *
1111 iso_stream_get (struct ehci_iso_stream *stream)
1112 {
1113         if (likely (stream != NULL))
1114                 stream->refcount++;
1115         return stream;
1116 }
1117
1118 static struct ehci_iso_stream *
1119 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1120 {
1121         unsigned                epnum;
1122         struct ehci_iso_stream  *stream;
1123         struct usb_host_endpoint *ep;
1124         unsigned long           flags;
1125
1126         epnum = usb_pipeendpoint (urb->pipe);
1127         if (usb_pipein(urb->pipe))
1128                 ep = urb->dev->ep_in[epnum];
1129         else
1130                 ep = urb->dev->ep_out[epnum];
1131
1132         spin_lock_irqsave (&ehci->lock, flags);
1133         stream = ep->hcpriv;
1134
1135         if (unlikely (stream == NULL)) {
1136                 stream = iso_stream_alloc(GFP_ATOMIC);
1137                 if (likely (stream != NULL)) {
1138                         /* dev->ep owns the initial refcount */
1139                         ep->hcpriv = stream;
1140                         stream->ep = ep;
1141                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1142                                         urb->interval);
1143                 }
1144
1145         /* if dev->ep [epnum] is a QH, hw is set */
1146         } else if (unlikely (stream->hw != NULL)) {
1147                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1148                         urb->dev->devpath, epnum,
1149                         usb_pipein(urb->pipe) ? "in" : "out");
1150                 stream = NULL;
1151         }
1152
1153         /* caller guarantees an eventual matching iso_stream_put */
1154         stream = iso_stream_get (stream);
1155
1156         spin_unlock_irqrestore (&ehci->lock, flags);
1157         return stream;
1158 }
1159
1160 /*-------------------------------------------------------------------------*/
1161
1162 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1163
1164 static struct ehci_iso_sched *
1165 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1166 {
1167         struct ehci_iso_sched   *iso_sched;
1168         int                     size = sizeof *iso_sched;
1169
1170         size += packets * sizeof (struct ehci_iso_packet);
1171         iso_sched = kzalloc(size, mem_flags);
1172         if (likely (iso_sched != NULL)) {
1173                 INIT_LIST_HEAD (&iso_sched->td_list);
1174         }
1175         return iso_sched;
1176 }
1177
1178 static inline void
1179 itd_sched_init(
1180         struct ehci_hcd         *ehci,
1181         struct ehci_iso_sched   *iso_sched,
1182         struct ehci_iso_stream  *stream,
1183         struct urb              *urb
1184 )
1185 {
1186         unsigned        i;
1187         dma_addr_t      dma = urb->transfer_dma;
1188
1189         /* how many uframes are needed for these transfers */
1190         iso_sched->span = urb->number_of_packets * stream->interval;
1191
1192         /* figure out per-uframe itd fields that we'll need later
1193          * when we fit new itds into the schedule.
1194          */
1195         for (i = 0; i < urb->number_of_packets; i++) {
1196                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
1197                 unsigned                length;
1198                 dma_addr_t              buf;
1199                 u32                     trans;
1200
1201                 length = urb->iso_frame_desc [i].length;
1202                 buf = dma + urb->iso_frame_desc [i].offset;
1203
1204                 trans = EHCI_ISOC_ACTIVE;
1205                 trans |= buf & 0x0fff;
1206                 if (unlikely (((i + 1) == urb->number_of_packets))
1207                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1208                         trans |= EHCI_ITD_IOC;
1209                 trans |= length << 16;
1210                 uframe->transaction = cpu_to_hc32(ehci, trans);
1211
1212                 /* might need to cross a buffer page within a uframe */
1213                 uframe->bufp = (buf & ~(u64)0x0fff);
1214                 buf += length;
1215                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1216                         uframe->cross = 1;
1217         }
1218 }
1219
1220 static void
1221 iso_sched_free (
1222         struct ehci_iso_stream  *stream,
1223         struct ehci_iso_sched   *iso_sched
1224 )
1225 {
1226         if (!iso_sched)
1227                 return;
1228         // caller must hold ehci->lock!
1229         list_splice (&iso_sched->td_list, &stream->free_list);
1230         kfree (iso_sched);
1231 }
1232
1233 static int
1234 itd_urb_transaction (
1235         struct ehci_iso_stream  *stream,
1236         struct ehci_hcd         *ehci,
1237         struct urb              *urb,
1238         gfp_t                   mem_flags
1239 )
1240 {
1241         struct ehci_itd         *itd;
1242         dma_addr_t              itd_dma;
1243         int                     i;
1244         unsigned                num_itds;
1245         struct ehci_iso_sched   *sched;
1246         unsigned long           flags;
1247
1248         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1249         if (unlikely (sched == NULL))
1250                 return -ENOMEM;
1251
1252         itd_sched_init(ehci, sched, stream, urb);
1253
1254         if (urb->interval < 8)
1255                 num_itds = 1 + (sched->span + 7) / 8;
1256         else
1257                 num_itds = urb->number_of_packets;
1258
1259         /* allocate/init ITDs */
1260         spin_lock_irqsave (&ehci->lock, flags);
1261         for (i = 0; i < num_itds; i++) {
1262
1263                 /* free_list.next might be cache-hot ... but maybe
1264                  * the HC caches it too. avoid that issue for now.
1265                  */
1266
1267                 /* prefer previously-allocated itds */
1268                 if (likely (!list_empty(&stream->free_list))) {
1269                         itd = list_entry (stream->free_list.prev,
1270                                         struct ehci_itd, itd_list);
1271                         list_del (&itd->itd_list);
1272                         itd_dma = itd->itd_dma;
1273                 } else {
1274                         spin_unlock_irqrestore (&ehci->lock, flags);
1275                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1276                                         &itd_dma);
1277                         spin_lock_irqsave (&ehci->lock, flags);
1278                         if (!itd) {
1279                                 iso_sched_free(stream, sched);
1280                                 spin_unlock_irqrestore(&ehci->lock, flags);
1281                                 return -ENOMEM;
1282                         }
1283                 }
1284
1285                 memset (itd, 0, sizeof *itd);
1286                 itd->itd_dma = itd_dma;
1287                 list_add (&itd->itd_list, &sched->td_list);
1288         }
1289         spin_unlock_irqrestore (&ehci->lock, flags);
1290
1291         /* temporarily store schedule info in hcpriv */
1292         urb->hcpriv = sched;
1293         urb->error_count = 0;
1294         return 0;
1295 }
1296
1297 /*-------------------------------------------------------------------------*/
1298
1299 static inline int
1300 itd_slot_ok (
1301         struct ehci_hcd         *ehci,
1302         u32                     mod,
1303         u32                     uframe,
1304         u8                      usecs,
1305         u32                     period
1306 )
1307 {
1308         uframe %= period;
1309         do {
1310                 /* can't commit more than 80% periodic == 100 usec */
1311                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1312                                 > (100 - usecs))
1313                         return 0;
1314
1315                 /* we know urb->interval is 2^N uframes */
1316                 uframe += period;
1317         } while (uframe < mod);
1318         return 1;
1319 }
1320
1321 static inline int
1322 sitd_slot_ok (
1323         struct ehci_hcd         *ehci,
1324         u32                     mod,
1325         struct ehci_iso_stream  *stream,
1326         u32                     uframe,
1327         struct ehci_iso_sched   *sched,
1328         u32                     period_uframes
1329 )
1330 {
1331         u32                     mask, tmp;
1332         u32                     frame, uf;
1333
1334         mask = stream->raw_mask << (uframe & 7);
1335
1336         /* for IN, don't wrap CSPLIT into the next frame */
1337         if (mask & ~0xffff)
1338                 return 0;
1339
1340         /* this multi-pass logic is simple, but performance may
1341          * suffer when the schedule data isn't cached.
1342          */
1343
1344         /* check bandwidth */
1345         uframe %= period_uframes;
1346         do {
1347                 u32             max_used;
1348
1349                 frame = uframe >> 3;
1350                 uf = uframe & 7;
1351
1352 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1353                 /* The tt's fullspeed bus bandwidth must be available.
1354                  * tt_available scheduling guarantees 10+% for control/bulk.
1355                  */
1356                 if (!tt_available (ehci, period_uframes << 3,
1357                                 stream->udev, frame, uf, stream->tt_usecs))
1358                         return 0;
1359 #else
1360                 /* tt must be idle for start(s), any gap, and csplit.
1361                  * assume scheduling slop leaves 10+% for control/bulk.
1362                  */
1363                 if (!tt_no_collision (ehci, period_uframes << 3,
1364                                 stream->udev, frame, mask))
1365                         return 0;
1366 #endif
1367
1368                 /* check starts (OUT uses more than one) */
1369                 max_used = 100 - stream->usecs;
1370                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1371                         if (periodic_usecs (ehci, frame, uf) > max_used)
1372                                 return 0;
1373                 }
1374
1375                 /* for IN, check CSPLIT */
1376                 if (stream->c_usecs) {
1377                         uf = uframe & 7;
1378                         max_used = 100 - stream->c_usecs;
1379                         do {
1380                                 tmp = 1 << uf;
1381                                 tmp <<= 8;
1382                                 if ((stream->raw_mask & tmp) == 0)
1383                                         continue;
1384                                 if (periodic_usecs (ehci, frame, uf)
1385                                                 > max_used)
1386                                         return 0;
1387                         } while (++uf < 8);
1388                 }
1389
1390                 /* we know urb->interval is 2^N uframes */
1391                 uframe += period_uframes;
1392         } while (uframe < mod);
1393
1394         stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1395         return 1;
1396 }
1397
1398 /*
1399  * This scheduler plans almost as far into the future as it has actual
1400  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1401  * "as small as possible" to be cache-friendlier.)  That limits the size
1402  * transfers you can stream reliably; avoid more than 64 msec per urb.
1403  * Also avoid queue depths of less than ehci's worst irq latency (affected
1404  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1405  * and other factors); or more than about 230 msec total (for portability,
1406  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1407  */
1408
1409 #define SCHEDULE_SLOP   80      /* microframes */
1410
1411 static int
1412 iso_stream_schedule (
1413         struct ehci_hcd         *ehci,
1414         struct urb              *urb,
1415         struct ehci_iso_stream  *stream
1416 )
1417 {
1418         u32                     now, next, start, period, span;
1419         int                     status;
1420         unsigned                mod = ehci->periodic_size << 3;
1421         struct ehci_iso_sched   *sched = urb->hcpriv;
1422
1423         period = urb->interval;
1424         span = sched->span;
1425         if (!stream->highspeed) {
1426                 period <<= 3;
1427                 span <<= 3;
1428         }
1429
1430         if (span > mod - SCHEDULE_SLOP) {
1431                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1432                 status = -EFBIG;
1433                 goto fail;
1434         }
1435
1436         now = ehci_read_frame_index(ehci) & (mod - 1);
1437
1438         /* Typical case: reuse current schedule, stream is still active.
1439          * Hopefully there are no gaps from the host falling behind
1440          * (irq delays etc), but if there are we'll take the next
1441          * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1442          */
1443         if (likely (!list_empty (&stream->td_list))) {
1444                 u32     excess;
1445
1446                 /* For high speed devices, allow scheduling within the
1447                  * isochronous scheduling threshold.  For full speed devices
1448                  * and Intel PCI-based controllers, don't (work around for
1449                  * Intel ICH9 bug).
1450                  */
1451                 if (!stream->highspeed && ehci->fs_i_thresh)
1452                         next = now + ehci->i_thresh;
1453                 else
1454                         next = now;
1455
1456                 /* Fell behind (by up to twice the slop amount)?
1457                  * We decide based on the time of the last currently-scheduled
1458                  * slot, not the time of the next available slot.
1459                  */
1460                 excess = (stream->next_uframe - period - next) & (mod - 1);
1461                 if (excess >= mod - 2 * SCHEDULE_SLOP)
1462                         start = next + excess - mod + period *
1463                                         DIV_ROUND_UP(mod - excess, period);
1464                 else
1465                         start = next + excess + period;
1466                 if (start - now >= mod) {
1467                         ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1468                                         urb, start - now - period, period,
1469                                         mod);
1470                         status = -EFBIG;
1471                         goto fail;
1472                 }
1473         }
1474
1475         /* need to schedule; when's the next (u)frame we could start?
1476          * this is bigger than ehci->i_thresh allows; scheduling itself
1477          * isn't free, the slop should handle reasonably slow cpus.  it
1478          * can also help high bandwidth if the dma and irq loads don't
1479          * jump until after the queue is primed.
1480          */
1481         else {
1482                 start = SCHEDULE_SLOP + (now & ~0x07);
1483
1484                 /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1485
1486                 /* find a uframe slot with enough bandwidth */
1487                 next = start + period;
1488                 for (; start < next; start++) {
1489
1490                         /* check schedule: enough space? */
1491                         if (stream->highspeed) {
1492                                 if (itd_slot_ok(ehci, mod, start,
1493                                                 stream->usecs, period))
1494                                         break;
1495                         } else {
1496                                 if ((start % 8) >= 6)
1497                                         continue;
1498                                 if (sitd_slot_ok(ehci, mod, stream,
1499                                                 start, sched, period))
1500                                         break;
1501                         }
1502                 }
1503
1504                 /* no room in the schedule */
1505                 if (start == next) {
1506                         ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1507                                 urb, now, now + mod);
1508                         status = -ENOSPC;
1509                         goto fail;
1510                 }
1511         }
1512
1513         /* Tried to schedule too far into the future? */
1514         if (unlikely(start - now + span - period
1515                                 >= mod - 2 * SCHEDULE_SLOP)) {
1516                 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1517                                 urb, start - now, span - period,
1518                                 mod - 2 * SCHEDULE_SLOP);
1519                 status = -EFBIG;
1520                 goto fail;
1521         }
1522
1523         stream->next_uframe = start & (mod - 1);
1524
1525         /* report high speed start in uframes; full speed, in frames */
1526         urb->start_frame = stream->next_uframe;
1527         if (!stream->highspeed)
1528                 urb->start_frame >>= 3;
1529         return 0;
1530
1531  fail:
1532         iso_sched_free(stream, sched);
1533         urb->hcpriv = NULL;
1534         return status;
1535 }
1536
1537 /*-------------------------------------------------------------------------*/
1538
1539 static inline void
1540 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1541                 struct ehci_itd *itd)
1542 {
1543         int i;
1544
1545         /* it's been recently zeroed */
1546         itd->hw_next = EHCI_LIST_END(ehci);
1547         itd->hw_bufp [0] = stream->buf0;
1548         itd->hw_bufp [1] = stream->buf1;
1549         itd->hw_bufp [2] = stream->buf2;
1550
1551         for (i = 0; i < 8; i++)
1552                 itd->index[i] = -1;
1553
1554         /* All other fields are filled when scheduling */
1555 }
1556
1557 static inline void
1558 itd_patch(
1559         struct ehci_hcd         *ehci,
1560         struct ehci_itd         *itd,
1561         struct ehci_iso_sched   *iso_sched,
1562         unsigned                index,
1563         u16                     uframe
1564 )
1565 {
1566         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1567         unsigned                pg = itd->pg;
1568
1569         // BUG_ON (pg == 6 && uf->cross);
1570
1571         uframe &= 0x07;
1572         itd->index [uframe] = index;
1573
1574         itd->hw_transaction[uframe] = uf->transaction;
1575         itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1576         itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1577         itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1578
1579         /* iso_frame_desc[].offset must be strictly increasing */
1580         if (unlikely (uf->cross)) {
1581                 u64     bufp = uf->bufp + 4096;
1582
1583                 itd->pg = ++pg;
1584                 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1585                 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1586         }
1587 }
1588
1589 static inline void
1590 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1591 {
1592         union ehci_shadow       *prev = &ehci->pshadow[frame];
1593         __hc32                  *hw_p = &ehci->periodic[frame];
1594         union ehci_shadow       here = *prev;
1595         __hc32                  type = 0;
1596
1597         /* skip any iso nodes which might belong to previous microframes */
1598         while (here.ptr) {
1599                 type = Q_NEXT_TYPE(ehci, *hw_p);
1600                 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1601                         break;
1602                 prev = periodic_next_shadow(ehci, prev, type);
1603                 hw_p = shadow_next_periodic(ehci, &here, type);
1604                 here = *prev;
1605         }
1606
1607         itd->itd_next = here;
1608         itd->hw_next = *hw_p;
1609         prev->itd = itd;
1610         itd->frame = frame;
1611         wmb ();
1612         *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1613 }
1614
1615 /* fit urb's itds into the selected schedule slot; activate as needed */
1616 static int
1617 itd_link_urb (
1618         struct ehci_hcd         *ehci,
1619         struct urb              *urb,
1620         unsigned                mod,
1621         struct ehci_iso_stream  *stream
1622 )
1623 {
1624         int                     packet;
1625         unsigned                next_uframe, uframe, frame;
1626         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1627         struct ehci_itd         *itd;
1628
1629         next_uframe = stream->next_uframe & (mod - 1);
1630
1631         if (unlikely (list_empty(&stream->td_list))) {
1632                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1633                                 += stream->bandwidth;
1634                 ehci_vdbg (ehci,
1635                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1636                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1637                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1638                         urb->interval,
1639                         next_uframe >> 3, next_uframe & 0x7);
1640         }
1641
1642         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1643                 if (ehci->amd_pll_fix == 1)
1644                         usb_amd_quirk_pll_disable();
1645         }
1646
1647         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1648
1649         /* fill iTDs uframe by uframe */
1650         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1651                 if (itd == NULL) {
1652                         /* ASSERT:  we have all necessary itds */
1653                         // BUG_ON (list_empty (&iso_sched->td_list));
1654
1655                         /* ASSERT:  no itds for this endpoint in this uframe */
1656
1657                         itd = list_entry (iso_sched->td_list.next,
1658                                         struct ehci_itd, itd_list);
1659                         list_move_tail (&itd->itd_list, &stream->td_list);
1660                         itd->stream = iso_stream_get (stream);
1661                         itd->urb = urb;
1662                         itd_init (ehci, stream, itd);
1663                 }
1664
1665                 uframe = next_uframe & 0x07;
1666                 frame = next_uframe >> 3;
1667
1668                 itd_patch(ehci, itd, iso_sched, packet, uframe);
1669
1670                 next_uframe += stream->interval;
1671                 next_uframe &= mod - 1;
1672                 packet++;
1673
1674                 /* link completed itds into the schedule */
1675                 if (((next_uframe >> 3) != frame)
1676                                 || packet == urb->number_of_packets) {
1677                         itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1678                         itd = NULL;
1679                 }
1680         }
1681         stream->next_uframe = next_uframe;
1682
1683         /* don't need that schedule data any more */
1684         iso_sched_free (stream, iso_sched);
1685         urb->hcpriv = NULL;
1686
1687         timer_action (ehci, TIMER_IO_WATCHDOG);
1688         return enable_periodic(ehci);
1689 }
1690
1691 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1692
1693 /* Process and recycle a completed ITD.  Return true iff its urb completed,
1694  * and hence its completion callback probably added things to the hardware
1695  * schedule.
1696  *
1697  * Note that we carefully avoid recycling this descriptor until after any
1698  * completion callback runs, so that it won't be reused quickly.  That is,
1699  * assuming (a) no more than two urbs per frame on this endpoint, and also
1700  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1701  * corrupts things if you reuse completed descriptors very quickly...
1702  */
1703 static unsigned
1704 itd_complete (
1705         struct ehci_hcd *ehci,
1706         struct ehci_itd *itd
1707 ) {
1708         struct urb                              *urb = itd->urb;
1709         struct usb_iso_packet_descriptor        *desc;
1710         u32                                     t;
1711         unsigned                                uframe;
1712         int                                     urb_index = -1;
1713         struct ehci_iso_stream                  *stream = itd->stream;
1714         struct usb_device                       *dev;
1715         unsigned                                retval = false;
1716
1717         /* for each uframe with a packet */
1718         for (uframe = 0; uframe < 8; uframe++) {
1719                 if (likely (itd->index[uframe] == -1))
1720                         continue;
1721                 urb_index = itd->index[uframe];
1722                 desc = &urb->iso_frame_desc [urb_index];
1723
1724                 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1725                 itd->hw_transaction [uframe] = 0;
1726
1727                 /* report transfer status */
1728                 if (unlikely (t & ISO_ERRS)) {
1729                         urb->error_count++;
1730                         if (t & EHCI_ISOC_BUF_ERR)
1731                                 desc->status = usb_pipein (urb->pipe)
1732                                         ? -ENOSR  /* hc couldn't read */
1733                                         : -ECOMM; /* hc couldn't write */
1734                         else if (t & EHCI_ISOC_BABBLE)
1735                                 desc->status = -EOVERFLOW;
1736                         else /* (t & EHCI_ISOC_XACTERR) */
1737                                 desc->status = -EPROTO;
1738
1739                         /* HC need not update length with this error */
1740                         if (!(t & EHCI_ISOC_BABBLE)) {
1741                                 desc->actual_length = EHCI_ITD_LENGTH(t);
1742                                 urb->actual_length += desc->actual_length;
1743                         }
1744                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1745                         desc->status = 0;
1746                         desc->actual_length = EHCI_ITD_LENGTH(t);
1747                         urb->actual_length += desc->actual_length;
1748                 } else {
1749                         /* URB was too late */
1750                         desc->status = -EXDEV;
1751                 }
1752         }
1753
1754         /* handle completion now? */
1755         if (likely ((urb_index + 1) != urb->number_of_packets))
1756                 goto done;
1757
1758         /* ASSERT: it's really the last itd for this urb
1759         list_for_each_entry (itd, &stream->td_list, itd_list)
1760                 BUG_ON (itd->urb == urb);
1761          */
1762
1763         /* give urb back to the driver; completion often (re)submits */
1764         dev = urb->dev;
1765         ehci_urb_done(ehci, urb, 0);
1766         retval = true;
1767         urb = NULL;
1768         (void) disable_periodic(ehci);
1769         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1770
1771         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
1772                 if (ehci->amd_pll_fix == 1)
1773                         usb_amd_quirk_pll_enable();
1774         }
1775
1776         if (unlikely(list_is_singular(&stream->td_list))) {
1777                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1778                                 -= stream->bandwidth;
1779                 ehci_vdbg (ehci,
1780                         "deschedule devp %s ep%d%s-iso\n",
1781                         dev->devpath, stream->bEndpointAddress & 0x0f,
1782                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1783         }
1784         iso_stream_put (ehci, stream);
1785
1786 done:
1787         itd->urb = NULL;
1788         if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1789                 /* OK to recycle this ITD now. */
1790                 itd->stream = NULL;
1791                 list_move(&itd->itd_list, &stream->free_list);
1792                 iso_stream_put(ehci, stream);
1793         } else {
1794                 /* HW might remember this ITD, so we can't recycle it yet.
1795                  * Move it to a safe place until a new frame starts.
1796                  */
1797                 list_move(&itd->itd_list, &ehci->cached_itd_list);
1798                 if (stream->refcount == 2) {
1799                         /* If iso_stream_put() were called here, stream
1800                          * would be freed.  Instead, just prevent reuse.
1801                          */
1802                         stream->ep->hcpriv = NULL;
1803                         stream->ep = NULL;
1804                 }
1805         }
1806         return retval;
1807 }
1808
1809 /*-------------------------------------------------------------------------*/
1810
1811 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1812         gfp_t mem_flags)
1813 {
1814         int                     status = -EINVAL;
1815         unsigned long           flags;
1816         struct ehci_iso_stream  *stream;
1817
1818         /* Get iso_stream head */
1819         stream = iso_stream_find (ehci, urb);
1820         if (unlikely (stream == NULL)) {
1821                 ehci_dbg (ehci, "can't get iso stream\n");
1822                 return -ENOMEM;
1823         }
1824         if (unlikely (urb->interval != stream->interval)) {
1825                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1826                         stream->interval, urb->interval);
1827                 goto done;
1828         }
1829
1830 #ifdef EHCI_URB_TRACE
1831         ehci_dbg (ehci,
1832                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1833                 __func__, urb->dev->devpath, urb,
1834                 usb_pipeendpoint (urb->pipe),
1835                 usb_pipein (urb->pipe) ? "in" : "out",
1836                 urb->transfer_buffer_length,
1837                 urb->number_of_packets, urb->interval,
1838                 stream);
1839 #endif
1840
1841         /* allocate ITDs w/o locking anything */
1842         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1843         if (unlikely (status < 0)) {
1844                 ehci_dbg (ehci, "can't init itds\n");
1845                 goto done;
1846         }
1847
1848         /* schedule ... need to lock */
1849         spin_lock_irqsave (&ehci->lock, flags);
1850         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1851                 status = -ESHUTDOWN;
1852                 goto done_not_linked;
1853         }
1854         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1855         if (unlikely(status))
1856                 goto done_not_linked;
1857         status = iso_stream_schedule(ehci, urb, stream);
1858         if (likely (status == 0))
1859                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1860         else
1861                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1862 done_not_linked:
1863         spin_unlock_irqrestore (&ehci->lock, flags);
1864
1865 done:
1866         if (unlikely (status < 0))
1867                 iso_stream_put (ehci, stream);
1868         return status;
1869 }
1870
1871 /*-------------------------------------------------------------------------*/
1872
1873 /*
1874  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1875  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1876  */
1877
1878 static inline void
1879 sitd_sched_init(
1880         struct ehci_hcd         *ehci,
1881         struct ehci_iso_sched   *iso_sched,
1882         struct ehci_iso_stream  *stream,
1883         struct urb              *urb
1884 )
1885 {
1886         unsigned        i;
1887         dma_addr_t      dma = urb->transfer_dma;
1888
1889         /* how many frames are needed for these transfers */
1890         iso_sched->span = urb->number_of_packets * stream->interval;
1891
1892         /* figure out per-frame sitd fields that we'll need later
1893          * when we fit new sitds into the schedule.
1894          */
1895         for (i = 0; i < urb->number_of_packets; i++) {
1896                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1897                 unsigned                length;
1898                 dma_addr_t              buf;
1899                 u32                     trans;
1900
1901                 length = urb->iso_frame_desc [i].length & 0x03ff;
1902                 buf = dma + urb->iso_frame_desc [i].offset;
1903
1904                 trans = SITD_STS_ACTIVE;
1905                 if (((i + 1) == urb->number_of_packets)
1906                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1907                         trans |= SITD_IOC;
1908                 trans |= length << 16;
1909                 packet->transaction = cpu_to_hc32(ehci, trans);
1910
1911                 /* might need to cross a buffer page within a td */
1912                 packet->bufp = buf;
1913                 packet->buf1 = (buf + length) & ~0x0fff;
1914                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1915                         packet->cross = 1;
1916
1917                 /* OUT uses multiple start-splits */
1918                 if (stream->bEndpointAddress & USB_DIR_IN)
1919                         continue;
1920                 length = (length + 187) / 188;
1921                 if (length > 1) /* BEGIN vs ALL */
1922                         length |= 1 << 3;
1923                 packet->buf1 |= length;
1924         }
1925 }
1926
1927 static int
1928 sitd_urb_transaction (
1929         struct ehci_iso_stream  *stream,
1930         struct ehci_hcd         *ehci,
1931         struct urb              *urb,
1932         gfp_t                   mem_flags
1933 )
1934 {
1935         struct ehci_sitd        *sitd;
1936         dma_addr_t              sitd_dma;
1937         int                     i;
1938         struct ehci_iso_sched   *iso_sched;
1939         unsigned long           flags;
1940
1941         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1942         if (iso_sched == NULL)
1943                 return -ENOMEM;
1944
1945         sitd_sched_init(ehci, iso_sched, stream, urb);
1946
1947         /* allocate/init sITDs */
1948         spin_lock_irqsave (&ehci->lock, flags);
1949         for (i = 0; i < urb->number_of_packets; i++) {
1950
1951                 /* NOTE:  for now, we don't try to handle wraparound cases
1952                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1953                  * means we never need two sitds for full speed packets.
1954                  */
1955
1956                 /* free_list.next might be cache-hot ... but maybe
1957                  * the HC caches it too. avoid that issue for now.
1958                  */
1959
1960                 /* prefer previously-allocated sitds */
1961                 if (!list_empty(&stream->free_list)) {
1962                         sitd = list_entry (stream->free_list.prev,
1963                                          struct ehci_sitd, sitd_list);
1964                         list_del (&sitd->sitd_list);
1965                         sitd_dma = sitd->sitd_dma;
1966                 } else {
1967                         spin_unlock_irqrestore (&ehci->lock, flags);
1968                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1969                                         &sitd_dma);
1970                         spin_lock_irqsave (&ehci->lock, flags);
1971                         if (!sitd) {
1972                                 iso_sched_free(stream, iso_sched);
1973                                 spin_unlock_irqrestore(&ehci->lock, flags);
1974                                 return -ENOMEM;
1975                         }
1976                 }
1977
1978                 memset (sitd, 0, sizeof *sitd);
1979                 sitd->sitd_dma = sitd_dma;
1980                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1981         }
1982
1983         /* temporarily store schedule info in hcpriv */
1984         urb->hcpriv = iso_sched;
1985         urb->error_count = 0;
1986
1987         spin_unlock_irqrestore (&ehci->lock, flags);
1988         return 0;
1989 }
1990
1991 /*-------------------------------------------------------------------------*/
1992
1993 static inline void
1994 sitd_patch(
1995         struct ehci_hcd         *ehci,
1996         struct ehci_iso_stream  *stream,
1997         struct ehci_sitd        *sitd,
1998         struct ehci_iso_sched   *iso_sched,
1999         unsigned                index
2000 )
2001 {
2002         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
2003         u64                     bufp = uf->bufp;
2004
2005         sitd->hw_next = EHCI_LIST_END(ehci);
2006         sitd->hw_fullspeed_ep = stream->address;
2007         sitd->hw_uframe = stream->splits;
2008         sitd->hw_results = uf->transaction;
2009         sitd->hw_backpointer = EHCI_LIST_END(ehci);
2010
2011         bufp = uf->bufp;
2012         sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
2013         sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
2014
2015         sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
2016         if (uf->cross)
2017                 bufp += 4096;
2018         sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
2019         sitd->index = index;
2020 }
2021
2022 static inline void
2023 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
2024 {
2025         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
2026         sitd->sitd_next = ehci->pshadow [frame];
2027         sitd->hw_next = ehci->periodic [frame];
2028         ehci->pshadow [frame].sitd = sitd;
2029         sitd->frame = frame;
2030         wmb ();
2031         ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
2032 }
2033
2034 /* fit urb's sitds into the selected schedule slot; activate as needed */
2035 static int
2036 sitd_link_urb (
2037         struct ehci_hcd         *ehci,
2038         struct urb              *urb,
2039         unsigned                mod,
2040         struct ehci_iso_stream  *stream
2041 )
2042 {
2043         int                     packet;
2044         unsigned                next_uframe;
2045         struct ehci_iso_sched   *sched = urb->hcpriv;
2046         struct ehci_sitd        *sitd;
2047
2048         next_uframe = stream->next_uframe;
2049
2050         if (list_empty(&stream->td_list)) {
2051                 /* usbfs ignores TT bandwidth */
2052                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2053                                 += stream->bandwidth;
2054                 ehci_vdbg (ehci,
2055                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2056                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2057                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2058                         (next_uframe >> 3) & (ehci->periodic_size - 1),
2059                         stream->interval, hc32_to_cpu(ehci, stream->splits));
2060         }
2061
2062         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2063                 if (ehci->amd_pll_fix == 1)
2064                         usb_amd_quirk_pll_disable();
2065         }
2066
2067         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2068
2069         /* fill sITDs frame by frame */
2070         for (packet = 0, sitd = NULL;
2071                         packet < urb->number_of_packets;
2072                         packet++) {
2073
2074                 /* ASSERT:  we have all necessary sitds */
2075                 BUG_ON (list_empty (&sched->td_list));
2076
2077                 /* ASSERT:  no itds for this endpoint in this frame */
2078
2079                 sitd = list_entry (sched->td_list.next,
2080                                 struct ehci_sitd, sitd_list);
2081                 list_move_tail (&sitd->sitd_list, &stream->td_list);
2082                 sitd->stream = iso_stream_get (stream);
2083                 sitd->urb = urb;
2084
2085                 sitd_patch(ehci, stream, sitd, sched, packet);
2086                 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2087                                 sitd);
2088
2089                 next_uframe += stream->interval << 3;
2090         }
2091         stream->next_uframe = next_uframe & (mod - 1);
2092
2093         /* don't need that schedule data any more */
2094         iso_sched_free (stream, sched);
2095         urb->hcpriv = NULL;
2096
2097         timer_action (ehci, TIMER_IO_WATCHDOG);
2098         return enable_periodic(ehci);
2099 }
2100
2101 /*-------------------------------------------------------------------------*/
2102
2103 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2104                                 | SITD_STS_XACT | SITD_STS_MMF)
2105
2106 /* Process and recycle a completed SITD.  Return true iff its urb completed,
2107  * and hence its completion callback probably added things to the hardware
2108  * schedule.
2109  *
2110  * Note that we carefully avoid recycling this descriptor until after any
2111  * completion callback runs, so that it won't be reused quickly.  That is,
2112  * assuming (a) no more than two urbs per frame on this endpoint, and also
2113  * (b) only this endpoint's completions submit URBs.  It seems some silicon
2114  * corrupts things if you reuse completed descriptors very quickly...
2115  */
2116 static unsigned
2117 sitd_complete (
2118         struct ehci_hcd         *ehci,
2119         struct ehci_sitd        *sitd
2120 ) {
2121         struct urb                              *urb = sitd->urb;
2122         struct usb_iso_packet_descriptor        *desc;
2123         u32                                     t;
2124         int                                     urb_index = -1;
2125         struct ehci_iso_stream                  *stream = sitd->stream;
2126         struct usb_device                       *dev;
2127         unsigned                                retval = false;
2128
2129         urb_index = sitd->index;
2130         desc = &urb->iso_frame_desc [urb_index];
2131         t = hc32_to_cpup(ehci, &sitd->hw_results);
2132
2133         /* report transfer status */
2134         if (t & SITD_ERRS) {
2135                 urb->error_count++;
2136                 if (t & SITD_STS_DBE)
2137                         desc->status = usb_pipein (urb->pipe)
2138                                 ? -ENOSR  /* hc couldn't read */
2139                                 : -ECOMM; /* hc couldn't write */
2140                 else if (t & SITD_STS_BABBLE)
2141                         desc->status = -EOVERFLOW;
2142                 else /* XACT, MMF, etc */
2143                         desc->status = -EPROTO;
2144         } else {
2145                 desc->status = 0;
2146                 desc->actual_length = desc->length - SITD_LENGTH(t);
2147                 urb->actual_length += desc->actual_length;
2148         }
2149
2150         /* handle completion now? */
2151         if ((urb_index + 1) != urb->number_of_packets)
2152                 goto done;
2153
2154         /* ASSERT: it's really the last sitd for this urb
2155         list_for_each_entry (sitd, &stream->td_list, sitd_list)
2156                 BUG_ON (sitd->urb == urb);
2157          */
2158
2159         /* give urb back to the driver; completion often (re)submits */
2160         dev = urb->dev;
2161         ehci_urb_done(ehci, urb, 0);
2162         retval = true;
2163         urb = NULL;
2164         (void) disable_periodic(ehci);
2165         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2166
2167         if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
2168                 if (ehci->amd_pll_fix == 1)
2169                         usb_amd_quirk_pll_enable();
2170         }
2171
2172         if (list_is_singular(&stream->td_list)) {
2173                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2174                                 -= stream->bandwidth;
2175                 ehci_vdbg (ehci,
2176                         "deschedule devp %s ep%d%s-iso\n",
2177                         dev->devpath, stream->bEndpointAddress & 0x0f,
2178                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2179         }
2180         iso_stream_put (ehci, stream);
2181
2182 done:
2183         sitd->urb = NULL;
2184         if (ehci->clock_frame != sitd->frame) {
2185                 /* OK to recycle this SITD now. */
2186                 sitd->stream = NULL;
2187                 list_move(&sitd->sitd_list, &stream->free_list);
2188                 iso_stream_put(ehci, stream);
2189         } else {
2190                 /* HW might remember this SITD, so we can't recycle it yet.
2191                  * Move it to a safe place until a new frame starts.
2192                  */
2193                 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2194                 if (stream->refcount == 2) {
2195                         /* If iso_stream_put() were called here, stream
2196                          * would be freed.  Instead, just prevent reuse.
2197                          */
2198                         stream->ep->hcpriv = NULL;
2199                         stream->ep = NULL;
2200                 }
2201         }
2202         return retval;
2203 }
2204
2205
2206 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2207         gfp_t mem_flags)
2208 {
2209         int                     status = -EINVAL;
2210         unsigned long           flags;
2211         struct ehci_iso_stream  *stream;
2212
2213         /* Get iso_stream head */
2214         stream = iso_stream_find (ehci, urb);
2215         if (stream == NULL) {
2216                 ehci_dbg (ehci, "can't get iso stream\n");
2217                 return -ENOMEM;
2218         }
2219         if (urb->interval != stream->interval) {
2220                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2221                         stream->interval, urb->interval);
2222                 goto done;
2223         }
2224
2225 #ifdef EHCI_URB_TRACE
2226         ehci_dbg (ehci,
2227                 "submit %p dev%s ep%d%s-iso len %d\n",
2228                 urb, urb->dev->devpath,
2229                 usb_pipeendpoint (urb->pipe),
2230                 usb_pipein (urb->pipe) ? "in" : "out",
2231                 urb->transfer_buffer_length);
2232 #endif
2233
2234         /* allocate SITDs */
2235         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2236         if (status < 0) {
2237                 ehci_dbg (ehci, "can't init sitds\n");
2238                 goto done;
2239         }
2240
2241         /* schedule ... need to lock */
2242         spin_lock_irqsave (&ehci->lock, flags);
2243         if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2244                 status = -ESHUTDOWN;
2245                 goto done_not_linked;
2246         }
2247         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2248         if (unlikely(status))
2249                 goto done_not_linked;
2250         status = iso_stream_schedule(ehci, urb, stream);
2251         if (status == 0)
2252                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2253         else
2254                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2255 done_not_linked:
2256         spin_unlock_irqrestore (&ehci->lock, flags);
2257
2258 done:
2259         if (status < 0)
2260                 iso_stream_put (ehci, stream);
2261         return status;
2262 }
2263
2264 /*-------------------------------------------------------------------------*/
2265
2266 static void free_cached_lists(struct ehci_hcd *ehci)
2267 {
2268         struct ehci_itd *itd, *n;
2269         struct ehci_sitd *sitd, *sn;
2270
2271         list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2272                 struct ehci_iso_stream  *stream = itd->stream;
2273                 itd->stream = NULL;
2274                 list_move(&itd->itd_list, &stream->free_list);
2275                 iso_stream_put(ehci, stream);
2276         }
2277
2278         list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2279                 struct ehci_iso_stream  *stream = sitd->stream;
2280                 sitd->stream = NULL;
2281                 list_move(&sitd->sitd_list, &stream->free_list);
2282                 iso_stream_put(ehci, stream);
2283         }
2284 }
2285
2286 /*-------------------------------------------------------------------------*/
2287
2288 static void
2289 scan_periodic (struct ehci_hcd *ehci)
2290 {
2291         unsigned        now_uframe, frame, clock, clock_frame, mod;
2292         unsigned        modified;
2293
2294         mod = ehci->periodic_size << 3;
2295
2296         /*
2297          * When running, scan from last scan point up to "now"
2298          * else clean up by scanning everything that's left.
2299          * Touches as few pages as possible:  cache-friendly.
2300          */
2301         now_uframe = ehci->next_uframe;
2302         if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2303                 clock = ehci_read_frame_index(ehci);
2304                 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2305         } else  {
2306                 clock = now_uframe + mod - 1;
2307                 clock_frame = -1;
2308         }
2309         if (ehci->clock_frame != clock_frame) {
2310                 free_cached_lists(ehci);
2311                 ehci->clock_frame = clock_frame;
2312         }
2313         clock &= mod - 1;
2314         clock_frame = clock >> 3;
2315         ++ehci->periodic_stamp;
2316
2317         for (;;) {
2318                 union ehci_shadow       q, *q_p;
2319                 __hc32                  type, *hw_p;
2320                 unsigned                incomplete = false;
2321
2322                 frame = now_uframe >> 3;
2323
2324 restart:
2325                 /* scan each element in frame's queue for completions */
2326                 q_p = &ehci->pshadow [frame];
2327                 hw_p = &ehci->periodic [frame];
2328                 q.ptr = q_p->ptr;
2329                 type = Q_NEXT_TYPE(ehci, *hw_p);
2330                 modified = 0;
2331
2332                 while (q.ptr != NULL) {
2333                         unsigned                uf;
2334                         union ehci_shadow       temp;
2335                         int                     live;
2336
2337                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2338                         switch (hc32_to_cpu(ehci, type)) {
2339                         case Q_TYPE_QH:
2340                                 /* handle any completions */
2341                                 temp.qh = qh_get (q.qh);
2342                                 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2343                                 q = q.qh->qh_next;
2344                                 if (temp.qh->stamp != ehci->periodic_stamp) {
2345                                         modified = qh_completions(ehci, temp.qh);
2346                                         if (!modified)
2347                                                 temp.qh->stamp = ehci->periodic_stamp;
2348                                         if (unlikely(list_empty(&temp.qh->qtd_list) ||
2349                                                         temp.qh->needs_rescan))
2350                                                 intr_deschedule(ehci, temp.qh);
2351                                 }
2352                                 qh_put (temp.qh);
2353                                 break;
2354                         case Q_TYPE_FSTN:
2355                                 /* for "save place" FSTNs, look at QH entries
2356                                  * in the previous frame for completions.
2357                                  */
2358                                 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2359                                         dbg ("ignoring completions from FSTNs");
2360                                 }
2361                                 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2362                                 q = q.fstn->fstn_next;
2363                                 break;
2364                         case Q_TYPE_ITD:
2365                                 /* If this ITD is still active, leave it for
2366                                  * later processing ... check the next entry.
2367                                  * No need to check for activity unless the
2368                                  * frame is current.
2369                                  */
2370                                 if (frame == clock_frame && live) {
2371                                         rmb();
2372                                         for (uf = 0; uf < 8; uf++) {
2373                                                 if (q.itd->hw_transaction[uf] &
2374                                                             ITD_ACTIVE(ehci))
2375                                                         break;
2376                                         }
2377                                         if (uf < 8) {
2378                                                 incomplete = true;
2379                                                 q_p = &q.itd->itd_next;
2380                                                 hw_p = &q.itd->hw_next;
2381                                                 type = Q_NEXT_TYPE(ehci,
2382                                                         q.itd->hw_next);
2383                                                 q = *q_p;
2384                                                 break;
2385                                         }
2386                                 }
2387
2388                                 /* Take finished ITDs out of the schedule
2389                                  * and process them:  recycle, maybe report
2390                                  * URB completion.  HC won't cache the
2391                                  * pointer for much longer, if at all.
2392                                  */
2393                                 *q_p = q.itd->itd_next;
2394                                 if (!ehci->use_dummy_qh ||
2395                                     q.itd->hw_next != EHCI_LIST_END(ehci))
2396                                         *hw_p = q.itd->hw_next;
2397                                 else
2398                                         *hw_p = ehci->dummy->qh_dma;
2399                                 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2400                                 wmb();
2401                                 modified = itd_complete (ehci, q.itd);
2402                                 q = *q_p;
2403                                 break;
2404                         case Q_TYPE_SITD:
2405                                 /* If this SITD is still active, leave it for
2406                                  * later processing ... check the next entry.
2407                                  * No need to check for activity unless the
2408                                  * frame is current.
2409                                  */
2410                                 if (((frame == clock_frame) ||
2411                                      (((frame + 1) & (ehci->periodic_size - 1))
2412                                       == clock_frame))
2413                                     && live
2414                                     && (q.sitd->hw_results &
2415                                         SITD_ACTIVE(ehci))) {
2416
2417                                         incomplete = true;
2418                                         q_p = &q.sitd->sitd_next;
2419                                         hw_p = &q.sitd->hw_next;
2420                                         type = Q_NEXT_TYPE(ehci,
2421                                                         q.sitd->hw_next);
2422                                         q = *q_p;
2423                                         break;
2424                                 }
2425
2426                                 /* Take finished SITDs out of the schedule
2427                                  * and process them:  recycle, maybe report
2428                                  * URB completion.
2429                                  */
2430                                 *q_p = q.sitd->sitd_next;
2431                                 if (!ehci->use_dummy_qh ||
2432                                     q.sitd->hw_next != EHCI_LIST_END(ehci))
2433                                         *hw_p = q.sitd->hw_next;
2434                                 else
2435                                         *hw_p = ehci->dummy->qh_dma;
2436                                 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2437                                 wmb();
2438                                 modified = sitd_complete (ehci, q.sitd);
2439                                 q = *q_p;
2440                                 break;
2441                         default:
2442                                 dbg ("corrupt type %d frame %d shadow %p",
2443                                         type, frame, q.ptr);
2444                                 // BUG ();
2445                                 q.ptr = NULL;
2446                         }
2447
2448                         /* assume completion callbacks modify the queue */
2449                         if (unlikely (modified)) {
2450                                 if (likely(ehci->periodic_sched > 0))
2451                                         goto restart;
2452                                 /* short-circuit this scan */
2453                                 now_uframe = clock;
2454                                 break;
2455                         }
2456                 }
2457
2458                 /* If we can tell we caught up to the hardware, stop now.
2459                  * We can't advance our scan without collecting the ISO
2460                  * transfers that are still pending in this frame.
2461                  */
2462                 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2463                         ehci->next_uframe = now_uframe;
2464                         break;
2465                 }
2466
2467                 // FIXME:  this assumes we won't get lapped when
2468                 // latencies climb; that should be rare, but...
2469                 // detect it, and just go all the way around.
2470                 // FLR might help detect this case, so long as latencies
2471                 // don't exceed periodic_size msec (default 1.024 sec).
2472
2473                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2474
2475                 if (now_uframe == clock) {
2476                         unsigned        now;
2477
2478                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2479                                         || ehci->periodic_sched == 0)
2480                                 break;
2481                         ehci->next_uframe = now_uframe;
2482                         now = ehci_read_frame_index(ehci) & (mod - 1);
2483                         if (now_uframe == now)
2484                                 break;
2485
2486                         /* rescan the rest of this frame, then ... */
2487                         clock = now;
2488                         clock_frame = clock >> 3;
2489                         if (ehci->clock_frame != clock_frame) {
2490                                 free_cached_lists(ehci);
2491                                 ehci->clock_frame = clock_frame;
2492                                 ++ehci->periodic_stamp;
2493                         }
2494                 } else {
2495                         now_uframe++;
2496                         now_uframe &= mod - 1;
2497                 }
2498         }
2499 }