2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
82 unsigned long segment_offset;
84 if (!seg || !trb || trb < seg->trbs)
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
90 return seg->dma + (segment_offset * sizeof(*trb));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
103 return trb->link.control & LINK_TOGGLE;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
119 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
134 if (last_trb(xhci, ring, *seg, *trb)) {
136 *trb = ((*seg)->trbs);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
161 (unsigned int) ring->cycle_state);
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168 if (ring == xhci->event_ring)
169 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
170 else if (ring == xhci->cmd_ring)
171 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
173 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
177 * See Cycle bit rules. SW is the consumer for the event ring only.
178 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
180 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
181 * chain bit is set), then set the chain bit in all the following link TRBs.
182 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
183 * have their chain bit cleared (so that each Link TRB is a separate TD).
185 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
186 * set, but other sections talk about dealing with the chain bit set. This was
187 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
188 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
190 * @more_trbs_coming: Will you enqueue more TRBs before calling
191 * prepare_transfer()?
193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
194 bool consumer, bool more_trbs_coming)
197 union xhci_trb *next;
198 unsigned long long addr;
200 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
201 next = ++(ring->enqueue);
204 /* Update the dequeue pointer further if that was a link TRB or we're at
205 * the end of an event ring segment (which doesn't have link TRBS)
207 while (last_trb(xhci, ring, ring->enq_seg, next)) {
209 if (ring != xhci->event_ring) {
211 * If the caller doesn't plan on enqueueing more
212 * TDs before ringing the doorbell, then we
213 * don't want to give the link TRB to the
214 * hardware just yet. We'll give the link TRB
215 * back in prepare_ring() just before we enqueue
216 * the TD at the top of the ring.
218 if (!chain && !more_trbs_coming)
221 /* If we're not dealing with 0.95 hardware,
222 * carry over the chain bit of the previous TRB
223 * (which may mean the chain bit is cleared).
225 if (!xhci_link_trb_quirk(xhci)) {
226 next->link.control &= ~TRB_CHAIN;
227 next->link.control |= chain;
229 /* Give this link TRB to the hardware */
231 next->link.control ^= TRB_CYCLE;
233 /* Toggle the cycle bit after the last ring segment. */
234 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
235 ring->cycle_state = (ring->cycle_state ? 0 : 1);
237 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
239 (unsigned int) ring->cycle_state);
242 ring->enq_seg = ring->enq_seg->next;
243 ring->enqueue = ring->enq_seg->trbs;
244 next = ring->enqueue;
246 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
247 if (ring == xhci->event_ring)
248 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
249 else if (ring == xhci->cmd_ring)
250 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
252 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
256 * Check to see if there's room to enqueue num_trbs on the ring. See rules
258 * FIXME: this would be simpler and faster if we just kept track of the number
259 * of free TRBs in a ring.
261 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
262 unsigned int num_trbs)
265 union xhci_trb *enq = ring->enqueue;
266 struct xhci_segment *enq_seg = ring->enq_seg;
267 struct xhci_segment *cur_seg;
268 unsigned int left_on_ring;
270 /* If we are currently pointing to a link TRB, advance the
271 * enqueue pointer before checking for space */
272 while (last_trb(xhci, ring, enq_seg, enq)) {
273 enq_seg = enq_seg->next;
277 /* Check if ring is empty */
278 if (enq == ring->dequeue) {
279 /* Can't use link trbs */
280 left_on_ring = TRBS_PER_SEGMENT - 1;
281 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
282 cur_seg = cur_seg->next)
283 left_on_ring += TRBS_PER_SEGMENT - 1;
285 /* Always need one TRB free in the ring. */
287 if (num_trbs > left_on_ring) {
288 xhci_warn(xhci, "Not enough room on ring; "
289 "need %u TRBs, %u TRBs left\n",
290 num_trbs, left_on_ring);
295 /* Make sure there's an extra empty TRB available */
296 for (i = 0; i <= num_trbs; ++i) {
297 if (enq == ring->dequeue)
300 while (last_trb(xhci, ring, enq_seg, enq)) {
301 enq_seg = enq_seg->next;
308 /* Ring the host controller doorbell after placing a command on the ring */
309 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
311 xhci_dbg(xhci, "// Ding dong!\n");
312 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
313 /* Flush PCI posted writes */
314 xhci_readl(xhci, &xhci->dba->doorbell[0]);
317 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
318 unsigned int slot_id,
319 unsigned int ep_index,
320 unsigned int stream_id)
322 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
323 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
324 unsigned int ep_state = ep->ep_state;
326 /* Don't ring the doorbell for this endpoint if there are pending
327 * cancellations because we don't want to interrupt processing.
328 * We don't want to restart any stream rings if there's a set dequeue
329 * pointer command pending because the device can choose to start any
330 * stream once the endpoint is on the HW schedule.
331 * FIXME - check all the stream rings for pending cancellations.
333 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
334 (ep_state & EP_HALTED))
336 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
337 /* The CPU has better things to do at this point than wait for a
338 * write-posting flush. It'll get there soon enough.
342 /* Ring the doorbell for any rings with pending URBs */
343 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
344 unsigned int slot_id,
345 unsigned int ep_index)
347 unsigned int stream_id;
348 struct xhci_virt_ep *ep;
350 ep = &xhci->devs[slot_id]->eps[ep_index];
352 /* A ring has pending URBs if its TD list is not empty */
353 if (!(ep->ep_state & EP_HAS_STREAMS)) {
354 if (!(list_empty(&ep->ring->td_list)))
355 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
359 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
361 struct xhci_stream_info *stream_info = ep->stream_info;
362 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
363 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
369 * Find the segment that trb is in. Start searching in start_seg.
370 * If we must move past a segment that has a link TRB with a toggle cycle state
371 * bit set, then we will toggle the value pointed at by cycle_state.
373 static struct xhci_segment *find_trb_seg(
374 struct xhci_segment *start_seg,
375 union xhci_trb *trb, int *cycle_state)
377 struct xhci_segment *cur_seg = start_seg;
378 struct xhci_generic_trb *generic_trb;
380 while (cur_seg->trbs > trb ||
381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
383 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
384 TRB_TYPE(TRB_LINK) &&
385 (generic_trb->field[3] & LINK_TOGGLE))
386 *cycle_state = ~(*cycle_state) & 0x1;
387 cur_seg = cur_seg->next;
388 if (cur_seg == start_seg)
389 /* Looped over the entire list. Oops! */
396 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
397 unsigned int slot_id, unsigned int ep_index,
398 unsigned int stream_id)
400 struct xhci_virt_ep *ep;
402 ep = &xhci->devs[slot_id]->eps[ep_index];
403 /* Common case: no streams */
404 if (!(ep->ep_state & EP_HAS_STREAMS))
407 if (stream_id == 0) {
409 "WARN: Slot ID %u, ep index %u has streams, "
410 "but URB has no stream ID.\n",
415 if (stream_id < ep->stream_info->num_streams)
416 return ep->stream_info->stream_rings[stream_id];
419 "WARN: Slot ID %u, ep index %u has "
420 "stream IDs 1 to %u allocated, "
421 "but stream ID %u is requested.\n",
423 ep->stream_info->num_streams - 1,
428 /* Get the right ring for the given URB.
429 * If the endpoint supports streams, boundary check the URB's stream ID.
430 * If the endpoint doesn't support streams, return the singular endpoint ring.
432 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
435 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
436 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
440 * Move the xHC's endpoint ring dequeue pointer past cur_td.
441 * Record the new state of the xHC's endpoint ring dequeue segment,
442 * dequeue pointer, and new consumer cycle state in state.
443 * Update our internal representation of the ring's dequeue pointer.
445 * We do this in three jumps:
446 * - First we update our new ring state to be the same as when the xHC stopped.
447 * - Then we traverse the ring to find the segment that contains
448 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
449 * any link TRBs with the toggle cycle bit set.
450 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
451 * if we've moved it past a link TRB with the toggle cycle bit set.
453 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
454 unsigned int slot_id, unsigned int ep_index,
455 unsigned int stream_id, struct xhci_td *cur_td,
456 struct xhci_dequeue_state *state)
458 struct xhci_virt_device *dev = xhci->devs[slot_id];
459 struct xhci_ring *ep_ring;
460 struct xhci_generic_trb *trb;
461 struct xhci_ep_ctx *ep_ctx;
464 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
465 ep_index, stream_id);
467 xhci_warn(xhci, "WARN can't find new dequeue state "
468 "for invalid stream ID %u.\n",
472 state->new_cycle_state = 0;
473 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
474 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
475 dev->eps[ep_index].stopped_trb,
476 &state->new_cycle_state);
477 if (!state->new_deq_seg) {
482 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
483 xhci_dbg(xhci, "Finding endpoint context\n");
484 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
485 state->new_cycle_state = 0x1 & ep_ctx->deq;
487 state->new_deq_ptr = cur_td->last_trb;
488 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
489 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
491 &state->new_cycle_state);
492 if (!state->new_deq_seg) {
497 trb = &state->new_deq_ptr->generic;
498 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
499 (trb->field[3] & LINK_TOGGLE))
500 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
501 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
503 /* Don't update the ring cycle state for the producer (us). */
504 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
506 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
507 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
508 (unsigned long long) addr);
509 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
510 ep_ring->dequeue = state->new_deq_ptr;
511 ep_ring->deq_seg = state->new_deq_seg;
514 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
515 struct xhci_td *cur_td)
517 struct xhci_segment *cur_seg;
518 union xhci_trb *cur_trb;
520 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
522 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
523 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
524 TRB_TYPE(TRB_LINK)) {
525 /* Unchain any chained Link TRBs, but
526 * leave the pointers intact.
528 cur_trb->generic.field[3] &= ~TRB_CHAIN;
529 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
530 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
531 "in seg %p (0x%llx dma)\n",
533 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
535 (unsigned long long)cur_seg->dma);
537 cur_trb->generic.field[0] = 0;
538 cur_trb->generic.field[1] = 0;
539 cur_trb->generic.field[2] = 0;
540 /* Preserve only the cycle bit of this TRB */
541 cur_trb->generic.field[3] &= TRB_CYCLE;
542 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
543 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
544 "in seg %p (0x%llx dma)\n",
546 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
548 (unsigned long long)cur_seg->dma);
550 if (cur_trb == cur_td->last_trb)
555 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
556 unsigned int ep_index, unsigned int stream_id,
557 struct xhci_segment *deq_seg,
558 union xhci_trb *deq_ptr, u32 cycle_state);
560 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
561 unsigned int slot_id, unsigned int ep_index,
562 unsigned int stream_id,
563 struct xhci_dequeue_state *deq_state)
565 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
567 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
568 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
569 deq_state->new_deq_seg,
570 (unsigned long long)deq_state->new_deq_seg->dma,
571 deq_state->new_deq_ptr,
572 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
573 deq_state->new_cycle_state);
574 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
575 deq_state->new_deq_seg,
576 deq_state->new_deq_ptr,
577 (u32) deq_state->new_cycle_state);
578 /* Stop the TD queueing code from ringing the doorbell until
579 * this command completes. The HC won't set the dequeue pointer
580 * if the ring is running, and ringing the doorbell starts the
583 ep->ep_state |= SET_DEQ_PENDING;
586 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
587 struct xhci_virt_ep *ep)
589 ep->ep_state &= ~EP_HALT_PENDING;
590 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
591 * timer is running on another CPU, we don't decrement stop_cmds_pending
592 * (since we didn't successfully stop the watchdog timer).
594 if (del_timer(&ep->stop_cmd_timer))
595 ep->stop_cmds_pending--;
598 /* Must be called with xhci->lock held in interrupt context */
599 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
600 struct xhci_td *cur_td, int status, char *adjective)
602 struct usb_hcd *hcd = xhci_to_hcd(xhci);
604 struct urb_priv *urb_priv;
607 urb_priv = urb->hcpriv;
610 /* Only giveback urb when this is the last td in urb */
611 if (urb_priv->td_cnt == urb_priv->length) {
612 usb_hcd_unlink_urb_from_ep(hcd, urb);
613 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
615 spin_unlock(&xhci->lock);
616 usb_hcd_giveback_urb(hcd, urb, status);
617 xhci_urb_free_priv(xhci, urb_priv);
618 spin_lock(&xhci->lock);
619 xhci_dbg(xhci, "%s URB given back\n", adjective);
624 * When we get a command completion for a Stop Endpoint Command, we need to
625 * unlink any cancelled TDs from the ring. There are two ways to do that:
627 * 1. If the HW was in the middle of processing the TD that needs to be
628 * cancelled, then we must move the ring's dequeue pointer past the last TRB
629 * in the TD with a Set Dequeue Pointer Command.
630 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
631 * bit cleared) so that the HW will skip over them.
633 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
634 union xhci_trb *trb, struct xhci_event_cmd *event)
636 unsigned int slot_id;
637 unsigned int ep_index;
638 struct xhci_virt_device *virt_dev;
639 struct xhci_ring *ep_ring;
640 struct xhci_virt_ep *ep;
641 struct list_head *entry;
642 struct xhci_td *cur_td = NULL;
643 struct xhci_td *last_unlinked_td;
645 struct xhci_dequeue_state deq_state;
647 if (unlikely(TRB_TO_SUSPEND_PORT(
648 xhci->cmd_ring->dequeue->generic.field[3]))) {
649 slot_id = TRB_TO_SLOT_ID(
650 xhci->cmd_ring->dequeue->generic.field[3]);
651 virt_dev = xhci->devs[slot_id];
653 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
656 xhci_warn(xhci, "Stop endpoint command "
657 "completion for disabled slot %u\n",
662 memset(&deq_state, 0, sizeof(deq_state));
663 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
664 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
665 ep = &xhci->devs[slot_id]->eps[ep_index];
667 if (list_empty(&ep->cancelled_td_list)) {
668 xhci_stop_watchdog_timer_in_irq(xhci, ep);
669 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
673 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
674 * We have the xHCI lock, so nothing can modify this list until we drop
675 * it. We're also in the event handler, so we can't get re-interrupted
676 * if another Stop Endpoint command completes
678 list_for_each(entry, &ep->cancelled_td_list) {
679 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
680 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
682 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
683 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
685 /* This shouldn't happen unless a driver is mucking
686 * with the stream ID after submission. This will
687 * leave the TD on the hardware ring, and the hardware
688 * will try to execute it, and may access a buffer
689 * that has already been freed. In the best case, the
690 * hardware will execute it, and the event handler will
691 * ignore the completion event for that TD, since it was
692 * removed from the td_list for that endpoint. In
693 * short, don't muck with the stream ID after
696 xhci_warn(xhci, "WARN Cancelled URB %p "
697 "has invalid stream ID %u.\n",
699 cur_td->urb->stream_id);
700 goto remove_finished_td;
703 * If we stopped on the TD we need to cancel, then we have to
704 * move the xHC endpoint ring dequeue pointer past this TD.
706 if (cur_td == ep->stopped_td)
707 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
708 cur_td->urb->stream_id,
711 td_to_noop(xhci, ep_ring, cur_td);
714 * The event handler won't see a completion for this TD anymore,
715 * so remove it from the endpoint ring's TD list. Keep it in
716 * the cancelled TD list for URB completion later.
718 list_del(&cur_td->td_list);
720 last_unlinked_td = cur_td;
721 xhci_stop_watchdog_timer_in_irq(xhci, ep);
723 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
724 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
725 xhci_queue_new_dequeue_state(xhci,
727 ep->stopped_td->urb->stream_id,
729 xhci_ring_cmd_db(xhci);
731 /* Otherwise ring the doorbell(s) to restart queued transfers */
732 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
734 ep->stopped_td = NULL;
735 ep->stopped_trb = NULL;
738 * Drop the lock and complete the URBs in the cancelled TD list.
739 * New TDs to be cancelled might be added to the end of the list before
740 * we can complete all the URBs for the TDs we already unlinked.
741 * So stop when we've completed the URB for the last TD we unlinked.
744 cur_td = list_entry(ep->cancelled_td_list.next,
745 struct xhci_td, cancelled_td_list);
746 list_del(&cur_td->cancelled_td_list);
748 /* Clean up the cancelled URB */
749 /* Doesn't matter what we pass for status, since the core will
750 * just overwrite it (because the URB has been unlinked).
752 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
754 /* Stop processing the cancelled list if the watchdog timer is
757 if (xhci->xhc_state & XHCI_STATE_DYING)
759 } while (cur_td != last_unlinked_td);
761 /* Return to the event handler with xhci->lock re-acquired */
764 /* Watchdog timer function for when a stop endpoint command fails to complete.
765 * In this case, we assume the host controller is broken or dying or dead. The
766 * host may still be completing some other events, so we have to be careful to
767 * let the event ring handler and the URB dequeueing/enqueueing functions know
768 * through xhci->state.
770 * The timer may also fire if the host takes a very long time to respond to the
771 * command, and the stop endpoint command completion handler cannot delete the
772 * timer before the timer function is called. Another endpoint cancellation may
773 * sneak in before the timer function can grab the lock, and that may queue
774 * another stop endpoint command and add the timer back. So we cannot use a
775 * simple flag to say whether there is a pending stop endpoint command for a
776 * particular endpoint.
778 * Instead we use a combination of that flag and a counter for the number of
779 * pending stop endpoint commands. If the timer is the tail end of the last
780 * stop endpoint command, and the endpoint's command is still pending, we assume
783 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
785 struct xhci_hcd *xhci;
786 struct xhci_virt_ep *ep;
787 struct xhci_virt_ep *temp_ep;
788 struct xhci_ring *ring;
789 struct xhci_td *cur_td;
792 ep = (struct xhci_virt_ep *) arg;
795 spin_lock(&xhci->lock);
797 ep->stop_cmds_pending--;
798 if (xhci->xhc_state & XHCI_STATE_DYING) {
799 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
800 "xHCI as DYING, exiting.\n");
801 spin_unlock(&xhci->lock);
804 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
805 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
807 spin_unlock(&xhci->lock);
811 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
812 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
813 /* Oops, HC is dead or dying or at least not responding to the stop
816 xhci->xhc_state |= XHCI_STATE_DYING;
817 /* Disable interrupts from the host controller and start halting it */
819 spin_unlock(&xhci->lock);
821 ret = xhci_halt(xhci);
823 spin_lock(&xhci->lock);
825 /* This is bad; the host is not responding to commands and it's
826 * not allowing itself to be halted. At least interrupts are
827 * disabled, so we can set HC_STATE_HALT and notify the
828 * USB core. But if we call usb_hc_died(), it will attempt to
829 * disconnect all device drivers under this host. Those
830 * disconnect() methods will wait for all URBs to be unlinked,
831 * so we must complete them.
833 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
834 xhci_warn(xhci, "Completing active URBs anyway.\n");
835 /* We could turn all TDs on the rings to no-ops. This won't
836 * help if the host has cached part of the ring, and is slow if
837 * we want to preserve the cycle bit. Skip it and hope the host
838 * doesn't touch the memory.
841 for (i = 0; i < MAX_HC_SLOTS; i++) {
844 for (j = 0; j < 31; j++) {
845 temp_ep = &xhci->devs[i]->eps[j];
846 ring = temp_ep->ring;
849 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
850 "ep index %u\n", i, j);
851 while (!list_empty(&ring->td_list)) {
852 cur_td = list_first_entry(&ring->td_list,
855 list_del(&cur_td->td_list);
856 if (!list_empty(&cur_td->cancelled_td_list))
857 list_del(&cur_td->cancelled_td_list);
858 xhci_giveback_urb_in_irq(xhci, cur_td,
859 -ESHUTDOWN, "killed");
861 while (!list_empty(&temp_ep->cancelled_td_list)) {
862 cur_td = list_first_entry(
863 &temp_ep->cancelled_td_list,
866 list_del(&cur_td->cancelled_td_list);
867 xhci_giveback_urb_in_irq(xhci, cur_td,
868 -ESHUTDOWN, "killed");
872 spin_unlock(&xhci->lock);
873 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
874 xhci_dbg(xhci, "Calling usb_hc_died()\n");
875 usb_hc_died(xhci_to_hcd(xhci));
876 xhci_dbg(xhci, "xHCI host controller is dead.\n");
880 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
881 * we need to clear the set deq pending flag in the endpoint ring state, so that
882 * the TD queueing code can ring the doorbell again. We also need to ring the
883 * endpoint doorbell to restart the ring, but only if there aren't more
884 * cancellations pending.
886 static void handle_set_deq_completion(struct xhci_hcd *xhci,
887 struct xhci_event_cmd *event,
890 unsigned int slot_id;
891 unsigned int ep_index;
892 unsigned int stream_id;
893 struct xhci_ring *ep_ring;
894 struct xhci_virt_device *dev;
895 struct xhci_ep_ctx *ep_ctx;
896 struct xhci_slot_ctx *slot_ctx;
898 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
899 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
900 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
901 dev = xhci->devs[slot_id];
903 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
905 xhci_warn(xhci, "WARN Set TR deq ptr command for "
906 "freed stream ID %u\n",
908 /* XXX: Harmless??? */
909 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
913 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
914 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
916 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
917 unsigned int ep_state;
918 unsigned int slot_state;
920 switch (GET_COMP_CODE(event->status)) {
922 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
923 "of stream ID configuration\n");
926 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
927 "to incorrect slot or ep state.\n");
928 ep_state = ep_ctx->ep_info;
929 ep_state &= EP_STATE_MASK;
930 slot_state = slot_ctx->dev_state;
931 slot_state = GET_SLOT_STATE(slot_state);
932 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
933 slot_state, ep_state);
936 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
937 "slot %u was not enabled.\n", slot_id);
940 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
941 "completion code of %u.\n",
942 GET_COMP_CODE(event->status));
945 /* OK what do we do now? The endpoint state is hosed, and we
946 * should never get to this point if the synchronization between
947 * queueing, and endpoint state are correct. This might happen
948 * if the device gets disconnected after we've finished
949 * cancelling URBs, which might not be an error...
952 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
956 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
957 /* Restart any rings with pending URBs */
958 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
961 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
962 struct xhci_event_cmd *event,
966 unsigned int ep_index;
968 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
969 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
970 /* This command will only fail if the endpoint wasn't halted,
973 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
974 (unsigned int) GET_COMP_CODE(event->status));
976 /* HW with the reset endpoint quirk needs to have a configure endpoint
977 * command complete before the endpoint can be used. Queue that here
978 * because the HW can't handle two commands being queued in a row.
980 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
981 xhci_dbg(xhci, "Queueing configure endpoint command\n");
982 xhci_queue_configure_endpoint(xhci,
983 xhci->devs[slot_id]->in_ctx->dma, slot_id,
985 xhci_ring_cmd_db(xhci);
987 /* Clear our internal halted state and restart the ring(s) */
988 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
989 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
993 /* Check to see if a command in the device's command queue matches this one.
994 * Signal the completion or free the command, and return 1. Return 0 if the
995 * completed command isn't at the head of the command list.
997 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
998 struct xhci_virt_device *virt_dev,
999 struct xhci_event_cmd *event)
1001 struct xhci_command *command;
1003 if (list_empty(&virt_dev->cmd_list))
1006 command = list_entry(virt_dev->cmd_list.next,
1007 struct xhci_command, cmd_list);
1008 if (xhci->cmd_ring->dequeue != command->command_trb)
1012 GET_COMP_CODE(event->status);
1013 list_del(&command->cmd_list);
1014 if (command->completion)
1015 complete(command->completion);
1017 xhci_free_command(xhci, command);
1021 static void handle_cmd_completion(struct xhci_hcd *xhci,
1022 struct xhci_event_cmd *event)
1024 int slot_id = TRB_TO_SLOT_ID(event->flags);
1026 dma_addr_t cmd_dequeue_dma;
1027 struct xhci_input_control_ctx *ctrl_ctx;
1028 struct xhci_virt_device *virt_dev;
1029 unsigned int ep_index;
1030 struct xhci_ring *ep_ring;
1031 unsigned int ep_state;
1033 cmd_dma = event->cmd_trb;
1034 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1035 xhci->cmd_ring->dequeue);
1036 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1037 if (cmd_dequeue_dma == 0) {
1038 xhci->error_bitmask |= 1 << 4;
1041 /* Does the DMA address match our internal dequeue pointer address? */
1042 if (cmd_dma != (u64) cmd_dequeue_dma) {
1043 xhci->error_bitmask |= 1 << 5;
1046 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1047 case TRB_TYPE(TRB_ENABLE_SLOT):
1048 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1049 xhci->slot_id = slot_id;
1052 complete(&xhci->addr_dev);
1054 case TRB_TYPE(TRB_DISABLE_SLOT):
1055 if (xhci->devs[slot_id])
1056 xhci_free_virt_device(xhci, slot_id);
1058 case TRB_TYPE(TRB_CONFIG_EP):
1059 virt_dev = xhci->devs[slot_id];
1060 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1063 * Configure endpoint commands can come from the USB core
1064 * configuration or alt setting changes, or because the HW
1065 * needed an extra configure endpoint command after a reset
1066 * endpoint command or streams were being configured.
1067 * If the command was for a halted endpoint, the xHCI driver
1068 * is not waiting on the configure endpoint command.
1070 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1072 /* Input ctx add_flags are the endpoint index plus one */
1073 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1074 /* A usb_set_interface() call directly after clearing a halted
1075 * condition may race on this quirky hardware. Not worth
1076 * worrying about, since this is prototype hardware. Not sure
1077 * if this will work for streams, but streams support was
1078 * untested on this prototype.
1080 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1081 ep_index != (unsigned int) -1 &&
1082 ctrl_ctx->add_flags - SLOT_FLAG ==
1083 ctrl_ctx->drop_flags) {
1084 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1085 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1086 if (!(ep_state & EP_HALTED))
1087 goto bandwidth_change;
1088 xhci_dbg(xhci, "Completed config ep cmd - "
1089 "last ep index = %d, state = %d\n",
1090 ep_index, ep_state);
1091 /* Clear internal halted state and restart ring(s) */
1092 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1094 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1098 xhci_dbg(xhci, "Completed config ep cmd\n");
1099 xhci->devs[slot_id]->cmd_status =
1100 GET_COMP_CODE(event->status);
1101 complete(&xhci->devs[slot_id]->cmd_completion);
1103 case TRB_TYPE(TRB_EVAL_CONTEXT):
1104 virt_dev = xhci->devs[slot_id];
1105 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1107 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1108 complete(&xhci->devs[slot_id]->cmd_completion);
1110 case TRB_TYPE(TRB_ADDR_DEV):
1111 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1112 complete(&xhci->addr_dev);
1114 case TRB_TYPE(TRB_STOP_RING):
1115 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1117 case TRB_TYPE(TRB_SET_DEQ):
1118 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1120 case TRB_TYPE(TRB_CMD_NOOP):
1121 ++xhci->noops_handled;
1123 case TRB_TYPE(TRB_RESET_EP):
1124 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1126 case TRB_TYPE(TRB_RESET_DEV):
1127 xhci_dbg(xhci, "Completed reset device command.\n");
1128 slot_id = TRB_TO_SLOT_ID(
1129 xhci->cmd_ring->dequeue->generic.field[3]);
1130 virt_dev = xhci->devs[slot_id];
1132 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1134 xhci_warn(xhci, "Reset device command completion "
1135 "for disabled slot %u\n", slot_id);
1137 case TRB_TYPE(TRB_NEC_GET_FW):
1138 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1139 xhci->error_bitmask |= 1 << 6;
1142 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1143 NEC_FW_MAJOR(event->status),
1144 NEC_FW_MINOR(event->status));
1147 /* Skip over unknown commands on the event ring */
1148 xhci->error_bitmask |= 1 << 6;
1151 inc_deq(xhci, xhci->cmd_ring, false);
1154 static void handle_vendor_event(struct xhci_hcd *xhci,
1155 union xhci_trb *event)
1159 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1160 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1161 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1162 handle_cmd_completion(xhci, &event->event_cmd);
1165 static void handle_port_status(struct xhci_hcd *xhci,
1166 union xhci_trb *event)
1168 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1175 /* Port status change events always have a successful completion code */
1176 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1177 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1178 xhci->error_bitmask |= 1 << 8;
1180 port_id = GET_PORT_ID(event->generic.field[0]);
1181 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1183 ports = HCS_MAX_PORTS(xhci->hcs_params1);
1184 if ((port_id <= 0) || (port_id > ports)) {
1185 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1189 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS * (port_id - 1);
1190 temp = xhci_readl(xhci, addr);
1191 if (hcd->state == HC_STATE_SUSPENDED) {
1192 xhci_dbg(xhci, "resume root hub\n");
1193 usb_hcd_resume_root_hub(hcd);
1196 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1197 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1199 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1200 if (!(temp1 & CMD_RUN)) {
1201 xhci_warn(xhci, "xHC is not running.\n");
1205 if (DEV_SUPERSPEED(temp)) {
1206 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1207 temp = xhci_port_state_to_neutral(temp);
1208 temp &= ~PORT_PLS_MASK;
1209 temp |= PORT_LINK_STROBE | XDEV_U0;
1210 xhci_writel(xhci, temp, addr);
1211 slot_id = xhci_find_slot_id_by_port(xhci, port_id);
1213 xhci_dbg(xhci, "slot_id is zero\n");
1216 xhci_ring_device(xhci, slot_id);
1217 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1218 /* Clear PORT_PLC */
1219 temp = xhci_readl(xhci, addr);
1220 temp = xhci_port_state_to_neutral(temp);
1222 xhci_writel(xhci, temp, addr);
1224 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1225 xhci->resume_done[port_id - 1] = jiffies +
1226 msecs_to_jiffies(20);
1227 mod_timer(&hcd->rh_timer,
1228 xhci->resume_done[port_id - 1]);
1229 /* Do the rest in GetPortStatus */
1234 /* Update event ring dequeue pointer before dropping the lock */
1235 inc_deq(xhci, xhci->event_ring, true);
1237 spin_unlock(&xhci->lock);
1238 /* Pass this up to the core */
1239 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1240 spin_lock(&xhci->lock);
1244 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1245 * at end_trb, which may be in another segment. If the suspect DMA address is a
1246 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1249 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1250 union xhci_trb *start_trb,
1251 union xhci_trb *end_trb,
1252 dma_addr_t suspect_dma)
1254 dma_addr_t start_dma;
1255 dma_addr_t end_seg_dma;
1256 dma_addr_t end_trb_dma;
1257 struct xhci_segment *cur_seg;
1259 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1260 cur_seg = start_seg;
1265 /* We may get an event for a Link TRB in the middle of a TD */
1266 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1267 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1268 /* If the end TRB isn't in this segment, this is set to 0 */
1269 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1271 if (end_trb_dma > 0) {
1272 /* The end TRB is in this segment, so suspect should be here */
1273 if (start_dma <= end_trb_dma) {
1274 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1277 /* Case for one segment with
1278 * a TD wrapped around to the top
1280 if ((suspect_dma >= start_dma &&
1281 suspect_dma <= end_seg_dma) ||
1282 (suspect_dma >= cur_seg->dma &&
1283 suspect_dma <= end_trb_dma))
1288 /* Might still be somewhere in this segment */
1289 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1292 cur_seg = cur_seg->next;
1293 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1294 } while (cur_seg != start_seg);
1299 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1300 unsigned int slot_id, unsigned int ep_index,
1301 unsigned int stream_id,
1302 struct xhci_td *td, union xhci_trb *event_trb)
1304 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1305 ep->ep_state |= EP_HALTED;
1306 ep->stopped_td = td;
1307 ep->stopped_trb = event_trb;
1308 ep->stopped_stream = stream_id;
1310 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1311 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1313 ep->stopped_td = NULL;
1314 ep->stopped_trb = NULL;
1315 ep->stopped_stream = 0;
1317 xhci_ring_cmd_db(xhci);
1320 /* Check if an error has halted the endpoint ring. The class driver will
1321 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1322 * However, a babble and other errors also halt the endpoint ring, and the class
1323 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1324 * Ring Dequeue Pointer command manually.
1326 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1327 struct xhci_ep_ctx *ep_ctx,
1328 unsigned int trb_comp_code)
1330 /* TRB completion codes that may require a manual halt cleanup */
1331 if (trb_comp_code == COMP_TX_ERR ||
1332 trb_comp_code == COMP_BABBLE ||
1333 trb_comp_code == COMP_SPLIT_ERR)
1334 /* The 0.96 spec says a babbling control endpoint
1335 * is not halted. The 0.96 spec says it is. Some HW
1336 * claims to be 0.95 compliant, but it halts the control
1337 * endpoint anyway. Check if a babble halted the
1340 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1346 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1348 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1349 /* Vendor defined "informational" completion code,
1350 * treat as not-an-error.
1352 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1354 xhci_dbg(xhci, "Treating code as success.\n");
1361 * Finish the td processing, remove the td from td list;
1362 * Return 1 if the urb can be given back.
1364 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1365 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1366 struct xhci_virt_ep *ep, int *status, bool skip)
1368 struct xhci_virt_device *xdev;
1369 struct xhci_ring *ep_ring;
1370 unsigned int slot_id;
1372 struct urb *urb = NULL;
1373 struct xhci_ep_ctx *ep_ctx;
1375 struct urb_priv *urb_priv;
1378 slot_id = TRB_TO_SLOT_ID(event->flags);
1379 xdev = xhci->devs[slot_id];
1380 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1381 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1382 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1383 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1388 if (trb_comp_code == COMP_STOP_INVAL ||
1389 trb_comp_code == COMP_STOP) {
1390 /* The Endpoint Stop Command completion will take care of any
1391 * stopped TDs. A stopped TD may be restarted, so don't update
1392 * the ring dequeue pointer or take this TD off any lists yet.
1394 ep->stopped_td = td;
1395 ep->stopped_trb = event_trb;
1398 if (trb_comp_code == COMP_STALL) {
1399 /* The transfer is completed from the driver's
1400 * perspective, but we need to issue a set dequeue
1401 * command for this stalled endpoint to move the dequeue
1402 * pointer past the TD. We can't do that here because
1403 * the halt condition must be cleared first. Let the
1404 * USB class driver clear the stall later.
1406 ep->stopped_td = td;
1407 ep->stopped_trb = event_trb;
1408 ep->stopped_stream = ep_ring->stream_id;
1409 } else if (xhci_requires_manual_halt_cleanup(xhci,
1410 ep_ctx, trb_comp_code)) {
1411 /* Other types of errors halt the endpoint, but the
1412 * class driver doesn't call usb_reset_endpoint() unless
1413 * the error is -EPIPE. Clear the halted status in the
1414 * xHCI hardware manually.
1416 xhci_cleanup_halted_endpoint(xhci,
1417 slot_id, ep_index, ep_ring->stream_id,
1420 /* Update ring dequeue pointer */
1421 while (ep_ring->dequeue != td->last_trb)
1422 inc_deq(xhci, ep_ring, false);
1423 inc_deq(xhci, ep_ring, false);
1427 /* Clean up the endpoint's TD list */
1429 urb_priv = urb->hcpriv;
1431 /* Do one last check of the actual transfer length.
1432 * If the host controller said we transferred more data than
1433 * the buffer length, urb->actual_length will be a very big
1434 * number (since it's unsigned). Play it safe and say we didn't
1435 * transfer anything.
1437 if (urb->actual_length > urb->transfer_buffer_length) {
1438 xhci_warn(xhci, "URB transfer length is wrong, "
1439 "xHC issue? req. len = %u, "
1441 urb->transfer_buffer_length,
1442 urb->actual_length);
1443 urb->actual_length = 0;
1444 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1445 *status = -EREMOTEIO;
1449 list_del(&td->td_list);
1450 /* Was this TD slated to be cancelled but completed anyway? */
1451 if (!list_empty(&td->cancelled_td_list))
1452 list_del(&td->cancelled_td_list);
1455 /* Giveback the urb when all the tds are completed */
1456 if (urb_priv->td_cnt == urb_priv->length)
1464 * Process control tds, update urb status and actual_length.
1466 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1467 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1468 struct xhci_virt_ep *ep, int *status)
1470 struct xhci_virt_device *xdev;
1471 struct xhci_ring *ep_ring;
1472 unsigned int slot_id;
1474 struct xhci_ep_ctx *ep_ctx;
1477 slot_id = TRB_TO_SLOT_ID(event->flags);
1478 xdev = xhci->devs[slot_id];
1479 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1480 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1481 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1482 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1484 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1485 switch (trb_comp_code) {
1487 if (event_trb == ep_ring->dequeue) {
1488 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1489 "without IOC set??\n");
1490 *status = -ESHUTDOWN;
1491 } else if (event_trb != td->last_trb) {
1492 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1493 "without IOC set??\n");
1494 *status = -ESHUTDOWN;
1496 xhci_dbg(xhci, "Successful control transfer!\n");
1501 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1502 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1503 *status = -EREMOTEIO;
1508 if (!xhci_requires_manual_halt_cleanup(xhci,
1509 ep_ctx, trb_comp_code))
1511 xhci_dbg(xhci, "TRB error code %u, "
1512 "halted endpoint index = %u\n",
1513 trb_comp_code, ep_index);
1514 /* else fall through */
1516 /* Did we transfer part of the data (middle) phase? */
1517 if (event_trb != ep_ring->dequeue &&
1518 event_trb != td->last_trb)
1519 td->urb->actual_length =
1520 td->urb->transfer_buffer_length
1521 - TRB_LEN(event->transfer_len);
1523 td->urb->actual_length = 0;
1525 xhci_cleanup_halted_endpoint(xhci,
1526 slot_id, ep_index, 0, td, event_trb);
1527 return finish_td(xhci, td, event_trb, event, ep, status, true);
1530 * Did we transfer any data, despite the errors that might have
1531 * happened? I.e. did we get past the setup stage?
1533 if (event_trb != ep_ring->dequeue) {
1534 /* The event was for the status stage */
1535 if (event_trb == td->last_trb) {
1536 if (td->urb->actual_length != 0) {
1537 /* Don't overwrite a previously set error code
1539 if ((*status == -EINPROGRESS || *status == 0) &&
1540 (td->urb->transfer_flags
1541 & URB_SHORT_NOT_OK))
1542 /* Did we already see a short data
1544 *status = -EREMOTEIO;
1546 td->urb->actual_length =
1547 td->urb->transfer_buffer_length;
1550 /* Maybe the event was for the data stage? */
1551 if (trb_comp_code != COMP_STOP_INVAL) {
1552 /* We didn't stop on a link TRB in the middle */
1553 td->urb->actual_length =
1554 td->urb->transfer_buffer_length -
1555 TRB_LEN(event->transfer_len);
1556 xhci_dbg(xhci, "Waiting for status "
1563 return finish_td(xhci, td, event_trb, event, ep, status, false);
1567 * Process isochronous tds, update urb packet status and actual_length.
1569 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1570 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1571 struct xhci_virt_ep *ep, int *status)
1573 struct xhci_ring *ep_ring;
1574 struct urb_priv *urb_priv;
1578 union xhci_trb *cur_trb;
1579 struct xhci_segment *cur_seg;
1582 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1583 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1584 urb_priv = td->urb->hcpriv;
1585 idx = urb_priv->td_cnt;
1588 /* The transfer is partly done */
1590 td->urb->iso_frame_desc[idx].status = -EXDEV;
1592 /* handle completion code */
1593 switch (trb_comp_code) {
1595 td->urb->iso_frame_desc[idx].status = 0;
1596 xhci_dbg(xhci, "Successful isoc transfer!\n");
1599 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1600 td->urb->iso_frame_desc[idx].status =
1603 td->urb->iso_frame_desc[idx].status = 0;
1606 td->urb->iso_frame_desc[idx].status = -ECOMM;
1609 case COMP_BUFF_OVER:
1611 td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1615 td->urb->iso_frame_desc[idx].status = -EPROTO;
1619 case COMP_STOP_INVAL:
1622 td->urb->iso_frame_desc[idx].status = -1;
1627 /* calc actual length */
1629 td->urb->iso_frame_desc[idx].actual_length = 0;
1630 /* Update ring dequeue pointer */
1631 while (ep_ring->dequeue != td->last_trb)
1632 inc_deq(xhci, ep_ring, false);
1633 inc_deq(xhci, ep_ring, false);
1634 return finish_td(xhci, td, event_trb, event, ep, status, true);
1637 if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1638 td->urb->iso_frame_desc[idx].actual_length =
1639 td->urb->iso_frame_desc[idx].length;
1640 td->urb->actual_length +=
1641 td->urb->iso_frame_desc[idx].length;
1643 for (cur_trb = ep_ring->dequeue,
1644 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1645 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1646 if ((cur_trb->generic.field[3] &
1647 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1648 (cur_trb->generic.field[3] &
1649 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1651 TRB_LEN(cur_trb->generic.field[2]);
1653 len += TRB_LEN(cur_trb->generic.field[2]) -
1654 TRB_LEN(event->transfer_len);
1656 if (trb_comp_code != COMP_STOP_INVAL) {
1657 td->urb->iso_frame_desc[idx].actual_length = len;
1658 td->urb->actual_length += len;
1662 if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1665 return finish_td(xhci, td, event_trb, event, ep, status, false);
1669 * Process bulk and interrupt tds, update urb status and actual_length.
1671 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1672 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1673 struct xhci_virt_ep *ep, int *status)
1675 struct xhci_ring *ep_ring;
1676 union xhci_trb *cur_trb;
1677 struct xhci_segment *cur_seg;
1680 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1681 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1683 switch (trb_comp_code) {
1685 /* Double check that the HW transferred everything. */
1686 if (event_trb != td->last_trb) {
1687 xhci_warn(xhci, "WARN Successful completion "
1689 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1690 *status = -EREMOTEIO;
1694 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1695 xhci_dbg(xhci, "Successful bulk "
1698 xhci_dbg(xhci, "Successful interrupt "
1704 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1705 *status = -EREMOTEIO;
1710 /* Others already handled above */
1713 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1714 "%d bytes untransferred\n",
1715 td->urb->ep->desc.bEndpointAddress,
1716 td->urb->transfer_buffer_length,
1717 TRB_LEN(event->transfer_len));
1718 /* Fast path - was this the last TRB in the TD for this URB? */
1719 if (event_trb == td->last_trb) {
1720 if (TRB_LEN(event->transfer_len) != 0) {
1721 td->urb->actual_length =
1722 td->urb->transfer_buffer_length -
1723 TRB_LEN(event->transfer_len);
1724 if (td->urb->transfer_buffer_length <
1725 td->urb->actual_length) {
1726 xhci_warn(xhci, "HC gave bad length "
1727 "of %d bytes left\n",
1728 TRB_LEN(event->transfer_len));
1729 td->urb->actual_length = 0;
1730 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1731 *status = -EREMOTEIO;
1735 /* Don't overwrite a previously set error code */
1736 if (*status == -EINPROGRESS) {
1737 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1738 *status = -EREMOTEIO;
1743 td->urb->actual_length =
1744 td->urb->transfer_buffer_length;
1745 /* Ignore a short packet completion if the
1746 * untransferred length was zero.
1748 if (*status == -EREMOTEIO)
1752 /* Slow path - walk the list, starting from the dequeue
1753 * pointer, to get the actual length transferred.
1755 td->urb->actual_length = 0;
1756 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1757 cur_trb != event_trb;
1758 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1759 if ((cur_trb->generic.field[3] &
1760 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1761 (cur_trb->generic.field[3] &
1762 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1763 td->urb->actual_length +=
1764 TRB_LEN(cur_trb->generic.field[2]);
1766 /* If the ring didn't stop on a Link or No-op TRB, add
1767 * in the actual bytes transferred from the Normal TRB
1769 if (trb_comp_code != COMP_STOP_INVAL)
1770 td->urb->actual_length +=
1771 TRB_LEN(cur_trb->generic.field[2]) -
1772 TRB_LEN(event->transfer_len);
1775 return finish_td(xhci, td, event_trb, event, ep, status, false);
1779 * If this function returns an error condition, it means it got a Transfer
1780 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1781 * At this point, the host controller is probably hosed and should be reset.
1783 static int handle_tx_event(struct xhci_hcd *xhci,
1784 struct xhci_transfer_event *event)
1786 struct xhci_virt_device *xdev;
1787 struct xhci_virt_ep *ep;
1788 struct xhci_ring *ep_ring;
1789 unsigned int slot_id;
1791 struct xhci_td *td = NULL;
1792 dma_addr_t event_dma;
1793 struct xhci_segment *event_seg;
1794 union xhci_trb *event_trb;
1795 struct urb *urb = NULL;
1796 int status = -EINPROGRESS;
1797 struct urb_priv *urb_priv;
1798 struct xhci_ep_ctx *ep_ctx;
1802 slot_id = TRB_TO_SLOT_ID(event->flags);
1803 xdev = xhci->devs[slot_id];
1805 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1809 /* Endpoint ID is 1 based, our index is zero based */
1810 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1811 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1812 ep = &xdev->eps[ep_index];
1813 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1814 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1816 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1817 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1818 "or incorrect stream ring\n");
1822 event_dma = event->buffer;
1823 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1824 /* Look for common error cases */
1825 switch (trb_comp_code) {
1826 /* Skip codes that require special handling depending on
1833 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1835 case COMP_STOP_INVAL:
1836 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1839 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1840 ep->ep_state |= EP_HALTED;
1844 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1847 case COMP_SPLIT_ERR:
1849 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1853 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1854 status = -EOVERFLOW;
1857 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1861 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1863 case COMP_BUFF_OVER:
1864 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1868 * When the Isoch ring is empty, the xHC will generate
1869 * a Ring Overrun Event for IN Isoch endpoint or Ring
1870 * Underrun Event for OUT Isoch endpoint.
1872 xhci_dbg(xhci, "underrun event on endpoint\n");
1873 if (!list_empty(&ep_ring->td_list))
1874 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1875 "still with TDs queued?\n",
1876 TRB_TO_SLOT_ID(event->flags), ep_index);
1879 xhci_dbg(xhci, "overrun event on endpoint\n");
1880 if (!list_empty(&ep_ring->td_list))
1881 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1882 "still with TDs queued?\n",
1883 TRB_TO_SLOT_ID(event->flags), ep_index);
1885 case COMP_MISSED_INT:
1887 * When encounter missed service error, one or more isoc tds
1888 * may be missed by xHC.
1889 * Set skip flag of the ep_ring; Complete the missed tds as
1890 * short transfer when process the ep_ring next time.
1893 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1896 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1900 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1906 /* This TRB should be in the TD at the head of this ring's
1909 if (list_empty(&ep_ring->td_list)) {
1910 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1911 "with no TDs queued?\n",
1912 TRB_TO_SLOT_ID(event->flags), ep_index);
1913 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1914 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1915 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1918 xhci_dbg(xhci, "td_list is empty while skip "
1919 "flag set. Clear skip flag.\n");
1925 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1926 /* Is this a TRB in the currently executing TD? */
1927 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1928 td->last_trb, event_dma);
1929 if (event_seg && ep->skip) {
1930 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1934 (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1935 /* HC is busted, give up! */
1936 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1937 "part of current TD\n");
1942 event_trb = &event_seg->trbs[(event_dma -
1943 event_seg->dma) / sizeof(*event_trb)];
1945 * No-op TRB should not trigger interrupts.
1946 * If event_trb is a no-op TRB, it means the
1947 * corresponding TD has been cancelled. Just ignore
1950 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1951 == TRB_TYPE(TRB_TR_NOOP)) {
1952 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1958 /* Now update the urb's actual_length and give back to
1961 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1962 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1964 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
1965 ret = process_isoc_td(xhci, td, event_trb, event, ep,
1968 ret = process_bulk_intr_td(xhci, td, event_trb, event,
1973 * Do not update event ring dequeue pointer if ep->skip is set.
1974 * Will roll back to continue process missed tds.
1976 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1977 inc_deq(xhci, xhci->event_ring, true);
1982 urb_priv = urb->hcpriv;
1983 /* Leave the TD around for the reset endpoint function
1984 * to use(but only if it's not a control endpoint,
1985 * since we already queued the Set TR dequeue pointer
1986 * command for stalled control endpoints).
1988 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1989 (trb_comp_code != COMP_STALL &&
1990 trb_comp_code != COMP_BABBLE))
1991 xhci_urb_free_priv(xhci, urb_priv);
1993 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1994 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1996 urb, urb->actual_length, status);
1997 spin_unlock(&xhci->lock);
1998 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1999 spin_lock(&xhci->lock);
2003 * If ep->skip is set, it means there are missed tds on the
2004 * endpoint ring need to take care of.
2005 * Process them as short transfer until reach the td pointed by
2008 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2014 * This function handles all OS-owned events on the event ring. It may drop
2015 * xhci->lock between event processing (e.g. to pass up port status changes).
2017 static void xhci_handle_event(struct xhci_hcd *xhci)
2019 union xhci_trb *event;
2020 int update_ptrs = 1;
2023 xhci_dbg(xhci, "In %s\n", __func__);
2024 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2025 xhci->error_bitmask |= 1 << 1;
2029 event = xhci->event_ring->dequeue;
2030 /* Does the HC or OS own the TRB? */
2031 if ((event->event_cmd.flags & TRB_CYCLE) !=
2032 xhci->event_ring->cycle_state) {
2033 xhci->error_bitmask |= 1 << 2;
2036 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2038 /* FIXME: Handle more event types. */
2039 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2040 case TRB_TYPE(TRB_COMPLETION):
2041 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2042 handle_cmd_completion(xhci, &event->event_cmd);
2043 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2045 case TRB_TYPE(TRB_PORT_STATUS):
2046 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2047 handle_port_status(xhci, event);
2048 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2051 case TRB_TYPE(TRB_TRANSFER):
2052 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2053 ret = handle_tx_event(xhci, &event->trans_event);
2054 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2056 xhci->error_bitmask |= 1 << 9;
2061 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2062 handle_vendor_event(xhci, event);
2064 xhci->error_bitmask |= 1 << 3;
2066 /* Any of the above functions may drop and re-acquire the lock, so check
2067 * to make sure a watchdog timer didn't mark the host as non-responsive.
2069 if (xhci->xhc_state & XHCI_STATE_DYING) {
2070 xhci_dbg(xhci, "xHCI host dying, returning from "
2071 "event handler.\n");
2076 /* Update SW event ring dequeue pointer */
2077 inc_deq(xhci, xhci->event_ring, true);
2079 /* Are there more items on the event ring? */
2080 xhci_handle_event(xhci);
2084 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2085 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2086 * indicators of an event TRB error, but we check the status *first* to be safe.
2088 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2090 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2092 union xhci_trb *trb;
2094 union xhci_trb *event_ring_deq;
2097 spin_lock(&xhci->lock);
2098 trb = xhci->event_ring->dequeue;
2099 /* Check if the xHC generated the interrupt, or the irq is shared */
2100 status = xhci_readl(xhci, &xhci->op_regs->status);
2101 if (status == 0xffffffff)
2104 if (!(status & STS_EINT)) {
2105 spin_unlock(&xhci->lock);
2108 xhci_dbg(xhci, "op reg status = %08x\n", status);
2109 xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2110 xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2111 (unsigned long long)
2112 xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2113 lower_32_bits(trb->link.segment_ptr),
2114 upper_32_bits(trb->link.segment_ptr),
2115 (unsigned int) trb->link.intr_target,
2116 (unsigned int) trb->link.control);
2118 if (status & STS_FATAL) {
2119 xhci_warn(xhci, "WARNING: Host System Error\n");
2122 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
2123 spin_unlock(&xhci->lock);
2128 * Clear the op reg interrupt status first,
2129 * so we can receive interrupts from other MSI-X interrupters.
2130 * Write 1 to clear the interrupt status.
2133 xhci_writel(xhci, status, &xhci->op_regs->status);
2134 /* FIXME when MSI-X is supported and there are multiple vectors */
2135 /* Clear the MSI-X event interrupt status */
2137 if (hcd->irq != -1) {
2139 /* Acknowledge the PCI interrupt */
2140 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2142 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2145 if (xhci->xhc_state & XHCI_STATE_DYING) {
2146 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2147 "Shouldn't IRQs be disabled?\n");
2148 /* Clear the event handler busy flag (RW1C);
2149 * the event ring should be empty.
2151 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2152 xhci_write_64(xhci, temp_64 | ERST_EHB,
2153 &xhci->ir_set->erst_dequeue);
2154 spin_unlock(&xhci->lock);
2159 event_ring_deq = xhci->event_ring->dequeue;
2160 /* FIXME this should be a delayed service routine
2161 * that clears the EHB.
2163 xhci_handle_event(xhci);
2165 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2166 /* If necessary, update the HW's version of the event ring deq ptr. */
2167 if (event_ring_deq != xhci->event_ring->dequeue) {
2168 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2169 xhci->event_ring->dequeue);
2171 xhci_warn(xhci, "WARN something wrong with SW event "
2172 "ring dequeue ptr.\n");
2173 /* Update HC event ring dequeue pointer */
2174 temp_64 &= ERST_PTR_MASK;
2175 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2178 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2179 temp_64 |= ERST_EHB;
2180 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2182 spin_unlock(&xhci->lock);
2187 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2191 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2193 ret = xhci_irq(hcd);
2198 /**** Endpoint Ring Operations ****/
2201 * Generic function for queueing a TRB on a ring.
2202 * The caller must have checked to make sure there's room on the ring.
2204 * @more_trbs_coming: Will you enqueue more TRBs before calling
2205 * prepare_transfer()?
2207 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2208 bool consumer, bool more_trbs_coming,
2209 u32 field1, u32 field2, u32 field3, u32 field4)
2211 struct xhci_generic_trb *trb;
2213 trb = &ring->enqueue->generic;
2214 trb->field[0] = field1;
2215 trb->field[1] = field2;
2216 trb->field[2] = field3;
2217 trb->field[3] = field4;
2218 inc_enq(xhci, ring, consumer, more_trbs_coming);
2222 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2223 * FIXME allocate segments if the ring is full.
2225 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2226 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2228 /* Make sure the endpoint has been added to xHC schedule */
2229 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2231 case EP_STATE_DISABLED:
2233 * USB core changed config/interfaces without notifying us,
2234 * or hardware is reporting the wrong state.
2236 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2238 case EP_STATE_ERROR:
2239 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2240 /* FIXME event handling code for error needs to clear it */
2241 /* XXX not sure if this should be -ENOENT or not */
2243 case EP_STATE_HALTED:
2244 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2245 case EP_STATE_STOPPED:
2246 case EP_STATE_RUNNING:
2249 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2251 * FIXME issue Configure Endpoint command to try to get the HC
2252 * back into a known state.
2256 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2257 /* FIXME allocate more room */
2258 xhci_err(xhci, "ERROR no room on ep ring\n");
2262 if (enqueue_is_link_trb(ep_ring)) {
2263 struct xhci_ring *ring = ep_ring;
2264 union xhci_trb *next;
2266 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2267 next = ring->enqueue;
2269 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2271 /* If we're not dealing with 0.95 hardware,
2272 * clear the chain bit.
2274 if (!xhci_link_trb_quirk(xhci))
2275 next->link.control &= ~TRB_CHAIN;
2277 next->link.control |= TRB_CHAIN;
2280 next->link.control ^= (u32) TRB_CYCLE;
2282 /* Toggle the cycle bit after the last ring segment. */
2283 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2284 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2285 if (!in_interrupt()) {
2286 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2287 "state for ring %p = %i\n",
2288 ring, (unsigned int)ring->cycle_state);
2291 ring->enq_seg = ring->enq_seg->next;
2292 ring->enqueue = ring->enq_seg->trbs;
2293 next = ring->enqueue;
2300 static int prepare_transfer(struct xhci_hcd *xhci,
2301 struct xhci_virt_device *xdev,
2302 unsigned int ep_index,
2303 unsigned int stream_id,
2304 unsigned int num_trbs,
2306 unsigned int td_index,
2310 struct urb_priv *urb_priv;
2312 struct xhci_ring *ep_ring;
2313 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2315 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2317 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2322 ret = prepare_ring(xhci, ep_ring,
2323 ep_ctx->ep_info & EP_STATE_MASK,
2324 num_trbs, mem_flags);
2328 urb_priv = urb->hcpriv;
2329 td = urb_priv->td[td_index];
2331 INIT_LIST_HEAD(&td->td_list);
2332 INIT_LIST_HEAD(&td->cancelled_td_list);
2334 if (td_index == 0) {
2335 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2336 if (unlikely(ret)) {
2337 xhci_urb_free_priv(xhci, urb_priv);
2344 /* Add this TD to the tail of the endpoint ring's TD list */
2345 list_add_tail(&td->td_list, &ep_ring->td_list);
2346 td->start_seg = ep_ring->enq_seg;
2347 td->first_trb = ep_ring->enqueue;
2349 urb_priv->td[td_index] = td;
2354 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2356 int num_sgs, num_trbs, running_total, temp, i;
2357 struct scatterlist *sg;
2360 num_sgs = urb->num_sgs;
2361 temp = urb->transfer_buffer_length;
2363 xhci_dbg(xhci, "count sg list trbs: \n");
2365 for_each_sg(urb->sg, sg, num_sgs, i) {
2366 unsigned int previous_total_trbs = num_trbs;
2367 unsigned int len = sg_dma_len(sg);
2369 /* Scatter gather list entries may cross 64KB boundaries */
2370 running_total = TRB_MAX_BUFF_SIZE -
2371 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2372 if (running_total != 0)
2375 /* How many more 64KB chunks to transfer, how many more TRBs? */
2376 while (running_total < sg_dma_len(sg)) {
2378 running_total += TRB_MAX_BUFF_SIZE;
2380 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2381 i, (unsigned long long)sg_dma_address(sg),
2382 len, len, num_trbs - previous_total_trbs);
2384 len = min_t(int, len, temp);
2389 xhci_dbg(xhci, "\n");
2390 if (!in_interrupt())
2391 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2393 urb->ep->desc.bEndpointAddress,
2394 urb->transfer_buffer_length,
2399 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2402 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2403 "TRBs, %d left\n", __func__,
2404 urb->ep->desc.bEndpointAddress, num_trbs);
2405 if (running_total != urb->transfer_buffer_length)
2406 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2407 "queued %#x (%d), asked for %#x (%d)\n",
2409 urb->ep->desc.bEndpointAddress,
2410 running_total, running_total,
2411 urb->transfer_buffer_length,
2412 urb->transfer_buffer_length);
2415 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2416 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2417 struct xhci_generic_trb *start_trb)
2420 * Pass all the TRBs to the hardware at once and make sure this write
2425 start_trb->field[3] |= start_cycle;
2427 start_trb->field[3] &= ~0x1;
2428 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2432 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2433 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2434 * (comprised of sg list entries) can take several service intervals to
2437 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2438 struct urb *urb, int slot_id, unsigned int ep_index)
2440 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2441 xhci->devs[slot_id]->out_ctx, ep_index);
2445 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2446 ep_interval = urb->interval;
2447 /* Convert to microframes */
2448 if (urb->dev->speed == USB_SPEED_LOW ||
2449 urb->dev->speed == USB_SPEED_FULL)
2451 /* FIXME change this to a warning and a suggestion to use the new API
2452 * to set the polling interval (once the API is added).
2454 if (xhci_interval != ep_interval) {
2455 if (printk_ratelimit())
2456 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2457 " (%d microframe%s) than xHCI "
2458 "(%d microframe%s)\n",
2460 ep_interval == 1 ? "" : "s",
2462 xhci_interval == 1 ? "" : "s");
2463 urb->interval = xhci_interval;
2464 /* Convert back to frames for LS/FS devices */
2465 if (urb->dev->speed == USB_SPEED_LOW ||
2466 urb->dev->speed == USB_SPEED_FULL)
2469 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2473 * The TD size is the number of bytes remaining in the TD (including this TRB),
2474 * right shifted by 10.
2475 * It must fit in bits 21:17, so it can't be bigger than 31.
2477 static u32 xhci_td_remainder(unsigned int remainder)
2479 u32 max = (1 << (21 - 17 + 1)) - 1;
2481 if ((remainder >> 10) >= max)
2484 return (remainder >> 10) << 17;
2487 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2488 struct urb *urb, int slot_id, unsigned int ep_index)
2490 struct xhci_ring *ep_ring;
2491 unsigned int num_trbs;
2492 struct urb_priv *urb_priv;
2494 struct scatterlist *sg;
2496 int trb_buff_len, this_sg_len, running_total;
2499 bool more_trbs_coming;
2501 struct xhci_generic_trb *start_trb;
2504 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2508 num_trbs = count_sg_trbs_needed(xhci, urb);
2509 num_sgs = urb->num_sgs;
2511 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2512 ep_index, urb->stream_id,
2513 num_trbs, urb, 0, mem_flags);
2514 if (trb_buff_len < 0)
2515 return trb_buff_len;
2517 urb_priv = urb->hcpriv;
2518 td = urb_priv->td[0];
2521 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2522 * until we've finished creating all the other TRBs. The ring's cycle
2523 * state may change as we enqueue the other TRBs, so save it too.
2525 start_trb = &ep_ring->enqueue->generic;
2526 start_cycle = ep_ring->cycle_state;
2530 * How much data is in the first TRB?
2532 * There are three forces at work for TRB buffer pointers and lengths:
2533 * 1. We don't want to walk off the end of this sg-list entry buffer.
2534 * 2. The transfer length that the driver requested may be smaller than
2535 * the amount of memory allocated for this scatter-gather list.
2536 * 3. TRBs buffers can't cross 64KB boundaries.
2539 addr = (u64) sg_dma_address(sg);
2540 this_sg_len = sg_dma_len(sg);
2541 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2542 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2543 if (trb_buff_len > urb->transfer_buffer_length)
2544 trb_buff_len = urb->transfer_buffer_length;
2545 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2549 /* Queue the first TRB, even if it's zero-length */
2552 u32 length_field = 0;
2555 /* Don't change the cycle bit of the first TRB until later */
2558 if (start_cycle == 0)
2561 field |= ep_ring->cycle_state;
2563 /* Chain all the TRBs together; clear the chain bit in the last
2564 * TRB to indicate it's the last TRB in the chain.
2569 /* FIXME - add check for ZERO_PACKET flag before this */
2570 td->last_trb = ep_ring->enqueue;
2573 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2574 "64KB boundary at %#x, end dma = %#x\n",
2575 (unsigned int) addr, trb_buff_len, trb_buff_len,
2576 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2577 (unsigned int) addr + trb_buff_len);
2578 if (TRB_MAX_BUFF_SIZE -
2579 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2580 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2581 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2582 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2583 (unsigned int) addr + trb_buff_len);
2585 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2587 length_field = TRB_LEN(trb_buff_len) |
2591 more_trbs_coming = true;
2593 more_trbs_coming = false;
2594 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2595 lower_32_bits(addr),
2596 upper_32_bits(addr),
2598 /* We always want to know if the TRB was short,
2599 * or we won't get an event when it completes.
2600 * (Unless we use event data TRBs, which are a
2601 * waste of space and HC resources.)
2603 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2605 running_total += trb_buff_len;
2607 /* Calculate length for next transfer --
2608 * Are we done queueing all the TRBs for this sg entry?
2610 this_sg_len -= trb_buff_len;
2611 if (this_sg_len == 0) {
2616 addr = (u64) sg_dma_address(sg);
2617 this_sg_len = sg_dma_len(sg);
2619 addr += trb_buff_len;
2622 trb_buff_len = TRB_MAX_BUFF_SIZE -
2623 (addr & (TRB_MAX_BUFF_SIZE - 1));
2624 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2625 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2627 urb->transfer_buffer_length - running_total;
2628 } while (running_total < urb->transfer_buffer_length);
2630 check_trb_math(urb, num_trbs, running_total);
2631 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2632 start_cycle, start_trb);
2636 /* This is very similar to what ehci-q.c qtd_fill() does */
2637 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2638 struct urb *urb, int slot_id, unsigned int ep_index)
2640 struct xhci_ring *ep_ring;
2641 struct urb_priv *urb_priv;
2644 struct xhci_generic_trb *start_trb;
2646 bool more_trbs_coming;
2648 u32 field, length_field;
2650 int running_total, trb_buff_len, ret;
2654 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2656 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2661 /* How much data is (potentially) left before the 64KB boundary? */
2662 running_total = TRB_MAX_BUFF_SIZE -
2663 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2665 /* If there's some data on this 64KB chunk, or we have to send a
2666 * zero-length transfer, we need at least one TRB
2668 if (running_total != 0 || urb->transfer_buffer_length == 0)
2670 /* How many more 64KB chunks to transfer, how many more TRBs? */
2671 while (running_total < urb->transfer_buffer_length) {
2673 running_total += TRB_MAX_BUFF_SIZE;
2675 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2677 if (!in_interrupt())
2678 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2679 "addr = %#llx, num_trbs = %d\n",
2680 urb->ep->desc.bEndpointAddress,
2681 urb->transfer_buffer_length,
2682 urb->transfer_buffer_length,
2683 (unsigned long long)urb->transfer_dma,
2686 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2687 ep_index, urb->stream_id,
2688 num_trbs, urb, 0, mem_flags);
2692 urb_priv = urb->hcpriv;
2693 td = urb_priv->td[0];
2696 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2697 * until we've finished creating all the other TRBs. The ring's cycle
2698 * state may change as we enqueue the other TRBs, so save it too.
2700 start_trb = &ep_ring->enqueue->generic;
2701 start_cycle = ep_ring->cycle_state;
2704 /* How much data is in the first TRB? */
2705 addr = (u64) urb->transfer_dma;
2706 trb_buff_len = TRB_MAX_BUFF_SIZE -
2707 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2708 if (trb_buff_len > urb->transfer_buffer_length)
2709 trb_buff_len = urb->transfer_buffer_length;
2713 /* Queue the first TRB, even if it's zero-length */
2718 /* Don't change the cycle bit of the first TRB until later */
2721 if (start_cycle == 0)
2724 field |= ep_ring->cycle_state;
2726 /* Chain all the TRBs together; clear the chain bit in the last
2727 * TRB to indicate it's the last TRB in the chain.
2732 /* FIXME - add check for ZERO_PACKET flag before this */
2733 td->last_trb = ep_ring->enqueue;
2736 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2738 length_field = TRB_LEN(trb_buff_len) |
2742 more_trbs_coming = true;
2744 more_trbs_coming = false;
2745 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2746 lower_32_bits(addr),
2747 upper_32_bits(addr),
2749 /* We always want to know if the TRB was short,
2750 * or we won't get an event when it completes.
2751 * (Unless we use event data TRBs, which are a
2752 * waste of space and HC resources.)
2754 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2756 running_total += trb_buff_len;
2758 /* Calculate length for next transfer */
2759 addr += trb_buff_len;
2760 trb_buff_len = urb->transfer_buffer_length - running_total;
2761 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2762 trb_buff_len = TRB_MAX_BUFF_SIZE;
2763 } while (running_total < urb->transfer_buffer_length);
2765 check_trb_math(urb, num_trbs, running_total);
2766 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2767 start_cycle, start_trb);
2771 /* Caller must have locked xhci->lock */
2772 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2773 struct urb *urb, int slot_id, unsigned int ep_index)
2775 struct xhci_ring *ep_ring;
2778 struct usb_ctrlrequest *setup;
2779 struct xhci_generic_trb *start_trb;
2781 u32 field, length_field;
2782 struct urb_priv *urb_priv;
2785 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2790 * Need to copy setup packet into setup TRB, so we can't use the setup
2793 if (!urb->setup_packet)
2796 if (!in_interrupt())
2797 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2799 /* 1 TRB for setup, 1 for status */
2802 * Don't need to check if we need additional event data and normal TRBs,
2803 * since data in control transfers will never get bigger than 16MB
2804 * XXX: can we get a buffer that crosses 64KB boundaries?
2806 if (urb->transfer_buffer_length > 0)
2808 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2809 ep_index, urb->stream_id,
2810 num_trbs, urb, 0, mem_flags);
2814 urb_priv = urb->hcpriv;
2815 td = urb_priv->td[0];
2818 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2819 * until we've finished creating all the other TRBs. The ring's cycle
2820 * state may change as we enqueue the other TRBs, so save it too.
2822 start_trb = &ep_ring->enqueue->generic;
2823 start_cycle = ep_ring->cycle_state;
2825 /* Queue setup TRB - see section 6.4.1.2.1 */
2826 /* FIXME better way to translate setup_packet into two u32 fields? */
2827 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2829 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2830 if (start_cycle == 0)
2832 queue_trb(xhci, ep_ring, false, true,
2833 /* FIXME endianness is probably going to bite my ass here. */
2834 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2835 setup->wIndex | setup->wLength << 16,
2836 TRB_LEN(8) | TRB_INTR_TARGET(0),
2837 /* Immediate data in pointer */
2840 /* If there's data, queue data TRBs */
2842 length_field = TRB_LEN(urb->transfer_buffer_length) |
2843 xhci_td_remainder(urb->transfer_buffer_length) |
2845 if (urb->transfer_buffer_length > 0) {
2846 if (setup->bRequestType & USB_DIR_IN)
2847 field |= TRB_DIR_IN;
2848 queue_trb(xhci, ep_ring, false, true,
2849 lower_32_bits(urb->transfer_dma),
2850 upper_32_bits(urb->transfer_dma),
2852 /* Event on short tx */
2853 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2856 /* Save the DMA address of the last TRB in the TD */
2857 td->last_trb = ep_ring->enqueue;
2859 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2860 /* If the device sent data, the status stage is an OUT transfer */
2861 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2865 queue_trb(xhci, ep_ring, false, false,
2869 /* Event on completion */
2870 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2872 giveback_first_trb(xhci, slot_id, ep_index, 0,
2873 start_cycle, start_trb);
2877 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2878 struct urb *urb, int i)
2881 u64 addr, td_len, running_total;
2883 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2884 td_len = urb->iso_frame_desc[i].length;
2886 running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2887 if (running_total != 0)
2890 while (running_total < td_len) {
2892 running_total += TRB_MAX_BUFF_SIZE;
2898 /* This is for isoc transfer */
2899 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2900 struct urb *urb, int slot_id, unsigned int ep_index)
2902 struct xhci_ring *ep_ring;
2903 struct urb_priv *urb_priv;
2905 int num_tds, trbs_per_td;
2906 struct xhci_generic_trb *start_trb;
2909 u32 field, length_field;
2910 int running_total, trb_buff_len, td_len, td_remain_len, ret;
2911 u64 start_addr, addr;
2913 bool more_trbs_coming;
2915 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2917 num_tds = urb->number_of_packets;
2919 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
2923 if (!in_interrupt())
2924 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
2925 " addr = %#llx, num_tds = %d\n",
2926 urb->ep->desc.bEndpointAddress,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length,
2929 (unsigned long long)urb->transfer_dma,
2932 start_addr = (u64) urb->transfer_dma;
2933 start_trb = &ep_ring->enqueue->generic;
2934 start_cycle = ep_ring->cycle_state;
2936 /* Queue the first TRB, even if it's zero-length */
2937 for (i = 0; i < num_tds; i++) {
2941 addr = start_addr + urb->iso_frame_desc[i].offset;
2942 td_len = urb->iso_frame_desc[i].length;
2943 td_remain_len = td_len;
2945 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
2947 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2948 urb->stream_id, trbs_per_td, urb, i, mem_flags);
2952 urb_priv = urb->hcpriv;
2953 td = urb_priv->td[i];
2955 for (j = 0; j < trbs_per_td; j++) {
2960 /* Queue the isoc TRB */
2961 field |= TRB_TYPE(TRB_ISOC);
2962 /* Assume URB_ISO_ASAP is set */
2965 if (start_cycle == 0)
2968 field |= ep_ring->cycle_state;
2971 /* Queue other normal TRBs */
2972 field |= TRB_TYPE(TRB_NORMAL);
2973 field |= ep_ring->cycle_state;
2976 /* Chain all the TRBs together; clear the chain bit in
2977 * the last TRB to indicate it's the last TRB in the
2980 if (j < trbs_per_td - 1) {
2982 more_trbs_coming = true;
2984 td->last_trb = ep_ring->enqueue;
2986 more_trbs_coming = false;
2989 /* Calculate TRB length */
2990 trb_buff_len = TRB_MAX_BUFF_SIZE -
2991 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2992 if (trb_buff_len > td_remain_len)
2993 trb_buff_len = td_remain_len;
2995 remainder = xhci_td_remainder(td_len - running_total);
2996 length_field = TRB_LEN(trb_buff_len) |
2999 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3000 lower_32_bits(addr),
3001 upper_32_bits(addr),
3003 /* We always want to know if the TRB was short,
3004 * or we won't get an event when it completes.
3005 * (Unless we use event data TRBs, which are a
3006 * waste of space and HC resources.)
3009 running_total += trb_buff_len;
3011 addr += trb_buff_len;
3012 td_remain_len -= trb_buff_len;
3015 /* Check TD length */
3016 if (running_total != td_len) {
3017 xhci_err(xhci, "ISOC TD length unmatch\n");
3022 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3023 start_cycle, start_trb);
3028 * Check transfer ring to guarantee there is enough room for the urb.
3029 * Update ISO URB start_frame and interval.
3030 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3031 * update the urb->start_frame by now.
3032 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3034 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3035 struct urb *urb, int slot_id, unsigned int ep_index)
3037 struct xhci_virt_device *xdev;
3038 struct xhci_ring *ep_ring;
3039 struct xhci_ep_ctx *ep_ctx;
3043 int num_tds, num_trbs, i;
3046 xdev = xhci->devs[slot_id];
3047 ep_ring = xdev->eps[ep_index].ring;
3048 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3051 num_tds = urb->number_of_packets;
3052 for (i = 0; i < num_tds; i++)
3053 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3055 /* Check the ring to guarantee there is enough room for the whole urb.
3056 * Do not insert any td of the urb to the ring if the check failed.
3058 ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3059 num_trbs, mem_flags);
3063 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3064 start_frame &= 0x3fff;
3066 urb->start_frame = start_frame;
3067 if (urb->dev->speed == USB_SPEED_LOW ||
3068 urb->dev->speed == USB_SPEED_FULL)
3069 urb->start_frame >>= 3;
3071 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3072 ep_interval = urb->interval;
3073 /* Convert to microframes */
3074 if (urb->dev->speed == USB_SPEED_LOW ||
3075 urb->dev->speed == USB_SPEED_FULL)
3077 /* FIXME change this to a warning and a suggestion to use the new API
3078 * to set the polling interval (once the API is added).
3080 if (xhci_interval != ep_interval) {
3081 if (printk_ratelimit())
3082 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3083 " (%d microframe%s) than xHCI "
3084 "(%d microframe%s)\n",
3086 ep_interval == 1 ? "" : "s",
3088 xhci_interval == 1 ? "" : "s");
3089 urb->interval = xhci_interval;
3090 /* Convert back to frames for LS/FS devices */
3091 if (urb->dev->speed == USB_SPEED_LOW ||
3092 urb->dev->speed == USB_SPEED_FULL)
3095 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3098 /**** Command Ring Operations ****/
3100 /* Generic function for queueing a command TRB on the command ring.
3101 * Check to make sure there's room on the command ring for one command TRB.
3102 * Also check that there's room reserved for commands that must not fail.
3103 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3104 * then only check for the number of reserved spots.
3105 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3106 * because the command event handler may want to resubmit a failed command.
3108 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3109 u32 field3, u32 field4, bool command_must_succeed)
3111 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3114 if (!command_must_succeed)
3117 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3118 reserved_trbs, GFP_ATOMIC);
3120 xhci_err(xhci, "ERR: No room for command on command ring\n");
3121 if (command_must_succeed)
3122 xhci_err(xhci, "ERR: Reserved TRB counting for "
3123 "unfailable commands failed.\n");
3126 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3127 field4 | xhci->cmd_ring->cycle_state);
3131 /* Queue a no-op command on the command ring */
3132 static int queue_cmd_noop(struct xhci_hcd *xhci)
3134 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
3138 * Place a no-op command on the command ring to test the command and
3141 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
3143 if (queue_cmd_noop(xhci) < 0)
3145 xhci->noops_submitted++;
3146 return xhci_ring_cmd_db;
3149 /* Queue a slot enable or disable request on the command ring */
3150 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3152 return queue_command(xhci, 0, 0, 0,
3153 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3156 /* Queue an address device command TRB */
3157 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3160 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3161 upper_32_bits(in_ctx_ptr), 0,
3162 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3166 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3167 u32 field1, u32 field2, u32 field3, u32 field4)
3169 return queue_command(xhci, field1, field2, field3, field4, false);
3172 /* Queue a reset device command TRB */
3173 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3175 return queue_command(xhci, 0, 0, 0,
3176 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3180 /* Queue a configure endpoint command TRB */
3181 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3182 u32 slot_id, bool command_must_succeed)
3184 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3185 upper_32_bits(in_ctx_ptr), 0,
3186 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3187 command_must_succeed);
3190 /* Queue an evaluate context command TRB */
3191 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3194 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3195 upper_32_bits(in_ctx_ptr), 0,
3196 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3201 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3202 * activity on an endpoint that is about to be suspended.
3204 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3205 unsigned int ep_index, int suspend)
3207 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3208 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3209 u32 type = TRB_TYPE(TRB_STOP_RING);
3210 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3212 return queue_command(xhci, 0, 0, 0,
3213 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3216 /* Set Transfer Ring Dequeue Pointer command.
3217 * This should not be used for endpoints that have streams enabled.
3219 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3220 unsigned int ep_index, unsigned int stream_id,
3221 struct xhci_segment *deq_seg,
3222 union xhci_trb *deq_ptr, u32 cycle_state)
3225 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3226 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3227 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3228 u32 type = TRB_TYPE(TRB_SET_DEQ);
3230 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3232 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3233 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3237 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3238 upper_32_bits(addr), trb_stream_id,
3239 trb_slot_id | trb_ep_index | type, false);
3242 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3243 unsigned int ep_index)
3245 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3246 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3247 u32 type = TRB_TYPE(TRB_RESET_EP);
3249 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,