drivers/video/fbdev/msm/mdss_dsi.c

   1 /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
   2  * Copyright (C) 2019 XiaoMi, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/delay.h>
  19 #include <linux/io.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/gpio.h>
  23 #include <linux/err.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/leds-qpnp-wled.h>
  26 #include <linux/clk.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/msm-bus.h>
  29 #include <linux/pm_qos.h>
  30 #include <linux/dma-buf.h>
  31
  32 #include "mdss.h"
  33 #include "mdss_panel.h"
  34 #include "mdss_dsi.h"
  35 #include "mdss_debug.h"
  36 #include "mdss_dsi_phy.h"
  37 #include "mdss_dba_utils.h"
  38
  39 #define CMDLINE_DSI_CTL_NUM_STRING_LEN 2
  40
  41 /* Master structure to hold all the information about the DSI/panel */
  42 static struct mdss_dsi_data *mdss_dsi_res;
  43
  44 #define DSI_DISABLE_PC_LATENCY 100
  45 #define DSI_ENABLE_PC_LATENCY PM_QOS_DEFAULT_VALUE
  46
  47 static struct pm_qos_request mdss_dsi_pm_qos_request;
  48
  49 void mdss_dump_dsi_debug_bus(u32 bus_dump_flag,
  50         u32 **dump_mem)
  51 {
  52         struct mdss_dsi_data *sdata = mdss_dsi_res;
  53         struct mdss_dsi_ctrl_pdata *m_ctrl, *s_ctrl;
  54         bool in_log, in_mem;
  55         u32 *dump_addr = NULL;
  56         u32 status0 = 0, status1 = 0;
  57         phys_addr_t phys = 0;
  58         int list_size = 0;
  59         int i;
  60         bool dsi0_active = false, dsi1_active = false;
  61
  62         if (!sdata || !sdata->dbg_bus || !sdata->dbg_bus_size)
  63                 return;
  64
  65         m_ctrl = sdata->ctrl_pdata[0];
  66         s_ctrl = sdata->ctrl_pdata[1];
  67
  68         if (!m_ctrl)
  69                 return;
  70
  71         if (m_ctrl && m_ctrl->shared_data->dsi0_active)
  72                 dsi0_active = true;
  73         if (s_ctrl && s_ctrl->shared_data->dsi1_active)
  74                 dsi1_active = true;
  75
  76         list_size = (sdata->dbg_bus_size * sizeof(sdata->dbg_bus[0]) * 4);
  77
  78         in_log = (bus_dump_flag & MDSS_DBG_DUMP_IN_LOG);
  79         in_mem = (bus_dump_flag & MDSS_DBG_DUMP_IN_MEM);
  80
  81         if (in_mem) {
  82                 if (!(*dump_mem))
  83                         *dump_mem = dma_alloc_coherent(&sdata->pdev->dev,
  84                                 list_size, &phys, GFP_KERNEL);
  85
  86                 if (*dump_mem) {
  87                         dump_addr = *dump_mem;
  88                         pr_info("%s: start_addr:0x%pK end_addr:0x%pK\n",
  89                                 __func__, dump_addr, dump_addr + list_size);
  90                 } else {
  91                         in_mem = false;
  92                         pr_err("dump_mem: allocation fails\n");
  93                 }
  94         }
  95
  96         pr_info("========= Start DSI Debug Bus =========\n");
  97
  98         mdss_dsi_clk_ctrl(m_ctrl, m_ctrl->dsi_clk_handle,
  99                           MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
 100
 101         for (i = 0; i < sdata->dbg_bus_size; i++) {
 102                 if (dsi0_active) {
 103                         writel_relaxed(sdata->dbg_bus[i],
 104                                         m_ctrl->ctrl_base + 0x124);
 105                         wmb(); /* ensure regsiter is committed */
 106                 }
 107                 if (dsi1_active) {
 108                         writel_relaxed(sdata->dbg_bus[i],
 109                                         s_ctrl->ctrl_base + 0x124);
 110                         wmb(); /* ensure register is committed */
 111                 }
 112
 113                 if (dsi0_active) {
 114                         status0 = readl_relaxed(m_ctrl->ctrl_base + 0x128);
 115                         if (in_log)
 116                                 pr_err("CTRL:0 bus_ctrl: 0x%x status: 0x%x\n",
 117                                         sdata->dbg_bus[i], status0);
 118                 }
 119                 if (dsi1_active) {
 120                         status1 = readl_relaxed(s_ctrl->ctrl_base + 0x128);
 121                         if (in_log)
 122                                 pr_err("CTRL:1 bus_ctrl: 0x%x status: 0x%x\n",
 123                                         sdata->dbg_bus[i], status1);
 124                 }
 125
 126                 if (dump_addr && in_mem) {
 127                         dump_addr[i*4]     = sdata->dbg_bus[i];
 128                         dump_addr[i*4 + 1] = status0;
 129                         dump_addr[i*4 + 2] = status1;
 130                         dump_addr[i*4 + 3] = 0x0;
 131                 }
 132         }
 133
 134         mdss_dsi_clk_ctrl(m_ctrl, m_ctrl->dsi_clk_handle,
 135                           MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF);
 136
 137         pr_info("========End DSI Debug Bus=========\n");
 138 }
 139
 140 static void mdss_dsi_pm_qos_add_request(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
 141 {
 142         struct irq_info *irq_info;
 143
 144         if (!ctrl_pdata || !ctrl_pdata->shared_data)
 145                 return;
 146
 147         irq_info = ctrl_pdata->dsi_hw->irq_info;
 148
 149         if (!irq_info)
 150                 return;
 151
 152         mutex_lock(&ctrl_pdata->shared_data->pm_qos_lock);
 153         if (!ctrl_pdata->shared_data->pm_qos_req_cnt) {
 154                 pr_debug("%s: add request irq\n", __func__);
 155
 156                 mdss_dsi_pm_qos_request.type = PM_QOS_REQ_AFFINE_IRQ;
 157                 mdss_dsi_pm_qos_request.irq = irq_info->irq;
 158                 pm_qos_add_request(&mdss_dsi_pm_qos_request,
 159                         PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 160         }
 161         ctrl_pdata->shared_data->pm_qos_req_cnt++;
 162         mutex_unlock(&ctrl_pdata->shared_data->pm_qos_lock);
 163 }
 164
 165 static void mdss_dsi_pm_qos_remove_request(struct dsi_shared_data *sdata)
 166 {
 167         if (!sdata)
 168                 return;
 169
 170         mutex_lock(&sdata->pm_qos_lock);
 171         if (sdata->pm_qos_req_cnt) {
 172                 sdata->pm_qos_req_cnt--;
 173                 if (!sdata->pm_qos_req_cnt) {
 174                         pr_debug("%s: remove request", __func__);
 175                         pm_qos_remove_request(&mdss_dsi_pm_qos_request);
 176                 }
 177         } else {
 178                 pr_warn("%s: unbalanced pm_qos ref count\n", __func__);
 179         }
 180         mutex_unlock(&sdata->pm_qos_lock);
 181 }
 182
 183 static void mdss_dsi_pm_qos_update_request(int val)
 184 {
 185         pr_debug("%s: update request %d", __func__, val);
 186         pm_qos_update_request(&mdss_dsi_pm_qos_request, val);
 187 }
 188
 189 static int mdss_dsi_pinctrl_set_state(struct mdss_dsi_ctrl_pdata *ctrl_pdata,
 190                                         bool active);
 191
 192 static struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl(u32 ctrl_id)
 193 {
 194         if (ctrl_id >= DSI_CTRL_MAX || !mdss_dsi_res)
 195                 return NULL;
 196
 197         return mdss_dsi_res->ctrl_pdata[ctrl_id];
 198 }
 199
 200 static void mdss_dsi_config_clk_src(struct platform_device *pdev)
 201 {
 202         struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev);
 203         struct dsi_shared_data *sdata = dsi_res->shared_data;
 204
 205         if (!sdata->ext_byte0_clk || !sdata->ext_pixel0_clk) {
 206                 pr_debug("%s: DSI-0 ext. clocks not present\n", __func__);
 207                 return;
 208         }
 209
 210         if (mdss_dsi_is_pll_src_default(sdata)) {
 211                 /*
 212                  * Default Mapping:
 213                  * 1. dual-dsi/single-dsi:
 214                  *     DSI0 <--> PLL0
 215                  *     DSI1 <--> PLL1
 216                  * 2. split-dsi:
 217                  *     DSI0 <--> PLL0
 218                  *     DSI1 <--> PLL0
 219                  */
 220                 sdata->byte0_parent = sdata->ext_byte0_clk;
 221                 sdata->pixel0_parent = sdata->ext_pixel0_clk;
 222
 223                 if (mdss_dsi_is_hw_config_split(sdata)) {
 224                         sdata->byte1_parent = sdata->byte0_parent;
 225                         sdata->pixel1_parent = sdata->pixel0_parent;
 226                 } else if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) {
 227                         sdata->byte1_parent = sdata->ext_byte1_clk;
 228                         sdata->pixel1_parent = sdata->ext_pixel1_clk;
 229                 } else {
 230                         pr_debug("%s: DSI-1 external clocks not present\n",
 231                                 __func__);
 232                         return;
 233                 }
 234
 235                 pr_debug("%s: default: DSI0 <--> PLL0, DSI1 <--> %s", __func__,
 236                         mdss_dsi_is_hw_config_split(sdata) ? "PLL0" : "PLL1");
 237         } else {
 238                 /*
 239                  * For split-dsi and single-dsi use cases, map the PLL source
 240                  * based on the pll source configuration. It is possible that
 241                  * for split-dsi case, the only supported config is to source
 242                  * the clocks from PLL0. This is not explictly checked here as
 243                  * it should have been already enforced when validating the
 244                  * board configuration.
 245                  */
 246                 if (mdss_dsi_is_pll_src_pll0(sdata)) {
 247                         pr_debug("%s: single source: PLL0", __func__);
 248                         sdata->byte0_parent = sdata->ext_byte0_clk;
 249                         sdata->pixel0_parent = sdata->ext_pixel0_clk;
 250                 } else if (mdss_dsi_is_pll_src_pll1(sdata)) {
 251                         if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) {
 252                                 pr_debug("%s: single source: PLL1", __func__);
 253                                 sdata->byte0_parent = sdata->ext_byte1_clk;
 254                                 sdata->pixel0_parent = sdata->ext_pixel1_clk;
 255                         } else {
 256                                 pr_err("%s: DSI-1 external clocks not present\n",
 257                                         __func__);
 258                                 return;
 259                         }
 260                 }
 261                 sdata->byte1_parent = sdata->byte0_parent;
 262                 sdata->pixel1_parent = sdata->pixel0_parent;
 263         }
 264
 265         return;
 266 }
 267
 268 static char const *mdss_dsi_get_clk_src(struct mdss_dsi_ctrl_pdata *ctrl)
 269 {
 270         struct dsi_shared_data *sdata;
 271
 272         if (!ctrl) {
 273                 pr_err("%s: Invalid input data\n", __func__);
 274                 return "????";
 275         }
 276
 277         sdata = ctrl->shared_data;
 278
 279         if (mdss_dsi_is_left_ctrl(ctrl)) {
 280                 if (sdata->byte0_parent == sdata->ext_byte0_clk)
 281                         return "PLL0";
 282                 else
 283                         return "PLL1";
 284         } else {
 285                 if (sdata->byte1_parent == sdata->ext_byte0_clk)
 286                         return "PLL0";
 287                 else
 288                         return "PLL1";
 289         }
 290 }
 291
 292 static int mdss_dsi_set_clk_src(struct mdss_dsi_ctrl_pdata *ctrl)
 293 {
 294         int rc;
 295         struct dsi_shared_data *sdata;
 296         struct clk *byte_parent, *pixel_parent;
 297
 298         if (!ctrl) {
 299                 pr_err("%s: Invalid input data\n", __func__);
 300                 return -EINVAL;
 301         }
 302
 303         sdata = ctrl->shared_data;
 304
 305         if (!ctrl->byte_clk_rcg || !ctrl->pixel_clk_rcg) {
 306                 pr_debug("%s: set_clk_src not needed\n", __func__);
 307                 return 0;
 308         }
 309
 310         if (mdss_dsi_is_left_ctrl(ctrl)) {
 311                 byte_parent = sdata->byte0_parent;
 312                 pixel_parent = sdata->pixel0_parent;
 313         } else {
 314                 byte_parent = sdata->byte1_parent;
 315                 pixel_parent = sdata->pixel1_parent;
 316         }
 317
 318         rc = clk_set_parent(ctrl->byte_clk_rcg, byte_parent);
 319         if (rc) {
 320                 pr_err("%s: failed to set parent for byte clk for ctrl%d. rc=%d\n",
 321                         __func__, ctrl->ndx, rc);
 322                 goto error;
 323         }
 324
 325         rc = clk_set_parent(ctrl->pixel_clk_rcg, pixel_parent);
 326         if (rc) {
 327                 pr_err("%s: failed to set parent for pixel clk for ctrl%d. rc=%d\n",
 328                         __func__, ctrl->ndx, rc);
 329                 goto error;
 330         }
 331
 332         pr_debug("%s: ctrl%d clock source set to %s", __func__, ctrl->ndx,
 333                 mdss_dsi_get_clk_src(ctrl));
 334
 335 error:
 336         return rc;
 337 }
 338
 339 static int mdss_dsi_regulator_init(struct platform_device *pdev,
 340                 struct dsi_shared_data *sdata)
 341 {
 342         int rc = 0, i = 0, j = 0;
 343
 344         if (!pdev || !sdata) {
 345                 pr_err("%s: invalid input\n", __func__);
 346                 return -EINVAL;
 347         }
 348
 349         for (i = DSI_CORE_PM; !rc && (i < DSI_MAX_PM); i++) {
 350                 rc = msm_dss_config_vreg(&pdev->dev,
 351                         sdata->power_data[i].vreg_config,
 352                         sdata->power_data[i].num_vreg, 1);
 353                 if (rc) {
 354                         pr_err("%s: failed to init vregs for %s\n",
 355                                 __func__, __mdss_dsi_pm_name(i));
 356                         for (j = i-1; j >= DSI_CORE_PM; j--) {
 357                                 msm_dss_config_vreg(&pdev->dev,
 358                                 sdata->power_data[j].vreg_config,
 359                                 sdata->power_data[j].num_vreg, 0);
 360                         }
 361                 }
 362         }
 363
 364         return rc;
 365 }
 366
 367 static int mdss_dsi_panel_power_off(struct mdss_panel_data *pdata)
 368 {
 369         int ret = 0;
 370         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
 371
 372         if (pdata == NULL) {
 373                 pr_err("%s: Invalid input data\n", __func__);
 374                 ret = -EINVAL;
 375                 goto end;
 376         }
 377
 378         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
 379                                 panel_data);
 380
 381         ret = mdss_dsi_panel_reset(pdata, 0);
 382         if (ret) {
 383                 pr_warn("%s: Panel reset failed. rc=%d\n", __func__, ret);
 384                 ret = 0;
 385         }
 386
 387         if (mdss_dsi_pinctrl_set_state(ctrl_pdata, false))
 388                 pr_debug("reset disable: pinctrl not enabled\n");
 389
 390         ret = msm_dss_enable_vreg(
 391                 ctrl_pdata->panel_power_data.vreg_config,
 392                 ctrl_pdata->panel_power_data.num_vreg, 0);
 393         if (ret)
 394                 pr_err("%s: failed to disable vregs for %s\n",
 395                         __func__, __mdss_dsi_pm_name(DSI_PANEL_PM));
 396
 397 end:
 398         return ret;
 399 }
 400
 401 static int mdss_dsi_panel_power_on(struct mdss_panel_data *pdata)
 402 {
 403         int ret = 0;
 404         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
 405
 406         if (pdata == NULL) {
 407                 pr_err("%s: Invalid input data\n", __func__);
 408                 return -EINVAL;
 409         }
 410
 411         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
 412                                 panel_data);
 413
 414         ret = msm_dss_enable_vreg(
 415                 ctrl_pdata->panel_power_data.vreg_config,
 416                 ctrl_pdata->panel_power_data.num_vreg, 1);
 417         if (ret) {
 418                 pr_err("%s: failed to enable vregs for %s\n",
 419                         __func__, __mdss_dsi_pm_name(DSI_PANEL_PM));
 420                 return ret;
 421         }
 422
 423         /*
 424          * If continuous splash screen feature is enabled, then we need to
 425          * request all the GPIOs that have already been configured in the
 426          * bootloader. This needs to be done irresepective of whether
 427          * the lp11_init flag is set or not.
 428          */
 429         if (pdata->panel_info.cont_splash_enabled ||
 430                 !pdata->panel_info.mipi.lp11_init) {
 431                 if (mdss_dsi_pinctrl_set_state(ctrl_pdata, true))
 432                         pr_debug("reset enable: pinctrl not enabled\n");
 433
 434                 ret = mdss_dsi_panel_reset(pdata, 1);
 435                 if (ret)
 436                         pr_err("%s: Panel reset failed. rc=%d\n",
 437                                         __func__, ret);
 438         }
 439
 440         return ret;
 441 }
 442
 443 static int mdss_dsi_panel_power_lp(struct mdss_panel_data *pdata, int enable)
 444 {
 445         /* Panel power control when entering/exiting lp mode */
 446         return 0;
 447 }
 448
 449 static int mdss_dsi_panel_power_ctrl(struct mdss_panel_data *pdata,
 450         int power_state)
 451 {
 452         int ret = 0;
 453         struct mdss_panel_info *pinfo;
 454
 455         if (pdata == NULL) {
 456                 pr_err("%s: Invalid input data\n", __func__);
 457                 return -EINVAL;
 458         }
 459
 460         pinfo = &pdata->panel_info;
 461         pr_debug("%s: cur_power_state=%d req_power_state=%d\n", __func__,
 462                 pinfo->panel_power_state, power_state);
 463
 464         if (pinfo->panel_power_state == power_state) {
 465                 pr_debug("%s: no change needed\n", __func__);
 466                 return 0;
 467         }
 468
 469         /*
 470          * If a dynamic mode switch is pending, the regulators should not
 471          * be turned off or on.
 472          */
 473         if (pdata->panel_info.dynamic_switch_pending)
 474                 return 0;
 475
 476         switch (power_state) {
 477         case MDSS_PANEL_POWER_OFF:
 478         case MDSS_PANEL_POWER_LCD_DISABLED:
 479                 /* if LCD has not been disabled, then disable it now */
 480                 if ((pinfo->panel_power_state != MDSS_PANEL_POWER_LCD_DISABLED)
 481                      && (pinfo->panel_power_state != MDSS_PANEL_POWER_OFF))
 482                         ret = mdss_dsi_panel_power_off(pdata);
 483                 break;
 484         case MDSS_PANEL_POWER_ON:
 485                 if (mdss_dsi_is_panel_on_lp(pdata))
 486                         ret = mdss_dsi_panel_power_lp(pdata, false);
 487                 else
 488                         ret = mdss_dsi_panel_power_on(pdata);
 489                 break;
 490         case MDSS_PANEL_POWER_LP1:
 491         case MDSS_PANEL_POWER_LP2:
 492                 ret = mdss_dsi_panel_power_lp(pdata, true);
 493                 break;
 494         default:
 495                 pr_err("%s: unknown panel power state requested (%d)\n",
 496                         __func__, power_state);
 497                 ret = -EINVAL;
 498         }
 499
 500         if (!ret)
 501                 pinfo->panel_power_state = power_state;
 502
 503         return ret;
 504 }
 505
 506 static void mdss_dsi_put_dt_vreg_data(struct device *dev,
 507         struct dss_module_power *module_power)
 508 {
 509         if (!module_power) {
 510                 pr_err("%s: invalid input\n", __func__);
 511                 return;
 512         }
 513
 514         if (module_power->vreg_config) {
 515                 devm_kfree(dev, module_power->vreg_config);
 516                 module_power->vreg_config = NULL;
 517         }
 518         module_power->num_vreg = 0;
 519 }
 520
 521 static int mdss_dsi_get_dt_vreg_data(struct device *dev,
 522         struct device_node *of_node, struct dss_module_power *mp,
 523         enum dsi_pm_type module)
 524 {
 525         int i = 0, rc = 0;
 526         u32 tmp = 0;
 527         struct device_node *supply_node = NULL;
 528         const char *pm_supply_name = NULL;
 529         struct device_node *supply_root_node = NULL;
 530
 531         if (!dev || !mp) {
 532                 pr_err("%s: invalid input\n", __func__);
 533                 rc = -EINVAL;
 534                 return rc;
 535         }
 536
 537         mp->num_vreg = 0;
 538         pm_supply_name = __mdss_dsi_pm_supply_node_name(module);
 539         supply_root_node = of_get_child_by_name(of_node, pm_supply_name);
 540         if (!supply_root_node) {
 541                 /*
 542                  * Try to get the root node for panel power supply using
 543                  * of_parse_phandle() API if of_get_child_by_name() API fails.
 544                  */
 545                 supply_root_node = of_parse_phandle(of_node, pm_supply_name, 0);
 546                 if (!supply_root_node) {
 547                         pr_err("no supply entry present: %s\n", pm_supply_name);
 548                         goto novreg;
 549                 }
 550         }
 551
 552
 553         for_each_child_of_node(supply_root_node, supply_node) {
 554                 mp->num_vreg++;
 555         }
 556
 557         if (mp->num_vreg == 0) {
 558                 pr_debug("%s: no vreg\n", __func__);
 559                 goto novreg;
 560         } else {
 561                 pr_debug("%s: vreg found. count=%d\n", __func__, mp->num_vreg);
 562         }
 563
 564         mp->vreg_config = devm_kzalloc(dev, sizeof(struct dss_vreg) *
 565                 mp->num_vreg, GFP_KERNEL);
 566         if (!mp->vreg_config) {
 567                 pr_err("%s: can't alloc vreg mem\n", __func__);
 568                 rc = -ENOMEM;
 569                 goto error;
 570         }
 571
 572         for_each_child_of_node(supply_root_node, supply_node) {
 573                 const char *st = NULL;
 574                 /* vreg-name */
 575                 rc = of_property_read_string(supply_node,
 576                         "qcom,supply-name", &st);
 577                 if (rc) {
 578                         pr_err("%s: error reading name. rc=%d\n",
 579                                 __func__, rc);
 580                         goto error;
 581                 }
 582                 snprintf(mp->vreg_config[i].vreg_name,
 583                         ARRAY_SIZE((mp->vreg_config[i].vreg_name)), "%s", st);
 584                 /* vreg-min-voltage */
 585                 rc = of_property_read_u32(supply_node,
 586                         "qcom,supply-min-voltage", &tmp);
 587                 if (rc) {
 588                         pr_err("%s: error reading min volt. rc=%d\n",
 589                                 __func__, rc);
 590                         goto error;
 591                 }
 592                 mp->vreg_config[i].min_voltage = tmp;
 593
 594                 /* vreg-max-voltage */
 595                 rc = of_property_read_u32(supply_node,
 596                         "qcom,supply-max-voltage", &tmp);
 597                 if (rc) {
 598                         pr_err("%s: error reading max volt. rc=%d\n",
 599                                 __func__, rc);
 600                         goto error;
 601                 }
 602                 mp->vreg_config[i].max_voltage = tmp;
 603
 604                 /* enable-load */
 605                 rc = of_property_read_u32(supply_node,
 606                         "qcom,supply-enable-load", &tmp);
 607                 if (rc) {
 608                         pr_err("%s: error reading enable load. rc=%d\n",
 609                                 __func__, rc);
 610                         goto error;
 611                 }
 612                 mp->vreg_config[i].enable_load = tmp;
 613
 614                 /* disable-load */
 615                 rc = of_property_read_u32(supply_node,
 616                         "qcom,supply-disable-load", &tmp);
 617                 if (rc) {
 618                         pr_err("%s: error reading disable load. rc=%d\n",
 619                                 __func__, rc);
 620                         goto error;
 621                 }
 622                 mp->vreg_config[i].disable_load = tmp;
 623
 624                 /* pre-sleep */
 625                 rc = of_property_read_u32(supply_node,
 626                         "qcom,supply-pre-on-sleep", &tmp);
 627                 if (rc) {
 628                         pr_debug("%s: error reading supply pre sleep value. rc=%d\n",
 629                                 __func__, rc);
 630                         rc = 0;
 631                 } else {
 632                         mp->vreg_config[i].pre_on_sleep = tmp;
 633                 }
 634
 635                 rc = of_property_read_u32(supply_node,
 636                         "qcom,supply-pre-off-sleep", &tmp);
 637                 if (rc) {
 638                         pr_debug("%s: error reading supply pre sleep value. rc=%d\n",
 639                                 __func__, rc);
 640                         rc = 0;
 641                 } else {
 642                         mp->vreg_config[i].pre_off_sleep = tmp;
 643                 }
 644
 645                 /* post-sleep */
 646                 rc = of_property_read_u32(supply_node,
 647                         "qcom,supply-post-on-sleep", &tmp);
 648                 if (rc) {
 649                         pr_debug("%s: error reading supply post sleep value. rc=%d\n",
 650                                 __func__, rc);
 651                         rc = 0;
 652                 } else {
 653                         mp->vreg_config[i].post_on_sleep = tmp;
 654                 }
 655
 656                 rc = of_property_read_u32(supply_node,
 657                         "qcom,supply-post-off-sleep", &tmp);
 658                 if (rc) {
 659                         pr_debug("%s: error reading supply post sleep value. rc=%d\n",
 660                                 __func__, rc);
 661                         rc = 0;
 662                 } else {
 663                         mp->vreg_config[i].post_off_sleep = tmp;
 664                 }
 665
 666                 mp->vreg_config[i].lp_disable_allowed =
 667                         of_property_read_bool(supply_node,
 668                         "qcom,supply-lp-mode-disable-allowed");
 669
 670                 pr_debug("%s: %s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d lp_disable_allowed=%d\n",
 671                         __func__,
 672                         mp->vreg_config[i].vreg_name,
 673                         mp->vreg_config[i].min_voltage,
 674                         mp->vreg_config[i].max_voltage,
 675                         mp->vreg_config[i].enable_load,
 676                         mp->vreg_config[i].disable_load,
 677                         mp->vreg_config[i].pre_on_sleep,
 678                         mp->vreg_config[i].post_on_sleep,
 679                         mp->vreg_config[i].pre_off_sleep,
 680                         mp->vreg_config[i].post_off_sleep,
 681                         mp->vreg_config[i].lp_disable_allowed);
 682                 ++i;
 683         }
 684
 685         return rc;
 686
 687 error:
 688         if (mp->vreg_config) {
 689                 devm_kfree(dev, mp->vreg_config);
 690                 mp->vreg_config = NULL;
 691         }
 692 novreg:
 693         mp->num_vreg = 0;
 694
 695         return rc;
 696 }
 697
 698 static int mdss_dsi_get_panel_cfg(char *panel_cfg,
 699                                 struct mdss_dsi_ctrl_pdata *ctrl)
 700 {
 701         int rc;
 702         struct mdss_panel_cfg *pan_cfg = NULL;
 703
 704         if (!panel_cfg)
 705                 return MDSS_PANEL_INTF_INVALID;
 706
 707         pan_cfg = ctrl->mdss_util->panel_intf_type(MDSS_PANEL_INTF_DSI);
 708         if (IS_ERR(pan_cfg)) {
 709                 return PTR_ERR(pan_cfg);
 710         } else if (!pan_cfg) {
 711                 panel_cfg[0] = 0;
 712                 return 0;
 713         }
 714
 715         pr_debug("%s:%d: cfg:[%s]\n", __func__, __LINE__,
 716                  pan_cfg->arg_cfg);
 717         rc = strlcpy(panel_cfg, pan_cfg->arg_cfg,
 718                      sizeof(pan_cfg->arg_cfg));
 719         return rc;
 720 }
 721
 722 struct buf_data {
 723         char *buf; /* cmd buf */
 724         int blen; /* cmd buf length */
 725         char *string_buf; /* cmd buf as string, 3 bytes per number */
 726         int sblen; /* string buffer length */
 727         int sync_flag;
 728         struct mutex dbg_mutex; /* mutex to synchronize read/write/flush */
 729 };
 730
 731 struct mdss_dsi_debugfs_info {
 732         struct dentry *root;
 733         struct mdss_dsi_ctrl_pdata ctrl_pdata;
 734         struct buf_data on_cmd;
 735         struct buf_data off_cmd;
 736         u32 override_flag;
 737 };
 738
 739 static int mdss_dsi_cmd_state_open(struct inode *inode, struct file *file)
 740 {
 741         /* non-seekable */
 742         file->private_data = inode->i_private;
 743         return nonseekable_open(inode, file);
 744 }
 745
 746 static ssize_t mdss_dsi_cmd_state_read(struct file *file, char __user *buf,
 747                                 size_t count, loff_t *ppos)
 748 {
 749         int *link_state = file->private_data;
 750         char buffer[32];
 751         int blen = 0;
 752
 753         if (*ppos)
 754                 return 0;
 755
 756         if ((*link_state) == DSI_HS_MODE)
 757                 blen = snprintf(buffer, sizeof(buffer), "dsi_hs_mode\n");
 758         else
 759                 blen = snprintf(buffer, sizeof(buffer), "dsi_lp_mode\n");
 760
 761         if (blen < 0)
 762                 return 0;
 763
 764         if (copy_to_user(buf, buffer, min(count, (size_t)blen+1)))
 765                 return -EFAULT;
 766
 767         *ppos += blen;
 768         return blen;
 769 }
 770
 771 static ssize_t mdss_dsi_cmd_state_write(struct file *file,
 772                         const char __user *p, size_t count, loff_t *ppos)
 773 {
 774         int *link_state = file->private_data;
 775         char *input;
 776
 777         if (!count) {
 778                 pr_err("%s: Zero bytes to be written\n", __func__);
 779                 return -EINVAL;
 780         }
 781
 782         input = kmalloc(count, GFP_KERNEL);
 783         if (!input) {
 784                 pr_err("%s: Failed to allocate memory\n", __func__);
 785                 return -ENOMEM;
 786         }
 787
 788         if (copy_from_user(input, p, count)) {
 789                 kfree(input);
 790                 return -EFAULT;
 791         }
 792         input[count-1] = '\0';
 793
 794         if (strnstr(input, "dsi_hs_mode", strlen("dsi_hs_mode")))
 795                 *link_state = DSI_HS_MODE;
 796         else
 797                 *link_state = DSI_LP_MODE;
 798
 799         kfree(input);
 800         return count;
 801 }
 802
 803 static const struct file_operations mdss_dsi_cmd_state_fop = {
 804         .open = mdss_dsi_cmd_state_open,
 805         .read = mdss_dsi_cmd_state_read,
 806         .write = mdss_dsi_cmd_state_write,
 807 };
 808
 809 static int mdss_dsi_cmd_open(struct inode *inode, struct file *file)
 810 {
 811         /* non-seekable */
 812         file->private_data = inode->i_private;
 813         return nonseekable_open(inode, file);
 814 }
 815
 816 static ssize_t mdss_dsi_cmd_read(struct file *file, char __user *buf,
 817                                  size_t count, loff_t *ppos)
 818 {
 819         struct buf_data *pcmds = file->private_data;
 820         char *bp;
 821         ssize_t ret = 0;
 822
 823         mutex_lock(&pcmds->dbg_mutex);
 824         if (*ppos == 0) {
 825                 kfree(pcmds->string_buf);
 826                 pcmds->string_buf = NULL;
 827                 pcmds->sblen = 0;
 828         }
 829
 830         if (!pcmds->string_buf) {
 831                 /*
 832                  * Buffer size is the sum of cmd length (3 bytes per number)
 833                  * with NULL terminater
 834                  */
 835                 int bsize = ((pcmds->blen)*3 + 1);
 836                 int blen = 0;
 837                 char *buffer;
 838
 839                 buffer = kmalloc(bsize, GFP_KERNEL);
 840                 if (!buffer) {
 841                         pr_err("%s: Failed to allocate memory\n", __func__);
 842                         mutex_unlock(&pcmds->dbg_mutex);
 843                         return -ENOMEM;
 844                 }
 845
 846                 bp = pcmds->buf;
 847                 while ((blen < (bsize-1)) &&
 848                        (bp < ((pcmds->buf) + (pcmds->blen)))) {
 849                         struct dsi_ctrl_hdr dchdr =
 850                                         *((struct dsi_ctrl_hdr *)bp);
 851                         int dhrlen = sizeof(dchdr), dlen;
 852                         char *tmp = (char *)(&dchdr);
 853                         dlen = dchdr.dlen;
 854                         dchdr.dlen = htons(dchdr.dlen);
 855                         while (dhrlen--)
 856                                 blen += snprintf(buffer+blen, bsize-blen,
 857                                                  "%02x ", (*tmp++));
 858
 859                         bp += sizeof(dchdr);
 860                         while (dlen--)
 861                                 blen += snprintf(buffer+blen, bsize-blen,
 862                                                  "%02x ", (*bp++));
 863                         buffer[blen-1] = '\n';
 864                 }
 865                 buffer[blen] = '\0';
 866                 pcmds->string_buf = buffer;
 867                 pcmds->sblen = blen;
 868         }
 869
 870         /*
 871          * The max value of count is PAGE_SIZE(4096).
 872          * It may need multiple times of reading if string buf is too large
 873          */
 874         if (*ppos >= (pcmds->sblen)) {
 875                 kfree(pcmds->string_buf);
 876                 pcmds->string_buf = NULL;
 877                 pcmds->sblen = 0;
 878                 mutex_unlock(&pcmds->dbg_mutex);
 879                 return 0; /* the end */
 880         }
 881         ret = simple_read_from_buffer(buf, count, ppos, pcmds->string_buf,
 882                                       pcmds->sblen);
 883         mutex_unlock(&pcmds->dbg_mutex);
 884         return ret;
 885 }
 886
 887 static ssize_t mdss_dsi_cmd_write(struct file *file, const char __user *p,
 888                                   size_t count, loff_t *ppos)
 889 {
 890         struct buf_data *pcmds = file->private_data;
 891         ssize_t ret = 0;
 892         unsigned int blen = 0;
 893         char *string_buf;
 894
 895         mutex_lock(&pcmds->dbg_mutex);
 896         if (*ppos == 0) {
 897                 kfree(pcmds->string_buf);
 898                 pcmds->string_buf = NULL;
 899                 pcmds->sblen = 0;
 900         }
 901
 902         /* Allocate memory for the received string */
 903         blen = count + (pcmds->sblen);
 904         if (blen > U32_MAX - 1) {
 905                 mutex_unlock(&pcmds->dbg_mutex);
 906                 return -EINVAL;
 907         }
 908
 909         string_buf = krealloc(pcmds->string_buf, blen + 1, GFP_KERNEL);
 910         if (!string_buf) {
 911                 pr_err("%s: Failed to allocate memory\n", __func__);
 912                 mutex_unlock(&pcmds->dbg_mutex);
 913                 return -ENOMEM;
 914         }
 915
 916         pcmds->string_buf = string_buf;
 917         /* Writing in batches is possible */
 918         ret = simple_write_to_buffer(string_buf, blen, ppos, p, count);
 919         if (ret < 0) {
 920                 pr_err("%s: Failed to copy data\n", __func__);
 921                 mutex_unlock(&pcmds->dbg_mutex);
 922                 return -EINVAL;
 923         }
 924
 925         string_buf[ret] = '\0';
 926         pcmds->sblen = count;
 927         mutex_unlock(&pcmds->dbg_mutex);
 928         return ret;
 929 }
 930
 931 static int mdss_dsi_cmd_flush(struct file *file, fl_owner_t id)
 932 {
 933         struct buf_data *pcmds = file->private_data;
 934         unsigned int len;
 935         int blen, i;
 936         char *buf, *bufp, *bp;
 937         struct dsi_ctrl_hdr *dchdr;
 938
 939         mutex_lock(&pcmds->dbg_mutex);
 940
 941         if (!pcmds->string_buf) {
 942                 mutex_unlock(&pcmds->dbg_mutex);
 943                 return 0;
 944         }
 945
 946         /*
 947          * Allocate memory for command buffer
 948          * 3 bytes per number, and 2 bytes for the last one
 949          */
 950         blen = ((pcmds->sblen) + 2) / 3;
 951         buf = kzalloc(blen, GFP_KERNEL);
 952         if (!buf) {
 953                 pr_err("%s: Failed to allocate memory\n", __func__);
 954                 kfree(pcmds->string_buf);
 955                 pcmds->string_buf = NULL;
 956                 pcmds->sblen = 0;
 957                 mutex_unlock(&pcmds->dbg_mutex);
 958                 return -ENOMEM;
 959         }
 960
 961         /* Translate the input string to command array */
 962         bufp = pcmds->string_buf;
 963         for (i = 0; i < blen; i++) {
 964                 uint32_t value = 0;
 965                 int step = 0;
 966                 if (sscanf(bufp, "%02x%n", &value, &step) > 0) {
 967                         *(buf+i) = (char)value;
 968                         bufp += step;
 969                 }
 970         }
 971
 972         /* Scan dcs commands */
 973         bp = buf;
 974         len = blen;
 975         while (len >= sizeof(*dchdr)) {
 976                 dchdr = (struct dsi_ctrl_hdr *)bp;
 977                 dchdr->dlen = ntohs(dchdr->dlen);
 978                 if (dchdr->dlen > (len - sizeof(*dchdr)) || dchdr->dlen < 0) {
 979                         pr_err("%s: dtsi cmd=%x error, len=%d\n",
 980                                 __func__, dchdr->dtype, dchdr->dlen);
 981                         kfree(buf);
 982                         mutex_unlock(&pcmds->dbg_mutex);
 983                         return -EINVAL;
 984                 }
 985                 bp += sizeof(*dchdr);
 986                 len -= sizeof(*dchdr);
 987                 bp += dchdr->dlen;
 988                 len -= dchdr->dlen;
 989         }
 990         if (len != 0) {
 991                 pr_err("%s: dcs_cmd=%x len=%d error!\n", __func__,
 992                                 bp[0], len);
 993                 kfree(buf);
 994                 mutex_unlock(&pcmds->dbg_mutex);
 995                 return -EINVAL;
 996         }
 997
 998         if (pcmds->sync_flag) {
 999                 pcmds->buf = buf;
1000                 pcmds->blen = blen;
1001                 pcmds->sync_flag = 0;
1002         } else {
1003                 kfree(pcmds->buf);
1004                 pcmds->buf = buf;
1005                 pcmds->blen = blen;
1006         }
1007         mutex_unlock(&pcmds->dbg_mutex);
1008         return 0;
1009 }
1010
1011 static const struct file_operations mdss_dsi_cmd_fop = {
1012         .open = mdss_dsi_cmd_open,
1013         .read = mdss_dsi_cmd_read,
1014         .write = mdss_dsi_cmd_write,
1015         .flush = mdss_dsi_cmd_flush,
1016 };
1017
1018 struct dentry *dsi_debugfs_create_dcs_cmd(const char *name, umode_t mode,
1019                                 struct dentry *parent, struct buf_data *cmd,
1020                                 struct dsi_panel_cmds ctrl_cmds)
1021 {
1022         mutex_init(&cmd->dbg_mutex);
1023         cmd->buf = ctrl_cmds.buf;
1024         cmd->blen = ctrl_cmds.blen;
1025         cmd->string_buf = NULL;
1026         cmd->sblen = 0;
1027         cmd->sync_flag = 1;
1028
1029         return debugfs_create_file(name, mode, parent,
1030                                    cmd, &mdss_dsi_cmd_fop);
1031 }
1032
1033 #define DEBUGFS_CREATE_DCS_CMD(name, node, cmd, ctrl_cmd) \
1034         dsi_debugfs_create_dcs_cmd(name, 0644, node, cmd, ctrl_cmd)
1035
1036 static int mdss_dsi_debugfs_setup(struct mdss_panel_data *pdata,
1037                         struct dentry *parent)
1038 {
1039         struct mdss_dsi_ctrl_pdata *ctrl_pdata, *dfs_ctrl;
1040         struct mdss_dsi_debugfs_info *dfs;
1041
1042         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1043                                 panel_data);
1044
1045         dfs = kzalloc(sizeof(*dfs), GFP_KERNEL);
1046         if (!dfs) {
1047                 pr_err("%s: No memory to create dsi ctrl debugfs info",
1048                         __func__);
1049                 return -ENOMEM;
1050         }
1051
1052         dfs->root = debugfs_create_dir("dsi_ctrl_pdata", parent);
1053         if (IS_ERR_OR_NULL(dfs->root)) {
1054 #ifdef CONFIG_DEBUG_FS
1055                 pr_err("%s: debugfs_create_dir dsi fail, error %ld\n",
1056                         __func__, PTR_ERR(dfs->root));
1057 #endif
1058                 kfree(dfs);
1059                 return -ENODEV;
1060         }
1061
1062         dfs_ctrl = &dfs->ctrl_pdata;
1063         debugfs_create_u32("override_flag", 0644, dfs->root,
1064                            &dfs->override_flag);
1065
1066         debugfs_create_bool("cmd_sync_wait_broadcast", 0644, dfs->root,
1067                             &dfs_ctrl->cmd_sync_wait_broadcast);
1068         debugfs_create_bool("cmd_sync_wait_trigger", 0644, dfs->root,
1069                             &dfs_ctrl->cmd_sync_wait_trigger);
1070
1071         debugfs_create_file("dsi_on_cmd_state", 0644, dfs->root,
1072                 &dfs_ctrl->on_cmds.link_state, &mdss_dsi_cmd_state_fop);
1073         debugfs_create_file("dsi_off_cmd_state", 0644, dfs->root,
1074                 &dfs_ctrl->off_cmds.link_state, &mdss_dsi_cmd_state_fop);
1075
1076         DEBUGFS_CREATE_DCS_CMD("dsi_on_cmd", dfs->root, &dfs->on_cmd,
1077                                 ctrl_pdata->on_cmds);
1078         DEBUGFS_CREATE_DCS_CMD("dsi_off_cmd", dfs->root, &dfs->off_cmd,
1079                                 ctrl_pdata->off_cmds);
1080
1081         debugfs_create_u32("dsi_err_counter", 0644, dfs->root,
1082                            &dfs_ctrl->err_cont.max_err_index);
1083         debugfs_create_u32("dsi_err_time_delta", 0644, dfs->root,
1084                            &dfs_ctrl->err_cont.err_time_delta);
1085
1086         dfs->override_flag = 0;
1087         dfs->ctrl_pdata = *ctrl_pdata;
1088         ctrl_pdata->debugfs_info = dfs;
1089         return 0;
1090 }
1091
1092 static int mdss_dsi_debugfs_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
1093 {
1094         int rc;
1095         struct mdss_panel_data *pdata;
1096         struct mdss_panel_info panel_info;
1097
1098         if (!ctrl_pdata) {
1099                 pr_warn_once("%s: Invalid pdata!\n", __func__);
1100                 return -EINVAL;
1101         }
1102
1103         pdata = &ctrl_pdata->panel_data;
1104         if (!pdata)
1105                 return -EINVAL;
1106
1107         panel_info = pdata->panel_info;
1108         rc = mdss_dsi_debugfs_setup(pdata, panel_info.debugfs_info->root);
1109         if (rc) {
1110 #ifdef CONFIG_DEBUG_FS
1111                 pr_err("%s: Error in initilizing dsi ctrl debugfs\n",
1112                                 __func__);
1113 #endif
1114                 return rc;
1115         }
1116
1117         pr_debug("%s: Initialized mdss_dsi_debugfs_init\n", __func__);
1118         return 0;
1119 }
1120
1121 static void mdss_dsi_debugfs_cleanup(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
1122 {
1123         struct mdss_panel_data *pdata = &ctrl_pdata->panel_data;
1124
1125         do {
1126                 struct mdss_dsi_ctrl_pdata *ctrl = container_of(pdata,
1127                         struct mdss_dsi_ctrl_pdata, panel_data);
1128                 struct mdss_dsi_debugfs_info *dfs = ctrl->debugfs_info;
1129                 if (dfs && dfs->root)
1130                         debugfs_remove_recursive(dfs->root);
1131                 kfree(dfs);
1132                 pdata = pdata->next;
1133         } while (pdata);
1134         pr_debug("%s: Cleaned up mdss_dsi_debugfs_info\n", __func__);
1135 }
1136
1137 static int _mdss_dsi_refresh_cmd(struct buf_data *new_cmds,
1138         struct dsi_panel_cmds *original_pcmds)
1139 {
1140         char *bp;
1141         int len, cnt, i;
1142         struct dsi_ctrl_hdr *dchdr;
1143         struct dsi_cmd_desc *cmds;
1144
1145         if (new_cmds->sync_flag)
1146                 return 0;
1147
1148         bp = new_cmds->buf;
1149         len = new_cmds->blen;
1150         cnt = 0;
1151         /* Scan dcs commands and get dcs command count */
1152         while (len >= sizeof(*dchdr)) {
1153                 dchdr = (struct dsi_ctrl_hdr *)bp;
1154                 if (dchdr->dlen > len) {
1155                         pr_err("%s: dtsi cmd=%x error, len=%d\n",
1156                                 __func__, dchdr->dtype, dchdr->dlen);
1157                         return -EINVAL;
1158                 }
1159                 bp += sizeof(*dchdr) + dchdr->dlen;
1160                 len -= sizeof(*dchdr) + dchdr->dlen;
1161                 cnt++;
1162         }
1163
1164         if (len != 0) {
1165                 pr_err("%s: dcs_cmd=%x len=%d error!\n", __func__,
1166                                 bp[0], len);
1167                 return -EINVAL;
1168         }
1169
1170         /* Reallocate space for dcs commands */
1171         cmds = kzalloc(cnt * sizeof(struct dsi_cmd_desc), GFP_KERNEL);
1172         if (!cmds) {
1173                 pr_err("%s: Failed to allocate memory\n", __func__);
1174                 return -ENOMEM;
1175         }
1176         kfree(original_pcmds->buf);
1177         kfree(original_pcmds->cmds);
1178         original_pcmds->cmd_cnt = cnt;
1179         original_pcmds->cmds = cmds;
1180         original_pcmds->buf = new_cmds->buf;
1181         original_pcmds->blen = new_cmds->blen;
1182
1183         bp = original_pcmds->buf;
1184         len = original_pcmds->blen;
1185         for (i = 0; i < cnt; i++) {
1186                 dchdr = (struct dsi_ctrl_hdr *)bp;
1187                 len -= sizeof(*dchdr);
1188                 bp += sizeof(*dchdr);
1189                 original_pcmds->cmds[i].dchdr = *dchdr;
1190                 original_pcmds->cmds[i].payload = bp;
1191                 bp += dchdr->dlen;
1192                 len -= dchdr->dlen;
1193         }
1194
1195         new_cmds->sync_flag = 1;
1196         return 0;
1197 }
1198
1199 static void mdss_dsi_debugfsinfo_to_dsictrl_info(
1200                         struct mdss_dsi_ctrl_pdata *ctrl_pdata)
1201 {
1202         struct mdss_dsi_debugfs_info *dfs = ctrl_pdata->debugfs_info;
1203         struct dsi_err_container *dfs_err_cont = &dfs->ctrl_pdata.err_cont;
1204         struct dsi_err_container *err_cont = &ctrl_pdata->err_cont;
1205
1206         ctrl_pdata->cmd_sync_wait_broadcast =
1207                         dfs->ctrl_pdata.cmd_sync_wait_broadcast;
1208         ctrl_pdata->cmd_sync_wait_trigger =
1209                         dfs->ctrl_pdata.cmd_sync_wait_trigger;
1210
1211         _mdss_dsi_refresh_cmd(&dfs->on_cmd, &ctrl_pdata->on_cmds);
1212         _mdss_dsi_refresh_cmd(&dfs->off_cmd, &ctrl_pdata->off_cmds);
1213
1214         ctrl_pdata->on_cmds.link_state =
1215                         dfs->ctrl_pdata.on_cmds.link_state;
1216         ctrl_pdata->off_cmds.link_state =
1217                         dfs->ctrl_pdata.off_cmds.link_state;
1218
1219         /* keep error counter between 2 to 10 */
1220         if (dfs_err_cont->max_err_index >= 2 &&
1221                 dfs_err_cont->max_err_index <= MAX_ERR_INDEX) {
1222                 err_cont->max_err_index = dfs_err_cont->max_err_index;
1223         } else {
1224                 dfs_err_cont->max_err_index = err_cont->max_err_index;
1225                 pr_warn("resetting the dsi error counter to %d\n",
1226                         err_cont->max_err_index);
1227         }
1228
1229         /* keep error duration between 16 ms to 100 seconds */
1230         if (dfs_err_cont->err_time_delta >= 16 &&
1231                 dfs_err_cont->err_time_delta <= 100000) {
1232                 err_cont->err_time_delta = dfs_err_cont->err_time_delta;
1233         } else {
1234                 dfs_err_cont->err_time_delta = err_cont->err_time_delta;
1235                 pr_warn("resetting the dsi error time delta to %d ms\n",
1236                         err_cont->err_time_delta);
1237         }
1238 }
1239
1240 static void mdss_dsi_validate_debugfs_info(
1241                 struct mdss_dsi_ctrl_pdata *ctrl_pdata)
1242 {
1243         struct mdss_dsi_debugfs_info *dfs = ctrl_pdata->debugfs_info;
1244
1245         if (dfs->override_flag) {
1246                 pr_debug("%s: Overriding dsi ctrl_pdata with debugfs data\n",
1247                         __func__);
1248                 dfs->override_flag = 0;
1249                 mdss_dsi_debugfsinfo_to_dsictrl_info(ctrl_pdata);
1250         }
1251 }
1252
1253 /**
1254  * mdss_dsi_clamp_phy_reset_config() - configure DSI phy reset mask
1255  * @ctrl: pointer to DSI controller structure
1256  * @enable: true to mask the reset signal, false to unmask
1257  *
1258  * Configure the register to mask/unmask the propagation of the mdss ahb
1259  * clock reset signal to the DSI PHY. This would be necessary when the MDSS
1260  * core is idle power collapsed with the DSI panel on. This function assumes
1261  * that the mmss_misc_ahb clock is already on.
1262  */
1263 static int mdss_dsi_clamp_phy_reset_config(struct mdss_dsi_ctrl_pdata *ctrl,
1264         bool enable)
1265 {
1266         u32 regval;
1267
1268         if (!ctrl) {
1269                 pr_warn_ratelimited("%s: invalid input\n", __func__);
1270                 return -EINVAL;
1271         }
1272
1273         if (!ctrl->mmss_misc_io.base) {
1274                 pr_warn_ratelimited("%s: mmss_misc_io not mapped\n", __func__);
1275                 return -EINVAL;
1276         }
1277
1278         if ((ctrl->shared_data->hw_rev >= MDSS_DSI_HW_REV_104) &&
1279                 (MDSS_GET_STEP(ctrl->shared_data->hw_rev) !=
1280                 MDSS_DSI_HW_REV_STEP_2)) {
1281                 u32 clamp_reg_off = ctrl->shared_data->ulps_clamp_ctrl_off;
1282
1283                 regval = MIPI_INP(ctrl->mmss_misc_io.base + clamp_reg_off);
1284                 if (enable)
1285                         regval = regval | BIT(30);
1286                 else
1287                         regval = regval & ~BIT(30);
1288                 MIPI_OUTP(ctrl->mmss_misc_io.base + clamp_reg_off, regval);
1289         } else {
1290                 u32 phyrst_reg_off = ctrl->shared_data->ulps_phyrst_ctrl_off;
1291
1292                 if (enable)
1293                         regval = BIT(0);
1294                 else
1295                         regval = 0;
1296                 MIPI_OUTP(ctrl->mmss_misc_io.base + phyrst_reg_off, regval);
1297         }
1298
1299         /* make sure that clamp ctrl is updated */
1300         wmb();
1301
1302         return 0;
1303 }
1304
1305 static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state)
1306 {
1307         int ret = 0;
1308         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1309         struct mdss_panel_info *panel_info = NULL;
1310
1311         if (pdata == NULL) {
1312                 pr_err("%s: Invalid input data\n", __func__);
1313                 return -EINVAL;
1314         }
1315
1316         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1317                                 panel_data);
1318
1319         panel_info = &ctrl_pdata->panel_data.panel_info;
1320
1321         pr_info("%s+: ctrl=%pK ndx=%d power_state=%d\n",
1322                 __func__, ctrl_pdata, ctrl_pdata->ndx, power_state);
1323         ctrl_pdata->dsi_pipe_ready = false;
1324
1325         if (power_state == panel_info->panel_power_state) {
1326                 pr_debug("%s: No change in power state %d -> %d\n", __func__,
1327                         panel_info->panel_power_state, power_state);
1328                 goto end;
1329         }
1330
1331         if (mdss_panel_is_power_on(power_state)) {
1332                 pr_debug("%s: dsi_off with panel always on\n", __func__);
1333                 goto panel_power_ctrl;
1334         }
1335
1336         /*
1337          * Link clocks should be turned off before PHY can be disabled.
1338          * For command mode panels, all clocks are turned off prior to reaching
1339          * here, so core clocks should be turned on before accessing hardware
1340          * registers. For video mode panel, turn off link clocks and then
1341          * disable PHY
1342          */
1343         if (pdata->panel_info.type == MIPI_CMD_PANEL)
1344                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1345                                         MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
1346         else
1347                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1348                                   MDSS_DSI_LINK_CLK, MDSS_DSI_CLK_OFF);
1349
1350         if (!pdata->panel_info.ulps_suspend_enabled) {
1351                 /* disable DSI controller */
1352                 mdss_dsi_controller_cfg(0, pdata);
1353
1354                 /* disable DSI phy */
1355                 mdss_dsi_phy_disable(ctrl_pdata);
1356         }
1357         ctrl_pdata->ctrl_state &= ~CTRL_STATE_DSI_ACTIVE;
1358         mdss_dsi_clamp_phy_reset_config(ctrl_pdata, false);
1359         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1360                           MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF);
1361
1362 panel_power_ctrl:
1363         ret = mdss_dsi_panel_power_ctrl(pdata, power_state);
1364         if (ret) {
1365                 pr_err("%s: Panel power off failed\n", __func__);
1366                 goto end;
1367         }
1368
1369         if (panel_info->dynamic_fps
1370             && (panel_info->dfps_update == DFPS_SUSPEND_RESUME_MODE)
1371             && (panel_info->new_fps != panel_info->mipi.frame_rate))
1372                 panel_info->mipi.frame_rate = panel_info->new_fps;
1373
1374         /* Initialize Max Packet size for DCS reads */
1375         ctrl_pdata->cur_max_pkt_size = 0;
1376 end:
1377         pr_info("%s-:\n", __func__);
1378
1379         return ret;
1380 }
1381
1382 int mdss_dsi_switch_mode(struct mdss_panel_data *pdata, int mode)
1383 {
1384         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1385         struct mipi_panel_info *pinfo;
1386         bool dsi_ctrl_setup_needed = false;
1387
1388         if (!pdata) {
1389                 pr_err("%s: Invalid input data\n", __func__);
1390                 return -EINVAL;
1391         }
1392         pr_debug("%s, start\n", __func__);
1393
1394         pinfo = &pdata->panel_info.mipi;
1395         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1396                 panel_data);
1397
1398         if ((pinfo->dms_mode != DYNAMIC_MODE_RESOLUTION_SWITCH_IMMEDIATE) &&
1399                         (pinfo->dms_mode != DYNAMIC_MODE_SWITCH_IMMEDIATE)) {
1400                 pr_debug("%s: Dynamic mode switch not enabled.\n", __func__);
1401                 return -EPERM;
1402         }
1403
1404         if (mode == MIPI_VIDEO_PANEL) {
1405                 mode = SWITCH_TO_VIDEO_MODE;
1406         } else if (mode == MIPI_CMD_PANEL) {
1407                 mode = SWITCH_TO_CMD_MODE;
1408         } else if (mode == SWITCH_RESOLUTION) {
1409                 dsi_ctrl_setup_needed = true;
1410                 pr_debug("Resolution switch mode selected\n");
1411         } else {
1412                 pr_err("Invalid mode selected, mode=%d\n", mode);
1413                 return -EINVAL;
1414         }
1415
1416         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1417                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1418         if (dsi_ctrl_setup_needed)
1419                 mdss_dsi_ctrl_setup(ctrl_pdata);
1420
1421         ATRACE_BEGIN("switch_cmds");
1422         ctrl_pdata->switch_mode(pdata, mode);
1423         ATRACE_END("switch_cmds");
1424
1425         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1426                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1427
1428         pr_debug("%s, end\n", __func__);
1429         return 0;
1430 }
1431
1432 static int mdss_dsi_reconfig(struct mdss_panel_data *pdata, int mode)
1433 {
1434         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1435         struct mipi_panel_info *pinfo;
1436
1437         if (!pdata) {
1438                 pr_err("%s: Invalid input data\n", __func__);
1439                 return -EINVAL;
1440         }
1441         pr_debug("%s, start\n", __func__);
1442
1443         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1444                 panel_data);
1445         pinfo = &pdata->panel_info.mipi;
1446
1447         if (pinfo->dms_mode == DYNAMIC_MODE_SWITCH_IMMEDIATE) {
1448                 /* reset DSI */
1449                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1450                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1451                 mdss_dsi_sw_reset(ctrl_pdata, true);
1452                 mdss_dsi_ctrl_setup(ctrl_pdata);
1453                 mdss_dsi_controller_cfg(true, pdata);
1454                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1455                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1456         }
1457
1458         pr_debug("%s, end\n", __func__);
1459         return 0;
1460 }
1461 static int mdss_dsi_update_panel_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata,
1462                                 int mode)
1463 {
1464         int ret = 0;
1465         struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
1466
1467         if (mode == DSI_CMD_MODE) {
1468                 pinfo->mipi.mode = DSI_CMD_MODE;
1469                 pinfo->type = MIPI_CMD_PANEL;
1470                 pinfo->mipi.vsync_enable = 1;
1471                 pinfo->mipi.hw_vsync_mode = 1;
1472                 pinfo->partial_update_enabled = pinfo->partial_update_supported;
1473         } else {        /*video mode*/
1474                 pinfo->mipi.mode = DSI_VIDEO_MODE;
1475                 pinfo->type = MIPI_VIDEO_PANEL;
1476                 pinfo->mipi.vsync_enable = 0;
1477                 pinfo->mipi.hw_vsync_mode = 0;
1478                 pinfo->partial_update_enabled = 0;
1479         }
1480
1481         ctrl_pdata->panel_mode = pinfo->mipi.mode;
1482         mdss_panel_get_dst_fmt(pinfo->bpp, pinfo->mipi.mode,
1483                         pinfo->mipi.pixel_packing, &(pinfo->mipi.dst_format));
1484         return ret;
1485 }
1486
1487 int mdss_dsi_on(struct mdss_panel_data *pdata)
1488 {
1489         int ret = 0;
1490         struct mdss_panel_info *pinfo;
1491         struct mipi_panel_info *mipi;
1492         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1493         int cur_power_state;
1494
1495         if (pdata == NULL) {
1496                 pr_err("%s: Invalid input data\n", __func__);
1497                 return -EINVAL;
1498         }
1499
1500         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1501                                 panel_data);
1502
1503         if (ctrl_pdata->debugfs_info)
1504                 mdss_dsi_validate_debugfs_info(ctrl_pdata);
1505
1506         cur_power_state = pdata->panel_info.panel_power_state;
1507         pr_info("%s+: ctrl=%pK ndx=%d cur_power_state=%d\n", __func__,
1508                 ctrl_pdata, ctrl_pdata->ndx, cur_power_state);
1509
1510         pinfo = &pdata->panel_info;
1511         mipi = &pdata->panel_info.mipi;
1512
1513         if (mdss_dsi_is_panel_on_interactive(pdata)) {
1514                 /*
1515                  * all interrupts are disabled at LK
1516                  * for cont_splash case, intr mask bits need
1517                  * to be restored to allow dcs command be
1518                  * sent to panel
1519                  */
1520                 mdss_dsi_restore_intr_mask(ctrl_pdata);
1521                 pr_debug("%s: panel already on\n", __func__);
1522                 goto end;
1523         }
1524
1525         ret = mdss_dsi_panel_power_ctrl(pdata, MDSS_PANEL_POWER_ON);
1526         if (ret) {
1527                 pr_err("%s:Panel power on failed. rc=%d\n", __func__, ret);
1528                 goto end;
1529         }
1530
1531         if (mdss_panel_is_power_on(cur_power_state)) {
1532                 pr_debug("%s: dsi_on from panel low power state\n", __func__);
1533                 goto end;
1534         }
1535
1536         ret = mdss_dsi_set_clk_src(ctrl_pdata);
1537         if (ret) {
1538                 pr_err("%s: failed to set clk src. rc=%d\n", __func__, ret);
1539                 goto end;
1540         }
1541
1542         /*
1543          * Enable DSI core clocks prior to resetting and initializing DSI
1544          * Phy. Phy and ctrl setup need to be done before enabling the link
1545          * clocks.
1546          */
1547         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1548                           MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
1549
1550         /*
1551          * If ULPS during suspend feature is enabled, then DSI PHY was
1552          * left on during suspend. In this case, we do not need to reset/init
1553          * PHY. This would have already been done when the CORE clocks are
1554          * turned on. However, if cont splash is disabled, the first time DSI
1555          * is powered on, phy init needs to be done unconditionally.
1556          */
1557         if (!pdata->panel_info.ulps_suspend_enabled || !ctrl_pdata->ulps) {
1558                 mdss_dsi_phy_sw_reset(ctrl_pdata);
1559                 mdss_dsi_phy_init(ctrl_pdata);
1560                 mdss_dsi_ctrl_setup(ctrl_pdata);
1561         }
1562         ctrl_pdata->ctrl_state |= CTRL_STATE_DSI_ACTIVE;
1563
1564         mdss_dsi_clamp_phy_reset_config(ctrl_pdata, true);
1565
1566         /* DSI link clocks need to be on prior to ctrl sw reset */
1567         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1568                           MDSS_DSI_LINK_CLK, MDSS_DSI_CLK_ON);
1569         mdss_dsi_sw_reset(ctrl_pdata, true);
1570
1571         /*
1572          * Issue hardware reset line after enabling the DSI clocks and data
1573          * data lanes for LP11 init
1574          */
1575         if (mipi->lp11_init) {
1576                 if (mdss_dsi_pinctrl_set_state(ctrl_pdata, true))
1577                         pr_debug("reset enable: pinctrl not enabled\n");
1578                 mdss_dsi_panel_reset(pdata, 1);
1579         }
1580
1581         if (mipi->init_delay)
1582                 usleep_range(mipi->init_delay, mipi->init_delay);
1583
1584         if (pdata->panel_info.type == MIPI_CMD_PANEL)
1585                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1586                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1587
1588 end:
1589         ctrl_pdata->dsi_pipe_ready = true;
1590         pr_info("%s-:\n", __func__);
1591         return ret;
1592 }
1593
1594 static int mdss_dsi_pinctrl_set_state(
1595         struct mdss_dsi_ctrl_pdata *ctrl_pdata,
1596         bool active)
1597 {
1598         struct pinctrl_state *pin_state;
1599         struct mdss_panel_info *pinfo = NULL;
1600         int rc = -EFAULT;
1601
1602         if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.pinctrl))
1603                 return PTR_ERR(ctrl_pdata->pin_res.pinctrl);
1604
1605         pinfo = &ctrl_pdata->panel_data.panel_info;
1606         if ((mdss_dsi_is_right_ctrl(ctrl_pdata) &&
1607                 mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data)) ||
1608                         pinfo->is_dba_panel) {
1609                 pr_debug("%s:%d, right ctrl pinctrl config not needed\n",
1610                         __func__, __LINE__);
1611                 return 0;
1612         }
1613
1614         pin_state = active ? ctrl_pdata->pin_res.gpio_state_active
1615                                 : ctrl_pdata->pin_res.gpio_state_suspend;
1616         if (!IS_ERR_OR_NULL(pin_state)) {
1617                 rc = pinctrl_select_state(ctrl_pdata->pin_res.pinctrl,
1618                                 pin_state);
1619                 if (rc)
1620                         pr_err("%s: can not set %s pins\n", __func__,
1621                                active ? MDSS_PINCTRL_STATE_DEFAULT
1622                                : MDSS_PINCTRL_STATE_SLEEP);
1623         } else {
1624                 pr_err("%s: invalid '%s' pinstate\n", __func__,
1625                        active ? MDSS_PINCTRL_STATE_DEFAULT
1626                        : MDSS_PINCTRL_STATE_SLEEP);
1627         }
1628         return rc;
1629 }
1630
1631 static int mdss_dsi_pinctrl_init(struct platform_device *pdev)
1632 {
1633         struct mdss_dsi_ctrl_pdata *ctrl_pdata;
1634
1635         ctrl_pdata = platform_get_drvdata(pdev);
1636         ctrl_pdata->pin_res.pinctrl = devm_pinctrl_get(&pdev->dev);
1637         if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.pinctrl)) {
1638                 pr_err("%s: failed to get pinctrl\n", __func__);
1639                 return PTR_ERR(ctrl_pdata->pin_res.pinctrl);
1640         }
1641
1642         ctrl_pdata->pin_res.gpio_state_active
1643                 = pinctrl_lookup_state(ctrl_pdata->pin_res.pinctrl,
1644                                 MDSS_PINCTRL_STATE_DEFAULT);
1645         if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.gpio_state_active))
1646                 pr_warn("%s: can not get default pinstate\n", __func__);
1647
1648         ctrl_pdata->pin_res.gpio_state_suspend
1649                 = pinctrl_lookup_state(ctrl_pdata->pin_res.pinctrl,
1650                                 MDSS_PINCTRL_STATE_SLEEP);
1651         if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.gpio_state_suspend))
1652                 pr_warn("%s: can not get sleep pinstate\n", __func__);
1653
1654         return 0;
1655 }
1656
1657 static int mdss_dsi_unblank(struct mdss_panel_data *pdata)
1658 {
1659         int ret = 0;
1660         struct mipi_panel_info *mipi;
1661         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1662         struct mdss_dsi_ctrl_pdata *sctrl = NULL;
1663
1664         if (pdata == NULL) {
1665                 pr_err("%s: Invalid input data\n", __func__);
1666                 return -EINVAL;
1667         }
1668
1669         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1670                                 panel_data);
1671         mipi  = &pdata->panel_info.mipi;
1672
1673         pr_debug("%s+: ctrl=%pK ndx=%d cur_power_state=%d ctrl_state=%x\n",
1674                         __func__, ctrl_pdata, ctrl_pdata->ndx,
1675                 pdata->panel_info.panel_power_state, ctrl_pdata->ctrl_state);
1676
1677         mdss_dsi_pm_qos_update_request(DSI_DISABLE_PC_LATENCY);
1678
1679         if (mdss_dsi_is_ctrl_clk_master(ctrl_pdata))
1680                 sctrl = mdss_dsi_get_ctrl_clk_slave();
1681
1682         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1683                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1684         if (sctrl)
1685                 mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle,
1686                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1687
1688         if (ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_LP) {
1689                 pr_debug("%s: dsi_unblank with panel always on\n", __func__);
1690                 if (ctrl_pdata->low_power_config)
1691                         ret = ctrl_pdata->low_power_config(pdata, false);
1692                 if (!ret)
1693                         ctrl_pdata->ctrl_state &= ~CTRL_STATE_PANEL_LP;
1694                 goto error;
1695         }
1696
1697         if (!(ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT)) {
1698                 if (!pdata->panel_info.dynamic_switch_pending) {
1699                         ATRACE_BEGIN("dsi_panel_on");
1700                         ret = ctrl_pdata->on(pdata);
1701                         if (ret) {
1702                                 pr_err("%s: unable to initialize the panel\n",
1703                                                         __func__);
1704                                 goto error;
1705                         }
1706                         ATRACE_END("dsi_panel_on");
1707                 }
1708         }
1709
1710         if ((pdata->panel_info.type == MIPI_CMD_PANEL) &&
1711                 mipi->vsync_enable && mipi->hw_vsync_mode) {
1712                 mdss_dsi_set_tear_on(ctrl_pdata);
1713                 if (mdss_dsi_is_te_based_esd(ctrl_pdata))
1714                         enable_irq(gpio_to_irq(ctrl_pdata->disp_te_gpio));
1715         }
1716
1717         ctrl_pdata->ctrl_state |= CTRL_STATE_PANEL_INIT;
1718
1719 error:
1720         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1721                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1722         if (sctrl)
1723                 mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle,
1724                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1725
1726         mdss_dsi_pm_qos_update_request(DSI_ENABLE_PC_LATENCY);
1727
1728         pr_debug("%s-:\n", __func__);
1729
1730         return ret;
1731 }
1732
1733 static int mdss_dsi_blank(struct mdss_panel_data *pdata, int power_state)
1734 {
1735         int ret = 0;
1736         struct mipi_panel_info *mipi;
1737         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1738
1739         if (pdata == NULL) {
1740                 pr_err("%s: Invalid input data\n", __func__);
1741                 return -EINVAL;
1742         }
1743
1744         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1745                                 panel_data);
1746         mipi = &pdata->panel_info.mipi;
1747
1748         pr_debug("%s+: ctrl=%pK ndx=%d power_state=%d\n",
1749                 __func__, ctrl_pdata, ctrl_pdata->ndx, power_state);
1750
1751         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1752                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1753
1754         if (mdss_panel_is_power_on_lp(power_state)) {
1755                 pr_debug("%s: low power state requested\n", __func__);
1756                 if (ctrl_pdata->low_power_config)
1757                         ret = ctrl_pdata->low_power_config(pdata, true);
1758                 if (!ret)
1759                         ctrl_pdata->ctrl_state |= CTRL_STATE_PANEL_LP;
1760                 goto error;
1761         }
1762
1763         if (pdata->panel_info.type == MIPI_VIDEO_PANEL &&
1764                         ctrl_pdata->off_cmds.link_state == DSI_LP_MODE) {
1765                 mdss_dsi_sw_reset(ctrl_pdata, false);
1766                 mdss_dsi_host_init(pdata);
1767         }
1768
1769         mdss_dsi_op_mode_config(DSI_CMD_MODE, pdata);
1770
1771         if (pdata->panel_info.dynamic_switch_pending) {
1772                 pr_info("%s: switching to %s mode\n", __func__,
1773                         (pdata->panel_info.mipi.mode ? "video" : "command"));
1774                 if (pdata->panel_info.type == MIPI_CMD_PANEL) {
1775                         ctrl_pdata->switch_mode(pdata, SWITCH_TO_VIDEO_MODE);
1776                 } else if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
1777                         ctrl_pdata->switch_mode(pdata, SWITCH_TO_CMD_MODE);
1778                         mdss_dsi_set_tear_off(ctrl_pdata);
1779                 }
1780         }
1781
1782         if ((pdata->panel_info.type == MIPI_CMD_PANEL) &&
1783                 mipi->vsync_enable && mipi->hw_vsync_mode) {
1784                 if (mdss_dsi_is_te_based_esd(ctrl_pdata)) {
1785                                 disable_irq(gpio_to_irq(
1786                                         ctrl_pdata->disp_te_gpio));
1787                                 atomic_dec(&ctrl_pdata->te_irq_ready);
1788                 }
1789                 mdss_dsi_set_tear_off(ctrl_pdata);
1790         }
1791
1792         if (ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT) {
1793                 if (!pdata->panel_info.dynamic_switch_pending) {
1794                         ATRACE_BEGIN("dsi_panel_off");
1795                         ret = ctrl_pdata->off(pdata);
1796                         if (ret) {
1797                                 pr_err("%s: Panel OFF failed\n", __func__);
1798                                 goto error;
1799                         }
1800                         ATRACE_END("dsi_panel_off");
1801                 }
1802                 ctrl_pdata->ctrl_state &= ~(CTRL_STATE_PANEL_INIT |
1803                         CTRL_STATE_PANEL_LP);
1804         }
1805
1806 error:
1807         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1808                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1809         pr_debug("%s-:End\n", __func__);
1810         return ret;
1811 }
1812
1813 static int mdss_dsi_post_panel_on(struct mdss_panel_data *pdata)
1814 {
1815         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1816
1817         if (pdata == NULL) {
1818                 pr_err("%s: Invalid input data\n", __func__);
1819                 return -EINVAL;
1820         }
1821
1822         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1823                                 panel_data);
1824
1825         pr_debug("%s+: ctrl=%pK ndx=%d\n", __func__,
1826                                 ctrl_pdata, ctrl_pdata->ndx);
1827
1828         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1829                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
1830
1831         if (ctrl_pdata->post_panel_on)
1832                 ctrl_pdata->post_panel_on(pdata);
1833
1834         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
1835                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
1836         pr_debug("%s-:\n", __func__);
1837
1838         return 0;
1839 }
1840
1841 static irqreturn_t test_hw_vsync_handler(int irq, void *data)
1842 {
1843         struct mdss_panel_data *pdata = (struct mdss_panel_data *)data;
1844
1845         pr_debug("HW VSYNC\n");
1846         MDSS_XLOG(0xaaa, irq);
1847         complete_all(&pdata->te_done);
1848         if (pdata->next)
1849                 complete_all(&pdata->next->te_done);
1850         return IRQ_HANDLED;
1851 }
1852
1853 static int mdss_dsi_disp_wake_thread(void *data)
1854 {
1855         static const struct sched_param max_rt_param = {
1856                 .sched_priority = MAX_RT_PRIO - 1
1857         };
1858         struct mdss_dsi_ctrl_pdata *ctrl_pdata = data;
1859         struct mdss_panel_data *pdata = &ctrl_pdata->panel_data;
1860
1861         sched_setscheduler_nocheck(current, SCHED_FIFO, &max_rt_param);
1862
1863         while (1) {
1864                 bool should_stop;
1865
1866                 wait_event(ctrl_pdata->wake_waitq,
1867                         (should_stop = kthread_should_stop()) ||
1868                         atomic_cmpxchg(&ctrl_pdata->disp_en,
1869                                        MDSS_DISPLAY_WAKING,
1870                                        MDSS_DISPLAY_ON) == MDSS_DISPLAY_WAKING);
1871
1872                 if (should_stop)
1873                         break;
1874
1875                 /* MDSS_EVENT_LINK_READY */
1876                 if (ctrl_pdata->refresh_clk_rate)
1877                         mdss_dsi_clk_refresh(pdata,
1878                                              ctrl_pdata->update_phy_timing);
1879                 mdss_dsi_on(pdata);
1880
1881                 /* MDSS_EVENT_UNBLANK */
1882                 mdss_dsi_unblank(pdata);
1883
1884                 /* MDSS_EVENT_PANEL_ON */
1885                 ctrl_pdata->ctrl_state |= CTRL_STATE_MDP_ACTIVE;
1886                 pdata->panel_info.esd_rdy = true;
1887
1888                 complete_all(&ctrl_pdata->wake_comp);
1889         }
1890
1891         return 0;
1892 }
1893
1894 static void mdss_dsi_display_wake(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
1895 {
1896         if (atomic_cmpxchg(&ctrl_pdata->disp_en, MDSS_DISPLAY_OFF,
1897                            MDSS_DISPLAY_WAKING) == MDSS_DISPLAY_OFF)
1898                 wake_up(&ctrl_pdata->wake_waitq);
1899 }
1900
1901 static int mdss_dsi_fb_unblank_cb(struct notifier_block *nb,
1902                                   unsigned long action, void *data)
1903 {
1904         struct mdss_dsi_ctrl_pdata *ctrl_pdata =
1905                 container_of(nb, typeof(*ctrl_pdata), wake_notif);
1906         int *blank = ((struct fb_event *)data)->data;
1907
1908         /* Parse unblank events as soon as they occur */
1909         if (action == FB_EARLY_EVENT_BLANK && *blank == FB_BLANK_UNBLANK)
1910                 mdss_dsi_display_wake(ctrl_pdata);
1911
1912         return NOTIFY_OK;
1913 }
1914
1915 int mdss_dsi_cont_splash_on(struct mdss_panel_data *pdata)
1916 {
1917         int ret = 0;
1918         struct mipi_panel_info *mipi;
1919         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1920
1921         pr_info("%s:%d DSI on for continuous splash.\n", __func__, __LINE__);
1922
1923         if (pdata == NULL) {
1924                 pr_err("%s: Invalid input data\n", __func__);
1925                 return -EINVAL;
1926         }
1927
1928         mipi = &pdata->panel_info.mipi;
1929
1930         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1931                                 panel_data);
1932
1933         pr_debug("%s+: ctrl=%pK ndx=%d\n", __func__,
1934                                 ctrl_pdata, ctrl_pdata->ndx);
1935
1936         WARN((ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT),
1937                 "Incorrect Ctrl state=0x%x\n", ctrl_pdata->ctrl_state);
1938
1939         mdss_dsi_ctrl_setup(ctrl_pdata);
1940         mdss_dsi_sw_reset(ctrl_pdata, true);
1941         pr_debug("%s-:End\n", __func__);
1942         return ret;
1943 }
1944
1945 static void __mdss_dsi_mask_dfps_errors(struct mdss_dsi_ctrl_pdata *ctrl,
1946                 bool mask)
1947 {
1948         u32 data = 0;
1949
1950         /*
1951          * Assumption is that the DSI clocks will be enabled
1952          * when this API is called from dfps thread
1953          */
1954         if (mask) {
1955                 /* mask FIFO underflow and PLL unlock bits */
1956                 mdss_dsi_set_reg(ctrl, 0x10c, 0x7c000000, 0x7c000000);
1957         } else {
1958                 data = MIPI_INP((ctrl->ctrl_base) + 0x0120);
1959                 if (data & BIT(16)) {
1960                         pr_debug("pll unlocked: 0x%x\n", data);
1961                         /* clear PLL unlock bit */
1962                         MIPI_OUTP((ctrl->ctrl_base) + 0x120, BIT(16));
1963                 }
1964
1965                 data = MIPI_INP((ctrl->ctrl_base) + 0x00c);
1966                 if (data & 0x88880000) {
1967                         pr_debug("dsi fifo underflow: 0x%x\n", data);
1968                         /* clear DSI FIFO underflow and empty */
1969                         MIPI_OUTP((ctrl->ctrl_base) + 0x00c, 0x99990000);
1970                 }
1971
1972                 /* restore FIFO underflow and PLL unlock bits */
1973                 mdss_dsi_set_reg(ctrl, 0x10c, 0x7c000000, 0x0);
1974         }
1975 }
1976
1977 static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata,
1978                 int new_fps)
1979 {
1980         u32 hsync_period, vsync_period;
1981         u32 new_dsi_v_total, current_dsi_v_total;
1982         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
1983
1984         if (pdata == NULL) {
1985                 pr_err("%s Invalid pdata\n", __func__);
1986                 return;
1987         }
1988
1989         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
1990                         panel_data);
1991         if (ctrl_pdata == NULL) {
1992                 pr_err("%s Invalid ctrl_pdata\n", __func__);
1993                 return;
1994         }
1995
1996         if (ctrl_pdata->timing_db_mode)
1997                 MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1);
1998
1999         vsync_period =
2000                 mdss_panel_get_vtotal(&pdata->panel_info);
2001         hsync_period =
2002                 mdss_panel_get_htotal(&pdata->panel_info, true);
2003         current_dsi_v_total =
2004                 MIPI_INP((ctrl_pdata->ctrl_base) + 0x2C);
2005         new_dsi_v_total =
2006                 ((vsync_period - 1) << 16) | (hsync_period - 1);
2007
2008         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C, new_dsi_v_total);
2009
2010         if (ctrl_pdata->timing_db_mode)
2011                 MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
2012
2013         pr_debug("%s new_fps:%d new_vtotal:0x%X cur_vtotal:0x%X frame_rate:%d\n",
2014                         __func__, new_fps, new_dsi_v_total, current_dsi_v_total,
2015                         ctrl_pdata->panel_data.panel_info.mipi.frame_rate);
2016
2017         ctrl_pdata->panel_data.panel_info.current_fps = new_fps;
2018         MDSS_XLOG(current_dsi_v_total, new_dsi_v_total, new_fps,
2019                 ctrl_pdata->timing_db_mode);
2020
2021 }
2022
2023 static void __mdss_dsi_dyn_refresh_config(
2024                 struct mdss_dsi_ctrl_pdata *ctrl_pdata)
2025 {
2026         int reg_data = 0;
2027         u32 phy_rev = ctrl_pdata->shared_data->phy_rev;
2028
2029         /* configure only for master control in split display */
2030         if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
2031                         mdss_dsi_is_ctrl_clk_slave(ctrl_pdata))
2032                 return;
2033
2034         switch (phy_rev) {
2035         case DSI_PHY_REV_10:
2036                 reg_data = MIPI_INP((ctrl_pdata->ctrl_base) +
2037                                 DSI_DYNAMIC_REFRESH_CTRL);
2038                 reg_data &= ~BIT(12);
2039                 MIPI_OUTP((ctrl_pdata->ctrl_base)
2040                                 + DSI_DYNAMIC_REFRESH_CTRL, reg_data);
2041                 break;
2042         case DSI_PHY_REV_20:
2043                 reg_data = BIT(13);
2044                 MIPI_OUTP((ctrl_pdata->ctrl_base)
2045                                 + DSI_DYNAMIC_REFRESH_CTRL, reg_data);
2046                 break;
2047         default:
2048                 pr_err("Phy rev %d unsupported\n", phy_rev);
2049                 break;
2050         }
2051
2052         pr_debug("Dynamic fps ctrl = 0x%x\n", reg_data);
2053 }
2054
2055 static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
2056 {
2057         u32 esc_clk_rate_hz;
2058         u32 pipe_delay, pipe_delay2 = 0, pll_delay;
2059         u32 hsync_period = 0;
2060         u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
2061         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2062         struct mdss_panel_info *pinfo = NULL;
2063         struct mdss_dsi_phy_ctrl *pd = NULL;
2064
2065         if (pdata == NULL) {
2066                 pr_err("%s Invalid pdata\n", __func__);
2067                 return;
2068         }
2069
2070         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2071                         panel_data);
2072         if (ctrl_pdata == NULL) {
2073                 pr_err("%s Invalid ctrl_pdata\n", __func__);
2074                 return;
2075         }
2076
2077         if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
2078                 mdss_dsi_is_ctrl_clk_slave(ctrl_pdata))
2079                 return;
2080
2081         pinfo = &pdata->panel_info;
2082         pd = &(pinfo->mipi.dsi_phy_db);
2083
2084         esc_clk_rate_hz = ctrl_pdata->esc_clk_rate_hz;
2085         pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate_hz);
2086         byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate_hz);
2087         hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) /
2088                                         esc_clk_rate_hz);
2089
2090         hsync_period = mdss_panel_get_htotal(pinfo, true);
2091         pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
2092         if (pinfo->mipi.eof_bllp_power_stop == 0)
2093                 pipe_delay += (17 / pclk_to_esc_ratio) +
2094                         ((21 + (pinfo->mipi.t_clk_pre + 1) +
2095                                 (pinfo->mipi.t_clk_post + 1)) /
2096                                 byte_to_esc_ratio) +
2097                         ((((pd->timing[8] >> 1) + 1) +
2098                         ((pd->timing[6] >> 1) + 1) +
2099                         ((pd->timing[3] * 4) + (pd->timing[5] >> 1) + 1) +
2100                         ((pd->timing[7] >> 1) + 1) +
2101                         ((pd->timing[1] >> 1) + 1) +
2102                         ((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio);
2103
2104         if (pinfo->mipi.force_clk_lane_hs)
2105                 pipe_delay2 = (6 / byte_to_esc_ratio) +
2106                         ((((pd->timing[1] >> 1) + 1) +
2107                         ((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio);
2108
2109         /* 130 us pll delay recommended by h/w doc */
2110         pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2;
2111
2112         MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY,
2113                                                 pipe_delay);
2114         MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY2,
2115                                                 pipe_delay2);
2116         MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PLL_DELAY,
2117                                                 pll_delay);
2118 }
2119
2120 static int __mdss_dsi_dfps_calc_clks(struct mdss_panel_data *pdata,
2121                 u64 new_clk_rate)
2122 {
2123         int rc = 0;
2124         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2125         struct mdss_panel_info *pinfo;
2126         u32 phy_rev;
2127
2128         if (pdata == NULL) {
2129                 pr_err("%s Invalid pdata\n", __func__);
2130                 return -EINVAL;
2131         }
2132
2133         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2134                         panel_data);
2135         if (ctrl_pdata == NULL) {
2136                 pr_err("%s Invalid ctrl_pdata\n", __func__);
2137                 return -EINVAL;
2138         }
2139
2140         pinfo = &pdata->panel_info;
2141         phy_rev = ctrl_pdata->shared_data->phy_rev;
2142
2143         pinfo->clk_rate = new_clk_rate;
2144         pinfo->mipi.dsi_pclk_rate = mdss_dsi_get_pclk_rate(pinfo,
2145                 new_clk_rate);
2146         __mdss_dsi_dyn_refresh_config(ctrl_pdata);
2147
2148         if (phy_rev == DSI_PHY_REV_20)
2149                 mdss_dsi_dfps_config_8996(ctrl_pdata);
2150
2151         __mdss_dsi_calc_dfps_delay(pdata);
2152
2153         /* take a backup of current clk rates */
2154         ctrl_pdata->pclk_rate_bkp = ctrl_pdata->pclk_rate;
2155         ctrl_pdata->byte_clk_rate_bkp = ctrl_pdata->byte_clk_rate;
2156
2157         ctrl_pdata->pclk_rate = pinfo->mipi.dsi_pclk_rate;
2158         do_div(new_clk_rate, 8U);
2159         ctrl_pdata->byte_clk_rate = (u32) new_clk_rate;
2160
2161         pr_debug("byte_rate=%i\n", ctrl_pdata->byte_clk_rate);
2162         pr_debug("pclk_rate=%i\n", ctrl_pdata->pclk_rate);
2163
2164         return rc;
2165 }
2166
2167 static int __mdss_dsi_dfps_update_clks(struct mdss_panel_data *pdata)
2168 {
2169         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2170         struct mdss_dsi_ctrl_pdata *sctrl_pdata = NULL;
2171         struct mdss_panel_info *pinfo, *spinfo = NULL;
2172         int rc = 0;
2173
2174         if (pdata == NULL) {
2175                 pr_err("%s Invalid pdata\n", __func__);
2176                 return -EINVAL;
2177         }
2178
2179         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2180                         panel_data);
2181         if (IS_ERR_OR_NULL(ctrl_pdata)) {
2182                 pr_err("Invalid ctrl_pdata = %lu\n", PTR_ERR(ctrl_pdata));
2183                 return PTR_ERR(ctrl_pdata);
2184         }
2185
2186         pinfo = &ctrl_pdata->panel_data.panel_info;
2187
2188         /*
2189          * In split display case, configure and enable dynamic refresh
2190          * register only after both the ctrl data is programmed. So,
2191          * ignore enabling dynamic refresh for the master control and
2192          * configure only when it is slave control.
2193          */
2194         if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
2195                         mdss_dsi_is_ctrl_clk_master(ctrl_pdata))
2196                 return 0;
2197
2198         if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
2199                         mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) {
2200                 sctrl_pdata = ctrl_pdata;
2201                 spinfo = pinfo;
2202                 ctrl_pdata = mdss_dsi_get_ctrl_clk_master();
2203                 if (IS_ERR_OR_NULL(ctrl_pdata)) {
2204                         pr_err("Invalid ctrl_pdata = %lu\n",
2205                                         PTR_ERR(ctrl_pdata));
2206                         return PTR_ERR(ctrl_pdata);
2207                 }
2208
2209                 pinfo = &ctrl_pdata->panel_data.panel_info;
2210         }
2211
2212         /*
2213          * For programming dynamic refresh registers, we need to change
2214          * the parent to shadow clocks for the software byte and pixel mux.
2215          * After switching to shadow clocks, if there is no ref count on
2216          * main byte and pixel clocks, clock driver may shutdown those
2217          * unreferenced  byte and pixel clocks. Hence add an extra reference
2218          * count to avoid shutting down the main byte and pixel clocks.
2219          */
2220         rc = clk_prepare_enable(ctrl_pdata->pll_byte_clk);
2221         if (rc) {
2222                 pr_err("Unable to add extra refcnt for byte clock\n");
2223                 goto error_byte;
2224         }
2225
2226         rc = clk_prepare_enable(ctrl_pdata->pll_pixel_clk);
2227         if (rc) {
2228                 pr_err("Unable to add extra refcnt for pixel clock\n");
2229                 goto error_pixel;
2230         }
2231
2232         /* change the parent to shadow clocks*/
2233         rc = clk_set_parent(ctrl_pdata->mux_byte_clk,
2234                         ctrl_pdata->shadow_byte_clk);
2235         if (rc) {
2236                 pr_err("Unable to set parent to shadow byte clock\n");
2237                 goto error_shadow_byte;
2238         }
2239
2240         rc = clk_set_parent(ctrl_pdata->mux_pixel_clk,
2241                         ctrl_pdata->shadow_pixel_clk);
2242         if (rc) {
2243                 pr_err("Unable to set parent to shadow pixel clock\n");
2244                 goto error_shadow_pixel;
2245         }
2246
2247         rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
2248                         MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate, 0);
2249         if (rc) {
2250                 pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
2251                                 __func__);
2252                 goto error_byte_link;
2253         }
2254
2255         rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
2256                         MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate, 0);
2257         if (rc) {
2258                 pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
2259                                 __func__);
2260                 goto error_pixel_link;
2261         }
2262
2263         if (sctrl_pdata) {
2264                 rc = mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle,
2265                         MDSS_DSI_LINK_BYTE_CLK, sctrl_pdata->byte_clk_rate, 0);
2266                 if (rc) {
2267                         pr_err("%s: slv dsi_byte_clk - clk_set_rate failed\n",
2268                                         __func__);
2269                         goto error_sbyte_link;
2270                 }
2271
2272                 rc = mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle,
2273                         MDSS_DSI_LINK_PIX_CLK, sctrl_pdata->pclk_rate, 0);
2274                 if (rc) {
2275                         pr_err("%s: slv dsi_pixel_clk - clk_set_rate failed\n",
2276                                         __func__);
2277                         goto error_spixel_link;
2278                 }
2279         }
2280
2281         rc = mdss_dsi_en_wait4dynamic_done(ctrl_pdata);
2282         if (rc < 0) {
2283                 pr_err("Unsuccessful dynamic fps change");
2284                 goto dfps_timeout;
2285         }
2286
2287         MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_CTRL, 0x00);
2288         if (sctrl_pdata)
2289                 MIPI_OUTP((sctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_CTRL,
2290                                 0x00);
2291
2292         rc = mdss_dsi_phy_pll_reset_status(ctrl_pdata);
2293         if (rc) {
2294                 pr_err("%s: pll cannot be locked reset core ready failed %d\n",
2295                         __func__, rc);
2296                 goto dfps_timeout;
2297         }
2298
2299         __mdss_dsi_mask_dfps_errors(ctrl_pdata, false);
2300         if (sctrl_pdata)
2301                 __mdss_dsi_mask_dfps_errors(sctrl_pdata, false);
2302
2303         /* Move the mux clocks to main byte and pixel clocks */
2304         rc = clk_set_parent(ctrl_pdata->mux_byte_clk,
2305                         ctrl_pdata->pll_byte_clk);
2306         if (rc)
2307                 pr_err("Unable to set parent back to main byte clock\n");
2308
2309         rc = clk_set_parent(ctrl_pdata->mux_pixel_clk,
2310                         ctrl_pdata->pll_pixel_clk);
2311         if (rc)
2312                 pr_err("Unable to set parent back to main pixel clock\n");
2313
2314         /* Remove extra ref count on parent clocks */
2315         clk_disable_unprepare(ctrl_pdata->pll_byte_clk);
2316         clk_disable_unprepare(ctrl_pdata->pll_pixel_clk);
2317
2318         return rc;
2319
2320 dfps_timeout:
2321         if (sctrl_pdata)
2322                 mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle,
2323                                 MDSS_DSI_LINK_PIX_CLK,
2324                                 sctrl_pdata->pclk_rate_bkp, 0);
2325 error_spixel_link:
2326         if (sctrl_pdata)
2327                 mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle,
2328                                 MDSS_DSI_LINK_BYTE_CLK,
2329                                 sctrl_pdata->byte_clk_rate_bkp, 0);
2330 error_sbyte_link:
2331         mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
2332                 MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate_bkp, 0);
2333 error_pixel_link:
2334         mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
2335                 MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate_bkp, 0);
2336 error_byte_link:
2337         clk_set_parent(ctrl_pdata->mux_pixel_clk, ctrl_pdata->pll_pixel_clk);
2338 error_shadow_pixel:
2339         clk_set_parent(ctrl_pdata->mux_byte_clk, ctrl_pdata->pll_byte_clk);
2340 error_shadow_byte:
2341         clk_disable_unprepare(ctrl_pdata->pll_pixel_clk);
2342 error_pixel:
2343         clk_disable_unprepare(ctrl_pdata->pll_byte_clk);
2344 error_byte:
2345         return rc;
2346 }
2347
2348 static int mdss_dsi_check_params(struct mdss_dsi_ctrl_pdata *ctrl, void *arg)
2349 {
2350         struct mdss_panel_info *var_pinfo, *pinfo;
2351         int rc = 0;
2352
2353         if (!ctrl || !arg)
2354                 return 0;
2355
2356         pinfo = &ctrl->panel_data.panel_info;
2357         if (!pinfo->is_pluggable)
2358                 return 0;
2359
2360         var_pinfo = (struct mdss_panel_info *)arg;
2361
2362         pr_debug("%s: reconfig xres: %d yres: %d, current xres: %d yres: %d\n",
2363                         __func__, var_pinfo->xres, var_pinfo->yres,
2364                                         pinfo->xres, pinfo->yres);
2365         if ((var_pinfo->xres != pinfo->xres) ||
2366                 (var_pinfo->yres != pinfo->yres) ||
2367                 (var_pinfo->lcdc.h_back_porch != pinfo->lcdc.h_back_porch) ||
2368                 (var_pinfo->lcdc.h_front_porch != pinfo->lcdc.h_front_porch) ||
2369                 (var_pinfo->lcdc.h_pulse_width != pinfo->lcdc.h_pulse_width) ||
2370                 (var_pinfo->lcdc.v_back_porch != pinfo->lcdc.v_back_porch) ||
2371                 (var_pinfo->lcdc.v_front_porch != pinfo->lcdc.v_front_porch) ||
2372                 (var_pinfo->lcdc.v_pulse_width != pinfo->lcdc.v_pulse_width)
2373                 )
2374                 rc = 1;
2375
2376         return rc;
2377 }
2378
2379 static void mdss_dsi_avr_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata,
2380                 int enabled)
2381 {
2382         u32 data = MIPI_INP((ctrl_pdata->ctrl_base) + 0x10);
2383
2384         /* DSI_VIDEO_MODE_CTRL */
2385         if (enabled)
2386                 data |= BIT(29); /* AVR_SUPPORT_ENABLED */
2387         else
2388                 data &= ~BIT(29);
2389
2390         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x10, data);
2391         MDSS_XLOG(ctrl_pdata->ndx, enabled, data);
2392 }
2393
2394 static int __mdss_dsi_dynamic_clock_switch(struct mdss_panel_data *pdata,
2395         u64 new_clk_rate)
2396 {
2397         int rc = 0;
2398         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2399         struct mdss_panel_info *pinfo;
2400         u32 phy_rev;
2401         u64 clk_rate_bkp;
2402
2403         pr_debug("%s+:\n", __func__);
2404
2405         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2406                         panel_data);
2407
2408         phy_rev = ctrl_pdata->shared_data->phy_rev;
2409         pinfo = &pdata->panel_info;
2410
2411         /* get the fps configured in HW */
2412         clk_rate_bkp = pinfo->clk_rate;
2413
2414         __mdss_dsi_mask_dfps_errors(ctrl_pdata, true);
2415
2416         if (phy_rev == DSI_PHY_REV_20) {
2417                 rc = mdss_dsi_phy_calc_timing_param(pinfo, phy_rev,
2418                                 new_clk_rate);
2419                 if (rc) {
2420                         pr_err("PHY calculations failed-%lld\n", new_clk_rate);
2421                         goto end_update;
2422                 }
2423         }
2424
2425         rc = __mdss_dsi_dfps_calc_clks(pdata, new_clk_rate);
2426         if (rc) {
2427                 pr_err("error calculating clocks for %lld\n", new_clk_rate);
2428                 goto error_clks;
2429         }
2430
2431         rc = __mdss_dsi_dfps_update_clks(pdata);
2432         if (rc) {
2433                 pr_err("Dynamic refresh failed-%lld\n", new_clk_rate);
2434                 goto error_dfps;
2435         }
2436         return rc;
2437 error_dfps:
2438         if (__mdss_dsi_dfps_calc_clks(pdata, clk_rate_bkp))
2439                 pr_err("error reverting clock calculations for %lld\n",
2440                                 clk_rate_bkp);
2441 error_clks:
2442         if (mdss_dsi_phy_calc_timing_param(pinfo, phy_rev, clk_rate_bkp))
2443                 pr_err("Unable to revert phy timing-%lld\n", clk_rate_bkp);
2444 end_update:
2445         return rc;
2446 }
2447
2448 static int mdss_dsi_dynamic_bitclk_config(struct mdss_panel_data *pdata)
2449 {
2450         int rc = 0;
2451         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2452         struct mdss_panel_info *pinfo;
2453
2454         pr_debug("%s+:\n", __func__);
2455
2456         if (pdata == NULL) {
2457                 pr_err("%s: Invalid input data\n", __func__);
2458                 return -EINVAL;
2459         }
2460
2461         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2462                         panel_data);
2463
2464         if (!ctrl_pdata->panel_data.panel_info.dynamic_bitclk) {
2465                 pr_err("Dynamic bitclk not enabled for this panel\n");
2466                 return -EINVAL;
2467         }
2468
2469         pinfo = &pdata->panel_info;
2470
2471         if (!pinfo->new_clk_rate || (pinfo->clk_rate == pinfo->new_clk_rate)) {
2472                 pr_debug("Bit clock update is not needed\n");
2473                 return 0;
2474         }
2475
2476         rc = __mdss_dsi_dynamic_clock_switch(&ctrl_pdata->panel_data,
2477                 pinfo->new_clk_rate);
2478         if (!rc && mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data)) {
2479                 struct mdss_dsi_ctrl_pdata *octrl =
2480                         mdss_dsi_get_other_ctrl(ctrl_pdata);
2481                 rc = __mdss_dsi_dynamic_clock_switch(&octrl->panel_data,
2482                         pinfo->new_clk_rate);
2483                 if (rc)
2484                         pr_err("failed to switch DSI bitclk for sctrl\n");
2485         } else if (rc) {
2486                 pr_err("failed to switch DSI bitclk\n");
2487         }
2488         return rc;
2489 }
2490
2491 static int mdss_dsi_dfps_config(struct mdss_panel_data *pdata, int new_fps)
2492 {
2493         int rc = 0;
2494         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2495         struct mdss_panel_info *pinfo;
2496
2497         pr_debug("%s+:\n", __func__);
2498
2499         if (pdata == NULL) {
2500                 pr_err("%s: Invalid input data\n", __func__);
2501                 return -EINVAL;
2502         }
2503
2504         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2505                         panel_data);
2506
2507         if (!ctrl_pdata->panel_data.panel_info.dynamic_fps) {
2508                 pr_err("Dynamic fps not enabled for this panel\n");
2509                 return -EINVAL;
2510         }
2511
2512         pinfo = &pdata->panel_info;
2513
2514         if (new_fps == pinfo->current_fps) {
2515                 /*
2516                  * This is unlikely as mdss driver checks for previously
2517                  * configured frame rate.
2518                  */
2519                 pr_debug("Panel is already at this FPS\n");
2520                 goto end_update;
2521         }
2522
2523         if (pinfo->dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP ||
2524                 pinfo->dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP) {
2525                 /* Porch method */
2526                 __mdss_dsi_update_video_mode_total(pdata, new_fps);
2527         } else if (pinfo->dfps_update == DFPS_IMMEDIATE_CLK_UPDATE_MODE) {
2528                 /* Clock update method */
2529                 u64 new_clk_rate = mdss_dsi_calc_bitclk
2530                         (&ctrl_pdata->panel_data.panel_info, new_fps);
2531                 if (!new_clk_rate) {
2532                         pr_err("%s: unable to get the new bit clock rate\n",
2533                                         __func__);
2534                         rc = -EINVAL;
2535                         goto end_update;
2536                 }
2537
2538                 rc = __mdss_dsi_dynamic_clock_switch(pdata, new_clk_rate);
2539                 if (!rc) {
2540                         struct mdss_dsi_ctrl_pdata *mctrl_pdata = NULL;
2541                         struct mdss_panel_info *mpinfo = NULL;
2542
2543                         if (mdss_dsi_is_hw_config_split
2544                                 (ctrl_pdata->shared_data) &&
2545                                 mdss_dsi_is_ctrl_clk_master(ctrl_pdata))
2546                                 goto end_update;
2547
2548                         if (mdss_dsi_is_hw_config_split
2549                                 (ctrl_pdata->shared_data) &&
2550                                 mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) {
2551                                 mctrl_pdata = mdss_dsi_get_ctrl_clk_master();
2552                                 if (IS_ERR_OR_NULL(mctrl_pdata)) {
2553                                         pr_err("Invalid mctrl_pdata\n");
2554                                         goto end_update;
2555                                 }
2556
2557                                 mpinfo = &mctrl_pdata->panel_data.panel_info;
2558                         }
2559                         /*
2560                          * update new fps that at this point is already
2561                          * updated in hw
2562                          */
2563                         pinfo->current_fps = new_fps;
2564                         if (mctrl_pdata && mpinfo)
2565                                 mpinfo->current_fps = new_fps;
2566                 }
2567         }
2568 end_update:
2569         return rc;
2570 }
2571
2572 static int mdss_dsi_ctl_partial_roi(struct mdss_panel_data *pdata)
2573 {
2574         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2575         int rc = -EINVAL;
2576
2577         if (pdata == NULL) {
2578                 pr_err("%s: Invalid input data\n", __func__);
2579                 return -EINVAL;
2580         }
2581
2582         if (!pdata->panel_info.partial_update_enabled)
2583                 return 0;
2584
2585         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2586                                 panel_data);
2587
2588         if (ctrl_pdata->set_col_page_addr)
2589                 rc = ctrl_pdata->set_col_page_addr(pdata, false);
2590
2591         return rc;
2592 }
2593
2594 static int mdss_dsi_dispparam(struct mdss_panel_data *pdata)
2595 {
2596         int rc = -EINVAL;
2597         u32 data = 10;
2598         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2599
2600         if (pdata == NULL) {
2601                 pr_err("%s: Invalid input data\n", __func__);
2602                 return -EINVAL;
2603         }
2604
2605         data = pdata->panel_info.panel_paramstatus;
2606
2607         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2608                                 panel_data);
2609
2610         if (ctrl_pdata->dispparam_fnc)
2611                 rc = ctrl_pdata->dispparam_fnc(pdata);
2612
2613         if (rc) {
2614                 pr_err("%s: unable to initialize the panel\n",
2615                                 __func__);
2616                 return rc;
2617         }
2618         return rc;
2619 }
2620
2621 static int mdss_dsi_set_stream_size(struct mdss_panel_data *pdata)
2622 {
2623         u32 stream_ctrl, stream_total, idle;
2624         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2625         struct mdss_panel_info *pinfo;
2626         struct dsc_desc *dsc = NULL;
2627         struct mdss_rect *roi;
2628         struct panel_horizontal_idle *pidle;
2629         int i;
2630
2631         if (pdata == NULL) {
2632                 pr_err("%s: Invalid input data\n", __func__);
2633                 return -EINVAL;
2634         }
2635
2636         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2637                                 panel_data);
2638
2639         pinfo = &pdata->panel_info;
2640
2641         if (!pinfo->partial_update_supported)
2642                 return -EINVAL;
2643
2644         if (pinfo->compression_mode == COMPRESSION_DSC)
2645                 dsc = &pinfo->dsc;
2646
2647         roi = &pinfo->roi;
2648
2649         /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
2650         if (dsc) {
2651                 u16 byte_num =  dsc->bytes_per_pkt;
2652
2653                 if (pinfo->mipi.insert_dcs_cmd)
2654                         byte_num++;
2655
2656                 stream_ctrl = (byte_num << 16) | (pinfo->mipi.vc << 8) |
2657                                 DTYPE_DCS_LWRITE;
2658                 stream_total = dsc->pic_height << 16 | dsc->pclk_per_line;
2659         } else  {
2660
2661                 stream_ctrl = (((roi->w * 3) + 1) << 16) |
2662                         (pdata->panel_info.mipi.vc << 8) | DTYPE_DCS_LWRITE;
2663                 stream_total = roi->h << 16 | roi->w;
2664         }
2665         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, stream_ctrl);
2666         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, stream_ctrl);
2667
2668         /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
2669         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, stream_total);
2670         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, stream_total);
2671
2672         /* set idle control -- dsi clk cycle */
2673         idle = 0;
2674         pidle = ctrl_pdata->line_idle;
2675         for (i = 0; i < ctrl_pdata->horizontal_idle_cnt; i++) {
2676                 if (roi->w > pidle->min && roi->w <= pidle->max) {
2677                         idle = pidle->idle;
2678                         pr_debug("%s: ndx=%d w=%d range=%d-%d idle=%d\n",
2679                                 __func__, ctrl_pdata->ndx, roi->w,
2680                                 pidle->min, pidle->max, pidle->idle);
2681                         break;
2682                 }
2683                 pidle++;
2684         }
2685
2686         if (idle)
2687                 idle |= BIT(12);        /* enable */
2688
2689         MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x194, idle);
2690
2691         if (dsc)
2692                 mdss_dsi_dsc_config(ctrl_pdata, dsc);
2693
2694         return 0;
2695 }
2696
2697 static void mdss_dsi_dba_work(struct work_struct *work)
2698 {
2699         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2700         struct delayed_work *dw = to_delayed_work(work);
2701         struct mdss_dba_utils_init_data utils_init_data;
2702         struct mdss_panel_info *pinfo;
2703
2704         ctrl_pdata = container_of(dw, struct mdss_dsi_ctrl_pdata, dba_work);
2705         if (!ctrl_pdata) {
2706                 pr_err("%s: invalid ctrl data\n", __func__);
2707                 return;
2708         }
2709
2710         pinfo = &ctrl_pdata->panel_data.panel_info;
2711         if (!pinfo) {
2712                 pr_err("%s: invalid ctrl data\n", __func__);
2713                 return;
2714         }
2715
2716         memset(&utils_init_data, 0, sizeof(utils_init_data));
2717
2718         utils_init_data.chip_name = ctrl_pdata->bridge_name;
2719         utils_init_data.client_name = "dsi";
2720         utils_init_data.instance_id = ctrl_pdata->bridge_index;
2721         utils_init_data.fb_node = ctrl_pdata->fb_node;
2722         utils_init_data.kobj = ctrl_pdata->kobj;
2723         utils_init_data.pinfo = pinfo;
2724         if (ctrl_pdata->mdss_util)
2725                 utils_init_data.cont_splash_enabled =
2726                         ctrl_pdata->mdss_util->panel_intf_status(
2727                         ctrl_pdata->panel_data.panel_info.pdest,
2728                         MDSS_PANEL_INTF_DSI) ? true : false;
2729         else
2730                 utils_init_data.cont_splash_enabled = false;
2731
2732         pinfo->dba_data = mdss_dba_utils_init(&utils_init_data);
2733
2734         if (!IS_ERR_OR_NULL(pinfo->dba_data)) {
2735                 ctrl_pdata->ds_registered = true;
2736         } else {
2737                 pr_debug("%s: dba device not ready, queue again\n", __func__);
2738                 queue_delayed_work(ctrl_pdata->workq,
2739                                 &ctrl_pdata->dba_work, HZ);
2740         }
2741 }
2742
2743 static int mdss_dsi_reset_write_ptr(struct mdss_panel_data *pdata)
2744 {
2745
2746         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2747         struct mdss_panel_info *pinfo;
2748         int rc = 0;
2749
2750         if (pdata == NULL) {
2751                 pr_err("%s: Invalid input data\n", __func__);
2752                 return -EINVAL;
2753         }
2754
2755         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
2756                         panel_data);
2757
2758         pinfo = &ctrl_pdata->panel_data.panel_info;
2759         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
2760                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
2761         /* Need to reset the DSI core since the pixel stream was stopped. */
2762         mdss_dsi_sw_reset(ctrl_pdata, true);
2763
2764         /*
2765          * Reset the partial update co-ordinates to the panel height and
2766          * width
2767          */
2768         if (pinfo->dcs_cmd_by_left && (ctrl_pdata->ndx == 1))
2769                 goto skip_cmd_send;
2770
2771         pinfo->roi.x = 0;
2772         pinfo->roi.y = 0;
2773         pinfo->roi.w = pinfo->xres;
2774         if (pinfo->dcs_cmd_by_left)
2775                 pinfo->roi.w = pinfo->xres;
2776         if (pdata->next)
2777                 pinfo->roi.w += pdata->next->panel_info.xres;
2778         pinfo->roi.h = pinfo->yres;
2779
2780         mdss_dsi_set_stream_size(pdata);
2781
2782         if (ctrl_pdata->set_col_page_addr)
2783                 rc = ctrl_pdata->set_col_page_addr(pdata, true);
2784
2785 skip_cmd_send:
2786         mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
2787                           MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF);
2788
2789         pr_debug("%s: DSI%d write ptr reset finished\n", __func__,
2790                         ctrl_pdata->ndx);
2791
2792         return rc;
2793 }
2794
2795 int mdss_dsi_register_recovery_handler(struct mdss_dsi_ctrl_pdata *ctrl,
2796         struct mdss_intf_recovery *recovery)
2797 {
2798         mutex_lock(&ctrl->mutex);
2799         ctrl->recovery = recovery;
2800         mutex_unlock(&ctrl->mutex);
2801         return 0;
2802 }
2803
2804 static int mdss_dsi_register_mdp_callback(struct mdss_dsi_ctrl_pdata *ctrl,
2805         struct mdss_intf_recovery *mdp_callback)
2806 {
2807         mutex_lock(&ctrl->mutex);
2808         ctrl->mdp_callback = mdp_callback;
2809         mutex_unlock(&ctrl->mutex);
2810         return 0;
2811 }
2812
2813 static int mdss_dsi_register_clamp_handler(struct mdss_dsi_ctrl_pdata *ctrl,
2814         struct mdss_intf_ulp_clamp *clamp_handler)
2815 {
2816         mutex_lock(&ctrl->mutex);
2817         ctrl->clamp_handler = clamp_handler;
2818         mutex_unlock(&ctrl->mutex);
2819         return 0;
2820 }
2821
2822 static struct device_node *mdss_dsi_get_fb_node_cb(struct platform_device *pdev)
2823 {
2824         struct device_node *fb_node;
2825         struct platform_device *dsi_dev;
2826         struct mdss_dsi_ctrl_pdata *ctrl_pdata;
2827
2828         if (pdev == NULL) {
2829                 pr_err("%s: Invalid input data\n", __func__);
2830                 return NULL;
2831         }
2832
2833         ctrl_pdata = platform_get_drvdata(pdev);
2834         dsi_dev = of_find_device_by_node(pdev->dev.of_node->parent);
2835         if (!dsi_dev) {
2836                 pr_err("Unable to find dsi master device: %s\n",
2837                         pdev->dev.of_node->full_name);
2838                 return NULL;
2839         }
2840
2841         fb_node = of_parse_phandle(dsi_dev->dev.of_node,
2842                         mdss_dsi_get_fb_name(ctrl_pdata), 0);
2843         if (!fb_node) {
2844                 pr_err("Unable to find fb node for device: %s\n", pdev->name);
2845                 return NULL;
2846         }
2847
2848         return fb_node;
2849 }
2850
2851 static void mdss_dsi_timing_db_ctrl(struct mdss_dsi_ctrl_pdata *ctrl,
2852                                                 int enable)
2853 {
2854         if (!ctrl || !ctrl->timing_db_mode ||
2855                 (ctrl->shared_data->hw_rev < MDSS_DSI_HW_REV_201))
2856                 return;
2857
2858         mdss_dsi_clk_ctrl(ctrl, ctrl->dsi_clk_handle,
2859                   MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
2860         MIPI_OUTP((ctrl->ctrl_base + 0x1e8), enable);
2861         wmb(); /* ensure timing db is disabled */
2862         mdss_dsi_clk_ctrl(ctrl, ctrl->dsi_clk_handle,
2863                   MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF);
2864 }
2865
2866 static struct mdss_dsi_ctrl_pdata *mdss_dsi_get_drvdata(struct device *dev)
2867 {
2868         struct msm_fb_data_type *mfd;
2869         struct mdss_panel_data *pdata;
2870         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
2871         struct fb_info *fbi = dev_get_drvdata(dev);
2872
2873         if (fbi) {
2874                 mfd = (struct msm_fb_data_type *)fbi->par;
2875                 pdata = dev_get_platdata(&mfd->pdev->dev);
2876
2877                 ctrl_pdata = container_of(pdata,
2878                         struct mdss_dsi_ctrl_pdata, panel_data);
2879         }
2880
2881         return ctrl_pdata;
2882 }
2883
2884 static ssize_t supp_bitclk_list_sysfs_rda(struct device *dev,
2885         struct device_attribute *attr, char *buf)
2886 {
2887         ssize_t ret = 0;
2888         int i = 0;
2889         struct mdss_dsi_ctrl_pdata *ctrl_pdata = mdss_dsi_get_drvdata(dev);
2890         struct mdss_panel_info *pinfo = NULL;
2891
2892         if (!ctrl_pdata) {
2893                 pr_err("%s: invalid input\n", __func__);
2894                 return -EINVAL;
2895         }
2896
2897         pinfo = &ctrl_pdata->panel_data.panel_info;
2898         if (!pinfo) {
2899                 pr_err("no panel connected\n");
2900                 return -ENODEV;
2901         }
2902
2903         if (!pinfo->dynamic_bitclk) {
2904                 pr_err_once("%s: Dynamic bitclk not enabled for this panel\n",
2905                                 __func__);
2906                 return -EINVAL;
2907         }
2908
2909         buf[0] = 0;
2910         for (i = 0; i < pinfo->supp_bitclk_len; i++) {
2911                 if (ret > 0)
2912                         ret += scnprintf(buf + ret, PAGE_SIZE - ret,
2913                                 ",%d", pinfo->supp_bitclks[i]);
2914                 else
2915                         ret += scnprintf(buf + ret, PAGE_SIZE - ret,
2916                                 "%d", pinfo->supp_bitclks[i]);
2917         }
2918
2919         ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
2920
2921         return ret;
2922 }
2923
2924 static ssize_t dynamic_bitclk_sysfs_wta(struct device *dev,
2925         struct device_attribute *attr, const char *buf, size_t count)
2926 {
2927         int rc = 0, i = 0;
2928         struct mdss_dsi_ctrl_pdata *ctrl_pdata = mdss_dsi_get_drvdata(dev);
2929         struct mdss_panel_info *pinfo = NULL;
2930         int clk_rate = 0;
2931
2932         if (!ctrl_pdata) {
2933                 pr_err("%s: invalid input\n", __func__);
2934                 return -EINVAL;
2935         }
2936
2937         pinfo = &ctrl_pdata->panel_data.panel_info;
2938         if (!pinfo) {
2939                 pr_err("no panel connected\n");
2940                 return -ENODEV;
2941         }
2942
2943         if (!pinfo->dynamic_bitclk) {
2944                 pr_err_once("%s: Dynamic bitclk not enabled for this panel\n",
2945                                 __func__);
2946                 return -EINVAL;
2947         }
2948
2949         if (mdss_panel_is_power_off(pinfo->panel_power_state)) {
2950                 pr_err_once("%s: Panel powered off!\n", __func__);
2951                 return -EINVAL;
2952         }
2953
2954         rc = kstrtoint(buf, 10, &clk_rate);
2955         if (rc) {
2956                 pr_err("%s: kstrtoint failed. rc=%d\n", __func__, rc);
2957                 return rc;
2958         }
2959
2960         for (i = 0; i < pinfo->supp_bitclk_len; i++) {
2961                 if (pinfo->supp_bitclks[i] == clk_rate)
2962                         break;
2963         }
2964         if (i == pinfo->supp_bitclk_len) {
2965                 pr_err("Requested bitclk: %d not supported\n", clk_rate);
2966                 return -EINVAL;
2967         }
2968
2969         pinfo->new_clk_rate = clk_rate;
2970         if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data)) {
2971                 struct mdss_dsi_ctrl_pdata *octrl =
2972                         mdss_dsi_get_other_ctrl(ctrl_pdata);
2973                 struct mdss_panel_info *opinfo = &octrl->panel_data.panel_info;
2974
2975                 opinfo->new_clk_rate = clk_rate;
2976         }
2977         return count;
2978 } /* dynamic_bitclk_sysfs_wta */
2979
2980 static ssize_t dynamic_bitclk_sysfs_rda(struct device *dev,
2981         struct device_attribute *attr, char *buf)
2982 {
2983         ssize_t ret;
2984         struct mdss_dsi_ctrl_pdata *ctrl_pdata = mdss_dsi_get_drvdata(dev);
2985         struct mdss_panel_info *pinfo = NULL;
2986
2987         if (!ctrl_pdata) {
2988                 pr_err("%s: invalid input\n", __func__);
2989                 return -EINVAL;
2990         }
2991
2992         pinfo = &ctrl_pdata->panel_data.panel_info;
2993         if (!pinfo) {
2994                 pr_err("no panel connected\n");
2995                 return -ENODEV;
2996         }
2997
2998         ret = snprintf(buf, PAGE_SIZE, "%llu\n", pinfo->clk_rate);
2999         pr_debug("%s: '%llu'\n", __func__, pinfo->clk_rate);
3000
3001         return ret;
3002 } /* dynamic_bitclk_sysfs_rda */
3003
3004 static DEVICE_ATTR(dynamic_bitclk, S_IRUGO | S_IWUSR | S_IWGRP,
3005         dynamic_bitclk_sysfs_rda, dynamic_bitclk_sysfs_wta);
3006 static DEVICE_ATTR(supported_bitclk, S_IRUGO, supp_bitclk_list_sysfs_rda, NULL);
3007
3008 static struct attribute *dynamic_bitclk_fs_attrs[] = {
3009         &dev_attr_dynamic_bitclk.attr,
3010         &dev_attr_supported_bitclk.attr,
3011         NULL,
3012 };
3013
3014 static struct attribute_group mdss_dsi_fs_attrs_group = {
3015         .attrs = dynamic_bitclk_fs_attrs,
3016 };
3017
3018 static int mdss_dsi_event_handler(struct mdss_panel_data *pdata,
3019                                   int event, void *arg)
3020 {
3021         int rc = 0;
3022         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
3023         struct fb_info *fbi;
3024         int power_state;
3025         u32 mode;
3026         struct mdss_panel_info *pinfo;
3027         int ret;
3028
3029         if (pdata == NULL) {
3030                 pr_err("%s: Invalid input data\n", __func__);
3031                 return -EINVAL;
3032         }
3033         pinfo = &pdata->panel_info;
3034         ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
3035                                 panel_data);
3036         pr_debug("%s+: ctrl=%d event=%d\n", __func__, ctrl_pdata->ndx, event);
3037
3038         MDSS_XLOG(event, arg, ctrl_pdata->ndx, 0x3333);
3039
3040         switch (event) {
3041         case MDSS_EVENT_CHECK_PARAMS:
3042                 pr_debug("%s:Entered Case MDSS_EVENT_CHECK_PARAMS\n", __func__);
3043                 if (mdss_dsi_check_params(ctrl_pdata, arg)) {
3044                         ctrl_pdata->update_phy_timing = true;
3045                         /*
3046                          * Call to MDSS_EVENT_CHECK_PARAMS expects
3047                          * the return value of 1, if there is a change
3048                          * in panel timing parameters.
3049                          */
3050                         rc = 1;
3051                 }
3052                 ctrl_pdata->refresh_clk_rate = true;
3053                 break;
3054         case MDSS_EVENT_LINK_READY:
3055                 /* The unblank notifier handles waking for unblank events */
3056                 mdss_dsi_display_wake(ctrl_pdata);
3057                 break;
3058         case MDSS_EVENT_POST_PANEL_ON:
3059                 rc = mdss_dsi_post_panel_on(pdata);
3060                 break;
3061         case MDSS_EVENT_BLANK:
3062                 power_state = (int) (unsigned long) arg;
3063                 mutex_lock(&ctrl_pdata->dsi_ctrl_mutex);
3064                 if (ctrl_pdata->off_cmds.link_state == DSI_HS_MODE)
3065                         rc = mdss_dsi_blank(pdata, power_state);
3066                 mutex_unlock(&ctrl_pdata->dsi_ctrl_mutex);
3067                 break;
3068         case MDSS_EVENT_PANEL_OFF:
3069                 power_state = (int) (unsigned long) arg;
3070                 ctrl_pdata->ctrl_state &= ~CTRL_STATE_MDP_ACTIVE;
3071                 mutex_lock(&ctrl_pdata->dsi_ctrl_mutex);
3072                 if (ctrl_pdata->off_cmds.link_state == DSI_LP_MODE)
3073                         rc = mdss_dsi_blank(pdata, power_state);
3074                 rc = mdss_dsi_off(pdata, power_state);
3075                 mutex_unlock(&ctrl_pdata->dsi_ctrl_mutex);
3076                 reinit_completion(&ctrl_pdata->wake_comp);
3077                 atomic_set(&ctrl_pdata->disp_en, MDSS_DISPLAY_OFF);
3078                 break;
3079         case MDSS_EVENT_DISABLE_PANEL:
3080                 /* disable esd thread */
3081                 disable_esd_thread();
3082
3083                 /* disable backlight */
3084                 ctrl_pdata->panel_data.set_backlight(pdata, 0);
3085
3086                 /* send the off commands */
3087                 ctrl_pdata->off(pdata);
3088
3089                 /* disable panel power */
3090                 ret = mdss_dsi_panel_power_ctrl(pdata,
3091                         MDSS_PANEL_POWER_LCD_DISABLED);
3092                 break;
3093         case MDSS_EVENT_CONT_SPLASH_FINISH:
3094                 if (ctrl_pdata->off_cmds.link_state == DSI_LP_MODE)
3095                         rc = mdss_dsi_blank(pdata, MDSS_PANEL_POWER_OFF);
3096                 ctrl_pdata->ctrl_state &= ~CTRL_STATE_MDP_ACTIVE;
3097                 rc = mdss_dsi_cont_splash_on(pdata);
3098                 break;
3099         case MDSS_EVENT_PANEL_CLK_CTRL:
3100                 mdss_dsi_clk_req(ctrl_pdata,
3101                         (struct dsi_panel_clk_ctrl *) arg);
3102                 break;
3103         case MDSS_EVENT_DSI_CMDLIST_KOFF:
3104                 mdss_dsi_cmdlist_commit(ctrl_pdata, 1);
3105                 break;
3106         case MDSS_EVENT_PANEL_UPDATE_FPS:
3107                 if (arg != NULL) {
3108                         rc = mdss_dsi_dfps_config(pdata,
3109                                          (int) (unsigned long) arg);
3110                         if (rc)
3111                                 pr_err("unable to change fps-%d, error-%d\n",
3112                                                 (int) (unsigned long) arg, rc);
3113                         else
3114                                 pr_debug("panel frame rate changed to %d\n",
3115                                                 (int) (unsigned long) arg);
3116                 }
3117                 break;
3118         case MDSS_EVENT_CONT_SPLASH_BEGIN:
3119                 if (ctrl_pdata->off_cmds.link_state == DSI_HS_MODE) {
3120                         /* Panel is Enabled in Bootloader */
3121                         rc = mdss_dsi_blank(pdata, MDSS_PANEL_POWER_OFF);
3122                 }
3123                 break;
3124         case MDSS_EVENT_DSC_PPS_SEND:
3125                 if (pinfo->compression_mode == COMPRESSION_DSC)
3126                         mdss_dsi_panel_dsc_pps_send(ctrl_pdata, pinfo);
3127                 break;
3128         case MDSS_EVENT_ENABLE_PARTIAL_ROI:
3129                 rc = mdss_dsi_ctl_partial_roi(pdata);
3130                 break;
3131         case MDSS_EVENT_DISPPARAM:
3132                 mutex_lock(&ctrl_pdata->dsi_ctrl_mutex);
3133                 rc = mdss_dsi_dispparam(pdata);
3134                 mutex_unlock(&ctrl_pdata->dsi_ctrl_mutex);
3135                 break;
3136         case MDSS_EVENT_DSI_RESET_WRITE_PTR:
3137                 rc = mdss_dsi_reset_write_ptr(pdata);
3138                 break;
3139         case MDSS_EVENT_DSI_STREAM_SIZE:
3140                 rc = mdss_dsi_set_stream_size(pdata);
3141                 break;
3142         case MDSS_EVENT_DSI_UPDATE_PANEL_DATA:
3143                 rc = mdss_dsi_update_panel_config(ctrl_pdata,
3144                                         (int)(unsigned long) arg);
3145                 break;
3146         case MDSS_EVENT_REGISTER_RECOVERY_HANDLER:
3147                 rc = mdss_dsi_register_recovery_handler(ctrl_pdata,
3148                         (struct mdss_intf_recovery *)arg);
3149                 break;
3150         case MDSS_EVENT_REGISTER_MDP_CALLBACK:
3151                 rc = mdss_dsi_register_mdp_callback(ctrl_pdata,
3152                         (struct mdss_intf_recovery *)arg);
3153                 break;
3154         case MDSS_EVENT_REGISTER_CLAMP_HANDLER:
3155                 rc = mdss_dsi_register_clamp_handler(ctrl_pdata,
3156                         (struct mdss_intf_ulp_clamp *)arg);
3157                 break;
3158         case MDSS_EVENT_DSI_DYNAMIC_SWITCH:
3159                 mode = (u32)(unsigned long) arg;
3160                 mdss_dsi_switch_mode(pdata, mode);
3161                 break;
3162         case MDSS_EVENT_DSI_RECONFIG_CMD:
3163                 mode = (u32)(unsigned long) arg;
3164                 rc = mdss_dsi_reconfig(pdata, mode);
3165                 break;
3166         case MDSS_EVENT_DSI_PANEL_STATUS:
3167                 rc = mdss_dsi_check_panel_status(ctrl_pdata, arg);
3168                 break;
3169         case MDSS_EVENT_PANEL_TIMING_SWITCH:
3170                 rc = mdss_dsi_panel_timing_switch(ctrl_pdata, arg);
3171                 break;
3172         case MDSS_EVENT_FB_REGISTERED:
3173                 mdss_dsi_debugfs_init(ctrl_pdata);
3174
3175                 fbi = (struct fb_info *)arg;
3176                 if (!fbi || !fbi->dev)
3177                         break;
3178
3179                 ctrl_pdata->kobj = &fbi->dev->kobj;
3180                 ctrl_pdata->fb_node = fbi->node;
3181
3182                 if (!mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) ||
3183                         (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
3184                         mdss_dsi_is_ctrl_clk_master(ctrl_pdata))) {
3185                         if (sysfs_create_group(&fbi->dev->kobj,
3186                                 &mdss_dsi_fs_attrs_group))
3187                                 pr_err("failed to create DSI sysfs group\n");
3188                 }
3189
3190                 if (IS_ENABLED(CONFIG_MSM_DBA) &&
3191                         pdata->panel_info.is_dba_panel) {
3192                                 queue_delayed_work(ctrl_pdata->workq,
3193                                         &ctrl_pdata->dba_work, HZ);
3194                 }
3195                 break;
3196         case MDSS_EVENT_DSI_TIMING_DB_CTRL:
3197                 mdss_dsi_timing_db_ctrl(ctrl_pdata, (int)(unsigned long)arg);
3198                 break;
3199         case MDSS_EVENT_AVR_MODE:
3200                 mdss_dsi_avr_config(ctrl_pdata, (int)(unsigned long) arg);
3201                 break;
3202         case MDSS_EVENT_DSI_DYNAMIC_BITCLK:
3203                 if (ctrl_pdata->panel_data.panel_info.dynamic_bitclk) {
3204                         rc = mdss_dsi_dynamic_bitclk_config(pdata);
3205                         if (rc)
3206                                 pr_err("unable to change bitclk error-%d\n",
3207                                         rc);
3208                 }
3209                 break;
3210         default:
3211                 pr_debug("%s: unhandled event=%d\n", __func__, event);
3212                 break;
3213         }
3214         pr_debug("%s-:event=%d, rc=%d\n", __func__, event, rc);
3215         return rc;
3216 }
3217
3218 static int mdss_dsi_set_override_cfg(char *override_cfg,
3219                 struct mdss_dsi_ctrl_pdata *ctrl_pdata, char *panel_cfg)
3220 {
3221         struct mdss_panel_info *pinfo = &ctrl_pdata->panel_data.panel_info;
3222         char *token = NULL;
3223
3224         pr_debug("%s: override config:%s\n", __func__, override_cfg);
3225         while ((token = strsep(&override_cfg, ":"))) {
3226                 if (!strcmp(token, OVERRIDE_CFG)) {
3227                         continue;
3228                 } else if (!strcmp(token, SIM_HW_TE_PANEL)) {
3229                         pinfo->sim_panel_mode = SIM_HW_TE_MODE;
3230                 } else if (!strcmp(token, SIM_SW_TE_PANEL)) {
3231                         pinfo->sim_panel_mode = SIM_SW_TE_MODE;
3232                 } else if (!strcmp(token, SIM_PANEL)) {
3233                         pinfo->sim_panel_mode = SIM_MODE;
3234                 } else {
3235                         pr_err("%s: invalid override_cfg token: %s\n",
3236                                         __func__, token);
3237                         return -EINVAL;
3238                 }
3239         }
3240         pr_debug("%s:sim_panel_mode:%d\n", __func__, pinfo->sim_panel_mode);
3241
3242         return 0;
3243 }
3244
3245 static struct device_node *mdss_dsi_pref_prim_panel(
3246                 struct platform_device *pdev)
3247 {
3248         struct device_node *dsi_pan_node = NULL;
3249
3250         pr_debug("%s:%d: Select primary panel from dt\n",
3251                                         __func__, __LINE__);
3252         dsi_pan_node = of_parse_phandle(pdev->dev.of_node,
3253                                         "qcom,dsi-pref-prim-pan", 0);
3254         if (!dsi_pan_node)
3255                 pr_err("%s:can't find panel phandle\n", __func__);
3256
3257         return dsi_pan_node;
3258 }
3259
3260 /**
3261  * mdss_dsi_find_panel_of_node(): find device node of dsi panel
3262  * @pdev: platform_device of the dsi ctrl node
3263  * @panel_cfg: string containing intf specific config data
3264  *
3265  * Function finds the panel device node using the interface
3266  * specific configuration data. This configuration data is
3267  * could be derived from the result of bootloader's GCDB
3268  * panel detection mechanism. If such config data doesn't
3269  * exist then this panel returns the default panel configured
3270  * in the device tree.
3271  *
3272  * returns pointer to panel node on success, NULL on error.
3273  */
3274 static struct device_node *mdss_dsi_find_panel_of_node(
3275                 struct platform_device *pdev, char *panel_cfg)
3276 {
3277         int len, i = 0;
3278         int ctrl_id = pdev->id - 1;
3279         char panel_name[MDSS_MAX_PANEL_LEN] = "";
3280         char ctrl_id_stream[3] =  "0:";
3281         char *str1 = NULL, *str2 = NULL, *override_cfg = NULL;
3282         char cfg_np_name[MDSS_MAX_PANEL_LEN] = "";
3283         struct device_node *dsi_pan_node = NULL, *mdss_node = NULL;
3284         struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev);
3285         struct mdss_panel_info *pinfo = &ctrl_pdata->panel_data.panel_info;
3286
3287         len = strlen(panel_cfg);
3288         ctrl_pdata->panel_data.dsc_cfg_np_name[0] = '\0';
3289         if (!len) {
3290                 /* no panel cfg chg, parse dt */
3291                 pr_debug("%s:%d: no cmd line cfg present\n",
3292                          __func__, __LINE__);
3293                 goto end;
3294         } else {
3295                 /* check if any override parameters are set */
3296                 pinfo->sim_panel_mode = 0;
3297                 override_cfg = strnstr(panel_cfg, "#" OVERRIDE_CFG, len);
3298                 if (override_cfg) {
3299                         *override_cfg = '\0';
3300                         if (mdss_dsi_set_override_cfg(override_cfg + 1,
3301                                         ctrl_pdata, panel_cfg))
3302                                 return NULL;
3303                         len = strlen(panel_cfg);
3304                 }
3305
3306                 if (ctrl_id == 1)
3307                         strlcpy(ctrl_id_stream, "1:", 3);
3308
3309                 /* get controller number */
3310                 str1 = strnstr(panel_cfg, ctrl_id_stream, len);
3311                 if (!str1) {
3312                         pr_err("%s: controller %s is not present in %s\n",
3313                                 __func__, ctrl_id_stream, panel_cfg);
3314                         goto end;
3315                 }
3316                 if ((str1 != panel_cfg) && (*(str1-1) != ':')) {
3317                         str1 += CMDLINE_DSI_CTL_NUM_STRING_LEN;
3318                         pr_debug("false match with config node name in \"%s\". search again in \"%s\"\n",
3319                                 panel_cfg, str1);
3320                         str1 = strnstr(str1, ctrl_id_stream, len);
3321                         if (!str1) {
3322                                 pr_err("%s: 2. controller %s is not present in %s\n",
3323                                         __func__, ctrl_id_stream, str1);
3324                                 goto end;
3325                         }
3326                 }
3327                 str1 += CMDLINE_DSI_CTL_NUM_STRING_LEN;
3328
3329                 /* get panel name */
3330                 str2 = strnchr(str1, strlen(str1), ':');
3331                 if (!str2) {
3332                         strlcpy(panel_name, str1, MDSS_MAX_PANEL_LEN);
3333                 } else {
3334                         for (i = 0; (str1 + i) < str2; i++)
3335                                 panel_name[i] = *(str1 + i);
3336                         panel_name[i] = 0;
3337                 }
3338                 pr_info("%s: cmdline:%s panel_name:%s\n",
3339                         __func__, panel_cfg, panel_name);
3340                 if (!strcmp(panel_name, NONE_PANEL))
3341                         goto exit;
3342
3343                 mdss_node = of_parse_phandle(pdev->dev.of_node,
3344                         "qcom,mdss-mdp", 0);
3345                 if (!mdss_node) {
3346                         pr_err("%s: %d: mdss_node null\n",
3347                                __func__, __LINE__);
3348                         return NULL;
3349                 }
3350                 dsi_pan_node = of_find_node_by_name(mdss_node, panel_name);
3351                 if (!dsi_pan_node) {
3352                         pr_err("%s: invalid pan node \"%s\"\n",
3353                                __func__, panel_name);
3354                         goto end;
3355                 } else {
3356                         /* extract config node name if present */
3357                         str1 += i;
3358                         str2 = strnstr(str1, "config", strlen(str1));
3359                         if (str2) {
3360                                 str1 = strnchr(str2, strlen(str2), ':');
3361                                 if (str1) {
3362                                         for (i = 0; ((str2 + i) < str1) &&
3363                                              i < (MDSS_MAX_PANEL_LEN - 1); i++)
3364                                                 cfg_np_name[i] = *(str2 + i);
3365                                         if ((i >= 0)
3366                                                 && (i < MDSS_MAX_PANEL_LEN))
3367                                                 cfg_np_name[i] = 0;
3368                                 } else {
3369                                         strlcpy(cfg_np_name, str2,
3370                                                 MDSS_MAX_PANEL_LEN);
3371                                 }
3372                                 strlcpy(ctrl_pdata->panel_data.dsc_cfg_np_name,
3373                                         cfg_np_name, MDSS_MAX_PANEL_LEN);
3374                         }
3375                 }
3376
3377                 return dsi_pan_node;
3378         }
3379 end:
3380         if (strcmp(panel_name, NONE_PANEL))
3381                 dsi_pan_node = mdss_dsi_pref_prim_panel(pdev);
3382 exit:
3383         return dsi_pan_node;
3384 }
3385
3386 static struct device_node *mdss_dsi_config_panel(struct platform_device *pdev,
3387         int ndx)
3388 {
3389         struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev);
3390         char panel_cfg[MDSS_MAX_PANEL_LEN];
3391         struct device_node *dsi_pan_node = NULL;
3392         int rc = 0;
3393
3394         if (!ctrl_pdata) {
3395                 pr_err("%s: Unable to get the ctrl_pdata\n", __func__);
3396                 return NULL;
3397         }
3398
3399         /* DSI panels can be different between controllers */
3400         rc = mdss_dsi_get_panel_cfg(panel_cfg, ctrl_pdata);
3401         if (!rc)
3402                 /* dsi panel cfg not present */
3403                 pr_warn("%s:%d:dsi specific cfg not present\n",
3404                         __func__, __LINE__);
3405
3406         /* find panel device node */
3407         dsi_pan_node = mdss_dsi_find_panel_of_node(pdev, panel_cfg);
3408         if (!dsi_pan_node) {
3409                 pr_err("%s: can't find panel node %s\n", __func__, panel_cfg);
3410                 of_node_put(dsi_pan_node);
3411                 return NULL;
3412         }
3413
3414         rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, ndx);
3415         if (rc) {
3416                 pr_err("%s: dsi panel init failed\n", __func__);
3417                 of_node_put(dsi_pan_node);
3418                 return NULL;
3419         }
3420
3421         return dsi_pan_node;
3422 }
3423
3424 static int mdss_dsi_ctrl_clock_init(struct platform_device *ctrl_pdev,
3425                                     struct mdss_dsi_ctrl_pdata *ctrl_pdata)
3426 {
3427         int rc = 0;
3428         struct mdss_dsi_clk_info info;
3429         struct mdss_dsi_clk_client client1 = {"dsi_clk_client"};
3430         struct mdss_dsi_clk_client client2 = {"mdp_event_client"};
3431         void *handle;
3432
3433         if (mdss_dsi_link_clk_init(ctrl_pdev, ctrl_pdata)) {
3434                 pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
3435                 return -EPERM;
3436         }
3437
3438         memset(&info, 0x0, sizeof(info));
3439
3440         info.core_clks.mdp_core_clk = ctrl_pdata->shared_data->mdp_core_clk;
3441         info.core_clks.mnoc_clk = ctrl_pdata->shared_data->mnoc_clk;
3442         info.core_clks.ahb_clk = ctrl_pdata->shared_data->ahb_clk;
3443         info.core_clks.axi_clk = ctrl_pdata->shared_data->axi_clk;
3444         info.core_clks.mmss_misc_ahb_clk =
3445                 ctrl_pdata->shared_data->mmss_misc_ahb_clk;
3446
3447         info.link_clks.esc_clk = ctrl_pdata->esc_clk;
3448         info.link_clks.byte_clk = ctrl_pdata->byte_clk;
3449         info.link_clks.pixel_clk = ctrl_pdata->pixel_clk;
3450         info.link_clks.byte_intf_clk = ctrl_pdata->byte_intf_clk;
3451
3452         info.pre_clkoff_cb = mdss_dsi_pre_clkoff_cb;
3453         info.post_clkon_cb = mdss_dsi_post_clkon_cb;
3454         info.pre_clkon_cb = mdss_dsi_pre_clkon_cb;
3455         info.post_clkoff_cb = mdss_dsi_post_clkoff_cb;
3456         info.priv_data = ctrl_pdata;
3457         snprintf(info.name, DSI_CLK_NAME_LEN, "DSI%d", ctrl_pdata->ndx);
3458         ctrl_pdata->clk_mngr = mdss_dsi_clk_init(&info);
3459         if (IS_ERR_OR_NULL(ctrl_pdata->clk_mngr)) {
3460                 rc = PTR_ERR(ctrl_pdata->clk_mngr);
3461                 ctrl_pdata->clk_mngr = NULL;
3462                 pr_err("dsi clock registration failed, rc = %d\n", rc);
3463                 goto error_link_clk_deinit;
3464         }
3465
3466         /*
3467          * There are two clients that control dsi clocks. MDP driver controls
3468          * the clock through MDSS_PANEL_EVENT_CLK_CTRL event and dsi driver
3469          * through clock interface. To differentiate between the votes from the
3470          * two clients, dsi driver will use two different handles to vote for
3471          * clock states from dsi and mdp driver.
3472          */
3473         handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client1);
3474         if (IS_ERR_OR_NULL(handle)) {
3475                 rc = PTR_ERR(handle);
3476                 pr_err("failed to register %s client, rc = %d\n",
3477                        client1.client_name, rc);
3478                 goto error_clk_deinit;
3479         } else {
3480                 ctrl_pdata->dsi_clk_handle = handle;
3481         }
3482
3483         handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client2);
3484         if (IS_ERR_OR_NULL(handle)) {
3485                 rc = PTR_ERR(handle);
3486                 pr_err("failed to register %s client, rc = %d\n",
3487                        client2.client_name, rc);
3488                 goto error_clk_client_deregister;
3489         } else {
3490                 ctrl_pdata->mdp_clk_handle = handle;
3491         }
3492
3493         return rc;
3494 error_clk_client_deregister:
3495         mdss_dsi_clk_deregister(ctrl_pdata->dsi_clk_handle);
3496 error_clk_deinit:
3497         mdss_dsi_clk_deinit(ctrl_pdata->clk_mngr);
3498 error_link_clk_deinit:
3499         mdss_dsi_link_clk_deinit(&ctrl_pdev->dev, ctrl_pdata);
3500         return rc;
3501 }
3502
3503 static int mdss_dsi_set_clk_rates(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
3504 {
3505         int rc = 0;
3506
3507         rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
3508                                         MDSS_DSI_LINK_BYTE_CLK,
3509                                         ctrl_pdata->byte_clk_rate,
3510                                         MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
3511         if (rc) {
3512                 pr_err("%s: dsi_byte_clk - clk_set_rate failed\n",
3513                                 __func__);
3514                 return rc;
3515         }
3516
3517         rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
3518                                         MDSS_DSI_LINK_PIX_CLK,
3519                                         ctrl_pdata->pclk_rate,
3520                                         MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
3521         if (rc) {
3522                 pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n",
3523                         __func__);
3524                 return rc;
3525         }
3526
3527         rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
3528                                         MDSS_DSI_LINK_ESC_CLK,
3529                                         ctrl_pdata->esc_clk_rate_hz,
3530                                         MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
3531         if (rc) {
3532                 pr_err("%s: dsi_esc_clk - clk_set_rate failed\n",
3533                         __func__);
3534                 return rc;
3535         }
3536
3537         return rc;
3538 }
3539
3540 static int mdss_dsi_cont_splash_config(struct mdss_panel_info *pinfo,
3541                                        struct mdss_dsi_ctrl_pdata *ctrl_pdata)
3542 {
3543         void *clk_handle;
3544         int rc = 0;
3545
3546         if (pinfo->cont_splash_enabled) {
3547                 rc = mdss_dsi_panel_power_ctrl(&(ctrl_pdata->panel_data),
3548                         MDSS_PANEL_POWER_ON);
3549                 if (rc) {
3550                         pr_err("%s: Panel power on failed\n", __func__);
3551                         return rc;
3552                 }
3553                 if (ctrl_pdata->bklt_ctrl == BL_PWM)
3554                         mdss_dsi_panel_pwm_enable(ctrl_pdata);
3555                 ctrl_pdata->ctrl_state |= (CTRL_STATE_PANEL_INIT |
3556                         CTRL_STATE_MDP_ACTIVE | CTRL_STATE_DSI_ACTIVE);
3557
3558                 /*
3559                  * MDP client removes this extra vote during splash reconfigure
3560                  * for command mode panel from interface. DSI removes the vote
3561                  * during suspend-resume for video mode panel.
3562                  */
3563                 if (ctrl_pdata->panel_data.panel_info.type == MIPI_CMD_PANEL)
3564                         clk_handle = ctrl_pdata->mdp_clk_handle;
3565                 else
3566                         clk_handle = ctrl_pdata->dsi_clk_handle;
3567
3568                 mdss_dsi_clk_ctrl(ctrl_pdata, clk_handle,
3569                                   MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON);
3570                 mdss_dsi_read_hw_revision(ctrl_pdata);
3571                 mdss_dsi_read_phy_revision(ctrl_pdata);
3572                 ctrl_pdata->is_phyreg_enabled = 1;
3573                 if (pinfo->type == MIPI_CMD_PANEL)
3574                         mdss_dsi_set_burst_mode(ctrl_pdata);
3575                 mdss_dsi_clamp_phy_reset_config(ctrl_pdata, true);
3576         } else {
3577                 /* Turn on the clocks to read the DSI and PHY revision */
3578                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
3579                                   MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON);
3580                 mdss_dsi_read_hw_revision(ctrl_pdata);
3581                 mdss_dsi_read_phy_revision(ctrl_pdata);
3582                 mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle,
3583                                   MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF);
3584                 pinfo->panel_power_state = MDSS_PANEL_POWER_OFF;
3585         }
3586
3587         return rc;
3588 }
3589
3590 static int mdss_dsi_get_bridge_chip_params(struct mdss_panel_info *pinfo,
3591                                        struct mdss_dsi_ctrl_pdata *ctrl_pdata,
3592                                        struct platform_device *pdev)
3593 {
3594         int rc = 0;
3595         u32 temp_val = 0;
3596
3597         if (!ctrl_pdata || !pdev || !pinfo) {
3598                 pr_err("%s: Invalid Params ctrl_pdata=%pK, pdev=%pK\n",
3599                         __func__, ctrl_pdata, pdev);
3600                 rc = -EINVAL;
3601                 goto end;
3602         }
3603
3604         if (pinfo->is_dba_panel) {
3605                 rc = of_property_read_u32(pdev->dev.of_node,
3606                         "qcom,bridge-index", &temp_val);
3607                 if (rc) {
3608                         pr_err("%s:%d Unable to read qcom,bridge-index, ret=%d\n",
3609                                 __func__, __LINE__, rc);
3610                         goto end;
3611                 }
3612                 pr_debug("%s: DT property %s is %X\n", __func__,
3613                         "qcom,bridge-index", temp_val);
3614                 ctrl_pdata->bridge_index = temp_val;
3615         }
3616 end:
3617         return rc;
3618 }
3619
3620 static int mdss_dsi_ctrl_validate_config(struct mdss_dsi_ctrl_pdata *ctrl)
3621 {
3622         int rc = 0;
3623
3624         if (!ctrl) {
3625                 rc = -EINVAL;
3626                 goto error;
3627         }
3628
3629         /*
3630          * check to make sure that the byte interface clock is specified for
3631          * DSI ctrl version 2 and above.
3632          */
3633         if ((ctrl->shared_data->hw_rev >= MDSS_DSI_HW_REV_200) &&
3634                 (!ctrl->byte_intf_clk)) {
3635                 pr_err("%s: byte intf clk must be defined for hw rev 0x%08x\n",
3636                         __func__, ctrl->shared_data->hw_rev);
3637                 rc = -EINVAL;
3638         }
3639
3640 error:
3641         return rc;
3642 }
3643
3644 static int mdss_dsi_ctrl_probe(struct platform_device *pdev)
3645 {
3646         int rc = 0;
3647         u32 index;
3648         struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
3649         struct mdss_panel_info *pinfo = NULL;
3650         struct device_node *dsi_pan_node = NULL;
3651         const char *ctrl_name;
3652         struct mdss_util_intf *util;
3653         static int te_irq_registered;
3654         struct mdss_panel_data *pdata;
3655
3656         if (!pdev || !pdev->dev.of_node) {
3657                 pr_err("%s: pdev not found for DSI controller\n", __func__);
3658                 return -ENODEV;
3659         }
3660         rc = of_property_read_u32(pdev->dev.of_node,
3661                                   "cell-index", &index);
3662         if (rc) {
3663                 dev_err(&pdev->dev, "%s: Cell-index not specified, rc=%d\n",
3664                         __func__, rc);
3665                 return rc;
3666         }
3667
3668         if (index == 0)
3669                 pdev->id = 1;
3670         else
3671                 pdev->id = 2;
3672
3673         ctrl_pdata = mdss_dsi_get_ctrl(index);
3674         if (!ctrl_pdata) {
3675                 pr_err("%s: Unable to get the ctrl_pdata\n", __func__);
3676                 return -EINVAL;
3677         }
3678
3679         platform_set_drvdata(pdev, ctrl_pdata);
3680
3681         util = mdss_get_util_intf();
3682         if (util == NULL) {
3683                 pr_err("Failed to get mdss utility functions\n");
3684                 return -ENODEV;
3685         }
3686
3687         ctrl_pdata->mdss_util = util;
3688         atomic_set(&ctrl_pdata->te_irq_ready, 0);
3689         ctrl_pdata->dsi_pipe_ready = false;
3690
3691         ctrl_name = of_get_property(pdev->dev.of_node, "label", NULL);
3692         if (!ctrl_name)
3693                 pr_info("%s:%d, DSI Ctrl name not specified\n",
3694                         __func__, __LINE__);
3695         else
3696                 pr_info("%s: DSI Ctrl name = %s\n",
3697                         __func__, ctrl_name);
3698
3699         rc = mdss_dsi_pinctrl_init(pdev);
3700         if (rc)
3701                 pr_warn("%s: failed to get pin resources\n", __func__);
3702
3703         if (index == 0) {
3704                 ctrl_pdata->panel_data.panel_info.pdest = DISPLAY_1;
3705                 ctrl_pdata->ndx = DSI_CTRL_0;
3706         } else {
3707                 ctrl_pdata->panel_data.panel_info.pdest = DISPLAY_2;
3708                 ctrl_pdata->ndx = DSI_CTRL_1;
3709         }
3710
3711         if (mdss_dsi_ctrl_clock_init(pdev, ctrl_pdata)) {
3712                 pr_err("%s: unable to initialize dsi clk manager\n", __func__);
3713                 return -EPERM;
3714         }
3715
3716         dsi_pan_node = mdss_dsi_config_panel(pdev, index);
3717         if (!dsi_pan_node) {
3718                 pr_err("%s: panel configuration failed\n", __func__);
3719                 return -EINVAL;
3720         }
3721
3722         if (!mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) ||
3723                 (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
3724                 (ctrl_pdata->panel_data.panel_info.pdest == DISPLAY_1))) {
3725                 rc = mdss_panel_parse_bl_settings(dsi_pan_node, ctrl_pdata);
3726                 if (rc) {
3727                         pr_warn("%s: dsi bl settings parse failed\n", __func__);
3728                         /* Panels like AMOLED and dsi2hdmi chip
3729                          * does not need backlight control.
3730                          * So we should not fail probe here.
3731                          */
3732                         ctrl_pdata->bklt_ctrl = UNKNOWN_CTRL;
3733                 }
3734         } else {
3735                 ctrl_pdata->bklt_ctrl = UNKNOWN_CTRL;
3736         }
3737
3738         rc = dsi_panel_device_register(pdev, dsi_pan_node, ctrl_pdata);
3739         if (rc) {
3740                 pr_err("%s: dsi panel dev reg failed\n", __func__);
3741                 goto error_pan_node;
3742         }
3743
3744         pinfo = &(ctrl_pdata->panel_data.panel_info);
3745         if (!(mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
3746                 mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) &&
3747                 (pinfo->dynamic_fps || pinfo->dynamic_bitclk)) {
3748                 rc = mdss_dsi_shadow_clk_init(pdev, ctrl_pdata);
3749
3750                 if (rc) {
3751                         pr_err("%s: unable to initialize shadow ctrl clks\n",
3752                                         __func__);
3753                         rc = -EPERM;
3754                 }
3755         }
3756
3757         rc = mdss_dsi_set_clk_rates(ctrl_pdata);
3758         if (rc) {
3759                 pr_err("%s: Failed to set dsi clk rates\n", __func__);
3760                 return rc;
3761         }
3762
3763         rc = mdss_dsi_cont_splash_config(pinfo, ctrl_pdata);
3764         if (rc) {
3765                 pr_err("%s: Failed to set dsi splash config\n", __func__);
3766                 return rc;
3767         }
3768
3769         if (mdss_dsi_is_te_based_esd(ctrl_pdata)) {
3770                 rc = devm_request_irq(&pdev->dev,
3771                         gpio_to_irq(ctrl_pdata->disp_te_gpio),
3772                         hw_vsync_handler, IRQF_TRIGGER_FALLING,
3773                         "VSYNC_GPIO", ctrl_pdata);
3774                 if (rc) {
3775                         pr_err("%s: TE request_irq failed for ESD\n", __func__);
3776                         goto error_shadow_clk_deinit;
3777                 }
3778                 te_irq_registered = 1;
3779                 disable_irq(gpio_to_irq(ctrl_pdata->disp_te_gpio));
3780         }
3781
3782         pdata = &ctrl_pdata->panel_data;
3783         init_completion(&pdata->te_done);
3784         if (pdata->panel_info.type == MIPI_CMD_PANEL) {
3785                 if (!te_irq_registered) {
3786                         rc = devm_request_irq(&pdev->dev,
3787                                 gpio_to_irq(pdata->panel_te_gpio),
3788                                 test_hw_vsync_handler, IRQF_TRIGGER_FALLING,
3789                                 "VSYNC_GPIO", &ctrl_pdata->panel_data);
3790                         if (rc) {
3791                                 pr_err("%s: TE request_irq failed\n", __func__);
3792                                 goto error_shadow_clk_deinit;
3793                         }
3794                         te_irq_registered = 1;
3795                         disable_irq_nosync(gpio_to_irq(pdata->panel_te_gpio));
3796                 }
3797         }
3798
3799         rc = mdss_dsi_get_bridge_chip_params(pinfo, ctrl_pdata, pdev);
3800         if (rc) {
3801                 pr_err("%s: Failed to get bridge params\n", __func__);
3802                 goto error_shadow_clk_deinit;
3803         }
3804
3805         ctrl_pdata->workq = create_workqueue("mdss_dsi_dba");
3806         if (!ctrl_pdata->workq) {
3807                 pr_err("%s: Error creating workqueue\n", __func__);
3808                 rc = -EPERM;
3809                 goto error_pan_node;
3810         }
3811
3812         INIT_DELAYED_WORK(&ctrl_pdata->dba_work, mdss_dsi_dba_work);
3813
3814         rc = mdss_dsi_ctrl_validate_config(ctrl_pdata);
3815         if (rc) {
3816                 pr_err("%s: invalid controller configuration\n", __func__);
3817                 goto error_shadow_clk_deinit;
3818         }
3819
3820         pr_info("%s: Dsi Ctrl->%d initialized, DSI rev:0x%x, PHY rev:0x%x\n",
3821                 __func__, index, ctrl_pdata->shared_data->hw_rev,
3822                 ctrl_pdata->shared_data->phy_rev);
3823         mdss_dsi_pm_qos_add_request(ctrl_pdata);
3824
3825         if (index == 0)
3826                 ctrl_pdata->shared_data->dsi0_active = true;
3827         else
3828                 ctrl_pdata->shared_data->dsi1_active = true;
3829
3830         mdss_dsi_debug_bus_init(mdss_dsi_res);
3831
3832         init_completion(&ctrl_pdata->wake_comp);
3833         init_waitqueue_head(&ctrl_pdata->wake_waitq);
3834         ctrl_pdata->wake_thread =
3835                 kthread_run_perf_critical(mdss_dsi_disp_wake_thread,
3836                                           ctrl_pdata, "mdss_display_wake");
3837         if (IS_ERR(ctrl_pdata->wake_thread)) {
3838                 rc = PTR_ERR(ctrl_pdata->wake_thread);
3839                 pr_err("%s: Failed to start display wake thread, rc=%d\n",
3840                        __func__, rc);
3841                 goto error_shadow_clk_deinit;
3842         }
3843
3844         /* It's sad but not fatal for the fb client register to fail */
3845         ctrl_pdata->wake_notif.notifier_call = mdss_dsi_fb_unblank_cb;
3846         ctrl_pdata->wake_notif.priority = INT_MAX;
3847         fb_register_client(&ctrl_pdata->wake_notif);
3848
3849         return 0;
3850
3851 error_shadow_clk_deinit:
3852         mdss_dsi_shadow_clk_deinit(&pdev->dev, ctrl_pdata);
3853 error_pan_node:
3854         mdss_dsi_unregister_bl_settings(ctrl_pdata);
3855         of_node_put(dsi_pan_node);
3856         return rc;
3857 }
3858
3859 static int mdss_dsi_bus_scale_init(struct platform_device *pdev,
3860                             struct dsi_shared_data  *sdata)
3861 {
3862         int rc = 0;
3863
3864         sdata->bus_scale_table = msm_bus_cl_get_pdata(pdev);
3865         if (IS_ERR_OR_NULL(sdata->bus_scale_table)) {
3866                 rc = PTR_ERR(sdata->bus_scale_table);
3867                 pr_err("%s: msm_bus_cl_get_pdata() failed, rc=%d\n", __func__,
3868                                                                      rc);
3869                 return rc;
3870                 sdata->bus_scale_table = NULL;
3871         }
3872
3873         sdata->bus_handle =
3874                 msm_bus_scale_register_client(sdata->bus_scale_table);
3875
3876         if (!sdata->bus_handle) {
3877                 rc = -EINVAL;
3878                 pr_err("%sbus_client register failed\n", __func__);
3879         }
3880
3881         return rc;
3882 }
3883
3884 static void mdss_dsi_bus_scale_deinit(struct dsi_shared_data *sdata)
3885 {
3886         if (sdata->bus_handle) {
3887                 if (sdata->bus_refcount)
3888                         msm_bus_scale_client_update_request(sdata->bus_handle,
3889                                                                         0);
3890
3891                 sdata->bus_refcount = 0;
3892                 msm_bus_scale_unregister_client(sdata->bus_handle);
3893                 sdata->bus_handle = 0;
3894         }
3895 }
3896
3897 static int mdss_dsi_parse_dt_params(struct platform_device *pdev,
3898                 struct dsi_shared_data *sdata)
3899 {
3900         int rc = 0;
3901
3902         rc = of_property_read_u32(pdev->dev.of_node,
3903                         "qcom,mmss-ulp-clamp-ctrl-offset",
3904                         &sdata->ulps_clamp_ctrl_off);
3905         if (!rc) {
3906                 rc = of_property_read_u32(pdev->dev.of_node,
3907                                 "qcom,mmss-phyreset-ctrl-offset",
3908                                 &sdata->ulps_phyrst_ctrl_off);
3909         }
3910
3911         sdata->cmd_clk_ln_recovery_en =
3912                 of_property_read_bool(pdev->dev.of_node,
3913                 "qcom,dsi-clk-ln-recovery");
3914
3915         return 0;
3916 }
3917
3918 static void mdss_dsi_res_deinit(struct platform_device *pdev)
3919 {
3920         int i;
3921         struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev);
3922         struct dsi_shared_data *sdata;
3923
3924         if (!dsi_res) {
3925                 pr_err("%s: DSI root device drvdata not found\n", __func__);
3926                 return;
3927         }
3928
3929         for (i = 0; i < DSI_CTRL_MAX; i++) {
3930                 if (dsi_res->ctrl_pdata[i]) {
3931                         if (dsi_res->ctrl_pdata[i]->ds_registered) {
3932                                 struct mdss_panel_info *pinfo =
3933                                         &dsi_res->ctrl_pdata[i]->
3934                                                 panel_data.panel_info;
3935
3936                                 if (pinfo)
3937                                         mdss_dba_utils_deinit(pinfo->dba_data);
3938                         }
3939
3940                         devm_kfree(&pdev->dev, dsi_res->ctrl_pdata[i]);
3941                 }
3942         }
3943
3944         sdata = dsi_res->shared_data;
3945         if (!sdata)
3946                 goto res_release;
3947
3948         for (i = (DSI_MAX_PM - 1); i >= DSI_CORE_PM; i--) {
3949                 if (msm_dss_config_vreg(&pdev->dev,
3950                                 sdata->power_data[i].vreg_config,
3951                                 sdata->power_data[i].num_vreg, 1) < 0)
3952                         pr_err("%s: failed to de-init vregs for %s\n",
3953                                 __func__, __mdss_dsi_pm_name(i));
3954                 mdss_dsi_put_dt_vreg_data(&pdev->dev,
3955                         &sdata->power_data[i]);
3956         }
3957
3958         mdss_dsi_bus_scale_deinit(sdata);
3959         mdss_dsi_core_clk_deinit(&pdev->dev, sdata);
3960
3961         if (sdata)
3962                 devm_kfree(&pdev->dev, sdata);
3963
3964 res_release:
3965         if (dsi_res)
3966                 devm_kfree(&pdev->dev, dsi_res);
3967
3968         return;
3969 }
3970
3971 static int mdss_dsi_res_init(struct platform_device *pdev)
3972 {
3973         int rc = 0, i;
3974         struct dsi_shared_data *sdata;
3975
3976         mdss_dsi_res = platform_get_drvdata(pdev);
3977         if (!mdss_dsi_res) {
3978                 mdss_dsi_res = devm_kzalloc(&pdev->dev,
3979                                           sizeof(struct mdss_dsi_data),
3980                                           GFP_KERNEL);
3981                 if (!mdss_dsi_res) {
3982                         pr_err("%s: FAILED: cannot alloc dsi data\n",
3983                                __func__);
3984                         rc = -ENOMEM;
3985                         goto mem_fail;
3986                 }
3987
3988                 mdss_dsi_res->shared_data = devm_kzalloc(&pdev->dev,
3989                                 sizeof(struct dsi_shared_data),
3990                                 GFP_KERNEL);
3991                 pr_debug("%s Allocated shared_data=%pK\n", __func__,
3992                                 mdss_dsi_res->shared_data);
3993                 if (!mdss_dsi_res->shared_data) {
3994                         pr_err("%s Unable to alloc mem for shared_data\n",
3995                                         __func__);
3996                         rc = -ENOMEM;
3997                         goto mem_fail;
3998                 }
3999
4000                 sdata = mdss_dsi_res->shared_data;
4001
4002                 rc = mdss_dsi_parse_dt_params(pdev, sdata);
4003                 if (rc) {
4004                         pr_err("%s: failed to parse mdss dsi DT params\n",
4005                                 __func__);
4006                         goto mem_fail;
4007                 }
4008
4009                 rc = mdss_dsi_core_clk_init(pdev, sdata);
4010                 if (rc) {
4011                         pr_err("%s: failed to initialize DSI core clocks\n",
4012                                 __func__);
4013                         goto mem_fail;
4014                 }
4015
4016                 /* Parse the regulator information */
4017                 for (i = DSI_CORE_PM; i < DSI_MAX_PM; i++) {
4018                         rc = mdss_dsi_get_dt_vreg_data(&pdev->dev,
4019                                 pdev->dev.of_node, &sdata->power_data[i], i);
4020                         if (rc) {
4021                                 pr_err("%s: '%s' get_dt_vreg_data failed.rc=%d\n",
4022                                         __func__, __mdss_dsi_pm_name(i), rc);
4023                                 i--;
4024                                 for (; i >= DSI_CORE_PM; i--)
4025                                         mdss_dsi_put_dt_vreg_data(&pdev->dev,
4026                                                 &sdata->power_data[i]);
4027                                 goto mem_fail;
4028                         }
4029                 }
4030                 rc = mdss_dsi_regulator_init(pdev, sdata);
4031                 if (rc) {
4032                         pr_err("%s: failed to init regulator, rc=%d\n",
4033                                                         __func__, rc);
4034                         goto mem_fail;
4035                 }
4036
4037                 rc = mdss_dsi_bus_scale_init(pdev, sdata);
4038                 if (rc) {
4039                         pr_err("%s: failed to init bus scale settings, rc=%d\n",
4040                                                         __func__, rc);
4041                         goto mem_fail;
4042                 }
4043
4044                 mutex_init(&sdata->phy_reg_lock);
4045                 mutex_init(&sdata->pm_qos_lock);
4046
4047                 for (i = 0; i < DSI_CTRL_MAX; i++) {
4048                         mdss_dsi_res->ctrl_pdata[i] = devm_kzalloc(&pdev->dev,
4049                                         sizeof(struct mdss_dsi_ctrl_pdata),
4050                                         GFP_KERNEL);
4051                         if (!mdss_dsi_res->ctrl_pdata[i]) {
4052                                 pr_err("%s Unable to alloc mem for ctrl=%d\n",
4053                                                 __func__, i);
4054                                 rc = -ENOMEM;
4055                                 goto mem_fail;
4056                         }
4057                         pr_debug("%s Allocated ctrl_pdata[%d]=%pK\n",
4058                                 __func__, i, mdss_dsi_res->ctrl_pdata[i]);
4059                         mdss_dsi_res->ctrl_pdata[i]->shared_data =
4060                                 mdss_dsi_res->shared_data;
4061                 }
4062
4063                 platform_set_drvdata(pdev, mdss_dsi_res);
4064         }
4065
4066         mdss_dsi_res->pdev = pdev;
4067         pr_debug("%s: Setting up mdss_dsi_res=%pK\n", __func__, mdss_dsi_res);
4068
4069         return 0;
4070
4071 mem_fail:
4072         mdss_dsi_res_deinit(pdev);
4073         return rc;
4074 }
4075
4076 static int mdss_dsi_parse_hw_cfg(struct platform_device *pdev, char *pan_cfg)
4077 {
4078         const char *data;
4079         struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev);
4080         struct dsi_shared_data *sdata;
4081         char dsi_cfg[20];
4082         char *cfg_prim = NULL, *cfg_sec = NULL, *ch = NULL;
4083         int i = 0;
4084
4085         if (!dsi_res) {
4086                 pr_err("%s: DSI root device drvdata not found\n", __func__);
4087                 return -EINVAL;
4088         }
4089
4090         sdata = mdss_dsi_res->shared_data;
4091         if (!sdata) {
4092                 pr_err("%s: DSI shared data not found\n", __func__);
4093                 return -EINVAL;
4094         }
4095
4096         sdata->hw_config = SINGLE_DSI;
4097
4098         if (pan_cfg)
4099                 cfg_prim = strnstr(pan_cfg, "cfg:", strlen(pan_cfg));
4100         if (cfg_prim) {
4101                 cfg_prim += 4;
4102
4103                 cfg_sec = strnchr(cfg_prim, strlen(cfg_prim), ':');
4104                 if (!cfg_sec)
4105                         cfg_sec = cfg_prim + strlen(cfg_prim);
4106
4107                 for (i = 0; ((cfg_prim + i) < cfg_sec) &&
4108                      (*(cfg_prim+i) != '#'); i++)
4109                         dsi_cfg[i] = *(cfg_prim + i);
4110
4111                 dsi_cfg[i] = '\0';
4112                 data = dsi_cfg;
4113         } else {
4114                 data = of_get_property(pdev->dev.of_node,
4115                         "hw-config", NULL);
4116         }
4117
4118         if (data) {
4119                 /*
4120                  * To handle the  override parameter (#override:sim)
4121                  * passed for simulator panels
4122                  */
4123                 ch = strnstr(data, "#", strlen(data));
4124                 ch ? *ch = '\0' : false;
4125
4126                 if (!strcmp(data, "dual_dsi"))
4127                         sdata->hw_config = DUAL_DSI;
4128                 else if (!strcmp(data, "split_dsi"))
4129                         sdata->hw_config = SPLIT_DSI;
4130                 else if (!strcmp(data, "single_dsi"))
4131                         sdata->hw_config = SINGLE_DSI;
4132                 else
4133                         pr_err("%s: Incorrect string for DSI config:%s. Setting default as SINGLE_DSI\n",
4134                                 __func__, data);
4135         } else {
4136                 pr_err("%s: Error: No DSI HW config found\n",
4137                         __func__);
4138                 return -EINVAL;
4139         }
4140
4141         pr_debug("%s: DSI h/w configuration is %d\n", __func__,
4142                 sdata->hw_config);
4143
4144         return 0;
4145 }
4146
4147 static void mdss_dsi_parse_pll_src_cfg(struct platform_device *pdev,
4148         char *pan_cfg)
4149 {
4150         const char *data;
4151         char *pll_ptr, pll_cfg[10] = {'\0'};
4152         struct dsi_shared_data *sdata = mdss_dsi_res->shared_data;
4153
4154         sdata->pll_src_config = PLL_SRC_DEFAULT;
4155
4156         if (pan_cfg) {
4157                 pll_ptr = strnstr(pan_cfg, ":pll0", strlen(pan_cfg));
4158                 if (!pll_ptr) {
4159                         pll_ptr = strnstr(pan_cfg, ":pll1", strlen(pan_cfg));
4160                         if (pll_ptr)
4161                                 strlcpy(pll_cfg, "PLL1", strlen(pll_cfg));
4162                 } else {
4163                         strlcpy(pll_cfg, "PLL0", strlen(pll_cfg));
4164                 }
4165         }
4166         data = pll_cfg;
4167
4168         if (!data || !strcmp(data, ""))
4169                 data = of_get_property(pdev->dev.of_node,
4170                         "pll-src-config", NULL);
4171         if (data) {
4172                 if (!strcmp(data, "PLL0"))
4173                         sdata->pll_src_config = PLL_SRC_0;
4174                 else if (!strcmp(data, "PLL1"))
4175                         sdata->pll_src_config = PLL_SRC_1;
4176                 else
4177                         pr_err("%s: invalid pll src config %s\n",
4178                                 __func__, data);
4179         } else {
4180                 pr_debug("%s: PLL src config not specified\n", __func__);
4181         }
4182
4183         pr_debug("%s: pll_src_config = %d", __func__, sdata->pll_src_config);
4184
4185         return;
4186 }
4187
4188 static int mdss_dsi_validate_pll_src_config(struct dsi_shared_data *sdata)
4189 {
4190         int rc = 0;
4191
4192         /*
4193          * DSI PLL1 can only drive DSI PHY1. As such:
4194          *     - For split dsi config, only PLL0 is supported
4195          *     - For dual dsi config, DSI0-PLL0 and DSI1-PLL1 is the only
4196          *       possible configuration
4197          */
4198         if (mdss_dsi_is_hw_config_split(sdata) &&
4199                 mdss_dsi_is_pll_src_pll1(sdata)) {
4200                 pr_err("%s: unsupported PLL config: using PLL1 for split-dsi\n",
4201                         __func__);
4202                 rc = -EINVAL;
4203                 goto error;
4204         }
4205
4206         if (mdss_dsi_is_hw_config_dual(sdata) &&
4207                 !mdss_dsi_is_pll_src_default(sdata)) {
4208                 pr_debug("%s: pll src config not applicable for dual-dsi\n",
4209                         __func__);
4210                 sdata->pll_src_config = PLL_SRC_DEFAULT;
4211         }
4212
4213 error:
4214         return rc;
4215 }
4216
4217 static int mdss_dsi_validate_config(struct platform_device *pdev)
4218 {
4219         struct dsi_shared_data *sdata = mdss_dsi_res->shared_data;
4220
4221         return mdss_dsi_validate_pll_src_config(sdata);
4222 }
4223
4224 static const struct of_device_id mdss_dsi_ctrl_dt_match[] = {
4225         {.compatible = "qcom,mdss-dsi-ctrl"},
4226         {}
4227 };
4228 MODULE_DEVICE_TABLE(of, mdss_dsi_ctrl_dt_match);
4229
4230 static int mdss_dsi_probe(struct platform_device *pdev)
4231 {
4232         struct mdss_panel_cfg *pan_cfg = NULL;
4233         struct mdss_util_intf *util;
4234         char *panel_cfg;
4235         int rc = 0;
4236
4237         util = mdss_get_util_intf();
4238         if (util == NULL) {
4239                 pr_err("%s: Failed to get mdss utility functions\n", __func__);
4240                 return -ENODEV;
4241         }
4242
4243         if (!util->mdp_probe_done) {
4244                 pr_err("%s: MDP not probed yet!\n", __func__);
4245                 return -EPROBE_DEFER;
4246         }
4247
4248         if (!pdev || !pdev->dev.of_node) {
4249                 pr_err("%s: DSI driver only supports device tree probe\n",
4250                         __func__);
4251                 return -ENOTSUPP;
4252         }
4253
4254         pan_cfg = util->panel_intf_type(MDSS_PANEL_INTF_HDMI);
4255         if (IS_ERR(pan_cfg)) {
4256                 return PTR_ERR(pan_cfg);
4257         } else if (pan_cfg) {
4258                 pr_debug("%s: HDMI is primary\n", __func__);
4259                 return -ENODEV;
4260         }
4261
4262         pan_cfg = util->panel_intf_type(MDSS_PANEL_INTF_DSI);
4263         if (IS_ERR_OR_NULL(pan_cfg)) {
4264                 rc = PTR_ERR(pan_cfg);
4265                 goto error;
4266         } else {
4267                 panel_cfg = pan_cfg->arg_cfg;
4268         }
4269
4270         rc = mdss_dsi_res_init(pdev);
4271         if (rc) {
4272                 pr_err("%s Unable to set dsi res\n", __func__);
4273                 return rc;
4274         }
4275
4276         rc = mdss_dsi_parse_hw_cfg(pdev, panel_cfg);
4277         if (rc) {
4278                 pr_err("%s Unable to parse dsi h/w config\n", __func__);
4279                 mdss_dsi_res_deinit(pdev);
4280                 return rc;
4281         }
4282
4283         mdss_dsi_parse_pll_src_cfg(pdev, panel_cfg);
4284
4285         of_platform_populate(pdev->dev.of_node, mdss_dsi_ctrl_dt_match,
4286                                 NULL, &pdev->dev);
4287
4288         rc = mdss_dsi_validate_config(pdev);
4289         if (rc) {
4290                 pr_err("%s: Invalid DSI hw configuration\n", __func__);
4291                 goto error;
4292         }
4293
4294         mdss_dsi_config_clk_src(pdev);
4295
4296 error:
4297         return rc;
4298 }
4299
4300 static int mdss_dsi_remove(struct platform_device *pdev)
4301 {
4302         mdss_dsi_res_deinit(pdev);
4303         return 0;
4304 }
4305
4306 static int mdss_dsi_ctrl_remove(struct platform_device *pdev)
4307 {
4308         struct msm_fb_data_type *mfd;
4309         struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev);
4310
4311         if (!ctrl_pdata) {
4312                 pr_err("%s: no driver data\n", __func__);
4313                 return -ENODEV;
4314         }
4315
4316         fb_unregister_client(&ctrl_pdata->wake_notif);
4317         kthread_stop(ctrl_pdata->wake_thread);
4318         mdss_dsi_pm_qos_remove_request(ctrl_pdata->shared_data);
4319
4320         if (msm_dss_config_vreg(&pdev->dev,
4321                         ctrl_pdata->panel_power_data.vreg_config,
4322                         ctrl_pdata->panel_power_data.num_vreg, 1) < 0)
4323                 pr_err("%s: failed to de-init vregs for %s\n",
4324                                 __func__, __mdss_dsi_pm_name(DSI_PANEL_PM));
4325         mdss_dsi_put_dt_vreg_data(&pdev->dev, &ctrl_pdata->panel_power_data);
4326
4327         mfd = platform_get_drvdata(pdev);
4328         msm_dss_iounmap(&ctrl_pdata->mmss_misc_io);
4329         msm_dss_iounmap(&ctrl_pdata->phy_io);
4330         msm_dss_iounmap(&ctrl_pdata->ctrl_io);
4331         mdss_dsi_debugfs_cleanup(ctrl_pdata);
4332
4333         if (ctrl_pdata->workq)
4334                 destroy_workqueue(ctrl_pdata->workq);
4335
4336         return 0;
4337 }
4338
4339 struct device dsi_dev;
4340
4341 int mdss_dsi_retrieve_ctrl_resources(struct platform_device *pdev, int mode,
4342                         struct mdss_dsi_ctrl_pdata *ctrl)
4343 {
4344         int rc = 0;
4345         u32 index;
4346
4347         rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index);
4348         if (rc) {
4349                 dev_err(&pdev->dev,
4350                         "%s: Cell-index not specified, rc=%d\n",
4351                                                 __func__, rc);
4352                 return rc;
4353         }
4354
4355         if (index == 0) {
4356                 if (mode != DISPLAY_1) {
4357                         pr_err("%s:%d Panel->Ctrl mapping is wrong\n",
4358                                        __func__, __LINE__);
4359                         return -EPERM;
4360                 }
4361         } else if (index == 1) {
4362                 if (mode != DISPLAY_2) {
4363                         pr_err("%s:%d Panel->Ctrl mapping is wrong\n",
4364                                        __func__, __LINE__);
4365                         return -EPERM;
4366                 }
4367         } else {
4368                 pr_err("%s:%d Unknown Ctrl mapped to panel\n",
4369                                __func__, __LINE__);
4370                 return -EPERM;
4371         }
4372
4373         rc = msm_dss_ioremap_byname(pdev, &ctrl->ctrl_io, "dsi_ctrl");
4374         if (rc) {
4375                 pr_err("%s:%d unable to remap dsi ctrl resources\n",
4376                                __func__, __LINE__);
4377                 return rc;
4378         }
4379
4380         ctrl->ctrl_base = ctrl->ctrl_io.base;
4381         ctrl->reg_size = ctrl->ctrl_io.len;
4382
4383         rc = msm_dss_ioremap_byname(pdev, &ctrl->phy_io, "dsi_phy");
4384         if (rc) {
4385                 pr_err("%s:%d unable to remap dsi phy resources\n",
4386                                __func__, __LINE__);
4387                 return rc;
4388         }
4389
4390         rc = msm_dss_ioremap_byname(pdev, &ctrl->phy_regulator_io,
4391                         "dsi_phy_regulator");
4392         if (rc)
4393                 pr_debug("%s:%d unable to remap dsi phy regulator resources\n",
4394                                __func__, __LINE__);
4395         else
4396                 pr_info("%s: phy_regulator_base=%pK phy_regulator_size=%x\n",
4397                         __func__, ctrl->phy_regulator_io.base,
4398                         ctrl->phy_regulator_io.len);
4399
4400         pr_info("%s: ctrl_base=%pK ctrl_size=%x phy_base=%pK phy_size=%x\n",
4401                 __func__, ctrl->ctrl_base, ctrl->reg_size, ctrl->phy_io.base,
4402                 ctrl->phy_io.len);
4403
4404         rc = msm_dss_ioremap_byname(pdev, &ctrl->mmss_misc_io,
4405                 "mmss_misc_phys");
4406         if (rc) {
4407                 pr_debug("%s:%d mmss_misc IO remap failed\n",
4408                         __func__, __LINE__);
4409         }
4410
4411         return 0;
4412 }
4413
4414 static int mdss_dsi_irq_init(struct device *dev, int irq_no,
4415                         struct mdss_dsi_ctrl_pdata *ctrl)
4416 {
4417         int ret;
4418
4419         ret = devm_request_irq(dev, irq_no, mdss_dsi_isr,
4420                                 0x0, "DSI", ctrl);
4421         if (ret) {
4422                 pr_err("msm_dsi_irq_init request_irq() failed!\n");
4423                 return ret;
4424         }
4425
4426         disable_irq(irq_no);
4427         ctrl->dsi_hw->irq_info = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
4428         if (!ctrl->dsi_hw->irq_info) {
4429                 pr_err("no mem to save irq info: kzalloc fail\n");
4430                 return -ENOMEM;
4431         }
4432         ctrl->dsi_hw->irq_info->irq = irq_no;
4433         ctrl->dsi_hw->irq_info->irq_ena = false;
4434
4435         return ret;
4436 }
4437
4438 static void __set_lane_map(struct mdss_dsi_ctrl_pdata *ctrl,
4439         enum dsi_physical_lane_id lane0,
4440         enum dsi_physical_lane_id lane1,
4441         enum dsi_physical_lane_id lane2,
4442         enum dsi_physical_lane_id lane3)
4443 {
4444         ctrl->lane_map[DSI_LOGICAL_LANE_0] = lane0;
4445         ctrl->lane_map[DSI_LOGICAL_LANE_1] = lane1;
4446         ctrl->lane_map[DSI_LOGICAL_LANE_2] = lane2;
4447         ctrl->lane_map[DSI_LOGICAL_LANE_3] = lane3;
4448 }
4449
4450 static void mdss_dsi_parse_lane_swap(struct device_node *np,
4451         struct mdss_dsi_ctrl_pdata *ctrl)
4452 {
4453         int rc;
4454         const char *data;
4455         u8 temp[DSI_LOGICAL_LANE_MAX];
4456         int i;
4457
4458         /* First, check for the newer version of the binding */
4459         rc = of_property_read_u8_array(np, "qcom,lane-map-v2", temp,
4460                 DSI_LOGICAL_LANE_MAX);
4461         if (!rc) {
4462                 for (i = DSI_LOGICAL_LANE_0; i < DSI_LOGICAL_LANE_MAX; i++)
4463                         ctrl->lane_map[i] = BIT(temp[i]);
4464                 return;
4465         } else if (rc != -EINVAL) {
4466                 pr_warn("%s: invalid lane map specfied. Defaulting to <0 1 2 3>\n",
4467                         __func__);
4468                 goto set_default;
4469         }
4470
4471         /* Check if an older version of the binding is present */
4472         data = of_get_property(np, "qcom,lane-map", NULL);
4473         if (!data)
4474                 goto set_default;
4475
4476         if (!strcmp(data, "lane_map_3012")) {
4477                 ctrl->dlane_swap = DSI_LANE_MAP_3012;
4478                 __set_lane_map(ctrl,
4479                         DSI_PHYSICAL_LANE_1,
4480                         DSI_PHYSICAL_LANE_2,
4481                         DSI_PHYSICAL_LANE_3,
4482                         DSI_PHYSICAL_LANE_0);
4483         } else if (!strcmp(data, "lane_map_2301")) {
4484                 ctrl->dlane_swap = DSI_LANE_MAP_2301;
4485                 __set_lane_map(ctrl,
4486                         DSI_PHYSICAL_LANE_2,
4487                         DSI_PHYSICAL_LANE_3,
4488                         DSI_PHYSICAL_LANE_0,
4489                         DSI_PHYSICAL_LANE_1);
4490         } else if (!strcmp(data, "lane_map_1230")) {
4491                 ctrl->dlane_swap = DSI_LANE_MAP_1230;
4492                 __set_lane_map(ctrl,
4493                         DSI_PHYSICAL_LANE_3,
4494                         DSI_PHYSICAL_LANE_0,
4495                         DSI_PHYSICAL_LANE_1,
4496                         DSI_PHYSICAL_LANE_2);
4497         } else if (!strcmp(data, "lane_map_0321")) {
4498                 ctrl->dlane_swap = DSI_LANE_MAP_0321;
4499                 __set_lane_map(ctrl,
4500                         DSI_PHYSICAL_LANE_0,
4501                         DSI_PHYSICAL_LANE_3,
4502                         DSI_PHYSICAL_LANE_2,
4503                         DSI_PHYSICAL_LANE_1);
4504         } else if (!strcmp(data, "lane_map_1032")) {
4505                 ctrl->dlane_swap = DSI_LANE_MAP_1032;
4506                 __set_lane_map(ctrl,
4507                         DSI_PHYSICAL_LANE_1,
4508                         DSI_PHYSICAL_LANE_0,
4509                         DSI_PHYSICAL_LANE_3,
4510                         DSI_PHYSICAL_LANE_2);
4511         } else if (!strcmp(data, "lane_map_2103")) {
4512                 ctrl->dlane_swap = DSI_LANE_MAP_2103;
4513                 __set_lane_map(ctrl,
4514                         DSI_PHYSICAL_LANE_2,
4515                         DSI_PHYSICAL_LANE_1,
4516                         DSI_PHYSICAL_LANE_0,
4517                         DSI_PHYSICAL_LANE_3);
4518         } else if (!strcmp(data, "lane_map_3210")) {
4519                 ctrl->dlane_swap = DSI_LANE_MAP_3210;
4520                 __set_lane_map(ctrl,
4521                         DSI_PHYSICAL_LANE_3,
4522                         DSI_PHYSICAL_LANE_2,
4523                         DSI_PHYSICAL_LANE_1,
4524                         DSI_PHYSICAL_LANE_0);
4525         } else {
4526                 pr_warn("%s: invalid lane map %s specified. defaulting to lane_map0123\n",
4527                         __func__, data);
4528         }
4529
4530         return;
4531
4532 set_default:
4533         /* default lane mapping */
4534         __set_lane_map(ctrl, DSI_PHYSICAL_LANE_0, DSI_PHYSICAL_LANE_1,
4535                 DSI_PHYSICAL_LANE_2, DSI_PHYSICAL_LANE_3);
4536         ctrl->dlane_swap = DSI_LANE_MAP_0123;
4537 }
4538
4539 static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev,
4540         struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata)
4541 {
4542         int i, len;
4543         struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
4544         const char *data;
4545
4546         ctrl_pdata->null_insert_enabled = of_property_read_bool(
4547                 ctrl_pdev->dev.of_node, "qcom,null-insertion-enabled");
4548
4549         data = of_get_property(ctrl_pdev->dev.of_node,
4550                 "qcom,platform-strength-ctrl", &len);
4551         if (!data) {
4552                 pr_err("%s:%d, Unable to read Phy Strength ctrl settings\n",
4553                         __func__, __LINE__);
4554                 return -EINVAL;
4555         } else {
4556                 pinfo->mipi.dsi_phy_db.strength_len = len;
4557                 for (i = 0; i < len; i++)
4558                         pinfo->mipi.dsi_phy_db.strength[i] = data[i];
4559         }
4560
4561         pinfo->mipi.dsi_phy_db.reg_ldo_mode = of_property_read_bool(
4562                 ctrl_pdev->dev.of_node, "qcom,regulator-ldo-mode");
4563
4564         data = of_get_property(ctrl_pdev->dev.of_node,
4565                 "qcom,platform-regulator-settings", &len);
4566         if (!data) {
4567                 pr_debug("%s:%d, Unable to read Phy regulator settings\n",
4568                         __func__, __LINE__);
4569                 pinfo->mipi.dsi_phy_db.regulator_len = 0;
4570         } else {
4571                 pinfo->mipi.dsi_phy_db.regulator_len = len;
4572                 for (i = 0; i < len; i++)
4573                         pinfo->mipi.dsi_phy_db.regulator[i] = data[i];
4574         }
4575
4576         data = of_get_property(ctrl_pdev->dev.of_node,
4577                 "qcom,platform-bist-ctrl", &len);
4578         if ((!data) || (len != 6))
4579                 pr_debug("%s:%d, Unable to read Phy Bist Ctrl settings\n",
4580                         __func__, __LINE__);
4581         else
4582                 for (i = 0; i < len; i++)
4583                         pinfo->mipi.dsi_phy_db.bistctrl[i] = data[i];
4584
4585         data = of_get_property(ctrl_pdev->dev.of_node,
4586                 "qcom,platform-lane-config", &len);
4587         if (!data) {
4588                 pr_err("%s:%d, Unable to read Phy lane configure settings\n",
4589                         __func__, __LINE__);
4590                 return -EINVAL;
4591         } else {
4592                 pinfo->mipi.dsi_phy_db.lanecfg_len = len;
4593                 for (i = 0; i < len; i++)
4594                         pinfo->mipi.dsi_phy_db.lanecfg[i] = data[i];
4595         }
4596
4597         ctrl_pdata->timing_db_mode = of_property_read_bool(
4598                 ctrl_pdev->dev.of_node, "qcom,timing-db-mode");
4599
4600         ctrl_pdata->cmd_sync_wait_broadcast = of_property_read_bool(
4601                 pan_node, "qcom,cmd-sync-wait-broadcast");
4602
4603         if (ctrl_pdata->cmd_sync_wait_broadcast &&
4604                 mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) &&
4605                 (pinfo->pdest == DISPLAY_2))
4606                 ctrl_pdata->cmd_sync_wait_trigger = true;
4607
4608         pr_debug("%s: cmd_sync_wait_enable=%d trigger=%d\n", __func__,
4609                                 ctrl_pdata->cmd_sync_wait_broadcast,
4610                                 ctrl_pdata->cmd_sync_wait_trigger);
4611
4612         mdss_dsi_parse_lane_swap(ctrl_pdev->dev.of_node, ctrl_pdata);
4613
4614         pinfo->is_pluggable = of_property_read_bool(ctrl_pdev->dev.of_node,
4615                 "qcom,pluggable");
4616
4617         data = of_get_property(ctrl_pdev->dev.of_node,
4618                 "qcom,display-id", &len);
4619         if (!data || len <= 0)
4620                 pr_err("%s:%d Unable to read qcom,display-id, data=%pK,len=%d\n",
4621                         __func__, __LINE__, data, len);
4622         else
4623                 snprintf(ctrl_pdata->panel_data.panel_info.display_id,
4624                         MDSS_DISPLAY_ID_MAX_LEN, "%s", data);
4625
4626         return 0;
4627
4628
4629 }
4630
4631 static int mdss_dsi_parse_gpio_params(struct platform_device *ctrl_pdev,
4632         struct mdss_dsi_ctrl_pdata *ctrl_pdata)
4633 {
4634         /*
4635          * If disp_en_gpio has been set previously (disp_en_gpio > 0)
4636          *  while parsing the panel node, then do not override it
4637          */
4638         struct mdss_panel_data *pdata = &ctrl_pdata->panel_data;
4639
4640         if (ctrl_pdata->disp_en_gpio <= 0) {
4641                 ctrl_pdata->disp_en_gpio = of_get_named_gpio(
4642                         ctrl_pdev->dev.of_node,
4643                         "qcom,platform-enable-gpio", 0);
4644
4645                 if (!gpio_is_valid(ctrl_pdata->disp_en_gpio))
4646                         pr_debug("%s:%d, Disp_en gpio not specified\n",
4647                                         __func__, __LINE__);
4648         }
4649
4650         ctrl_pdata->disp_te_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
4651                 "qcom,platform-te-gpio", 0);
4652
4653         if (!gpio_is_valid(ctrl_pdata->disp_te_gpio))
4654                 pr_err("%s:%d, TE gpio not specified\n",
4655                                                 __func__, __LINE__);
4656         pdata->panel_te_gpio = ctrl_pdata->disp_te_gpio;
4657
4658         ctrl_pdata->bklt_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
4659                 "qcom,platform-bklight-en-gpio", 0);
4660         if (!gpio_is_valid(ctrl_pdata->bklt_en_gpio))
4661                 pr_info("%s: bklt_en gpio not specified\n", __func__);
4662
4663         ctrl_pdata->bklt_en_gpio_invert =
4664                         of_property_read_bool(ctrl_pdev->dev.of_node,
4665                                 "qcom,platform-bklight-en-gpio-invert");
4666
4667         ctrl_pdata->avdd_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
4668                         "qcom,platform-avdd-en-gpio", 0);
4669         if (!gpio_is_valid(ctrl_pdata->avdd_en_gpio))
4670                 pr_info("%s: avdd_en gpio not specified\n", __func__);
4671
4672         ctrl_pdata->avdd_en_gpio_invert =
4673                         of_property_read_bool(ctrl_pdev->dev.of_node,
4674                                 "qcom,platform-avdd-en-gpio-invert");
4675
4676         ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
4677                          "qcom,platform-reset-gpio", 0);
4678         if (!gpio_is_valid(ctrl_pdata->rst_gpio))
4679                 pr_err("%s:%d, reset gpio not specified\n",
4680                                                 __func__, __LINE__);
4681
4682         ctrl_pdata->lcd_mode_sel_gpio = of_get_named_gpio(
4683                         ctrl_pdev->dev.of_node, "qcom,panel-mode-gpio", 0);
4684         if (!gpio_is_valid(ctrl_pdata->lcd_mode_sel_gpio)) {
4685                 pr_debug("%s:%d mode gpio not specified\n", __func__, __LINE__);
4686                 ctrl_pdata->lcd_mode_sel_gpio = -EINVAL;
4687         }
4688
4689         return 0;
4690 }
4691
4692 static void mdss_dsi_set_prim_panel(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
4693 {
4694         struct mdss_dsi_ctrl_pdata *octrl = NULL;
4695         struct mdss_panel_info *pinfo;
4696
4697         pinfo = &ctrl_pdata->panel_data.panel_info;
4698
4699         /*
4700          * for Split and Single DSI case default is always primary
4701          * and for Dual dsi case below assumptions are made.
4702          *      1. DSI controller with bridge chip is always secondary
4703          *      2. When there is no brigde chip, DSI1 is secondary
4704          */
4705         pinfo->is_prim_panel = true;
4706         if (mdss_dsi_is_hw_config_dual(ctrl_pdata->shared_data)) {
4707                 if (mdss_dsi_is_right_ctrl(ctrl_pdata)) {
4708                         octrl = mdss_dsi_get_other_ctrl(ctrl_pdata);
4709                         if (octrl && octrl->panel_data.panel_info.is_prim_panel)
4710                                 pinfo->is_prim_panel = false;
4711                         else
4712                                 pinfo->is_prim_panel = true;
4713                 }
4714         }
4715 }
4716
4717 int dsi_panel_device_register(struct platform_device *ctrl_pdev,
4718         struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata)
4719 {
4720         struct mipi_panel_info *mipi;
4721         int rc;
4722         struct dsi_shared_data *sdata;
4723         struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
4724         struct resource *res;
4725         u64 clk_rate;
4726
4727         mipi  = &(pinfo->mipi);
4728
4729         pinfo->type =
4730                 ((mipi->mode == DSI_VIDEO_MODE)
4731                         ? MIPI_VIDEO_PANEL : MIPI_CMD_PANEL);
4732
4733         pinfo->clk_rate = mdss_dsi_calc_bitclk(pinfo, mipi->frame_rate);
4734         if (!pinfo->clk_rate) {
4735                 pr_err("%s: unable to calculate the DSI bit clock\n", __func__);
4736                 return -EINVAL;
4737         }
4738
4739         pinfo->mipi.dsi_pclk_rate = mdss_dsi_get_pclk_rate(pinfo,
4740                 pinfo->clk_rate);
4741         if (!pinfo->mipi.dsi_pclk_rate) {
4742                 pr_err("%s: unable to calculate the DSI pclk\n", __func__);
4743                 return -EINVAL;
4744         }
4745
4746         ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate;
4747         clk_rate = pinfo->clk_rate;
4748         do_div(clk_rate, 8U);
4749         ctrl_pdata->byte_clk_rate = (u32)clk_rate;
4750         pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
4751                         ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);
4752
4753         ctrl_pdata->esc_clk_rate_hz = pinfo->esc_clk_rate_hz;
4754         pr_debug("%s: esc clk=%d\n", __func__,
4755                         ctrl_pdata->esc_clk_rate_hz);
4756
4757         rc = mdss_dsi_get_dt_vreg_data(&ctrl_pdev->dev, pan_node,
4758                 &ctrl_pdata->panel_power_data, DSI_PANEL_PM);
4759         if (rc) {
4760                 DEV_ERR("%s: '%s' get_dt_vreg_data failed.rc=%d\n",
4761                         __func__, __mdss_dsi_pm_name(DSI_PANEL_PM), rc);
4762                 return rc;
4763         }
4764
4765         rc = msm_dss_config_vreg(&ctrl_pdev->dev,
4766                 ctrl_pdata->panel_power_data.vreg_config,
4767                 ctrl_pdata->panel_power_data.num_vreg, 1);
4768         if (rc) {
4769                 pr_err("%s: failed to init regulator, rc=%d\n",
4770                                                 __func__, rc);
4771                 return rc;
4772         }
4773
4774         rc = mdss_dsi_parse_ctrl_params(ctrl_pdev, pan_node, ctrl_pdata);
4775         if (rc) {
4776                 pr_err("%s: failed to parse ctrl settings, rc=%d\n",
4777                                                 __func__, rc);
4778                 return rc;
4779         }
4780
4781         /* default state of gpio is false */
4782         ctrl_pdata->bklt_en_gpio_state = false;
4783
4784         pinfo->panel_max_fps = mdss_panel_get_framerate(pinfo);
4785         pinfo->panel_max_vtotal = mdss_panel_get_vtotal(pinfo);
4786
4787         rc = mdss_dsi_parse_gpio_params(ctrl_pdev, ctrl_pdata);
4788         if (rc) {
4789                 pr_err("%s: failed to parse gpio params, rc=%d\n",
4790                                                 __func__, rc);
4791                 return rc;
4792         }
4793
4794         if (mdss_dsi_retrieve_ctrl_resources(ctrl_pdev,
4795                                              pinfo->pdest,
4796                                              ctrl_pdata)) {
4797                 pr_err("%s: unable to get Dsi controller res\n", __func__);
4798                 return -EPERM;
4799         }
4800
4801         ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler;
4802         ctrl_pdata->panel_data.get_fb_node = mdss_dsi_get_fb_node_cb;
4803
4804         if (ctrl_pdata->status_mode == ESD_REG ||
4805                         ctrl_pdata->status_mode == ESD_REG_NT35596)
4806                 ctrl_pdata->check_status = mdss_dsi_reg_status_check;
4807         else if (ctrl_pdata->status_mode == ESD_REG_MULTI)
4808                 ctrl_pdata->check_status = mdss_dsi_multi_reg_status_check;
4809         else if (ctrl_pdata->status_mode == ESD_BTA)
4810                 ctrl_pdata->check_status = mdss_dsi_bta_status_check;
4811
4812         if (ctrl_pdata->status_mode == ESD_MAX) {
4813                 pr_err("%s: Using default BTA for ESD check\n", __func__);
4814                 ctrl_pdata->check_status = mdss_dsi_bta_status_check;
4815         }
4816         if (ctrl_pdata->bklt_ctrl == BL_PWM)
4817                 mdss_dsi_panel_pwm_cfg(ctrl_pdata);
4818
4819         mdss_dsi_ctrl_init(&ctrl_pdev->dev, ctrl_pdata);
4820         mdss_dsi_set_prim_panel(ctrl_pdata);
4821
4822         ctrl_pdata->dsi_irq_line = of_property_read_bool(
4823                                 ctrl_pdev->dev.of_node, "qcom,dsi-irq-line");
4824
4825         if (ctrl_pdata->dsi_irq_line) {
4826                 /* DSI has it's own irq line */
4827                 res = platform_get_resource(ctrl_pdev, IORESOURCE_IRQ, 0);
4828                 if (!res || res->start == 0) {
4829                         pr_err("%s:%d unable to get the MDSS irq resources\n",
4830                                                         __func__, __LINE__);
4831                         return -ENODEV;
4832                 }
4833                 rc = mdss_dsi_irq_init(&ctrl_pdev->dev, res->start, ctrl_pdata);
4834                 if (rc) {
4835                         dev_err(&ctrl_pdev->dev, "%s: failed to init irq\n",
4836                                                         __func__);
4837                         return rc;
4838                 }
4839         }
4840         ctrl_pdata->ctrl_state = CTRL_STATE_UNKNOWN;
4841
4842         /*
4843          * If ULPS during suspend is enabled, add an extra vote for the
4844          * DSI CTRL power module. This keeps the regulator always enabled.
4845          * This is needed for the DSI PHY to maintain ULPS state during
4846          * suspend also.
4847          */
4848         sdata = ctrl_pdata->shared_data;
4849
4850         if (pinfo->ulps_suspend_enabled) {
4851                 rc = msm_dss_enable_vreg(
4852                         sdata->power_data[DSI_PHY_PM].vreg_config,
4853                         sdata->power_data[DSI_PHY_PM].num_vreg, 1);
4854                 if (rc) {
4855                         pr_err("%s: failed to enable vregs for DSI_CTRL_PM\n",
4856                                 __func__);
4857                         return rc;
4858                 }
4859         }
4860
4861         pinfo->cont_splash_enabled =
4862                 ctrl_pdata->mdss_util->panel_intf_status(pinfo->pdest,
4863                 MDSS_PANEL_INTF_DSI) ? true : false;
4864
4865         pr_info("%s: Continuous splash %s\n", __func__,
4866                 pinfo->cont_splash_enabled ? "enabled" : "disabled");
4867
4868         rc = mdss_register_panel(ctrl_pdev, &(ctrl_pdata->panel_data));
4869         if (rc) {
4870                 pr_err("%s: unable to register MIPI DSI panel\n", __func__);
4871                 return rc;
4872         }
4873
4874         if (pinfo->pdest == DISPLAY_1) {
4875                 mdss_debug_register_io("dsi0_ctrl", &ctrl_pdata->ctrl_io, NULL);
4876                 mdss_debug_register_io("dsi0_phy", &ctrl_pdata->phy_io, NULL);
4877                 if (ctrl_pdata->phy_regulator_io.len)
4878                         mdss_debug_register_io("dsi0_phy_regulator",
4879                                 &ctrl_pdata->phy_regulator_io, NULL);
4880         } else {
4881                 mdss_debug_register_io("dsi1_ctrl", &ctrl_pdata->ctrl_io, NULL);
4882                 mdss_debug_register_io("dsi1_phy", &ctrl_pdata->phy_io, NULL);
4883                 if (ctrl_pdata->phy_regulator_io.len)
4884                         mdss_debug_register_io("dsi1_phy_regulator",
4885                                 &ctrl_pdata->phy_regulator_io, NULL);
4886         }
4887
4888         panel_debug_register_base("panel",
4889                 ctrl_pdata->ctrl_base, ctrl_pdata->reg_size);
4890
4891         pr_debug("%s: Panel data initialized\n", __func__);
4892         return 0;
4893 }
4894
4895 static const struct of_device_id mdss_dsi_dt_match[] = {
4896         {.compatible = "qcom,mdss-dsi"},
4897         {}
4898 };
4899 MODULE_DEVICE_TABLE(of, mdss_dsi_dt_match);
4900
4901 static struct platform_driver mdss_dsi_driver = {
4902         .probe = mdss_dsi_probe,
4903         .remove = mdss_dsi_remove,
4904         .shutdown = NULL,
4905         .driver = {
4906                 .name = "mdss_dsi",
4907                 .of_match_table = mdss_dsi_dt_match,
4908         },
4909 };
4910
4911 static struct platform_driver mdss_dsi_ctrl_driver = {
4912         .probe = mdss_dsi_ctrl_probe,
4913         .remove = mdss_dsi_ctrl_remove,
4914         .shutdown = NULL,
4915         .driver = {
4916                 .name = "mdss_dsi_ctrl",
4917                 .of_match_table = mdss_dsi_ctrl_dt_match,
4918         },
4919 };
4920
4921 static int mdss_dsi_register_driver(void)
4922 {
4923         return platform_driver_register(&mdss_dsi_driver);
4924 }
4925
4926 static int __init mdss_dsi_driver_init(void)
4927 {
4928         int ret;
4929
4930         ret = mdss_dsi_register_driver();
4931         if (ret) {
4932                 pr_err("mdss_dsi_register_driver() failed!\n");
4933                 return ret;
4934         }
4935
4936         return ret;
4937 }
4938 module_init(mdss_dsi_driver_init);
4939
4940
4941 static int mdss_dsi_ctrl_register_driver(void)
4942 {
4943         return platform_driver_register(&mdss_dsi_ctrl_driver);
4944 }
4945
4946 static int __init mdss_dsi_ctrl_driver_init(void)
4947 {
4948         int ret;
4949
4950         ret = mdss_dsi_ctrl_register_driver();
4951         if (ret) {
4952                 pr_err("mdss_dsi_ctrl_register_driver() failed!\n");
4953                 return ret;
4954         }
4955
4956         return ret;
4957 }
4958 module_init(mdss_dsi_ctrl_driver_init);
4959
4960 static void __exit mdss_dsi_driver_cleanup(void)
4961 {
4962         platform_driver_unregister(&mdss_dsi_ctrl_driver);
4963 }
4964 module_exit(mdss_dsi_driver_cleanup);
4965
4966 MODULE_LICENSE("GPL v2");
4967 MODULE_DESCRIPTION("DSI controller driver");
4968 MODULE_AUTHOR("Chandan Uddaraju <chandanu@codeaurora.org>");