6 #define VS1011E_OPCODE_READ 0x03
7 #define VS1011E_OPCODE_WRITE 0x02
9 #define REGADDR_MODE 0x00
10 #define REGADDR_STATUS 0x01
11 #define REGADDR_BASS 0x02
12 #define REGADDR_CLOCKF 0x03
13 #define REGADDR_DECODE_TIME 0x04
14 #define REGADDR_AUDATA 0x05
15 #define REGADDR_WRAM 0x06
16 #define REGADDR_WRAMADDR 0x07
17 #define REGADDR_HDAT0 0x08
18 #define REGADDR_HDAT1 0x09
19 #define REGADDR_AIADDR 0x0A
20 #define REGADDR_VOL 0x0B
21 #define REGADDR_AICTRL0 0x0C
22 #define REGADDR_AICTRL1 0x0D
23 #define REGADDR_AICTRL2 0x0E
24 #define REGADDR_AICTRL3 0x0F
26 #define SM_DIFF (1 << 0)
27 #define SM_LAYER12 (1 << 1)
28 #define SM_RESET (1 << 2)
29 #define SM_OUTOFWAV (1 << 3)
30 #define SM_SETTOZERO1 (1 << 4)
31 #define SM_TESTS (1 << 5)
32 #define SM_STREAM (1 << 6)
33 #define SM_SETTOZERO2 (1 << 7)
34 #define SM_DACT (1 << 8)
35 #define SM_SDIORD (1 << 9)
36 #define SM_SDISHARE (1 << 10)
37 #define SM_SDINEW (1 << 11)
38 #define SM_SETTOZERO3 (1 << 12)
39 #define SM_SETTOZERO4 (1 << 13)
41 #define SCI_BASS_BITBASS_ST_AMP 12
42 #define SCI_BASS_BITBASS_ST_FREQ 8
43 #define SCI_BASS_BITBASS_SB_AMP 4
44 #define SCI_BASS_BITBASS_SB_FREQ 0
46 #define VS1011E_RESET1() do { *PORTCONF_P4DR |= PORTCONF_P4BIT_VSRST; } while (0)
47 #define VS1011E_RESET0() do { *PORTCONF_P4DR &= ~PORTCONF_P4BIT_VSRST; } while (0)
49 #define VS1011E_CHK_DREQ() (((*PORTCONF_P4DR) & PORTCONF_P4BIT_VSDREQ) ? 0 : 1)
51 static void _delay_ms(int ms)
54 for (i = 0; i < ms * 10000; i++) {
58 static void _delay_us(int us)
61 for (i = 0; i < us * 10; i++) {
65 static void vs1011e_read(uint8 addr, uint16 * stat);
66 static void vs1011e_write(uint8 addr, uint16 stat);
70 vs1011e_reset_by_hardware();
71 vs1011e_reset_by_software();
74 void vs1011e_reset_by_hardware()
76 // Assert vs1011 reset
82 // Release vs1011 reset
84 // Delay 10ms (2.5ms accordig to datasheet)
86 // Set volume to minimum
87 vs1011e_write(REGADDR_VOL, 0xFFFF);
89 vs1011e_write(REGADDR_CLOCKF, 0x9800);
92 // Set slow sample rate for slow analog part startup
93 vs1011e_write(REGADDR_AUDATA, 10);
96 // Switch on the analog parts
97 vs1011e_write(REGADDR_VOL, 0xFEFE);
98 vs1011e_write(REGADDR_AUDATA, 44101);
99 vs1011e_write(REGADDR_VOL, 0x0202);
102 void vs1011e_reset_by_software()
108 // Set SW reset bit, set VS1011 native mode on SPI
109 vs1011e_write(REGADDR_MODE,
110 SM_LAYER12 | SM_RESET | SM_SDINEW | SM_TESTS);
113 // Rewrite SCI_CLOCKF after soft reset
114 vs1011e_write(REGADDR_CLOCKF, 0x9800);
116 spi_select(SpiTarget_VS1011E_DATA);
118 while (VS1011E_CHK_DREQ()) {
123 for (i = 0; i < 1024; i++) {
125 while (VS1011E_CHK_DREQ()) {
133 void vs1011e_cancel_data()
136 while (VS1011E_CHK_DREQ()) {
139 spi_select(SpiTarget_VS1011E_DATA);
140 for (i = 0; i < 2048; i++) {
141 while (VS1011E_CHK_DREQ()) {
148 void vs1011e_set_enhancer(uint8 st_amp, uint8 st_freq, uint8 sb_amp,
152 (st_amp << SCI_BASS_BITBASS_ST_AMP) |
153 (st_freq << SCI_BASS_BITBASS_ST_FREQ) |
154 (sb_amp << SCI_BASS_BITBASS_SB_AMP) |
155 (sb_freq << SCI_BASS_BITBASS_SB_FREQ);
156 vs1011e_write(REGADDR_BASS, val);
159 void vs1011e_get_enhancer(uint8 * st_amp, uint8 * st_freq,
160 uint8 * sb_amp, uint8 * sb_freq)
163 vs1011e_read(REGADDR_BASS, &val);
164 *st_amp = (val >> SCI_BASS_BITBASS_ST_AMP) & 0x0F;
165 *st_freq = (val >> SCI_BASS_BITBASS_ST_FREQ) & 0x0F;
166 *sb_amp = (val >> SCI_BASS_BITBASS_SB_AMP) & 0x0F;
167 *sb_freq = (val >> SCI_BASS_BITBASS_SB_FREQ) & 0x0F;
170 void vs1011e_volume_read(uint8 * left, uint8 * right)
173 vs1011e_read(REGADDR_VOL, &val);
178 void vs1011e_volume_write(const uint8 left, const uint8 right)
181 (((uint16) left << 8) & 0xFF00) | (((uint16) right << 0) &
183 vs1011e_write(REGADDR_VOL, val);
188 int (*readfunc)(void * buf, const int len))
193 * Read the song data.
195 int n = readfunc(buf, siz);
202 spi_select(SpiTarget_VS1011E_DATA);
203 for (i = 0; i < n; i++) {
204 while (VS1011E_CHK_DREQ()) { }
205 spi_tx(*((char *)buf + i));
211 void vs1011e_decodetime_read(uint16 * sec)
213 vs1011e_read(REGADDR_DECODE_TIME, sec);
216 void vs1011e_decodetime_write(const uint16 sec)
218 vs1011e_write(REGADDR_DECODE_TIME, sec);
221 void vs1011e_sinetest_init()
223 while (VS1011E_CHK_DREQ()) {
226 spi_select(SpiTarget_VS1011E_DATA);
238 void vs1011e_sinetest_fini()
240 while (VS1011E_CHK_DREQ()) {
243 spi_select(SpiTarget_VS1011E_DATA);
254 vs1011e_cancel_data();
257 void vs1011e_register_print()
262 xprintf(PSTR("===================\r\n"));
263 for (i = 0; i <= 0x0F; i++) {
264 vs1011e_read(i, &val);
265 xprintf(PSTR("0x%02X: 0x%04X\r\n"), i, val);
267 xprintf(PSTR("===================\r\n"));
271 static void vs1011e_read(uint8 addr, uint16 * stat)
273 while (VS1011E_CHK_DREQ()) {
276 spi_select(SpiTarget_VS1011E_CTRL);
278 spi_tx(VS1011E_OPCODE_READ);
282 *stat |= spi_rx() << 8;
288 static void vs1011e_write(uint8 addr, uint16 stat)
290 while (VS1011E_CHK_DREQ()) {
293 spi_select(SpiTarget_VS1011E_CTRL);
295 spi_tx(VS1011E_OPCODE_WRITE);