1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
30 #include "opcode/m68k.h"
31 #include "m68k-parse.h"
41 /* This string holds the chars that always start a comment. If the
42 pre-processor is disabled, these aren't very useful. The macro
43 tc_comment_chars points to this. We use this, rather than the
44 usual comment_chars, so that the --bitwise-or option will work. */
45 #if defined (TE_SVR4) || defined (TE_DELTA)
46 const char *m68k_comment_chars = "|#";
48 const char *m68k_comment_chars = "|";
51 /* This array holds the chars that only start a comment at the beginning of
52 a line. If the line seems to have the form '# 123 filename'
53 .line and .file directives will appear in the pre-processed output */
54 /* Note that input_file.c hand checks for '#' at the beginning of the
55 first line of the input file. This is because the compiler outputs
56 #NO_APP at the beginning of its output. */
57 /* Also note that comments like this one will always work. */
58 const char line_comment_chars[] = "#*";
60 const char line_separator_chars[] = ";";
62 /* Chars that can be used to separate mant from exp in floating point nums. */
63 const char EXP_CHARS[] = "eE";
65 /* Chars that mean this number is a floating point constant, as
66 in "0f12.456" or "0d1.2345e12". */
68 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
70 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
71 changed in read.c . Ideally it shouldn't have to know about it at all,
72 but nothing is ideal around here. */
74 /* Are we trying to generate PIC code? If so, absolute references
75 ought to be made into linkage table references or pc-relative
76 references. Not implemented. For ELF there are other means
77 to denote pic relocations. */
80 static int flag_short_refs; /* -l option. */
81 static int flag_long_jumps; /* -S option. */
82 static int flag_keep_pcrel; /* --pcrel option. */
84 #ifdef REGISTER_PREFIX_OPTIONAL
85 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
87 int flag_reg_prefix_optional;
90 /* Whether --register-prefix-optional was used on the command line. */
91 static int reg_prefix_optional_seen;
93 /* The floating point coprocessor to use by default. */
94 static enum m68k_register m68k_float_copnum = COP1;
96 /* If this is non-zero, then references to number(%pc) will be taken
97 to refer to number, rather than to %pc + number. */
98 static int m68k_abspcadd;
100 /* If this is non-zero, then the quick forms of the move, add, and sub
101 instructions are used when possible. */
102 static int m68k_quick = 1;
104 /* If this is non-zero, then if the size is not specified for a base
105 or outer displacement, the assembler assumes that the size should
107 static int m68k_rel32 = 1;
109 /* This is non-zero if m68k_rel32 was set from the command line. */
110 static int m68k_rel32_from_cmdline;
112 /* The default width to use for an index register when using a base
114 static enum m68k_size m68k_index_width_default = SIZE_LONG;
116 /* We want to warn if any text labels are misaligned. In order to get
117 the right line number, we need to record the line number for each
121 struct label_line *next;
128 /* The list of labels. */
130 static struct label_line *labels;
132 /* The current label. */
134 static struct label_line *current_label;
136 /* Pointer to list holding the opcodes sorted by name. */
137 static struct m68k_opcode const ** m68k_sorted_opcodes;
139 /* Its an arbitrary name: This means I don't approve of it.
141 static struct obstack robyn;
145 const char *m_operands;
146 unsigned long m_opcode;
150 struct m68k_incant *m_next;
153 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
154 #define gettwo(x) (((x)->m_opcode)&0xffff)
156 static const enum m68k_register m68000_ctrl[] = { 0 };
157 static const enum m68k_register m68010_ctrl[] = {
161 static const enum m68k_register m68020_ctrl[] = {
162 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
165 static const enum m68k_register m68040_ctrl[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
167 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
170 static const enum m68k_register m68060_ctrl[] = {
171 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
172 USP, VBR, URP, SRP, PCR,
175 static const enum m68k_register mcf_ctrl[] = {
176 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
177 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
180 static const enum m68k_register mcf51qe_ctrl[] = {
184 static const enum m68k_register mcf5206_ctrl[] = {
185 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
188 static const enum m68k_register mcf5208_ctrl[] = {
189 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
192 static const enum m68k_register mcf5210a_ctrl[] = {
193 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
196 static const enum m68k_register mcf5213_ctrl[] = {
197 VBR, RAMBAR, RAMBAR1, FLASHBAR,
200 static const enum m68k_register mcf5216_ctrl[] = {
201 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
204 static const enum m68k_register mcf52223_ctrl[] = {
205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
208 static const enum m68k_register mcf52235_ctrl[] = {
209 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
212 static const enum m68k_register mcf5225_ctrl[] = {
213 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
216 static const enum m68k_register mcf5235_ctrl[] = {
217 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
220 static const enum m68k_register mcf5249_ctrl[] = {
221 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
224 static const enum m68k_register mcf5250_ctrl[] = {
228 static const enum m68k_register mcf5253_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
232 static const enum m68k_register mcf5271_ctrl[] = {
233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
236 static const enum m68k_register mcf5272_ctrl[] = {
237 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
240 static const enum m68k_register mcf5275_ctrl[] = {
241 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
244 static const enum m68k_register mcf5282_ctrl[] = {
245 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
248 static const enum m68k_register mcf5307_ctrl[] = {
249 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252 static const enum m68k_register mcf5329_ctrl[] = {
253 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
256 static const enum m68k_register mcf5373_ctrl[] = {
257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
260 static const enum m68k_register mcfv4e_ctrl[] = {
261 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
262 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
264 MPCR /* Multiprocessor Control register */,
265 EDRAMBAR /* Embedded DRAM Base Address Register */,
266 /* Permutation control registers. */
267 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
268 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
270 TC /* ASID */, BUSCR /* MMUBAR */,
271 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
272 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
273 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
276 static const enum m68k_register mcf5407_ctrl[] = {
277 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
278 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
281 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
282 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
285 static const enum m68k_register mcf54455_ctrl[] = {
286 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
287 VBR, PC, RAMBAR1, MBAR,
289 TC /* ASID */, BUSCR /* MMUBAR */,
290 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
291 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
294 static const enum m68k_register mcf5475_ctrl[] = {
295 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
296 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
298 TC /* ASID */, BUSCR /* MMUBAR */,
299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
300 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
303 static const enum m68k_register mcf5485_ctrl[] = {
304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
305 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
307 TC /* ASID */, BUSCR /* MMUBAR */,
308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
309 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
312 static const enum m68k_register fido_ctrl[] = {
313 SFC, DFC, USP, VBR, CAC, MBO,
316 #define cpu32_ctrl m68010_ctrl
318 static const enum m68k_register *control_regs;
320 /* Internal form of a 68020 instruction. */
324 const char *args; /* List of opcode info. */
327 int numo; /* Number of shorts in opcode. */
330 struct m68k_op operands[6];
332 int nexp; /* Number of exprs in use. */
333 struct m68k_exp exprs[4];
335 int nfrag; /* Number of frags we have to produce. */
338 int fragoff; /* Where in the current opcode the frag ends. */
345 int nrel; /* Num of reloc strucs in use. */
352 /* In a pc relative address the difference between the address
353 of the offset and the address that the offset is relative
354 to. This depends on the addressing mode. Basically this
355 is the value to put in the offset field to address the
356 first byte of the offset, without regarding the special
357 significance of some values (in the branch instruction, for
361 /* Whether this expression needs special pic relocation, and if
363 enum pic_relocation pic_reloc;
366 reloc[5]; /* Five is enough??? */
369 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
370 #define float_of_arch(x) ((x) & mfloat)
371 #define mmu_of_arch(x) ((x) & mmmu)
372 #define arch_coldfire_p(x) ((x) & mcfisa_a)
373 #define arch_coldfire_fpu(x) ((x) & cfloat)
375 /* Macros for determining if cpu supports a specific addressing mode. */
376 #define HAVE_LONG_DISP(x) \
377 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
378 #define HAVE_LONG_CALL(x) \
379 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
380 #define HAVE_LONG_COND(x) \
381 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
382 #define HAVE_LONG_BRANCH(x) \
383 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
384 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
386 static struct m68k_it the_ins; /* The instruction being assembled. */
388 #define op(ex) ((ex)->exp.X_op)
389 #define adds(ex) ((ex)->exp.X_add_symbol)
390 #define subs(ex) ((ex)->exp.X_op_symbol)
391 #define offs(ex) ((ex)->exp.X_add_number)
393 /* Macros for adding things to the m68k_it struct. */
394 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
396 /* Like addword, but goes BEFORE general operands. */
399 insop (int w, const struct m68k_incant *opcode)
402 for (z = the_ins.numo; z > opcode->m_codenum; --z)
403 the_ins.opcode[z] = the_ins.opcode[z - 1];
404 for (z = 0; z < the_ins.nrel; z++)
405 the_ins.reloc[z].n += 2;
406 for (z = 0; z < the_ins.nfrag; z++)
407 the_ins.fragb[z].fragoff++;
408 the_ins.opcode[opcode->m_codenum] = w;
412 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
415 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
417 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
418 ? the_ins.numo * 2 - 1
420 ? the_ins.numo * 2 + 1
421 : the_ins.numo * 2));
422 the_ins.reloc[the_ins.nrel].exp = exp->exp;
423 the_ins.reloc[the_ins.nrel].wid = width;
424 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
426 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
428 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
431 /* Cause an extra frag to be generated here, inserting up to 10 bytes
432 (that value is chosen in the frag_var call in md_assemble). TYPE
433 is the subtype of the frag to be generated; its primary type is
434 rs_machine_dependent.
436 The TYPE parameter is also used by md_convert_frag_1 and
437 md_estimate_size_before_relax. The appropriate type of fixup will
438 be emitted by md_convert_frag_1.
440 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
442 add_frag (symbolS *add, offsetT off, int type)
444 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
445 the_ins.fragb[the_ins.nfrag].fadd = add;
446 the_ins.fragb[the_ins.nfrag].foff = off;
447 the_ins.fragb[the_ins.nfrag++].fragty = type;
451 (op (ex) != O_constant && op (ex) != O_big)
453 static char *crack_operand (char *str, struct m68k_op *opP);
454 static int get_num (struct m68k_exp *exp, int ok);
455 static int reverse_16_bits (int in);
456 static int reverse_8_bits (int in);
457 static void install_gen_operand (int mode, int val);
458 static void install_operand (int mode, int val);
459 static void s_bss (int);
460 static void s_data1 (int);
461 static void s_data2 (int);
462 static void s_even (int);
463 static void s_proc (int);
464 static void s_chip (int);
465 static void s_fopt (int);
466 static void s_opt (int);
467 static void s_reg (int);
468 static void s_restore (int);
469 static void s_save (int);
470 static void s_mri_if (int);
471 static void s_mri_else (int);
472 static void s_mri_endi (int);
473 static void s_mri_break (int);
474 static void s_mri_next (int);
475 static void s_mri_for (int);
476 static void s_mri_endf (int);
477 static void s_mri_repeat (int);
478 static void s_mri_until (int);
479 static void s_mri_while (int);
480 static void s_mri_endw (int);
481 static void s_m68k_cpu (int);
482 static void s_m68k_arch (int);
486 unsigned long arch; /* Architecture features. */
487 const enum m68k_register *control_regs; /* Control regs on chip */
488 const char *name; /* Name */
489 int alias; /* Alias for a cannonical name. If 1, then
490 succeeds canonical name, if -1 then
491 succeeds canonical name, if <-1 ||>1 this is a
492 deprecated name, and the next/previous name
496 /* We hold flags for features explicitly enabled and explicitly
498 static int current_architecture;
499 static int not_current_architecture;
500 static const struct m68k_cpu *selected_arch;
501 static const struct m68k_cpu *selected_cpu;
502 static int initialized;
504 /* Architecture models. */
505 static const struct m68k_cpu m68k_archs[] =
507 {m68000, m68000_ctrl, "68000", 0},
508 {m68010, m68010_ctrl, "68010", 0},
509 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
510 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
511 {m68040, m68040_ctrl, "68040", 0},
512 {m68060, m68060_ctrl, "68060", 0},
513 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
514 {fido_a, fido_ctrl, "fidoa", 0},
515 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
520 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
524 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
526 static const struct m68k_cpu m68k_extensions[] =
528 {m68851, NULL, "68851", -1},
529 {m68881, NULL, "68881", -1},
530 {m68881, NULL, "68882", -1},
532 {cfloat|m68881, NULL, "float", 0},
534 {mcfhwdiv, NULL, "div", 1},
535 {mcfusp, NULL, "usp", 1},
536 {mcfmac, NULL, "mac", 1},
537 {mcfemac, NULL, "emac", 1},
543 static const struct m68k_cpu m68k_cpus[] =
545 {m68000, m68000_ctrl, "68000", 0},
546 {m68000, m68000_ctrl, "68ec000", 1},
547 {m68000, m68000_ctrl, "68hc000", 1},
548 {m68000, m68000_ctrl, "68hc001", 1},
549 {m68000, m68000_ctrl, "68008", 1},
550 {m68000, m68000_ctrl, "68302", 1},
551 {m68000, m68000_ctrl, "68306", 1},
552 {m68000, m68000_ctrl, "68307", 1},
553 {m68000, m68000_ctrl, "68322", 1},
554 {m68000, m68000_ctrl, "68356", 1},
555 {m68010, m68010_ctrl, "68010", 0},
556 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
557 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
558 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
559 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
560 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
561 {m68040, m68040_ctrl, "68040", 0},
562 {m68040, m68040_ctrl, "68ec040", 1},
563 {m68060, m68060_ctrl, "68060", 0},
564 {m68060, m68060_ctrl, "68ec060", 1},
566 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
567 {cpu32|m68881, cpu32_ctrl, "68330", 1},
568 {cpu32|m68881, cpu32_ctrl, "68331", 1},
569 {cpu32|m68881, cpu32_ctrl, "68332", 1},
570 {cpu32|m68881, cpu32_ctrl, "68333", 1},
571 {cpu32|m68881, cpu32_ctrl, "68334", 1},
572 {cpu32|m68881, cpu32_ctrl, "68336", 1},
573 {cpu32|m68881, cpu32_ctrl, "68340", 1},
574 {cpu32|m68881, cpu32_ctrl, "68341", 1},
575 {cpu32|m68881, cpu32_ctrl, "68349", 1},
576 {cpu32|m68881, cpu32_ctrl, "68360", 1},
578 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
580 {mcfisa_a, mcf_ctrl, "5200", 0},
581 {mcfisa_a, mcf_ctrl, "5202", 1},
582 {mcfisa_a, mcf_ctrl, "5204", 1},
583 {mcfisa_a, mcf5206_ctrl, "5206", 1},
585 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
619 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
620 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
625 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
635 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
653 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
661 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
669 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
671 {fido_a, fido_ctrl, "fidoa", 0},
672 {fido_a, fido_ctrl, "fido", 1},
677 static const struct m68k_cpu *m68k_lookup_cpu
678 (const char *, const struct m68k_cpu *, int, int *);
679 static int m68k_set_arch (const char *, int, int);
680 static int m68k_set_cpu (const char *, int, int);
681 static int m68k_set_extension (const char *, int, int);
682 static void m68k_init_arch (void);
684 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
685 architecture and we have a lot of relaxation modes. */
687 /* Macros used in the relaxation code. */
688 #define TAB(x,y) (((x) << 2) + (y))
689 #define TABTYPE(x) ((x) >> 2)
691 /* Relaxation states. */
697 /* Here are all the relaxation modes we support. First we can relax ordinary
698 branches. On 68020 and higher and on CPU32 all branch instructions take
699 three forms, so on these CPUs all branches always remain as such. When we
700 have to expand to the LONG form on a 68000, though, we substitute an
701 absolute jump instead. This is a direct replacement for unconditional
702 branches and a branch over a jump for conditional branches. However, if the
703 user requires PIC and disables this with --pcrel, we can only relax between
704 BYTE and SHORT forms, punting if that isn't enough. This gives us four
705 different relaxation modes for branches: */
707 #define BRANCHBWL 0 /* Branch byte, word, or long. */
708 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
709 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
710 #define BRANCHBW 3 /* Branch byte or word. */
712 /* We also relax coprocessor branches and DBcc's. All CPUs that support
713 coprocessor branches support them in word and long forms, so we have only
714 one relaxation mode for them. DBcc's are word only on all CPUs. We can
715 relax them to the LONG form with a branch-around sequence. This sequence
716 can use a long branch (if available) or an absolute jump (if acceptable).
717 This gives us two relaxation modes. If long branches are not available and
718 absolute jumps are not acceptable, we don't relax DBcc's. */
720 #define FBRANCH 4 /* Coprocessor branch. */
721 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
722 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
724 /* That's all for instruction relaxation. However, we also relax PC-relative
725 operands. Specifically, we have three operand relaxation modes. On the
726 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
727 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
728 two. Also PC+displacement+index operands in their simple form (with a non-
729 suppressed index without memory indirection) are supported on all CPUs, but
730 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
731 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
732 form of the PC+displacement+index operand. Finally, some absolute operands
733 can be relaxed down to 16-bit PC-relative. */
735 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
736 #define PCINDEX 8 /* PC + displacement + index. */
737 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
739 /* This relaxation is required for branches where there is no long
740 branch and we are in pcrel mode. We generate a bne/beq pair. */
741 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
744 /* Note that calls to frag_var need to specify the maximum expansion
745 needed; this is currently 12 bytes for bne/beq pair. */
746 #define FRAG_VAR_SIZE 12
749 How far Forward this mode will reach:
750 How far Backward this mode will reach:
751 How many bytes this mode will add to the size of the frag
752 Which mode to go to if the offset won't fit in this one
754 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
755 relax_typeS md_relax_table[] =
757 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
758 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
762 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
763 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
767 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
768 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
772 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
777 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
778 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
782 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
783 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
787 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
788 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
792 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
793 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
797 { 125, -130, 0, TAB (PCINDEX, SHORT) },
798 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
802 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
803 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
807 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
808 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
813 /* These are the machine dependent pseudo-ops. These are included so
814 the assembler can work on the output from the SUN C compiler, which
817 /* This table describes all the machine specific pseudo-ops the assembler
818 has to support. The fields are:
819 pseudo-op name without dot
820 function to call to execute this pseudo-op
821 Integer arg to pass to the function. */
822 const pseudo_typeS md_pseudo_table[] =
824 {"data1", s_data1, 0},
825 {"data2", s_data2, 0},
828 {"skip", s_space, 0},
830 #if defined (TE_SUN3) || defined (OBJ_ELF)
831 {"align", s_align_bytes, 0},
834 {"swbeg", s_ignore, 0},
836 {"extend", float_cons, 'x'},
837 {"ldouble", float_cons, 'x'},
839 {"arch", s_m68k_arch, 0},
840 {"cpu", s_m68k_cpu, 0},
842 /* The following pseudo-ops are supported for MRI compatibility. */
844 {"comline", s_space, 1},
846 {"mask2", s_ignore, 0},
849 {"restore", s_restore, 0},
853 {"if.b", s_mri_if, 'b'},
854 {"if.w", s_mri_if, 'w'},
855 {"if.l", s_mri_if, 'l'},
856 {"else", s_mri_else, 0},
857 {"else.s", s_mri_else, 's'},
858 {"else.l", s_mri_else, 'l'},
859 {"endi", s_mri_endi, 0},
860 {"break", s_mri_break, 0},
861 {"break.s", s_mri_break, 's'},
862 {"break.l", s_mri_break, 'l'},
863 {"next", s_mri_next, 0},
864 {"next.s", s_mri_next, 's'},
865 {"next.l", s_mri_next, 'l'},
866 {"for", s_mri_for, 0},
867 {"for.b", s_mri_for, 'b'},
868 {"for.w", s_mri_for, 'w'},
869 {"for.l", s_mri_for, 'l'},
870 {"endf", s_mri_endf, 0},
871 {"repeat", s_mri_repeat, 0},
872 {"until", s_mri_until, 0},
873 {"until.b", s_mri_until, 'b'},
874 {"until.w", s_mri_until, 'w'},
875 {"until.l", s_mri_until, 'l'},
876 {"while", s_mri_while, 0},
877 {"while.b", s_mri_while, 'b'},
878 {"while.w", s_mri_while, 'w'},
879 {"while.l", s_mri_while, 'l'},
880 {"endw", s_mri_endw, 0},
885 /* The mote pseudo ops are put into the opcode table, since they
886 don't start with a . they look like opcodes to gas. */
888 const pseudo_typeS mote_pseudo_table[] =
901 {"xdef", s_globl, 0},
903 {"align", s_align_bytes, 0},
905 {"align", s_align_ptwo, 0},
908 {"sect", obj_coff_section, 0},
909 {"section", obj_coff_section, 0},
914 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
915 gives identical results to a 32-bit host. */
916 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
917 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
919 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
920 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
921 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
922 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
924 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
925 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
926 #define islong(x) (1)
928 static char notend_table[256];
929 static char alt_notend_table[256];
931 (! (notend_table[(unsigned char) *s] \
933 && alt_notend_table[(unsigned char) s[1]])))
937 /* Return zero if the reference to SYMBOL from within the same segment may
940 /* On an ELF system, we can't relax an externally visible symbol,
941 because it may be overridden by a shared library. However, if
942 TARGET_OS is "elf", then we presume that we are assembling for an
943 embedded system, in which case we don't have to worry about shared
944 libraries, and we can relax any external sym. */
946 #define relaxable_symbol(symbol) \
947 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
948 || S_IS_WEAK (symbol)))
950 /* Compute the relocation code for a fixup of SIZE bytes, using pc
951 relative relocation if PCREL is non-zero. PIC says whether a special
952 pic relocation was requested. */
954 static bfd_reloc_code_real_type
955 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
963 return BFD_RELOC_8_GOT_PCREL;
965 return BFD_RELOC_16_GOT_PCREL;
967 return BFD_RELOC_32_GOT_PCREL;
975 return BFD_RELOC_8_GOTOFF;
977 return BFD_RELOC_16_GOTOFF;
979 return BFD_RELOC_32_GOTOFF;
987 return BFD_RELOC_8_PLT_PCREL;
989 return BFD_RELOC_16_PLT_PCREL;
991 return BFD_RELOC_32_PLT_PCREL;
999 return BFD_RELOC_8_PLTOFF;
1001 return BFD_RELOC_16_PLTOFF;
1003 return BFD_RELOC_32_PLTOFF;
1013 return BFD_RELOC_8_PCREL;
1015 return BFD_RELOC_16_PCREL;
1017 return BFD_RELOC_32_PCREL;
1027 return BFD_RELOC_16;
1029 return BFD_RELOC_32;
1036 if (pic == pic_none)
1037 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1039 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1043 if (pic == pic_none)
1044 as_bad (_("Can not do %d byte relocation"), size);
1046 as_bad (_("Can not do %d byte pic relocation"), size);
1049 return BFD_RELOC_NONE;
1052 /* Here we decide which fixups can be adjusted to make them relative
1053 to the beginning of the section instead of the symbol. Basically
1054 we need to make sure that the dynamic relocations are done
1055 correctly, so in some cases we force the original symbol to be
1058 tc_m68k_fix_adjustable (fixS *fixP)
1060 /* Adjust_reloc_syms doesn't know about the GOT. */
1061 switch (fixP->fx_r_type)
1063 case BFD_RELOC_8_GOT_PCREL:
1064 case BFD_RELOC_16_GOT_PCREL:
1065 case BFD_RELOC_32_GOT_PCREL:
1066 case BFD_RELOC_8_GOTOFF:
1067 case BFD_RELOC_16_GOTOFF:
1068 case BFD_RELOC_32_GOTOFF:
1069 case BFD_RELOC_8_PLT_PCREL:
1070 case BFD_RELOC_16_PLT_PCREL:
1071 case BFD_RELOC_32_PLT_PCREL:
1072 case BFD_RELOC_8_PLTOFF:
1073 case BFD_RELOC_16_PLTOFF:
1074 case BFD_RELOC_32_PLTOFF:
1077 case BFD_RELOC_VTABLE_INHERIT:
1078 case BFD_RELOC_VTABLE_ENTRY:
1086 #else /* !OBJ_ELF */
1088 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1090 /* PR gas/3041 Weak symbols are not relaxable
1091 because they must be treated as extern. */
1092 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1094 #endif /* OBJ_ELF */
1097 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1100 bfd_reloc_code_real_type code;
1102 /* If the tcbit is set, then this was a fixup of a negative value
1103 that was never resolved. We do not have a reloc to handle this,
1104 so just return. We assume that other code will have detected this
1105 situation and produced a helpful error message, so we just tell the
1106 user that the reloc cannot be produced. */
1110 as_bad_where (fixp->fx_file, fixp->fx_line,
1111 _("Unable to produce reloc against symbol '%s'"),
1112 S_GET_NAME (fixp->fx_addsy));
1116 if (fixp->fx_r_type != BFD_RELOC_NONE)
1118 code = fixp->fx_r_type;
1120 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1121 that fixup_segment converted a non-PC relative reloc into a
1122 PC relative reloc. In such a case, we need to convert the
1129 code = BFD_RELOC_8_PCREL;
1132 code = BFD_RELOC_16_PCREL;
1135 code = BFD_RELOC_32_PCREL;
1137 case BFD_RELOC_8_PCREL:
1138 case BFD_RELOC_16_PCREL:
1139 case BFD_RELOC_32_PCREL:
1140 case BFD_RELOC_8_GOT_PCREL:
1141 case BFD_RELOC_16_GOT_PCREL:
1142 case BFD_RELOC_32_GOT_PCREL:
1143 case BFD_RELOC_8_GOTOFF:
1144 case BFD_RELOC_16_GOTOFF:
1145 case BFD_RELOC_32_GOTOFF:
1146 case BFD_RELOC_8_PLT_PCREL:
1147 case BFD_RELOC_16_PLT_PCREL:
1148 case BFD_RELOC_32_PLT_PCREL:
1149 case BFD_RELOC_8_PLTOFF:
1150 case BFD_RELOC_16_PLTOFF:
1151 case BFD_RELOC_32_PLTOFF:
1154 as_bad_where (fixp->fx_file, fixp->fx_line,
1155 _("Cannot make %s relocation PC relative"),
1156 bfd_get_reloc_code_name (code));
1162 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1163 switch (F (fixp->fx_size, fixp->fx_pcrel))
1165 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1166 MAP (1, 0, BFD_RELOC_8);
1167 MAP (2, 0, BFD_RELOC_16);
1168 MAP (4, 0, BFD_RELOC_32);
1169 MAP (1, 1, BFD_RELOC_8_PCREL);
1170 MAP (2, 1, BFD_RELOC_16_PCREL);
1171 MAP (4, 1, BFD_RELOC_32_PCREL);
1179 reloc = (arelent *) xmalloc (sizeof (arelent));
1180 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1181 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1182 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1185 reloc->addend = fixp->fx_addnumber;
1186 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1188 && S_IS_WEAK (fixp->fx_addsy)
1189 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1190 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1191 to put the symbol offset into frags referencing a weak symbol. */
1192 reloc->addend = fixp->fx_addnumber
1193 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1197 if (!fixp->fx_pcrel)
1198 reloc->addend = fixp->fx_addnumber;
1200 reloc->addend = (section->vma
1201 /* Explicit sign extension in case char is
1203 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1204 + fixp->fx_addnumber
1205 + md_pcrel_from (fixp));
1208 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1209 assert (reloc->howto != 0);
1214 /* Handle of the OPCODE hash table. NULL means any use before
1215 m68k_ip_begin() will crash. */
1216 static struct hash_control *op_hash;
1218 /* Assemble an m68k instruction. */
1221 m68k_ip (char *instring)
1224 register struct m68k_op *opP;
1225 register const struct m68k_incant *opcode;
1226 register const char *s;
1227 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1228 char *pdot, *pdotmove;
1229 enum m68k_size siz1, siz2;
1233 struct m68k_op operands_backup[6];
1234 LITTLENUM_TYPE words[6];
1235 LITTLENUM_TYPE *wordp;
1236 unsigned long ok_arch = 0;
1238 if (*instring == ' ')
1239 instring++; /* Skip leading whitespace. */
1241 /* Scan up to end of operation-code, which MUST end in end-of-string
1242 or exactly 1 space. */
1244 for (p = instring; *p != '\0'; p++)
1254 the_ins.error = _("No operator");
1258 /* p now points to the end of the opcode name, probably whitespace.
1259 Make sure the name is null terminated by clobbering the
1260 whitespace, look it up in the hash table, then fix it back.
1261 Remove a dot, first, since the opcode tables have none. */
1264 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1265 *pdotmove = pdotmove[1];
1271 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1276 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1277 *pdotmove = pdotmove[-1];
1284 the_ins.error = _("Unknown operator");
1288 /* Found a legitimate opcode, start matching operands. */
1292 if (opcode->m_operands == 0)
1294 char *old = input_line_pointer;
1296 input_line_pointer = p;
1297 /* Ahh - it's a motorola style psuedo op. */
1298 mote_pseudo_table[opcode->m_opnum].poc_handler
1299 (mote_pseudo_table[opcode->m_opnum].poc_val);
1300 input_line_pointer = old;
1306 if (flag_mri && opcode->m_opnum == 0)
1308 /* In MRI mode, random garbage is allowed after an instruction
1309 which accepts no operands. */
1310 the_ins.args = opcode->m_operands;
1311 the_ins.numargs = opcode->m_opnum;
1312 the_ins.numo = opcode->m_codenum;
1313 the_ins.opcode[0] = getone (opcode);
1314 the_ins.opcode[1] = gettwo (opcode);
1318 for (opP = &the_ins.operands[0]; *p; opP++)
1320 p = crack_operand (p, opP);
1324 the_ins.error = opP->error;
1329 opsfound = opP - &the_ins.operands[0];
1331 /* This ugly hack is to support the floating pt opcodes in their
1332 standard form. Essentially, we fake a first enty of type COP#1 */
1333 if (opcode->m_operands[0] == 'I')
1337 for (n = opsfound; n > 0; --n)
1338 the_ins.operands[n] = the_ins.operands[n - 1];
1340 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1341 the_ins.operands[0].mode = CONTROL;
1342 the_ins.operands[0].reg = m68k_float_copnum;
1346 /* We've got the operands. Find an opcode that'll accept them. */
1349 /* If we didn't get the right number of ops, or we have no
1350 common model with this pattern then reject this pattern. */
1352 ok_arch |= opcode->m_arch;
1353 if (opsfound != opcode->m_opnum
1354 || ((opcode->m_arch & current_architecture) == 0))
1360 /* Make a copy of the operands of this insn so that
1361 we can modify them safely, should we want to. */
1362 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1363 for (i = 0; i < opsfound; i++)
1364 operands_backup[i] = the_ins.operands[i];
1366 for (s = opcode->m_operands, opP = &operands_backup[0];
1370 /* Warning: this switch is huge! */
1371 /* I've tried to organize the cases into this order:
1372 non-alpha first, then alpha by letter. Lower-case
1373 goes directly before uppercase counterpart. */
1374 /* Code with multiple case ...: gets sorted by the lowest
1375 case ... it belongs to. I hope this makes sense. */
1481 if (opP->reg == PC || opP->reg == ZPC)
1498 if (opP->reg == PC || opP->reg == ZPC)
1517 if (opP->reg == PC || opP->reg == ZPC)
1527 if (opP->mode != IMMED)
1529 else if (s[1] == 'b'
1530 && ! isvar (&opP->disp)
1531 && (opP->disp.exp.X_op != O_constant
1532 || ! isbyte (opP->disp.exp.X_add_number)))
1534 else if (s[1] == 'B'
1535 && ! isvar (&opP->disp)
1536 && (opP->disp.exp.X_op != O_constant
1537 || ! issbyte (opP->disp.exp.X_add_number)))
1539 else if (s[1] == 'w'
1540 && ! isvar (&opP->disp)
1541 && (opP->disp.exp.X_op != O_constant
1542 || ! isword (opP->disp.exp.X_add_number)))
1544 else if (s[1] == 'W'
1545 && ! isvar (&opP->disp)
1546 && (opP->disp.exp.X_op != O_constant
1547 || ! issword (opP->disp.exp.X_add_number)))
1553 if (opP->mode != IMMED)
1558 if (opP->mode == AREG
1559 || opP->mode == CONTROL
1560 || opP->mode == FPREG
1561 || opP->mode == IMMED
1562 || opP->mode == REGLST
1563 || (opP->mode != ABSL
1565 || opP->reg == ZPC)))
1570 if (opP->mode == CONTROL
1571 || opP->mode == FPREG
1572 || opP->mode == REGLST
1573 || opP->mode == IMMED
1574 || (opP->mode != ABSL
1576 || opP->reg == ZPC)))
1604 if (opP->mode == CONTROL
1605 || opP->mode == FPREG
1606 || opP->mode == REGLST)
1611 if (opP->mode != AINC)
1616 if (opP->mode != ADEC)
1666 if (opP->reg == PC || opP->reg == ZPC)
1687 case '~': /* For now! (JF FOO is this right?) */
1709 if (opP->mode != CONTROL
1710 || (opP->reg != TT0 && opP->reg != TT1))
1715 if (opP->mode != AREG)
1720 if (opP->mode != AINDR)
1725 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1726 && (opP->mode != DISP
1728 || opP->reg > ADDR7))
1733 if (opP->mode != ABSL
1735 && strncmp (instring, "jbsr", 4) == 0))
1758 if (opP->mode != CONTROL || opP->reg != CCR)
1763 if (opP->mode != DISP
1765 || opP->reg > ADDR7)
1770 if (opP->mode != DREG)
1775 if (opP->reg != ACC)
1780 if (opP->reg != ACC && opP->reg != ACC1
1781 && opP->reg != ACC2 && opP->reg != ACC3)
1786 if (opP->mode != FPREG)
1791 if (opP->reg != MACSR)
1796 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1801 if (opP->reg != MASK)
1806 if (opP->mode != CONTROL
1813 if (opP->mode != LSH && opP->mode != RSH)
1818 if (opP->mode != CONTROL
1820 || opP->reg > last_movec_reg
1825 const enum m68k_register *rp;
1827 for (rp = control_regs; *rp; rp++)
1829 if (*rp == opP->reg)
1831 /* In most CPUs RAMBAR refers to control reg
1832 c05 (RAMBAR1), but a few CPUs have it
1833 refer to c04 (RAMBAR0). */
1834 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1836 opP->reg = RAMBAR_ALT;
1846 if (opP->mode != IMMED)
1852 if (opP->mode == DREG
1853 || opP->mode == AREG
1854 || opP->mode == FPREG)
1863 opP->mask = 1 << (opP->reg - DATA0);
1866 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1869 opP->mask = 1 << (opP->reg - FP0 + 16);
1877 else if (opP->mode == CONTROL)
1886 opP->mask = 1 << 24;
1889 opP->mask = 1 << 25;
1892 opP->mask = 1 << 26;
1901 else if (opP->mode != REGLST)
1903 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1905 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1910 if (opP->mode != IMMED)
1912 else if (opP->disp.exp.X_op != O_constant
1913 || ! issbyte (opP->disp.exp.X_add_number))
1915 else if (! m68k_quick
1916 && instring[3] != 'q'
1917 && instring[4] != 'q')
1922 if (opP->mode != DREG
1923 && opP->mode != IMMED
1924 && opP->mode != ABSL)
1929 if (opP->mode != IMMED)
1931 else if (opP->disp.exp.X_op != O_constant
1932 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1934 else if (! m68k_quick
1935 && (strncmp (instring, "add", 3) == 0
1936 || strncmp (instring, "sub", 3) == 0)
1937 && instring[3] != 'q')
1942 if (opP->mode != DREG && opP->mode != AREG)
1947 if (opP->mode != AINDR
1948 && (opP->mode != BASE
1950 && opP->reg != ZADDR0)
1951 || opP->disp.exp.X_op != O_absent
1952 || ((opP->index.reg < DATA0
1953 || opP->index.reg > DATA7)
1954 && (opP->index.reg < ADDR0
1955 || opP->index.reg > ADDR7))
1956 || opP->index.size != SIZE_UNSPEC
1957 || opP->index.scale != 1))
1962 if (opP->mode != CONTROL
1963 || ! (opP->reg == FPI
1965 || opP->reg == FPC))
1970 if (opP->mode != CONTROL || opP->reg != SR)
1975 if (opP->mode != IMMED)
1977 else if (opP->disp.exp.X_op != O_constant
1978 || TRUNC (opP->disp.exp.X_add_number) > 7)
1983 if (opP->mode != CONTROL || opP->reg != USP)
1988 if (opP->mode != IMMED)
1990 else if (opP->disp.exp.X_op != O_constant
1991 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1992 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1997 if (opP->mode != IMMED)
1999 else if (opP->disp.exp.X_op != O_constant
2000 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2005 if (opP->mode != IMMED)
2007 else if (opP->disp.exp.X_op != O_constant
2008 || TRUNC (opP->disp.exp.X_add_number) > 511)
2012 /* JF these are out of order. We could put them
2013 in order if we were willing to put up with
2014 bunches of #ifdef m68851s in the code.
2016 Don't forget that you need these operands
2017 to use 68030 MMU instructions. */
2019 /* Memory addressing mode used by pflushr. */
2021 if (opP->mode == CONTROL
2022 || opP->mode == FPREG
2023 || opP->mode == DREG
2024 || opP->mode == AREG
2025 || opP->mode == REGLST)
2027 /* We should accept immediate operands, but they
2028 supposedly have to be quad word, and we don't
2029 handle that. I would like to see what a Motorola
2030 assembler does before doing something here. */
2031 if (opP->mode == IMMED)
2036 if (opP->mode != CONTROL
2037 || (opP->reg != SFC && opP->reg != DFC))
2042 if (opP->mode != CONTROL || opP->reg != TC)
2047 if (opP->mode != CONTROL || opP->reg != AC)
2052 if (opP->mode != CONTROL
2055 && opP->reg != SCC))
2060 if (opP->mode != CONTROL
2066 if (opP->mode != CONTROL
2069 && opP->reg != CRP))
2093 if (opP->mode != CONTROL
2094 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2095 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2100 if (opP->mode != CONTROL || opP->reg != PSR)
2105 if (opP->mode != CONTROL || opP->reg != PCSR)
2110 if (opP->mode != CONTROL
2119 if (opP->mode != ABSL)
2124 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2126 /* FIXME: kludge instead of fixing parser:
2127 upper/lower registers are *not* CONTROL
2128 registers, but ordinary ones. */
2129 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2130 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2137 if (!(opP->mode == AINDR
2138 || (opP->mode == DISP
2139 && !(opP->reg == PC || opP->reg == ZPC))))
2144 if (!(opP->mode == AINDR || opP->mode == DISP))
2156 /* Since we have found the correct instruction, copy
2157 in the modifications that we may have made. */
2159 for (i = 0; i < opsfound; i++)
2160 the_ins.operands[i] = operands_backup[i];
2166 opcode = opcode->m_next;
2171 && !(ok_arch & current_architecture))
2173 const struct m68k_cpu *cpu;
2176 char *buf = xmalloc (space + 1);
2180 the_ins.error = buf;
2181 /* Make sure there's a NUL at the end of the buffer -- strncpy
2182 won't write one when it runs out of buffer. */
2184 #define APPEND(STRING) \
2185 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2187 APPEND (_("invalid instruction for this architecture; needs "));
2191 APPEND ("ColdFire ISA_A");
2194 APPEND ("ColdFire ");
2195 APPEND (_("hardware divide"));
2198 APPEND ("ColdFire ISA_A+");
2201 APPEND ("ColdFire ISA_B");
2204 APPEND ("ColdFire ISA_C");
2207 APPEND ("ColdFire fpu");
2210 APPEND ("M68K fpu");
2213 APPEND ("M68K mmu");
2217 APPEND (_("or higher"));
2221 APPEND (_("or higher"));
2225 APPEND (_("or higher"));
2233 for (cpu = m68k_cpus; cpu->name; cpu++)
2234 if (!cpu->alias && (cpu->arch & ok_arch))
2236 const struct m68k_cpu *alias;
2237 int seen_master = 0;
2243 for (alias = cpu; alias != m68k_cpus; alias--)
2244 if (alias[-1].alias >= 0)
2246 for (; !seen_master || alias->alias > 0; alias++)
2256 APPEND (alias->name);
2269 /* We ran out of space, so replace the end of the list
2274 strcpy (buf, " ...");
2278 the_ins.error = _("operands mismatch");
2285 /* Now assemble it. */
2286 the_ins.args = opcode->m_operands;
2287 the_ins.numargs = opcode->m_opnum;
2288 the_ins.numo = opcode->m_codenum;
2289 the_ins.opcode[0] = getone (opcode);
2290 the_ins.opcode[1] = gettwo (opcode);
2292 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2297 /* This switch is a doozy.
2298 Watch the first step; its a big one! */
2331 tmpreg = 0x3c; /* 7.4 */
2332 if (strchr ("bwl", s[1]))
2333 nextword = get_num (&opP->disp, 90);
2335 nextword = get_num (&opP->disp, 0);
2336 if (isvar (&opP->disp))
2337 add_fix (s[1], &opP->disp, 0, 0);
2341 if (!isbyte (nextword))
2342 opP->error = _("operand out of range");
2347 if (!isword (nextword))
2348 opP->error = _("operand out of range");
2353 if (!issword (nextword))
2354 opP->error = _("operand out of range");
2359 addword (nextword >> 16);
2386 /* We gotta put out some float. */
2387 if (op (&opP->disp) != O_big)
2392 /* Can other cases happen here? */
2393 if (op (&opP->disp) != O_constant)
2396 val = (valueT) offs (&opP->disp);
2400 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2401 val >>= LITTLENUM_NUMBER_OF_BITS;
2405 offs (&opP->disp) = gencnt;
2407 if (offs (&opP->disp) > 0)
2409 if (offs (&opP->disp) > baseo)
2411 as_warn (_("Bignum too big for %c format; truncated"),
2413 offs (&opP->disp) = baseo;
2415 baseo -= offs (&opP->disp);
2418 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2419 offs (&opP->disp)--;
2424 gen_to_words (words, baseo, (long) outro);
2425 for (wordp = words; baseo--; wordp++)
2429 tmpreg = opP->reg - DATA; /* 0.dreg */
2432 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2435 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2438 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2441 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2445 nextword = get_num (&opP->disp, 90);
2447 /* Convert mode 5 addressing with a zero offset into
2448 mode 2 addressing to reduce the instruction size by a
2450 if (! isvar (&opP->disp)
2452 && (opP->disp.size == SIZE_UNSPEC)
2453 && (opP->reg >= ADDR0)
2454 && (opP->reg <= ADDR7))
2456 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2461 && ! isvar (&opP->disp)
2464 opP->disp.exp.X_op = O_symbol;
2465 opP->disp.exp.X_add_symbol =
2466 section_symbol (absolute_section);
2469 /* Force into index mode. Hope this works. */
2471 /* We do the first bit for 32-bit displacements, and the
2472 second bit for 16 bit ones. It is possible that we
2473 should make the default be WORD instead of LONG, but
2474 I think that'd break GCC, so we put up with a little
2475 inefficiency for the sake of working output. */
2477 if (!issword (nextword)
2478 || (isvar (&opP->disp)
2479 && ((opP->disp.size == SIZE_UNSPEC
2480 && flag_short_refs == 0
2481 && cpu_of_arch (current_architecture) >= m68020
2482 && ! arch_coldfire_p (current_architecture))
2483 || opP->disp.size == SIZE_LONG)))
2485 if (cpu_of_arch (current_architecture) < m68020
2486 || arch_coldfire_p (current_architecture))
2488 _("displacement too large for this architecture; needs 68020 or higher");
2490 tmpreg = 0x3B; /* 7.3 */
2492 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2493 if (isvar (&opP->disp))
2497 if (opP->disp.size == SIZE_LONG
2499 /* If the displacement needs pic
2500 relocation it cannot be relaxed. */
2501 || opP->disp.pic_reloc != pic_none
2506 add_fix ('l', &opP->disp, 1, 2);
2510 add_frag (adds (&opP->disp),
2511 SEXT (offs (&opP->disp)),
2512 TAB (PCREL1632, SZ_UNDEF));
2519 add_fix ('l', &opP->disp, 0, 0);
2524 addword (nextword >> 16);
2529 tmpreg = 0x3A; /* 7.2 */
2531 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2533 if (isvar (&opP->disp))
2537 add_fix ('w', &opP->disp, 1, 0);
2540 add_fix ('w', &opP->disp, 0, 0);
2550 baseo = get_num (&opP->disp, 90);
2551 if (opP->mode == POST || opP->mode == PRE)
2552 outro = get_num (&opP->odisp, 90);
2553 /* Figure out the `addressing mode'.
2554 Also turn on the BASE_DISABLE bit, if needed. */
2555 if (opP->reg == PC || opP->reg == ZPC)
2557 tmpreg = 0x3b; /* 7.3 */
2558 if (opP->reg == ZPC)
2561 else if (opP->reg == 0)
2564 tmpreg = 0x30; /* 6.garbage */
2566 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2569 tmpreg = 0x30 + opP->reg - ZADDR0;
2572 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2574 siz1 = opP->disp.size;
2575 if (opP->mode == POST || opP->mode == PRE)
2576 siz2 = opP->odisp.size;
2580 /* Index register stuff. */
2581 if (opP->index.reg != 0
2582 && opP->index.reg >= DATA
2583 && opP->index.reg <= ADDR7)
2585 nextword |= (opP->index.reg - DATA) << 12;
2587 if (opP->index.size == SIZE_LONG
2588 || (opP->index.size == SIZE_UNSPEC
2589 && m68k_index_width_default == SIZE_LONG))
2592 if ((opP->index.scale != 1
2593 && cpu_of_arch (current_architecture) < m68020)
2594 || (opP->index.scale == 8
2595 && (arch_coldfire_p (current_architecture)
2596 && !arch_coldfire_fpu (current_architecture))))
2599 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2602 if (arch_coldfire_p (current_architecture)
2603 && opP->index.size == SIZE_WORD)
2604 opP->error = _("invalid index size for coldfire");
2606 switch (opP->index.scale)
2623 GET US OUT OF HERE! */
2625 /* Must be INDEX, with an index register. Address
2626 register cannot be ZERO-PC, and either :b was
2627 forced, or we know it will fit. For a 68000 or
2628 68010, force this mode anyways, because the
2629 larger modes aren't supported. */
2630 if (opP->mode == BASE
2631 && ((opP->reg >= ADDR0
2632 && opP->reg <= ADDR7)
2635 if (siz1 == SIZE_BYTE
2636 || cpu_of_arch (current_architecture) < m68020
2637 || arch_coldfire_p (current_architecture)
2638 || (siz1 == SIZE_UNSPEC
2639 && ! isvar (&opP->disp)
2640 && issbyte (baseo)))
2642 nextword += baseo & 0xff;
2644 if (isvar (&opP->disp))
2646 /* Do a byte relocation. If it doesn't
2647 fit (possible on m68000) let the
2648 fixup processing complain later. */
2650 add_fix ('B', &opP->disp, 1, 1);
2652 add_fix ('B', &opP->disp, 0, 0);
2654 else if (siz1 != SIZE_BYTE)
2656 if (siz1 != SIZE_UNSPEC)
2657 as_warn (_("Forcing byte displacement"));
2658 if (! issbyte (baseo))
2659 opP->error = _("byte displacement out of range");
2664 else if (siz1 == SIZE_UNSPEC
2666 && isvar (&opP->disp)
2667 && subs (&opP->disp) == NULL
2669 /* If the displacement needs pic
2670 relocation it cannot be relaxed. */
2671 && opP->disp.pic_reloc == pic_none
2675 /* The code in md_convert_frag_1 needs to be
2676 able to adjust nextword. Call frag_grow
2677 to ensure that we have enough space in
2678 the frag obstack to make all the bytes
2681 nextword += baseo & 0xff;
2683 add_frag (adds (&opP->disp),
2684 SEXT (offs (&opP->disp)),
2685 TAB (PCINDEX, SZ_UNDEF));
2693 nextword |= 0x40; /* No index reg. */
2694 if (opP->index.reg >= ZDATA0
2695 && opP->index.reg <= ZDATA7)
2696 nextword |= (opP->index.reg - ZDATA0) << 12;
2697 else if (opP->index.reg >= ZADDR0
2698 || opP->index.reg <= ZADDR7)
2699 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2702 /* It isn't simple. */
2704 if (cpu_of_arch (current_architecture) < m68020
2705 || arch_coldfire_p (current_architecture))
2707 _("invalid operand mode for this architecture; needs 68020 or higher");
2710 /* If the guy specified a width, we assume that it is
2711 wide enough. Maybe it isn't. If so, we lose. */
2715 if (isvar (&opP->disp)
2717 : ! issword (baseo))
2722 else if (! isvar (&opP->disp) && baseo == 0)
2731 as_warn (_(":b not permitted; defaulting to :w"));
2741 /* Figure out inner displacement stuff. */
2742 if (opP->mode == POST || opP->mode == PRE)
2744 if (cpu_of_arch (current_architecture) & cpu32)
2745 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2749 if (isvar (&opP->odisp)
2751 : ! issword (outro))
2756 else if (! isvar (&opP->odisp) && outro == 0)
2765 as_warn (_(":b not permitted; defaulting to :w"));
2774 if (opP->mode == POST
2775 && (nextword & 0x40) == 0)
2780 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2782 if (opP->reg == PC || opP->reg == ZPC)
2783 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2785 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2787 if (siz1 == SIZE_LONG)
2788 addword (baseo >> 16);
2789 if (siz1 != SIZE_UNSPEC)
2792 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2793 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2794 if (siz2 == SIZE_LONG)
2795 addword (outro >> 16);
2796 if (siz2 != SIZE_UNSPEC)
2802 nextword = get_num (&opP->disp, 90);
2803 switch (opP->disp.size)
2808 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2810 tmpreg = 0x38; /* 7.0 */
2814 if (isvar (&opP->disp)
2815 && !subs (&opP->disp)
2816 && adds (&opP->disp)
2818 /* If the displacement needs pic relocation it
2819 cannot be relaxed. */
2820 && opP->disp.pic_reloc == pic_none
2823 && !strchr ("~%&$?", s[0]))
2825 tmpreg = 0x3A; /* 7.2 */
2826 add_frag (adds (&opP->disp),
2827 SEXT (offs (&opP->disp)),
2828 TAB (ABSTOPCREL, SZ_UNDEF));
2831 /* Fall through into long. */
2833 if (isvar (&opP->disp))
2834 add_fix ('l', &opP->disp, 0, 0);
2836 tmpreg = 0x39;/* 7.1 mode */
2837 addword (nextword >> 16);
2842 as_bad (_("unsupported byte value; use a different suffix"));
2846 if (isvar (&opP->disp))
2847 add_fix ('w', &opP->disp, 0, 0);
2849 tmpreg = 0x38;/* 7.0 mode */
2857 as_bad (_("unknown/incorrect operand"));
2861 /* If s[0] is '4', then this is for the mac instructions
2862 that can have a trailing_ampersand set. If so, set 0x100
2863 bit on tmpreg so install_gen_operand can check for it and
2864 set the appropriate bit (word2, bit 5). */
2867 if (opP->trailing_ampersand)
2870 install_gen_operand (s[1], tmpreg);
2876 { /* JF: I hate floating point! */
2891 tmpreg = get_num (&opP->disp, tmpreg);
2892 if (isvar (&opP->disp))
2893 add_fix (s[1], &opP->disp, 0, 0);
2896 case 'b': /* Danger: These do no check for
2897 certain types of overflow.
2899 if (!isbyte (tmpreg))
2900 opP->error = _("out of range");
2901 insop (tmpreg, opcode);
2902 if (isvar (&opP->disp))
2903 the_ins.reloc[the_ins.nrel - 1].n =
2904 (opcode->m_codenum) * 2 + 1;
2907 if (!issbyte (tmpreg))
2908 opP->error = _("out of range");
2909 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2910 if (isvar (&opP->disp))
2911 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2914 if (!isword (tmpreg))
2915 opP->error = _("out of range");
2916 insop (tmpreg, opcode);
2917 if (isvar (&opP->disp))
2918 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2921 if (!issword (tmpreg))
2922 opP->error = _("out of range");
2923 insop (tmpreg, opcode);
2924 if (isvar (&opP->disp))
2925 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2928 /* Because of the way insop works, we put these two out
2930 insop (tmpreg, opcode);
2931 insop (tmpreg >> 16, opcode);
2932 if (isvar (&opP->disp))
2933 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2940 install_operand (s[1], tmpreg);
2951 install_operand (s[1], opP->reg - ADDR);
2955 tmpreg = get_num (&opP->disp, 90);
2960 add_fix ('B', &opP->disp, 1, -1);
2963 add_fix ('w', &opP->disp, 1, 0);
2968 the_ins.opcode[0] |= 0xff;
2969 add_fix ('l', &opP->disp, 1, 0);
2973 case 'g': /* Conditional branch */
2974 have_disp = HAVE_LONG_CALL (current_architecture);
2977 case 'b': /* Unconditional branch */
2978 have_disp = HAVE_LONG_BRANCH (current_architecture);
2979 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2982 case 's': /* Unconditional subroutine */
2983 have_disp = HAVE_LONG_CALL (current_architecture);
2986 if (subs (&opP->disp) /* We can't relax it. */
2988 /* If the displacement needs pic relocation it cannot be
2990 || opP->disp.pic_reloc != pic_none
2995 as_warn (_("Can't use long branches on this architecture"));
2999 /* This could either be a symbol, or an absolute
3000 address. If it's an absolute address, turn it into
3001 an absolute jump right here and keep it out of the
3003 if (adds (&opP->disp) == 0)
3005 if (the_ins.opcode[0] == 0x6000) /* jbra */
3006 the_ins.opcode[0] = 0x4EF9;
3007 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3008 the_ins.opcode[0] = 0x4EB9;
3011 the_ins.opcode[0] ^= 0x0100;
3012 the_ins.opcode[0] |= 0x0006;
3015 add_fix ('l', &opP->disp, 0, 0);
3021 /* Now we know it's going into the relaxer. Now figure
3022 out which mode. We try in this order of preference:
3023 long branch, absolute jump, byte/word branches only. */
3025 add_frag (adds (&opP->disp),
3026 SEXT (offs (&opP->disp)),
3027 TAB (BRANCHBWL, SZ_UNDEF));
3028 else if (! flag_keep_pcrel)
3030 if ((the_ins.opcode[0] == 0x6000)
3031 || (the_ins.opcode[0] == 0x6100))
3032 add_frag (adds (&opP->disp),
3033 SEXT (offs (&opP->disp)),
3034 TAB (BRABSJUNC, SZ_UNDEF));
3036 add_frag (adds (&opP->disp),
3037 SEXT (offs (&opP->disp)),
3038 TAB (BRABSJCOND, SZ_UNDEF));
3041 add_frag (adds (&opP->disp),
3042 SEXT (offs (&opP->disp)),
3043 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3044 : TAB (BRANCHBW, SZ_UNDEF)));
3047 if (isvar (&opP->disp))
3049 /* Check for DBcc instructions. We can relax them,
3050 but only if we have long branches and/or absolute
3052 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3053 && (HAVE_LONG_BRANCH (current_architecture)
3054 || ! flag_keep_pcrel))
3056 if (HAVE_LONG_BRANCH (current_architecture))
3057 add_frag (adds (&opP->disp),
3058 SEXT (offs (&opP->disp)),
3059 TAB (DBCCLBR, SZ_UNDEF));
3061 add_frag (adds (&opP->disp),
3062 SEXT (offs (&opP->disp)),
3063 TAB (DBCCABSJ, SZ_UNDEF));
3066 add_fix ('w', &opP->disp, 1, 0);
3070 case 'C': /* Fixed size LONG coproc branches. */
3071 add_fix ('l', &opP->disp, 1, 0);
3075 case 'c': /* Var size Coprocesssor branches. */
3076 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3078 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3079 add_fix ('l', &opP->disp, 1, 0);
3084 add_frag (adds (&opP->disp),
3085 SEXT (offs (&opP->disp)),
3086 TAB (FBRANCH, SZ_UNDEF));
3093 case 'C': /* Ignore it. */
3096 case 'd': /* JF this is a kludge. */
3097 install_operand ('s', opP->reg - ADDR);
3098 tmpreg = get_num (&opP->disp, 90);
3099 if (!issword (tmpreg))
3101 as_warn (_("Expression out of range, using 0"));
3108 install_operand (s[1], opP->reg - DATA);
3111 case 'e': /* EMAC ACCx, reg/reg. */
3112 install_operand (s[1], opP->reg - ACC);
3115 case 'E': /* Ignore it. */
3119 install_operand (s[1], opP->reg - FP0);
3122 case 'g': /* EMAC ACCEXTx. */
3123 install_operand (s[1], opP->reg - ACCEXT01);
3126 case 'G': /* Ignore it. */
3131 tmpreg = opP->reg - COP0;
3132 install_operand (s[1], tmpreg);
3135 case 'i': /* MAC/EMAC scale factor. */
3136 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3139 case 'J': /* JF foo. */
3279 install_operand (s[1], tmpreg);
3283 tmpreg = get_num (&opP->disp, 55);
3284 install_operand (s[1], tmpreg & 0x7f);
3291 if (tmpreg & 0x7FF0000)
3292 as_bad (_("Floating point register in register list"));
3293 insop (reverse_16_bits (tmpreg), opcode);
3297 if (tmpreg & 0x700FFFF)
3298 as_bad (_("Wrong register in floating-point reglist"));
3299 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3307 if (tmpreg & 0x7FF0000)
3308 as_bad (_("Floating point register in register list"));
3309 insop (tmpreg, opcode);
3311 else if (s[1] == '8')
3313 if (tmpreg & 0x0FFFFFF)
3314 as_bad (_("incorrect register in reglist"));
3315 install_operand (s[1], tmpreg >> 24);
3319 if (tmpreg & 0x700FFFF)
3320 as_bad (_("wrong register in floating-point reglist"));
3322 install_operand (s[1], tmpreg >> 16);
3327 install_operand (s[1], get_num (&opP->disp, 60));
3331 tmpreg = ((opP->mode == DREG)
3332 ? 0x20 + (int) (opP->reg - DATA)
3333 : (get_num (&opP->disp, 40) & 0x1F));
3334 install_operand (s[1], tmpreg);
3338 tmpreg = get_num (&opP->disp, 10);
3341 install_operand (s[1], tmpreg);
3345 /* This depends on the fact that ADDR registers are eight
3346 more than their corresponding DATA regs, so the result
3347 will have the ADDR_REG bit set. */
3348 install_operand (s[1], opP->reg - DATA);
3352 if (opP->mode == AINDR)
3353 install_operand (s[1], opP->reg - DATA);
3355 install_operand (s[1], opP->index.reg - DATA);
3359 if (opP->reg == FPI)
3361 else if (opP->reg == FPS)
3363 else if (opP->reg == FPC)
3367 install_operand (s[1], tmpreg);
3370 case 'S': /* Ignore it. */
3374 install_operand (s[1], get_num (&opP->disp, 30));
3377 case 'U': /* Ignore it. */
3396 as_fatal (_("failed sanity check"));
3397 } /* switch on cache token. */
3398 install_operand (s[1], tmpreg);
3401 /* JF: These are out of order, I fear. */
3414 install_operand (s[1], tmpreg);
3440 install_operand (s[1], tmpreg);
3444 if (opP->reg == VAL)
3463 install_operand (s[1], tmpreg);
3477 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3488 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3494 install_operand (s[1], tmpreg);
3497 know (opP->reg == PSR);
3500 know (opP->reg == PCSR);
3515 install_operand (s[1], tmpreg);
3518 tmpreg = get_num (&opP->disp, 20);
3519 install_operand (s[1], tmpreg);
3521 case '_': /* used only for move16 absolute 32-bit address. */
3522 if (isvar (&opP->disp))
3523 add_fix ('l', &opP->disp, 0, 0);
3524 tmpreg = get_num (&opP->disp, 90);
3525 addword (tmpreg >> 16);
3526 addword (tmpreg & 0xFFFF);
3529 install_operand (s[1], opP->reg - DATA0L);
3530 opP->reg -= (DATA0L);
3531 opP->reg &= 0x0F; /* remove upper/lower bit. */
3534 tmpreg = get_num (&opP->disp, 80);
3537 install_operand (s[1], tmpreg);
3540 tmpreg = get_num (&opP->disp, 10);
3541 install_operand (s[1], tmpreg - 1);
3544 tmpreg = get_num (&opP->disp, 65);
3545 install_operand (s[1], tmpreg);
3552 /* By the time whe get here (FINALLY) the_ins contains the complete
3553 instruction, ready to be emitted. . . */
3557 reverse_16_bits (int in)
3562 static int mask[16] =
3564 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3565 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3567 for (n = 0; n < 16; n++)
3570 out |= mask[15 - n];
3573 } /* reverse_16_bits() */
3576 reverse_8_bits (int in)
3581 static int mask[8] =
3583 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3586 for (n = 0; n < 8; n++)
3592 } /* reverse_8_bits() */
3594 /* Cause an extra frag to be generated here, inserting up to
3595 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3596 generated; its primary type is rs_machine_dependent.
3598 The TYPE parameter is also used by md_convert_frag_1 and
3599 md_estimate_size_before_relax. The appropriate type of fixup will
3600 be emitted by md_convert_frag_1.
3602 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3604 install_operand (int mode, int val)
3609 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3612 the_ins.opcode[0] |= val << 9;
3615 the_ins.opcode[1] |= val << 9;
3618 the_ins.opcode[1] |= val << 12;
3621 the_ins.opcode[1] |= val << 6;
3624 the_ins.opcode[1] |= val;
3627 the_ins.opcode[2] |= val << 12;
3630 the_ins.opcode[2] |= val << 6;
3633 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3634 three words long! */
3636 the_ins.opcode[2] |= val;
3639 the_ins.opcode[1] |= val << 7;
3642 the_ins.opcode[1] |= val << 10;
3646 the_ins.opcode[1] |= val << 5;
3651 the_ins.opcode[1] |= (val << 10) | (val << 7);
3654 the_ins.opcode[1] |= (val << 12) | val;
3657 the_ins.opcode[0] |= val = 0xff;
3660 the_ins.opcode[0] |= val << 9;
3663 the_ins.opcode[1] |= val;
3666 the_ins.opcode[1] |= val;
3667 the_ins.numo++; /* What a hack. */
3670 the_ins.opcode[1] |= val << 4;
3678 the_ins.opcode[0] |= (val << 6);
3681 the_ins.opcode[1] = (val >> 16);
3682 the_ins.opcode[2] = val & 0xffff;
3685 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3686 the_ins.opcode[0] |= ((val & 0x7) << 9);
3687 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3689 case 'n': /* MAC/EMAC Rx on !load. */
3690 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3691 the_ins.opcode[0] |= ((val & 0x7) << 9);
3692 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3694 case 'o': /* MAC/EMAC Rx on load. */
3695 the_ins.opcode[1] |= val << 12;
3696 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3698 case 'M': /* MAC/EMAC Ry on !load. */
3699 the_ins.opcode[0] |= (val & 0xF);
3700 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3702 case 'N': /* MAC/EMAC Ry on load. */
3703 the_ins.opcode[1] |= (val & 0xF);
3704 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3707 the_ins.opcode[1] |= ((val != 1) << 10);
3710 the_ins.opcode[0] |= ((val & 0x3) << 9);
3713 the_ins.opcode[0] |= ((val & 0x3) << 0);
3715 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3716 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3717 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3719 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3720 the_ins.opcode[0] |= ((val & 0x1) << 7);
3721 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3724 the_ins.opcode[1] |= ((val & 0x3) << 9);
3727 the_ins.opcode[0] |= (val & 0x1) <<10;
3731 as_fatal (_("failed sanity check."));
3736 install_gen_operand (int mode, int val)
3740 case '/': /* Special for mask loads for mac/msac insns with
3741 possible mask; trailing_ampersend set in bit 8. */
3742 the_ins.opcode[0] |= (val & 0x3f);
3743 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3746 the_ins.opcode[0] |= val;
3749 /* This is a kludge!!! */
3750 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3759 the_ins.opcode[0] |= val;
3761 /* more stuff goes here. */
3763 as_fatal (_("failed sanity check."));
3767 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3768 then deal with the bitfield hack. */
3771 crack_operand (char *str, struct m68k_op *opP)
3773 register int parens;
3775 register char *beg_str;
3783 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3789 else if (*str == ')')
3793 opP->error = _("Extra )");
3799 if (flag_mri && *str == '\'')
3800 inquote = ! inquote;
3802 if (!*str && parens)
3804 opP->error = _("Missing )");
3809 if (m68k_ip_op (beg_str, opP) != 0)
3816 c = *++str; /* JF bitfield hack. */
3821 as_bad (_("Missing operand"));
3824 /* Detect MRI REG symbols and convert them to REGLSTs. */
3825 if (opP->mode == CONTROL && (int)opP->reg < 0)
3828 opP->mask = ~(int)opP->reg;
3835 /* This is the guts of the machine-dependent assembler. STR points to a
3836 machine dependent instruction. This function is supposed to emit
3837 the frags/bytes it assembles to.
3841 insert_reg (const char *regname, int regnum)
3846 #ifdef REGISTER_PREFIX
3847 if (!flag_reg_prefix_optional)
3849 buf[0] = REGISTER_PREFIX;
3850 strcpy (buf + 1, regname);
3855 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3856 &zero_address_frag));
3858 for (i = 0; regname[i]; i++)
3859 buf[i] = TOUPPER (regname[i]);
3862 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3863 &zero_address_frag));
3872 static const struct init_entry init_table[] =
3932 { "accext01", ACCEXT01 },
3933 { "accext23", ACCEXT23 },
3937 /* Control registers. */
3938 { "sfc", SFC }, /* Source Function Code. */
3940 { "dfc", DFC }, /* Destination Function Code. */
3942 { "cacr", CACR }, /* Cache Control Register. */
3943 { "caar", CAAR }, /* Cache Address Register. */
3945 { "usp", USP }, /* User Stack Pointer. */
3946 { "vbr", VBR }, /* Vector Base Register. */
3947 { "msp", MSP }, /* Master Stack Pointer. */
3948 { "isp", ISP }, /* Interrupt Stack Pointer. */
3950 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3951 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3952 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3953 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3955 /* 68ec040 versions of same */
3956 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3957 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3958 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3959 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3961 /* Coldfire versions of same. The ColdFire programmer's reference
3962 manual indicated that the order is 2,3,0,1, but Ken Rose
3963 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3964 { "acr0", ACR0 }, /* Access Control Unit 0. */
3965 { "acr1", ACR1 }, /* Access Control Unit 1. */
3966 { "acr2", ACR2 }, /* Access Control Unit 2. */
3967 { "acr3", ACR3 }, /* Access Control Unit 3. */
3969 { "tc", TC }, /* MMU Translation Control Register. */
3973 { "mmusr", MMUSR }, /* MMU Status Register. */
3974 { "srp", SRP }, /* User Root Pointer. */
3975 { "urp", URP }, /* Supervisor Root Pointer. */
3978 { "mmubar", MMUBAR },
3981 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3982 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3983 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3984 { "mbar", MBAR }, /* Module Base Address Register. */
3986 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3987 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3988 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3989 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3990 { "mpcr", MPCR }, /* mcfv4e registers. */
3991 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3992 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3993 { "asid", TC }, /* mcfv4e registers. */
3994 { "mmubar", BUSCR }, /* mcfv4e registers. */
3995 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3996 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3997 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3998 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3999 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4000 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4001 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4002 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4003 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4004 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4005 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4006 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4008 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4009 { "rambar", RAMBAR }, /* mcf528x registers. */
4011 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4013 { "cac", CAC }, /* fido registers. */
4014 { "mbb", MBO }, /* fido registers (obsolete). */
4015 { "mbo", MBO }, /* fido registers. */
4016 /* End of control registers. */
4050 /* 68ec030 versions of same. */
4053 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4056 /* Suppressed data and address registers. */
4074 /* Upper and lower data and address registers, used by macw and msacw. */
4115 init_regtable (void)
4118 for (i = 0; init_table[i].name; i++)
4119 insert_reg (init_table[i].name, init_table[i].number);
4123 md_assemble (char *str)
4130 int shorts_this_frag;
4133 if (!selected_cpu && !selected_arch)
4135 /* We've not selected an architecture yet. Set the default
4136 now. We do this lazily so that an initial .cpu or .arch directive
4138 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4139 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4144 /* In MRI mode, the instruction and operands are separated by a
4145 space. Anything following the operands is a comment. The label
4146 has already been removed. */
4154 for (s = str; *s != '\0'; s++)
4156 if ((*s == ' ' || *s == '\t') && ! inquote)
4174 inquote = ! inquote;
4179 memset (&the_ins, '\0', sizeof (the_ins));
4184 for (n = 0; n < the_ins.numargs; n++)
4185 if (the_ins.operands[n].error)
4187 er = the_ins.operands[n].error;
4193 as_bad (_("%s -- statement `%s' ignored"), er, str);
4197 /* If there is a current label, record that it marks an instruction. */
4198 if (current_label != NULL)
4200 current_label->text = 1;
4201 current_label = NULL;
4205 /* Tie dwarf2 debug info to the address at the start of the insn. */
4206 dwarf2_emit_insn (0);
4209 if (the_ins.nfrag == 0)
4211 /* No frag hacking involved; just put it out. */
4212 toP = frag_more (2 * the_ins.numo);
4213 fromP = &the_ins.opcode[0];
4214 for (m = the_ins.numo; m; --m)
4216 md_number_to_chars (toP, (long) (*fromP), 2);
4220 /* Put out symbol-dependent info. */
4221 for (m = 0; m < the_ins.nrel; m++)
4223 switch (the_ins.reloc[m].wid)
4242 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4243 the_ins.reloc[m].wid);
4246 fixP = fix_new_exp (frag_now,
4247 ((toP - frag_now->fr_literal)
4248 - the_ins.numo * 2 + the_ins.reloc[m].n),
4250 &the_ins.reloc[m].exp,
4251 the_ins.reloc[m].pcrel,
4252 get_reloc_code (n, the_ins.reloc[m].pcrel,
4253 the_ins.reloc[m].pic_reloc));
4254 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4255 if (the_ins.reloc[m].wid == 'B')
4256 fixP->fx_signed = 1;
4261 /* There's some frag hacking. */
4263 /* Calculate the max frag size. */
4266 wid = 2 * the_ins.fragb[0].fragoff;
4267 for (n = 1; n < the_ins.nfrag; n++)
4268 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4269 /* frag_var part. */
4270 wid += FRAG_VAR_SIZE;
4271 /* Make sure the whole insn fits in one chunk, in particular that
4272 the var part is attached, as we access one byte before the
4273 variable frag for byte branches. */
4277 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4282 wid = 2 * the_ins.fragb[n].fragoff;
4284 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4285 toP = frag_more (wid);
4287 shorts_this_frag = 0;
4288 for (m = wid / 2; m; --m)
4290 md_number_to_chars (toP, (long) (*fromP), 2);
4295 for (m = 0; m < the_ins.nrel; m++)
4297 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4299 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4302 wid = the_ins.reloc[m].wid;
4305 the_ins.reloc[m].wid = 0;
4306 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4308 fixP = fix_new_exp (frag_now,
4309 ((toP - frag_now->fr_literal)
4310 - the_ins.numo * 2 + the_ins.reloc[m].n),
4312 &the_ins.reloc[m].exp,
4313 the_ins.reloc[m].pcrel,
4314 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4315 the_ins.reloc[m].pic_reloc));
4316 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4318 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4319 (relax_substateT) (the_ins.fragb[n].fragty),
4320 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4322 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4323 shorts_this_frag = 0;
4326 toP = frag_more (n * 2);
4329 md_number_to_chars (toP, (long) (*fromP), 2);
4335 for (m = 0; m < the_ins.nrel; m++)
4339 wid = the_ins.reloc[m].wid;
4342 the_ins.reloc[m].wid = 0;
4343 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4345 fixP = fix_new_exp (frag_now,
4346 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4347 - shorts_this_frag * 2),
4349 &the_ins.reloc[m].exp,
4350 the_ins.reloc[m].pcrel,
4351 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4352 the_ins.reloc[m].pic_reloc));
4353 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4357 /* Comparison function used by qsort to rank the opcode entries by name. */
4360 m68k_compare_opcode (const void * v1, const void * v2)
4362 struct m68k_opcode * op1, * op2;
4368 op1 = *(struct m68k_opcode **) v1;
4369 op2 = *(struct m68k_opcode **) v2;
4371 /* Compare the two names. If different, return the comparison.
4372 If the same, return the order they are in the opcode table. */
4373 ret = strcmp (op1->name, op2->name);
4384 const struct m68k_opcode *ins;
4385 struct m68k_incant *hack, *slak;
4386 const char *retval = 0; /* Empty string, or error msg text. */
4389 /* Set up hash tables with 68000 instructions.
4390 similar to what the vax assembler does. */
4391 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4392 a copy of it at runtime, adding in the information we want but isn't
4393 there. I think it'd be better to have an awk script hack the table
4394 at compile time. Or even just xstr the table and use it as-is. But
4395 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4400 flag_reg_prefix_optional = 1;
4402 if (! m68k_rel32_from_cmdline)
4406 /* First sort the opcode table into alphabetical order to seperate
4407 the order that the assembler wants to see the opcodes from the
4408 order that the disassembler wants to see them. */
4409 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4410 if (!m68k_sorted_opcodes)
4411 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4412 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4414 for (i = m68k_numopcodes; i--;)
4415 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4417 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4418 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4420 op_hash = hash_new ();
4422 obstack_begin (&robyn, 4000);
4423 for (i = 0; i < m68k_numopcodes; i++)
4425 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4428 ins = m68k_sorted_opcodes[i];
4430 /* We must enter all insns into the table, because .arch and
4431 .cpu directives can change things. */
4432 slak->m_operands = ins->args;
4433 slak->m_arch = ins->arch;
4434 slak->m_opcode = ins->opcode;
4436 /* In most cases we can determine the number of opcode words
4437 by checking the second word of the mask. Unfortunately
4438 some instructions have 2 opcode words, but no fixed bits
4439 in the second word. A leading dot in the operands
4440 string also indicates 2 opcodes. */
4441 if (*slak->m_operands == '.')
4444 slak->m_codenum = 2;
4446 else if (ins->match & 0xffffL)
4447 slak->m_codenum = 2;
4449 slak->m_codenum = 1;
4450 slak->m_opnum = strlen (slak->m_operands) / 2;
4452 if (i + 1 != m68k_numopcodes
4453 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4455 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4460 slak = slak->m_next;
4464 retval = hash_insert (op_hash, ins->name, (char *) hack);
4466 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4469 for (i = 0; i < m68k_numaliases; i++)
4471 const char *name = m68k_opcode_aliases[i].primary;
4472 const char *alias = m68k_opcode_aliases[i].alias;
4473 void *val = hash_find (op_hash, name);
4476 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4477 retval = hash_insert (op_hash, alias, val);
4479 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4482 /* In MRI mode, all unsized branches are variable sized. Normally,
4483 they are word sized. */
4486 static struct m68k_opcode_alias mri_aliases[] =
4507 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4510 const char *name = mri_aliases[i].primary;
4511 const char *alias = mri_aliases[i].alias;
4512 void *val = hash_find (op_hash, name);
4515 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4516 retval = hash_jam (op_hash, alias, val);
4518 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4522 for (i = 0; i < (int) sizeof (notend_table); i++)
4524 notend_table[i] = 0;
4525 alt_notend_table[i] = 0;
4528 notend_table[','] = 1;
4529 notend_table['{'] = 1;
4530 notend_table['}'] = 1;
4531 alt_notend_table['a'] = 1;
4532 alt_notend_table['A'] = 1;
4533 alt_notend_table['d'] = 1;
4534 alt_notend_table['D'] = 1;
4535 alt_notend_table['#'] = 1;
4536 alt_notend_table['&'] = 1;
4537 alt_notend_table['f'] = 1;
4538 alt_notend_table['F'] = 1;
4539 #ifdef REGISTER_PREFIX
4540 alt_notend_table[REGISTER_PREFIX] = 1;
4543 /* We need to put '(' in alt_notend_table to handle
4544 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4545 alt_notend_table['('] = 1;
4547 /* We need to put '@' in alt_notend_table to handle
4548 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4549 alt_notend_table['@'] = 1;
4551 /* We need to put digits in alt_notend_table to handle
4552 bfextu %d0{24:1},%d0 */
4553 alt_notend_table['0'] = 1;
4554 alt_notend_table['1'] = 1;
4555 alt_notend_table['2'] = 1;
4556 alt_notend_table['3'] = 1;
4557 alt_notend_table['4'] = 1;
4558 alt_notend_table['5'] = 1;
4559 alt_notend_table['6'] = 1;
4560 alt_notend_table['7'] = 1;
4561 alt_notend_table['8'] = 1;
4562 alt_notend_table['9'] = 1;
4564 #ifndef MIT_SYNTAX_ONLY
4565 /* Insert pseudo ops, these have to go into the opcode table since
4566 gas expects pseudo ops to start with a dot. */
4570 while (mote_pseudo_table[n].poc_name)
4572 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4573 hash_insert (op_hash,
4574 mote_pseudo_table[n].poc_name, (char *) hack);
4575 hack->m_operands = 0;
4585 record_alignment (text_section, 2);
4586 record_alignment (data_section, 2);
4587 record_alignment (bss_section, 2);
4592 /* This is called when a label is defined. */
4595 m68k_frob_label (symbolS *sym)
4597 struct label_line *n;
4599 n = (struct label_line *) xmalloc (sizeof *n);
4602 as_where (&n->file, &n->line);
4608 dwarf2_emit_label (sym);
4612 /* This is called when a value that is not an instruction is emitted. */
4615 m68k_flush_pending_output (void)
4617 current_label = NULL;
4620 /* This is called at the end of the assembly, when the final value of
4621 the label is known. We warn if this is a text symbol aligned at an
4625 m68k_frob_symbol (symbolS *sym)
4627 if (S_GET_SEGMENT (sym) == reg_section
4628 && (int) S_GET_VALUE (sym) < 0)
4630 S_SET_SEGMENT (sym, absolute_section);
4631 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4633 else if ((S_GET_VALUE (sym) & 1) != 0)
4635 struct label_line *l;
4637 for (l = labels; l != NULL; l = l->next)
4639 if (l->label == sym)
4642 as_warn_where (l->file, l->line,
4643 _("text label `%s' aligned to odd boundary"),
4651 /* This is called if we go in or out of MRI mode because of the .mri
4655 m68k_mri_mode_change (int on)
4659 if (! flag_reg_prefix_optional)
4661 flag_reg_prefix_optional = 1;
4662 #ifdef REGISTER_PREFIX
4667 if (! m68k_rel32_from_cmdline)
4672 if (! reg_prefix_optional_seen)
4674 #ifdef REGISTER_PREFIX_OPTIONAL
4675 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4677 flag_reg_prefix_optional = 0;
4679 #ifdef REGISTER_PREFIX
4684 if (! m68k_rel32_from_cmdline)
4690 md_atof (int type, char *litP, int *sizeP)
4692 return ieee_md_atof (type, litP, sizeP, TRUE);
4696 md_number_to_chars (char *buf, valueT val, int n)
4698 number_to_chars_bigendian (buf, val, n);
4702 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4704 offsetT val = *valP;
4705 addressT upper_limit;
4706 offsetT lower_limit;
4708 /* This is unnecessary but it convinces the native rs6000 compiler
4709 to generate the code we want. */
4710 char *buf = fixP->fx_frag->fr_literal;
4711 buf += fixP->fx_where;
4712 /* End ibm compiler workaround. */
4716 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4722 memset (buf, 0, fixP->fx_size);
4723 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4725 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4726 && !S_IS_DEFINED (fixP->fx_addsy)
4727 && !S_IS_WEAK (fixP->fx_addsy))
4728 S_SET_WEAK (fixP->fx_addsy);
4731 #elif defined(OBJ_AOUT)
4732 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4733 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4735 memset (buf, 0, fixP->fx_size);
4736 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4741 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4742 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4745 switch (fixP->fx_size)
4747 /* The cast to offsetT below are necessary to make code
4748 correct for machines where ints are smaller than offsetT. */
4752 lower_limit = - (offsetT) 0x80;
4755 *buf++ = (val >> 8);
4757 upper_limit = 0x7fff;
4758 lower_limit = - (offsetT) 0x8000;
4761 *buf++ = (val >> 24);
4762 *buf++ = (val >> 16);
4763 *buf++ = (val >> 8);
4765 upper_limit = 0x7fffffff;
4766 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4769 BAD_CASE (fixP->fx_size);
4772 /* Fix up a negative reloc. */
4773 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4775 fixP->fx_addsy = fixP->fx_subsy;
4776 fixP->fx_subsy = NULL;
4780 /* For non-pc-relative values, it's conceivable we might get something
4781 like "0xff" for a byte field. So extend the upper part of the range
4782 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4783 so that we can do any range checking at all. */
4784 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4785 upper_limit = upper_limit * 2 + 1;
4787 if ((addressT) val > upper_limit
4788 && (val > 0 || val < lower_limit))
4789 as_bad_where (fixP->fx_file, fixP->fx_line,
4790 _("value %ld out of range"), (long)val);
4792 /* A one byte PC-relative reloc means a short branch. We can't use
4793 a short branch with a value of 0 or -1, because those indicate
4794 different opcodes (branches with longer offsets). fixup_segment
4795 in write.c may have clobbered fx_pcrel, so we need to examine the
4798 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4799 && fixP->fx_size == 1
4800 && (fixP->fx_addsy == NULL
4801 || S_IS_DEFINED (fixP->fx_addsy))
4802 && (val == 0 || val == -1))
4803 as_bad_where (fixP->fx_file, fixP->fx_line,
4804 _("invalid byte branch offset"));
4807 /* *fragP has been relaxed to its final size, and now needs to have
4808 the bytes inside it modified to conform to the new size There is UGLY
4812 md_convert_frag_1 (fragS *fragP)
4817 /* Address in object code of the displacement. */
4818 register int object_address = fragP->fr_fix + fragP->fr_address;
4820 /* Address in gas core of the place to store the displacement. */
4821 /* This convinces the native rs6000 compiler to generate the code we
4823 register char *buffer_address = fragP->fr_literal;
4824 buffer_address += fragP->fr_fix;
4825 /* End ibm compiler workaround. */
4827 /* The displacement of the address, from current location. */
4828 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4829 disp = (disp + fragP->fr_offset) - object_address;
4831 switch (fragP->fr_subtype)
4833 case TAB (BRANCHBWL, BYTE):
4834 case TAB (BRABSJUNC, BYTE):
4835 case TAB (BRABSJCOND, BYTE):
4836 case TAB (BRANCHBW, BYTE):
4837 case TAB (BRANCHBWPL, BYTE):
4838 know (issbyte (disp));
4840 as_bad_where (fragP->fr_file, fragP->fr_line,
4841 _("short branch with zero offset: use :w"));
4842 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4843 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4844 fixP->fx_pcrel_adjust = -1;
4846 case TAB (BRANCHBWL, SHORT):
4847 case TAB (BRABSJUNC, SHORT):
4848 case TAB (BRABSJCOND, SHORT):
4849 case TAB (BRANCHBW, SHORT):
4850 case TAB (BRANCHBWPL, SHORT):
4851 fragP->fr_opcode[1] = 0x00;
4852 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4853 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4856 case TAB (BRANCHBWL, LONG):
4857 fragP->fr_opcode[1] = (char) 0xFF;
4858 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4859 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4862 case TAB (BRANCHBWPL, LONG):
4863 /* Here we are converting an unconditional branch into a pair of
4864 conditional branches, in order to get the range. */
4865 fragP->fr_opcode[0] = 0x66; /* bne */
4866 fragP->fr_opcode[1] = 0xFF;
4867 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4868 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4869 fixP->fx_file = fragP->fr_file;
4870 fixP->fx_line = fragP->fr_line;
4871 fragP->fr_fix += 4; /* Skip first offset */
4872 buffer_address += 4;
4873 *buffer_address++ = 0x67; /* beq */
4874 *buffer_address++ = 0xff;
4875 fragP->fr_fix += 2; /* Skip second branch opcode */
4876 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4877 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4880 case TAB (BRABSJUNC, LONG):
4881 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4883 if (flag_keep_pcrel)
4884 as_bad_where (fragP->fr_file, fragP->fr_line,
4885 _("Conversion of PC relative BSR to absolute JSR"));
4886 fragP->fr_opcode[0] = 0x4E;
4887 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4888 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4889 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4892 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4894 if (flag_keep_pcrel)
4895 as_bad_where (fragP->fr_file, fragP->fr_line,
4896 _("Conversion of PC relative branch to absolute jump"));
4897 fragP->fr_opcode[0] = 0x4E;
4898 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4899 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4900 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4905 /* This cannot happen, because jbsr and jbra are the only two
4906 unconditional branches. */
4910 case TAB (BRABSJCOND, LONG):
4911 if (flag_keep_pcrel)
4912 as_bad_where (fragP->fr_file, fragP->fr_line,
4913 _("Conversion of PC relative conditional branch to absolute jump"));
4915 /* Only Bcc 68000 instructions can come here
4916 Change bcc into b!cc/jmp absl long. */
4917 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4918 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4920 /* JF: these used to be fr_opcode[2,3], but they may be in a
4921 different frag, in which case referring to them is a no-no.
4922 Only fr_opcode[0,1] are guaranteed to work. */
4923 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4924 *buffer_address++ = (char) 0xf9;
4925 fragP->fr_fix += 2; /* Account for jmp instruction. */
4926 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4927 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4930 case TAB (FBRANCH, SHORT):
4931 know ((fragP->fr_opcode[1] & 0x40) == 0);
4932 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4933 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4936 case TAB (FBRANCH, LONG):
4937 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4938 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4939 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4942 case TAB (DBCCLBR, SHORT):
4943 case TAB (DBCCABSJ, SHORT):
4944 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4945 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4948 case TAB (DBCCLBR, LONG):
4949 /* Only DBcc instructions can come here.
4950 Change dbcc into dbcc/bral.
4951 JF: these used to be fr_opcode[2-7], but that's wrong. */
4952 if (flag_keep_pcrel)
4953 as_bad_where (fragP->fr_file, fragP->fr_line,
4954 _("Conversion of DBcc to absolute jump"));
4956 *buffer_address++ = 0x00; /* Branch offset = 4. */
4957 *buffer_address++ = 0x04;
4958 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4959 *buffer_address++ = 0x06;
4960 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4961 *buffer_address++ = (char) 0xff;
4963 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4964 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4965 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4968 case TAB (DBCCABSJ, LONG):
4969 /* Only DBcc instructions can come here.
4970 Change dbcc into dbcc/jmp.
4971 JF: these used to be fr_opcode[2-7], but that's wrong. */
4972 if (flag_keep_pcrel)
4973 as_bad_where (fragP->fr_file, fragP->fr_line,
4974 _("Conversion of PC relative conditional branch to absolute jump"));
4976 *buffer_address++ = 0x00; /* Branch offset = 4. */
4977 *buffer_address++ = 0x04;
4978 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4979 *buffer_address++ = 0x06;
4980 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4981 *buffer_address++ = (char) 0xf9;
4983 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4984 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4985 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4988 case TAB (PCREL1632, SHORT):
4989 fragP->fr_opcode[1] &= ~0x3F;
4990 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4991 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4992 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4995 case TAB (PCREL1632, LONG):
4996 /* Already set to mode 7.3; this indicates: PC indirect with
4997 suppressed index, 32-bit displacement. */
4998 *buffer_address++ = 0x01;
4999 *buffer_address++ = 0x70;
5001 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5002 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5003 fixP->fx_pcrel_adjust = 2;
5006 case TAB (PCINDEX, BYTE):
5007 assert (fragP->fr_fix >= 2);
5008 buffer_address[-2] &= ~1;
5009 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5010 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5011 fixP->fx_pcrel_adjust = 1;
5013 case TAB (PCINDEX, SHORT):
5014 assert (fragP->fr_fix >= 2);
5015 buffer_address[-2] |= 0x1;
5016 buffer_address[-1] = 0x20;
5017 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5018 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5019 fixP->fx_pcrel_adjust = 2;
5022 case TAB (PCINDEX, LONG):
5023 assert (fragP->fr_fix >= 2);
5024 buffer_address[-2] |= 0x1;
5025 buffer_address[-1] = 0x30;
5026 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5027 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5028 fixP->fx_pcrel_adjust = 2;
5031 case TAB (ABSTOPCREL, SHORT):
5032 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5033 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5036 case TAB (ABSTOPCREL, LONG):
5037 if (flag_keep_pcrel)
5038 as_bad_where (fragP->fr_file, fragP->fr_line,
5039 _("Conversion of PC relative displacement to absolute"));
5040 /* The thing to do here is force it to ABSOLUTE LONG, since
5041 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5042 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5044 fragP->fr_opcode[1] &= ~0x3F;
5045 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5046 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5047 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5053 fixP->fx_file = fragP->fr_file;
5054 fixP->fx_line = fragP->fr_line;
5059 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5060 segT sec ATTRIBUTE_UNUSED,
5063 md_convert_frag_1 (fragP);
5066 /* Force truly undefined symbols to their maximum size, and generally set up
5067 the frag list to be relaxed
5070 md_estimate_size_before_relax (fragS *fragP, segT segment)
5072 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5073 switch (fragP->fr_subtype)
5075 case TAB (BRANCHBWL, SZ_UNDEF):
5076 case TAB (BRANCHBWPL, SZ_UNDEF):
5077 case TAB (BRABSJUNC, SZ_UNDEF):
5078 case TAB (BRABSJCOND, SZ_UNDEF):
5080 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5081 && relaxable_symbol (fragP->fr_symbol))
5083 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5085 else if (flag_short_refs)
5087 /* Symbol is undefined and we want short ref. */
5088 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5092 /* Symbol is still undefined. Make it LONG. */
5093 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5098 case TAB (BRANCHBW, SZ_UNDEF):
5100 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5101 && relaxable_symbol (fragP->fr_symbol))
5103 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5107 /* Symbol is undefined and we don't have long branches. */
5108 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5113 case TAB (FBRANCH, SZ_UNDEF):
5114 case TAB (DBCCLBR, SZ_UNDEF):
5115 case TAB (DBCCABSJ, SZ_UNDEF):
5116 case TAB (PCREL1632, SZ_UNDEF):
5118 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5119 && relaxable_symbol (fragP->fr_symbol))
5122 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5126 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5131 case TAB (PCINDEX, SZ_UNDEF):
5132 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5133 && relaxable_symbol (fragP->fr_symbol)))
5135 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5139 fragP->fr_subtype = TAB (PCINDEX, LONG);
5143 case TAB (ABSTOPCREL, SZ_UNDEF):
5145 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5146 && relaxable_symbol (fragP->fr_symbol)))
5148 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5152 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5161 /* Now that SZ_UNDEF are taken care of, check others. */
5162 switch (fragP->fr_subtype)
5164 case TAB (BRANCHBWL, BYTE):
5165 case TAB (BRABSJUNC, BYTE):
5166 case TAB (BRABSJCOND, BYTE):
5167 case TAB (BRANCHBW, BYTE):
5168 /* We can't do a short jump to the next instruction, so in that
5169 case we force word mode. If the symbol is at the start of a
5170 frag, and it is the next frag with any data in it (usually
5171 this is just the next frag, but assembler listings may
5172 introduce empty frags), we must use word mode. */
5173 if (fragP->fr_symbol)
5177 sym_frag = symbol_get_frag (fragP->fr_symbol);
5178 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5182 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5186 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5193 return md_relax_table[fragP->fr_subtype].rlx_length;
5196 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5197 /* the bit-field entries in the relocation_info struct plays hell
5198 with the byte-order problems of cross-assembly. So as a hack,
5199 I added this mach. dependent ri twiddler. Ugly, but it gets
5201 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5202 are symbolnum, most sig. byte first. Last byte is broken up with
5203 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5204 nibble as nuthin. (on Sun 3 at least) */
5205 /* Translate the internal relocation information into target-specific
5209 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5212 md_number_to_chars (the_bytes, ri->r_address, 4);
5213 /* Now the fun stuff. */
5214 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5215 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5216 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5217 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5218 | ((ri->r_length << 5) & 0x60)
5219 | ((ri->r_extern << 4) & 0x10));
5224 #endif /* OBJ_AOUT or OBJ_BOUT */
5226 #ifndef WORKING_DOT_WORD
5227 int md_short_jump_size = 4;
5228 int md_long_jump_size = 6;
5231 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5232 fragS *frag ATTRIBUTE_UNUSED,
5233 symbolS *to_symbol ATTRIBUTE_UNUSED)
5237 offset = to_addr - (from_addr + 2);
5239 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5240 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5244 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5245 fragS *frag, symbolS *to_symbol)
5249 if (!HAVE_LONG_BRANCH (current_architecture))
5251 if (flag_keep_pcrel)
5252 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5253 offset = to_addr - S_GET_VALUE (to_symbol);
5254 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5255 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5256 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5261 offset = to_addr - (from_addr + 2);
5262 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5263 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5269 /* Different values of OK tell what its OK to return. Things that
5270 aren't OK are an error (what a shock, no?)
5273 10: Absolute 1:8 only
5274 20: Absolute 0:7 only
5275 30: absolute 0:15 only
5276 40: Absolute 0:31 only
5277 50: absolute 0:127 only
5278 55: absolute -64:63 only
5279 60: absolute -128:127 only
5280 65: absolute 0:511 only
5281 70: absolute 0:4095 only
5282 80: absolute -1, 1:7 only
5286 get_num (struct m68k_exp *exp, int ok)
5288 if (exp->exp.X_op == O_absent)
5290 /* Do the same thing the VAX asm does. */
5291 op (exp) = O_constant;
5297 as_warn (_("expression out of range: defaulting to 1"));
5301 else if (exp->exp.X_op == O_constant)
5306 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5308 as_warn (_("expression out of range: defaulting to 1"));
5313 if ((valueT) TRUNC (offs (exp)) > 7)
5317 if ((valueT) TRUNC (offs (exp)) > 15)
5321 if ((valueT) TRUNC (offs (exp)) > 32)
5325 if ((valueT) TRUNC (offs (exp)) > 127)
5329 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5333 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5337 if ((valueT) TRUNC (offs (exp)) > 511)
5341 if ((valueT) TRUNC (offs (exp)) > 4095)
5344 as_warn (_("expression out of range: defaulting to 0"));
5349 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5350 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5352 as_warn (_("expression out of range: defaulting to 1"));
5360 else if (exp->exp.X_op == O_big)
5362 if (offs (exp) <= 0 /* flonum. */
5363 && (ok == 90 /* no bignums */
5364 || (ok > 10 /* Small-int ranges including 0 ok. */
5365 /* If we have a flonum zero, a zero integer should
5366 do as well (e.g., in moveq). */
5367 && generic_floating_point_number.exponent == 0
5368 && generic_floating_point_number.low[0] == 0)))
5370 /* HACK! Turn it into a long. */
5371 LITTLENUM_TYPE words[6];
5373 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5374 op (exp) = O_constant;
5377 offs (exp) = words[1] | (words[0] << 16);
5381 op (exp) = O_constant;
5384 offs (exp) = (ok == 10) ? 1 : 0;
5385 as_warn (_("Can't deal with expression; defaulting to %ld"),
5391 if (ok >= 10 && ok <= 80)
5393 op (exp) = O_constant;
5396 offs (exp) = (ok == 10) ? 1 : 0;
5397 as_warn (_("Can't deal with expression; defaulting to %ld"),
5402 if (exp->size != SIZE_UNSPEC)
5410 if (!isbyte (offs (exp)))
5411 as_warn (_("expression doesn't fit in BYTE"));
5414 if (!isword (offs (exp)))
5415 as_warn (_("expression doesn't fit in WORD"));
5423 /* These are the back-ends for the various machine dependent pseudo-ops. */
5426 s_data1 (int ignore ATTRIBUTE_UNUSED)
5428 subseg_set (data_section, 1);
5429 demand_empty_rest_of_line ();
5433 s_data2 (int ignore ATTRIBUTE_UNUSED)
5435 subseg_set (data_section, 2);
5436 demand_empty_rest_of_line ();
5440 s_bss (int ignore ATTRIBUTE_UNUSED)
5442 /* We don't support putting frags in the BSS segment, we fake it
5443 by marking in_bss, then looking at s_skip for clues. */
5445 subseg_set (bss_section, 0);
5446 demand_empty_rest_of_line ();
5450 s_even (int ignore ATTRIBUTE_UNUSED)
5453 register long temp_fill;
5455 temp = 1; /* JF should be 2? */
5456 temp_fill = get_absolute_expression ();
5457 if (!need_pass_2) /* Never make frag if expect extra pass. */
5458 frag_align (temp, (int) temp_fill, 0);
5459 demand_empty_rest_of_line ();
5460 record_alignment (now_seg, temp);
5464 s_proc (int ignore ATTRIBUTE_UNUSED)
5466 demand_empty_rest_of_line ();
5469 /* Pseudo-ops handled for MRI compatibility. */
5471 /* This function returns non-zero if the argument is a conditional
5472 pseudo-op. This is called when checking whether a pending
5473 alignment is needed. */
5476 m68k_conditional_pseudoop (pseudo_typeS *pop)
5478 return (pop->poc_handler == s_mri_if
5479 || pop->poc_handler == s_mri_else);
5482 /* Handle an MRI style chip specification. */
5491 s = input_line_pointer;
5492 /* We can't use get_symbol_end since the processor names are not proper
5494 while (is_part_of_name (c = *input_line_pointer++))
5496 *--input_line_pointer = 0;
5497 for (i = 0; m68k_cpus[i].name; i++)
5498 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5500 if (!m68k_cpus[i].name)
5502 as_bad (_("%s: unrecognized processor name"), s);
5503 *input_line_pointer = c;
5504 ignore_rest_of_line ();
5507 *input_line_pointer = c;
5509 if (*input_line_pointer == '/')
5510 current_architecture = 0;
5512 current_architecture &= m68881 | m68851;
5513 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5514 control_regs = m68k_cpus[i].control_regs;
5516 while (*input_line_pointer == '/')
5518 ++input_line_pointer;
5519 s = input_line_pointer;
5520 /* We can't use get_symbol_end since the processor names are not
5522 while (is_part_of_name (c = *input_line_pointer++))
5524 *--input_line_pointer = 0;
5525 if (strcmp (s, "68881") == 0)
5526 current_architecture |= m68881;
5527 else if (strcmp (s, "68851") == 0)
5528 current_architecture |= m68851;
5529 *input_line_pointer = c;
5533 /* The MRI CHIP pseudo-op. */
5536 s_chip (int ignore ATTRIBUTE_UNUSED)
5542 stop = mri_comment_field (&stopc);
5545 mri_comment_end (stop, stopc);
5546 demand_empty_rest_of_line ();
5549 /* The MRI FOPT pseudo-op. */
5552 s_fopt (int ignore ATTRIBUTE_UNUSED)
5556 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5560 input_line_pointer += 3;
5561 temp = get_absolute_expression ();
5562 if (temp < 0 || temp > 7)
5563 as_bad (_("bad coprocessor id"));
5565 m68k_float_copnum = COP0 + temp;
5569 as_bad (_("unrecognized fopt option"));
5570 ignore_rest_of_line ();
5574 demand_empty_rest_of_line ();
5577 /* The structure used to handle the MRI OPT pseudo-op. */
5581 /* The name of the option. */
5584 /* If this is not NULL, just call this function. The first argument
5585 is the ARG field of this structure, the second argument is
5586 whether the option was negated. */
5587 void (*pfn) (int arg, int on);
5589 /* If this is not NULL, and the PFN field is NULL, set the variable
5590 this points to. Set it to the ARG field if the option was not
5591 negated, and the NOTARG field otherwise. */
5594 /* The value to pass to PFN or to assign to *PVAR. */
5597 /* The value to assign to *PVAR if the option is negated. If PFN is
5598 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5599 the option may not be negated. */
5603 /* The table used to handle the MRI OPT pseudo-op. */
5605 static void skip_to_comma (int, int);
5606 static void opt_nest (int, int);
5607 static void opt_chip (int, int);
5608 static void opt_list (int, int);
5609 static void opt_list_symbols (int, int);
5611 static const struct opt_action opt_table[] =
5613 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5615 /* We do relaxing, so there is little use for these options. */
5616 { "b", 0, 0, 0, 0 },
5617 { "brs", 0, 0, 0, 0 },
5618 { "brb", 0, 0, 0, 0 },
5619 { "brl", 0, 0, 0, 0 },
5620 { "brw", 0, 0, 0, 0 },
5622 { "c", 0, 0, 0, 0 },
5623 { "cex", 0, 0, 0, 0 },
5624 { "case", 0, &symbols_case_sensitive, 1, 0 },
5625 { "cl", 0, 0, 0, 0 },
5626 { "cre", 0, 0, 0, 0 },
5627 { "d", 0, &flag_keep_locals, 1, 0 },
5628 { "e", 0, 0, 0, 0 },
5629 { "f", 0, &flag_short_refs, 1, 0 },
5630 { "frs", 0, &flag_short_refs, 1, 0 },
5631 { "frl", 0, &flag_short_refs, 0, 1 },
5632 { "g", 0, 0, 0, 0 },
5633 { "i", 0, 0, 0, 0 },
5634 { "m", 0, 0, 0, 0 },
5635 { "mex", 0, 0, 0, 0 },
5636 { "mc", 0, 0, 0, 0 },
5637 { "md", 0, 0, 0, 0 },
5638 { "nest", opt_nest, 0, 0, 0 },
5639 { "next", skip_to_comma, 0, 0, 0 },
5640 { "o", 0, 0, 0, 0 },
5641 { "old", 0, 0, 0, 0 },
5642 { "op", skip_to_comma, 0, 0, 0 },
5643 { "pco", 0, 0, 0, 0 },
5644 { "p", opt_chip, 0, 0, 0 },
5645 { "pcr", 0, 0, 0, 0 },
5646 { "pcs", 0, 0, 0, 0 },
5647 { "r", 0, 0, 0, 0 },
5648 { "quick", 0, &m68k_quick, 1, 0 },
5649 { "rel32", 0, &m68k_rel32, 1, 0 },
5650 { "s", opt_list, 0, 0, 0 },
5651 { "t", opt_list_symbols, 0, 0, 0 },
5652 { "w", 0, &flag_no_warnings, 0, 1 },
5656 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5658 /* The MRI OPT pseudo-op. */
5661 s_opt (int ignore ATTRIBUTE_UNUSED)
5669 const struct opt_action *o;
5674 if (*input_line_pointer == '-')
5676 ++input_line_pointer;
5679 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5681 input_line_pointer += 2;
5685 s = input_line_pointer;
5686 c = get_symbol_end ();
5688 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5690 if (strcasecmp (s, o->name) == 0)
5694 /* Restore input_line_pointer now in case the option
5696 *input_line_pointer = c;
5697 (*o->pfn) (o->arg, t);
5699 else if (o->pvar != NULL)
5701 if (! t && o->arg == o->notarg)
5702 as_bad (_("option `%s' may not be negated"), s);
5703 *input_line_pointer = c;
5704 *o->pvar = t ? o->arg : o->notarg;
5707 *input_line_pointer = c;
5713 as_bad (_("option `%s' not recognized"), s);
5714 *input_line_pointer = c;
5717 while (*input_line_pointer++ == ',');
5719 /* Move back to terminating character. */
5720 --input_line_pointer;
5721 demand_empty_rest_of_line ();
5724 /* Skip ahead to a comma. This is used for OPT options which we do
5725 not support and which take arguments. */
5728 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5730 while (*input_line_pointer != ','
5731 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5732 ++input_line_pointer;
5735 /* Handle the OPT NEST=depth option. */
5738 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5740 if (*input_line_pointer != '=')
5742 as_bad (_("bad format of OPT NEST=depth"));
5746 ++input_line_pointer;
5747 max_macro_nest = get_absolute_expression ();
5750 /* Handle the OPT P=chip option. */
5753 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5755 if (*input_line_pointer != '=')
5757 /* This is just OPT P, which we do not support. */
5761 ++input_line_pointer;
5765 /* Handle the OPT S option. */
5768 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5773 /* Handle the OPT T option. */
5776 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5779 listing |= LISTING_SYMBOLS;
5781 listing &= ~LISTING_SYMBOLS;
5784 /* Handle the MRI REG pseudo-op. */
5787 s_reg (int ignore ATTRIBUTE_UNUSED)
5796 if (line_label == NULL)
5798 as_bad (_("missing label"));
5799 ignore_rest_of_line ();
5804 stop = mri_comment_field (&stopc);
5808 s = input_line_pointer;
5809 while (ISALNUM (*input_line_pointer)
5810 #ifdef REGISTER_PREFIX
5811 || *input_line_pointer == REGISTER_PREFIX
5813 || *input_line_pointer == '/'
5814 || *input_line_pointer == '-')
5815 ++input_line_pointer;
5816 c = *input_line_pointer;
5817 *input_line_pointer = '\0';
5819 if (m68k_ip_op (s, &rop) != 0)
5821 if (rop.error == NULL)
5822 as_bad (_("bad register list"));
5824 as_bad (_("bad register list: %s"), rop.error);
5825 *input_line_pointer = c;
5826 ignore_rest_of_line ();
5830 *input_line_pointer = c;
5832 if (rop.mode == REGLST)
5834 else if (rop.mode == DREG)
5835 mask = 1 << (rop.reg - DATA0);
5836 else if (rop.mode == AREG)
5837 mask = 1 << (rop.reg - ADDR0 + 8);
5838 else if (rop.mode == FPREG)
5839 mask = 1 << (rop.reg - FP0 + 16);
5840 else if (rop.mode == CONTROL
5843 else if (rop.mode == CONTROL
5846 else if (rop.mode == CONTROL
5851 as_bad (_("bad register list"));
5852 ignore_rest_of_line ();
5856 S_SET_SEGMENT (line_label, reg_section);
5857 S_SET_VALUE (line_label, ~mask);
5858 symbol_set_frag (line_label, &zero_address_frag);
5861 mri_comment_end (stop, stopc);
5863 demand_empty_rest_of_line ();
5866 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5870 struct save_opts *next;
5872 int symbols_case_sensitive;
5876 const enum m68k_register *control_regs;
5881 /* FIXME: We don't save OPT S. */
5884 /* This variable holds the stack of saved options. */
5886 static struct save_opts *save_stack;
5888 /* The MRI SAVE pseudo-op. */
5891 s_save (int ignore ATTRIBUTE_UNUSED)
5893 struct save_opts *s;
5895 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5896 s->abspcadd = m68k_abspcadd;
5897 s->symbols_case_sensitive = symbols_case_sensitive;
5898 s->keep_locals = flag_keep_locals;
5899 s->short_refs = flag_short_refs;
5900 s->architecture = current_architecture;
5901 s->control_regs = control_regs;
5902 s->quick = m68k_quick;
5903 s->rel32 = m68k_rel32;
5904 s->listing = listing;
5905 s->no_warnings = flag_no_warnings;
5907 s->next = save_stack;
5910 demand_empty_rest_of_line ();
5913 /* The MRI RESTORE pseudo-op. */
5916 s_restore (int ignore ATTRIBUTE_UNUSED)
5918 struct save_opts *s;
5920 if (save_stack == NULL)
5922 as_bad (_("restore without save"));
5923 ignore_rest_of_line ();
5928 save_stack = s->next;
5930 m68k_abspcadd = s->abspcadd;
5931 symbols_case_sensitive = s->symbols_case_sensitive;
5932 flag_keep_locals = s->keep_locals;
5933 flag_short_refs = s->short_refs;
5934 current_architecture = s->architecture;
5935 control_regs = s->control_regs;
5936 m68k_quick = s->quick;
5937 m68k_rel32 = s->rel32;
5938 listing = s->listing;
5939 flag_no_warnings = s->no_warnings;
5943 demand_empty_rest_of_line ();
5946 /* Types of MRI structured control directives. */
5948 enum mri_control_type
5956 /* This structure is used to stack the MRI structured control
5959 struct mri_control_info
5961 /* The directive within which this one is enclosed. */
5962 struct mri_control_info *outer;
5964 /* The type of directive. */
5965 enum mri_control_type type;
5967 /* Whether an ELSE has been in an IF. */
5970 /* The add or sub statement at the end of a FOR. */
5973 /* The label of the top of a FOR or REPEAT loop. */
5976 /* The label to jump to for the next iteration, or the else
5977 expression of a conditional. */
5980 /* The label to jump to to break out of the loop, or the label past
5981 the end of a conditional. */
5985 /* The stack of MRI structured control directives. */
5987 static struct mri_control_info *mri_control_stack;
5989 /* The current MRI structured control directive index number, used to
5990 generate label names. */
5992 static int mri_control_index;
5994 /* Assemble an instruction for an MRI structured control directive. */
5997 mri_assemble (char *str)
6001 /* md_assemble expects the opcode to be in lower case. */
6002 for (s = str; *s != ' ' && *s != '\0'; s++)
6008 /* Generate a new MRI label structured control directive label name. */
6011 mri_control_label (void)
6015 n = (char *) xmalloc (20);
6016 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6017 ++mri_control_index;
6021 /* Create a new MRI structured control directive. */
6023 static struct mri_control_info *
6024 push_mri_control (enum mri_control_type type)
6026 struct mri_control_info *n;
6028 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6032 if (type == mri_if || type == mri_while)
6035 n->top = mri_control_label ();
6036 n->next = mri_control_label ();
6037 n->bottom = mri_control_label ();
6039 n->outer = mri_control_stack;
6040 mri_control_stack = n;
6045 /* Pop off the stack of MRI structured control directives. */
6048 pop_mri_control (void)
6050 struct mri_control_info *n;
6052 n = mri_control_stack;
6053 mri_control_stack = n->outer;
6061 /* Recognize a condition code in an MRI structured control expression. */
6064 parse_mri_condition (int *pcc)
6068 know (*input_line_pointer == '<');
6070 ++input_line_pointer;
6071 c1 = *input_line_pointer++;
6072 c2 = *input_line_pointer++;
6074 if (*input_line_pointer != '>')
6076 as_bad (_("syntax error in structured control directive"));
6080 ++input_line_pointer;
6086 *pcc = (c1 << 8) | c2;
6091 /* Parse a single operand in an MRI structured control expression. */
6094 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6095 char **rightstart, char **rightstop)
6107 if (*input_line_pointer == '<')
6109 /* It's just a condition code. */
6110 return parse_mri_condition (pcc);
6113 /* Look ahead for the condition code. */
6114 for (s = input_line_pointer; *s != '\0'; ++s)
6116 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6121 as_bad (_("missing condition code in structured control directive"));
6125 *leftstart = input_line_pointer;
6127 if (*leftstop > *leftstart
6128 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6131 input_line_pointer = s;
6132 if (! parse_mri_condition (pcc))
6135 /* Look ahead for AND or OR or end of line. */
6136 for (s = input_line_pointer; *s != '\0'; ++s)
6138 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6139 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6141 if ((s == input_line_pointer
6144 && ((strncasecmp (s, "AND", 3) == 0
6145 && (s[3] == '.' || ! is_part_of_name (s[3])))
6146 || (strncasecmp (s, "OR", 2) == 0
6147 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6151 *rightstart = input_line_pointer;
6153 if (*rightstop > *rightstart
6154 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6157 input_line_pointer = s;
6162 #define MCC(b1, b2) (((b1) << 8) | (b2))
6164 /* Swap the sense of a condition. This changes the condition so that
6165 it generates the same result when the operands are swapped. */
6168 swap_mri_condition (int cc)
6172 case MCC ('h', 'i'): return MCC ('c', 's');
6173 case MCC ('l', 's'): return MCC ('c', 'c');
6174 /* <HS> is an alias for <CC>. */
6175 case MCC ('h', 's'):
6176 case MCC ('c', 'c'): return MCC ('l', 's');
6177 /* <LO> is an alias for <CS>. */
6178 case MCC ('l', 'o'):
6179 case MCC ('c', 's'): return MCC ('h', 'i');
6180 case MCC ('p', 'l'): return MCC ('m', 'i');
6181 case MCC ('m', 'i'): return MCC ('p', 'l');
6182 case MCC ('g', 'e'): return MCC ('l', 'e');
6183 case MCC ('l', 't'): return MCC ('g', 't');
6184 case MCC ('g', 't'): return MCC ('l', 't');
6185 case MCC ('l', 'e'): return MCC ('g', 'e');
6186 /* Issue a warning for conditions we can not swap. */
6187 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6188 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6189 case MCC ('v', 'c'):
6190 case MCC ('v', 's'):
6192 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6193 (char) (cc >> 8), (char) (cc));
6199 /* Reverse the sense of a condition. */
6202 reverse_mri_condition (int cc)
6206 case MCC ('h', 'i'): return MCC ('l', 's');
6207 case MCC ('l', 's'): return MCC ('h', 'i');
6208 /* <HS> is an alias for <CC> */
6209 case MCC ('h', 's'): return MCC ('l', 'o');
6210 case MCC ('c', 'c'): return MCC ('c', 's');
6211 /* <LO> is an alias for <CS> */
6212 case MCC ('l', 'o'): return MCC ('h', 's');
6213 case MCC ('c', 's'): return MCC ('c', 'c');
6214 case MCC ('n', 'e'): return MCC ('e', 'q');
6215 case MCC ('e', 'q'): return MCC ('n', 'e');
6216 case MCC ('v', 'c'): return MCC ('v', 's');
6217 case MCC ('v', 's'): return MCC ('v', 'c');
6218 case MCC ('p', 'l'): return MCC ('m', 'i');
6219 case MCC ('m', 'i'): return MCC ('p', 'l');
6220 case MCC ('g', 'e'): return MCC ('l', 't');
6221 case MCC ('l', 't'): return MCC ('g', 'e');
6222 case MCC ('g', 't'): return MCC ('l', 'e');
6223 case MCC ('l', 'e'): return MCC ('g', 't');
6228 /* Build an MRI structured control expression. This generates test
6229 and branch instructions. It goes to TRUELAB if the condition is
6230 true, and to FALSELAB if the condition is false. Exactly one of
6231 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6232 is the size qualifier for the expression. EXTENT is the size to
6233 use for the branch. */
6236 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6237 char *rightstart, char *rightstop,
6238 const char *truelab, const char *falselab,
6244 if (leftstart != NULL)
6246 struct m68k_op leftop, rightop;
6249 /* Swap the compare operands, if necessary, to produce a legal
6250 m68k compare instruction. Comparing a register operand with
6251 a non-register operand requires the register to be on the
6252 right (cmp, cmpa). Comparing an immediate value with
6253 anything requires the immediate value to be on the left
6258 (void) m68k_ip_op (leftstart, &leftop);
6263 (void) m68k_ip_op (rightstart, &rightop);
6266 if (rightop.mode == IMMED
6267 || ((leftop.mode == DREG || leftop.mode == AREG)
6268 && (rightop.mode != DREG && rightop.mode != AREG)))
6272 /* Correct conditional handling:
6273 if #1 <lt> d0 then ;means if (1 < d0)
6279 cmp #1,d0 if we do *not* swap the operands
6280 bgt true we need the swapped condition!
6287 leftstart = rightstart;
6290 leftstop = rightstop;
6295 cc = swap_mri_condition (cc);
6299 if (truelab == NULL)
6301 cc = reverse_mri_condition (cc);
6305 if (leftstart != NULL)
6307 buf = (char *) xmalloc (20
6308 + (leftstop - leftstart)
6309 + (rightstop - rightstart));
6315 *s++ = TOLOWER (qual);
6317 memcpy (s, leftstart, leftstop - leftstart);
6318 s += leftstop - leftstart;
6320 memcpy (s, rightstart, rightstop - rightstart);
6321 s += rightstop - rightstart;
6327 buf = (char *) xmalloc (20 + strlen (truelab));
6333 *s++ = TOLOWER (extent);
6335 strcpy (s, truelab);
6340 /* Parse an MRI structured control expression. This generates test
6341 and branch instructions. STOP is where the expression ends. It
6342 goes to TRUELAB if the condition is true, and to FALSELAB if the
6343 condition is false. Exactly one of TRUELAB and FALSELAB will be
6344 NULL, meaning to fall through. QUAL is the size qualifier for the
6345 expression. EXTENT is the size to use for the branch. */
6348 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6349 const char *falselab, int extent)
6361 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6362 &rightstart, &rightstop))
6368 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6372 if (falselab != NULL)
6375 flab = mri_control_label ();
6377 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6378 rightstop, (const char *) NULL, flab, extent);
6380 input_line_pointer += 3;
6381 if (*input_line_pointer != '.'
6382 || input_line_pointer[1] == '\0')
6386 qual = input_line_pointer[1];
6387 input_line_pointer += 2;
6390 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6391 &rightstart, &rightstop))
6397 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6398 rightstop, truelab, falselab, extent);
6400 if (falselab == NULL)
6403 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6407 if (truelab != NULL)
6410 tlab = mri_control_label ();
6412 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6413 rightstop, tlab, (const char *) NULL, extent);
6415 input_line_pointer += 2;
6416 if (*input_line_pointer != '.'
6417 || input_line_pointer[1] == '\0')
6421 qual = input_line_pointer[1];
6422 input_line_pointer += 2;
6425 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6426 &rightstart, &rightstop))
6432 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6433 rightstop, truelab, falselab, extent);
6435 if (truelab == NULL)
6440 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6441 rightstop, truelab, falselab, extent);
6445 if (input_line_pointer != stop)
6446 as_bad (_("syntax error in structured control directive"));
6449 /* Handle the MRI IF pseudo-op. This may be a structured control
6450 directive, or it may be a regular assembler conditional, depending
6458 struct mri_control_info *n;
6460 /* A structured control directive must end with THEN with an
6461 optional qualifier. */
6462 s = input_line_pointer;
6463 /* We only accept '*' as introduction of comments if preceded by white space
6464 or at first column of a line (I think this can't actually happen here?)
6465 This is important when assembling:
6466 if d0 <ne> 12(a0,d0*2) then
6467 if d0 <ne> #CONST*20 then. */
6468 while (! (is_end_of_line[(unsigned char) *s]
6471 && (s == input_line_pointer
6473 || *(s-1) == '\t'))))
6476 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6479 if (s - input_line_pointer > 1
6483 if (s - input_line_pointer < 3
6484 || strncasecmp (s - 3, "THEN", 4) != 0)
6488 as_bad (_("missing then"));
6489 ignore_rest_of_line ();
6493 /* It's a conditional. */
6498 /* Since this might be a conditional if, this pseudo-op will be
6499 called even if we are supported to be ignoring input. Double
6500 check now. Clobber *input_line_pointer so that ignore_input
6501 thinks that this is not a special pseudo-op. */
6502 c = *input_line_pointer;
6503 *input_line_pointer = 0;
6504 if (ignore_input ())
6506 *input_line_pointer = c;
6507 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6508 ++input_line_pointer;
6509 demand_empty_rest_of_line ();
6512 *input_line_pointer = c;
6514 n = push_mri_control (mri_if);
6516 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6517 n->next, s[1] == '.' ? s[2] : '\0');
6520 input_line_pointer = s + 3;
6522 input_line_pointer = s + 1;
6526 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6527 ++input_line_pointer;
6530 demand_empty_rest_of_line ();
6533 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6534 structured IF, associate the ELSE with the IF. Otherwise, assume
6535 it is a conditional else. */
6538 s_mri_else (int qual)
6545 && (mri_control_stack == NULL
6546 || mri_control_stack->type != mri_if
6547 || mri_control_stack->else_seen))
6553 c = *input_line_pointer;
6554 *input_line_pointer = 0;
6555 if (ignore_input ())
6557 *input_line_pointer = c;
6558 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6559 ++input_line_pointer;
6560 demand_empty_rest_of_line ();
6563 *input_line_pointer = c;
6565 if (mri_control_stack == NULL
6566 || mri_control_stack->type != mri_if
6567 || mri_control_stack->else_seen)
6569 as_bad (_("else without matching if"));
6570 ignore_rest_of_line ();
6574 mri_control_stack->else_seen = 1;
6576 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6577 q[0] = TOLOWER (qual);
6579 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6583 colon (mri_control_stack->next);
6587 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6588 ++input_line_pointer;
6591 demand_empty_rest_of_line ();
6594 /* Handle the MRI ENDI pseudo-op. */
6597 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6599 if (mri_control_stack == NULL
6600 || mri_control_stack->type != mri_if)
6602 as_bad (_("endi without matching if"));
6603 ignore_rest_of_line ();
6607 /* ignore_input will not return true for ENDI, so we don't need to
6608 worry about checking it again here. */
6610 if (! mri_control_stack->else_seen)
6611 colon (mri_control_stack->next);
6612 colon (mri_control_stack->bottom);
6618 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6619 ++input_line_pointer;
6622 demand_empty_rest_of_line ();
6625 /* Handle the MRI BREAK pseudo-op. */
6628 s_mri_break (int extent)
6630 struct mri_control_info *n;
6634 n = mri_control_stack;
6636 && n->type != mri_for
6637 && n->type != mri_repeat
6638 && n->type != mri_while)
6642 as_bad (_("break outside of structured loop"));
6643 ignore_rest_of_line ();
6647 buf = (char *) xmalloc (20 + strlen (n->bottom));
6648 ex[0] = TOLOWER (extent);
6650 sprintf (buf, "bra%s %s", ex, n->bottom);
6656 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6657 ++input_line_pointer;
6660 demand_empty_rest_of_line ();
6663 /* Handle the MRI NEXT pseudo-op. */
6666 s_mri_next (int extent)
6668 struct mri_control_info *n;
6672 n = mri_control_stack;
6674 && n->type != mri_for
6675 && n->type != mri_repeat
6676 && n->type != mri_while)
6680 as_bad (_("next outside of structured loop"));
6681 ignore_rest_of_line ();
6685 buf = (char *) xmalloc (20 + strlen (n->next));
6686 ex[0] = TOLOWER (extent);
6688 sprintf (buf, "bra%s %s", ex, n->next);
6694 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6695 ++input_line_pointer;
6698 demand_empty_rest_of_line ();
6701 /* Handle the MRI FOR pseudo-op. */
6704 s_mri_for (int qual)
6706 const char *varstart, *varstop;
6707 const char *initstart, *initstop;
6708 const char *endstart, *endstop;
6709 const char *bystart, *bystop;
6713 struct mri_control_info *n;
6719 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6723 varstart = input_line_pointer;
6725 /* Look for the '='. */
6726 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6727 && *input_line_pointer != '=')
6728 ++input_line_pointer;
6729 if (*input_line_pointer != '=')
6731 as_bad (_("missing ="));
6732 ignore_rest_of_line ();
6736 varstop = input_line_pointer;
6737 if (varstop > varstart
6738 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6741 ++input_line_pointer;
6743 initstart = input_line_pointer;
6745 /* Look for TO or DOWNTO. */
6748 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6750 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6751 && ! is_part_of_name (input_line_pointer[2]))
6753 initstop = input_line_pointer;
6754 input_line_pointer += 2;
6757 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6758 && ! is_part_of_name (input_line_pointer[6]))
6760 initstop = input_line_pointer;
6762 input_line_pointer += 6;
6765 ++input_line_pointer;
6767 if (initstop == NULL)
6769 as_bad (_("missing to or downto"));
6770 ignore_rest_of_line ();
6773 if (initstop > initstart
6774 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6778 endstart = input_line_pointer;
6780 /* Look for BY or DO. */
6783 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6785 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6786 && ! is_part_of_name (input_line_pointer[2]))
6788 endstop = input_line_pointer;
6790 input_line_pointer += 2;
6793 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6794 && (input_line_pointer[2] == '.'
6795 || ! is_part_of_name (input_line_pointer[2])))
6797 endstop = input_line_pointer;
6798 input_line_pointer += 2;
6801 ++input_line_pointer;
6803 if (endstop == NULL)
6805 as_bad (_("missing do"));
6806 ignore_rest_of_line ();
6809 if (endstop > endstart
6810 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6816 bystop = bystart + 2;
6821 bystart = input_line_pointer;
6825 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6827 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6828 && (input_line_pointer[2] == '.'
6829 || ! is_part_of_name (input_line_pointer[2])))
6831 bystop = input_line_pointer;
6832 input_line_pointer += 2;
6835 ++input_line_pointer;
6839 as_bad (_("missing do"));
6840 ignore_rest_of_line ();
6843 if (bystop > bystart
6844 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6848 if (*input_line_pointer != '.')
6852 extent = input_line_pointer[1];
6853 input_line_pointer += 2;
6856 /* We have fully parsed the FOR operands. Now build the loop. */
6857 n = push_mri_control (mri_for);
6859 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6861 /* Move init,var. */
6868 *s++ = TOLOWER (qual);
6870 memcpy (s, initstart, initstop - initstart);
6871 s += initstop - initstart;
6873 memcpy (s, varstart, varstop - varstart);
6874 s += varstop - varstart;
6886 *s++ = TOLOWER (qual);
6888 memcpy (s, endstart, endstop - endstart);
6889 s += endstop - endstart;
6891 memcpy (s, varstart, varstop - varstart);
6892 s += varstop - varstart;
6897 ex[0] = TOLOWER (extent);
6900 sprintf (buf, "blt%s %s", ex, n->bottom);
6902 sprintf (buf, "bgt%s %s", ex, n->bottom);
6905 /* Put together the add or sub instruction used by ENDF. */
6913 *s++ = TOLOWER (qual);
6915 memcpy (s, bystart, bystop - bystart);
6916 s += bystop - bystart;
6918 memcpy (s, varstart, varstop - varstart);
6919 s += varstop - varstart;
6925 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6926 ++input_line_pointer;
6929 demand_empty_rest_of_line ();
6932 /* Handle the MRI ENDF pseudo-op. */
6935 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6937 if (mri_control_stack == NULL
6938 || mri_control_stack->type != mri_for)
6940 as_bad (_("endf without for"));
6941 ignore_rest_of_line ();
6945 colon (mri_control_stack->next);
6947 mri_assemble (mri_control_stack->incr);
6949 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6950 mri_assemble (mri_control_stack->incr);
6952 free (mri_control_stack->incr);
6954 colon (mri_control_stack->bottom);
6960 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6961 ++input_line_pointer;
6964 demand_empty_rest_of_line ();
6967 /* Handle the MRI REPEAT pseudo-op. */
6970 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6972 struct mri_control_info *n;
6974 n = push_mri_control (mri_repeat);
6978 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6979 ++input_line_pointer;
6981 demand_empty_rest_of_line ();
6984 /* Handle the MRI UNTIL pseudo-op. */
6987 s_mri_until (int qual)
6991 if (mri_control_stack == NULL
6992 || mri_control_stack->type != mri_repeat)
6994 as_bad (_("until without repeat"));
6995 ignore_rest_of_line ();
6999 colon (mri_control_stack->next);
7001 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7004 parse_mri_control_expression (s, qual, (const char *) NULL,
7005 mri_control_stack->top, '\0');
7007 colon (mri_control_stack->bottom);
7009 input_line_pointer = s;
7015 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7016 ++input_line_pointer;
7019 demand_empty_rest_of_line ();
7022 /* Handle the MRI WHILE pseudo-op. */
7025 s_mri_while (int qual)
7029 struct mri_control_info *n;
7031 s = input_line_pointer;
7032 /* We only accept '*' as introduction of comments if preceded by white space
7033 or at first column of a line (I think this can't actually happen here?)
7034 This is important when assembling:
7035 while d0 <ne> 12(a0,d0*2) do
7036 while d0 <ne> #CONST*20 do. */
7037 while (! (is_end_of_line[(unsigned char) *s]
7040 && (s == input_line_pointer
7042 || *(s-1) == '\t'))))
7045 while (*s == ' ' || *s == '\t')
7047 if (s - input_line_pointer > 1
7050 if (s - input_line_pointer < 2
7051 || strncasecmp (s - 1, "DO", 2) != 0)
7053 as_bad (_("missing do"));
7054 ignore_rest_of_line ();
7058 n = push_mri_control (mri_while);
7062 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7063 s[1] == '.' ? s[2] : '\0');
7065 input_line_pointer = s + 1;
7066 if (*input_line_pointer == '.')
7067 input_line_pointer += 2;
7071 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7072 ++input_line_pointer;
7075 demand_empty_rest_of_line ();
7078 /* Handle the MRI ENDW pseudo-op. */
7081 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7085 if (mri_control_stack == NULL
7086 || mri_control_stack->type != mri_while)
7088 as_bad (_("endw without while"));
7089 ignore_rest_of_line ();
7093 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7094 sprintf (buf, "bra %s", mri_control_stack->next);
7098 colon (mri_control_stack->bottom);
7104 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7105 ++input_line_pointer;
7108 demand_empty_rest_of_line ();
7111 /* Parse a .cpu directive. */
7114 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7121 as_bad (_("already assembled instructions"));
7122 ignore_rest_of_line ();
7126 name = input_line_pointer;
7127 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7128 input_line_pointer++;
7129 saved_char = *input_line_pointer;
7130 *input_line_pointer = 0;
7132 m68k_set_cpu (name, 1, 0);
7134 *input_line_pointer = saved_char;
7135 demand_empty_rest_of_line ();
7139 /* Parse a .arch directive. */
7142 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7149 as_bad (_("already assembled instructions"));
7150 ignore_rest_of_line ();
7154 name = input_line_pointer;
7155 while (*input_line_pointer && *input_line_pointer != ','
7156 && !ISSPACE (*input_line_pointer))
7157 input_line_pointer++;
7158 saved_char = *input_line_pointer;
7159 *input_line_pointer = 0;
7161 if (m68k_set_arch (name, 1, 0))
7163 /* Scan extensions. */
7166 *input_line_pointer++ = saved_char;
7167 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7169 name = input_line_pointer;
7170 while (*input_line_pointer && *input_line_pointer != ','
7171 && !ISSPACE (*input_line_pointer))
7172 input_line_pointer++;
7173 saved_char = *input_line_pointer;
7174 *input_line_pointer = 0;
7176 while (m68k_set_extension (name, 1, 0));
7179 *input_line_pointer = saved_char;
7180 demand_empty_rest_of_line ();
7184 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7185 if none is found, the caller is responsible for emitting an error
7186 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7187 cpu name, if it begins with a '6' (possibly skipping an intervening
7188 'c'. We also allow a 'c' in the same place. if NEGATED is
7189 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7190 the option is indeed negated. */
7192 static const struct m68k_cpu *
7193 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7194 int allow_m, int *negated)
7196 /* allow negated value? */
7201 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7208 /* Remove 'm' or 'mc' prefix from 68k variants. */
7215 else if (arg[1] == 'c' && arg[2] == '6')
7219 else if (arg[0] == 'c' && arg[1] == '6')
7222 for (; table->name; table++)
7223 if (!strcmp (arg, table->name))
7225 if (table->alias < -1 || table->alias > 1)
7226 as_bad (_("`%s' is deprecated, use `%s'"),
7227 table->name, table[table->alias < 0 ? 1 : -1].name);
7233 /* Set the cpu, issuing errors if it is unrecognized. */
7236 m68k_set_cpu (char const *name, int allow_m, int silent)
7238 const struct m68k_cpu *cpu;
7240 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7245 as_bad (_("cpu `%s' unrecognized"), name);
7252 /* Set the architecture, issuing errors if it is unrecognized. */
7255 m68k_set_arch (char const *name, int allow_m, int silent)
7257 const struct m68k_cpu *arch;
7259 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7264 as_bad (_("architecture `%s' unrecognized"), name);
7267 selected_arch = arch;
7271 /* Set the architecture extension, issuing errors if it is
7272 unrecognized, or invalid */
7275 m68k_set_extension (char const *name, int allow_m, int silent)
7278 const struct m68k_cpu *ext;
7280 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7285 as_bad (_("extension `%s' unrecognized"), name);
7290 not_current_architecture |= ext->arch;
7292 current_architecture |= ext->arch;
7297 Invocation line includes a switch not recognized by the base assembler.
7301 const char *md_shortopts = "lSA:m:kQ:V";
7303 const char *md_shortopts = "lSA:m:k";
7306 struct option md_longopts[] = {
7307 #define OPTION_PIC (OPTION_MD_BASE)
7308 {"pic", no_argument, NULL, OPTION_PIC},
7309 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7310 {"register-prefix-optional", no_argument, NULL,
7311 OPTION_REGISTER_PREFIX_OPTIONAL},
7312 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7313 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7314 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7315 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7316 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7317 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7318 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7319 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7320 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7321 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7322 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7323 {"pcrel", no_argument, NULL, OPTION_PCREL},
7324 {NULL, no_argument, NULL, 0}
7326 size_t md_longopts_size = sizeof (md_longopts);
7329 md_parse_option (int c, char *arg)
7333 case 'l': /* -l means keep external to 2 bit offset
7334 rather than 16 bit one. */
7335 flag_short_refs = 1;
7338 case 'S': /* -S means that jbsr's always turn into
7340 flag_long_jumps = 1;
7343 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7344 branches into absolute jumps. */
7345 flag_keep_pcrel = 1;
7351 break; /* -pic, Position Independent Code. */
7353 case OPTION_REGISTER_PREFIX_OPTIONAL:
7354 flag_reg_prefix_optional = 1;
7355 reg_prefix_optional_seen = 1;
7358 /* -V: SVR4 argument to print version ID. */
7360 print_version_id ();
7363 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7364 should be emitted or not. FIXME: Not implemented. */
7368 case OPTION_BITWISE_OR:
7373 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7375 for (s = m68k_comment_chars; *s != '\0'; s++)
7379 m68k_comment_chars = n;
7383 case OPTION_BASE_SIZE_DEFAULT_16:
7384 m68k_index_width_default = SIZE_WORD;
7387 case OPTION_BASE_SIZE_DEFAULT_32:
7388 m68k_index_width_default = SIZE_LONG;
7391 case OPTION_DISP_SIZE_DEFAULT_16:
7393 m68k_rel32_from_cmdline = 1;
7396 case OPTION_DISP_SIZE_DEFAULT_32:
7398 m68k_rel32_from_cmdline = 1;
7403 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7406 /* Intentional fall-through. */
7408 if (!strncmp (arg, "arch=", 5))
7409 m68k_set_arch (arg + 5, 1, 0);
7410 else if (!strncmp (arg, "cpu=", 4))
7411 m68k_set_cpu (arg + 4, 1, 0);
7412 else if (m68k_set_extension (arg, 0, 1))
7414 else if (m68k_set_arch (arg, 0, 1))
7416 else if (m68k_set_cpu (arg, 0, 1))
7429 /* Setup tables from the selected arch and/or cpu */
7432 m68k_init_arch (void)
7434 if (not_current_architecture & current_architecture)
7436 as_bad (_("architecture features both enabled and disabled"));
7437 not_current_architecture &= ~current_architecture;
7441 current_architecture |= selected_arch->arch;
7442 control_regs = selected_arch->control_regs;
7445 current_architecture |= selected_cpu->arch;
7447 current_architecture &= ~not_current_architecture;
7449 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7451 /* Determine which float is really meant. */
7452 if (current_architecture & (m68k_mask & ~m68881))
7453 current_architecture ^= cfloat;
7455 current_architecture ^= m68881;
7460 control_regs = selected_cpu->control_regs;
7461 if (current_architecture & ~selected_cpu->arch)
7463 as_bad (_("selected processor does not have all features of selected architecture"));
7464 current_architecture
7465 = selected_cpu->arch & ~not_current_architecture;
7469 if ((current_architecture & m68k_mask)
7470 && (current_architecture & ~m68k_mask))
7472 as_bad (_ ("m68k and cf features both selected"));
7473 if (current_architecture & m68k_mask)
7474 current_architecture &= m68k_mask;
7476 current_architecture &= ~m68k_mask;
7479 /* Permit m68881 specification with all cpus; those that can't work
7480 with a coprocessor could be doing emulation. */
7481 if (current_architecture & m68851)
7483 if (current_architecture & m68040)
7484 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7486 /* What other incompatibilities could we check for? */
7488 if (cpu_of_arch (current_architecture) < m68020
7489 || arch_coldfire_p (current_architecture))
7490 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7496 md_show_usage (FILE *stream)
7498 const char *default_cpu = TARGET_CPU;
7500 unsigned int default_arch;
7502 /* Get the canonical name for the default target CPU. */
7503 if (*default_cpu == 'm')
7505 for (i = 0; m68k_cpus[i].name; i++)
7507 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7509 default_arch = m68k_cpus[i].arch;
7510 while (m68k_cpus[i].alias > 0)
7512 while (m68k_cpus[i].alias < 0)
7514 default_cpu = m68k_cpus[i].name;
7518 fprintf (stream, _("\
7519 -march=<arch> set architecture\n\
7520 -mcpu=<cpu> set cpu [default %s]\n\
7522 for (i = 0; m68k_extensions[i].name; i++)
7523 fprintf (stream, _("\
7524 -m[no-]%-16s enable/disable%s architecture extension\n\
7525 "), m68k_extensions[i].name,
7526 m68k_extensions[i].alias > 0 ? " ColdFire"
7527 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7529 fprintf (stream, _("\
7530 -l use 1 word for refs to undefined symbols [default 2]\n\
7531 -pic, -k generate position independent code\n\
7532 -S turn jbsr into jsr\n\
7533 --pcrel never turn PC-relative branches into absolute jumps\n\
7534 --register-prefix-optional\n\
7535 recognize register names without prefix character\n\
7536 --bitwise-or do not treat `|' as a comment character\n\
7537 --base-size-default-16 base reg without size is 16 bits\n\
7538 --base-size-default-32 base reg without size is 32 bits (default)\n\
7539 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7540 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7543 fprintf (stream, _("Architecture variants are: "));
7544 for (i = 0; m68k_archs[i].name; i++)
7547 fprintf (stream, " | ");
7548 fprintf (stream, m68k_archs[i].name);
7550 fprintf (stream, "\n");
7552 fprintf (stream, _("Processor variants are: "));
7553 for (i = 0; m68k_cpus[i].name; i++)
7556 fprintf (stream, " | ");
7557 fprintf (stream, m68k_cpus[i].name);
7559 fprintf (stream, _("\n"));
7564 /* TEST2: Test md_assemble() */
7565 /* Warning, this routine probably doesn't work anymore. */
7569 struct m68k_it the_ins;
7577 if (!gets (buf) || !*buf)
7579 if (buf[0] == '|' || buf[1] == '.')
7581 for (cp = buf; *cp; cp++)
7586 memset (&the_ins, '\0', sizeof (the_ins));
7587 m68k_ip (&the_ins, buf);
7590 printf (_("Error %s in %s\n"), the_ins.error, buf);
7594 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7595 for (n = 0; n < the_ins.numo; n++)
7596 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7598 print_the_insn (&the_ins.opcode[0], stdout);
7599 (void) putchar ('\n');
7601 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7603 if (the_ins.operands[n].error)
7605 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7608 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7609 the_ins.operands[n].reg);
7610 if (the_ins.operands[n].b_const)
7611 printf ("Constant: '%.*s', ",
7612 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7613 the_ins.operands[n].b_const);
7614 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7615 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7616 if (the_ins.operands[n].b_iadd)
7617 printf ("Iadd: '%.*s',",
7618 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7619 the_ins.operands[n].b_iadd);
7628 is_label (char *str)
7632 while (*str && *str != ' ')
7634 if (str[-1] == ':' || str[1] == '=')
7641 /* Possible states for relaxation:
7643 0 0 branch offset byte (bra, etc)
7647 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7651 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7658 /* We have no need to default values of symbols. */
7661 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7666 /* Round up a section size to the appropriate boundary. */
7668 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7671 /* For a.out, force the section size to be aligned. If we don't do
7672 this, BFD will align it for us, but it will not write out the
7673 final bytes of the section. This may be a bug in BFD, but it is
7674 easier to fix it here since that is how the other a.out targets
7678 align = bfd_get_section_alignment (stdoutput, segment);
7679 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7685 /* Exactly what point is a PC-relative offset relative TO?
7686 On the 68k, it is relative to the address of the first extension
7687 word. The difference between the addresses of the offset and the
7688 first extension word is stored in fx_pcrel_adjust. */
7690 md_pcrel_from (fixS *fixP)
7694 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7695 sign extend the value here. */
7696 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7699 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7704 m68k_elf_final_processing (void)
7708 if (arch_coldfire_fpu (current_architecture))
7709 flags |= EF_M68K_CFV4E;
7710 /* Set file-specific flags if this is a cpu32 processor. */
7711 if (cpu_of_arch (current_architecture) & cpu32)
7712 flags |= EF_M68K_CPU32;
7713 else if (cpu_of_arch (current_architecture) & fido_a)
7714 flags |= EF_M68K_FIDO;
7715 else if ((cpu_of_arch (current_architecture) & m68000up)
7716 && !(cpu_of_arch (current_architecture) & m68020up))
7717 flags |= EF_M68K_M68000;
7719 if (current_architecture & mcfisa_a)
7721 static const unsigned isa_features[][2] =
7723 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7724 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7725 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7726 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7727 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7728 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7729 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7732 static const unsigned mac_features[][2] =
7734 {EF_M68K_CF_MAC, mcfmac},
7735 {EF_M68K_CF_EMAC, mcfemac},
7741 pattern = (current_architecture
7742 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7743 for (ix = 0; isa_features[ix][1]; ix++)
7745 if (pattern == isa_features[ix][1])
7747 flags |= isa_features[ix][0];
7751 if (!isa_features[ix][1])
7754 as_warn (_("Not a defined coldfire architecture"));
7758 if (current_architecture & cfloat)
7759 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7761 pattern = current_architecture & (mcfmac|mcfemac);
7764 for (ix = 0; mac_features[ix][1]; ix++)
7766 if (pattern == mac_features[ix][1])
7768 flags |= mac_features[ix][0];
7772 if (!mac_features[ix][1])
7777 elf_elfheader (stdoutput)->e_flags |= flags;
7782 tc_m68k_regname_to_dw2regnum (char *regname)
7784 unsigned int regnum;
7785 static const char *const regnames[] =
7787 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7788 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7789 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7793 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7794 if (strcmp (regname, regnames[regnum]) == 0)
7801 tc_m68k_frame_initial_instructions (void)
7803 static int sp_regno = -1;
7806 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7808 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7809 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);