1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32 = -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32 = -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float = 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float = 0;
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG,
296 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
298 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask;
305 unsigned long mips_cprmask[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa = ISA_UNKNOWN;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2)
355 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
357 /* True if -mdspr2 was passed or implied by arguments passed on the
358 command line (e.g., by -march). */
359 static int file_ase_dspr2;
361 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
362 || mips_opts.isa == ISA_MIPS64R2)
364 /* True if -mmt was passed or implied by arguments passed on the
365 command line (e.g., by -march). */
366 static int file_ase_mt;
368 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
369 || mips_opts.isa == ISA_MIPS64R2)
371 /* The argument of the -march= flag. The architecture we are assembling. */
372 static int file_mips_arch = CPU_UNKNOWN;
373 static const char *mips_arch_string;
375 /* The argument of the -mtune= flag. The architecture for which we
377 static int mips_tune = CPU_UNKNOWN;
378 static const char *mips_tune_string;
380 /* True when generating 32-bit code for a 64-bit processor. */
381 static int mips_32bitmode = 0;
383 /* True if the given ABI requires 32-bit registers. */
384 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
386 /* Likewise 64-bit registers. */
387 #define ABI_NEEDS_64BIT_REGS(ABI) \
389 || (ABI) == N64_ABI \
392 /* Return true if ISA supports 64 bit wide gp registers. */
393 #define ISA_HAS_64BIT_REGS(ISA) \
394 ((ISA) == ISA_MIPS3 \
395 || (ISA) == ISA_MIPS4 \
396 || (ISA) == ISA_MIPS5 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports 64 bit wide float registers. */
401 #define ISA_HAS_64BIT_FPRS(ISA) \
402 ((ISA) == ISA_MIPS3 \
403 || (ISA) == ISA_MIPS4 \
404 || (ISA) == ISA_MIPS5 \
405 || (ISA) == ISA_MIPS32R2 \
406 || (ISA) == ISA_MIPS64 \
407 || (ISA) == ISA_MIPS64R2)
409 /* Return true if ISA supports 64-bit right rotate (dror et al.)
411 #define ISA_HAS_DROR(ISA) \
412 ((ISA) == ISA_MIPS64R2 \
413 || (mips_opts.micromips \
414 && ISA_HAS_64BIT_REGS (ISA)) \
417 /* Return true if ISA supports 32-bit right rotate (ror et al.)
419 #define ISA_HAS_ROR(ISA) \
420 ((ISA) == ISA_MIPS32R2 \
421 || (ISA) == ISA_MIPS64R2 \
422 || mips_opts.ase_smartmips \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
428 ((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS64 \
431 || (ISA) == ISA_MIPS64R2)
433 /* Return true if ISA supports move to/from high part of a 64-bit
434 floating-point register. */
435 #define ISA_HAS_MXHC1(ISA) \
436 ((ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64R2)
439 #define HAVE_32BIT_GPRS \
440 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
442 #define HAVE_32BIT_FPRS \
443 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
445 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
446 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
448 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
450 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
452 /* True if relocations are stored in-place. */
453 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
455 /* The ABI-derived address size. */
456 #define HAVE_64BIT_ADDRESSES \
457 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
458 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
460 /* The size of symbolic constants (i.e., expressions of the form
461 "SYMBOL" or "SYMBOL + OFFSET"). */
462 #define HAVE_32BIT_SYMBOLS \
463 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
464 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
466 /* Addresses are loaded in different ways, depending on the address size
467 in use. The n32 ABI Documentation also mandates the use of additions
468 with overflow checking, but existing implementations don't follow it. */
469 #define ADDRESS_ADD_INSN \
470 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
472 #define ADDRESS_ADDI_INSN \
473 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
475 #define ADDRESS_LOAD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
478 #define ADDRESS_STORE_INSN \
479 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
481 /* Return true if the given CPU supports the MIPS16 ASE. */
482 #define CPU_HAS_MIPS16(cpu) \
483 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
484 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
486 /* Return true if the given CPU supports the microMIPS ASE. */
487 #define CPU_HAS_MICROMIPS(cpu) 0
489 /* True if CPU has a dror instruction. */
490 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
492 /* True if CPU has a ror instruction. */
493 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
495 /* True if CPU has seq/sne and seqi/snei instructions. */
496 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
498 /* True if CPU does not implement the all the coprocessor insns. For these
499 CPUs only those COP insns are accepted that are explicitly marked to be
500 available on the CPU. ISA membership for COP insns is ignored. */
501 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Returns true for a (non floating-point) coprocessor instruction. Reading
574 or writing the condition code is only possible on the coprocessors and
575 these insns are not marked with INSN_COP. Thus for these insns use the
576 condition-code flags. */
577 #define COP_INSN(PINFO) \
578 (PINFO != INSN_MACRO \
579 && ((PINFO) & (FP_S | FP_D)) == 0 \
580 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
582 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
583 has been selected. This implies, in particular, that addresses of text
584 labels have their LSB set. */
585 #define HAVE_CODE_COMPRESSION \
586 ((mips_opts.mips16 | mips_opts.micromips) != 0)
588 /* MIPS PIC level. */
590 enum mips_pic_level mips_pic;
592 /* 1 if we should generate 32 bit offsets from the $gp register in
593 SVR4_PIC mode. Currently has no meaning in other modes. */
594 static int mips_big_got = 0;
596 /* 1 if trap instructions should used for overflow rather than break
598 static int mips_trap = 0;
600 /* 1 if double width floating point constants should not be constructed
601 by assembling two single width halves into two single width floating
602 point registers which just happen to alias the double width destination
603 register. On some architectures this aliasing can be disabled by a bit
604 in the status register, and the setting of this bit cannot be determined
605 automatically at assemble time. */
606 static int mips_disable_float_construction;
608 /* Non-zero if any .set noreorder directives were used. */
610 static int mips_any_noreorder;
612 /* Non-zero if nops should be inserted when the register referenced in
613 an mfhi/mflo instruction is read in the next two instructions. */
614 static int mips_7000_hilo_fix;
616 /* The size of objects in the small data section. */
617 static unsigned int g_switch_value = 8;
618 /* Whether the -G option was used. */
619 static int g_switch_seen = 0;
624 /* If we can determine in advance that GP optimization won't be
625 possible, we can skip the relaxation stuff that tries to produce
626 GP-relative references. This makes delay slot optimization work
629 This function can only provide a guess, but it seems to work for
630 gcc output. It needs to guess right for gcc, otherwise gcc
631 will put what it thinks is a GP-relative instruction in a branch
634 I don't know if a fix is needed for the SVR4_PIC mode. I've only
635 fixed it for the non-PIC mode. KR 95/04/07 */
636 static int nopic_need_relax (symbolS *, int);
638 /* handle of the OPCODE hash table */
639 static struct hash_control *op_hash = NULL;
641 /* The opcode hash table we use for the mips16. */
642 static struct hash_control *mips16_op_hash = NULL;
644 /* The opcode hash table we use for the microMIPS ASE. */
645 static struct hash_control *micromips_op_hash = NULL;
647 /* This array holds the chars that always start a comment. If the
648 pre-processor is disabled, these aren't very useful */
649 const char comment_chars[] = "#";
651 /* This array holds the chars that only start a comment at the beginning of
652 a line. If the line seems to have the form '# 123 filename'
653 .line and .file directives will appear in the pre-processed output */
654 /* Note that input_file.c hand checks for '#' at the beginning of the
655 first line of the input file. This is because the compiler outputs
656 #NO_APP at the beginning of its output. */
657 /* Also note that C style comments are always supported. */
658 const char line_comment_chars[] = "#";
660 /* This array holds machine specific line separator characters. */
661 const char line_separator_chars[] = ";";
663 /* Chars that can be used to separate mant from exp in floating point nums */
664 const char EXP_CHARS[] = "eE";
666 /* Chars that mean this number is a floating point constant */
669 const char FLT_CHARS[] = "rRsSfFdDxXpP";
671 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
672 changed in read.c . Ideally it shouldn't have to know about it at all,
673 but nothing is ideal around here.
676 static char *insn_error;
678 static int auto_align = 1;
680 /* When outputting SVR4 PIC code, the assembler needs to know the
681 offset in the stack frame from which to restore the $gp register.
682 This is set by the .cprestore pseudo-op, and saved in this
684 static offsetT mips_cprestore_offset = -1;
686 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
687 more optimizations, it can use a register value instead of a memory-saved
688 offset and even an other register than $gp as global pointer. */
689 static offsetT mips_cpreturn_offset = -1;
690 static int mips_cpreturn_register = -1;
691 static int mips_gp_register = GP;
692 static int mips_gprel_offset = 0;
694 /* Whether mips_cprestore_offset has been set in the current function
695 (or whether it has already been warned about, if not). */
696 static int mips_cprestore_valid = 0;
698 /* This is the register which holds the stack frame, as set by the
699 .frame pseudo-op. This is needed to implement .cprestore. */
700 static int mips_frame_reg = SP;
702 /* Whether mips_frame_reg has been set in the current function
703 (or whether it has already been warned about, if not). */
704 static int mips_frame_reg_valid = 0;
706 /* To output NOP instructions correctly, we need to keep information
707 about the previous two instructions. */
709 /* Whether we are optimizing. The default value of 2 means to remove
710 unneeded NOPs and swap branch instructions when possible. A value
711 of 1 means to not swap branches. A value of 0 means to always
713 static int mips_optimize = 2;
715 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
716 equivalent to seeing no -g option at all. */
717 static int mips_debug = 0;
719 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
720 #define MAX_VR4130_NOPS 4
722 /* The maximum number of NOPs needed to fill delay slots. */
723 #define MAX_DELAY_NOPS 2
725 /* The maximum number of NOPs needed for any purpose. */
728 /* A list of previous instructions, with index 0 being the most recent.
729 We need to look back MAX_NOPS instructions when filling delay slots
730 or working around processor errata. We need to look back one
731 instruction further if we're thinking about using history[0] to
732 fill a branch delay slot. */
733 static struct mips_cl_insn history[1 + MAX_NOPS];
735 /* Nop instructions used by emit_nop. */
736 static struct mips_cl_insn nop_insn;
737 static struct mips_cl_insn mips16_nop_insn;
738 static struct mips_cl_insn micromips_nop16_insn;
739 static struct mips_cl_insn micromips_nop32_insn;
741 /* The appropriate nop for the current mode. */
742 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
743 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
745 /* The size of NOP_INSN in bytes. */
746 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
748 /* If this is set, it points to a frag holding nop instructions which
749 were inserted before the start of a noreorder section. If those
750 nops turn out to be unnecessary, the size of the frag can be
752 static fragS *prev_nop_frag;
754 /* The number of nop instructions we created in prev_nop_frag. */
755 static int prev_nop_frag_holds;
757 /* The number of nop instructions that we know we need in
759 static int prev_nop_frag_required;
761 /* The number of instructions we've seen since prev_nop_frag. */
762 static int prev_nop_frag_since;
764 /* For ECOFF and ELF, relocations against symbols are done in two
765 parts, with a HI relocation and a LO relocation. Each relocation
766 has only 16 bits of space to store an addend. This means that in
767 order for the linker to handle carries correctly, it must be able
768 to locate both the HI and the LO relocation. This means that the
769 relocations must appear in order in the relocation table.
771 In order to implement this, we keep track of each unmatched HI
772 relocation. We then sort them so that they immediately precede the
773 corresponding LO relocation. */
778 struct mips_hi_fixup *next;
781 /* The section this fixup is in. */
785 /* The list of unmatched HI relocs. */
787 static struct mips_hi_fixup *mips_hi_fixup_list;
789 /* The frag containing the last explicit relocation operator.
790 Null if explicit relocations have not been used. */
792 static fragS *prev_reloc_op_frag;
794 /* Map normal MIPS register numbers to mips16 register numbers. */
796 #define X ILLEGAL_REG
797 static const int mips32_to_16_reg_map[] =
799 X, X, 2, 3, 4, 5, 6, 7,
800 X, X, X, X, X, X, X, X,
801 0, 1, X, X, X, X, X, X,
802 X, X, X, X, X, X, X, X
806 /* Map mips16 register numbers to normal MIPS register numbers. */
808 static const unsigned int mips16_to_32_reg_map[] =
810 16, 17, 2, 3, 4, 5, 6, 7
813 /* Map normal MIPS register numbers to microMIPS register numbers. */
815 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
823 #define X ILLEGAL_REG
824 /* reg type h: 4, 5, 6. */
825 static const int mips32_to_micromips_reg_h_map[] =
827 X, X, X, X, 4, 5, 6, X,
828 X, X, X, X, X, X, X, X,
829 X, X, X, X, X, X, X, X,
830 X, X, X, X, X, X, X, X
833 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
834 static const int mips32_to_micromips_reg_m_map[] =
836 0, X, 2, 3, X, X, X, X,
837 X, X, X, X, X, X, X, X,
838 4, 1, 5, 6, 7, X, X, X,
839 X, X, X, X, X, X, X, X
842 /* reg type q: 0, 2-7. 17. */
843 static const int mips32_to_micromips_reg_q_map[] =
845 0, X, 2, 3, 4, 5, 6, 7,
846 X, X, X, X, X, X, X, X,
847 X, 1, X, X, X, X, X, X,
848 X, X, X, X, X, X, X, X
851 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
854 /* Map microMIPS register numbers to normal MIPS register numbers. */
856 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
863 /* The microMIPS registers with type h. */
864 static const unsigned int micromips_to_32_reg_h_map[] =
866 5, 5, 6, 4, 4, 4, 4, 4
869 /* The microMIPS registers with type i. */
870 static const unsigned int micromips_to_32_reg_i_map[] =
872 6, 7, 7, 21, 22, 5, 6, 7
875 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
877 /* The microMIPS registers with type m. */
878 static const unsigned int micromips_to_32_reg_m_map[] =
880 0, 17, 2, 3, 16, 18, 19, 20
883 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
885 /* The microMIPS registers with type q. */
886 static const unsigned int micromips_to_32_reg_q_map[] =
888 0, 17, 2, 3, 4, 5, 6, 7
891 /* microMIPS imm type B. */
892 static const int micromips_imm_b_map[] =
894 1, 4, 8, 12, 16, 20, 24, -1
897 /* microMIPS imm type C. */
898 static const int micromips_imm_c_map[] =
900 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
903 /* Classifies the kind of instructions we're interested in when
904 implementing -mfix-vr4120. */
905 enum fix_vr4120_class
913 NUM_FIX_VR4120_CLASSES
916 /* ...likewise -mfix-loongson2f-jump. */
917 static bfd_boolean mips_fix_loongson2f_jump;
919 /* ...likewise -mfix-loongson2f-nop. */
920 static bfd_boolean mips_fix_loongson2f_nop;
922 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
923 static bfd_boolean mips_fix_loongson2f;
925 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
926 there must be at least one other instruction between an instruction
927 of type X and an instruction of type Y. */
928 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
930 /* True if -mfix-vr4120 is in force. */
931 static int mips_fix_vr4120;
933 /* ...likewise -mfix-vr4130. */
934 static int mips_fix_vr4130;
936 /* ...likewise -mfix-24k. */
937 static int mips_fix_24k;
939 /* ...likewise -mfix-cn63xxp1 */
940 static bfd_boolean mips_fix_cn63xxp1;
942 /* We don't relax branches by default, since this causes us to expand
943 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
944 fail to compute the offset before expanding the macro to the most
945 efficient expansion. */
947 static int mips_relax_branch;
949 /* The expansion of many macros depends on the type of symbol that
950 they refer to. For example, when generating position-dependent code,
951 a macro that refers to a symbol may have two different expansions,
952 one which uses GP-relative addresses and one which uses absolute
953 addresses. When generating SVR4-style PIC, a macro may have
954 different expansions for local and global symbols.
956 We handle these situations by generating both sequences and putting
957 them in variant frags. In position-dependent code, the first sequence
958 will be the GP-relative one and the second sequence will be the
959 absolute one. In SVR4 PIC, the first sequence will be for global
960 symbols and the second will be for local symbols.
962 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
963 SECOND are the lengths of the two sequences in bytes. These fields
964 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
965 the subtype has the following flags:
968 Set if it has been decided that we should use the second
969 sequence instead of the first.
972 Set in the first variant frag if the macro's second implementation
973 is longer than its first. This refers to the macro as a whole,
974 not an individual relaxation.
977 Set in the first variant frag if the macro appeared in a .set nomacro
978 block and if one alternative requires a warning but the other does not.
981 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
984 RELAX_DELAY_SLOT_16BIT
985 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
988 RELAX_DELAY_SLOT_SIZE_FIRST
989 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
990 the macro is of the wrong size for the branch delay slot.
992 RELAX_DELAY_SLOT_SIZE_SECOND
993 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
994 the macro is of the wrong size for the branch delay slot.
996 The frag's "opcode" points to the first fixup for relaxable code.
998 Relaxable macros are generated using a sequence such as:
1000 relax_start (SYMBOL);
1001 ... generate first expansion ...
1003 ... generate second expansion ...
1006 The code and fixups for the unwanted alternative are discarded
1007 by md_convert_frag. */
1008 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1010 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1011 #define RELAX_SECOND(X) ((X) & 0xff)
1012 #define RELAX_USE_SECOND 0x10000
1013 #define RELAX_SECOND_LONGER 0x20000
1014 #define RELAX_NOMACRO 0x40000
1015 #define RELAX_DELAY_SLOT 0x80000
1016 #define RELAX_DELAY_SLOT_16BIT 0x100000
1017 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1018 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1020 /* Branch without likely bit. If label is out of range, we turn:
1022 beq reg1, reg2, label
1032 with the following opcode replacements:
1039 bltzal <-> bgezal (with jal label instead of j label)
1041 Even though keeping the delay slot instruction in the delay slot of
1042 the branch would be more efficient, it would be very tricky to do
1043 correctly, because we'd have to introduce a variable frag *after*
1044 the delay slot instruction, and expand that instead. Let's do it
1045 the easy way for now, even if the branch-not-taken case now costs
1046 one additional instruction. Out-of-range branches are not supposed
1047 to be common, anyway.
1049 Branch likely. If label is out of range, we turn:
1051 beql reg1, reg2, label
1052 delay slot (annulled if branch not taken)
1061 delay slot (executed only if branch taken)
1064 It would be possible to generate a shorter sequence by losing the
1065 likely bit, generating something like:
1070 delay slot (executed only if branch taken)
1082 bltzall -> bgezal (with jal label instead of j label)
1083 bgezall -> bltzal (ditto)
1086 but it's not clear that it would actually improve performance. */
1087 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1088 ((relax_substateT) \
1091 | ((toofar) ? 0x20 : 0) \
1092 | ((link) ? 0x40 : 0) \
1093 | ((likely) ? 0x80 : 0) \
1094 | ((uncond) ? 0x100 : 0)))
1095 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1096 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1097 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1098 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1099 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1100 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1102 /* For mips16 code, we use an entirely different form of relaxation.
1103 mips16 supports two versions of most instructions which take
1104 immediate values: a small one which takes some small value, and a
1105 larger one which takes a 16 bit value. Since branches also follow
1106 this pattern, relaxing these values is required.
1108 We can assemble both mips16 and normal MIPS code in a single
1109 object. Therefore, we need to support this type of relaxation at
1110 the same time that we support the relaxation described above. We
1111 use the high bit of the subtype field to distinguish these cases.
1113 The information we store for this type of relaxation is the
1114 argument code found in the opcode file for this relocation, whether
1115 the user explicitly requested a small or extended form, and whether
1116 the relocation is in a jump or jal delay slot. That tells us the
1117 size of the value, and how it should be stored. We also store
1118 whether the fragment is considered to be extended or not. We also
1119 store whether this is known to be a branch to a different section,
1120 whether we have tried to relax this frag yet, and whether we have
1121 ever extended a PC relative fragment because of a shift count. */
1122 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1125 | ((small) ? 0x100 : 0) \
1126 | ((ext) ? 0x200 : 0) \
1127 | ((dslot) ? 0x400 : 0) \
1128 | ((jal_dslot) ? 0x800 : 0))
1129 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1130 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1131 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1132 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1133 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1134 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1135 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1136 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1137 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1138 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1139 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1140 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1142 /* For microMIPS code, we use relaxation similar to one we use for
1143 MIPS16 code. Some instructions that take immediate values support
1144 two encodings: a small one which takes some small value, and a
1145 larger one which takes a 16 bit value. As some branches also follow
1146 this pattern, relaxing these values is required.
1148 We can assemble both microMIPS and normal MIPS code in a single
1149 object. Therefore, we need to support this type of relaxation at
1150 the same time that we support the relaxation described above. We
1151 use one of the high bits of the subtype field to distinguish these
1154 The information we store for this type of relaxation is the argument
1155 code found in the opcode file for this relocation, the register
1156 selected as the assembler temporary, whether the branch is
1157 unconditional, whether it is compact, whether it stores the link
1158 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1159 branches to a sequence of instructions is enabled, and whether the
1160 displacement of a branch is too large to fit as an immediate argument
1161 of a 16-bit and a 32-bit branch, respectively. */
1162 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1163 relax32, toofar16, toofar32) \
1166 | (((at) & 0x1f) << 8) \
1167 | ((uncond) ? 0x2000 : 0) \
1168 | ((compact) ? 0x4000 : 0) \
1169 | ((link) ? 0x8000 : 0) \
1170 | ((relax32) ? 0x10000 : 0) \
1171 | ((toofar16) ? 0x20000 : 0) \
1172 | ((toofar32) ? 0x40000 : 0))
1173 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1174 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1175 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1176 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1177 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1178 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1179 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1181 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1182 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1183 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1184 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1185 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1186 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1188 /* Is the given value a sign-extended 32-bit value? */
1189 #define IS_SEXT_32BIT_NUM(x) \
1190 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1191 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193 /* Is the given value a sign-extended 16-bit value? */
1194 #define IS_SEXT_16BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0x7fff) == 0 \
1196 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198 /* Is the given value a sign-extended 12-bit value? */
1199 #define IS_SEXT_12BIT_NUM(x) \
1200 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1203 #define IS_ZEXT_32BIT_NUM(x) \
1204 (((x) &~ (offsetT) 0xffffffff) == 0 \
1205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1207 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1208 VALUE << SHIFT. VALUE is evaluated exactly once. */
1209 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1210 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1211 | (((VALUE) & (MASK)) << (SHIFT)))
1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1216 (((STRUCT) >> (SHIFT)) & (MASK))
1218 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1219 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1221 include/opcode/mips.h specifies operand fields using the macros
1222 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1223 with "MIPS16OP" instead of "OP". */
1224 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1227 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1228 OP_MASK_##FIELD, OP_SH_##FIELD); \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1233 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1237 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1238 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1240 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1241 : EXTRACT_BITS ((INSN).insn_opcode, \
1242 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1243 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1244 EXTRACT_BITS ((INSN).insn_opcode, \
1245 MIPS16OP_MASK_##FIELD, \
1246 MIPS16OP_SH_##FIELD)
1248 /* Whether or not we are emitting a branch-likely macro. */
1249 static bfd_boolean emit_branch_likely_macro = FALSE;
1251 /* Global variables used when generating relaxable macros. See the
1252 comment above RELAX_ENCODE for more details about how relaxation
1255 /* 0 if we're not emitting a relaxable macro.
1256 1 if we're emitting the first of the two relaxation alternatives.
1257 2 if we're emitting the second alternative. */
1260 /* The first relaxable fixup in the current frag. (In other words,
1261 the first fixup that refers to relaxable code.) */
1264 /* sizes[0] says how many bytes of the first alternative are stored in
1265 the current frag. Likewise sizes[1] for the second alternative. */
1266 unsigned int sizes[2];
1268 /* The symbol on which the choice of sequence depends. */
1272 /* Global variables used to decide whether a macro needs a warning. */
1274 /* True if the macro is in a branch delay slot. */
1275 bfd_boolean delay_slot_p;
1277 /* Set to the length in bytes required if the macro is in a delay slot
1278 that requires a specific length of instruction, otherwise zero. */
1279 unsigned int delay_slot_length;
1281 /* For relaxable macros, sizes[0] is the length of the first alternative
1282 in bytes and sizes[1] is the length of the second alternative.
1283 For non-relaxable macros, both elements give the length of the
1285 unsigned int sizes[2];
1287 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1288 instruction of the first alternative in bytes and first_insn_sizes[1]
1289 is the length of the first instruction of the second alternative.
1290 For non-relaxable macros, both elements give the length of the first
1291 instruction in bytes.
1293 Set to zero if we haven't yet seen the first instruction. */
1294 unsigned int first_insn_sizes[2];
1296 /* For relaxable macros, insns[0] is the number of instructions for the
1297 first alternative and insns[1] is the number of instructions for the
1300 For non-relaxable macros, both elements give the number of
1301 instructions for the macro. */
1302 unsigned int insns[2];
1304 /* The first variant frag for this macro. */
1306 } mips_macro_warning;
1308 /* Prototypes for static functions. */
1310 #define internalError() \
1311 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1313 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1315 static void append_insn
1316 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1317 bfd_boolean expansionp);
1318 static void mips_no_prev_insn (void);
1319 static void macro_build (expressionS *, const char *, const char *, ...);
1320 static void mips16_macro_build
1321 (expressionS *, const char *, const char *, va_list *);
1322 static void load_register (int, expressionS *, int);
1323 static void macro_start (void);
1324 static void macro_end (void);
1325 static void macro (struct mips_cl_insn * ip);
1326 static void mips16_macro (struct mips_cl_insn * ip);
1327 static void mips_ip (char *str, struct mips_cl_insn * ip);
1328 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1329 static void mips16_immed
1330 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1331 unsigned long *, bfd_boolean *, unsigned short *);
1332 static size_t my_getSmallExpression
1333 (expressionS *, bfd_reloc_code_real_type *, char *);
1334 static void my_getExpression (expressionS *, char *);
1335 static void s_align (int);
1336 static void s_change_sec (int);
1337 static void s_change_section (int);
1338 static void s_cons (int);
1339 static void s_float_cons (int);
1340 static void s_mips_globl (int);
1341 static void s_option (int);
1342 static void s_mipsset (int);
1343 static void s_abicalls (int);
1344 static void s_cpload (int);
1345 static void s_cpsetup (int);
1346 static void s_cplocal (int);
1347 static void s_cprestore (int);
1348 static void s_cpreturn (int);
1349 static void s_dtprelword (int);
1350 static void s_dtpreldword (int);
1351 static void s_gpvalue (int);
1352 static void s_gpword (int);
1353 static void s_gpdword (int);
1354 static void s_cpadd (int);
1355 static void s_insn (int);
1356 static void md_obj_begin (void);
1357 static void md_obj_end (void);
1358 static void s_mips_ent (int);
1359 static void s_mips_end (int);
1360 static void s_mips_frame (int);
1361 static void s_mips_mask (int reg_type);
1362 static void s_mips_stab (int);
1363 static void s_mips_weakext (int);
1364 static void s_mips_file (int);
1365 static void s_mips_loc (int);
1366 static bfd_boolean pic_need_relax (symbolS *, asection *);
1367 static int relaxed_branch_length (fragS *, asection *, int);
1368 static int validate_mips_insn (const struct mips_opcode *);
1369 static int validate_micromips_insn (const struct mips_opcode *);
1370 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1371 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1373 /* Table and functions used to map between CPU/ISA names, and
1374 ISA levels, and CPU numbers. */
1376 struct mips_cpu_info
1378 const char *name; /* CPU or ISA name. */
1379 int flags; /* ASEs available, or ISA flag. */
1380 int isa; /* ISA level. */
1381 int cpu; /* CPU number (default CPU if ISA). */
1384 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1385 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1386 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1387 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1388 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1389 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1390 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1392 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option, 0},
1417 {"set", s_mipsset, 0},
1418 {"rdata", s_change_sec, 'r'},
1419 {"sdata", s_change_sec, 's'},
1420 {"livereg", s_ignore, 0},
1421 {"abicalls", s_abicalls, 0},
1422 {"cpload", s_cpload, 0},
1423 {"cpsetup", s_cpsetup, 0},
1424 {"cplocal", s_cplocal, 0},
1425 {"cprestore", s_cprestore, 0},
1426 {"cpreturn", s_cpreturn, 0},
1427 {"dtprelword", s_dtprelword, 0},
1428 {"dtpreldword", s_dtpreldword, 0},
1429 {"gpvalue", s_gpvalue, 0},
1430 {"gpword", s_gpword, 0},
1431 {"gpdword", s_gpdword, 0},
1432 {"cpadd", s_cpadd, 0},
1433 {"insn", s_insn, 0},
1435 /* Relatively generic pseudo-ops that happen to be used on MIPS
1437 {"asciiz", stringer, 8 + 1},
1438 {"bss", s_change_sec, 'b'},
1440 {"half", s_cons, 1},
1441 {"dword", s_cons, 3},
1442 {"weakext", s_mips_weakext, 0},
1443 {"origin", s_org, 0},
1444 {"repeat", s_rept, 0},
1446 /* For MIPS this is non-standard, but we define it for consistency. */
1447 {"sbss", s_change_sec, 'B'},
1449 /* These pseudo-ops are defined in read.c, but must be overridden
1450 here for one reason or another. */
1451 {"align", s_align, 0},
1452 {"byte", s_cons, 0},
1453 {"data", s_change_sec, 'd'},
1454 {"double", s_float_cons, 'd'},
1455 {"float", s_float_cons, 'f'},
1456 {"globl", s_mips_globl, 0},
1457 {"global", s_mips_globl, 0},
1458 {"hword", s_cons, 1},
1460 {"long", s_cons, 2},
1461 {"octa", s_cons, 4},
1462 {"quad", s_cons, 3},
1463 {"section", s_change_section, 0},
1464 {"short", s_cons, 1},
1465 {"single", s_float_cons, 'f'},
1466 {"stabn", s_mips_stab, 'n'},
1467 {"text", s_change_sec, 't'},
1468 {"word", s_cons, 2},
1470 { "extern", ecoff_directive_extern, 0},
1475 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1477 /* These pseudo-ops should be defined by the object file format.
1478 However, a.out doesn't support them, so we have versions here. */
1479 {"aent", s_mips_ent, 1},
1480 {"bgnb", s_ignore, 0},
1481 {"end", s_mips_end, 0},
1482 {"endb", s_ignore, 0},
1483 {"ent", s_mips_ent, 0},
1484 {"file", s_mips_file, 0},
1485 {"fmask", s_mips_mask, 'F'},
1486 {"frame", s_mips_frame, 0},
1487 {"loc", s_mips_loc, 0},
1488 {"mask", s_mips_mask, 'R'},
1489 {"verstamp", s_ignore, 0},
1493 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1494 purpose of the `.dc.a' internal pseudo-op. */
1497 mips_address_bytes (void)
1499 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1502 extern void pop_insert (const pseudo_typeS *);
1505 mips_pop_insert (void)
1507 pop_insert (mips_pseudo_table);
1508 if (! ECOFF_DEBUGGING)
1509 pop_insert (mips_nonecoff_pseudo_table);
1512 /* Symbols labelling the current insn. */
1514 struct insn_label_list
1516 struct insn_label_list *next;
1520 static struct insn_label_list *free_insn_labels;
1521 #define label_list tc_segment_info_data.labels
1523 static void mips_clear_insn_labels (void);
1524 static void mips_mark_labels (void);
1525 static void mips_compressed_mark_labels (void);
1528 mips_clear_insn_labels (void)
1530 register struct insn_label_list **pl;
1531 segment_info_type *si;
1535 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1538 si = seg_info (now_seg);
1539 *pl = si->label_list;
1540 si->label_list = NULL;
1544 /* Mark instruction labels in MIPS16/microMIPS mode. */
1547 mips_mark_labels (void)
1549 if (HAVE_CODE_COMPRESSION)
1550 mips_compressed_mark_labels ();
1553 static char *expr_end;
1555 /* Expressions which appear in instructions. These are set by
1558 static expressionS imm_expr;
1559 static expressionS imm2_expr;
1560 static expressionS offset_expr;
1562 /* Relocs associated with imm_expr and offset_expr. */
1564 static bfd_reloc_code_real_type imm_reloc[3]
1565 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1566 static bfd_reloc_code_real_type offset_reloc[3]
1567 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1569 /* This is set to the resulting size of the instruction to be produced
1570 by mips16_ip if an explicit extension is used or by mips_ip if an
1571 explicit size is supplied. */
1573 static unsigned int forced_insn_length;
1576 /* The pdr segment for per procedure frame/regmask info. Not used for
1579 static segT pdr_seg;
1582 /* The default target format to use. */
1584 #if defined (TE_FreeBSD)
1585 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1586 #elif defined (TE_TMIPS)
1587 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1589 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1593 mips_target_format (void)
1595 switch (OUTPUT_FLAVOR)
1597 case bfd_target_ecoff_flavour:
1598 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1599 case bfd_target_coff_flavour:
1601 case bfd_target_elf_flavour:
1603 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1604 return (target_big_endian
1605 ? "elf32-bigmips-vxworks"
1606 : "elf32-littlemips-vxworks");
1608 return (target_big_endian
1609 ? (HAVE_64BIT_OBJECTS
1610 ? ELF_TARGET ("elf64-", "big")
1612 ? ELF_TARGET ("elf32-n", "big")
1613 : ELF_TARGET ("elf32-", "big")))
1614 : (HAVE_64BIT_OBJECTS
1615 ? ELF_TARGET ("elf64-", "little")
1617 ? ELF_TARGET ("elf32-n", "little")
1618 : ELF_TARGET ("elf32-", "little"))));
1625 /* Return the length of a microMIPS instruction in bytes. If bits of
1626 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1627 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1628 major opcode) will require further modifications to the opcode
1631 static inline unsigned int
1632 micromips_insn_length (const struct mips_opcode *mo)
1634 return (mo->mask >> 16) == 0 ? 2 : 4;
1637 /* Return the length of instruction INSN. */
1639 static inline unsigned int
1640 insn_length (const struct mips_cl_insn *insn)
1642 if (mips_opts.micromips)
1643 return micromips_insn_length (insn->insn_mo);
1644 else if (mips_opts.mips16)
1645 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1650 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1653 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1658 insn->use_extend = FALSE;
1660 insn->insn_opcode = mo->match;
1663 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1664 insn->fixp[i] = NULL;
1665 insn->fixed_p = (mips_opts.noreorder > 0);
1666 insn->noreorder_p = (mips_opts.noreorder > 0);
1667 insn->mips16_absolute_jump_p = 0;
1668 insn->complete_p = 0;
1671 /* Record the current MIPS16/microMIPS mode in now_seg. */
1674 mips_record_compressed_mode (void)
1676 segment_info_type *si;
1678 si = seg_info (now_seg);
1679 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1680 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1681 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1682 si->tc_segment_info_data.micromips = mips_opts.micromips;
1685 /* Install INSN at the location specified by its "frag" and "where" fields. */
1688 install_insn (const struct mips_cl_insn *insn)
1690 char *f = insn->frag->fr_literal + insn->where;
1691 if (!HAVE_CODE_COMPRESSION)
1692 md_number_to_chars (f, insn->insn_opcode, 4);
1693 else if (mips_opts.micromips)
1695 unsigned int length = insn_length (insn);
1697 md_number_to_chars (f, insn->insn_opcode, 2);
1698 else if (length == 4)
1700 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1702 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1705 as_bad (_("48-bit microMIPS instructions are not supported"));
1707 else if (insn->mips16_absolute_jump_p)
1709 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1710 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1714 if (insn->use_extend)
1716 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1719 md_number_to_chars (f, insn->insn_opcode, 2);
1721 mips_record_compressed_mode ();
1724 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1725 and install the opcode in the new location. */
1728 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1733 insn->where = where;
1734 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1735 if (insn->fixp[i] != NULL)
1737 insn->fixp[i]->fx_frag = frag;
1738 insn->fixp[i]->fx_where = where;
1740 install_insn (insn);
1743 /* Add INSN to the end of the output. */
1746 add_fixed_insn (struct mips_cl_insn *insn)
1748 char *f = frag_more (insn_length (insn));
1749 move_insn (insn, frag_now, f - frag_now->fr_literal);
1752 /* Start a variant frag and move INSN to the start of the variant part,
1753 marking it as fixed. The other arguments are as for frag_var. */
1756 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1757 relax_substateT subtype, symbolS *symbol, offsetT offset)
1759 frag_grow (max_chars);
1760 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1762 frag_var (rs_machine_dependent, max_chars, var,
1763 subtype, symbol, offset, NULL);
1766 /* Insert N copies of INSN into the history buffer, starting at
1767 position FIRST. Neither FIRST nor N need to be clipped. */
1770 insert_into_history (unsigned int first, unsigned int n,
1771 const struct mips_cl_insn *insn)
1773 if (mips_relax.sequence != 2)
1777 for (i = ARRAY_SIZE (history); i-- > first;)
1779 history[i] = history[i - n];
1785 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1786 the idea is to make it obvious at a glance that each errata is
1790 init_vr4120_conflicts (void)
1792 #define CONFLICT(FIRST, SECOND) \
1793 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1795 /* Errata 21 - [D]DIV[U] after [D]MACC */
1796 CONFLICT (MACC, DIV);
1797 CONFLICT (DMACC, DIV);
1799 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1800 CONFLICT (DMULT, DMULT);
1801 CONFLICT (DMULT, DMACC);
1802 CONFLICT (DMACC, DMULT);
1803 CONFLICT (DMACC, DMACC);
1805 /* Errata 24 - MT{LO,HI} after [D]MACC */
1806 CONFLICT (MACC, MTHILO);
1807 CONFLICT (DMACC, MTHILO);
1809 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1810 instruction is executed immediately after a MACC or DMACC
1811 instruction, the result of [either instruction] is incorrect." */
1812 CONFLICT (MACC, MULT);
1813 CONFLICT (MACC, DMULT);
1814 CONFLICT (DMACC, MULT);
1815 CONFLICT (DMACC, DMULT);
1817 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1818 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1819 DDIV or DDIVU instruction, the result of the MACC or
1820 DMACC instruction is incorrect.". */
1821 CONFLICT (DMULT, MACC);
1822 CONFLICT (DMULT, DMACC);
1823 CONFLICT (DIV, MACC);
1824 CONFLICT (DIV, DMACC);
1834 #define RTYPE_MASK 0x1ff00
1835 #define RTYPE_NUM 0x00100
1836 #define RTYPE_FPU 0x00200
1837 #define RTYPE_FCC 0x00400
1838 #define RTYPE_VEC 0x00800
1839 #define RTYPE_GP 0x01000
1840 #define RTYPE_CP0 0x02000
1841 #define RTYPE_PC 0x04000
1842 #define RTYPE_ACC 0x08000
1843 #define RTYPE_CCC 0x10000
1844 #define RNUM_MASK 0x000ff
1845 #define RWARN 0x80000
1847 #define GENERIC_REGISTER_NUMBERS \
1848 {"$0", RTYPE_NUM | 0}, \
1849 {"$1", RTYPE_NUM | 1}, \
1850 {"$2", RTYPE_NUM | 2}, \
1851 {"$3", RTYPE_NUM | 3}, \
1852 {"$4", RTYPE_NUM | 4}, \
1853 {"$5", RTYPE_NUM | 5}, \
1854 {"$6", RTYPE_NUM | 6}, \
1855 {"$7", RTYPE_NUM | 7}, \
1856 {"$8", RTYPE_NUM | 8}, \
1857 {"$9", RTYPE_NUM | 9}, \
1858 {"$10", RTYPE_NUM | 10}, \
1859 {"$11", RTYPE_NUM | 11}, \
1860 {"$12", RTYPE_NUM | 12}, \
1861 {"$13", RTYPE_NUM | 13}, \
1862 {"$14", RTYPE_NUM | 14}, \
1863 {"$15", RTYPE_NUM | 15}, \
1864 {"$16", RTYPE_NUM | 16}, \
1865 {"$17", RTYPE_NUM | 17}, \
1866 {"$18", RTYPE_NUM | 18}, \
1867 {"$19", RTYPE_NUM | 19}, \
1868 {"$20", RTYPE_NUM | 20}, \
1869 {"$21", RTYPE_NUM | 21}, \
1870 {"$22", RTYPE_NUM | 22}, \
1871 {"$23", RTYPE_NUM | 23}, \
1872 {"$24", RTYPE_NUM | 24}, \
1873 {"$25", RTYPE_NUM | 25}, \
1874 {"$26", RTYPE_NUM | 26}, \
1875 {"$27", RTYPE_NUM | 27}, \
1876 {"$28", RTYPE_NUM | 28}, \
1877 {"$29", RTYPE_NUM | 29}, \
1878 {"$30", RTYPE_NUM | 30}, \
1879 {"$31", RTYPE_NUM | 31}
1881 #define FPU_REGISTER_NAMES \
1882 {"$f0", RTYPE_FPU | 0}, \
1883 {"$f1", RTYPE_FPU | 1}, \
1884 {"$f2", RTYPE_FPU | 2}, \
1885 {"$f3", RTYPE_FPU | 3}, \
1886 {"$f4", RTYPE_FPU | 4}, \
1887 {"$f5", RTYPE_FPU | 5}, \
1888 {"$f6", RTYPE_FPU | 6}, \
1889 {"$f7", RTYPE_FPU | 7}, \
1890 {"$f8", RTYPE_FPU | 8}, \
1891 {"$f9", RTYPE_FPU | 9}, \
1892 {"$f10", RTYPE_FPU | 10}, \
1893 {"$f11", RTYPE_FPU | 11}, \
1894 {"$f12", RTYPE_FPU | 12}, \
1895 {"$f13", RTYPE_FPU | 13}, \
1896 {"$f14", RTYPE_FPU | 14}, \
1897 {"$f15", RTYPE_FPU | 15}, \
1898 {"$f16", RTYPE_FPU | 16}, \
1899 {"$f17", RTYPE_FPU | 17}, \
1900 {"$f18", RTYPE_FPU | 18}, \
1901 {"$f19", RTYPE_FPU | 19}, \
1902 {"$f20", RTYPE_FPU | 20}, \
1903 {"$f21", RTYPE_FPU | 21}, \
1904 {"$f22", RTYPE_FPU | 22}, \
1905 {"$f23", RTYPE_FPU | 23}, \
1906 {"$f24", RTYPE_FPU | 24}, \
1907 {"$f25", RTYPE_FPU | 25}, \
1908 {"$f26", RTYPE_FPU | 26}, \
1909 {"$f27", RTYPE_FPU | 27}, \
1910 {"$f28", RTYPE_FPU | 28}, \
1911 {"$f29", RTYPE_FPU | 29}, \
1912 {"$f30", RTYPE_FPU | 30}, \
1913 {"$f31", RTYPE_FPU | 31}
1915 #define FPU_CONDITION_CODE_NAMES \
1916 {"$fcc0", RTYPE_FCC | 0}, \
1917 {"$fcc1", RTYPE_FCC | 1}, \
1918 {"$fcc2", RTYPE_FCC | 2}, \
1919 {"$fcc3", RTYPE_FCC | 3}, \
1920 {"$fcc4", RTYPE_FCC | 4}, \
1921 {"$fcc5", RTYPE_FCC | 5}, \
1922 {"$fcc6", RTYPE_FCC | 6}, \
1923 {"$fcc7", RTYPE_FCC | 7}
1925 #define COPROC_CONDITION_CODE_NAMES \
1926 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1927 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1928 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1929 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1930 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1931 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1932 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1933 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1935 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1936 {"$a4", RTYPE_GP | 8}, \
1937 {"$a5", RTYPE_GP | 9}, \
1938 {"$a6", RTYPE_GP | 10}, \
1939 {"$a7", RTYPE_GP | 11}, \
1940 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1941 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1942 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1943 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1944 {"$t0", RTYPE_GP | 12}, \
1945 {"$t1", RTYPE_GP | 13}, \
1946 {"$t2", RTYPE_GP | 14}, \
1947 {"$t3", RTYPE_GP | 15}
1949 #define O32_SYMBOLIC_REGISTER_NAMES \
1950 {"$t0", RTYPE_GP | 8}, \
1951 {"$t1", RTYPE_GP | 9}, \
1952 {"$t2", RTYPE_GP | 10}, \
1953 {"$t3", RTYPE_GP | 11}, \
1954 {"$t4", RTYPE_GP | 12}, \
1955 {"$t5", RTYPE_GP | 13}, \
1956 {"$t6", RTYPE_GP | 14}, \
1957 {"$t7", RTYPE_GP | 15}, \
1958 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1959 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1960 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1961 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1963 /* Remaining symbolic register names */
1964 #define SYMBOLIC_REGISTER_NAMES \
1965 {"$zero", RTYPE_GP | 0}, \
1966 {"$at", RTYPE_GP | 1}, \
1967 {"$AT", RTYPE_GP | 1}, \
1968 {"$v0", RTYPE_GP | 2}, \
1969 {"$v1", RTYPE_GP | 3}, \
1970 {"$a0", RTYPE_GP | 4}, \
1971 {"$a1", RTYPE_GP | 5}, \
1972 {"$a2", RTYPE_GP | 6}, \
1973 {"$a3", RTYPE_GP | 7}, \
1974 {"$s0", RTYPE_GP | 16}, \
1975 {"$s1", RTYPE_GP | 17}, \
1976 {"$s2", RTYPE_GP | 18}, \
1977 {"$s3", RTYPE_GP | 19}, \
1978 {"$s4", RTYPE_GP | 20}, \
1979 {"$s5", RTYPE_GP | 21}, \
1980 {"$s6", RTYPE_GP | 22}, \
1981 {"$s7", RTYPE_GP | 23}, \
1982 {"$t8", RTYPE_GP | 24}, \
1983 {"$t9", RTYPE_GP | 25}, \
1984 {"$k0", RTYPE_GP | 26}, \
1985 {"$kt0", RTYPE_GP | 26}, \
1986 {"$k1", RTYPE_GP | 27}, \
1987 {"$kt1", RTYPE_GP | 27}, \
1988 {"$gp", RTYPE_GP | 28}, \
1989 {"$sp", RTYPE_GP | 29}, \
1990 {"$s8", RTYPE_GP | 30}, \
1991 {"$fp", RTYPE_GP | 30}, \
1992 {"$ra", RTYPE_GP | 31}
1994 #define MIPS16_SPECIAL_REGISTER_NAMES \
1995 {"$pc", RTYPE_PC | 0}
1997 #define MDMX_VECTOR_REGISTER_NAMES \
1998 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1999 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2000 {"$v2", RTYPE_VEC | 2}, \
2001 {"$v3", RTYPE_VEC | 3}, \
2002 {"$v4", RTYPE_VEC | 4}, \
2003 {"$v5", RTYPE_VEC | 5}, \
2004 {"$v6", RTYPE_VEC | 6}, \
2005 {"$v7", RTYPE_VEC | 7}, \
2006 {"$v8", RTYPE_VEC | 8}, \
2007 {"$v9", RTYPE_VEC | 9}, \
2008 {"$v10", RTYPE_VEC | 10}, \
2009 {"$v11", RTYPE_VEC | 11}, \
2010 {"$v12", RTYPE_VEC | 12}, \
2011 {"$v13", RTYPE_VEC | 13}, \
2012 {"$v14", RTYPE_VEC | 14}, \
2013 {"$v15", RTYPE_VEC | 15}, \
2014 {"$v16", RTYPE_VEC | 16}, \
2015 {"$v17", RTYPE_VEC | 17}, \
2016 {"$v18", RTYPE_VEC | 18}, \
2017 {"$v19", RTYPE_VEC | 19}, \
2018 {"$v20", RTYPE_VEC | 20}, \
2019 {"$v21", RTYPE_VEC | 21}, \
2020 {"$v22", RTYPE_VEC | 22}, \
2021 {"$v23", RTYPE_VEC | 23}, \
2022 {"$v24", RTYPE_VEC | 24}, \
2023 {"$v25", RTYPE_VEC | 25}, \
2024 {"$v26", RTYPE_VEC | 26}, \
2025 {"$v27", RTYPE_VEC | 27}, \
2026 {"$v28", RTYPE_VEC | 28}, \
2027 {"$v29", RTYPE_VEC | 29}, \
2028 {"$v30", RTYPE_VEC | 30}, \
2029 {"$v31", RTYPE_VEC | 31}
2031 #define MIPS_DSP_ACCUMULATOR_NAMES \
2032 {"$ac0", RTYPE_ACC | 0}, \
2033 {"$ac1", RTYPE_ACC | 1}, \
2034 {"$ac2", RTYPE_ACC | 2}, \
2035 {"$ac3", RTYPE_ACC | 3}
2037 static const struct regname reg_names[] = {
2038 GENERIC_REGISTER_NUMBERS,
2040 FPU_CONDITION_CODE_NAMES,
2041 COPROC_CONDITION_CODE_NAMES,
2043 /* The $txx registers depends on the abi,
2044 these will be added later into the symbol table from
2045 one of the tables below once mips_abi is set after
2046 parsing of arguments from the command line. */
2047 SYMBOLIC_REGISTER_NAMES,
2049 MIPS16_SPECIAL_REGISTER_NAMES,
2050 MDMX_VECTOR_REGISTER_NAMES,
2051 MIPS_DSP_ACCUMULATOR_NAMES,
2055 static const struct regname reg_names_o32[] = {
2056 O32_SYMBOLIC_REGISTER_NAMES,
2060 static const struct regname reg_names_n32n64[] = {
2061 N32N64_SYMBOLIC_REGISTER_NAMES,
2065 /* Check if S points at a valid register specifier according to TYPES.
2066 If so, then return 1, advance S to consume the specifier and store
2067 the register's number in REGNOP, otherwise return 0. */
2070 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2077 /* Find end of name. */
2079 if (is_name_beginner (*e))
2081 while (is_part_of_name (*e))
2084 /* Terminate name. */
2088 /* Look for a register symbol. */
2089 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2091 int r = S_GET_VALUE (symbolP);
2093 reg = r & RNUM_MASK;
2094 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2095 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2096 reg = (r & RNUM_MASK) - 2;
2098 /* Else see if this is a register defined in an itbl entry. */
2099 else if ((types & RTYPE_GP) && itbl_have_entries)
2106 if (itbl_get_reg_val (n, &r))
2107 reg = r & RNUM_MASK;
2110 /* Advance to next token if a register was recognised. */
2113 else if (types & RWARN)
2114 as_warn (_("Unrecognized register name `%s'"), *s);
2122 /* Check if S points at a valid register list according to TYPES.
2123 If so, then return 1, advance S to consume the list and store
2124 the registers present on the list as a bitmask of ones in REGLISTP,
2125 otherwise return 0. A valid list comprises a comma-separated
2126 enumeration of valid single registers and/or dash-separated
2127 contiguous register ranges as determined by their numbers.
2129 As a special exception if one of s0-s7 registers is specified as
2130 the range's lower delimiter and s8 (fp) is its upper one, then no
2131 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2132 are selected; they have to be listed separately if needed. */
2135 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2137 unsigned int reglist = 0;
2138 unsigned int lastregno;
2139 bfd_boolean ok = TRUE;
2140 unsigned int regmask;
2141 char *s_endlist = *s;
2145 while (reg_lookup (s, types, ®no))
2151 ok = reg_lookup (s, types, &lastregno);
2152 if (ok && lastregno < regno)
2158 if (lastregno == FP && regno >= S0 && regno <= S7)
2163 regmask = 1 << lastregno;
2164 regmask = (regmask << 1) - 1;
2165 regmask ^= (1 << regno) - 1;
2179 *reglistp = reglist;
2180 return ok && reglist != 0;
2183 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2184 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2187 is_opcode_valid (const struct mips_opcode *mo)
2189 int isa = mips_opts.isa;
2192 if (mips_opts.ase_mdmx)
2194 if (mips_opts.ase_dsp)
2196 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2198 if (mips_opts.ase_dspr2)
2200 if (mips_opts.ase_mt)
2202 if (mips_opts.ase_mips3d)
2204 if (mips_opts.ase_smartmips)
2205 isa |= INSN_SMARTMIPS;
2207 /* Don't accept instructions based on the ISA if the CPU does not implement
2208 all the coprocessor insns. */
2209 if (NO_ISA_COP (mips_opts.arch)
2210 && COP_INSN (mo->pinfo))
2213 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2216 /* Check whether the instruction or macro requires single-precision or
2217 double-precision floating-point support. Note that this information is
2218 stored differently in the opcode table for insns and macros. */
2219 if (mo->pinfo == INSN_MACRO)
2221 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2222 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2226 fp_s = mo->pinfo & FP_S;
2227 fp_d = mo->pinfo & FP_D;
2230 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2233 if (fp_s && mips_opts.soft_float)
2239 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2240 selected ISA and architecture. */
2243 is_opcode_valid_16 (const struct mips_opcode *mo)
2245 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2248 /* Return TRUE if the size of the microMIPS opcode MO matches one
2249 explicitly requested. Always TRUE in the standard MIPS mode. */
2252 is_size_valid (const struct mips_opcode *mo)
2254 if (!mips_opts.micromips)
2257 if (!forced_insn_length)
2259 if (mo->pinfo == INSN_MACRO)
2261 return forced_insn_length == micromips_insn_length (mo);
2264 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2265 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2268 is_delay_slot_valid (const struct mips_opcode *mo)
2270 if (!mips_opts.micromips)
2273 if (mo->pinfo == INSN_MACRO)
2275 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2276 && micromips_insn_length (mo) != 4)
2278 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2279 && micromips_insn_length (mo) != 2)
2285 /* This function is called once, at assembler startup time. It should set up
2286 all the tables, etc. that the MD part of the assembler will need. */
2291 const char *retval = NULL;
2295 if (mips_pic != NO_PIC)
2297 if (g_switch_seen && g_switch_value != 0)
2298 as_bad (_("-G may not be used in position-independent code"));
2302 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2303 as_warn (_("Could not set architecture and machine"));
2305 op_hash = hash_new ();
2307 for (i = 0; i < NUMOPCODES;)
2309 const char *name = mips_opcodes[i].name;
2311 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2314 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2315 mips_opcodes[i].name, retval);
2316 /* Probably a memory allocation problem? Give up now. */
2317 as_fatal (_("Broken assembler. No assembly attempted."));
2321 if (mips_opcodes[i].pinfo != INSN_MACRO)
2323 if (!validate_mips_insn (&mips_opcodes[i]))
2325 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2327 create_insn (&nop_insn, mips_opcodes + i);
2328 if (mips_fix_loongson2f_nop)
2329 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2330 nop_insn.fixed_p = 1;
2335 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2338 mips16_op_hash = hash_new ();
2341 while (i < bfd_mips16_num_opcodes)
2343 const char *name = mips16_opcodes[i].name;
2345 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2347 as_fatal (_("internal: can't hash `%s': %s"),
2348 mips16_opcodes[i].name, retval);
2351 if (mips16_opcodes[i].pinfo != INSN_MACRO
2352 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2353 != mips16_opcodes[i].match))
2355 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2356 mips16_opcodes[i].name, mips16_opcodes[i].args);
2359 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2361 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2362 mips16_nop_insn.fixed_p = 1;
2366 while (i < bfd_mips16_num_opcodes
2367 && strcmp (mips16_opcodes[i].name, name) == 0);
2370 micromips_op_hash = hash_new ();
2373 while (i < bfd_micromips_num_opcodes)
2375 const char *name = micromips_opcodes[i].name;
2377 retval = hash_insert (micromips_op_hash, name,
2378 (void *) µmips_opcodes[i]);
2380 as_fatal (_("internal: can't hash `%s': %s"),
2381 micromips_opcodes[i].name, retval);
2383 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2385 struct mips_cl_insn *micromips_nop_insn;
2387 if (!validate_micromips_insn (µmips_opcodes[i]))
2390 if (micromips_insn_length (micromips_opcodes + i) == 2)
2391 micromips_nop_insn = µmips_nop16_insn;
2392 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2393 micromips_nop_insn = µmips_nop32_insn;
2397 if (micromips_nop_insn->insn_mo == NULL
2398 && strcmp (name, "nop") == 0)
2400 create_insn (micromips_nop_insn, micromips_opcodes + i);
2401 micromips_nop_insn->fixed_p = 1;
2404 while (++i < bfd_micromips_num_opcodes
2405 && strcmp (micromips_opcodes[i].name, name) == 0);
2409 as_fatal (_("Broken assembler. No assembly attempted."));
2411 /* We add all the general register names to the symbol table. This
2412 helps us detect invalid uses of them. */
2413 for (i = 0; reg_names[i].name; i++)
2414 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2415 reg_names[i].num, /* & RNUM_MASK, */
2416 &zero_address_frag));
2418 for (i = 0; reg_names_n32n64[i].name; i++)
2419 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2420 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2421 &zero_address_frag));
2423 for (i = 0; reg_names_o32[i].name; i++)
2424 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2425 reg_names_o32[i].num, /* & RNUM_MASK, */
2426 &zero_address_frag));
2428 mips_no_prev_insn ();
2431 mips_cprmask[0] = 0;
2432 mips_cprmask[1] = 0;
2433 mips_cprmask[2] = 0;
2434 mips_cprmask[3] = 0;
2436 /* set the default alignment for the text section (2**2) */
2437 record_alignment (text_section, 2);
2439 bfd_set_gp_size (stdoutput, g_switch_value);
2444 /* On a native system other than VxWorks, sections must be aligned
2445 to 16 byte boundaries. When configured for an embedded ELF
2446 target, we don't bother. */
2447 if (strncmp (TARGET_OS, "elf", 3) != 0
2448 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2450 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2451 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2452 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2455 /* Create a .reginfo section for register masks and a .mdebug
2456 section for debugging information. */
2464 subseg = now_subseg;
2466 /* The ABI says this section should be loaded so that the
2467 running program can access it. However, we don't load it
2468 if we are configured for an embedded target */
2469 flags = SEC_READONLY | SEC_DATA;
2470 if (strncmp (TARGET_OS, "elf", 3) != 0)
2471 flags |= SEC_ALLOC | SEC_LOAD;
2473 if (mips_abi != N64_ABI)
2475 sec = subseg_new (".reginfo", (subsegT) 0);
2477 bfd_set_section_flags (stdoutput, sec, flags);
2478 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2480 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2484 /* The 64-bit ABI uses a .MIPS.options section rather than
2485 .reginfo section. */
2486 sec = subseg_new (".MIPS.options", (subsegT) 0);
2487 bfd_set_section_flags (stdoutput, sec, flags);
2488 bfd_set_section_alignment (stdoutput, sec, 3);
2490 /* Set up the option header. */
2492 Elf_Internal_Options opthdr;
2495 opthdr.kind = ODK_REGINFO;
2496 opthdr.size = (sizeof (Elf_External_Options)
2497 + sizeof (Elf64_External_RegInfo));
2500 f = frag_more (sizeof (Elf_External_Options));
2501 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2502 (Elf_External_Options *) f);
2504 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2508 if (ECOFF_DEBUGGING)
2510 sec = subseg_new (".mdebug", (subsegT) 0);
2511 (void) bfd_set_section_flags (stdoutput, sec,
2512 SEC_HAS_CONTENTS | SEC_READONLY);
2513 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2515 else if (mips_flag_pdr)
2517 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2518 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2519 SEC_READONLY | SEC_RELOC
2521 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2524 subseg_set (seg, subseg);
2527 #endif /* OBJ_ELF */
2529 if (! ECOFF_DEBUGGING)
2532 if (mips_fix_vr4120)
2533 init_vr4120_conflicts ();
2539 mips_emit_delays ();
2540 if (! ECOFF_DEBUGGING)
2545 md_assemble (char *str)
2547 struct mips_cl_insn insn;
2548 bfd_reloc_code_real_type unused_reloc[3]
2549 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2551 imm_expr.X_op = O_absent;
2552 imm2_expr.X_op = O_absent;
2553 offset_expr.X_op = O_absent;
2554 imm_reloc[0] = BFD_RELOC_UNUSED;
2555 imm_reloc[1] = BFD_RELOC_UNUSED;
2556 imm_reloc[2] = BFD_RELOC_UNUSED;
2557 offset_reloc[0] = BFD_RELOC_UNUSED;
2558 offset_reloc[1] = BFD_RELOC_UNUSED;
2559 offset_reloc[2] = BFD_RELOC_UNUSED;
2561 if (mips_opts.mips16)
2562 mips16_ip (str, &insn);
2565 mips_ip (str, &insn);
2566 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2567 str, insn.insn_opcode));
2572 as_bad ("%s `%s'", insn_error, str);
2576 if (insn.insn_mo->pinfo == INSN_MACRO)
2579 if (mips_opts.mips16)
2580 mips16_macro (&insn);
2587 if (imm_expr.X_op != O_absent)
2588 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2589 else if (offset_expr.X_op != O_absent)
2590 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2592 append_insn (&insn, NULL, unused_reloc, FALSE);
2596 /* Convenience functions for abstracting away the differences between
2597 MIPS16 and non-MIPS16 relocations. */
2599 static inline bfd_boolean
2600 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2604 case BFD_RELOC_MIPS16_JMP:
2605 case BFD_RELOC_MIPS16_GPREL:
2606 case BFD_RELOC_MIPS16_GOT16:
2607 case BFD_RELOC_MIPS16_CALL16:
2608 case BFD_RELOC_MIPS16_HI16_S:
2609 case BFD_RELOC_MIPS16_HI16:
2610 case BFD_RELOC_MIPS16_LO16:
2618 static inline bfd_boolean
2619 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2623 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2624 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2625 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2626 case BFD_RELOC_MICROMIPS_GPREL16:
2627 case BFD_RELOC_MICROMIPS_JMP:
2628 case BFD_RELOC_MICROMIPS_HI16:
2629 case BFD_RELOC_MICROMIPS_HI16_S:
2630 case BFD_RELOC_MICROMIPS_LO16:
2631 case BFD_RELOC_MICROMIPS_LITERAL:
2632 case BFD_RELOC_MICROMIPS_GOT16:
2633 case BFD_RELOC_MICROMIPS_CALL16:
2634 case BFD_RELOC_MICROMIPS_GOT_HI16:
2635 case BFD_RELOC_MICROMIPS_GOT_LO16:
2636 case BFD_RELOC_MICROMIPS_CALL_HI16:
2637 case BFD_RELOC_MICROMIPS_CALL_LO16:
2638 case BFD_RELOC_MICROMIPS_SUB:
2639 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2640 case BFD_RELOC_MICROMIPS_GOT_OFST:
2641 case BFD_RELOC_MICROMIPS_GOT_DISP:
2642 case BFD_RELOC_MICROMIPS_HIGHEST:
2643 case BFD_RELOC_MICROMIPS_HIGHER:
2644 case BFD_RELOC_MICROMIPS_SCN_DISP:
2645 case BFD_RELOC_MICROMIPS_JALR:
2653 static inline bfd_boolean
2654 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2656 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2659 static inline bfd_boolean
2660 got16_reloc_p (bfd_reloc_code_real_type reloc)
2662 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2663 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2666 static inline bfd_boolean
2667 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2669 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2670 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2673 static inline bfd_boolean
2674 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2676 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2677 || reloc == BFD_RELOC_MICROMIPS_LO16);
2680 static inline bfd_boolean
2681 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2683 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2686 /* Return true if the given relocation might need a matching %lo().
2687 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2688 need a matching %lo() when applied to local symbols. */
2690 static inline bfd_boolean
2691 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2693 return (HAVE_IN_PLACE_ADDENDS
2694 && (hi16_reloc_p (reloc)
2695 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2696 all GOT16 relocations evaluate to "G". */
2697 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2700 /* Return the type of %lo() reloc needed by RELOC, given that
2701 reloc_needs_lo_p. */
2703 static inline bfd_reloc_code_real_type
2704 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2706 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2707 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2711 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2714 static inline bfd_boolean
2715 fixup_has_matching_lo_p (fixS *fixp)
2717 return (fixp->fx_next != NULL
2718 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2719 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2720 && fixp->fx_offset == fixp->fx_next->fx_offset);
2723 /* This function returns true if modifying a register requires a
2727 reg_needs_delay (unsigned int reg)
2729 unsigned long prev_pinfo;
2731 prev_pinfo = history[0].insn_mo->pinfo;
2732 if (! mips_opts.noreorder
2733 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2734 && ! gpr_interlocks)
2735 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2736 && ! cop_interlocks)))
2738 /* A load from a coprocessor or from memory. All load delays
2739 delay the use of general register rt for one instruction. */
2740 /* Itbl support may require additional care here. */
2741 know (prev_pinfo & INSN_WRITE_GPR_T);
2742 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2749 /* Move all labels in insn_labels to the current insertion point. */
2752 mips_move_labels (void)
2754 segment_info_type *si = seg_info (now_seg);
2755 struct insn_label_list *l;
2758 for (l = si->label_list; l != NULL; l = l->next)
2760 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2761 symbol_set_frag (l->label, frag_now);
2762 val = (valueT) frag_now_fix ();
2763 /* MIPS16/microMIPS text labels are stored as odd. */
2764 if (HAVE_CODE_COMPRESSION)
2766 S_SET_VALUE (l->label, val);
2771 s_is_linkonce (symbolS *sym, segT from_seg)
2773 bfd_boolean linkonce = FALSE;
2774 segT symseg = S_GET_SEGMENT (sym);
2776 if (symseg != from_seg && !S_IS_LOCAL (sym))
2778 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2781 /* The GNU toolchain uses an extension for ELF: a section
2782 beginning with the magic string .gnu.linkonce is a
2783 linkonce section. */
2784 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2785 sizeof ".gnu.linkonce" - 1) == 0)
2792 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2793 linker to handle them specially, such as generating jalx instructions
2794 when needed. We also make them odd for the duration of the assembly,
2795 in order to generate the right sort of code. We will make them even
2796 in the adjust_symtab routine, while leaving them marked. This is
2797 convenient for the debugger and the disassembler. The linker knows
2798 to make them odd again. */
2801 mips_compressed_mark_labels (void)
2803 segment_info_type *si = seg_info (now_seg);
2804 struct insn_label_list *l;
2806 gas_assert (HAVE_CODE_COMPRESSION);
2808 for (l = si->label_list; l != NULL; l = l->next)
2810 symbolS *label = l->label;
2812 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2815 if (mips_opts.mips16)
2816 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2818 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2821 if ((S_GET_VALUE (label) & 1) == 0
2822 /* Don't adjust the address if the label is global or weak, or
2823 in a link-once section, since we'll be emitting symbol reloc
2824 references to it which will be patched up by the linker, and
2825 the final value of the symbol may or may not be MIPS16/microMIPS. */
2826 && ! S_IS_WEAK (label)
2827 && ! S_IS_EXTERNAL (label)
2828 && ! s_is_linkonce (label, now_seg))
2829 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2833 /* End the current frag. Make it a variant frag and record the
2837 relax_close_frag (void)
2839 mips_macro_warning.first_frag = frag_now;
2840 frag_var (rs_machine_dependent, 0, 0,
2841 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2842 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2844 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2845 mips_relax.first_fixup = 0;
2848 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2849 See the comment above RELAX_ENCODE for more details. */
2852 relax_start (symbolS *symbol)
2854 gas_assert (mips_relax.sequence == 0);
2855 mips_relax.sequence = 1;
2856 mips_relax.symbol = symbol;
2859 /* Start generating the second version of a relaxable sequence.
2860 See the comment above RELAX_ENCODE for more details. */
2865 gas_assert (mips_relax.sequence == 1);
2866 mips_relax.sequence = 2;
2869 /* End the current relaxable sequence. */
2874 gas_assert (mips_relax.sequence == 2);
2875 relax_close_frag ();
2876 mips_relax.sequence = 0;
2879 /* Return true if IP is a delayed branch or jump. */
2881 static inline bfd_boolean
2882 delayed_branch_p (const struct mips_cl_insn *ip)
2884 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2885 | INSN_COND_BRANCH_DELAY
2886 | INSN_COND_BRANCH_LIKELY)) != 0;
2889 /* Return true if IP is a compact branch or jump. */
2891 static inline bfd_boolean
2892 compact_branch_p (const struct mips_cl_insn *ip)
2894 if (mips_opts.mips16)
2895 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2896 | MIPS16_INSN_COND_BRANCH)) != 0;
2898 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2899 | INSN2_COND_BRANCH)) != 0;
2902 /* Return true if IP is an unconditional branch or jump. */
2904 static inline bfd_boolean
2905 uncond_branch_p (const struct mips_cl_insn *ip)
2907 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2908 || (mips_opts.mips16
2909 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2910 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2913 /* Return true if IP is a branch-likely instruction. */
2915 static inline bfd_boolean
2916 branch_likely_p (const struct mips_cl_insn *ip)
2918 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2921 /* Return the type of nop that should be used to fill the delay slot
2922 of delayed branch IP. */
2924 static struct mips_cl_insn *
2925 get_delay_slot_nop (const struct mips_cl_insn *ip)
2927 if (mips_opts.micromips
2928 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2929 return µmips_nop32_insn;
2933 /* Return the mask of core registers that IP reads or writes. */
2936 gpr_mod_mask (const struct mips_cl_insn *ip)
2938 unsigned long pinfo2;
2942 pinfo2 = ip->insn_mo->pinfo2;
2943 if (mips_opts.micromips)
2945 if (pinfo2 & INSN2_MOD_GPR_MB)
2946 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
2947 if (pinfo2 & INSN2_MOD_GPR_MC)
2948 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
2949 if (pinfo2 & INSN2_MOD_GPR_MD)
2950 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2951 if (pinfo2 & INSN2_MOD_GPR_ME)
2952 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
2953 if (pinfo2 & INSN2_MOD_GPR_MF)
2954 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2955 if (pinfo2 & INSN2_MOD_GPR_MG)
2956 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
2957 if (pinfo2 & INSN2_MOD_GPR_MHI)
2959 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
2960 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
2962 if (pinfo2 & INSN2_MOD_GPR_MJ)
2963 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
2964 if (pinfo2 & INSN2_MOD_GPR_MM)
2965 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
2966 if (pinfo2 & INSN2_MOD_GPR_MN)
2967 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
2968 if (pinfo2 & INSN2_MOD_GPR_MP)
2969 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
2970 if (pinfo2 & INSN2_MOD_GPR_MQ)
2971 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
2972 if (pinfo2 & INSN2_MOD_SP)
2978 /* Return the mask of core registers that IP reads. */
2981 gpr_read_mask (const struct mips_cl_insn *ip)
2983 unsigned long pinfo, pinfo2;
2986 mask = gpr_mod_mask (ip);
2987 pinfo = ip->insn_mo->pinfo;
2988 pinfo2 = ip->insn_mo->pinfo2;
2989 if (mips_opts.mips16)
2991 if (pinfo & MIPS16_INSN_READ_X)
2992 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2993 if (pinfo & MIPS16_INSN_READ_Y)
2994 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2995 if (pinfo & MIPS16_INSN_READ_T)
2997 if (pinfo & MIPS16_INSN_READ_SP)
2999 if (pinfo & MIPS16_INSN_READ_31)
3001 if (pinfo & MIPS16_INSN_READ_Z)
3002 mask |= 1 << (mips16_to_32_reg_map
3003 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3004 if (pinfo & MIPS16_INSN_READ_GPR_X)
3005 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3009 if (pinfo2 & INSN2_READ_GPR_D)
3010 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3011 if (pinfo & INSN_READ_GPR_T)
3012 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3013 if (pinfo & INSN_READ_GPR_S)
3014 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3015 if (pinfo2 & INSN2_READ_GP)
3017 if (pinfo2 & INSN2_READ_GPR_31)
3019 if (pinfo2 & INSN2_READ_GPR_Z)
3020 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3022 /* Don't include register 0. */
3026 /* Return the mask of core registers that IP writes. */
3029 gpr_write_mask (const struct mips_cl_insn *ip)
3031 unsigned long pinfo, pinfo2;
3034 mask = gpr_mod_mask (ip);
3035 pinfo = ip->insn_mo->pinfo;
3036 pinfo2 = ip->insn_mo->pinfo2;
3037 if (mips_opts.mips16)
3039 if (pinfo & MIPS16_INSN_WRITE_X)
3040 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3041 if (pinfo & MIPS16_INSN_WRITE_Y)
3042 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3043 if (pinfo & MIPS16_INSN_WRITE_Z)
3044 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3045 if (pinfo & MIPS16_INSN_WRITE_T)
3047 if (pinfo & MIPS16_INSN_WRITE_SP)
3049 if (pinfo & MIPS16_INSN_WRITE_31)
3051 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3052 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3056 if (pinfo & INSN_WRITE_GPR_D)
3057 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3058 if (pinfo & INSN_WRITE_GPR_T)
3059 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3060 if (pinfo2 & INSN2_WRITE_GPR_S)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3062 if (pinfo & INSN_WRITE_GPR_31)
3064 if (pinfo2 & INSN2_WRITE_GPR_Z)
3065 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3067 /* Don't include register 0. */
3071 /* Return the mask of floating-point registers that IP reads. */
3074 fpr_read_mask (const struct mips_cl_insn *ip)
3076 unsigned long pinfo, pinfo2;
3080 pinfo = ip->insn_mo->pinfo;
3081 pinfo2 = ip->insn_mo->pinfo2;
3082 if (!mips_opts.mips16)
3084 if (pinfo2 & INSN2_READ_FPR_D)
3085 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3086 if (pinfo & INSN_READ_FPR_S)
3087 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3088 if (pinfo & INSN_READ_FPR_T)
3089 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3090 if (pinfo & INSN_READ_FPR_R)
3091 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3092 if (pinfo2 & INSN2_READ_FPR_Z)
3093 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3095 /* Conservatively treat all operands to an FP_D instruction are doubles.
3096 (This is overly pessimistic for things like cvt.d.s.) */
3097 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3102 /* Return the mask of floating-point registers that IP writes. */
3105 fpr_write_mask (const struct mips_cl_insn *ip)
3107 unsigned long pinfo, pinfo2;
3111 pinfo = ip->insn_mo->pinfo;
3112 pinfo2 = ip->insn_mo->pinfo2;
3113 if (!mips_opts.mips16)
3115 if (pinfo & INSN_WRITE_FPR_D)
3116 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3117 if (pinfo & INSN_WRITE_FPR_S)
3118 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3119 if (pinfo & INSN_WRITE_FPR_T)
3120 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3121 if (pinfo2 & INSN2_WRITE_FPR_Z)
3122 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3124 /* Conservatively treat all operands to an FP_D instruction are doubles.
3125 (This is overly pessimistic for things like cvt.s.d.) */
3126 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3131 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3132 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3133 by VR4120 errata. */
3136 classify_vr4120_insn (const char *name)
3138 if (strncmp (name, "macc", 4) == 0)
3139 return FIX_VR4120_MACC;
3140 if (strncmp (name, "dmacc", 5) == 0)
3141 return FIX_VR4120_DMACC;
3142 if (strncmp (name, "mult", 4) == 0)
3143 return FIX_VR4120_MULT;
3144 if (strncmp (name, "dmult", 5) == 0)
3145 return FIX_VR4120_DMULT;
3146 if (strstr (name, "div"))
3147 return FIX_VR4120_DIV;
3148 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3149 return FIX_VR4120_MTHILO;
3150 return NUM_FIX_VR4120_CLASSES;
3153 #define INSN_ERET 0x42000018
3154 #define INSN_DERET 0x4200001f
3156 /* Return the number of instructions that must separate INSN1 and INSN2,
3157 where INSN1 is the earlier instruction. Return the worst-case value
3158 for any INSN2 if INSN2 is null. */
3161 insns_between (const struct mips_cl_insn *insn1,
3162 const struct mips_cl_insn *insn2)
3164 unsigned long pinfo1, pinfo2;
3167 /* This function needs to know which pinfo flags are set for INSN2
3168 and which registers INSN2 uses. The former is stored in PINFO2 and
3169 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3170 will have every flag set and INSN2_USES_GPR will always return true. */
3171 pinfo1 = insn1->insn_mo->pinfo;
3172 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3174 #define INSN2_USES_GPR(REG) \
3175 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3177 /* For most targets, write-after-read dependencies on the HI and LO
3178 registers must be separated by at least two instructions. */
3179 if (!hilo_interlocks)
3181 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3183 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3187 /* If we're working around r7000 errata, there must be two instructions
3188 between an mfhi or mflo and any instruction that uses the result. */
3189 if (mips_7000_hilo_fix
3190 && !mips_opts.micromips
3191 && MF_HILO_INSN (pinfo1)
3192 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3195 /* If we're working around 24K errata, one instruction is required
3196 if an ERET or DERET is followed by a branch instruction. */
3197 if (mips_fix_24k && !mips_opts.micromips)
3199 if (insn1->insn_opcode == INSN_ERET
3200 || insn1->insn_opcode == INSN_DERET)
3203 || insn2->insn_opcode == INSN_ERET
3204 || insn2->insn_opcode == INSN_DERET
3205 || delayed_branch_p (insn2))
3210 /* If working around VR4120 errata, check for combinations that need
3211 a single intervening instruction. */
3212 if (mips_fix_vr4120 && !mips_opts.micromips)
3214 unsigned int class1, class2;
3216 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3217 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3221 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3222 if (vr4120_conflicts[class1] & (1 << class2))
3227 if (!HAVE_CODE_COMPRESSION)
3229 /* Check for GPR or coprocessor load delays. All such delays
3230 are on the RT register. */
3231 /* Itbl support may require additional care here. */
3232 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3233 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3235 know (pinfo1 & INSN_WRITE_GPR_T);
3236 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3240 /* Check for generic coprocessor hazards.
3242 This case is not handled very well. There is no special
3243 knowledge of CP0 handling, and the coprocessors other than
3244 the floating point unit are not distinguished at all. */
3245 /* Itbl support may require additional care here. FIXME!
3246 Need to modify this to include knowledge about
3247 user specified delays! */
3248 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3249 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3251 /* Handle cases where INSN1 writes to a known general coprocessor
3252 register. There must be a one instruction delay before INSN2
3253 if INSN2 reads that register, otherwise no delay is needed. */
3254 mask = fpr_write_mask (insn1);
3257 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3262 /* Read-after-write dependencies on the control registers
3263 require a two-instruction gap. */
3264 if ((pinfo1 & INSN_WRITE_COND_CODE)
3265 && (pinfo2 & INSN_READ_COND_CODE))
3268 /* We don't know exactly what INSN1 does. If INSN2 is
3269 also a coprocessor instruction, assume there must be
3270 a one instruction gap. */
3271 if (pinfo2 & INSN_COP)
3276 /* Check for read-after-write dependencies on the coprocessor
3277 control registers in cases where INSN1 does not need a general
3278 coprocessor delay. This means that INSN1 is a floating point
3279 comparison instruction. */
3280 /* Itbl support may require additional care here. */
3281 else if (!cop_interlocks
3282 && (pinfo1 & INSN_WRITE_COND_CODE)
3283 && (pinfo2 & INSN_READ_COND_CODE))
3287 #undef INSN2_USES_GPR
3292 /* Return the number of nops that would be needed to work around the
3293 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3294 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3295 that are contained within the first IGNORE instructions of HIST. */
3298 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3299 const struct mips_cl_insn *insn)
3304 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3305 are not affected by the errata. */
3307 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3308 || strcmp (insn->insn_mo->name, "mtlo") == 0
3309 || strcmp (insn->insn_mo->name, "mthi") == 0))
3312 /* Search for the first MFLO or MFHI. */
3313 for (i = 0; i < MAX_VR4130_NOPS; i++)
3314 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3316 /* Extract the destination register. */
3317 mask = gpr_write_mask (&hist[i]);
3319 /* No nops are needed if INSN reads that register. */
3320 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3323 /* ...or if any of the intervening instructions do. */
3324 for (j = 0; j < i; j++)
3325 if (gpr_read_mask (&hist[j]) & mask)
3329 return MAX_VR4130_NOPS - i;
3334 #define BASE_REG_EQ(INSN1, INSN2) \
3335 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3336 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3338 /* Return the minimum alignment for this store instruction. */
3341 fix_24k_align_to (const struct mips_opcode *mo)
3343 if (strcmp (mo->name, "sh") == 0)
3346 if (strcmp (mo->name, "swc1") == 0
3347 || strcmp (mo->name, "swc2") == 0
3348 || strcmp (mo->name, "sw") == 0
3349 || strcmp (mo->name, "sc") == 0
3350 || strcmp (mo->name, "s.s") == 0)
3353 if (strcmp (mo->name, "sdc1") == 0
3354 || strcmp (mo->name, "sdc2") == 0
3355 || strcmp (mo->name, "s.d") == 0)
3362 struct fix_24k_store_info
3364 /* Immediate offset, if any, for this store instruction. */
3366 /* Alignment required by this store instruction. */
3368 /* True for register offsets. */
3369 int register_offset;
3372 /* Comparison function used by qsort. */
3375 fix_24k_sort (const void *a, const void *b)
3377 const struct fix_24k_store_info *pos1 = a;
3378 const struct fix_24k_store_info *pos2 = b;
3380 return (pos1->off - pos2->off);
3383 /* INSN is a store instruction. Try to record the store information
3384 in STINFO. Return false if the information isn't known. */
3387 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3388 const struct mips_cl_insn *insn)
3390 /* The instruction must have a known offset. */
3391 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3394 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3395 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3399 /* Return the number of nops that would be needed to work around the 24k
3400 "lost data on stores during refill" errata if instruction INSN
3401 immediately followed the 2 instructions described by HIST.
3402 Ignore hazards that are contained within the first IGNORE
3403 instructions of HIST.
3405 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3406 for the data cache refills and store data. The following describes
3407 the scenario where the store data could be lost.
3409 * A data cache miss, due to either a load or a store, causing fill
3410 data to be supplied by the memory subsystem
3411 * The first three doublewords of fill data are returned and written
3413 * A sequence of four stores occurs in consecutive cycles around the
3414 final doubleword of the fill:
3418 * Zero, One or more instructions
3421 The four stores A-D must be to different doublewords of the line that
3422 is being filled. The fourth instruction in the sequence above permits
3423 the fill of the final doubleword to be transferred from the FSB into
3424 the cache. In the sequence above, the stores may be either integer
3425 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3426 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3427 different doublewords on the line. If the floating point unit is
3428 running in 1:2 mode, it is not possible to create the sequence above
3429 using only floating point store instructions.
3431 In this case, the cache line being filled is incorrectly marked
3432 invalid, thereby losing the data from any store to the line that
3433 occurs between the original miss and the completion of the five
3434 cycle sequence shown above.
3436 The workarounds are:
3438 * Run the data cache in write-through mode.
3439 * Insert a non-store instruction between
3440 Store A and Store B or Store B and Store C. */
3443 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3444 const struct mips_cl_insn *insn)
3446 struct fix_24k_store_info pos[3];
3447 int align, i, base_offset;
3452 /* If the previous instruction wasn't a store, there's nothing to
3454 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3457 /* If the instructions after the previous one are unknown, we have
3458 to assume the worst. */
3462 /* Check whether we are dealing with three consecutive stores. */
3463 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3464 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3467 /* If we don't know the relationship between the store addresses,
3468 assume the worst. */
3469 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3470 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3473 if (!fix_24k_record_store_info (&pos[0], insn)
3474 || !fix_24k_record_store_info (&pos[1], &hist[0])
3475 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3478 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3480 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3481 X bytes and such that the base register + X is known to be aligned
3484 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3488 align = pos[0].align_to;
3489 base_offset = pos[0].off;
3490 for (i = 1; i < 3; i++)
3491 if (align < pos[i].align_to)
3493 align = pos[i].align_to;
3494 base_offset = pos[i].off;
3496 for (i = 0; i < 3; i++)
3497 pos[i].off -= base_offset;
3500 pos[0].off &= ~align + 1;
3501 pos[1].off &= ~align + 1;
3502 pos[2].off &= ~align + 1;
3504 /* If any two stores write to the same chunk, they also write to the
3505 same doubleword. The offsets are still sorted at this point. */
3506 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3509 /* A range of at least 9 bytes is needed for the stores to be in
3510 non-overlapping doublewords. */
3511 if (pos[2].off - pos[0].off <= 8)
3514 if (pos[2].off - pos[1].off >= 24
3515 || pos[1].off - pos[0].off >= 24
3516 || pos[2].off - pos[0].off >= 32)
3522 /* Return the number of nops that would be needed if instruction INSN
3523 immediately followed the MAX_NOPS instructions given by HIST,
3524 where HIST[0] is the most recent instruction. Ignore hazards
3525 between INSN and the first IGNORE instructions in HIST.
3527 If INSN is null, return the worse-case number of nops for any
3531 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3532 const struct mips_cl_insn *insn)
3534 int i, nops, tmp_nops;
3537 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3539 tmp_nops = insns_between (hist + i, insn) - i;
3540 if (tmp_nops > nops)
3544 if (mips_fix_vr4130 && !mips_opts.micromips)
3546 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3547 if (tmp_nops > nops)
3551 if (mips_fix_24k && !mips_opts.micromips)
3553 tmp_nops = nops_for_24k (ignore, hist, insn);
3554 if (tmp_nops > nops)
3561 /* The variable arguments provide NUM_INSNS extra instructions that
3562 might be added to HIST. Return the largest number of nops that
3563 would be needed after the extended sequence, ignoring hazards
3564 in the first IGNORE instructions. */
3567 nops_for_sequence (int num_insns, int ignore,
3568 const struct mips_cl_insn *hist, ...)
3571 struct mips_cl_insn buffer[MAX_NOPS];
3572 struct mips_cl_insn *cursor;
3575 va_start (args, hist);
3576 cursor = buffer + num_insns;
3577 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3578 while (cursor > buffer)
3579 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3581 nops = nops_for_insn (ignore, buffer, NULL);
3586 /* Like nops_for_insn, but if INSN is a branch, take into account the
3587 worst-case delay for the branch target. */
3590 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3591 const struct mips_cl_insn *insn)
3595 nops = nops_for_insn (ignore, hist, insn);
3596 if (delayed_branch_p (insn))
3598 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3599 hist, insn, get_delay_slot_nop (insn));
3600 if (tmp_nops > nops)
3603 else if (compact_branch_p (insn))
3605 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3606 if (tmp_nops > nops)
3612 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3615 fix_loongson2f_nop (struct mips_cl_insn * ip)
3617 gas_assert (!HAVE_CODE_COMPRESSION);
3618 if (strcmp (ip->insn_mo->name, "nop") == 0)
3619 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3622 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3623 jr target pc &= 'hffff_ffff_cfff_ffff. */
3626 fix_loongson2f_jump (struct mips_cl_insn * ip)
3628 gas_assert (!HAVE_CODE_COMPRESSION);
3629 if (strcmp (ip->insn_mo->name, "j") == 0
3630 || strcmp (ip->insn_mo->name, "jr") == 0
3631 || strcmp (ip->insn_mo->name, "jalr") == 0)
3639 sreg = EXTRACT_OPERAND (0, RS, *ip);
3640 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3643 ep.X_op = O_constant;
3644 ep.X_add_number = 0xcfff0000;
3645 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3646 ep.X_add_number = 0xffff;
3647 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3648 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3653 fix_loongson2f (struct mips_cl_insn * ip)
3655 if (mips_fix_loongson2f_nop)
3656 fix_loongson2f_nop (ip);
3658 if (mips_fix_loongson2f_jump)
3659 fix_loongson2f_jump (ip);
3662 /* IP is a branch that has a delay slot, and we need to fill it
3663 automatically. Return true if we can do that by swapping IP
3664 with the previous instruction. */
3667 can_swap_branch_p (struct mips_cl_insn *ip)
3669 unsigned long pinfo, pinfo2, prev_pinfo;
3670 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3672 /* For microMIPS, disable reordering. */
3673 if (mips_opts.micromips)
3676 /* -O2 and above is required for this optimization. */
3677 if (mips_optimize < 2)
3680 /* If we have seen .set volatile or .set nomove, don't optimize. */
3681 if (mips_opts.nomove)
3684 /* We can't swap if the previous instruction's position is fixed. */
3685 if (history[0].fixed_p)
3688 /* If the previous previous insn was in a .set noreorder, we can't
3689 swap. Actually, the MIPS assembler will swap in this situation.
3690 However, gcc configured -with-gnu-as will generate code like
3698 in which we can not swap the bne and INSN. If gcc is not configured
3699 -with-gnu-as, it does not output the .set pseudo-ops. */
3700 if (history[1].noreorder_p)
3703 /* If the previous instruction had a fixup in mips16 mode, we can not
3704 swap. This normally means that the previous instruction was a 4
3705 byte branch anyhow. */
3706 if (mips_opts.mips16 && history[0].fixp[0])
3709 /* If the branch is itself the target of a branch, we can not swap.
3710 We cheat on this; all we check for is whether there is a label on
3711 this instruction. If there are any branches to anything other than
3712 a label, users must use .set noreorder. */
3713 if (seg_info (now_seg)->label_list)
3716 /* If the previous instruction is in a variant frag other than this
3717 branch's one, we cannot do the swap. This does not apply to
3718 MIPS16/microMIPS code, which uses variant frags for different
3720 if (!HAVE_CODE_COMPRESSION
3722 && history[0].frag->fr_type == rs_machine_dependent)
3725 /* We do not swap with instructions that cannot architecturally
3726 be placed in a branch delay slot, such as SYNC or ERET. We
3727 also refrain from swapping with a trap instruction, since it
3728 complicates trap handlers to have the trap instruction be in
3730 prev_pinfo = history[0].insn_mo->pinfo;
3731 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3734 /* Check for conflicts between the branch and the instructions
3735 before the candidate delay slot. */
3736 if (nops_for_insn (0, history + 1, ip) > 0)
3739 /* Check for conflicts between the swapped sequence and the
3740 target of the branch. */
3741 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3744 /* If the branch reads a register that the previous
3745 instruction sets, we can not swap. */
3746 gpr_read = gpr_read_mask (ip);
3747 prev_gpr_write = gpr_write_mask (&history[0]);
3748 if (gpr_read & prev_gpr_write)
3751 /* If the branch writes a register that the previous
3752 instruction sets, we can not swap. */
3753 gpr_write = gpr_write_mask (ip);
3754 if (gpr_write & prev_gpr_write)
3757 /* If the branch writes a register that the previous
3758 instruction reads, we can not swap. */
3759 prev_gpr_read = gpr_read_mask (&history[0]);
3760 if (gpr_write & prev_gpr_read)
3763 /* If one instruction sets a condition code and the
3764 other one uses a condition code, we can not swap. */
3765 pinfo = ip->insn_mo->pinfo;
3766 if ((pinfo & INSN_READ_COND_CODE)
3767 && (prev_pinfo & INSN_WRITE_COND_CODE))
3769 if ((pinfo & INSN_WRITE_COND_CODE)
3770 && (prev_pinfo & INSN_READ_COND_CODE))
3773 /* If the previous instruction uses the PC, we can not swap. */
3774 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3777 /* If the previous instruction has an incorrect size for a fixed
3778 branch delay slot in microMIPS mode, we cannot swap. */
3779 pinfo2 = ip->insn_mo->pinfo2;
3780 if (mips_opts.micromips
3781 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3782 && insn_length (history) != 2)
3784 if (mips_opts.micromips
3785 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3786 && insn_length (history) != 4)
3792 /* Decide how we should add IP to the instruction stream. */
3794 static enum append_method
3795 get_append_method (struct mips_cl_insn *ip)
3797 unsigned long pinfo;
3799 /* The relaxed version of a macro sequence must be inherently
3801 if (mips_relax.sequence == 2)
3804 /* We must not dabble with instructions in a ".set norerorder" block. */
3805 if (mips_opts.noreorder)
3808 /* Otherwise, it's our responsibility to fill branch delay slots. */
3809 if (delayed_branch_p (ip))
3811 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3814 pinfo = ip->insn_mo->pinfo;
3815 if (mips_opts.mips16
3816 && ISA_SUPPORTS_MIPS16E
3817 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3818 return APPEND_ADD_COMPACT;
3820 return APPEND_ADD_WITH_NOP;
3826 /* IP is a MIPS16 instruction whose opcode we have just changed.
3827 Point IP->insn_mo to the new opcode's definition. */
3830 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3832 const struct mips_opcode *mo, *end;
3834 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3835 for (mo = ip->insn_mo; mo < end; mo++)
3836 if ((ip->insn_opcode & mo->mask) == mo->match)
3844 /* For microMIPS macros, we need to generate a local number label
3845 as the target of branches. */
3846 #define MICROMIPS_LABEL_CHAR '\037'
3847 static unsigned long micromips_target_label;
3848 static char micromips_target_name[32];
3851 micromips_label_name (void)
3853 char *p = micromips_target_name;
3854 char symbol_name_temporary[24];
3862 l = micromips_target_label;
3863 #ifdef LOCAL_LABEL_PREFIX
3864 *p++ = LOCAL_LABEL_PREFIX;
3867 *p++ = MICROMIPS_LABEL_CHAR;
3870 symbol_name_temporary[i++] = l % 10 + '0';
3875 *p++ = symbol_name_temporary[--i];
3878 return micromips_target_name;
3882 micromips_label_expr (expressionS *label_expr)
3884 label_expr->X_op = O_symbol;
3885 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3886 label_expr->X_add_number = 0;
3890 micromips_label_inc (void)
3892 micromips_target_label++;
3893 *micromips_target_name = '\0';
3897 micromips_add_label (void)
3901 s = colon (micromips_label_name ());
3902 micromips_label_inc ();
3903 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3905 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3909 /* If assembling microMIPS code, then return the microMIPS reloc
3910 corresponding to the requested one if any. Otherwise return
3911 the reloc unchanged. */
3913 static bfd_reloc_code_real_type
3914 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3916 static const bfd_reloc_code_real_type relocs[][2] =
3918 /* Keep sorted incrementally by the left-hand key. */
3919 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3920 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3921 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3922 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3923 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3924 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3925 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3926 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3927 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3928 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3929 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3930 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3931 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3932 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3933 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3934 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3935 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3936 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3937 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3938 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3939 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3940 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3941 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3942 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3943 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3944 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3945 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3947 bfd_reloc_code_real_type r;
3950 if (!mips_opts.micromips)
3952 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3958 return relocs[i][1];
3963 /* Output an instruction. IP is the instruction information.
3964 ADDRESS_EXPR is an operand of the instruction to be used with
3965 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3966 a macro expansion. */
3969 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3970 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3972 unsigned long prev_pinfo2, pinfo;
3973 bfd_boolean relaxed_branch = FALSE;
3974 enum append_method method;
3975 bfd_boolean relax32;
3977 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3978 fix_loongson2f (ip);
3980 mips_mark_labels ();
3982 file_ase_mips16 |= mips_opts.mips16;
3983 file_ase_micromips |= mips_opts.micromips;
3985 prev_pinfo2 = history[0].insn_mo->pinfo2;
3986 pinfo = ip->insn_mo->pinfo;
3988 if (mips_opts.micromips
3990 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3991 && micromips_insn_length (ip->insn_mo) != 2)
3992 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3993 && micromips_insn_length (ip->insn_mo) != 4)))
3994 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
3995 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
3997 if (address_expr == NULL)
3999 else if (*reloc_type <= BFD_RELOC_UNUSED
4000 && address_expr->X_op == O_constant)
4005 switch (*reloc_type)
4008 ip->insn_opcode |= address_expr->X_add_number;
4011 case BFD_RELOC_MIPS_HIGHEST:
4012 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4013 ip->insn_opcode |= tmp & 0xffff;
4016 case BFD_RELOC_MIPS_HIGHER:
4017 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4018 ip->insn_opcode |= tmp & 0xffff;
4021 case BFD_RELOC_HI16_S:
4022 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4023 ip->insn_opcode |= tmp & 0xffff;
4026 case BFD_RELOC_HI16:
4027 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4030 case BFD_RELOC_UNUSED:
4031 case BFD_RELOC_LO16:
4032 case BFD_RELOC_MIPS_GOT_DISP:
4033 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4036 case BFD_RELOC_MIPS_JMP:
4040 shift = mips_opts.micromips ? 1 : 2;
4041 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4042 as_bad (_("jump to misaligned address (0x%lx)"),
4043 (unsigned long) address_expr->X_add_number);
4044 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4050 case BFD_RELOC_MIPS16_JMP:
4051 if ((address_expr->X_add_number & 3) != 0)
4052 as_bad (_("jump to misaligned address (0x%lx)"),
4053 (unsigned long) address_expr->X_add_number);
4055 (((address_expr->X_add_number & 0x7c0000) << 3)
4056 | ((address_expr->X_add_number & 0xf800000) >> 7)
4057 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4061 case BFD_RELOC_16_PCREL_S2:
4065 shift = mips_opts.micromips ? 1 : 2;
4066 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4067 as_bad (_("branch to misaligned address (0x%lx)"),
4068 (unsigned long) address_expr->X_add_number);
4069 if (!mips_relax_branch)
4071 if ((address_expr->X_add_number + (1 << (shift + 15)))
4072 & ~((1 << (shift + 16)) - 1))
4073 as_bad (_("branch address range overflow (0x%lx)"),
4074 (unsigned long) address_expr->X_add_number);
4075 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4087 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4089 /* There are a lot of optimizations we could do that we don't.
4090 In particular, we do not, in general, reorder instructions.
4091 If you use gcc with optimization, it will reorder
4092 instructions and generally do much more optimization then we
4093 do here; repeating all that work in the assembler would only
4094 benefit hand written assembly code, and does not seem worth
4096 int nops = (mips_optimize == 0
4097 ? nops_for_insn (0, history, NULL)
4098 : nops_for_insn_or_target (0, history, ip));
4102 unsigned long old_frag_offset;
4105 old_frag = frag_now;
4106 old_frag_offset = frag_now_fix ();
4108 for (i = 0; i < nops; i++)
4109 add_fixed_insn (NOP_INSN);
4110 insert_into_history (0, nops, NOP_INSN);
4114 listing_prev_line ();
4115 /* We may be at the start of a variant frag. In case we
4116 are, make sure there is enough space for the frag
4117 after the frags created by listing_prev_line. The
4118 argument to frag_grow here must be at least as large
4119 as the argument to all other calls to frag_grow in
4120 this file. We don't have to worry about being in the
4121 middle of a variant frag, because the variants insert
4122 all needed nop instructions themselves. */
4126 mips_move_labels ();
4128 #ifndef NO_ECOFF_DEBUGGING
4129 if (ECOFF_DEBUGGING)
4130 ecoff_fix_loc (old_frag, old_frag_offset);
4134 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4138 /* Work out how many nops in prev_nop_frag are needed by IP,
4139 ignoring hazards generated by the first prev_nop_frag_since
4141 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4142 gas_assert (nops <= prev_nop_frag_holds);
4144 /* Enforce NOPS as a minimum. */
4145 if (nops > prev_nop_frag_required)
4146 prev_nop_frag_required = nops;
4148 if (prev_nop_frag_holds == prev_nop_frag_required)
4150 /* Settle for the current number of nops. Update the history
4151 accordingly (for the benefit of any future .set reorder code). */
4152 prev_nop_frag = NULL;
4153 insert_into_history (prev_nop_frag_since,
4154 prev_nop_frag_holds, NOP_INSN);
4158 /* Allow this instruction to replace one of the nops that was
4159 tentatively added to prev_nop_frag. */
4160 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4161 prev_nop_frag_holds--;
4162 prev_nop_frag_since++;
4166 method = get_append_method (ip);
4169 /* The value passed to dwarf2_emit_insn is the distance between
4170 the beginning of the current instruction and the address that
4171 should be recorded in the debug tables. This is normally the
4174 For MIPS16/microMIPS debug info we want to use ISA-encoded
4175 addresses, so we use -1 for an address higher by one than the
4178 If the instruction produced is a branch that we will swap with
4179 the preceding instruction, then we add the displacement by which
4180 the branch will be moved backwards. This is more appropriate
4181 and for MIPS16/microMIPS code also prevents a debugger from
4182 placing a breakpoint in the middle of the branch (and corrupting
4183 code if software breakpoints are used). */
4184 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0)
4185 + (method == APPEND_SWAP ? insn_length (history) : 0));
4188 relax32 = (mips_relax_branch
4189 /* Don't try branch relaxation within .set nomacro, or within
4190 .set noat if we use $at for PIC computations. If it turns
4191 out that the branch was out-of-range, we'll get an error. */
4192 && !mips_opts.warn_about_macros
4193 && (mips_opts.at || mips_pic == NO_PIC)
4194 /* Don't relax BPOSGE32/64 as they have no complementing
4196 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4198 if (!HAVE_CODE_COMPRESSION
4201 && *reloc_type == BFD_RELOC_16_PCREL_S2
4202 && delayed_branch_p (ip))
4204 relaxed_branch = TRUE;
4205 add_relaxed_insn (ip, (relaxed_branch_length
4207 uncond_branch_p (ip) ? -1
4208 : branch_likely_p (ip) ? 1
4212 uncond_branch_p (ip),
4213 branch_likely_p (ip),
4214 pinfo & INSN_WRITE_GPR_31,
4216 address_expr->X_add_symbol,
4217 address_expr->X_add_number);
4218 *reloc_type = BFD_RELOC_UNUSED;
4220 else if (mips_opts.micromips
4222 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4223 || *reloc_type > BFD_RELOC_UNUSED)
4224 && (delayed_branch_p (ip) || compact_branch_p (ip))
4225 /* Don't try branch relaxation when users specify
4226 16-bit/32-bit instructions. */
4227 && !forced_insn_length)
4229 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4230 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4231 int uncond = uncond_branch_p (ip) ? -1 : 0;
4232 int compact = compact_branch_p (ip);
4233 int al = pinfo & INSN_WRITE_GPR_31;
4236 gas_assert (address_expr != NULL);
4237 gas_assert (!mips_relax.sequence);
4239 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4240 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4241 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4243 address_expr->X_add_symbol,
4244 address_expr->X_add_number);
4245 *reloc_type = BFD_RELOC_UNUSED;
4247 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4249 /* We need to set up a variant frag. */
4250 gas_assert (address_expr != NULL);
4251 add_relaxed_insn (ip, 4, 0,
4253 (*reloc_type - BFD_RELOC_UNUSED,
4254 forced_insn_length == 2, forced_insn_length == 4,
4255 delayed_branch_p (&history[0]),
4256 history[0].mips16_absolute_jump_p),
4257 make_expr_symbol (address_expr), 0);
4259 else if (mips_opts.mips16
4261 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4263 if (!delayed_branch_p (ip))
4264 /* Make sure there is enough room to swap this instruction with
4265 a following jump instruction. */
4267 add_fixed_insn (ip);
4271 if (mips_opts.mips16
4272 && mips_opts.noreorder
4273 && delayed_branch_p (&history[0]))
4274 as_warn (_("extended instruction in delay slot"));
4276 if (mips_relax.sequence)
4278 /* If we've reached the end of this frag, turn it into a variant
4279 frag and record the information for the instructions we've
4281 if (frag_room () < 4)
4282 relax_close_frag ();
4283 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4286 if (mips_relax.sequence != 2)
4288 if (mips_macro_warning.first_insn_sizes[0] == 0)
4289 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4290 mips_macro_warning.sizes[0] += insn_length (ip);
4291 mips_macro_warning.insns[0]++;
4293 if (mips_relax.sequence != 1)
4295 if (mips_macro_warning.first_insn_sizes[1] == 0)
4296 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4297 mips_macro_warning.sizes[1] += insn_length (ip);
4298 mips_macro_warning.insns[1]++;
4301 if (mips_opts.mips16)
4304 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4306 add_fixed_insn (ip);
4309 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4311 bfd_reloc_code_real_type final_type[3];
4312 reloc_howto_type *howto0;
4313 reloc_howto_type *howto;
4316 /* Perform any necessary conversion to microMIPS relocations
4317 and find out how many relocations there actually are. */
4318 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4319 final_type[i] = micromips_map_reloc (reloc_type[i]);
4321 /* In a compound relocation, it is the final (outermost)
4322 operator that determines the relocated field. */
4323 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4327 /* To reproduce this failure try assembling gas/testsuites/
4328 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4330 as_bad (_("Unsupported MIPS relocation number %d"),
4332 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4336 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4337 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4338 bfd_get_reloc_size (howto),
4340 howto0 && howto0->pc_relative,
4343 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4344 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4345 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4347 /* These relocations can have an addend that won't fit in
4348 4 octets for 64bit assembly. */
4350 && ! howto->partial_inplace
4351 && (reloc_type[0] == BFD_RELOC_16
4352 || reloc_type[0] == BFD_RELOC_32
4353 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4354 || reloc_type[0] == BFD_RELOC_GPREL16
4355 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4356 || reloc_type[0] == BFD_RELOC_GPREL32
4357 || reloc_type[0] == BFD_RELOC_64
4358 || reloc_type[0] == BFD_RELOC_CTOR
4359 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4360 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4361 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4362 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4363 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4364 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4365 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4366 || hi16_reloc_p (reloc_type[0])
4367 || lo16_reloc_p (reloc_type[0])))
4368 ip->fixp[0]->fx_no_overflow = 1;
4370 if (mips_relax.sequence)
4372 if (mips_relax.first_fixup == 0)
4373 mips_relax.first_fixup = ip->fixp[0];
4375 else if (reloc_needs_lo_p (*reloc_type))
4377 struct mips_hi_fixup *hi_fixup;
4379 /* Reuse the last entry if it already has a matching %lo. */
4380 hi_fixup = mips_hi_fixup_list;
4382 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4384 hi_fixup = ((struct mips_hi_fixup *)
4385 xmalloc (sizeof (struct mips_hi_fixup)));
4386 hi_fixup->next = mips_hi_fixup_list;
4387 mips_hi_fixup_list = hi_fixup;
4389 hi_fixup->fixp = ip->fixp[0];
4390 hi_fixup->seg = now_seg;
4393 /* Add fixups for the second and third relocations, if given.
4394 Note that the ABI allows the second relocation to be
4395 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4396 moment we only use RSS_UNDEF, but we could add support
4397 for the others if it ever becomes necessary. */
4398 for (i = 1; i < 3; i++)
4399 if (reloc_type[i] != BFD_RELOC_UNUSED)
4401 ip->fixp[i] = fix_new (ip->frag, ip->where,
4402 ip->fixp[0]->fx_size, NULL, 0,
4403 FALSE, final_type[i]);
4405 /* Use fx_tcbit to mark compound relocs. */
4406 ip->fixp[0]->fx_tcbit = 1;
4407 ip->fixp[i]->fx_tcbit = 1;
4412 /* Update the register mask information. */
4413 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4414 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4419 insert_into_history (0, 1, ip);
4422 case APPEND_ADD_WITH_NOP:
4424 struct mips_cl_insn *nop;
4426 insert_into_history (0, 1, ip);
4427 nop = get_delay_slot_nop (ip);
4428 add_fixed_insn (nop);
4429 insert_into_history (0, 1, nop);
4430 if (mips_relax.sequence)
4431 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4435 case APPEND_ADD_COMPACT:
4436 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4437 gas_assert (mips_opts.mips16);
4438 ip->insn_opcode |= 0x0080;
4439 find_altered_mips16_opcode (ip);
4441 insert_into_history (0, 1, ip);
4446 struct mips_cl_insn delay = history[0];
4447 if (mips_opts.mips16)
4449 know (delay.frag == ip->frag);
4450 move_insn (ip, delay.frag, delay.where);
4451 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4453 else if (mips_opts.micromips)
4455 /* We don't reorder for micromips. */
4458 else if (relaxed_branch)
4460 /* Add the delay slot instruction to the end of the
4461 current frag and shrink the fixed part of the
4462 original frag. If the branch occupies the tail of
4463 the latter, move it backwards to cover the gap. */
4464 delay.frag->fr_fix -= 4;
4465 if (delay.frag == ip->frag)
4466 move_insn (ip, ip->frag, ip->where - 4);
4467 add_fixed_insn (&delay);
4471 move_insn (&delay, ip->frag, ip->where);
4472 move_insn (ip, history[0].frag, history[0].where);
4476 insert_into_history (0, 1, &delay);
4481 /* If we have just completed an unconditional branch, clear the history. */
4482 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4483 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4484 mips_no_prev_insn ();
4486 /* We need to emit a label at the end of branch-likely macros. */
4487 if (emit_branch_likely_macro)
4489 emit_branch_likely_macro = FALSE;
4490 micromips_add_label ();
4493 /* We just output an insn, so the next one doesn't have a label. */
4494 mips_clear_insn_labels ();
4497 /* Forget that there was any previous instruction or label. */
4500 mips_no_prev_insn (void)
4502 prev_nop_frag = NULL;
4503 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4504 mips_clear_insn_labels ();
4507 /* This function must be called before we emit something other than
4508 instructions. It is like mips_no_prev_insn except that it inserts
4509 any NOPS that might be needed by previous instructions. */
4512 mips_emit_delays (void)
4514 if (! mips_opts.noreorder)
4516 int nops = nops_for_insn (0, history, NULL);
4520 add_fixed_insn (NOP_INSN);
4521 mips_move_labels ();
4524 mips_no_prev_insn ();
4527 /* Start a (possibly nested) noreorder block. */
4530 start_noreorder (void)
4532 if (mips_opts.noreorder == 0)
4537 /* None of the instructions before the .set noreorder can be moved. */
4538 for (i = 0; i < ARRAY_SIZE (history); i++)
4539 history[i].fixed_p = 1;
4541 /* Insert any nops that might be needed between the .set noreorder
4542 block and the previous instructions. We will later remove any
4543 nops that turn out not to be needed. */
4544 nops = nops_for_insn (0, history, NULL);
4547 if (mips_optimize != 0)
4549 /* Record the frag which holds the nop instructions, so
4550 that we can remove them if we don't need them. */
4551 frag_grow (nops * NOP_INSN_SIZE);
4552 prev_nop_frag = frag_now;
4553 prev_nop_frag_holds = nops;
4554 prev_nop_frag_required = 0;
4555 prev_nop_frag_since = 0;
4558 for (; nops > 0; --nops)
4559 add_fixed_insn (NOP_INSN);
4561 /* Move on to a new frag, so that it is safe to simply
4562 decrease the size of prev_nop_frag. */
4563 frag_wane (frag_now);
4565 mips_move_labels ();
4567 mips_mark_labels ();
4568 mips_clear_insn_labels ();
4570 mips_opts.noreorder++;
4571 mips_any_noreorder = 1;
4574 /* End a nested noreorder block. */
4577 end_noreorder (void)
4580 mips_opts.noreorder--;
4581 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4583 /* Commit to inserting prev_nop_frag_required nops and go back to
4584 handling nop insertion the .set reorder way. */
4585 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4587 insert_into_history (prev_nop_frag_since,
4588 prev_nop_frag_required, NOP_INSN);
4589 prev_nop_frag = NULL;
4593 /* Set up global variables for the start of a new macro. */
4598 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4599 memset (&mips_macro_warning.first_insn_sizes, 0,
4600 sizeof (mips_macro_warning.first_insn_sizes));
4601 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4602 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4603 && delayed_branch_p (&history[0]));
4604 switch (history[0].insn_mo->pinfo2
4605 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4607 case INSN2_BRANCH_DELAY_32BIT:
4608 mips_macro_warning.delay_slot_length = 4;
4610 case INSN2_BRANCH_DELAY_16BIT:
4611 mips_macro_warning.delay_slot_length = 2;
4614 mips_macro_warning.delay_slot_length = 0;
4617 mips_macro_warning.first_frag = NULL;
4620 /* Given that a macro is longer than one instruction or of the wrong size,
4621 return the appropriate warning for it. Return null if no warning is
4622 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4623 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4624 and RELAX_NOMACRO. */
4627 macro_warning (relax_substateT subtype)
4629 if (subtype & RELAX_DELAY_SLOT)
4630 return _("Macro instruction expanded into multiple instructions"
4631 " in a branch delay slot");
4632 else if (subtype & RELAX_NOMACRO)
4633 return _("Macro instruction expanded into multiple instructions");
4634 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4635 | RELAX_DELAY_SLOT_SIZE_SECOND))
4636 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4637 ? _("Macro instruction expanded into a wrong size instruction"
4638 " in a 16-bit branch delay slot")
4639 : _("Macro instruction expanded into a wrong size instruction"
4640 " in a 32-bit branch delay slot"));
4645 /* Finish up a macro. Emit warnings as appropriate. */
4650 /* Relaxation warning flags. */
4651 relax_substateT subtype = 0;
4653 /* Check delay slot size requirements. */
4654 if (mips_macro_warning.delay_slot_length == 2)
4655 subtype |= RELAX_DELAY_SLOT_16BIT;
4656 if (mips_macro_warning.delay_slot_length != 0)
4658 if (mips_macro_warning.delay_slot_length
4659 != mips_macro_warning.first_insn_sizes[0])
4660 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4661 if (mips_macro_warning.delay_slot_length
4662 != mips_macro_warning.first_insn_sizes[1])
4663 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4666 /* Check instruction count requirements. */
4667 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4669 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4670 subtype |= RELAX_SECOND_LONGER;
4671 if (mips_opts.warn_about_macros)
4672 subtype |= RELAX_NOMACRO;
4673 if (mips_macro_warning.delay_slot_p)
4674 subtype |= RELAX_DELAY_SLOT;
4677 /* If both alternatives fail to fill a delay slot correctly,
4678 emit the warning now. */
4679 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4680 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4685 s = subtype & (RELAX_DELAY_SLOT_16BIT
4686 | RELAX_DELAY_SLOT_SIZE_FIRST
4687 | RELAX_DELAY_SLOT_SIZE_SECOND);
4688 msg = macro_warning (s);
4690 as_warn ("%s", msg);
4694 /* If both implementations are longer than 1 instruction, then emit the
4696 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4701 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4702 msg = macro_warning (s);
4704 as_warn ("%s", msg);
4708 /* If any flags still set, then one implementation might need a warning
4709 and the other either will need one of a different kind or none at all.
4710 Pass any remaining flags over to relaxation. */
4711 if (mips_macro_warning.first_frag != NULL)
4712 mips_macro_warning.first_frag->fr_subtype |= subtype;
4715 /* Instruction operand formats used in macros that vary between
4716 standard MIPS and microMIPS code. */
4718 static const char * const brk_fmt[2] = { "c", "mF" };
4719 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4720 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4721 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4722 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4723 static const char * const mfhl_fmt[2] = { "d", "mj" };
4724 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4725 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4727 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4728 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4729 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4730 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4731 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4732 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4733 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4734 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4736 /* Read a macro's relocation codes from *ARGS and store them in *R.
4737 The first argument in *ARGS will be either the code for a single
4738 relocation or -1 followed by the three codes that make up a
4739 composite relocation. */
4742 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4746 next = va_arg (*args, int);
4748 r[0] = (bfd_reloc_code_real_type) next;
4750 for (i = 0; i < 3; i++)
4751 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4754 /* Build an instruction created by a macro expansion. This is passed
4755 a pointer to the count of instructions created so far, an
4756 expression, the name of the instruction to build, an operand format
4757 string, and corresponding arguments. */
4760 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4762 const struct mips_opcode *mo = NULL;
4763 bfd_reloc_code_real_type r[3];
4764 const struct mips_opcode *amo;
4765 struct hash_control *hash;
4766 struct mips_cl_insn insn;
4769 va_start (args, fmt);
4771 if (mips_opts.mips16)
4773 mips16_macro_build (ep, name, fmt, &args);
4778 r[0] = BFD_RELOC_UNUSED;
4779 r[1] = BFD_RELOC_UNUSED;
4780 r[2] = BFD_RELOC_UNUSED;
4781 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4782 amo = (struct mips_opcode *) hash_find (hash, name);
4784 gas_assert (strcmp (name, amo->name) == 0);
4788 /* Search until we get a match for NAME. It is assumed here that
4789 macros will never generate MDMX, MIPS-3D, or MT instructions.
4790 We try to match an instruction that fulfils the branch delay
4791 slot instruction length requirement (if any) of the previous
4792 instruction. While doing this we record the first instruction
4793 seen that matches all the other conditions and use it anyway
4794 if the requirement cannot be met; we will issue an appropriate
4795 warning later on. */
4796 if (strcmp (fmt, amo->args) == 0
4797 && amo->pinfo != INSN_MACRO
4798 && is_opcode_valid (amo)
4799 && is_size_valid (amo))
4801 if (is_delay_slot_valid (amo))
4811 gas_assert (amo->name);
4813 while (strcmp (name, amo->name) == 0);
4816 create_insn (&insn, mo);
4834 INSERT_OPERAND (mips_opts.micromips,
4835 EXTLSB, insn, va_arg (args, int));
4840 /* Note that in the macro case, these arguments are already
4841 in MSB form. (When handling the instruction in the
4842 non-macro case, these arguments are sizes from which
4843 MSB values must be calculated.) */
4844 INSERT_OPERAND (mips_opts.micromips,
4845 INSMSB, insn, va_arg (args, int));
4851 /* Note that in the macro case, these arguments are already
4852 in MSBD form. (When handling the instruction in the
4853 non-macro case, these arguments are sizes from which
4854 MSBD values must be calculated.) */
4855 INSERT_OPERAND (mips_opts.micromips,
4856 EXTMSBD, insn, va_arg (args, int));
4860 gas_assert (!mips_opts.micromips);
4861 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4870 gas_assert (!mips_opts.micromips);
4871 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
4875 gas_assert (mips_opts.micromips);
4879 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4883 gas_assert (!mips_opts.micromips);
4884 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4888 gas_assert (!mips_opts.micromips);
4890 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4894 if (mips_opts.micromips)
4895 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4897 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4901 gas_assert (!mips_opts.micromips);
4903 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4907 gas_assert (!mips_opts.micromips);
4909 int tmp = va_arg (args, int);
4911 INSERT_OPERAND (0, RT, insn, tmp);
4912 INSERT_OPERAND (0, RD, insn, tmp);
4918 gas_assert (!mips_opts.micromips);
4919 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4926 INSERT_OPERAND (mips_opts.micromips,
4927 SHAMT, insn, va_arg (args, int));
4931 gas_assert (!mips_opts.micromips);
4932 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4936 gas_assert (!mips_opts.micromips);
4937 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4941 gas_assert (!mips_opts.micromips);
4942 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4946 gas_assert (!mips_opts.micromips);
4947 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4954 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4959 macro_read_relocs (&args, r);
4960 gas_assert (*r == BFD_RELOC_GPREL16
4961 || *r == BFD_RELOC_MIPS_HIGHER
4962 || *r == BFD_RELOC_HI16_S
4963 || *r == BFD_RELOC_LO16
4964 || *r == BFD_RELOC_MIPS_GOT_OFST);
4968 macro_read_relocs (&args, r);
4972 macro_read_relocs (&args, r);
4973 gas_assert (ep != NULL
4974 && (ep->X_op == O_constant
4975 || (ep->X_op == O_symbol
4976 && (*r == BFD_RELOC_MIPS_HIGHEST
4977 || *r == BFD_RELOC_HI16_S
4978 || *r == BFD_RELOC_HI16
4979 || *r == BFD_RELOC_GPREL16
4980 || *r == BFD_RELOC_MIPS_GOT_HI16
4981 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4985 gas_assert (ep != NULL);
4988 * This allows macro() to pass an immediate expression for
4989 * creating short branches without creating a symbol.
4991 * We don't allow branch relaxation for these branches, as
4992 * they should only appear in ".set nomacro" anyway.
4994 if (ep->X_op == O_constant)
4996 /* For microMIPS we always use relocations for branches.
4997 So we should not resolve immediate values. */
4998 gas_assert (!mips_opts.micromips);
5000 if ((ep->X_add_number & 3) != 0)
5001 as_bad (_("branch to misaligned address (0x%lx)"),
5002 (unsigned long) ep->X_add_number);
5003 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5004 as_bad (_("branch address range overflow (0x%lx)"),
5005 (unsigned long) ep->X_add_number);
5006 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5010 *r = BFD_RELOC_16_PCREL_S2;
5014 gas_assert (ep != NULL);
5015 *r = BFD_RELOC_MIPS_JMP;
5019 gas_assert (!mips_opts.micromips);
5020 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5024 INSERT_OPERAND (mips_opts.micromips,
5025 CACHE, insn, va_arg (args, unsigned long));
5029 gas_assert (mips_opts.micromips);
5030 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5034 gas_assert (mips_opts.micromips);
5035 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5039 gas_assert (mips_opts.micromips);
5040 INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long));
5044 gas_assert (mips_opts.micromips);
5045 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5048 case 'm': /* Opcode extension character. */
5049 gas_assert (mips_opts.micromips);
5053 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5057 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5061 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5075 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5077 append_insn (&insn, ep, r, TRUE);
5081 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5084 struct mips_opcode *mo;
5085 struct mips_cl_insn insn;
5086 bfd_reloc_code_real_type r[3]
5087 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5089 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5091 gas_assert (strcmp (name, mo->name) == 0);
5093 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5096 gas_assert (mo->name);
5097 gas_assert (strcmp (name, mo->name) == 0);
5100 create_insn (&insn, mo);
5118 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5123 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5127 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5131 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5141 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5148 regno = va_arg (*args, int);
5149 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5150 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5171 gas_assert (ep != NULL);
5173 if (ep->X_op != O_constant)
5174 *r = (int) BFD_RELOC_UNUSED + c;
5177 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5178 FALSE, &insn.insn_opcode, &insn.use_extend,
5181 *r = BFD_RELOC_UNUSED;
5187 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5194 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5196 append_insn (&insn, ep, r, TRUE);
5200 * Sign-extend 32-bit mode constants that have bit 31 set and all
5201 * higher bits unset.
5204 normalize_constant_expr (expressionS *ex)
5206 if (ex->X_op == O_constant
5207 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5208 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5213 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5214 * all higher bits unset.
5217 normalize_address_expr (expressionS *ex)
5219 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5220 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5221 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5222 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5227 * Generate a "jalr" instruction with a relocation hint to the called
5228 * function. This occurs in NewABI PIC code.
5231 macro_build_jalr (expressionS *ep, int cprestore)
5233 static const bfd_reloc_code_real_type jalr_relocs[2]
5234 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5235 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5239 if (MIPS_JALR_HINT_P (ep))
5244 if (!mips_opts.micromips)
5245 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5248 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5249 if (MIPS_JALR_HINT_P (ep))
5250 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5252 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5254 if (MIPS_JALR_HINT_P (ep))
5255 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5259 * Generate a "lui" instruction.
5262 macro_build_lui (expressionS *ep, int regnum)
5264 gas_assert (! mips_opts.mips16);
5266 if (ep->X_op != O_constant)
5268 gas_assert (ep->X_op == O_symbol);
5269 /* _gp_disp is a special case, used from s_cpload.
5270 __gnu_local_gp is used if mips_no_shared. */
5271 gas_assert (mips_pic == NO_PIC
5273 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5274 || (! mips_in_shared
5275 && strcmp (S_GET_NAME (ep->X_add_symbol),
5276 "__gnu_local_gp") == 0));
5279 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5282 /* Generate a sequence of instructions to do a load or store from a constant
5283 offset off of a base register (breg) into/from a target register (treg),
5284 using AT if necessary. */
5286 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5287 int treg, int breg, int dbl)
5289 gas_assert (ep->X_op == O_constant);
5291 /* Sign-extending 32-bit constants makes their handling easier. */
5293 normalize_constant_expr (ep);
5295 /* Right now, this routine can only handle signed 32-bit constants. */
5296 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5297 as_warn (_("operand overflow"));
5299 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5301 /* Signed 16-bit offset will fit in the op. Easy! */
5302 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5306 /* 32-bit offset, need multiple instructions and AT, like:
5307 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5308 addu $tempreg,$tempreg,$breg
5309 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5310 to handle the complete offset. */
5311 macro_build_lui (ep, AT);
5312 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5313 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5316 as_bad (_("Macro used $at after \".set noat\""));
5321 * Generates code to set the $at register to true (one)
5322 * if reg is less than the immediate expression.
5325 set_at (int reg, int unsignedp)
5327 if (imm_expr.X_op == O_constant
5328 && imm_expr.X_add_number >= -0x8000
5329 && imm_expr.X_add_number < 0x8000)
5330 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5331 AT, reg, BFD_RELOC_LO16);
5334 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5335 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5339 /* Warn if an expression is not a constant. */
5342 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5344 if (ex->X_op == O_big)
5345 as_bad (_("unsupported large constant"));
5346 else if (ex->X_op != O_constant)
5347 as_bad (_("Instruction %s requires absolute expression"),
5350 if (HAVE_32BIT_GPRS)
5351 normalize_constant_expr (ex);
5354 /* Count the leading zeroes by performing a binary chop. This is a
5355 bulky bit of source, but performance is a LOT better for the
5356 majority of values than a simple loop to count the bits:
5357 for (lcnt = 0; (lcnt < 32); lcnt++)
5358 if ((v) & (1 << (31 - lcnt)))
5360 However it is not code size friendly, and the gain will drop a bit
5361 on certain cached systems.
5363 #define COUNT_TOP_ZEROES(v) \
5364 (((v) & ~0xffff) == 0 \
5365 ? ((v) & ~0xff) == 0 \
5366 ? ((v) & ~0xf) == 0 \
5367 ? ((v) & ~0x3) == 0 \
5368 ? ((v) & ~0x1) == 0 \
5373 : ((v) & ~0x7) == 0 \
5376 : ((v) & ~0x3f) == 0 \
5377 ? ((v) & ~0x1f) == 0 \
5380 : ((v) & ~0x7f) == 0 \
5383 : ((v) & ~0xfff) == 0 \
5384 ? ((v) & ~0x3ff) == 0 \
5385 ? ((v) & ~0x1ff) == 0 \
5388 : ((v) & ~0x7ff) == 0 \
5391 : ((v) & ~0x3fff) == 0 \
5392 ? ((v) & ~0x1fff) == 0 \
5395 : ((v) & ~0x7fff) == 0 \
5398 : ((v) & ~0xffffff) == 0 \
5399 ? ((v) & ~0xfffff) == 0 \
5400 ? ((v) & ~0x3ffff) == 0 \
5401 ? ((v) & ~0x1ffff) == 0 \
5404 : ((v) & ~0x7ffff) == 0 \
5407 : ((v) & ~0x3fffff) == 0 \
5408 ? ((v) & ~0x1fffff) == 0 \
5411 : ((v) & ~0x7fffff) == 0 \
5414 : ((v) & ~0xfffffff) == 0 \
5415 ? ((v) & ~0x3ffffff) == 0 \
5416 ? ((v) & ~0x1ffffff) == 0 \
5419 : ((v) & ~0x7ffffff) == 0 \
5422 : ((v) & ~0x3fffffff) == 0 \
5423 ? ((v) & ~0x1fffffff) == 0 \
5426 : ((v) & ~0x7fffffff) == 0 \
5431 * This routine generates the least number of instructions necessary to load
5432 * an absolute expression value into a register.
5435 load_register (int reg, expressionS *ep, int dbl)
5438 expressionS hi32, lo32;
5440 if (ep->X_op != O_big)
5442 gas_assert (ep->X_op == O_constant);
5444 /* Sign-extending 32-bit constants makes their handling easier. */
5446 normalize_constant_expr (ep);
5448 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5450 /* We can handle 16 bit signed values with an addiu to
5451 $zero. No need to ever use daddiu here, since $zero and
5452 the result are always correct in 32 bit mode. */
5453 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5456 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5458 /* We can handle 16 bit unsigned values with an ori to
5460 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5463 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5465 /* 32 bit values require an lui. */
5466 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5467 if ((ep->X_add_number & 0xffff) != 0)
5468 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5473 /* The value is larger than 32 bits. */
5475 if (!dbl || HAVE_32BIT_GPRS)
5479 sprintf_vma (value, ep->X_add_number);
5480 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5481 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5485 if (ep->X_op != O_big)
5488 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5489 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5490 hi32.X_add_number &= 0xffffffff;
5492 lo32.X_add_number &= 0xffffffff;
5496 gas_assert (ep->X_add_number > 2);
5497 if (ep->X_add_number == 3)
5498 generic_bignum[3] = 0;
5499 else if (ep->X_add_number > 4)
5500 as_bad (_("Number larger than 64 bits"));
5501 lo32.X_op = O_constant;
5502 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5503 hi32.X_op = O_constant;
5504 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5507 if (hi32.X_add_number == 0)
5512 unsigned long hi, lo;
5514 if (hi32.X_add_number == (offsetT) 0xffffffff)
5516 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5518 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5521 if (lo32.X_add_number & 0x80000000)
5523 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5524 if (lo32.X_add_number & 0xffff)
5525 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5530 /* Check for 16bit shifted constant. We know that hi32 is
5531 non-zero, so start the mask on the first bit of the hi32
5536 unsigned long himask, lomask;
5540 himask = 0xffff >> (32 - shift);
5541 lomask = (0xffff << shift) & 0xffffffff;
5545 himask = 0xffff << (shift - 32);
5548 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5549 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5553 tmp.X_op = O_constant;
5555 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5556 | (lo32.X_add_number >> shift));
5558 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5559 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5560 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5561 reg, reg, (shift >= 32) ? shift - 32 : shift);
5566 while (shift <= (64 - 16));
5568 /* Find the bit number of the lowest one bit, and store the
5569 shifted value in hi/lo. */
5570 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5571 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5575 while ((lo & 1) == 0)
5580 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5586 while ((hi & 1) == 0)
5595 /* Optimize if the shifted value is a (power of 2) - 1. */
5596 if ((hi == 0 && ((lo + 1) & lo) == 0)
5597 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5599 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5604 /* This instruction will set the register to be all
5606 tmp.X_op = O_constant;
5607 tmp.X_add_number = (offsetT) -1;
5608 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5612 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5613 reg, reg, (bit >= 32) ? bit - 32 : bit);
5615 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5616 reg, reg, (shift >= 32) ? shift - 32 : shift);
5621 /* Sign extend hi32 before calling load_register, because we can
5622 generally get better code when we load a sign extended value. */
5623 if ((hi32.X_add_number & 0x80000000) != 0)
5624 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5625 load_register (reg, &hi32, 0);
5628 if ((lo32.X_add_number & 0xffff0000) == 0)
5632 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5640 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5642 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5643 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5649 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5653 mid16.X_add_number >>= 16;
5654 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5655 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5658 if ((lo32.X_add_number & 0xffff) != 0)
5659 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5663 load_delay_nop (void)
5665 if (!gpr_interlocks)
5666 macro_build (NULL, "nop", "");
5669 /* Load an address into a register. */
5672 load_address (int reg, expressionS *ep, int *used_at)
5674 if (ep->X_op != O_constant
5675 && ep->X_op != O_symbol)
5677 as_bad (_("expression too complex"));
5678 ep->X_op = O_constant;
5681 if (ep->X_op == O_constant)
5683 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5687 if (mips_pic == NO_PIC)
5689 /* If this is a reference to a GP relative symbol, we want
5690 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5692 lui $reg,<sym> (BFD_RELOC_HI16_S)
5693 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5694 If we have an addend, we always use the latter form.
5696 With 64bit address space and a usable $at we want
5697 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5698 lui $at,<sym> (BFD_RELOC_HI16_S)
5699 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5700 daddiu $at,<sym> (BFD_RELOC_LO16)
5704 If $at is already in use, we use a path which is suboptimal
5705 on superscalar processors.
5706 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5707 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5709 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5711 daddiu $reg,<sym> (BFD_RELOC_LO16)
5713 For GP relative symbols in 64bit address space we can use
5714 the same sequence as in 32bit address space. */
5715 if (HAVE_64BIT_SYMBOLS)
5717 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5718 && !nopic_need_relax (ep->X_add_symbol, 1))
5720 relax_start (ep->X_add_symbol);
5721 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5722 mips_gp_register, BFD_RELOC_GPREL16);
5726 if (*used_at == 0 && mips_opts.at)
5728 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5729 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5730 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5731 BFD_RELOC_MIPS_HIGHER);
5732 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5733 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5734 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5739 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5740 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5741 BFD_RELOC_MIPS_HIGHER);
5742 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5743 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5744 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5745 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5748 if (mips_relax.sequence)
5753 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5754 && !nopic_need_relax (ep->X_add_symbol, 1))
5756 relax_start (ep->X_add_symbol);
5757 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5758 mips_gp_register, BFD_RELOC_GPREL16);
5761 macro_build_lui (ep, reg);
5762 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5763 reg, reg, BFD_RELOC_LO16);
5764 if (mips_relax.sequence)
5768 else if (!mips_big_got)
5772 /* If this is a reference to an external symbol, we want
5773 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5775 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5777 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5778 If there is a constant, it must be added in after.
5780 If we have NewABI, we want
5781 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5782 unless we're referencing a global symbol with a non-zero
5783 offset, in which case cst must be added separately. */
5786 if (ep->X_add_number)
5788 ex.X_add_number = ep->X_add_number;
5789 ep->X_add_number = 0;
5790 relax_start (ep->X_add_symbol);
5791 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5792 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5793 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5794 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5795 ex.X_op = O_constant;
5796 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5797 reg, reg, BFD_RELOC_LO16);
5798 ep->X_add_number = ex.X_add_number;
5801 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5802 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5803 if (mips_relax.sequence)
5808 ex.X_add_number = ep->X_add_number;
5809 ep->X_add_number = 0;
5810 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5811 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5813 relax_start (ep->X_add_symbol);
5815 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5819 if (ex.X_add_number != 0)
5821 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5822 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5823 ex.X_op = O_constant;
5824 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5825 reg, reg, BFD_RELOC_LO16);
5829 else if (mips_big_got)
5833 /* This is the large GOT case. If this is a reference to an
5834 external symbol, we want
5835 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5837 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5839 Otherwise, for a reference to a local symbol in old ABI, we want
5840 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5842 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5843 If there is a constant, it must be added in after.
5845 In the NewABI, for local symbols, with or without offsets, we want:
5846 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5847 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5851 ex.X_add_number = ep->X_add_number;
5852 ep->X_add_number = 0;
5853 relax_start (ep->X_add_symbol);
5854 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5855 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5856 reg, reg, mips_gp_register);
5857 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5858 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5859 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5860 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5861 else if (ex.X_add_number)
5863 ex.X_op = O_constant;
5864 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5868 ep->X_add_number = ex.X_add_number;
5870 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5871 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5872 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5873 BFD_RELOC_MIPS_GOT_OFST);
5878 ex.X_add_number = ep->X_add_number;
5879 ep->X_add_number = 0;
5880 relax_start (ep->X_add_symbol);
5881 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5882 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5883 reg, reg, mips_gp_register);
5884 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5885 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5887 if (reg_needs_delay (mips_gp_register))
5889 /* We need a nop before loading from $gp. This special
5890 check is required because the lui which starts the main
5891 instruction stream does not refer to $gp, and so will not
5892 insert the nop which may be required. */
5893 macro_build (NULL, "nop", "");
5895 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5896 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5898 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5902 if (ex.X_add_number != 0)
5904 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5905 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5906 ex.X_op = O_constant;
5907 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5915 if (!mips_opts.at && *used_at == 1)
5916 as_bad (_("Macro used $at after \".set noat\""));
5919 /* Move the contents of register SOURCE into register DEST. */
5922 move_register (int dest, int source)
5924 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5925 instruction specifically requires a 32-bit one. */
5926 if (mips_opts.micromips
5927 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5928 macro_build (NULL, "move", "mp,mj", dest, source );
5930 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5934 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5935 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5936 The two alternatives are:
5938 Global symbol Local sybmol
5939 ------------- ------------
5940 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5942 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5944 load_got_offset emits the first instruction and add_got_offset
5945 emits the second for a 16-bit offset or add_got_offset_hilo emits
5946 a sequence to add a 32-bit offset using a scratch register. */
5949 load_got_offset (int dest, expressionS *local)
5954 global.X_add_number = 0;
5956 relax_start (local->X_add_symbol);
5957 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5958 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5960 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5961 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5966 add_got_offset (int dest, expressionS *local)
5970 global.X_op = O_constant;
5971 global.X_op_symbol = NULL;
5972 global.X_add_symbol = NULL;
5973 global.X_add_number = local->X_add_number;
5975 relax_start (local->X_add_symbol);
5976 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5977 dest, dest, BFD_RELOC_LO16);
5979 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5984 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5987 int hold_mips_optimize;
5989 global.X_op = O_constant;
5990 global.X_op_symbol = NULL;
5991 global.X_add_symbol = NULL;
5992 global.X_add_number = local->X_add_number;
5994 relax_start (local->X_add_symbol);
5995 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5997 /* Set mips_optimize around the lui instruction to avoid
5998 inserting an unnecessary nop after the lw. */
5999 hold_mips_optimize = mips_optimize;
6001 macro_build_lui (&global, tmp);
6002 mips_optimize = hold_mips_optimize;
6003 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6009 /* Emit a sequence of instructions to emulate a branch likely operation.
6010 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6011 is its complementing branch with the original condition negated.
6012 CALL is set if the original branch specified the link operation.
6013 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6015 Code like this is produced in the noreorder mode:
6020 delay slot (executed only if branch taken)
6028 delay slot (executed only if branch taken)
6031 In the reorder mode the delay slot would be filled with a nop anyway,
6032 so code produced is simply:
6037 This function is used when producing code for the microMIPS ASE that
6038 does not implement branch likely instructions in hardware. */
6041 macro_build_branch_likely (const char *br, const char *brneg,
6042 int call, expressionS *ep, const char *fmt,
6043 unsigned int sreg, unsigned int treg)
6045 int noreorder = mips_opts.noreorder;
6048 gas_assert (mips_opts.micromips);
6052 micromips_label_expr (&expr1);
6053 macro_build (&expr1, brneg, fmt, sreg, treg);
6054 macro_build (NULL, "nop", "");
6055 macro_build (ep, call ? "bal" : "b", "p");
6057 /* Set to true so that append_insn adds a label. */
6058 emit_branch_likely_macro = TRUE;
6062 macro_build (ep, br, fmt, sreg, treg);
6063 macro_build (NULL, "nop", "");
6068 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6069 the condition code tested. EP specifies the branch target. */
6072 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6099 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6102 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6103 the register tested. EP specifies the branch target. */
6106 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6108 const char *brneg = NULL;
6118 br = mips_opts.micromips ? "bgez" : "bgezl";
6122 gas_assert (mips_opts.micromips);
6131 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6138 br = mips_opts.micromips ? "blez" : "blezl";
6145 br = mips_opts.micromips ? "bltz" : "bltzl";
6149 gas_assert (mips_opts.micromips);
6157 if (mips_opts.micromips && brneg)
6158 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6160 macro_build (ep, br, "s,p", sreg);
6163 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6164 TREG as the registers tested. EP specifies the branch target. */
6167 macro_build_branch_rsrt (int type, expressionS *ep,
6168 unsigned int sreg, unsigned int treg)
6170 const char *brneg = NULL;
6182 br = mips_opts.micromips ? "beq" : "beql";
6191 br = mips_opts.micromips ? "bne" : "bnel";
6197 if (mips_opts.micromips && brneg)
6198 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6200 macro_build (ep, br, "s,t,p", sreg, treg);
6205 * This routine implements the seemingly endless macro or synthesized
6206 * instructions and addressing modes in the mips assembly language. Many
6207 * of these macros are simple and are similar to each other. These could
6208 * probably be handled by some kind of table or grammar approach instead of
6209 * this verbose method. Others are not simple macros but are more like
6210 * optimizing code generation.
6211 * One interesting optimization is when several store macros appear
6212 * consecutively that would load AT with the upper half of the same address.
6213 * The ensuing load upper instructions are ommited. This implies some kind
6214 * of global optimization. We currently only optimize within a single macro.
6215 * For many of the load and store macros if the address is specified as a
6216 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6217 * first load register 'at' with zero and use it as the base register. The
6218 * mips assembler simply uses register $zero. Just one tiny optimization
6222 macro (struct mips_cl_insn *ip)
6224 unsigned int treg, sreg, dreg, breg;
6225 unsigned int tempreg;
6228 expressionS label_expr;
6246 bfd_reloc_code_real_type r;
6247 int hold_mips_optimize;
6249 gas_assert (! mips_opts.mips16);
6251 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6252 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6253 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6254 mask = ip->insn_mo->mask;
6256 label_expr.X_op = O_constant;
6257 label_expr.X_op_symbol = NULL;
6258 label_expr.X_add_symbol = NULL;
6259 label_expr.X_add_number = 0;
6261 expr1.X_op = O_constant;
6262 expr1.X_op_symbol = NULL;
6263 expr1.X_add_symbol = NULL;
6264 expr1.X_add_number = 1;
6279 if (mips_opts.micromips)
6280 micromips_label_expr (&label_expr);
6282 label_expr.X_add_number = 8;
6283 macro_build (&label_expr, "bgez", "s,p", sreg);
6285 macro_build (NULL, "nop", "");
6287 move_register (dreg, sreg);
6288 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6289 if (mips_opts.micromips)
6290 micromips_add_label ();
6307 if (!mips_opts.micromips)
6309 if (imm_expr.X_op == O_constant
6310 && imm_expr.X_add_number >= -0x200
6311 && imm_expr.X_add_number < 0x200)
6313 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6322 if (imm_expr.X_op == O_constant
6323 && imm_expr.X_add_number >= -0x8000
6324 && imm_expr.X_add_number < 0x8000)
6326 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6331 load_register (AT, &imm_expr, dbl);
6332 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6351 if (imm_expr.X_op == O_constant
6352 && imm_expr.X_add_number >= 0
6353 && imm_expr.X_add_number < 0x10000)
6355 if (mask != M_NOR_I)
6356 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6359 macro_build (&imm_expr, "ori", "t,r,i",
6360 treg, sreg, BFD_RELOC_LO16);
6361 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6367 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6368 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6372 switch (imm_expr.X_add_number)
6375 macro_build (NULL, "nop", "");
6378 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6381 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6382 (int) imm_expr.X_add_number);
6391 gas_assert (mips_opts.micromips);
6392 macro_build_branch_ccl (mask, &offset_expr,
6393 EXTRACT_OPERAND (1, BCC, *ip));
6400 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6406 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6411 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6418 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6420 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6424 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6425 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6426 &offset_expr, AT, ZERO);
6436 macro_build_branch_rs (mask, &offset_expr, sreg);
6442 /* Check for > max integer. */
6443 maxnum = 0x7fffffff;
6444 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6451 if (imm_expr.X_op == O_constant
6452 && imm_expr.X_add_number >= maxnum
6453 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6456 /* Result is always false. */
6458 macro_build (NULL, "nop", "");
6460 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6463 if (imm_expr.X_op != O_constant)
6464 as_bad (_("Unsupported large constant"));
6465 ++imm_expr.X_add_number;
6469 if (mask == M_BGEL_I)
6471 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6473 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6474 &offset_expr, sreg);
6477 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6479 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6480 &offset_expr, sreg);
6483 maxnum = 0x7fffffff;
6484 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6491 maxnum = - maxnum - 1;
6492 if (imm_expr.X_op == O_constant
6493 && imm_expr.X_add_number <= maxnum
6494 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6497 /* result is always true */
6498 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6499 macro_build (&offset_expr, "b", "p");
6504 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6505 &offset_expr, AT, ZERO);
6514 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6515 &offset_expr, ZERO, treg);
6519 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6520 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6521 &offset_expr, AT, ZERO);
6530 && imm_expr.X_op == O_constant
6531 && imm_expr.X_add_number == -1))
6533 if (imm_expr.X_op != O_constant)
6534 as_bad (_("Unsupported large constant"));
6535 ++imm_expr.X_add_number;
6539 if (mask == M_BGEUL_I)
6541 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6543 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6544 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6545 &offset_expr, sreg, ZERO);
6550 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6551 &offset_expr, AT, ZERO);
6559 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6561 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6565 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6566 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6567 &offset_expr, AT, ZERO);
6575 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6576 &offset_expr, sreg, ZERO);
6582 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6583 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6584 &offset_expr, AT, ZERO);
6592 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6594 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6598 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6599 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6600 &offset_expr, AT, ZERO);
6607 maxnum = 0x7fffffff;
6608 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6615 if (imm_expr.X_op == O_constant
6616 && imm_expr.X_add_number >= maxnum
6617 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6619 if (imm_expr.X_op != O_constant)
6620 as_bad (_("Unsupported large constant"));
6621 ++imm_expr.X_add_number;
6625 if (mask == M_BLTL_I)
6627 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6628 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6629 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6630 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6635 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6636 &offset_expr, AT, ZERO);
6644 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6645 &offset_expr, sreg, ZERO);
6651 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6652 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6653 &offset_expr, AT, ZERO);
6662 && imm_expr.X_op == O_constant
6663 && imm_expr.X_add_number == -1))
6665 if (imm_expr.X_op != O_constant)
6666 as_bad (_("Unsupported large constant"));
6667 ++imm_expr.X_add_number;
6671 if (mask == M_BLTUL_I)
6673 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6675 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6676 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6677 &offset_expr, sreg, ZERO);
6682 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6683 &offset_expr, AT, ZERO);
6691 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6693 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6697 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6698 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6699 &offset_expr, AT, ZERO);
6709 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6710 &offset_expr, ZERO, treg);
6714 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6715 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6716 &offset_expr, AT, ZERO);
6722 /* Use unsigned arithmetic. */
6726 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6728 as_bad (_("Unsupported large constant"));
6733 pos = imm_expr.X_add_number;
6734 size = imm2_expr.X_add_number;
6739 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6742 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6744 as_bad (_("Improper extract size (%lu, position %lu)"),
6745 (unsigned long) size, (unsigned long) pos);
6749 if (size <= 32 && pos < 32)
6754 else if (size <= 32)
6764 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6771 /* Use unsigned arithmetic. */
6775 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6777 as_bad (_("Unsupported large constant"));
6782 pos = imm_expr.X_add_number;
6783 size = imm2_expr.X_add_number;
6788 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6791 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6793 as_bad (_("Improper insert size (%lu, position %lu)"),
6794 (unsigned long) size, (unsigned long) pos);
6798 if (pos < 32 && (pos + size - 1) < 32)
6813 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6814 (int) (pos + size - 1));
6830 as_warn (_("Divide by zero."));
6832 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6834 macro_build (NULL, "break", BRK_FMT, 7);
6841 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6842 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6846 if (mips_opts.micromips)
6847 micromips_label_expr (&label_expr);
6849 label_expr.X_add_number = 8;
6850 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6851 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6852 macro_build (NULL, "break", BRK_FMT, 7);
6853 if (mips_opts.micromips)
6854 micromips_add_label ();
6856 expr1.X_add_number = -1;
6858 load_register (AT, &expr1, dbl);
6859 if (mips_opts.micromips)
6860 micromips_label_expr (&label_expr);
6862 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6863 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6866 expr1.X_add_number = 1;
6867 load_register (AT, &expr1, dbl);
6868 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6872 expr1.X_add_number = 0x80000000;
6873 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6877 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6878 /* We want to close the noreorder block as soon as possible, so
6879 that later insns are available for delay slot filling. */
6884 if (mips_opts.micromips)
6885 micromips_label_expr (&label_expr);
6887 label_expr.X_add_number = 8;
6888 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6889 macro_build (NULL, "nop", "");
6891 /* We want to close the noreorder block as soon as possible, so
6892 that later insns are available for delay slot filling. */
6895 macro_build (NULL, "break", BRK_FMT, 6);
6897 if (mips_opts.micromips)
6898 micromips_add_label ();
6899 macro_build (NULL, s, MFHL_FMT, dreg);
6938 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6940 as_warn (_("Divide by zero."));
6942 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6944 macro_build (NULL, "break", BRK_FMT, 7);
6947 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6949 if (strcmp (s2, "mflo") == 0)
6950 move_register (dreg, sreg);
6952 move_register (dreg, ZERO);
6955 if (imm_expr.X_op == O_constant
6956 && imm_expr.X_add_number == -1
6957 && s[strlen (s) - 1] != 'u')
6959 if (strcmp (s2, "mflo") == 0)
6961 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6964 move_register (dreg, ZERO);
6969 load_register (AT, &imm_expr, dbl);
6970 macro_build (NULL, s, "z,s,t", sreg, AT);
6971 macro_build (NULL, s2, MFHL_FMT, dreg);
6993 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6994 macro_build (NULL, s, "z,s,t", sreg, treg);
6995 /* We want to close the noreorder block as soon as possible, so
6996 that later insns are available for delay slot filling. */
7001 if (mips_opts.micromips)
7002 micromips_label_expr (&label_expr);
7004 label_expr.X_add_number = 8;
7005 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7006 macro_build (NULL, s, "z,s,t", sreg, treg);
7008 /* We want to close the noreorder block as soon as possible, so
7009 that later insns are available for delay slot filling. */
7011 macro_build (NULL, "break", BRK_FMT, 7);
7012 if (mips_opts.micromips)
7013 micromips_add_label ();
7015 macro_build (NULL, s2, MFHL_FMT, dreg);
7027 /* Load the address of a symbol into a register. If breg is not
7028 zero, we then add a base register to it. */
7030 if (dbl && HAVE_32BIT_GPRS)
7031 as_warn (_("dla used to load 32-bit register"));
7033 if (!dbl && HAVE_64BIT_OBJECTS)
7034 as_warn (_("la used to load 64-bit address"));
7036 if (offset_expr.X_op == O_constant
7037 && offset_expr.X_add_number >= -0x8000
7038 && offset_expr.X_add_number < 0x8000)
7040 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7041 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7045 if (mips_opts.at && (treg == breg))
7055 if (offset_expr.X_op != O_symbol
7056 && offset_expr.X_op != O_constant)
7058 as_bad (_("Expression too complex"));
7059 offset_expr.X_op = O_constant;
7062 if (offset_expr.X_op == O_constant)
7063 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7064 else if (mips_pic == NO_PIC)
7066 /* If this is a reference to a GP relative symbol, we want
7067 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7069 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7070 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7071 If we have a constant, we need two instructions anyhow,
7072 so we may as well always use the latter form.
7074 With 64bit address space and a usable $at we want
7075 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7076 lui $at,<sym> (BFD_RELOC_HI16_S)
7077 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7078 daddiu $at,<sym> (BFD_RELOC_LO16)
7080 daddu $tempreg,$tempreg,$at
7082 If $at is already in use, we use a path which is suboptimal
7083 on superscalar processors.
7084 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7085 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7087 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7089 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7091 For GP relative symbols in 64bit address space we can use
7092 the same sequence as in 32bit address space. */
7093 if (HAVE_64BIT_SYMBOLS)
7095 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7096 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7098 relax_start (offset_expr.X_add_symbol);
7099 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7100 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7104 if (used_at == 0 && mips_opts.at)
7106 macro_build (&offset_expr, "lui", LUI_FMT,
7107 tempreg, BFD_RELOC_MIPS_HIGHEST);
7108 macro_build (&offset_expr, "lui", LUI_FMT,
7109 AT, BFD_RELOC_HI16_S);
7110 macro_build (&offset_expr, "daddiu", "t,r,j",
7111 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7112 macro_build (&offset_expr, "daddiu", "t,r,j",
7113 AT, AT, BFD_RELOC_LO16);
7114 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7115 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7120 macro_build (&offset_expr, "lui", LUI_FMT,
7121 tempreg, BFD_RELOC_MIPS_HIGHEST);
7122 macro_build (&offset_expr, "daddiu", "t,r,j",
7123 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7124 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7125 macro_build (&offset_expr, "daddiu", "t,r,j",
7126 tempreg, tempreg, BFD_RELOC_HI16_S);
7127 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7128 macro_build (&offset_expr, "daddiu", "t,r,j",
7129 tempreg, tempreg, BFD_RELOC_LO16);
7132 if (mips_relax.sequence)
7137 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7138 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7140 relax_start (offset_expr.X_add_symbol);
7141 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7142 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7145 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7146 as_bad (_("Offset too large"));
7147 macro_build_lui (&offset_expr, tempreg);
7148 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7149 tempreg, tempreg, BFD_RELOC_LO16);
7150 if (mips_relax.sequence)
7154 else if (!mips_big_got && !HAVE_NEWABI)
7156 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7158 /* If this is a reference to an external symbol, and there
7159 is no constant, we want
7160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7161 or for lca or if tempreg is PIC_CALL_REG
7162 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7163 For a local symbol, we want
7164 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7166 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7168 If we have a small constant, and this is a reference to
7169 an external symbol, we want
7170 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7172 addiu $tempreg,$tempreg,<constant>
7173 For a local symbol, we want the same instruction
7174 sequence, but we output a BFD_RELOC_LO16 reloc on the
7177 If we have a large constant, and this is a reference to
7178 an external symbol, we want
7179 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7180 lui $at,<hiconstant>
7181 addiu $at,$at,<loconstant>
7182 addu $tempreg,$tempreg,$at
7183 For a local symbol, we want the same instruction
7184 sequence, but we output a BFD_RELOC_LO16 reloc on the
7188 if (offset_expr.X_add_number == 0)
7190 if (mips_pic == SVR4_PIC
7192 && (call || tempreg == PIC_CALL_REG))
7193 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7195 relax_start (offset_expr.X_add_symbol);
7196 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7197 lw_reloc_type, mips_gp_register);
7200 /* We're going to put in an addu instruction using
7201 tempreg, so we may as well insert the nop right
7206 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7207 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7209 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7210 tempreg, tempreg, BFD_RELOC_LO16);
7212 /* FIXME: If breg == 0, and the next instruction uses
7213 $tempreg, then if this variant case is used an extra
7214 nop will be generated. */
7216 else if (offset_expr.X_add_number >= -0x8000
7217 && offset_expr.X_add_number < 0x8000)
7219 load_got_offset (tempreg, &offset_expr);
7221 add_got_offset (tempreg, &offset_expr);
7225 expr1.X_add_number = offset_expr.X_add_number;
7226 offset_expr.X_add_number =
7227 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7228 load_got_offset (tempreg, &offset_expr);
7229 offset_expr.X_add_number = expr1.X_add_number;
7230 /* If we are going to add in a base register, and the
7231 target register and the base register are the same,
7232 then we are using AT as a temporary register. Since
7233 we want to load the constant into AT, we add our
7234 current AT (from the global offset table) and the
7235 register into the register now, and pretend we were
7236 not using a base register. */
7240 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7245 add_got_offset_hilo (tempreg, &offset_expr, AT);
7249 else if (!mips_big_got && HAVE_NEWABI)
7251 int add_breg_early = 0;
7253 /* If this is a reference to an external, and there is no
7254 constant, or local symbol (*), with or without a
7256 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7257 or for lca or if tempreg is PIC_CALL_REG
7258 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7260 If we have a small constant, and this is a reference to
7261 an external symbol, we want
7262 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7263 addiu $tempreg,$tempreg,<constant>
7265 If we have a large constant, and this is a reference to
7266 an external symbol, we want
7267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7268 lui $at,<hiconstant>
7269 addiu $at,$at,<loconstant>
7270 addu $tempreg,$tempreg,$at
7272 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7273 local symbols, even though it introduces an additional
7276 if (offset_expr.X_add_number)
7278 expr1.X_add_number = offset_expr.X_add_number;
7279 offset_expr.X_add_number = 0;
7281 relax_start (offset_expr.X_add_symbol);
7282 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7283 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7285 if (expr1.X_add_number >= -0x8000
7286 && expr1.X_add_number < 0x8000)
7288 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7289 tempreg, tempreg, BFD_RELOC_LO16);
7291 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7293 /* If we are going to add in a base register, and the
7294 target register and the base register are the same,
7295 then we are using AT as a temporary register. Since
7296 we want to load the constant into AT, we add our
7297 current AT (from the global offset table) and the
7298 register into the register now, and pretend we were
7299 not using a base register. */
7304 gas_assert (tempreg == AT);
7305 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7311 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7312 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7318 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7321 offset_expr.X_add_number = expr1.X_add_number;
7323 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7324 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7328 treg, tempreg, breg);
7334 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7336 relax_start (offset_expr.X_add_symbol);
7337 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7338 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7340 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7341 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7346 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7347 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7350 else if (mips_big_got && !HAVE_NEWABI)
7353 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7354 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7355 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7357 /* This is the large GOT case. If this is a reference to an
7358 external symbol, and there is no constant, we want
7359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7360 addu $tempreg,$tempreg,$gp
7361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7362 or for lca or if tempreg is PIC_CALL_REG
7363 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7364 addu $tempreg,$tempreg,$gp
7365 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7366 For a local symbol, we want
7367 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7369 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7371 If we have a small constant, and this is a reference to
7372 an external symbol, we want
7373 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7374 addu $tempreg,$tempreg,$gp
7375 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7377 addiu $tempreg,$tempreg,<constant>
7378 For a local symbol, we want
7379 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7381 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7383 If we have a large constant, and this is a reference to
7384 an external symbol, we want
7385 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7386 addu $tempreg,$tempreg,$gp
7387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7388 lui $at,<hiconstant>
7389 addiu $at,$at,<loconstant>
7390 addu $tempreg,$tempreg,$at
7391 For a local symbol, we want
7392 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7393 lui $at,<hiconstant>
7394 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7395 addu $tempreg,$tempreg,$at
7398 expr1.X_add_number = offset_expr.X_add_number;
7399 offset_expr.X_add_number = 0;
7400 relax_start (offset_expr.X_add_symbol);
7401 gpdelay = reg_needs_delay (mips_gp_register);
7402 if (expr1.X_add_number == 0 && breg == 0
7403 && (call || tempreg == PIC_CALL_REG))
7405 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7406 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7408 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7410 tempreg, tempreg, mips_gp_register);
7411 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7412 tempreg, lw_reloc_type, tempreg);
7413 if (expr1.X_add_number == 0)
7417 /* We're going to put in an addu instruction using
7418 tempreg, so we may as well insert the nop right
7423 else if (expr1.X_add_number >= -0x8000
7424 && expr1.X_add_number < 0x8000)
7427 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7428 tempreg, tempreg, BFD_RELOC_LO16);
7432 /* If we are going to add in a base register, and the
7433 target register and the base register are the same,
7434 then we are using AT as a temporary register. Since
7435 we want to load the constant into AT, we add our
7436 current AT (from the global offset table) and the
7437 register into the register now, and pretend we were
7438 not using a base register. */
7443 gas_assert (tempreg == AT);
7445 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7450 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7451 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7455 offset_expr.X_add_number =
7456 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7461 /* This is needed because this instruction uses $gp, but
7462 the first instruction on the main stream does not. */
7463 macro_build (NULL, "nop", "");
7466 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7467 local_reloc_type, mips_gp_register);
7468 if (expr1.X_add_number >= -0x8000
7469 && expr1.X_add_number < 0x8000)
7472 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7473 tempreg, tempreg, BFD_RELOC_LO16);
7474 /* FIXME: If add_number is 0, and there was no base
7475 register, the external symbol case ended with a load,
7476 so if the symbol turns out to not be external, and
7477 the next instruction uses tempreg, an unnecessary nop
7478 will be inserted. */
7484 /* We must add in the base register now, as in the
7485 external symbol case. */
7486 gas_assert (tempreg == AT);
7488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7491 /* We set breg to 0 because we have arranged to add
7492 it in in both cases. */
7496 macro_build_lui (&expr1, AT);
7497 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7498 AT, AT, BFD_RELOC_LO16);
7499 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7500 tempreg, tempreg, AT);
7505 else if (mips_big_got && HAVE_NEWABI)
7507 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7508 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7509 int add_breg_early = 0;
7511 /* This is the large GOT case. If this is a reference to an
7512 external symbol, and there is no constant, we want
7513 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7514 add $tempreg,$tempreg,$gp
7515 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7516 or for lca or if tempreg is PIC_CALL_REG
7517 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7518 add $tempreg,$tempreg,$gp
7519 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7521 If we have a small constant, and this is a reference to
7522 an external symbol, we want
7523 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7524 add $tempreg,$tempreg,$gp
7525 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7526 addi $tempreg,$tempreg,<constant>
7528 If we have a large constant, and this is a reference to
7529 an external symbol, we want
7530 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7531 addu $tempreg,$tempreg,$gp
7532 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7533 lui $at,<hiconstant>
7534 addi $at,$at,<loconstant>
7535 add $tempreg,$tempreg,$at
7537 If we have NewABI, and we know it's a local symbol, we want
7538 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7539 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7540 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7542 relax_start (offset_expr.X_add_symbol);
7544 expr1.X_add_number = offset_expr.X_add_number;
7545 offset_expr.X_add_number = 0;
7547 if (expr1.X_add_number == 0 && breg == 0
7548 && (call || tempreg == PIC_CALL_REG))
7550 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7551 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7553 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7554 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7555 tempreg, tempreg, mips_gp_register);
7556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7557 tempreg, lw_reloc_type, tempreg);
7559 if (expr1.X_add_number == 0)
7561 else if (expr1.X_add_number >= -0x8000
7562 && expr1.X_add_number < 0x8000)
7564 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7565 tempreg, tempreg, BFD_RELOC_LO16);
7567 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7569 /* If we are going to add in a base register, and the
7570 target register and the base register are the same,
7571 then we are using AT as a temporary register. Since
7572 we want to load the constant into AT, we add our
7573 current AT (from the global offset table) and the
7574 register into the register now, and pretend we were
7575 not using a base register. */
7580 gas_assert (tempreg == AT);
7581 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7587 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7588 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7593 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7596 offset_expr.X_add_number = expr1.X_add_number;
7597 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7598 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7599 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7600 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7604 treg, tempreg, breg);
7614 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7618 gas_assert (!mips_opts.micromips);
7620 unsigned long temp = (treg << 16) | (0x01);
7621 macro_build (NULL, "c2", "C", temp);
7626 gas_assert (!mips_opts.micromips);
7628 unsigned long temp = (0x02);
7629 macro_build (NULL, "c2", "C", temp);
7634 gas_assert (!mips_opts.micromips);
7636 unsigned long temp = (treg << 16) | (0x02);
7637 macro_build (NULL, "c2", "C", temp);
7642 gas_assert (!mips_opts.micromips);
7643 macro_build (NULL, "c2", "C", 3);
7647 gas_assert (!mips_opts.micromips);
7649 unsigned long temp = (treg << 16) | 0x03;
7650 macro_build (NULL, "c2", "C", temp);
7655 /* The j instruction may not be used in PIC code, since it
7656 requires an absolute address. We convert it to a b
7658 if (mips_pic == NO_PIC)
7659 macro_build (&offset_expr, "j", "a");
7661 macro_build (&offset_expr, "b", "p");
7664 /* The jal instructions must be handled as macros because when
7665 generating PIC code they expand to multi-instruction
7666 sequences. Normally they are simple instructions. */
7671 gas_assert (mips_opts.micromips);
7679 if (mips_pic == NO_PIC)
7681 s = jals ? "jalrs" : "jalr";
7682 if (mips_opts.micromips && dreg == RA)
7683 macro_build (NULL, s, "mj", sreg);
7685 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7689 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7690 && mips_cprestore_offset >= 0);
7692 if (sreg != PIC_CALL_REG)
7693 as_warn (_("MIPS PIC call to register other than $25"));
7695 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7696 ? "jalrs" : "jalr");
7697 if (mips_opts.micromips && dreg == RA)
7698 macro_build (NULL, s, "mj", sreg);
7700 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7701 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7703 if (mips_cprestore_offset < 0)
7704 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7707 if (!mips_frame_reg_valid)
7709 as_warn (_("No .frame pseudo-op used in PIC code"));
7710 /* Quiet this warning. */
7711 mips_frame_reg_valid = 1;
7713 if (!mips_cprestore_valid)
7715 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7716 /* Quiet this warning. */
7717 mips_cprestore_valid = 1;
7719 if (mips_opts.noreorder)
7720 macro_build (NULL, "nop", "");
7721 expr1.X_add_number = mips_cprestore_offset;
7722 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7725 HAVE_64BIT_ADDRESSES);
7733 gas_assert (mips_opts.micromips);
7737 if (mips_pic == NO_PIC)
7738 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7739 else if (mips_pic == SVR4_PIC)
7741 /* If this is a reference to an external symbol, and we are
7742 using a small GOT, we want
7743 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7747 lw $gp,cprestore($sp)
7748 The cprestore value is set using the .cprestore
7749 pseudo-op. If we are using a big GOT, we want
7750 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7752 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7756 lw $gp,cprestore($sp)
7757 If the symbol is not external, we want
7758 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7760 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7763 lw $gp,cprestore($sp)
7765 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7766 sequences above, minus nops, unless the symbol is local,
7767 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7773 relax_start (offset_expr.X_add_symbol);
7774 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7775 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7779 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7785 relax_start (offset_expr.X_add_symbol);
7786 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7787 BFD_RELOC_MIPS_CALL_HI16);
7788 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7789 PIC_CALL_REG, mips_gp_register);
7790 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7791 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7794 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7795 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7797 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7798 PIC_CALL_REG, PIC_CALL_REG,
7799 BFD_RELOC_MIPS_GOT_OFST);
7803 macro_build_jalr (&offset_expr, 0);
7807 relax_start (offset_expr.X_add_symbol);
7810 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7811 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7820 gpdelay = reg_needs_delay (mips_gp_register);
7821 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7822 BFD_RELOC_MIPS_CALL_HI16);
7823 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7824 PIC_CALL_REG, mips_gp_register);
7825 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7826 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7831 macro_build (NULL, "nop", "");
7833 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7834 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7837 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7838 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7840 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7842 if (mips_cprestore_offset < 0)
7843 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7846 if (!mips_frame_reg_valid)
7848 as_warn (_("No .frame pseudo-op used in PIC code"));
7849 /* Quiet this warning. */
7850 mips_frame_reg_valid = 1;
7852 if (!mips_cprestore_valid)
7854 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7855 /* Quiet this warning. */
7856 mips_cprestore_valid = 1;
7858 if (mips_opts.noreorder)
7859 macro_build (NULL, "nop", "");
7860 expr1.X_add_number = mips_cprestore_offset;
7861 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7864 HAVE_64BIT_ADDRESSES);
7868 else if (mips_pic == VXWORKS_PIC)
7869 as_bad (_("Non-PIC jump used in PIC library"));
7902 gas_assert (!mips_opts.micromips);
7905 /* Itbl support may require additional care here. */
7912 /* Itbl support may require additional care here. */
7920 off12 = mips_opts.micromips;
7921 /* Itbl support may require additional care here. */
7926 gas_assert (!mips_opts.micromips);
7929 /* Itbl support may require additional care here. */
7937 off12 = mips_opts.micromips;
7944 off12 = mips_opts.micromips;
7950 /* Itbl support may require additional care here. */
7958 off12 = mips_opts.micromips;
7959 /* Itbl support may require additional care here. */
7966 /* Itbl support may require additional care here. */
7974 off12 = mips_opts.micromips;
7981 off12 = mips_opts.micromips;
7988 off12 = mips_opts.micromips;
7995 off12 = mips_opts.micromips;
8002 off12 = mips_opts.micromips;
8007 gas_assert (mips_opts.micromips);
8016 gas_assert (mips_opts.micromips);
8025 gas_assert (mips_opts.micromips);
8033 gas_assert (mips_opts.micromips);
8040 if (breg == treg + lp)
8043 tempreg = treg + lp;
8063 gas_assert (!mips_opts.micromips);
8066 /* Itbl support may require additional care here. */
8073 /* Itbl support may require additional care here. */
8081 off12 = mips_opts.micromips;
8082 /* Itbl support may require additional care here. */
8087 gas_assert (!mips_opts.micromips);
8090 /* Itbl support may require additional care here. */
8098 off12 = mips_opts.micromips;
8105 off12 = mips_opts.micromips;
8112 off12 = mips_opts.micromips;
8119 off12 = mips_opts.micromips;
8125 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8126 off12 = mips_opts.micromips;
8132 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8133 off12 = mips_opts.micromips;
8140 /* Itbl support may require additional care here. */
8147 off12 = mips_opts.micromips;
8148 /* Itbl support may require additional care here. */
8153 gas_assert (!mips_opts.micromips);
8156 /* Itbl support may require additional care here. */
8164 off12 = mips_opts.micromips;
8171 off12 = mips_opts.micromips;
8176 gas_assert (mips_opts.micromips);
8184 gas_assert (mips_opts.micromips);
8192 gas_assert (mips_opts.micromips);
8200 gas_assert (mips_opts.micromips);
8210 && NO_ISA_COP (mips_opts.arch)
8211 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8213 as_bad (_("Opcode not supported on this processor: %s"),
8214 mips_cpu_info_from_arch (mips_opts.arch)->name);
8218 if (offset_expr.X_op != O_constant
8219 && offset_expr.X_op != O_symbol)
8221 as_bad (_("Expression too complex"));
8222 offset_expr.X_op = O_constant;
8225 if (HAVE_32BIT_ADDRESSES
8226 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8230 sprintf_vma (value, offset_expr.X_add_number);
8231 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8234 /* A constant expression in PIC code can be handled just as it
8235 is in non PIC code. */
8236 if (offset_expr.X_op == O_constant)
8240 expr1.X_add_number = offset_expr.X_add_number;
8241 normalize_address_expr (&expr1);
8242 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8244 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8245 & ~(bfd_vma) 0xffff);
8248 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8250 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8251 & ~(bfd_vma) 0xfff);
8256 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8258 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8259 tempreg, tempreg, breg);
8263 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8265 macro_build (NULL, s, fmt,
8266 treg, (unsigned long) offset_expr.X_add_number, breg);
8270 /* A 12-bit offset field is too narrow to be used for a low-part
8271 relocation, so load the whole address into the auxillary
8272 register. In the case of "A(b)" addresses, we first load
8273 absolute address "A" into the register and then add base
8274 register "b". In the case of "o(b)" addresses, we simply
8275 need to add 16-bit offset "o" to base register "b", and
8276 offset_reloc already contains the relocations associated
8280 load_address (tempreg, &offset_expr, &used_at);
8282 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8283 tempreg, tempreg, breg);
8286 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8288 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8289 expr1.X_add_number = 0;
8290 macro_build (NULL, s, fmt,
8291 treg, (unsigned long) expr1.X_add_number, tempreg);
8293 else if (mips_pic == NO_PIC)
8295 /* If this is a reference to a GP relative symbol, and there
8296 is no base register, we want
8297 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8298 Otherwise, if there is no base register, we want
8299 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8300 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8301 If we have a constant, we need two instructions anyhow,
8302 so we always use the latter form.
8304 If we have a base register, and this is a reference to a
8305 GP relative symbol, we want
8306 addu $tempreg,$breg,$gp
8307 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8309 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8310 addu $tempreg,$tempreg,$breg
8311 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8312 With a constant we always use the latter case.
8314 With 64bit address space and no base register and $at usable,
8316 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8317 lui $at,<sym> (BFD_RELOC_HI16_S)
8318 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8321 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8322 If we have a base register, we want
8323 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8324 lui $at,<sym> (BFD_RELOC_HI16_S)
8325 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8329 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8331 Without $at we can't generate the optimal path for superscalar
8332 processors here since this would require two temporary registers.
8333 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8334 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8336 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8338 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8339 If we have a base register, we want
8340 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8341 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8343 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8345 daddu $tempreg,$tempreg,$breg
8346 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8348 For GP relative symbols in 64bit address space we can use
8349 the same sequence as in 32bit address space. */
8350 if (HAVE_64BIT_SYMBOLS)
8352 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8353 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8355 relax_start (offset_expr.X_add_symbol);
8358 macro_build (&offset_expr, s, fmt, treg,
8359 BFD_RELOC_GPREL16, mips_gp_register);
8363 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8364 tempreg, breg, mips_gp_register);
8365 macro_build (&offset_expr, s, fmt, treg,
8366 BFD_RELOC_GPREL16, tempreg);
8371 if (used_at == 0 && mips_opts.at)
8373 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8374 BFD_RELOC_MIPS_HIGHEST);
8375 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8377 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8378 tempreg, BFD_RELOC_MIPS_HIGHER);
8380 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8381 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8382 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8383 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8389 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8390 BFD_RELOC_MIPS_HIGHEST);
8391 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8392 tempreg, BFD_RELOC_MIPS_HIGHER);
8393 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8394 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8395 tempreg, BFD_RELOC_HI16_S);
8396 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8398 macro_build (NULL, "daddu", "d,v,t",
8399 tempreg, tempreg, breg);
8400 macro_build (&offset_expr, s, fmt, treg,
8401 BFD_RELOC_LO16, tempreg);
8404 if (mips_relax.sequence)
8411 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8412 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8414 relax_start (offset_expr.X_add_symbol);
8415 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8419 macro_build_lui (&offset_expr, tempreg);
8420 macro_build (&offset_expr, s, fmt, treg,
8421 BFD_RELOC_LO16, tempreg);
8422 if (mips_relax.sequence)
8427 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8428 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8430 relax_start (offset_expr.X_add_symbol);
8431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8432 tempreg, breg, mips_gp_register);
8433 macro_build (&offset_expr, s, fmt, treg,
8434 BFD_RELOC_GPREL16, tempreg);
8437 macro_build_lui (&offset_expr, tempreg);
8438 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8439 tempreg, tempreg, breg);
8440 macro_build (&offset_expr, s, fmt, treg,
8441 BFD_RELOC_LO16, tempreg);
8442 if (mips_relax.sequence)
8446 else if (!mips_big_got)
8448 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8450 /* If this is a reference to an external symbol, we want
8451 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8453 <op> $treg,0($tempreg)
8455 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8457 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8458 <op> $treg,0($tempreg)
8461 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8462 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8464 If there is a base register, we add it to $tempreg before
8465 the <op>. If there is a constant, we stick it in the
8466 <op> instruction. We don't handle constants larger than
8467 16 bits, because we have no way to load the upper 16 bits
8468 (actually, we could handle them for the subset of cases
8469 in which we are not using $at). */
8470 gas_assert (offset_expr.X_op == O_symbol);
8473 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8474 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8477 tempreg, tempreg, breg);
8478 macro_build (&offset_expr, s, fmt, treg,
8479 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8482 expr1.X_add_number = offset_expr.X_add_number;
8483 offset_expr.X_add_number = 0;
8484 if (expr1.X_add_number < -0x8000
8485 || expr1.X_add_number >= 0x8000)
8486 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8487 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8488 lw_reloc_type, mips_gp_register);
8490 relax_start (offset_expr.X_add_symbol);
8492 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8493 tempreg, BFD_RELOC_LO16);
8496 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8497 tempreg, tempreg, breg);
8498 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8500 else if (mips_big_got && !HAVE_NEWABI)
8504 /* If this is a reference to an external symbol, we want
8505 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8506 addu $tempreg,$tempreg,$gp
8507 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8508 <op> $treg,0($tempreg)
8510 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8512 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8513 <op> $treg,0($tempreg)
8514 If there is a base register, we add it to $tempreg before
8515 the <op>. If there is a constant, we stick it in the
8516 <op> instruction. We don't handle constants larger than
8517 16 bits, because we have no way to load the upper 16 bits
8518 (actually, we could handle them for the subset of cases
8519 in which we are not using $at). */
8520 gas_assert (offset_expr.X_op == O_symbol);
8521 expr1.X_add_number = offset_expr.X_add_number;
8522 offset_expr.X_add_number = 0;
8523 if (expr1.X_add_number < -0x8000
8524 || expr1.X_add_number >= 0x8000)
8525 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8526 gpdelay = reg_needs_delay (mips_gp_register);
8527 relax_start (offset_expr.X_add_symbol);
8528 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8529 BFD_RELOC_MIPS_GOT_HI16);
8530 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8532 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8533 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8536 macro_build (NULL, "nop", "");
8537 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8538 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8540 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8541 tempreg, BFD_RELOC_LO16);
8545 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8546 tempreg, tempreg, breg);
8547 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8549 else if (mips_big_got && HAVE_NEWABI)
8551 /* If this is a reference to an external symbol, we want
8552 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8553 add $tempreg,$tempreg,$gp
8554 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8555 <op> $treg,<ofst>($tempreg)
8556 Otherwise, for local symbols, we want:
8557 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8558 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8559 gas_assert (offset_expr.X_op == O_symbol);
8560 expr1.X_add_number = offset_expr.X_add_number;
8561 offset_expr.X_add_number = 0;
8562 if (expr1.X_add_number < -0x8000
8563 || expr1.X_add_number >= 0x8000)
8564 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8565 relax_start (offset_expr.X_add_symbol);
8566 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8567 BFD_RELOC_MIPS_GOT_HI16);
8568 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8570 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8571 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8573 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8574 tempreg, tempreg, breg);
8575 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8578 offset_expr.X_add_number = expr1.X_add_number;
8579 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8580 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8582 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8583 tempreg, tempreg, breg);
8584 macro_build (&offset_expr, s, fmt, treg,
8585 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8595 load_register (treg, &imm_expr, 0);
8599 load_register (treg, &imm_expr, 1);
8603 if (imm_expr.X_op == O_constant)
8606 load_register (AT, &imm_expr, 0);
8607 macro_build (NULL, "mtc1", "t,G", AT, treg);
8612 gas_assert (offset_expr.X_op == O_symbol
8613 && strcmp (segment_name (S_GET_SEGMENT
8614 (offset_expr.X_add_symbol)),
8616 && offset_expr.X_add_number == 0);
8617 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8618 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8623 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8624 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8625 order 32 bits of the value and the low order 32 bits are either
8626 zero or in OFFSET_EXPR. */
8627 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8629 if (HAVE_64BIT_GPRS)
8630 load_register (treg, &imm_expr, 1);
8635 if (target_big_endian)
8647 load_register (hreg, &imm_expr, 0);
8650 if (offset_expr.X_op == O_absent)
8651 move_register (lreg, 0);
8654 gas_assert (offset_expr.X_op == O_constant);
8655 load_register (lreg, &offset_expr, 0);
8662 /* We know that sym is in the .rdata section. First we get the
8663 upper 16 bits of the address. */
8664 if (mips_pic == NO_PIC)
8666 macro_build_lui (&offset_expr, AT);
8671 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8672 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8676 /* Now we load the register(s). */
8677 if (HAVE_64BIT_GPRS)
8680 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8685 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8688 /* FIXME: How in the world do we deal with the possible
8690 offset_expr.X_add_number += 4;
8691 macro_build (&offset_expr, "lw", "t,o(b)",
8692 treg + 1, BFD_RELOC_LO16, AT);
8698 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8699 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8700 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8701 the value and the low order 32 bits are either zero or in
8703 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8706 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8707 if (HAVE_64BIT_FPRS)
8709 gas_assert (HAVE_64BIT_GPRS);
8710 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8714 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8715 if (offset_expr.X_op == O_absent)
8716 macro_build (NULL, "mtc1", "t,G", 0, treg);
8719 gas_assert (offset_expr.X_op == O_constant);
8720 load_register (AT, &offset_expr, 0);
8721 macro_build (NULL, "mtc1", "t,G", AT, treg);
8727 gas_assert (offset_expr.X_op == O_symbol
8728 && offset_expr.X_add_number == 0);
8729 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8730 if (strcmp (s, ".lit8") == 0)
8732 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8734 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8735 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8738 breg = mips_gp_register;
8739 r = BFD_RELOC_MIPS_LITERAL;
8744 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8746 if (mips_pic != NO_PIC)
8747 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8748 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8751 /* FIXME: This won't work for a 64 bit address. */
8752 macro_build_lui (&offset_expr, AT);
8755 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8757 macro_build (&offset_expr, "ldc1", "T,o(b)",
8758 treg, BFD_RELOC_LO16, AT);
8767 /* Even on a big endian machine $fn comes before $fn+1. We have
8768 to adjust when loading from memory. */
8771 gas_assert (!mips_opts.micromips);
8772 gas_assert (mips_opts.isa == ISA_MIPS1);
8773 macro_build (&offset_expr, "lwc1", "T,o(b)",
8774 target_big_endian ? treg + 1 : treg, r, breg);
8775 /* FIXME: A possible overflow which I don't know how to deal
8777 offset_expr.X_add_number += 4;
8778 macro_build (&offset_expr, "lwc1", "T,o(b)",
8779 target_big_endian ? treg : treg + 1, r, breg);
8783 gas_assert (!mips_opts.micromips);
8784 gas_assert (mips_opts.isa == ISA_MIPS1);
8785 /* Even on a big endian machine $fn comes before $fn+1. We have
8786 to adjust when storing to memory. */
8787 macro_build (&offset_expr, "swc1", "T,o(b)",
8788 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8789 offset_expr.X_add_number += 4;
8790 macro_build (&offset_expr, "swc1", "T,o(b)",
8791 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8795 gas_assert (!mips_opts.micromips);
8797 * The MIPS assembler seems to check for X_add_number not
8798 * being double aligned and generating:
8801 * addiu at,at,%lo(foo+1)
8804 * But, the resulting address is the same after relocation so why
8805 * generate the extra instruction?
8807 /* Itbl support may require additional care here. */
8810 if (mips_opts.isa != ISA_MIPS1)
8819 gas_assert (!mips_opts.micromips);
8820 /* Itbl support may require additional care here. */
8823 if (mips_opts.isa != ISA_MIPS1)
8833 if (HAVE_64BIT_GPRS)
8843 if (HAVE_64BIT_GPRS)
8851 if (offset_expr.X_op != O_symbol
8852 && offset_expr.X_op != O_constant)
8854 as_bad (_("Expression too complex"));
8855 offset_expr.X_op = O_constant;
8858 if (HAVE_32BIT_ADDRESSES
8859 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8863 sprintf_vma (value, offset_expr.X_add_number);
8864 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8867 /* Even on a big endian machine $fn comes before $fn+1. We have
8868 to adjust when loading from memory. We set coproc if we must
8869 load $fn+1 first. */
8870 /* Itbl support may require additional care here. */
8871 if (!target_big_endian)
8874 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8876 /* If this is a reference to a GP relative symbol, we want
8877 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8878 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8879 If we have a base register, we use this
8881 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8882 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8883 If this is not a GP relative symbol, we want
8884 lui $at,<sym> (BFD_RELOC_HI16_S)
8885 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8886 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8887 If there is a base register, we add it to $at after the
8888 lui instruction. If there is a constant, we always use
8890 if (offset_expr.X_op == O_symbol
8891 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8892 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8894 relax_start (offset_expr.X_add_symbol);
8897 tempreg = mips_gp_register;
8901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8902 AT, breg, mips_gp_register);
8907 /* Itbl support may require additional care here. */
8908 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8909 BFD_RELOC_GPREL16, tempreg);
8910 offset_expr.X_add_number += 4;
8912 /* Set mips_optimize to 2 to avoid inserting an
8914 hold_mips_optimize = mips_optimize;
8916 /* Itbl support may require additional care here. */
8917 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8918 BFD_RELOC_GPREL16, tempreg);
8919 mips_optimize = hold_mips_optimize;
8923 offset_expr.X_add_number -= 4;
8926 macro_build_lui (&offset_expr, AT);
8928 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8929 /* Itbl support may require additional care here. */
8930 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8931 BFD_RELOC_LO16, AT);
8932 /* FIXME: How do we handle overflow here? */
8933 offset_expr.X_add_number += 4;
8934 /* Itbl support may require additional care here. */
8935 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8936 BFD_RELOC_LO16, AT);
8937 if (mips_relax.sequence)
8940 else if (!mips_big_got)
8942 /* If this is a reference to an external symbol, we want
8943 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8948 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8950 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8951 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8952 If there is a base register we add it to $at before the
8953 lwc1 instructions. If there is a constant we include it
8954 in the lwc1 instructions. */
8956 expr1.X_add_number = offset_expr.X_add_number;
8957 if (expr1.X_add_number < -0x8000
8958 || expr1.X_add_number >= 0x8000 - 4)
8959 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8960 load_got_offset (AT, &offset_expr);
8963 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8965 /* Set mips_optimize to 2 to avoid inserting an undesired
8967 hold_mips_optimize = mips_optimize;
8970 /* Itbl support may require additional care here. */
8971 relax_start (offset_expr.X_add_symbol);
8972 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
8973 BFD_RELOC_LO16, AT);
8974 expr1.X_add_number += 4;
8975 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
8976 BFD_RELOC_LO16, AT);
8978 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8979 BFD_RELOC_LO16, AT);
8980 offset_expr.X_add_number += 4;
8981 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8982 BFD_RELOC_LO16, AT);
8985 mips_optimize = hold_mips_optimize;
8987 else if (mips_big_got)
8991 /* If this is a reference to an external symbol, we want
8992 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8994 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
8999 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9001 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9002 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9003 If there is a base register we add it to $at before the
9004 lwc1 instructions. If there is a constant we include it
9005 in the lwc1 instructions. */
9007 expr1.X_add_number = offset_expr.X_add_number;
9008 offset_expr.X_add_number = 0;
9009 if (expr1.X_add_number < -0x8000
9010 || expr1.X_add_number >= 0x8000 - 4)
9011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9012 gpdelay = reg_needs_delay (mips_gp_register);
9013 relax_start (offset_expr.X_add_symbol);
9014 macro_build (&offset_expr, "lui", LUI_FMT,
9015 AT, BFD_RELOC_MIPS_GOT_HI16);
9016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9017 AT, AT, mips_gp_register);
9018 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9019 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9023 /* Itbl support may require additional care here. */
9024 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9025 BFD_RELOC_LO16, AT);
9026 expr1.X_add_number += 4;
9028 /* Set mips_optimize to 2 to avoid inserting an undesired
9030 hold_mips_optimize = mips_optimize;
9032 /* Itbl support may require additional care here. */
9033 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9034 BFD_RELOC_LO16, AT);
9035 mips_optimize = hold_mips_optimize;
9036 expr1.X_add_number -= 4;
9039 offset_expr.X_add_number = expr1.X_add_number;
9041 macro_build (NULL, "nop", "");
9042 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9043 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9046 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9047 /* Itbl support may require additional care here. */
9048 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9049 BFD_RELOC_LO16, AT);
9050 offset_expr.X_add_number += 4;
9052 /* Set mips_optimize to 2 to avoid inserting an undesired
9054 hold_mips_optimize = mips_optimize;
9056 /* Itbl support may require additional care here. */
9057 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9058 BFD_RELOC_LO16, AT);
9059 mips_optimize = hold_mips_optimize;
9068 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9071 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9073 macro_build (&offset_expr, s, "t,o(b)", treg,
9074 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9076 if (!HAVE_64BIT_GPRS)
9078 offset_expr.X_add_number += 4;
9079 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9080 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9085 /* New code added to support COPZ instructions.
9086 This code builds table entries out of the macros in mip_opcodes.
9087 R4000 uses interlocks to handle coproc delays.
9088 Other chips (like the R3000) require nops to be inserted for delays.
9090 FIXME: Currently, we require that the user handle delays.
9091 In order to fill delay slots for non-interlocked chips,
9092 we must have a way to specify delays based on the coprocessor.
9093 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9094 What are the side-effects of the cop instruction?
9095 What cache support might we have and what are its effects?
9096 Both coprocessor & memory require delays. how long???
9097 What registers are read/set/modified?
9099 If an itbl is provided to interpret cop instructions,
9100 this knowledge can be encoded in the itbl spec. */
9114 gas_assert (!mips_opts.micromips);
9115 if (NO_ISA_COP (mips_opts.arch)
9116 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9118 as_bad (_("opcode not supported on this processor: %s"),
9119 mips_cpu_info_from_arch (mips_opts.arch)->name);
9123 /* For now we just do C (same as Cz). The parameter will be
9124 stored in insn_opcode by mips_ip. */
9125 macro_build (NULL, s, "C", ip->insn_opcode);
9129 move_register (dreg, sreg);
9135 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9136 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9142 /* The MIPS assembler some times generates shifts and adds. I'm
9143 not trying to be that fancy. GCC should do this for us
9146 load_register (AT, &imm_expr, dbl);
9147 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9148 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9164 load_register (AT, &imm_expr, dbl);
9165 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9166 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9167 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9168 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9170 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9173 if (mips_opts.micromips)
9174 micromips_label_expr (&label_expr);
9176 label_expr.X_add_number = 8;
9177 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9178 macro_build (NULL, "nop", "");
9179 macro_build (NULL, "break", BRK_FMT, 6);
9180 if (mips_opts.micromips)
9181 micromips_add_label ();
9184 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9200 load_register (AT, &imm_expr, dbl);
9201 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9202 sreg, imm ? AT : treg);
9203 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9204 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9206 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9209 if (mips_opts.micromips)
9210 micromips_label_expr (&label_expr);
9212 label_expr.X_add_number = 8;
9213 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9214 macro_build (NULL, "nop", "");
9215 macro_build (NULL, "break", BRK_FMT, 6);
9216 if (mips_opts.micromips)
9217 micromips_add_label ();
9223 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9234 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9235 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9239 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9240 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9241 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9242 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9246 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9257 macro_build (NULL, "negu", "d,w", tempreg, treg);
9258 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9262 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9263 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9264 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9265 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9274 if (imm_expr.X_op != O_constant)
9275 as_bad (_("Improper rotate count"));
9276 rot = imm_expr.X_add_number & 0x3f;
9277 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9279 rot = (64 - rot) & 0x3f;
9281 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9283 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9288 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9291 l = (rot < 0x20) ? "dsll" : "dsll32";
9292 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9295 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9296 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9297 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9305 if (imm_expr.X_op != O_constant)
9306 as_bad (_("Improper rotate count"));
9307 rot = imm_expr.X_add_number & 0x1f;
9308 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9310 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9315 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9319 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9320 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9321 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9326 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9328 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9332 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9333 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9334 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9335 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9339 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9341 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9345 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9346 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9347 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9348 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9357 if (imm_expr.X_op != O_constant)
9358 as_bad (_("Improper rotate count"));
9359 rot = imm_expr.X_add_number & 0x3f;
9360 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9363 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9365 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9370 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9373 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9374 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9377 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9378 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9379 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9387 if (imm_expr.X_op != O_constant)
9388 as_bad (_("Improper rotate count"));
9389 rot = imm_expr.X_add_number & 0x1f;
9390 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9392 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9397 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9401 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9402 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9403 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9409 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9411 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9414 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9415 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9420 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9422 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9427 as_warn (_("Instruction %s: result is always false"),
9429 move_register (dreg, 0);
9432 if (CPU_HAS_SEQ (mips_opts.arch)
9433 && -512 <= imm_expr.X_add_number
9434 && imm_expr.X_add_number < 512)
9436 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9437 (int) imm_expr.X_add_number);
9440 if (imm_expr.X_op == O_constant
9441 && imm_expr.X_add_number >= 0
9442 && imm_expr.X_add_number < 0x10000)
9444 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9446 else if (imm_expr.X_op == O_constant
9447 && imm_expr.X_add_number > -0x8000
9448 && imm_expr.X_add_number < 0)
9450 imm_expr.X_add_number = -imm_expr.X_add_number;
9451 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9452 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9454 else if (CPU_HAS_SEQ (mips_opts.arch))
9457 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9458 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9463 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9464 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9467 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9470 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9476 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9477 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9480 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9482 if (imm_expr.X_op == O_constant
9483 && imm_expr.X_add_number >= -0x8000
9484 && imm_expr.X_add_number < 0x8000)
9486 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9487 dreg, sreg, BFD_RELOC_LO16);
9491 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9492 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9496 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9499 case M_SGT: /* sreg > treg <==> treg < sreg */
9505 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9508 case M_SGT_I: /* sreg > I <==> I < sreg */
9515 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9516 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9519 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9525 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9526 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9529 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9536 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9537 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9538 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9542 if (imm_expr.X_op == O_constant
9543 && imm_expr.X_add_number >= -0x8000
9544 && imm_expr.X_add_number < 0x8000)
9546 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9550 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9551 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9555 if (imm_expr.X_op == O_constant
9556 && imm_expr.X_add_number >= -0x8000
9557 && imm_expr.X_add_number < 0x8000)
9559 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9564 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9565 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9570 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9572 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9575 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9576 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9581 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9583 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9588 as_warn (_("Instruction %s: result is always true"),
9590 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9591 dreg, 0, BFD_RELOC_LO16);
9594 if (CPU_HAS_SEQ (mips_opts.arch)
9595 && -512 <= imm_expr.X_add_number
9596 && imm_expr.X_add_number < 512)
9598 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9599 (int) imm_expr.X_add_number);
9602 if (imm_expr.X_op == O_constant
9603 && imm_expr.X_add_number >= 0
9604 && imm_expr.X_add_number < 0x10000)
9606 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9608 else if (imm_expr.X_op == O_constant
9609 && imm_expr.X_add_number > -0x8000
9610 && imm_expr.X_add_number < 0)
9612 imm_expr.X_add_number = -imm_expr.X_add_number;
9613 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9614 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9616 else if (CPU_HAS_SEQ (mips_opts.arch))
9619 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9620 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9625 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9626 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9629 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9644 if (!mips_opts.micromips)
9646 if (imm_expr.X_op == O_constant
9647 && imm_expr.X_add_number > -0x200
9648 && imm_expr.X_add_number <= 0x200)
9650 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9659 if (imm_expr.X_op == O_constant
9660 && imm_expr.X_add_number > -0x8000
9661 && imm_expr.X_add_number <= 0x8000)
9663 imm_expr.X_add_number = -imm_expr.X_add_number;
9664 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9669 load_register (AT, &imm_expr, dbl);
9670 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9692 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9693 macro_build (NULL, s, "s,t", sreg, AT);
9698 gas_assert (!mips_opts.micromips);
9699 gas_assert (mips_opts.isa == ISA_MIPS1);
9701 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9702 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9705 * Is the double cfc1 instruction a bug in the mips assembler;
9706 * or is there a reason for it?
9709 macro_build (NULL, "cfc1", "t,G", treg, RA);
9710 macro_build (NULL, "cfc1", "t,G", treg, RA);
9711 macro_build (NULL, "nop", "");
9712 expr1.X_add_number = 3;
9713 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9714 expr1.X_add_number = 2;
9715 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9716 macro_build (NULL, "ctc1", "t,G", AT, RA);
9717 macro_build (NULL, "nop", "");
9718 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9720 macro_build (NULL, "ctc1", "t,G", treg, RA);
9721 macro_build (NULL, "nop", "");
9744 off12 = mips_opts.micromips;
9752 off12 = mips_opts.micromips;
9768 off12 = mips_opts.micromips;
9777 off12 = mips_opts.micromips;
9782 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9783 as_bad (_("Operand overflow"));
9786 expr1.X_add_number = 0;
9791 load_address (tempreg, ep, &used_at);
9793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9794 tempreg, tempreg, breg);
9800 && (offset_expr.X_op != O_constant
9801 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9802 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9806 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9807 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9812 else if (!ust && treg == breg)
9823 if (!target_big_endian)
9824 ep->X_add_number += off;
9826 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9828 macro_build (NULL, s, "t,~(b)",
9829 tempreg, (unsigned long) ep->X_add_number, breg);
9831 if (!target_big_endian)
9832 ep->X_add_number -= off;
9834 ep->X_add_number += off;
9836 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9838 macro_build (NULL, s2, "t,~(b)",
9839 tempreg, (unsigned long) ep->X_add_number, breg);
9841 /* If necessary, move the result in tempreg to the final destination. */
9842 if (!ust && treg != tempreg)
9844 /* Protect second load's delay slot. */
9846 move_register (treg, tempreg);
9852 if (target_big_endian == ust)
9853 ep->X_add_number += off;
9854 tempreg = ust || ab ? treg : AT;
9855 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9857 /* For halfword transfers we need a temporary register to shuffle
9858 bytes. Unfortunately for M_USH_A we have none available before
9859 the next store as AT holds the base address. We deal with this
9860 case by clobbering TREG and then restoring it as with ULH. */
9861 tempreg = ust == ab ? treg : AT;
9863 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9865 if (target_big_endian == ust)
9866 ep->X_add_number -= off;
9868 ep->X_add_number += off;
9869 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9871 /* For M_USH_A re-retrieve the LSB. */
9874 if (target_big_endian)
9875 ep->X_add_number += off;
9877 ep->X_add_number -= off;
9878 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9880 /* For ULH and M_USH_A OR the LSB in. */
9883 tempreg = !ab ? AT : treg;
9884 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9885 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9890 /* FIXME: Check if this is one of the itbl macros, since they
9891 are added dynamically. */
9892 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9895 if (!mips_opts.at && used_at)
9896 as_bad (_("Macro used $at after \".set noat\""));
9899 /* Implement macros in mips16 mode. */
9902 mips16_macro (struct mips_cl_insn *ip)
9905 int xreg, yreg, zreg, tmp;
9908 const char *s, *s2, *s3;
9910 mask = ip->insn_mo->mask;
9912 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9913 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9914 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9916 expr1.X_op = O_constant;
9917 expr1.X_op_symbol = NULL;
9918 expr1.X_add_symbol = NULL;
9919 expr1.X_add_number = 1;
9939 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9940 expr1.X_add_number = 2;
9941 macro_build (&expr1, "bnez", "x,p", yreg);
9942 macro_build (NULL, "break", "6", 7);
9944 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9945 since that causes an overflow. We should do that as well,
9946 but I don't see how to do the comparisons without a temporary
9949 macro_build (NULL, s, "x", zreg);
9969 macro_build (NULL, s, "0,x,y", xreg, yreg);
9970 expr1.X_add_number = 2;
9971 macro_build (&expr1, "bnez", "x,p", yreg);
9972 macro_build (NULL, "break", "6", 7);
9974 macro_build (NULL, s2, "x", zreg);
9980 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
9981 macro_build (NULL, "mflo", "x", zreg);
9989 if (imm_expr.X_op != O_constant)
9990 as_bad (_("Unsupported large constant"));
9991 imm_expr.X_add_number = -imm_expr.X_add_number;
9992 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
9996 if (imm_expr.X_op != O_constant)
9997 as_bad (_("Unsupported large constant"));
9998 imm_expr.X_add_number = -imm_expr.X_add_number;
9999 macro_build (&imm_expr, "addiu", "x,k", xreg);
10003 if (imm_expr.X_op != O_constant)
10004 as_bad (_("Unsupported large constant"));
10005 imm_expr.X_add_number = -imm_expr.X_add_number;
10006 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10028 goto do_reverse_branch;
10032 goto do_reverse_branch;
10044 goto do_reverse_branch;
10055 macro_build (NULL, s, "x,y", xreg, yreg);
10056 macro_build (&offset_expr, s2, "p");
10083 goto do_addone_branch_i;
10088 goto do_addone_branch_i;
10103 goto do_addone_branch_i;
10109 do_addone_branch_i:
10110 if (imm_expr.X_op != O_constant)
10111 as_bad (_("Unsupported large constant"));
10112 ++imm_expr.X_add_number;
10115 macro_build (&imm_expr, s, s3, xreg);
10116 macro_build (&offset_expr, s2, "p");
10120 expr1.X_add_number = 0;
10121 macro_build (&expr1, "slti", "x,8", yreg);
10123 move_register (xreg, yreg);
10124 expr1.X_add_number = 2;
10125 macro_build (&expr1, "bteqz", "p");
10126 macro_build (NULL, "neg", "x,w", xreg, xreg);
10130 /* For consistency checking, verify that all bits are specified either
10131 by the match/mask part of the instruction definition, or by the
10134 validate_mips_insn (const struct mips_opcode *opc)
10136 const char *p = opc->args;
10138 unsigned long used_bits = opc->mask;
10140 if ((used_bits & opc->match) != opc->match)
10142 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10143 opc->name, opc->args);
10146 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10156 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10157 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10158 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10159 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10160 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10161 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10162 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10163 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10164 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10165 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10166 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10167 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10168 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10170 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10171 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10172 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10173 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10174 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10175 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10176 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10177 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10178 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10179 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10180 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10181 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10182 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10183 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10184 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10187 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10188 c, opc->name, opc->args);
10192 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10193 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10195 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10196 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10197 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10198 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10200 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10201 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10203 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10204 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10206 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10207 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10208 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10209 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10210 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10211 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10212 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10213 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10214 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10215 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10216 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10217 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10218 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10219 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10220 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10221 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10222 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10224 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10225 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10226 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10227 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10229 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10230 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10231 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10232 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10233 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10234 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10235 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10236 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10237 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10240 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10241 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10242 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10243 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10244 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10247 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10248 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10249 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10250 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10251 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10252 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10253 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10254 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10255 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10256 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10257 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10258 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10259 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10260 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10261 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10262 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10263 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10264 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10266 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10267 c, opc->name, opc->args);
10271 if (used_bits != 0xffffffff)
10273 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10274 ~used_bits & 0xffffffff, opc->name, opc->args);
10280 /* For consistency checking, verify that the length implied matches the
10281 major opcode and that all bits are specified either by the match/mask
10282 part of the instruction definition, or by the operand list. */
10285 validate_micromips_insn (const struct mips_opcode *opc)
10287 unsigned long match = opc->match;
10288 unsigned long mask = opc->mask;
10289 const char *p = opc->args;
10290 unsigned long insn_bits;
10291 unsigned long used_bits;
10292 unsigned long major;
10293 unsigned int length;
10297 if ((mask & match) != match)
10299 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10300 opc->name, opc->args);
10303 length = micromips_insn_length (opc);
10304 if (length != 2 && length != 4)
10306 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10307 "%s %s"), length, opc->name, opc->args);
10310 major = match >> (10 + 8 * (length - 2));
10311 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10312 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10314 as_bad (_("Internal error: bad microMIPS opcode "
10315 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10319 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10320 insn_bits = 1 << 4 * length;
10321 insn_bits <<= 4 * length;
10324 #define USE_BITS(field) \
10325 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10336 case 'A': USE_BITS (EXTLSB); break;
10337 case 'B': USE_BITS (INSMSB); break;
10338 case 'C': USE_BITS (EXTMSBD); break;
10339 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10340 case 'E': USE_BITS (EXTLSB); break;
10341 case 'F': USE_BITS (INSMSB); break;
10342 case 'G': USE_BITS (EXTMSBD); break;
10343 case 'H': USE_BITS (EXTMSBD); break;
10345 as_bad (_("Internal error: bad mips opcode "
10346 "(unknown extension operand type `%c%c'): %s %s"),
10347 e, c, opc->name, opc->args);
10355 case 'A': USE_BITS (IMMA); break;
10356 case 'B': USE_BITS (IMMB); break;
10357 case 'C': USE_BITS (IMMC); break;
10358 case 'D': USE_BITS (IMMD); break;
10359 case 'E': USE_BITS (IMME); break;
10360 case 'F': USE_BITS (IMMF); break;
10361 case 'G': USE_BITS (IMMG); break;
10362 case 'H': USE_BITS (IMMH); break;
10363 case 'I': USE_BITS (IMMI); break;
10364 case 'J': USE_BITS (IMMJ); break;
10365 case 'L': USE_BITS (IMML); break;
10366 case 'M': USE_BITS (IMMM); break;
10367 case 'N': USE_BITS (IMMN); break;
10368 case 'O': USE_BITS (IMMO); break;
10369 case 'P': USE_BITS (IMMP); break;
10370 case 'Q': USE_BITS (IMMQ); break;
10371 case 'U': USE_BITS (IMMU); break;
10372 case 'W': USE_BITS (IMMW); break;
10373 case 'X': USE_BITS (IMMX); break;
10374 case 'Y': USE_BITS (IMMY); break;
10377 case 'b': USE_BITS (MB); break;
10378 case 'c': USE_BITS (MC); break;
10379 case 'd': USE_BITS (MD); break;
10380 case 'e': USE_BITS (ME); break;
10381 case 'f': USE_BITS (MF); break;
10382 case 'g': USE_BITS (MG); break;
10383 case 'h': USE_BITS (MH); break;
10384 case 'i': USE_BITS (MI); break;
10385 case 'j': USE_BITS (MJ); break;
10386 case 'l': USE_BITS (ML); break;
10387 case 'm': USE_BITS (MM); break;
10388 case 'n': USE_BITS (MN); break;
10389 case 'p': USE_BITS (MP); break;
10390 case 'q': USE_BITS (MQ); break;
10398 as_bad (_("Internal error: bad mips opcode "
10399 "(unknown extension operand type `%c%c'): %s %s"),
10400 e, c, opc->name, opc->args);
10404 case '.': USE_BITS (OFFSET10); break;
10405 case '1': USE_BITS (STYPE); break;
10406 case '<': USE_BITS (SHAMT); break;
10407 case '>': USE_BITS (SHAMT); break;
10408 case 'B': USE_BITS (CODE10); break;
10409 case 'C': USE_BITS (COPZ); break;
10410 case 'D': USE_BITS (FD); break;
10411 case 'E': USE_BITS (RT); break;
10412 case 'G': USE_BITS (RS); break;
10413 case 'H': USE_BITS (SEL); break;
10414 case 'K': USE_BITS (RS); break;
10415 case 'M': USE_BITS (CCC); break;
10416 case 'N': USE_BITS (BCC); break;
10417 case 'R': USE_BITS (FR); break;
10418 case 'S': USE_BITS (FS); break;
10419 case 'T': USE_BITS (FT); break;
10420 case 'V': USE_BITS (FS); break;
10421 case 'a': USE_BITS (TARGET); break;
10422 case 'b': USE_BITS (RS); break;
10423 case 'c': USE_BITS (CODE); break;
10424 case 'd': USE_BITS (RD); break;
10425 case 'h': USE_BITS (PREFX); break;
10426 case 'i': USE_BITS (IMMEDIATE); break;
10427 case 'j': USE_BITS (DELTA); break;
10428 case 'k': USE_BITS (CACHE); break;
10429 case 'n': USE_BITS (RT); break;
10430 case 'o': USE_BITS (DELTA); break;
10431 case 'p': USE_BITS (DELTA); break;
10432 case 'q': USE_BITS (CODE2); break;
10433 case 'r': USE_BITS (RS); break;
10434 case 's': USE_BITS (RS); break;
10435 case 't': USE_BITS (RT); break;
10436 case 'u': USE_BITS (IMMEDIATE); break;
10437 case 'v': USE_BITS (RS); break;
10438 case 'w': USE_BITS (RT); break;
10439 case 'y': USE_BITS (RS3); break;
10441 case '|': USE_BITS (TRAP); break;
10442 case '~': USE_BITS (OFFSET12); break;
10444 as_bad (_("Internal error: bad microMIPS opcode "
10445 "(unknown operand type `%c'): %s %s"),
10446 c, opc->name, opc->args);
10450 if (used_bits != insn_bits)
10452 if (~used_bits & insn_bits)
10453 as_bad (_("Internal error: bad microMIPS opcode "
10454 "(bits 0x%lx undefined): %s %s"),
10455 ~used_bits & insn_bits, opc->name, opc->args);
10456 if (used_bits & ~insn_bits)
10457 as_bad (_("Internal error: bad microMIPS opcode "
10458 "(bits 0x%lx defined): %s %s"),
10459 used_bits & ~insn_bits, opc->name, opc->args);
10465 /* UDI immediates. */
10466 struct mips_immed {
10468 unsigned int shift;
10469 unsigned long mask;
10473 static const struct mips_immed mips_immed[] = {
10474 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10475 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10476 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10477 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10481 /* Check whether an odd floating-point register is allowed. */
10483 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10485 const char *s = insn->name;
10487 if (insn->pinfo == INSN_MACRO)
10488 /* Let a macro pass, we'll catch it later when it is expanded. */
10491 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10493 /* Allow odd registers for single-precision ops. */
10494 switch (insn->pinfo & (FP_S | FP_D))
10498 return 1; /* both single precision - ok */
10500 return 0; /* both double precision - fail */
10505 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10506 s = strchr (insn->name, '.');
10508 s = s != NULL ? strchr (s + 1, '.') : NULL;
10509 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10512 /* Single-precision coprocessor loads and moves are OK too. */
10513 if ((insn->pinfo & FP_S)
10514 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10515 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10521 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10522 taking bits from BIT up. */
10524 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10526 return (ep->X_op == O_constant
10527 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10528 && ep->X_add_number >= min << bit
10529 && ep->X_add_number < max << bit);
10532 /* This routine assembles an instruction into its binary format. As a
10533 side effect, it sets one of the global variables imm_reloc or
10534 offset_reloc to the type of relocation to do if one of the operands
10535 is an address expression. */
10538 mips_ip (char *str, struct mips_cl_insn *ip)
10540 bfd_boolean wrong_delay_slot_insns = FALSE;
10541 bfd_boolean need_delay_slot_ok = TRUE;
10542 struct mips_opcode *firstinsn = NULL;
10543 const struct mips_opcode *past;
10544 struct hash_control *hash;
10548 struct mips_opcode *insn;
10550 unsigned int regno;
10551 unsigned int lastregno;
10552 unsigned int destregno = 0;
10553 unsigned int lastpos = 0;
10554 unsigned int limlo, limhi;
10556 offsetT min_range, max_range;
10560 unsigned int rtype;
10566 if (mips_opts.micromips)
10568 hash = micromips_op_hash;
10569 past = µmips_opcodes[bfd_micromips_num_opcodes];
10574 past = &mips_opcodes[NUMOPCODES];
10576 forced_insn_length = 0;
10579 /* We first try to match an instruction up to a space or to the end. */
10580 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10583 /* Make a copy of the instruction so that we can fiddle with it. */
10584 name = alloca (end + 1);
10585 memcpy (name, str, end);
10590 insn = (struct mips_opcode *) hash_find (hash, name);
10592 if (insn != NULL || !mips_opts.micromips)
10594 if (forced_insn_length)
10597 /* See if there's an instruction size override suffix,
10598 either `16' or `32', at the end of the mnemonic proper,
10599 that defines the operation, i.e. before the first `.'
10600 character if any. Strip it and retry. */
10601 dot = strchr (name, '.');
10602 opend = dot != NULL ? dot - name : end;
10605 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10606 forced_insn_length = 2;
10607 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10608 forced_insn_length = 4;
10611 memcpy (name + opend - 2, name + opend, end - opend + 1);
10615 insn_error = _("Unrecognized opcode");
10619 /* For microMIPS instructions placed in a fixed-length branch delay slot
10620 we make up to two passes over the relevant fragment of the opcode
10621 table. First we try instructions that meet the delay slot's length
10622 requirement. If none matched, then we retry with the remaining ones
10623 and if one matches, then we use it and then issue an appropriate
10624 warning later on. */
10625 argsStart = s = str + end;
10628 bfd_boolean delay_slot_ok;
10629 bfd_boolean size_ok;
10632 gas_assert (strcmp (insn->name, name) == 0);
10634 ok = is_opcode_valid (insn);
10635 size_ok = is_size_valid (insn);
10636 delay_slot_ok = is_delay_slot_valid (insn);
10637 if (!delay_slot_ok && !wrong_delay_slot_insns)
10640 wrong_delay_slot_insns = TRUE;
10642 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10644 static char buf[256];
10646 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10651 if (wrong_delay_slot_insns && need_delay_slot_ok)
10653 gas_assert (firstinsn);
10654 need_delay_slot_ok = FALSE;
10664 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10665 mips_cpu_info_from_arch (mips_opts.arch)->name,
10666 mips_cpu_info_from_isa (mips_opts.isa)->name);
10668 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10669 8 * forced_insn_length);
10675 create_insn (ip, insn);
10678 lastregno = 0xffffffff;
10679 for (args = insn->args;; ++args)
10683 s += strspn (s, " \t");
10687 case '\0': /* end of args */
10692 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10693 gas_assert (!mips_opts.micromips);
10694 my_getExpression (&imm_expr, s);
10695 check_absolute_expr (ip, &imm_expr);
10696 if ((unsigned long) imm_expr.X_add_number != 1
10697 && (unsigned long) imm_expr.X_add_number != 3)
10699 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10700 (unsigned long) imm_expr.X_add_number);
10702 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
10703 imm_expr.X_op = O_absent;
10707 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10708 gas_assert (!mips_opts.micromips);
10709 my_getExpression (&imm_expr, s);
10710 check_absolute_expr (ip, &imm_expr);
10711 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10713 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10714 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
10716 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
10717 imm_expr.X_op = O_absent;
10721 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10722 gas_assert (!mips_opts.micromips);
10723 my_getExpression (&imm_expr, s);
10724 check_absolute_expr (ip, &imm_expr);
10725 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10727 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10728 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
10730 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
10731 imm_expr.X_op = O_absent;
10735 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10736 gas_assert (!mips_opts.micromips);
10737 my_getExpression (&imm_expr, s);
10738 check_absolute_expr (ip, &imm_expr);
10739 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10741 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10742 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
10744 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
10745 imm_expr.X_op = O_absent;
10749 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10750 gas_assert (!mips_opts.micromips);
10751 my_getExpression (&imm_expr, s);
10752 check_absolute_expr (ip, &imm_expr);
10753 if (imm_expr.X_add_number & ~OP_MASK_RS)
10755 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10756 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
10758 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
10759 imm_expr.X_op = O_absent;
10763 case '7': /* Four DSP accumulators in bits 11,12. */
10764 gas_assert (!mips_opts.micromips);
10765 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10766 s[3] >= '0' && s[3] <= '3')
10768 regno = s[3] - '0';
10770 INSERT_OPERAND (0, DSPACC, *ip, regno);
10774 as_bad (_("Invalid dsp acc register"));
10777 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10778 gas_assert (!mips_opts.micromips);
10779 my_getExpression (&imm_expr, s);
10780 check_absolute_expr (ip, &imm_expr);
10781 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10783 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10785 (unsigned long) imm_expr.X_add_number);
10787 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
10788 imm_expr.X_op = O_absent;
10792 case '9': /* Four DSP accumulators in bits 21,22. */
10793 gas_assert (!mips_opts.micromips);
10794 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10795 s[3] >= '0' && s[3] <= '3')
10797 regno = s[3] - '0';
10799 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10803 as_bad (_("Invalid dsp acc register"));
10806 case '0': /* DSP 6-bit signed immediate in bit 20. */
10807 gas_assert (!mips_opts.micromips);
10808 my_getExpression (&imm_expr, s);
10809 check_absolute_expr (ip, &imm_expr);
10810 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10811 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10812 if (imm_expr.X_add_number < min_range ||
10813 imm_expr.X_add_number > max_range)
10815 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10816 (long) min_range, (long) max_range,
10817 (long) imm_expr.X_add_number);
10819 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
10820 imm_expr.X_op = O_absent;
10824 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10825 gas_assert (!mips_opts.micromips);
10826 my_getExpression (&imm_expr, s);
10827 check_absolute_expr (ip, &imm_expr);
10828 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10830 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10832 (unsigned long) imm_expr.X_add_number);
10834 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10835 imm_expr.X_op = O_absent;
10839 case ':': /* DSP 7-bit signed immediate in bit 19. */
10840 gas_assert (!mips_opts.micromips);
10841 my_getExpression (&imm_expr, s);
10842 check_absolute_expr (ip, &imm_expr);
10843 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10844 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10845 if (imm_expr.X_add_number < min_range ||
10846 imm_expr.X_add_number > max_range)
10848 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10849 (long) min_range, (long) max_range,
10850 (long) imm_expr.X_add_number);
10852 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10853 imm_expr.X_op = O_absent;
10857 case '@': /* DSP 10-bit signed immediate in bit 16. */
10858 gas_assert (!mips_opts.micromips);
10859 my_getExpression (&imm_expr, s);
10860 check_absolute_expr (ip, &imm_expr);
10861 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10862 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10863 if (imm_expr.X_add_number < min_range ||
10864 imm_expr.X_add_number > max_range)
10866 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10867 (long) min_range, (long) max_range,
10868 (long) imm_expr.X_add_number);
10870 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
10871 imm_expr.X_op = O_absent;
10875 case '!': /* MT usermode flag bit. */
10876 gas_assert (!mips_opts.micromips);
10877 my_getExpression (&imm_expr, s);
10878 check_absolute_expr (ip, &imm_expr);
10879 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10880 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10881 (unsigned long) imm_expr.X_add_number);
10882 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10883 imm_expr.X_op = O_absent;
10887 case '$': /* MT load high flag bit. */
10888 gas_assert (!mips_opts.micromips);
10889 my_getExpression (&imm_expr, s);
10890 check_absolute_expr (ip, &imm_expr);
10891 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10892 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10893 (unsigned long) imm_expr.X_add_number);
10894 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10895 imm_expr.X_op = O_absent;
10899 case '*': /* Four DSP accumulators in bits 18,19. */
10900 gas_assert (!mips_opts.micromips);
10901 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10902 s[3] >= '0' && s[3] <= '3')
10904 regno = s[3] - '0';
10906 INSERT_OPERAND (0, MTACC_T, *ip, regno);
10910 as_bad (_("Invalid dsp/smartmips acc register"));
10913 case '&': /* Four DSP accumulators in bits 13,14. */
10914 gas_assert (!mips_opts.micromips);
10915 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10916 s[3] >= '0' && s[3] <= '3')
10918 regno = s[3] - '0';
10920 INSERT_OPERAND (0, MTACC_D, *ip, regno);
10924 as_bad (_("Invalid dsp/smartmips acc register"));
10936 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
10940 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
10944 gas_assert (!mips_opts.micromips);
10945 INSERT_OPERAND (0, FT, *ip, lastregno);
10949 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
10955 /* Handle optional base register.
10956 Either the base register is omitted or
10957 we must have a left paren. */
10958 /* This is dependent on the next operand specifier
10959 is a base register specification. */
10960 gas_assert (args[1] == 'b'
10961 || (mips_opts.micromips
10963 && (args[2] == 'l' || args[2] == 'n'
10964 || args[2] == 's' || args[2] == 'a')));
10965 if (*s == '\0' && args[1] == 'b')
10967 /* Fall through. */
10969 case ')': /* These must match exactly. */
10974 case '[': /* These must match exactly. */
10976 gas_assert (!mips_opts.micromips);
10981 case '+': /* Opcode extension character. */
10984 case '1': /* UDI immediates. */
10988 gas_assert (!mips_opts.micromips);
10990 const struct mips_immed *imm = mips_immed;
10992 while (imm->type && imm->type != *args)
10996 my_getExpression (&imm_expr, s);
10997 check_absolute_expr (ip, &imm_expr);
10998 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11000 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11001 imm->desc ? imm->desc : ip->insn_mo->name,
11002 (unsigned long) imm_expr.X_add_number,
11003 (unsigned long) imm_expr.X_add_number);
11004 imm_expr.X_add_number &= imm->mask;
11006 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11008 imm_expr.X_op = O_absent;
11013 case 'A': /* ins/ext position, becomes LSB. */
11022 my_getExpression (&imm_expr, s);
11023 check_absolute_expr (ip, &imm_expr);
11024 if ((unsigned long) imm_expr.X_add_number < limlo
11025 || (unsigned long) imm_expr.X_add_number > limhi)
11027 as_bad (_("Improper position (%lu)"),
11028 (unsigned long) imm_expr.X_add_number);
11029 imm_expr.X_add_number = limlo;
11031 lastpos = imm_expr.X_add_number;
11032 INSERT_OPERAND (mips_opts.micromips,
11033 EXTLSB, *ip, imm_expr.X_add_number);
11034 imm_expr.X_op = O_absent;
11038 case 'B': /* ins size, becomes MSB. */
11047 my_getExpression (&imm_expr, s);
11048 check_absolute_expr (ip, &imm_expr);
11049 /* Check for negative input so that small negative numbers
11050 will not succeed incorrectly. The checks against
11051 (pos+size) transitively check "size" itself,
11052 assuming that "pos" is reasonable. */
11053 if ((long) imm_expr.X_add_number < 0
11054 || ((unsigned long) imm_expr.X_add_number
11056 || ((unsigned long) imm_expr.X_add_number
11057 + lastpos) > limhi)
11059 as_bad (_("Improper insert size (%lu, position %lu)"),
11060 (unsigned long) imm_expr.X_add_number,
11061 (unsigned long) lastpos);
11062 imm_expr.X_add_number = limlo - lastpos;
11064 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11065 lastpos + imm_expr.X_add_number - 1);
11066 imm_expr.X_op = O_absent;
11070 case 'C': /* ext size, becomes MSBD. */
11083 my_getExpression (&imm_expr, s);
11084 check_absolute_expr (ip, &imm_expr);
11085 /* Check for negative input so that small negative numbers
11086 will not succeed incorrectly. The checks against
11087 (pos+size) transitively check "size" itself,
11088 assuming that "pos" is reasonable. */
11089 if ((long) imm_expr.X_add_number < 0
11090 || ((unsigned long) imm_expr.X_add_number
11092 || ((unsigned long) imm_expr.X_add_number
11093 + lastpos) > limhi)
11095 as_bad (_("Improper extract size (%lu, position %lu)"),
11096 (unsigned long) imm_expr.X_add_number,
11097 (unsigned long) lastpos);
11098 imm_expr.X_add_number = limlo - lastpos;
11100 INSERT_OPERAND (mips_opts.micromips,
11101 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11102 imm_expr.X_op = O_absent;
11107 /* +D is for disassembly only; never match. */
11111 /* "+I" is like "I", except that imm2_expr is used. */
11112 my_getExpression (&imm2_expr, s);
11113 if (imm2_expr.X_op != O_big
11114 && imm2_expr.X_op != O_constant)
11115 insn_error = _("absolute expression required");
11116 if (HAVE_32BIT_GPRS)
11117 normalize_constant_expr (&imm2_expr);
11121 case 'T': /* Coprocessor register. */
11122 gas_assert (!mips_opts.micromips);
11123 /* +T is for disassembly only; never match. */
11126 case 't': /* Coprocessor register number. */
11127 gas_assert (!mips_opts.micromips);
11128 if (s[0] == '$' && ISDIGIT (s[1]))
11138 while (ISDIGIT (*s));
11140 as_bad (_("Invalid register number (%d)"), regno);
11143 INSERT_OPERAND (0, RT, *ip, regno);
11148 as_bad (_("Invalid coprocessor 0 register number"));
11152 /* bbit[01] and bbit[01]32 bit index. Give error if index
11153 is not in the valid range. */
11154 gas_assert (!mips_opts.micromips);
11155 my_getExpression (&imm_expr, s);
11156 check_absolute_expr (ip, &imm_expr);
11157 if ((unsigned) imm_expr.X_add_number > 31)
11159 as_bad (_("Improper bit index (%lu)"),
11160 (unsigned long) imm_expr.X_add_number);
11161 imm_expr.X_add_number = 0;
11163 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11164 imm_expr.X_op = O_absent;
11169 /* bbit[01] bit index when bbit is used but we generate
11170 bbit[01]32 because the index is over 32. Move to the
11171 next candidate if index is not in the valid range. */
11172 gas_assert (!mips_opts.micromips);
11173 my_getExpression (&imm_expr, s);
11174 check_absolute_expr (ip, &imm_expr);
11175 if ((unsigned) imm_expr.X_add_number < 32
11176 || (unsigned) imm_expr.X_add_number > 63)
11178 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11179 imm_expr.X_op = O_absent;
11184 /* cins, cins32, exts and exts32 position field. Give error
11185 if it's not in the valid range. */
11186 gas_assert (!mips_opts.micromips);
11187 my_getExpression (&imm_expr, s);
11188 check_absolute_expr (ip, &imm_expr);
11189 if ((unsigned) imm_expr.X_add_number > 31)
11191 as_bad (_("Improper position (%lu)"),
11192 (unsigned long) imm_expr.X_add_number);
11193 imm_expr.X_add_number = 0;
11195 /* Make the pos explicit to simplify +S. */
11196 lastpos = imm_expr.X_add_number + 32;
11197 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11198 imm_expr.X_op = O_absent;
11203 /* cins, cins32, exts and exts32 position field. Move to
11204 the next candidate if it's not in the valid range. */
11205 gas_assert (!mips_opts.micromips);
11206 my_getExpression (&imm_expr, s);
11207 check_absolute_expr (ip, &imm_expr);
11208 if ((unsigned) imm_expr.X_add_number < 32
11209 || (unsigned) imm_expr.X_add_number > 63)
11211 lastpos = imm_expr.X_add_number;
11212 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11213 imm_expr.X_op = O_absent;
11218 /* cins and exts length-minus-one field. */
11219 gas_assert (!mips_opts.micromips);
11220 my_getExpression (&imm_expr, s);
11221 check_absolute_expr (ip, &imm_expr);
11222 if ((unsigned long) imm_expr.X_add_number > 31)
11224 as_bad (_("Improper size (%lu)"),
11225 (unsigned long) imm_expr.X_add_number);
11226 imm_expr.X_add_number = 0;
11228 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11229 imm_expr.X_op = O_absent;
11234 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11235 length-minus-one field. */
11236 gas_assert (!mips_opts.micromips);
11237 my_getExpression (&imm_expr, s);
11238 check_absolute_expr (ip, &imm_expr);
11239 if ((long) imm_expr.X_add_number < 0
11240 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11242 as_bad (_("Improper size (%lu)"),
11243 (unsigned long) imm_expr.X_add_number);
11244 imm_expr.X_add_number = 0;
11246 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11247 imm_expr.X_op = O_absent;
11252 /* seqi/snei immediate field. */
11253 gas_assert (!mips_opts.micromips);
11254 my_getExpression (&imm_expr, s);
11255 check_absolute_expr (ip, &imm_expr);
11256 if ((long) imm_expr.X_add_number < -512
11257 || (long) imm_expr.X_add_number >= 512)
11259 as_bad (_("Improper immediate (%ld)"),
11260 (long) imm_expr.X_add_number);
11261 imm_expr.X_add_number = 0;
11263 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11264 imm_expr.X_op = O_absent;
11268 case 'a': /* 8-bit signed offset in bit 6 */
11269 gas_assert (!mips_opts.micromips);
11270 my_getExpression (&imm_expr, s);
11271 check_absolute_expr (ip, &imm_expr);
11272 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11273 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11274 if (imm_expr.X_add_number < min_range
11275 || imm_expr.X_add_number > max_range)
11277 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11278 (long) min_range, (long) max_range,
11279 (long) imm_expr.X_add_number);
11281 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11282 imm_expr.X_op = O_absent;
11286 case 'b': /* 8-bit signed offset in bit 3 */
11287 gas_assert (!mips_opts.micromips);
11288 my_getExpression (&imm_expr, s);
11289 check_absolute_expr (ip, &imm_expr);
11290 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11291 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11292 if (imm_expr.X_add_number < min_range
11293 || imm_expr.X_add_number > max_range)
11295 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11296 (long) min_range, (long) max_range,
11297 (long) imm_expr.X_add_number);
11299 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11300 imm_expr.X_op = O_absent;
11304 case 'c': /* 9-bit signed offset in bit 6 */
11305 gas_assert (!mips_opts.micromips);
11306 my_getExpression (&imm_expr, s);
11307 check_absolute_expr (ip, &imm_expr);
11308 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11309 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11310 /* We check the offset range before adjusted. */
11313 if (imm_expr.X_add_number < min_range
11314 || imm_expr.X_add_number > max_range)
11316 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11317 (long) min_range, (long) max_range,
11318 (long) imm_expr.X_add_number);
11320 if (imm_expr.X_add_number & 0xf)
11322 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11323 (long) imm_expr.X_add_number);
11325 /* Right shift 4 bits to adjust the offset operand. */
11326 INSERT_OPERAND (0, OFFSET_C, *ip,
11327 imm_expr.X_add_number >> 4);
11328 imm_expr.X_op = O_absent;
11333 gas_assert (!mips_opts.micromips);
11334 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11336 if (regno == AT && mips_opts.at)
11338 if (mips_opts.at == ATREG)
11339 as_warn (_("used $at without \".set noat\""));
11341 as_warn (_("used $%u with \".set at=$%u\""),
11342 regno, mips_opts.at);
11344 INSERT_OPERAND (0, RZ, *ip, regno);
11348 gas_assert (!mips_opts.micromips);
11349 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11351 INSERT_OPERAND (0, FZ, *ip, regno);
11355 as_bad (_("Internal error: bad %s opcode "
11356 "(unknown extension operand type `+%c'): %s %s"),
11357 mips_opts.micromips ? "microMIPS" : "MIPS",
11358 *args, insn->name, insn->args);
11359 /* Further processing is fruitless. */
11364 case '.': /* 10-bit offset. */
11365 case '~': /* 12-bit offset. */
11366 gas_assert (mips_opts.micromips);
11368 int shift = *args == '.' ? 9 : 11;
11371 /* Check whether there is only a single bracketed expression
11372 left. If so, it must be the base register and the
11373 constant must be zero. */
11374 if (*s == '(' && strchr (s + 1, '(') == 0)
11377 /* If this value won't fit into the offset, then go find
11378 a macro that will generate a 16- or 32-bit offset code
11380 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11381 if ((i == 0 && (imm_expr.X_op != O_constant
11382 || imm_expr.X_add_number >= 1 << shift
11383 || imm_expr.X_add_number < -1 << shift))
11386 imm_expr.X_op = O_absent;
11390 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11392 INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number);
11393 imm_expr.X_op = O_absent;
11398 case '<': /* must be at least one digit */
11400 * According to the manual, if the shift amount is greater
11401 * than 31 or less than 0, then the shift amount should be
11402 * mod 32. In reality the mips assembler issues an error.
11403 * We issue a warning and mask out all but the low 5 bits.
11405 my_getExpression (&imm_expr, s);
11406 check_absolute_expr (ip, &imm_expr);
11407 if ((unsigned long) imm_expr.X_add_number > 31)
11408 as_warn (_("Improper shift amount (%lu)"),
11409 (unsigned long) imm_expr.X_add_number);
11410 INSERT_OPERAND (mips_opts.micromips,
11411 SHAMT, *ip, imm_expr.X_add_number);
11412 imm_expr.X_op = O_absent;
11416 case '>': /* shift amount minus 32 */
11417 my_getExpression (&imm_expr, s);
11418 check_absolute_expr (ip, &imm_expr);
11419 if ((unsigned long) imm_expr.X_add_number < 32
11420 || (unsigned long) imm_expr.X_add_number > 63)
11422 INSERT_OPERAND (mips_opts.micromips,
11423 SHAMT, *ip, imm_expr.X_add_number - 32);
11424 imm_expr.X_op = O_absent;
11428 case 'k': /* CACHE code. */
11429 case 'h': /* PREFX code. */
11430 case '1': /* SYNC type. */
11431 my_getExpression (&imm_expr, s);
11432 check_absolute_expr (ip, &imm_expr);
11433 if ((unsigned long) imm_expr.X_add_number > 31)
11434 as_warn (_("Invalid value for `%s' (%lu)"),
11436 (unsigned long) imm_expr.X_add_number);
11440 if (mips_fix_cn63xxp1
11441 && !mips_opts.micromips
11442 && strcmp ("pref", insn->name) == 0)
11443 switch (imm_expr.X_add_number)
11452 case 31: /* These are ok. */
11455 default: /* The rest must be changed to 28. */
11456 imm_expr.X_add_number = 28;
11459 INSERT_OPERAND (mips_opts.micromips,
11460 CACHE, *ip, imm_expr.X_add_number);
11463 INSERT_OPERAND (mips_opts.micromips,
11464 PREFX, *ip, imm_expr.X_add_number);
11467 INSERT_OPERAND (mips_opts.micromips,
11468 STYPE, *ip, imm_expr.X_add_number);
11471 imm_expr.X_op = O_absent;
11475 case 'c': /* BREAK code. */
11477 unsigned long mask = (mips_opts.micromips
11478 ? MICROMIPSOP_MASK_CODE
11481 my_getExpression (&imm_expr, s);
11482 check_absolute_expr (ip, &imm_expr);
11483 if ((unsigned long) imm_expr.X_add_number > mask)
11484 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11486 mask, (unsigned long) imm_expr.X_add_number);
11487 INSERT_OPERAND (mips_opts.micromips,
11488 CODE, *ip, imm_expr.X_add_number);
11489 imm_expr.X_op = O_absent;
11494 case 'q': /* Lower BREAK code. */
11496 unsigned long mask = (mips_opts.micromips
11497 ? MICROMIPSOP_MASK_CODE2
11500 my_getExpression (&imm_expr, s);
11501 check_absolute_expr (ip, &imm_expr);
11502 if ((unsigned long) imm_expr.X_add_number > mask)
11503 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11505 mask, (unsigned long) imm_expr.X_add_number);
11506 INSERT_OPERAND (mips_opts.micromips,
11507 CODE2, *ip, imm_expr.X_add_number);
11508 imm_expr.X_op = O_absent;
11513 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11515 unsigned long mask = (mips_opts.micromips
11516 ? MICROMIPSOP_MASK_CODE10
11519 my_getExpression (&imm_expr, s);
11520 check_absolute_expr (ip, &imm_expr);
11521 if ((unsigned long) imm_expr.X_add_number > mask)
11522 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11524 mask, (unsigned long) imm_expr.X_add_number);
11525 if (mips_opts.micromips)
11526 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11528 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11529 imm_expr.X_op = O_absent;
11534 case 'C': /* 25- or 23-bit coprocessor code. */
11536 unsigned long mask = (mips_opts.micromips
11537 ? MICROMIPSOP_MASK_COPZ
11540 my_getExpression (&imm_expr, s);
11541 check_absolute_expr (ip, &imm_expr);
11542 if ((unsigned long) imm_expr.X_add_number > mask)
11543 as_warn (_("Coproccesor code > %u bits (%lu)"),
11544 mips_opts.micromips ? 23U : 25U,
11545 (unsigned long) imm_expr.X_add_number);
11546 INSERT_OPERAND (mips_opts.micromips,
11547 COPZ, *ip, imm_expr.X_add_number);
11548 imm_expr.X_op = O_absent;
11553 case 'J': /* 19-bit WAIT code. */
11554 gas_assert (!mips_opts.micromips);
11555 my_getExpression (&imm_expr, s);
11556 check_absolute_expr (ip, &imm_expr);
11557 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11559 as_warn (_("Illegal 19-bit code (%lu)"),
11560 (unsigned long) imm_expr.X_add_number);
11561 imm_expr.X_add_number &= OP_MASK_CODE19;
11563 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11564 imm_expr.X_op = O_absent;
11568 case 'P': /* Performance register. */
11569 gas_assert (!mips_opts.micromips);
11570 my_getExpression (&imm_expr, s);
11571 check_absolute_expr (ip, &imm_expr);
11572 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11573 as_warn (_("Invalid performance register (%lu)"),
11574 (unsigned long) imm_expr.X_add_number);
11575 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11576 imm_expr.X_op = O_absent;
11580 case 'G': /* Coprocessor destination register. */
11582 unsigned long opcode = ip->insn_opcode;
11583 unsigned long mask;
11584 unsigned int types;
11587 if (mips_opts.micromips)
11589 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11590 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11591 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11595 case 0x000000fc: /* mfc0 */
11596 case 0x000002fc: /* mtc0 */
11597 case 0x580000fc: /* dmfc0 */
11598 case 0x580002fc: /* dmtc0 */
11608 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11609 cop0 = opcode == OP_OP_COP0;
11611 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11612 ok = reg_lookup (&s, types, ®no);
11613 if (mips_opts.micromips)
11614 INSERT_OPERAND (1, RS, *ip, regno);
11616 INSERT_OPERAND (0, RD, *ip, regno);
11625 case 'y': /* ALNV.PS source register. */
11626 gas_assert (mips_opts.micromips);
11628 case 'x': /* Ignore register name. */
11629 case 'U': /* Destination register (CLO/CLZ). */
11630 case 'g': /* Coprocessor destination register. */
11631 gas_assert (!mips_opts.micromips);
11632 case 'b': /* Base register. */
11633 case 'd': /* Destination register. */
11634 case 's': /* Source register. */
11635 case 't': /* Target register. */
11636 case 'r': /* Both target and source. */
11637 case 'v': /* Both dest and source. */
11638 case 'w': /* Both dest and target. */
11639 case 'E': /* Coprocessor target register. */
11640 case 'K': /* RDHWR destination register. */
11641 case 'z': /* Must be zero register. */
11644 if (*args == 'E' || *args == 'K')
11645 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11648 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11649 if (regno == AT && mips_opts.at)
11651 if (mips_opts.at == ATREG)
11652 as_warn (_("Used $at without \".set noat\""));
11654 as_warn (_("Used $%u with \".set at=$%u\""),
11655 regno, mips_opts.at);
11665 if (c == 'r' || c == 'v' || c == 'w')
11672 /* 'z' only matches $0. */
11673 if (c == 'z' && regno != 0)
11676 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11678 if (regno == lastregno)
11681 = _("Source and destination must be different");
11684 if (regno == 31 && lastregno == 0xffffffff)
11687 = _("A destination register must be supplied");
11691 /* Now that we have assembled one operand, we use the args
11692 string to figure out where it goes in the instruction. */
11699 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11703 if (mips_opts.micromips)
11704 INSERT_OPERAND (1, RS, *ip, regno);
11706 INSERT_OPERAND (0, RD, *ip, regno);
11711 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11715 gas_assert (!mips_opts.micromips);
11716 INSERT_OPERAND (0, RD, *ip, regno);
11717 INSERT_OPERAND (0, RT, *ip, regno);
11723 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11727 gas_assert (mips_opts.micromips);
11728 INSERT_OPERAND (1, RS3, *ip, regno);
11732 /* This case exists because on the r3000 trunc
11733 expands into a macro which requires a gp
11734 register. On the r6000 or r4000 it is
11735 assembled into a single instruction which
11736 ignores the register. Thus the insn version
11737 is MIPS_ISA2 and uses 'x', and the macro
11738 version is MIPS_ISA1 and uses 't'. */
11742 /* This case is for the div instruction, which
11743 acts differently if the destination argument
11744 is $0. This only matches $0, and is checked
11745 outside the switch. */
11755 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11759 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11764 case 'O': /* MDMX alignment immediate constant. */
11765 gas_assert (!mips_opts.micromips);
11766 my_getExpression (&imm_expr, s);
11767 check_absolute_expr (ip, &imm_expr);
11768 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11769 as_warn (_("Improper align amount (%ld), using low bits"),
11770 (long) imm_expr.X_add_number);
11771 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11772 imm_expr.X_op = O_absent;
11776 case 'Q': /* MDMX vector, element sel, or const. */
11779 /* MDMX Immediate. */
11780 gas_assert (!mips_opts.micromips);
11781 my_getExpression (&imm_expr, s);
11782 check_absolute_expr (ip, &imm_expr);
11783 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11784 as_warn (_("Invalid MDMX Immediate (%ld)"),
11785 (long) imm_expr.X_add_number);
11786 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11787 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11788 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11790 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11791 imm_expr.X_op = O_absent;
11795 /* Not MDMX Immediate. Fall through. */
11796 case 'X': /* MDMX destination register. */
11797 case 'Y': /* MDMX source register. */
11798 case 'Z': /* MDMX target register. */
11801 gas_assert (!mips_opts.micromips);
11802 case 'D': /* Floating point destination register. */
11803 case 'S': /* Floating point source register. */
11804 case 'T': /* Floating point target register. */
11805 case 'R': /* Floating point source register. */
11809 || (mips_opts.ase_mdmx
11810 && (ip->insn_mo->pinfo & FP_D)
11811 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11812 | INSN_COPROC_MEMORY_DELAY
11813 | INSN_LOAD_COPROC_DELAY
11814 | INSN_LOAD_MEMORY_DELAY
11815 | INSN_STORE_MEMORY))))
11816 rtype |= RTYPE_VEC;
11818 if (reg_lookup (&s, rtype, ®no))
11820 if ((regno & 1) != 0
11822 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11823 as_warn (_("Float register should be even, was %d"),
11831 if (c == 'V' || c == 'W')
11842 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11848 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11852 /* This is like 'Z', but also needs to fix the MDMX
11853 vector/scalar select bits. Note that the
11854 scalar immediate case is handled above. */
11857 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11858 int max_el = (is_qh ? 3 : 7);
11860 my_getExpression(&imm_expr, s);
11861 check_absolute_expr (ip, &imm_expr);
11863 if (imm_expr.X_add_number > max_el)
11864 as_bad (_("Bad element selector %ld"),
11865 (long) imm_expr.X_add_number);
11866 imm_expr.X_add_number &= max_el;
11867 ip->insn_opcode |= (imm_expr.X_add_number
11870 imm_expr.X_op = O_absent;
11872 as_warn (_("Expecting ']' found '%s'"), s);
11878 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11879 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11882 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11885 /* Fall through. */
11889 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
11893 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
11903 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11907 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
11913 my_getExpression (&imm_expr, s);
11914 if (imm_expr.X_op != O_big
11915 && imm_expr.X_op != O_constant)
11916 insn_error = _("absolute expression required");
11917 if (HAVE_32BIT_GPRS)
11918 normalize_constant_expr (&imm_expr);
11923 my_getExpression (&offset_expr, s);
11924 normalize_address_expr (&offset_expr);
11925 *imm_reloc = BFD_RELOC_32;
11938 unsigned char temp[8];
11940 unsigned int length;
11945 /* These only appear as the last operand in an
11946 instruction, and every instruction that accepts
11947 them in any variant accepts them in all variants.
11948 This means we don't have to worry about backing out
11949 any changes if the instruction does not match.
11951 The difference between them is the size of the
11952 floating point constant and where it goes. For 'F'
11953 and 'L' the constant is 64 bits; for 'f' and 'l' it
11954 is 32 bits. Where the constant is placed is based
11955 on how the MIPS assembler does things:
11958 f -- immediate value
11961 The .lit4 and .lit8 sections are only used if
11962 permitted by the -G argument.
11964 The code below needs to know whether the target register
11965 is 32 or 64 bits wide. It relies on the fact 'f' and
11966 'F' are used with GPR-based instructions and 'l' and
11967 'L' are used with FPR-based instructions. */
11969 f64 = *args == 'F' || *args == 'L';
11970 using_gprs = *args == 'F' || *args == 'f';
11972 save_in = input_line_pointer;
11973 input_line_pointer = s;
11974 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
11976 s = input_line_pointer;
11977 input_line_pointer = save_in;
11978 if (err != NULL && *err != '\0')
11980 as_bad (_("Bad floating point constant: %s"), err);
11981 memset (temp, '\0', sizeof temp);
11982 length = f64 ? 8 : 4;
11985 gas_assert (length == (unsigned) (f64 ? 8 : 4));
11989 && (g_switch_value < 4
11990 || (temp[0] == 0 && temp[1] == 0)
11991 || (temp[2] == 0 && temp[3] == 0))))
11993 imm_expr.X_op = O_constant;
11994 if (!target_big_endian)
11995 imm_expr.X_add_number = bfd_getl32 (temp);
11997 imm_expr.X_add_number = bfd_getb32 (temp);
11999 else if (length > 4
12000 && !mips_disable_float_construction
12001 /* Constants can only be constructed in GPRs and
12002 copied to FPRs if the GPRs are at least as wide
12003 as the FPRs. Force the constant into memory if
12004 we are using 64-bit FPRs but the GPRs are only
12007 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12008 && ((temp[0] == 0 && temp[1] == 0)
12009 || (temp[2] == 0 && temp[3] == 0))
12010 && ((temp[4] == 0 && temp[5] == 0)
12011 || (temp[6] == 0 && temp[7] == 0)))
12013 /* The value is simple enough to load with a couple of
12014 instructions. If using 32-bit registers, set
12015 imm_expr to the high order 32 bits and offset_expr to
12016 the low order 32 bits. Otherwise, set imm_expr to
12017 the entire 64 bit constant. */
12018 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12020 imm_expr.X_op = O_constant;
12021 offset_expr.X_op = O_constant;
12022 if (!target_big_endian)
12024 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12025 offset_expr.X_add_number = bfd_getl32 (temp);
12029 imm_expr.X_add_number = bfd_getb32 (temp);
12030 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12032 if (offset_expr.X_add_number == 0)
12033 offset_expr.X_op = O_absent;
12035 else if (sizeof (imm_expr.X_add_number) > 4)
12037 imm_expr.X_op = O_constant;
12038 if (!target_big_endian)
12039 imm_expr.X_add_number = bfd_getl64 (temp);
12041 imm_expr.X_add_number = bfd_getb64 (temp);
12045 imm_expr.X_op = O_big;
12046 imm_expr.X_add_number = 4;
12047 if (!target_big_endian)
12049 generic_bignum[0] = bfd_getl16 (temp);
12050 generic_bignum[1] = bfd_getl16 (temp + 2);
12051 generic_bignum[2] = bfd_getl16 (temp + 4);
12052 generic_bignum[3] = bfd_getl16 (temp + 6);
12056 generic_bignum[0] = bfd_getb16 (temp + 6);
12057 generic_bignum[1] = bfd_getb16 (temp + 4);
12058 generic_bignum[2] = bfd_getb16 (temp + 2);
12059 generic_bignum[3] = bfd_getb16 (temp);
12065 const char *newname;
12068 /* Switch to the right section. */
12070 subseg = now_subseg;
12073 default: /* unused default case avoids warnings. */
12075 newname = RDATA_SECTION_NAME;
12076 if (g_switch_value >= 8)
12080 newname = RDATA_SECTION_NAME;
12083 gas_assert (g_switch_value >= 4);
12087 new_seg = subseg_new (newname, (subsegT) 0);
12089 bfd_set_section_flags (stdoutput, new_seg,
12094 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12095 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12096 record_alignment (new_seg, 4);
12098 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12099 if (seg == now_seg)
12100 as_bad (_("Can't use floating point insn in this section"));
12102 /* Set the argument to the current address in the
12104 offset_expr.X_op = O_symbol;
12105 offset_expr.X_add_symbol = symbol_temp_new_now ();
12106 offset_expr.X_add_number = 0;
12108 /* Put the floating point number into the section. */
12109 p = frag_more ((int) length);
12110 memcpy (p, temp, length);
12112 /* Switch back to the original section. */
12113 subseg_set (seg, subseg);
12118 case 'i': /* 16-bit unsigned immediate. */
12119 case 'j': /* 16-bit signed immediate. */
12120 *imm_reloc = BFD_RELOC_LO16;
12121 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12124 offsetT minval, maxval;
12126 more = (insn + 1 < past
12127 && strcmp (insn->name, insn[1].name) == 0);
12129 /* If the expression was written as an unsigned number,
12130 only treat it as signed if there are no more
12134 && sizeof (imm_expr.X_add_number) <= 4
12135 && imm_expr.X_op == O_constant
12136 && imm_expr.X_add_number < 0
12137 && imm_expr.X_unsigned
12138 && HAVE_64BIT_GPRS)
12141 /* For compatibility with older assemblers, we accept
12142 0x8000-0xffff as signed 16-bit numbers when only
12143 signed numbers are allowed. */
12145 minval = 0, maxval = 0xffff;
12147 minval = -0x8000, maxval = 0x7fff;
12149 minval = -0x8000, maxval = 0xffff;
12151 if (imm_expr.X_op != O_constant
12152 || imm_expr.X_add_number < minval
12153 || imm_expr.X_add_number > maxval)
12157 if (imm_expr.X_op == O_constant
12158 || imm_expr.X_op == O_big)
12159 as_bad (_("Expression out of range"));
12165 case 'o': /* 16-bit offset. */
12166 offset_reloc[0] = BFD_RELOC_LO16;
12167 offset_reloc[1] = BFD_RELOC_UNUSED;
12168 offset_reloc[2] = BFD_RELOC_UNUSED;
12170 /* Check whether there is only a single bracketed expression
12171 left. If so, it must be the base register and the
12172 constant must be zero. */
12173 if (*s == '(' && strchr (s + 1, '(') == 0)
12175 offset_expr.X_op = O_constant;
12176 offset_expr.X_add_number = 0;
12180 /* If this value won't fit into a 16 bit offset, then go
12181 find a macro that will generate the 32 bit offset
12183 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12184 && (offset_expr.X_op != O_constant
12185 || offset_expr.X_add_number >= 0x8000
12186 || offset_expr.X_add_number < -0x8000))
12192 case 'p': /* PC-relative offset. */
12193 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12194 my_getExpression (&offset_expr, s);
12198 case 'u': /* Upper 16 bits. */
12199 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12200 && imm_expr.X_op == O_constant
12201 && (imm_expr.X_add_number < 0
12202 || imm_expr.X_add_number >= 0x10000))
12203 as_bad (_("lui expression (%lu) not in range 0..65535"),
12204 (unsigned long) imm_expr.X_add_number);
12208 case 'a': /* 26-bit address. */
12209 *offset_reloc = BFD_RELOC_MIPS_JMP;
12210 my_getExpression (&offset_expr, s);
12214 case 'N': /* 3-bit branch condition code. */
12215 case 'M': /* 3-bit compare condition code. */
12217 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12218 rtype |= RTYPE_FCC;
12219 if (!reg_lookup (&s, rtype, ®no))
12221 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12222 || strcmp (str + strlen (str) - 5, "any2f") == 0
12223 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12224 && (regno & 1) != 0)
12225 as_warn (_("Condition code register should be even for %s, "
12228 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12229 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12230 && (regno & 3) != 0)
12231 as_warn (_("Condition code register should be 0 or 4 for %s, "
12235 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12237 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12241 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12252 while (ISDIGIT (*s));
12255 c = 8; /* Invalid sel value. */
12258 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12259 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12263 gas_assert (!mips_opts.micromips);
12264 /* Must be at least one digit. */
12265 my_getExpression (&imm_expr, s);
12266 check_absolute_expr (ip, &imm_expr);
12268 if ((unsigned long) imm_expr.X_add_number
12269 > (unsigned long) OP_MASK_VECBYTE)
12271 as_bad (_("bad byte vector index (%ld)"),
12272 (long) imm_expr.X_add_number);
12273 imm_expr.X_add_number = 0;
12276 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12277 imm_expr.X_op = O_absent;
12282 gas_assert (!mips_opts.micromips);
12283 my_getExpression (&imm_expr, s);
12284 check_absolute_expr (ip, &imm_expr);
12286 if ((unsigned long) imm_expr.X_add_number
12287 > (unsigned long) OP_MASK_VECALIGN)
12289 as_bad (_("bad byte vector index (%ld)"),
12290 (long) imm_expr.X_add_number);
12291 imm_expr.X_add_number = 0;
12294 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12295 imm_expr.X_op = O_absent;
12299 case 'm': /* Opcode extension character. */
12300 gas_assert (mips_opts.micromips);
12305 if (strncmp (s, "$pc", 3) == 0)
12333 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12334 if (regno == AT && mips_opts.at)
12336 if (mips_opts.at == ATREG)
12337 as_warn (_("Used $at without \".set noat\""));
12339 as_warn (_("Used $%u with \".set at=$%u\""),
12340 regno, mips_opts.at);
12346 gas_assert (args[1] == ',');
12352 gas_assert (args[1] == ',');
12354 continue; /* Nothing to do. */
12360 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12362 if (regno == lastregno)
12365 = _("Source and destination must be different");
12368 if (regno == 31 && lastregno == 0xffffffff)
12371 = _("A destination register must be supplied");
12382 gas_assert (args[1] == ',');
12389 gas_assert (args[1] == ',');
12392 continue; /* Nothing to do. */
12396 /* Make sure regno is the same as lastregno. */
12397 if (c == 't' && regno != lastregno)
12400 /* Make sure regno is the same as destregno. */
12401 if (c == 'x' && regno != destregno)
12404 /* We need to save regno, before regno maps to the
12405 microMIPS register encoding. */
12415 regno = ILLEGAL_REG;
12419 regno = mips32_to_micromips_reg_b_map[regno];
12423 regno = mips32_to_micromips_reg_c_map[regno];
12427 regno = mips32_to_micromips_reg_d_map[regno];
12431 regno = mips32_to_micromips_reg_e_map[regno];
12435 regno = mips32_to_micromips_reg_f_map[regno];
12439 regno = mips32_to_micromips_reg_g_map[regno];
12443 regno = mips32_to_micromips_reg_h_map[regno];
12447 switch (EXTRACT_OPERAND (1, MI, *ip))
12452 else if (regno == 22)
12454 else if (regno == 5)
12456 else if (regno == 6)
12458 else if (regno == 7)
12461 regno = ILLEGAL_REG;
12467 else if (regno == 7)
12470 regno = ILLEGAL_REG;
12477 regno = ILLEGAL_REG;
12481 regno = ILLEGAL_REG;
12487 regno = mips32_to_micromips_reg_l_map[regno];
12491 regno = mips32_to_micromips_reg_m_map[regno];
12495 regno = mips32_to_micromips_reg_n_map[regno];
12499 regno = mips32_to_micromips_reg_q_map[regno];
12504 regno = ILLEGAL_REG;
12509 regno = ILLEGAL_REG;
12514 regno = ILLEGAL_REG;
12517 case 'j': /* Do nothing. */
12527 if (regno == ILLEGAL_REG)
12533 INSERT_OPERAND (1, MB, *ip, regno);
12537 INSERT_OPERAND (1, MC, *ip, regno);
12541 INSERT_OPERAND (1, MD, *ip, regno);
12545 INSERT_OPERAND (1, ME, *ip, regno);
12549 INSERT_OPERAND (1, MF, *ip, regno);
12553 INSERT_OPERAND (1, MG, *ip, regno);
12557 INSERT_OPERAND (1, MH, *ip, regno);
12561 INSERT_OPERAND (1, MI, *ip, regno);
12565 INSERT_OPERAND (1, MJ, *ip, regno);
12569 INSERT_OPERAND (1, ML, *ip, regno);
12573 INSERT_OPERAND (1, MM, *ip, regno);
12577 INSERT_OPERAND (1, MN, *ip, regno);
12581 INSERT_OPERAND (1, MP, *ip, regno);
12585 INSERT_OPERAND (1, MQ, *ip, regno);
12588 case 'a': /* Do nothing. */
12589 case 's': /* Do nothing. */
12590 case 't': /* Do nothing. */
12591 case 'x': /* Do nothing. */
12592 case 'y': /* Do nothing. */
12593 case 'z': /* Do nothing. */
12603 bfd_reloc_code_real_type r[3];
12607 /* Check whether there is only a single bracketed
12608 expression left. If so, it must be the base register
12609 and the constant must be zero. */
12610 if (*s == '(' && strchr (s + 1, '(') == 0)
12612 INSERT_OPERAND (1, IMMA, *ip, 0);
12616 if (my_getSmallExpression (&ep, r, s) > 0
12617 || !expr_const_in_range (&ep, -64, 64, 2))
12620 imm = ep.X_add_number >> 2;
12621 INSERT_OPERAND (1, IMMA, *ip, imm);
12628 bfd_reloc_code_real_type r[3];
12632 if (my_getSmallExpression (&ep, r, s) > 0
12633 || ep.X_op != O_constant)
12636 for (imm = 0; imm < 8; imm++)
12637 if (micromips_imm_b_map[imm] == ep.X_add_number)
12642 INSERT_OPERAND (1, IMMB, *ip, imm);
12649 bfd_reloc_code_real_type r[3];
12653 if (my_getSmallExpression (&ep, r, s) > 0
12654 || ep.X_op != O_constant)
12657 for (imm = 0; imm < 16; imm++)
12658 if (micromips_imm_c_map[imm] == ep.X_add_number)
12663 INSERT_OPERAND (1, IMMC, *ip, imm);
12668 case 'D': /* pc relative offset */
12669 case 'E': /* pc relative offset */
12670 my_getExpression (&offset_expr, s);
12671 if (offset_expr.X_op == O_register)
12674 if (!forced_insn_length)
12675 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12677 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12679 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12685 bfd_reloc_code_real_type r[3];
12689 if (my_getSmallExpression (&ep, r, s) > 0
12690 || !expr_const_in_range (&ep, 0, 16, 0))
12693 imm = ep.X_add_number;
12694 INSERT_OPERAND (1, IMMF, *ip, imm);
12701 bfd_reloc_code_real_type r[3];
12705 /* Check whether there is only a single bracketed
12706 expression left. If so, it must be the base register
12707 and the constant must be zero. */
12708 if (*s == '(' && strchr (s + 1, '(') == 0)
12710 INSERT_OPERAND (1, IMMG, *ip, 0);
12714 if (my_getSmallExpression (&ep, r, s) > 0
12715 || !expr_const_in_range (&ep, -1, 15, 0))
12718 imm = ep.X_add_number & 15;
12719 INSERT_OPERAND (1, IMMG, *ip, imm);
12726 bfd_reloc_code_real_type r[3];
12730 /* Check whether there is only a single bracketed
12731 expression left. If so, it must be the base register
12732 and the constant must be zero. */
12733 if (*s == '(' && strchr (s + 1, '(') == 0)
12735 INSERT_OPERAND (1, IMMH, *ip, 0);
12739 if (my_getSmallExpression (&ep, r, s) > 0
12740 || !expr_const_in_range (&ep, 0, 16, 1))
12743 imm = ep.X_add_number >> 1;
12744 INSERT_OPERAND (1, IMMH, *ip, imm);
12751 bfd_reloc_code_real_type r[3];
12755 if (my_getSmallExpression (&ep, r, s) > 0
12756 || !expr_const_in_range (&ep, -1, 127, 0))
12759 imm = ep.X_add_number & 127;
12760 INSERT_OPERAND (1, IMMI, *ip, imm);
12767 bfd_reloc_code_real_type r[3];
12771 /* Check whether there is only a single bracketed
12772 expression left. If so, it must be the base register
12773 and the constant must be zero. */
12774 if (*s == '(' && strchr (s + 1, '(') == 0)
12776 INSERT_OPERAND (1, IMMJ, *ip, 0);
12780 if (my_getSmallExpression (&ep, r, s) > 0
12781 || !expr_const_in_range (&ep, 0, 16, 2))
12784 imm = ep.X_add_number >> 2;
12785 INSERT_OPERAND (1, IMMJ, *ip, imm);
12792 bfd_reloc_code_real_type r[3];
12796 /* Check whether there is only a single bracketed
12797 expression left. If so, it must be the base register
12798 and the constant must be zero. */
12799 if (*s == '(' && strchr (s + 1, '(') == 0)
12801 INSERT_OPERAND (1, IMML, *ip, 0);
12805 if (my_getSmallExpression (&ep, r, s) > 0
12806 || !expr_const_in_range (&ep, 0, 16, 0))
12809 imm = ep.X_add_number;
12810 INSERT_OPERAND (1, IMML, *ip, imm);
12817 bfd_reloc_code_real_type r[3];
12821 if (my_getSmallExpression (&ep, r, s) > 0
12822 || !expr_const_in_range (&ep, 1, 9, 0))
12825 imm = ep.X_add_number & 7;
12826 INSERT_OPERAND (1, IMMM, *ip, imm);
12831 case 'N': /* Register list for lwm and swm. */
12833 /* A comma-separated list of registers and/or
12834 dash-separated contiguous ranges including
12835 both ra and a set of one or more registers
12836 starting at s0 up to s3 which have to be
12843 and any permutations of these. */
12844 unsigned int reglist;
12847 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12850 if ((reglist & 0xfff1ffff) != 0x80010000)
12853 reglist = (reglist >> 17) & 7;
12855 if ((reglist & -reglist) != reglist)
12858 imm = ffs (reglist) - 1;
12859 INSERT_OPERAND (1, IMMN, *ip, imm);
12863 case 'O': /* sdbbp 4-bit code. */
12865 bfd_reloc_code_real_type r[3];
12869 if (my_getSmallExpression (&ep, r, s) > 0
12870 || !expr_const_in_range (&ep, 0, 16, 0))
12873 imm = ep.X_add_number;
12874 INSERT_OPERAND (1, IMMO, *ip, imm);
12881 bfd_reloc_code_real_type r[3];
12885 if (my_getSmallExpression (&ep, r, s) > 0
12886 || !expr_const_in_range (&ep, 0, 32, 2))
12889 imm = ep.X_add_number >> 2;
12890 INSERT_OPERAND (1, IMMP, *ip, imm);
12897 bfd_reloc_code_real_type r[3];
12901 if (my_getSmallExpression (&ep, r, s) > 0
12902 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12905 imm = ep.X_add_number >> 2;
12906 INSERT_OPERAND (1, IMMQ, *ip, imm);
12913 bfd_reloc_code_real_type r[3];
12917 /* Check whether there is only a single bracketed
12918 expression left. If so, it must be the base register
12919 and the constant must be zero. */
12920 if (*s == '(' && strchr (s + 1, '(') == 0)
12922 INSERT_OPERAND (1, IMMU, *ip, 0);
12926 if (my_getSmallExpression (&ep, r, s) > 0
12927 || !expr_const_in_range (&ep, 0, 32, 2))
12930 imm = ep.X_add_number >> 2;
12931 INSERT_OPERAND (1, IMMU, *ip, imm);
12938 bfd_reloc_code_real_type r[3];
12942 if (my_getSmallExpression (&ep, r, s) > 0
12943 || !expr_const_in_range (&ep, 0, 64, 2))
12946 imm = ep.X_add_number >> 2;
12947 INSERT_OPERAND (1, IMMW, *ip, imm);
12954 bfd_reloc_code_real_type r[3];
12958 if (my_getSmallExpression (&ep, r, s) > 0
12959 || !expr_const_in_range (&ep, -8, 8, 0))
12962 imm = ep.X_add_number;
12963 INSERT_OPERAND (1, IMMX, *ip, imm);
12970 bfd_reloc_code_real_type r[3];
12974 if (my_getSmallExpression (&ep, r, s) > 0
12975 || expr_const_in_range (&ep, -2, 2, 2)
12976 || !expr_const_in_range (&ep, -258, 258, 2))
12979 imm = ep.X_add_number >> 2;
12980 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
12981 INSERT_OPERAND (1, IMMY, *ip, imm);
12988 bfd_reloc_code_real_type r[3];
12991 if (my_getSmallExpression (&ep, r, s) > 0
12992 || !expr_const_in_range (&ep, 0, 1, 0))
12999 as_bad (_("Internal error: bad microMIPS opcode "
13000 "(unknown extension operand type `m%c'): %s %s"),
13001 *args, insn->name, insn->args);
13002 /* Further processing is fruitless. */
13007 case 'n': /* Register list for 32-bit lwm and swm. */
13008 gas_assert (mips_opts.micromips);
13010 /* A comma-separated list of registers and/or
13011 dash-separated contiguous ranges including
13012 at least one of ra and a set of one or more
13013 registers starting at s0 up to s7 and then
13014 s8 which have to be consecutive, e.g.:
13022 and any permutations of these. */
13023 unsigned int reglist;
13027 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13030 if ((reglist & 0x3f00ffff) != 0)
13033 ra = (reglist >> 27) & 0x10;
13034 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13036 if ((reglist & -reglist) != reglist)
13039 imm = (ffs (reglist) - 1) | ra;
13040 INSERT_OPERAND (1, RT, *ip, imm);
13041 imm_expr.X_op = O_absent;
13045 case '|': /* 4-bit trap code. */
13046 gas_assert (mips_opts.micromips);
13047 my_getExpression (&imm_expr, s);
13048 check_absolute_expr (ip, &imm_expr);
13049 if ((unsigned long) imm_expr.X_add_number
13050 > MICROMIPSOP_MASK_TRAP)
13051 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13052 (unsigned long) imm_expr.X_add_number,
13053 ip->insn_mo->name);
13054 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13055 imm_expr.X_op = O_absent;
13060 as_bad (_("Bad char = '%c'\n"), *args);
13065 /* Args don't match. */
13067 insn_error = _("Illegal operands");
13068 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13073 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13075 gas_assert (firstinsn);
13076 need_delay_slot_ok = FALSE;
13085 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13087 /* This routine assembles an instruction into its binary format when
13088 assembling for the mips16. As a side effect, it sets one of the
13089 global variables imm_reloc or offset_reloc to the type of relocation
13090 to do if one of the operands is an address expression. It also sets
13091 forced_insn_length to the resulting instruction size in bytes if the
13092 user explicitly requested a small or extended instruction. */
13095 mips16_ip (char *str, struct mips_cl_insn *ip)
13099 struct mips_opcode *insn;
13101 unsigned int regno;
13102 unsigned int lastregno = 0;
13108 forced_insn_length = 0;
13110 for (s = str; ISLOWER (*s); ++s)
13122 if (s[1] == 't' && s[2] == ' ')
13125 forced_insn_length = 2;
13129 else if (s[1] == 'e' && s[2] == ' ')
13132 forced_insn_length = 4;
13136 /* Fall through. */
13138 insn_error = _("unknown opcode");
13142 if (mips_opts.noautoextend && !forced_insn_length)
13143 forced_insn_length = 2;
13145 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13147 insn_error = _("unrecognized opcode");
13156 gas_assert (strcmp (insn->name, str) == 0);
13158 ok = is_opcode_valid_16 (insn);
13161 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13162 && strcmp (insn->name, insn[1].name) == 0)
13171 static char buf[100];
13173 _("opcode not supported on this processor: %s (%s)"),
13174 mips_cpu_info_from_arch (mips_opts.arch)->name,
13175 mips_cpu_info_from_isa (mips_opts.isa)->name);
13182 create_insn (ip, insn);
13183 imm_expr.X_op = O_absent;
13184 imm_reloc[0] = BFD_RELOC_UNUSED;
13185 imm_reloc[1] = BFD_RELOC_UNUSED;
13186 imm_reloc[2] = BFD_RELOC_UNUSED;
13187 imm2_expr.X_op = O_absent;
13188 offset_expr.X_op = O_absent;
13189 offset_reloc[0] = BFD_RELOC_UNUSED;
13190 offset_reloc[1] = BFD_RELOC_UNUSED;
13191 offset_reloc[2] = BFD_RELOC_UNUSED;
13192 for (args = insn->args; 1; ++args)
13199 /* In this switch statement we call break if we did not find
13200 a match, continue if we did find a match, or return if we
13209 /* Stuff the immediate value in now, if we can. */
13210 if (imm_expr.X_op == O_constant
13211 && *imm_reloc > BFD_RELOC_UNUSED
13212 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13213 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13214 && insn->pinfo != INSN_MACRO)
13218 switch (*offset_reloc)
13220 case BFD_RELOC_MIPS16_HI16_S:
13221 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13224 case BFD_RELOC_MIPS16_HI16:
13225 tmp = imm_expr.X_add_number >> 16;
13228 case BFD_RELOC_MIPS16_LO16:
13229 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13233 case BFD_RELOC_UNUSED:
13234 tmp = imm_expr.X_add_number;
13240 *offset_reloc = BFD_RELOC_UNUSED;
13242 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13243 tmp, TRUE, forced_insn_length == 2,
13244 forced_insn_length == 4, &ip->insn_opcode,
13245 &ip->use_extend, &ip->extend);
13246 imm_expr.X_op = O_absent;
13247 *imm_reloc = BFD_RELOC_UNUSED;
13261 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13264 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13280 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13282 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13286 /* Fall through. */
13297 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13299 if (c == 'v' || c == 'w')
13302 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13304 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13315 if (c == 'v' || c == 'w')
13317 regno = mips16_to_32_reg_map[lastregno];
13331 regno = mips32_to_16_reg_map[regno];
13336 regno = ILLEGAL_REG;
13341 regno = ILLEGAL_REG;
13346 regno = ILLEGAL_REG;
13351 if (regno == AT && mips_opts.at)
13353 if (mips_opts.at == ATREG)
13354 as_warn (_("used $at without \".set noat\""));
13356 as_warn (_("used $%u with \".set at=$%u\""),
13357 regno, mips_opts.at);
13365 if (regno == ILLEGAL_REG)
13372 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13376 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13379 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13382 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13388 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13391 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13392 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13402 if (strncmp (s, "$pc", 3) == 0)
13419 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13422 if (imm_expr.X_op != O_constant)
13424 forced_insn_length = 4;
13425 ip->use_extend = TRUE;
13430 /* We need to relax this instruction. */
13431 *offset_reloc = *imm_reloc;
13432 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13437 *imm_reloc = BFD_RELOC_UNUSED;
13438 /* Fall through. */
13445 my_getExpression (&imm_expr, s);
13446 if (imm_expr.X_op == O_register)
13448 /* What we thought was an expression turned out to
13451 if (s[0] == '(' && args[1] == '(')
13453 /* It looks like the expression was omitted
13454 before a register indirection, which means
13455 that the expression is implicitly zero. We
13456 still set up imm_expr, so that we handle
13457 explicit extensions correctly. */
13458 imm_expr.X_op = O_constant;
13459 imm_expr.X_add_number = 0;
13460 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13467 /* We need to relax this instruction. */
13468 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13477 /* We use offset_reloc rather than imm_reloc for the PC
13478 relative operands. This lets macros with both
13479 immediate and address operands work correctly. */
13480 my_getExpression (&offset_expr, s);
13482 if (offset_expr.X_op == O_register)
13485 /* We need to relax this instruction. */
13486 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13490 case '6': /* break code */
13491 my_getExpression (&imm_expr, s);
13492 check_absolute_expr (ip, &imm_expr);
13493 if ((unsigned long) imm_expr.X_add_number > 63)
13494 as_warn (_("Invalid value for `%s' (%lu)"),
13496 (unsigned long) imm_expr.X_add_number);
13497 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13498 imm_expr.X_op = O_absent;
13502 case 'a': /* 26 bit address */
13503 my_getExpression (&offset_expr, s);
13505 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13506 ip->insn_opcode <<= 16;
13509 case 'l': /* register list for entry macro */
13510 case 'L': /* register list for exit macro */
13520 unsigned int freg, reg1, reg2;
13522 while (*s == ' ' || *s == ',')
13524 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13526 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13530 as_bad (_("can't parse register list"));
13540 if (!reg_lookup (&s, freg ? RTYPE_FPU
13541 : (RTYPE_GP | RTYPE_NUM), ®2))
13543 as_bad (_("invalid register list"));
13547 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13549 mask &= ~ (7 << 3);
13552 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13554 mask &= ~ (7 << 3);
13557 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13558 mask |= (reg2 - 3) << 3;
13559 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13560 mask |= (reg2 - 15) << 1;
13561 else if (reg1 == RA && reg2 == RA)
13565 as_bad (_("invalid register list"));
13569 /* The mask is filled in in the opcode table for the
13570 benefit of the disassembler. We remove it before
13571 applying the actual mask. */
13572 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13573 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13577 case 'm': /* Register list for save insn. */
13578 case 'M': /* Register list for restore insn. */
13581 int framesz = 0, seen_framesz = 0;
13582 int nargs = 0, statics = 0, sregs = 0;
13586 unsigned int reg1, reg2;
13588 SKIP_SPACE_TABS (s);
13591 SKIP_SPACE_TABS (s);
13593 my_getExpression (&imm_expr, s);
13594 if (imm_expr.X_op == O_constant)
13596 /* Handle the frame size. */
13599 as_bad (_("more than one frame size in list"));
13603 framesz = imm_expr.X_add_number;
13604 imm_expr.X_op = O_absent;
13609 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13611 as_bad (_("can't parse register list"));
13623 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13626 as_bad (_("can't parse register list"));
13631 while (reg1 <= reg2)
13633 if (reg1 >= 4 && reg1 <= 7)
13637 nargs |= 1 << (reg1 - 4);
13639 /* statics $a0-$a3 */
13640 statics |= 1 << (reg1 - 4);
13642 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13645 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13647 else if (reg1 == 31)
13649 /* Add $ra to insn. */
13654 as_bad (_("unexpected register in list"));
13662 /* Encode args/statics combination. */
13663 if (nargs & statics)
13664 as_bad (_("arg/static registers overlap"));
13665 else if (nargs == 0xf)
13666 /* All $a0-$a3 are args. */
13667 opcode |= MIPS16_ALL_ARGS << 16;
13668 else if (statics == 0xf)
13669 /* All $a0-$a3 are statics. */
13670 opcode |= MIPS16_ALL_STATICS << 16;
13673 int narg = 0, nstat = 0;
13675 /* Count arg registers. */
13676 while (nargs & 0x1)
13682 as_bad (_("invalid arg register list"));
13684 /* Count static registers. */
13685 while (statics & 0x8)
13687 statics = (statics << 1) & 0xf;
13691 as_bad (_("invalid static register list"));
13693 /* Encode args/statics. */
13694 opcode |= ((narg << 2) | nstat) << 16;
13697 /* Encode $s0/$s1. */
13698 if (sregs & (1 << 0)) /* $s0 */
13700 if (sregs & (1 << 1)) /* $s1 */
13706 /* Count regs $s2-$s8. */
13714 as_bad (_("invalid static register list"));
13715 /* Encode $s2-$s8. */
13716 opcode |= nsreg << 24;
13719 /* Encode frame size. */
13721 as_bad (_("missing frame size"));
13722 else if ((framesz & 7) != 0 || framesz < 0
13723 || framesz > 0xff * 8)
13724 as_bad (_("invalid frame size"));
13725 else if (framesz != 128 || (opcode >> 16) != 0)
13728 opcode |= (((framesz & 0xf0) << 16)
13729 | (framesz & 0x0f));
13732 /* Finally build the instruction. */
13733 if ((opcode >> 16) != 0 || framesz == 0)
13735 ip->use_extend = TRUE;
13736 ip->extend = opcode >> 16;
13738 ip->insn_opcode |= opcode & 0x7f;
13742 case 'e': /* extend code */
13743 my_getExpression (&imm_expr, s);
13744 check_absolute_expr (ip, &imm_expr);
13745 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13747 as_warn (_("Invalid value for `%s' (%lu)"),
13749 (unsigned long) imm_expr.X_add_number);
13750 imm_expr.X_add_number &= 0x7ff;
13752 ip->insn_opcode |= imm_expr.X_add_number;
13753 imm_expr.X_op = O_absent;
13763 /* Args don't match. */
13764 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13765 strcmp (insn->name, insn[1].name) == 0)
13772 insn_error = _("illegal operands");
13778 /* This structure holds information we know about a mips16 immediate
13781 struct mips16_immed_operand
13783 /* The type code used in the argument string in the opcode table. */
13785 /* The number of bits in the short form of the opcode. */
13787 /* The number of bits in the extended form of the opcode. */
13789 /* The amount by which the short form is shifted when it is used;
13790 for example, the sw instruction has a shift count of 2. */
13792 /* The amount by which the short form is shifted when it is stored
13793 into the instruction code. */
13795 /* Non-zero if the short form is unsigned. */
13797 /* Non-zero if the extended form is unsigned. */
13799 /* Non-zero if the value is PC relative. */
13803 /* The mips16 immediate operand types. */
13805 static const struct mips16_immed_operand mips16_immed_operands[] =
13807 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13808 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13809 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13810 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13811 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13812 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13813 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13814 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13815 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13816 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13817 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13818 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13819 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13820 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13821 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13822 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13823 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13824 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13825 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13826 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13827 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13830 #define MIPS16_NUM_IMMED \
13831 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13833 /* Handle a mips16 instruction with an immediate value. This or's the
13834 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13835 whether an extended value is needed; if one is needed, it sets
13836 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13837 If SMALL is true, an unextended opcode was explicitly requested.
13838 If EXT is true, an extended opcode was explicitly requested. If
13839 WARN is true, warn if EXT does not match reality. */
13842 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13843 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13844 unsigned long *insn, bfd_boolean *use_extend,
13845 unsigned short *extend)
13847 const struct mips16_immed_operand *op;
13848 int mintiny, maxtiny;
13849 bfd_boolean needext;
13851 op = mips16_immed_operands;
13852 while (op->type != type)
13855 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13860 if (type == '<' || type == '>' || type == '[' || type == ']')
13863 maxtiny = 1 << op->nbits;
13868 maxtiny = (1 << op->nbits) - 1;
13873 mintiny = - (1 << (op->nbits - 1));
13874 maxtiny = (1 << (op->nbits - 1)) - 1;
13877 /* Branch offsets have an implicit 0 in the lowest bit. */
13878 if (type == 'p' || type == 'q')
13881 if ((val & ((1 << op->shift) - 1)) != 0
13882 || val < (mintiny << op->shift)
13883 || val > (maxtiny << op->shift))
13888 if (warn && ext && ! needext)
13889 as_warn_where (file, line,
13890 _("extended operand requested but not required"));
13891 if (small && needext)
13892 as_bad_where (file, line, _("invalid unextended operand value"));
13894 if (small || (! ext && ! needext))
13898 *use_extend = FALSE;
13899 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13900 insnval <<= op->op_shift;
13905 long minext, maxext;
13911 maxext = (1 << op->extbits) - 1;
13915 minext = - (1 << (op->extbits - 1));
13916 maxext = (1 << (op->extbits - 1)) - 1;
13918 if (val < minext || val > maxext)
13919 as_bad_where (file, line,
13920 _("operand value out of range for instruction"));
13922 *use_extend = TRUE;
13923 if (op->extbits == 16)
13925 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13928 else if (op->extbits == 15)
13930 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13935 extval = ((val & 0x1f) << 6) | (val & 0x20);
13939 *extend = (unsigned short) extval;
13944 struct percent_op_match
13947 bfd_reloc_code_real_type reloc;
13950 static const struct percent_op_match mips_percent_op[] =
13952 {"%lo", BFD_RELOC_LO16},
13954 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13955 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13956 {"%call16", BFD_RELOC_MIPS_CALL16},
13957 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13958 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13959 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13960 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13961 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13962 {"%got", BFD_RELOC_MIPS_GOT16},
13963 {"%gp_rel", BFD_RELOC_GPREL16},
13964 {"%half", BFD_RELOC_16},
13965 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13966 {"%higher", BFD_RELOC_MIPS_HIGHER},
13967 {"%neg", BFD_RELOC_MIPS_SUB},
13968 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13969 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13970 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13971 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13972 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13973 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13974 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13976 {"%hi", BFD_RELOC_HI16_S}
13979 static const struct percent_op_match mips16_percent_op[] =
13981 {"%lo", BFD_RELOC_MIPS16_LO16},
13982 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13983 {"%got", BFD_RELOC_MIPS16_GOT16},
13984 {"%call16", BFD_RELOC_MIPS16_CALL16},
13985 {"%hi", BFD_RELOC_MIPS16_HI16_S}
13989 /* Return true if *STR points to a relocation operator. When returning true,
13990 move *STR over the operator and store its relocation code in *RELOC.
13991 Leave both *STR and *RELOC alone when returning false. */
13994 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13996 const struct percent_op_match *percent_op;
13999 if (mips_opts.mips16)
14001 percent_op = mips16_percent_op;
14002 limit = ARRAY_SIZE (mips16_percent_op);
14006 percent_op = mips_percent_op;
14007 limit = ARRAY_SIZE (mips_percent_op);
14010 for (i = 0; i < limit; i++)
14011 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14013 int len = strlen (percent_op[i].str);
14015 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14018 *str += strlen (percent_op[i].str);
14019 *reloc = percent_op[i].reloc;
14021 /* Check whether the output BFD supports this relocation.
14022 If not, issue an error and fall back on something safe. */
14023 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14025 as_bad (_("relocation %s isn't supported by the current ABI"),
14026 percent_op[i].str);
14027 *reloc = BFD_RELOC_UNUSED;
14035 /* Parse string STR as a 16-bit relocatable operand. Store the
14036 expression in *EP and the relocations in the array starting
14037 at RELOC. Return the number of relocation operators used.
14039 On exit, EXPR_END points to the first character after the expression. */
14042 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14045 bfd_reloc_code_real_type reversed_reloc[3];
14046 size_t reloc_index, i;
14047 int crux_depth, str_depth;
14050 /* Search for the start of the main expression, recoding relocations
14051 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14052 of the main expression and with CRUX_DEPTH containing the number
14053 of open brackets at that point. */
14060 crux_depth = str_depth;
14062 /* Skip over whitespace and brackets, keeping count of the number
14064 while (*str == ' ' || *str == '\t' || *str == '(')
14069 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14070 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14072 my_getExpression (ep, crux);
14075 /* Match every open bracket. */
14076 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14080 if (crux_depth > 0)
14081 as_bad (_("unclosed '('"));
14085 if (reloc_index != 0)
14087 prev_reloc_op_frag = frag_now;
14088 for (i = 0; i < reloc_index; i++)
14089 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14092 return reloc_index;
14096 my_getExpression (expressionS *ep, char *str)
14100 save_in = input_line_pointer;
14101 input_line_pointer = str;
14103 expr_end = input_line_pointer;
14104 input_line_pointer = save_in;
14108 md_atof (int type, char *litP, int *sizeP)
14110 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14114 md_number_to_chars (char *buf, valueT val, int n)
14116 if (target_big_endian)
14117 number_to_chars_bigendian (buf, val, n);
14119 number_to_chars_littleendian (buf, val, n);
14123 static int support_64bit_objects(void)
14125 const char **list, **l;
14128 list = bfd_target_list ();
14129 for (l = list; *l != NULL; l++)
14130 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14131 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14133 yes = (*l != NULL);
14137 #endif /* OBJ_ELF */
14139 const char *md_shortopts = "O::g::G:";
14143 OPTION_MARCH = OPTION_MD_BASE,
14165 OPTION_NO_SMARTMIPS,
14169 OPTION_NO_MICROMIPS,
14170 OPTION_COMPAT_ARCH_BASE,
14179 OPTION_M7000_HILO_FIX,
14180 OPTION_MNO_7000_HILO_FIX,
14183 OPTION_FIX_LOONGSON2F_JUMP,
14184 OPTION_NO_FIX_LOONGSON2F_JUMP,
14185 OPTION_FIX_LOONGSON2F_NOP,
14186 OPTION_NO_FIX_LOONGSON2F_NOP,
14188 OPTION_NO_FIX_VR4120,
14190 OPTION_NO_FIX_VR4130,
14191 OPTION_FIX_CN63XXP1,
14192 OPTION_NO_FIX_CN63XXP1,
14199 OPTION_CONSTRUCT_FLOATS,
14200 OPTION_NO_CONSTRUCT_FLOATS,
14203 OPTION_RELAX_BRANCH,
14204 OPTION_NO_RELAX_BRANCH,
14211 OPTION_SINGLE_FLOAT,
14212 OPTION_DOUBLE_FLOAT,
14215 OPTION_CALL_SHARED,
14216 OPTION_CALL_NONPIC,
14226 OPTION_MVXWORKS_PIC,
14227 #endif /* OBJ_ELF */
14231 struct option md_longopts[] =
14233 /* Options which specify architecture. */
14234 {"march", required_argument, NULL, OPTION_MARCH},
14235 {"mtune", required_argument, NULL, OPTION_MTUNE},
14236 {"mips0", no_argument, NULL, OPTION_MIPS1},
14237 {"mips1", no_argument, NULL, OPTION_MIPS1},
14238 {"mips2", no_argument, NULL, OPTION_MIPS2},
14239 {"mips3", no_argument, NULL, OPTION_MIPS3},
14240 {"mips4", no_argument, NULL, OPTION_MIPS4},
14241 {"mips5", no_argument, NULL, OPTION_MIPS5},
14242 {"mips32", no_argument, NULL, OPTION_MIPS32},
14243 {"mips64", no_argument, NULL, OPTION_MIPS64},
14244 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14245 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14247 /* Options which specify Application Specific Extensions (ASEs). */
14248 {"mips16", no_argument, NULL, OPTION_MIPS16},
14249 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14250 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14251 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14252 {"mdmx", no_argument, NULL, OPTION_MDMX},
14253 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14254 {"mdsp", no_argument, NULL, OPTION_DSP},
14255 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14256 {"mmt", no_argument, NULL, OPTION_MT},
14257 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14258 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14259 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14260 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14261 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14262 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14263 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14265 /* Old-style architecture options. Don't add more of these. */
14266 {"m4650", no_argument, NULL, OPTION_M4650},
14267 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14268 {"m4010", no_argument, NULL, OPTION_M4010},
14269 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14270 {"m4100", no_argument, NULL, OPTION_M4100},
14271 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14272 {"m3900", no_argument, NULL, OPTION_M3900},
14273 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14275 /* Options which enable bug fixes. */
14276 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14277 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14278 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14279 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14280 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14281 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14282 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14283 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14284 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14285 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14286 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14287 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14288 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14289 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14290 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14292 /* Miscellaneous options. */
14293 {"trap", no_argument, NULL, OPTION_TRAP},
14294 {"no-break", no_argument, NULL, OPTION_TRAP},
14295 {"break", no_argument, NULL, OPTION_BREAK},
14296 {"no-trap", no_argument, NULL, OPTION_BREAK},
14297 {"EB", no_argument, NULL, OPTION_EB},
14298 {"EL", no_argument, NULL, OPTION_EL},
14299 {"mfp32", no_argument, NULL, OPTION_FP32},
14300 {"mgp32", no_argument, NULL, OPTION_GP32},
14301 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14302 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14303 {"mfp64", no_argument, NULL, OPTION_FP64},
14304 {"mgp64", no_argument, NULL, OPTION_GP64},
14305 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14306 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14307 {"mshared", no_argument, NULL, OPTION_MSHARED},
14308 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14309 {"msym32", no_argument, NULL, OPTION_MSYM32},
14310 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14311 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14312 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14313 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14314 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14316 /* Strictly speaking this next option is ELF specific,
14317 but we allow it for other ports as well in order to
14318 make testing easier. */
14319 {"32", no_argument, NULL, OPTION_32},
14321 /* ELF-specific options. */
14323 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14324 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14325 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14326 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14327 {"xgot", no_argument, NULL, OPTION_XGOT},
14328 {"mabi", required_argument, NULL, OPTION_MABI},
14329 {"n32", no_argument, NULL, OPTION_N32},
14330 {"64", no_argument, NULL, OPTION_64},
14331 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14332 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14333 {"mpdr", no_argument, NULL, OPTION_PDR},
14334 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14335 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14336 #endif /* OBJ_ELF */
14338 {NULL, no_argument, NULL, 0}
14340 size_t md_longopts_size = sizeof (md_longopts);
14342 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14343 NEW_VALUE. Warn if another value was already specified. Note:
14344 we have to defer parsing the -march and -mtune arguments in order
14345 to handle 'from-abi' correctly, since the ABI might be specified
14346 in a later argument. */
14349 mips_set_option_string (const char **string_ptr, const char *new_value)
14351 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14352 as_warn (_("A different %s was already specified, is now %s"),
14353 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14356 *string_ptr = new_value;
14360 md_parse_option (int c, char *arg)
14364 case OPTION_CONSTRUCT_FLOATS:
14365 mips_disable_float_construction = 0;
14368 case OPTION_NO_CONSTRUCT_FLOATS:
14369 mips_disable_float_construction = 1;
14381 target_big_endian = 1;
14385 target_big_endian = 0;
14391 else if (arg[0] == '0')
14393 else if (arg[0] == '1')
14403 mips_debug = atoi (arg);
14407 file_mips_isa = ISA_MIPS1;
14411 file_mips_isa = ISA_MIPS2;
14415 file_mips_isa = ISA_MIPS3;
14419 file_mips_isa = ISA_MIPS4;
14423 file_mips_isa = ISA_MIPS5;
14426 case OPTION_MIPS32:
14427 file_mips_isa = ISA_MIPS32;
14430 case OPTION_MIPS32R2:
14431 file_mips_isa = ISA_MIPS32R2;
14434 case OPTION_MIPS64R2:
14435 file_mips_isa = ISA_MIPS64R2;
14438 case OPTION_MIPS64:
14439 file_mips_isa = ISA_MIPS64;
14443 mips_set_option_string (&mips_tune_string, arg);
14447 mips_set_option_string (&mips_arch_string, arg);
14451 mips_set_option_string (&mips_arch_string, "4650");
14452 mips_set_option_string (&mips_tune_string, "4650");
14455 case OPTION_NO_M4650:
14459 mips_set_option_string (&mips_arch_string, "4010");
14460 mips_set_option_string (&mips_tune_string, "4010");
14463 case OPTION_NO_M4010:
14467 mips_set_option_string (&mips_arch_string, "4100");
14468 mips_set_option_string (&mips_tune_string, "4100");
14471 case OPTION_NO_M4100:
14475 mips_set_option_string (&mips_arch_string, "3900");
14476 mips_set_option_string (&mips_tune_string, "3900");
14479 case OPTION_NO_M3900:
14483 mips_opts.ase_mdmx = 1;
14486 case OPTION_NO_MDMX:
14487 mips_opts.ase_mdmx = 0;
14491 mips_opts.ase_dsp = 1;
14492 mips_opts.ase_dspr2 = 0;
14495 case OPTION_NO_DSP:
14496 mips_opts.ase_dsp = 0;
14497 mips_opts.ase_dspr2 = 0;
14501 mips_opts.ase_dspr2 = 1;
14502 mips_opts.ase_dsp = 1;
14505 case OPTION_NO_DSPR2:
14506 mips_opts.ase_dspr2 = 0;
14507 mips_opts.ase_dsp = 0;
14511 mips_opts.ase_mt = 1;
14515 mips_opts.ase_mt = 0;
14518 case OPTION_MICROMIPS:
14519 if (mips_opts.mips16 == 1)
14521 as_bad (_("-mmicromips cannot be used with -mips16"));
14524 mips_opts.micromips = 1;
14525 mips_no_prev_insn ();
14528 case OPTION_NO_MICROMIPS:
14529 mips_opts.micromips = 0;
14530 mips_no_prev_insn ();
14533 case OPTION_MIPS16:
14534 if (mips_opts.micromips == 1)
14536 as_bad (_("-mips16 cannot be used with -micromips"));
14539 mips_opts.mips16 = 1;
14540 mips_no_prev_insn ();
14543 case OPTION_NO_MIPS16:
14544 mips_opts.mips16 = 0;
14545 mips_no_prev_insn ();
14548 case OPTION_MIPS3D:
14549 mips_opts.ase_mips3d = 1;
14552 case OPTION_NO_MIPS3D:
14553 mips_opts.ase_mips3d = 0;
14556 case OPTION_SMARTMIPS:
14557 mips_opts.ase_smartmips = 1;
14560 case OPTION_NO_SMARTMIPS:
14561 mips_opts.ase_smartmips = 0;
14564 case OPTION_FIX_24K:
14568 case OPTION_NO_FIX_24K:
14572 case OPTION_FIX_LOONGSON2F_JUMP:
14573 mips_fix_loongson2f_jump = TRUE;
14576 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14577 mips_fix_loongson2f_jump = FALSE;
14580 case OPTION_FIX_LOONGSON2F_NOP:
14581 mips_fix_loongson2f_nop = TRUE;
14584 case OPTION_NO_FIX_LOONGSON2F_NOP:
14585 mips_fix_loongson2f_nop = FALSE;
14588 case OPTION_FIX_VR4120:
14589 mips_fix_vr4120 = 1;
14592 case OPTION_NO_FIX_VR4120:
14593 mips_fix_vr4120 = 0;
14596 case OPTION_FIX_VR4130:
14597 mips_fix_vr4130 = 1;
14600 case OPTION_NO_FIX_VR4130:
14601 mips_fix_vr4130 = 0;
14604 case OPTION_FIX_CN63XXP1:
14605 mips_fix_cn63xxp1 = TRUE;
14608 case OPTION_NO_FIX_CN63XXP1:
14609 mips_fix_cn63xxp1 = FALSE;
14612 case OPTION_RELAX_BRANCH:
14613 mips_relax_branch = 1;
14616 case OPTION_NO_RELAX_BRANCH:
14617 mips_relax_branch = 0;
14620 case OPTION_MSHARED:
14621 mips_in_shared = TRUE;
14624 case OPTION_MNO_SHARED:
14625 mips_in_shared = FALSE;
14628 case OPTION_MSYM32:
14629 mips_opts.sym32 = TRUE;
14632 case OPTION_MNO_SYM32:
14633 mips_opts.sym32 = FALSE;
14637 /* When generating ELF code, we permit -KPIC and -call_shared to
14638 select SVR4_PIC, and -non_shared to select no PIC. This is
14639 intended to be compatible with Irix 5. */
14640 case OPTION_CALL_SHARED:
14643 as_bad (_("-call_shared is supported only for ELF format"));
14646 mips_pic = SVR4_PIC;
14647 mips_abicalls = TRUE;
14650 case OPTION_CALL_NONPIC:
14653 as_bad (_("-call_nonpic is supported only for ELF format"));
14657 mips_abicalls = TRUE;
14660 case OPTION_NON_SHARED:
14663 as_bad (_("-non_shared is supported only for ELF format"));
14667 mips_abicalls = FALSE;
14670 /* The -xgot option tells the assembler to use 32 bit offsets
14671 when accessing the got in SVR4_PIC mode. It is for Irix
14676 #endif /* OBJ_ELF */
14679 g_switch_value = atoi (arg);
14683 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14687 mips_abi = O32_ABI;
14688 /* We silently ignore -32 for non-ELF targets. This greatly
14689 simplifies the construction of the MIPS GAS test cases. */
14696 as_bad (_("-n32 is supported for ELF format only"));
14699 mips_abi = N32_ABI;
14705 as_bad (_("-64 is supported for ELF format only"));
14708 mips_abi = N64_ABI;
14709 if (!support_64bit_objects())
14710 as_fatal (_("No compiled in support for 64 bit object file format"));
14712 #endif /* OBJ_ELF */
14715 file_mips_gp32 = 1;
14719 file_mips_gp32 = 0;
14723 file_mips_fp32 = 1;
14727 file_mips_fp32 = 0;
14730 case OPTION_SINGLE_FLOAT:
14731 file_mips_single_float = 1;
14734 case OPTION_DOUBLE_FLOAT:
14735 file_mips_single_float = 0;
14738 case OPTION_SOFT_FLOAT:
14739 file_mips_soft_float = 1;
14742 case OPTION_HARD_FLOAT:
14743 file_mips_soft_float = 0;
14750 as_bad (_("-mabi is supported for ELF format only"));
14753 if (strcmp (arg, "32") == 0)
14754 mips_abi = O32_ABI;
14755 else if (strcmp (arg, "o64") == 0)
14756 mips_abi = O64_ABI;
14757 else if (strcmp (arg, "n32") == 0)
14758 mips_abi = N32_ABI;
14759 else if (strcmp (arg, "64") == 0)
14761 mips_abi = N64_ABI;
14762 if (! support_64bit_objects())
14763 as_fatal (_("No compiled in support for 64 bit object file "
14766 else if (strcmp (arg, "eabi") == 0)
14767 mips_abi = EABI_ABI;
14770 as_fatal (_("invalid abi -mabi=%s"), arg);
14774 #endif /* OBJ_ELF */
14776 case OPTION_M7000_HILO_FIX:
14777 mips_7000_hilo_fix = TRUE;
14780 case OPTION_MNO_7000_HILO_FIX:
14781 mips_7000_hilo_fix = FALSE;
14785 case OPTION_MDEBUG:
14786 mips_flag_mdebug = TRUE;
14789 case OPTION_NO_MDEBUG:
14790 mips_flag_mdebug = FALSE;
14794 mips_flag_pdr = TRUE;
14797 case OPTION_NO_PDR:
14798 mips_flag_pdr = FALSE;
14801 case OPTION_MVXWORKS_PIC:
14802 mips_pic = VXWORKS_PIC;
14804 #endif /* OBJ_ELF */
14810 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14815 /* Set up globals to generate code for the ISA or processor
14816 described by INFO. */
14819 mips_set_architecture (const struct mips_cpu_info *info)
14823 file_mips_arch = info->cpu;
14824 mips_opts.arch = info->cpu;
14825 mips_opts.isa = info->isa;
14830 /* Likewise for tuning. */
14833 mips_set_tune (const struct mips_cpu_info *info)
14836 mips_tune = info->cpu;
14841 mips_after_parse_args (void)
14843 const struct mips_cpu_info *arch_info = 0;
14844 const struct mips_cpu_info *tune_info = 0;
14846 /* GP relative stuff not working for PE */
14847 if (strncmp (TARGET_OS, "pe", 2) == 0)
14849 if (g_switch_seen && g_switch_value != 0)
14850 as_bad (_("-G not supported in this configuration."));
14851 g_switch_value = 0;
14854 if (mips_abi == NO_ABI)
14855 mips_abi = MIPS_DEFAULT_ABI;
14857 /* The following code determines the architecture and register size.
14858 Similar code was added to GCC 3.3 (see override_options() in
14859 config/mips/mips.c). The GAS and GCC code should be kept in sync
14860 as much as possible. */
14862 if (mips_arch_string != 0)
14863 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14865 if (file_mips_isa != ISA_UNKNOWN)
14867 /* Handle -mipsN. At this point, file_mips_isa contains the
14868 ISA level specified by -mipsN, while arch_info->isa contains
14869 the -march selection (if any). */
14870 if (arch_info != 0)
14872 /* -march takes precedence over -mipsN, since it is more descriptive.
14873 There's no harm in specifying both as long as the ISA levels
14875 if (file_mips_isa != arch_info->isa)
14876 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14877 mips_cpu_info_from_isa (file_mips_isa)->name,
14878 mips_cpu_info_from_isa (arch_info->isa)->name);
14881 arch_info = mips_cpu_info_from_isa (file_mips_isa);
14884 if (arch_info == 0)
14885 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14887 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14888 as_bad (_("-march=%s is not compatible with the selected ABI"),
14891 mips_set_architecture (arch_info);
14893 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14894 if (mips_tune_string != 0)
14895 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14897 if (tune_info == 0)
14898 mips_set_tune (arch_info);
14900 mips_set_tune (tune_info);
14902 if (file_mips_gp32 >= 0)
14904 /* The user specified the size of the integer registers. Make sure
14905 it agrees with the ABI and ISA. */
14906 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14907 as_bad (_("-mgp64 used with a 32-bit processor"));
14908 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14909 as_bad (_("-mgp32 used with a 64-bit ABI"));
14910 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14911 as_bad (_("-mgp64 used with a 32-bit ABI"));
14915 /* Infer the integer register size from the ABI and processor.
14916 Restrict ourselves to 32-bit registers if that's all the
14917 processor has, or if the ABI cannot handle 64-bit registers. */
14918 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14919 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14922 switch (file_mips_fp32)
14926 /* No user specified float register size.
14927 ??? GAS treats single-float processors as though they had 64-bit
14928 float registers (although it complains when double-precision
14929 instructions are used). As things stand, saying they have 32-bit
14930 registers would lead to spurious "register must be even" messages.
14931 So here we assume float registers are never smaller than the
14933 if (file_mips_gp32 == 0)
14934 /* 64-bit integer registers implies 64-bit float registers. */
14935 file_mips_fp32 = 0;
14936 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
14937 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14938 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14939 file_mips_fp32 = 0;
14941 /* 32-bit float registers. */
14942 file_mips_fp32 = 1;
14945 /* The user specified the size of the float registers. Check if it
14946 agrees with the ABI and ISA. */
14948 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14949 as_bad (_("-mfp64 used with a 32-bit fpu"));
14950 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14951 && !ISA_HAS_MXHC1 (mips_opts.isa))
14952 as_warn (_("-mfp64 used with a 32-bit ABI"));
14955 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14956 as_warn (_("-mfp32 used with a 64-bit ABI"));
14960 /* End of GCC-shared inference code. */
14962 /* This flag is set when we have a 64-bit capable CPU but use only
14963 32-bit wide registers. Note that EABI does not use it. */
14964 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14965 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14966 || mips_abi == O32_ABI))
14967 mips_32bitmode = 1;
14969 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14970 as_bad (_("trap exception not supported at ISA 1"));
14972 /* If the selected architecture includes support for ASEs, enable
14973 generation of code for them. */
14974 if (mips_opts.mips16 == -1)
14975 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
14976 if (mips_opts.micromips == -1)
14977 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
14978 if (mips_opts.ase_mips3d == -1)
14979 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
14980 && file_mips_fp32 == 0) ? 1 : 0;
14981 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
14982 as_bad (_("-mfp32 used with -mips3d"));
14984 if (mips_opts.ase_mdmx == -1)
14985 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
14986 && file_mips_fp32 == 0) ? 1 : 0;
14987 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
14988 as_bad (_("-mfp32 used with -mdmx"));
14990 if (mips_opts.ase_smartmips == -1)
14991 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
14992 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
14993 as_warn (_("%s ISA does not support SmartMIPS"),
14994 mips_cpu_info_from_isa (mips_opts.isa)->name);
14996 if (mips_opts.ase_dsp == -1)
14997 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
14998 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
14999 as_warn (_("%s ISA does not support DSP ASE"),
15000 mips_cpu_info_from_isa (mips_opts.isa)->name);
15002 if (mips_opts.ase_dspr2 == -1)
15004 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15005 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15007 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15008 as_warn (_("%s ISA does not support DSP R2 ASE"),
15009 mips_cpu_info_from_isa (mips_opts.isa)->name);
15011 if (mips_opts.ase_mt == -1)
15012 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15013 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15014 as_warn (_("%s ISA does not support MT ASE"),
15015 mips_cpu_info_from_isa (mips_opts.isa)->name);
15017 file_mips_isa = mips_opts.isa;
15018 file_ase_mips3d = mips_opts.ase_mips3d;
15019 file_ase_mdmx = mips_opts.ase_mdmx;
15020 file_ase_smartmips = mips_opts.ase_smartmips;
15021 file_ase_dsp = mips_opts.ase_dsp;
15022 file_ase_dspr2 = mips_opts.ase_dspr2;
15023 file_ase_mt = mips_opts.ase_mt;
15024 mips_opts.gp32 = file_mips_gp32;
15025 mips_opts.fp32 = file_mips_fp32;
15026 mips_opts.soft_float = file_mips_soft_float;
15027 mips_opts.single_float = file_mips_single_float;
15029 if (mips_flag_mdebug < 0)
15031 #ifdef OBJ_MAYBE_ECOFF
15032 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15033 mips_flag_mdebug = 1;
15035 #endif /* OBJ_MAYBE_ECOFF */
15036 mips_flag_mdebug = 0;
15041 mips_init_after_args (void)
15043 /* initialize opcodes */
15044 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15045 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15049 md_pcrel_from (fixS *fixP)
15051 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15052 switch (fixP->fx_r_type)
15054 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15055 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15056 /* Return the address of the delay slot. */
15059 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15060 case BFD_RELOC_MICROMIPS_JMP:
15061 case BFD_RELOC_16_PCREL_S2:
15062 case BFD_RELOC_MIPS_JMP:
15063 /* Return the address of the delay slot. */
15067 /* We have no relocation type for PC relative MIPS16 instructions. */
15068 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15069 as_bad_where (fixP->fx_file, fixP->fx_line,
15070 _("PC relative MIPS16 instruction references a different section"));
15075 /* This is called before the symbol table is processed. In order to
15076 work with gcc when using mips-tfile, we must keep all local labels.
15077 However, in other cases, we want to discard them. If we were
15078 called with -g, but we didn't see any debugging information, it may
15079 mean that gcc is smuggling debugging information through to
15080 mips-tfile, in which case we must generate all local labels. */
15083 mips_frob_file_before_adjust (void)
15085 #ifndef NO_ECOFF_DEBUGGING
15086 if (ECOFF_DEBUGGING
15088 && ! ecoff_debugging_seen)
15089 flag_keep_locals = 1;
15093 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15094 the corresponding LO16 reloc. This is called before md_apply_fix and
15095 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15096 relocation operators.
15098 For our purposes, a %lo() expression matches a %got() or %hi()
15101 (a) it refers to the same symbol; and
15102 (b) the offset applied in the %lo() expression is no lower than
15103 the offset applied in the %got() or %hi().
15105 (b) allows us to cope with code like:
15108 lh $4,%lo(foo+2)($4)
15110 ...which is legal on RELA targets, and has a well-defined behaviour
15111 if the user knows that adding 2 to "foo" will not induce a carry to
15114 When several %lo()s match a particular %got() or %hi(), we use the
15115 following rules to distinguish them:
15117 (1) %lo()s with smaller offsets are a better match than %lo()s with
15120 (2) %lo()s with no matching %got() or %hi() are better than those
15121 that already have a matching %got() or %hi().
15123 (3) later %lo()s are better than earlier %lo()s.
15125 These rules are applied in order.
15127 (1) means, among other things, that %lo()s with identical offsets are
15128 chosen if they exist.
15130 (2) means that we won't associate several high-part relocations with
15131 the same low-part relocation unless there's no alternative. Having
15132 several high parts for the same low part is a GNU extension; this rule
15133 allows careful users to avoid it.
15135 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15136 with the last high-part relocation being at the front of the list.
15137 It therefore makes sense to choose the last matching low-part
15138 relocation, all other things being equal. It's also easier
15139 to code that way. */
15142 mips_frob_file (void)
15144 struct mips_hi_fixup *l;
15145 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15147 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15149 segment_info_type *seginfo;
15150 bfd_boolean matched_lo_p;
15151 fixS **hi_pos, **lo_pos, **pos;
15153 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15155 /* If a GOT16 relocation turns out to be against a global symbol,
15156 there isn't supposed to be a matching LO. */
15157 if (got16_reloc_p (l->fixp->fx_r_type)
15158 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15161 /* Check quickly whether the next fixup happens to be a matching %lo. */
15162 if (fixup_has_matching_lo_p (l->fixp))
15165 seginfo = seg_info (l->seg);
15167 /* Set HI_POS to the position of this relocation in the chain.
15168 Set LO_POS to the position of the chosen low-part relocation.
15169 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15170 relocation that matches an immediately-preceding high-part
15174 matched_lo_p = FALSE;
15175 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15177 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15179 if (*pos == l->fixp)
15182 if ((*pos)->fx_r_type == looking_for_rtype
15183 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15184 && (*pos)->fx_offset >= l->fixp->fx_offset
15186 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15188 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15191 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15192 && fixup_has_matching_lo_p (*pos));
15195 /* If we found a match, remove the high-part relocation from its
15196 current position and insert it before the low-part relocation.
15197 Make the offsets match so that fixup_has_matching_lo_p()
15200 We don't warn about unmatched high-part relocations since some
15201 versions of gcc have been known to emit dead "lui ...%hi(...)"
15203 if (lo_pos != NULL)
15205 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15206 if (l->fixp->fx_next != *lo_pos)
15208 *hi_pos = l->fixp->fx_next;
15209 l->fixp->fx_next = *lo_pos;
15216 /* We may have combined relocations without symbols in the N32/N64 ABI.
15217 We have to prevent gas from dropping them. */
15220 mips_force_relocation (fixS *fixp)
15222 if (generic_force_reloc (fixp))
15225 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15226 so that the linker relaxation can update targets. */
15227 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15228 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15229 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15233 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15234 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15235 || hi16_reloc_p (fixp->fx_r_type)
15236 || lo16_reloc_p (fixp->fx_r_type)))
15242 /* Apply a fixup to the object file. */
15245 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15249 reloc_howto_type *howto;
15251 /* We ignore generic BFD relocations we don't know about. */
15252 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15256 gas_assert (fixP->fx_size == 2
15257 || fixP->fx_size == 4
15258 || fixP->fx_r_type == BFD_RELOC_16
15259 || fixP->fx_r_type == BFD_RELOC_64
15260 || fixP->fx_r_type == BFD_RELOC_CTOR
15261 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15262 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15263 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15264 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15265 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15267 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15269 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15270 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15271 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15272 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15274 /* Don't treat parts of a composite relocation as done. There are two
15277 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15278 should nevertheless be emitted if the first part is.
15280 (2) In normal usage, composite relocations are never assembly-time
15281 constants. The easiest way of dealing with the pathological
15282 exceptions is to generate a relocation against STN_UNDEF and
15283 leave everything up to the linker. */
15284 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15287 switch (fixP->fx_r_type)
15289 case BFD_RELOC_MIPS_TLS_GD:
15290 case BFD_RELOC_MIPS_TLS_LDM:
15291 case BFD_RELOC_MIPS_TLS_DTPREL32:
15292 case BFD_RELOC_MIPS_TLS_DTPREL64:
15293 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15294 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15295 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15296 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15297 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15298 case BFD_RELOC_MICROMIPS_TLS_GD:
15299 case BFD_RELOC_MICROMIPS_TLS_LDM:
15300 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15301 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15302 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15303 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15304 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15305 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15308 case BFD_RELOC_MIPS_JMP:
15309 case BFD_RELOC_MIPS_SHIFT5:
15310 case BFD_RELOC_MIPS_SHIFT6:
15311 case BFD_RELOC_MIPS_GOT_DISP:
15312 case BFD_RELOC_MIPS_GOT_PAGE:
15313 case BFD_RELOC_MIPS_GOT_OFST:
15314 case BFD_RELOC_MIPS_SUB:
15315 case BFD_RELOC_MIPS_INSERT_A:
15316 case BFD_RELOC_MIPS_INSERT_B:
15317 case BFD_RELOC_MIPS_DELETE:
15318 case BFD_RELOC_MIPS_HIGHEST:
15319 case BFD_RELOC_MIPS_HIGHER:
15320 case BFD_RELOC_MIPS_SCN_DISP:
15321 case BFD_RELOC_MIPS_REL16:
15322 case BFD_RELOC_MIPS_RELGOT:
15323 case BFD_RELOC_MIPS_JALR:
15324 case BFD_RELOC_HI16:
15325 case BFD_RELOC_HI16_S:
15326 case BFD_RELOC_GPREL16:
15327 case BFD_RELOC_MIPS_LITERAL:
15328 case BFD_RELOC_MIPS_CALL16:
15329 case BFD_RELOC_MIPS_GOT16:
15330 case BFD_RELOC_GPREL32:
15331 case BFD_RELOC_MIPS_GOT_HI16:
15332 case BFD_RELOC_MIPS_GOT_LO16:
15333 case BFD_RELOC_MIPS_CALL_HI16:
15334 case BFD_RELOC_MIPS_CALL_LO16:
15335 case BFD_RELOC_MIPS16_GPREL:
15336 case BFD_RELOC_MIPS16_GOT16:
15337 case BFD_RELOC_MIPS16_CALL16:
15338 case BFD_RELOC_MIPS16_HI16:
15339 case BFD_RELOC_MIPS16_HI16_S:
15340 case BFD_RELOC_MIPS16_JMP:
15341 case BFD_RELOC_MICROMIPS_JMP:
15342 case BFD_RELOC_MICROMIPS_GOT_DISP:
15343 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15344 case BFD_RELOC_MICROMIPS_GOT_OFST:
15345 case BFD_RELOC_MICROMIPS_SUB:
15346 case BFD_RELOC_MICROMIPS_HIGHEST:
15347 case BFD_RELOC_MICROMIPS_HIGHER:
15348 case BFD_RELOC_MICROMIPS_SCN_DISP:
15349 case BFD_RELOC_MICROMIPS_JALR:
15350 case BFD_RELOC_MICROMIPS_HI16:
15351 case BFD_RELOC_MICROMIPS_HI16_S:
15352 case BFD_RELOC_MICROMIPS_GPREL16:
15353 case BFD_RELOC_MICROMIPS_LITERAL:
15354 case BFD_RELOC_MICROMIPS_CALL16:
15355 case BFD_RELOC_MICROMIPS_GOT16:
15356 case BFD_RELOC_MICROMIPS_GOT_HI16:
15357 case BFD_RELOC_MICROMIPS_GOT_LO16:
15358 case BFD_RELOC_MICROMIPS_CALL_HI16:
15359 case BFD_RELOC_MICROMIPS_CALL_LO16:
15360 /* Nothing needed to do. The value comes from the reloc entry. */
15364 /* This is handled like BFD_RELOC_32, but we output a sign
15365 extended value if we are only 32 bits. */
15368 if (8 <= sizeof (valueT))
15369 md_number_to_chars ((char *) buf, *valP, 8);
15374 if ((*valP & 0x80000000) != 0)
15378 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15380 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15386 case BFD_RELOC_RVA:
15389 /* If we are deleting this reloc entry, we must fill in the
15390 value now. This can happen if we have a .word which is not
15391 resolved when it appears but is later defined. */
15393 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15396 case BFD_RELOC_LO16:
15397 case BFD_RELOC_MIPS16_LO16:
15398 case BFD_RELOC_MICROMIPS_LO16:
15399 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15400 may be safe to remove, but if so it's not obvious. */
15401 /* When handling an embedded PIC switch statement, we can wind
15402 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15405 if (*valP + 0x8000 > 0xffff)
15406 as_bad_where (fixP->fx_file, fixP->fx_line,
15407 _("relocation overflow"));
15408 /* 32-bit microMIPS instructions are divided into two halfwords.
15409 Relocations always refer to the second halfword, regardless
15411 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15413 md_number_to_chars ((char *) buf, *valP, 2);
15417 case BFD_RELOC_16_PCREL_S2:
15418 if ((*valP & 0x3) != 0)
15419 as_bad_where (fixP->fx_file, fixP->fx_line,
15420 _("Branch to misaligned address (%lx)"), (long) *valP);
15422 /* We need to save the bits in the instruction since fixup_segment()
15423 might be deleting the relocation entry (i.e., a branch within
15424 the current segment). */
15425 if (! fixP->fx_done)
15428 /* Update old instruction data. */
15429 if (target_big_endian)
15430 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15432 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15434 if (*valP + 0x20000 <= 0x3ffff)
15436 insn |= (*valP >> 2) & 0xffff;
15437 md_number_to_chars ((char *) buf, insn, 4);
15439 else if (mips_pic == NO_PIC
15441 && fixP->fx_frag->fr_address >= text_section->vma
15442 && (fixP->fx_frag->fr_address
15443 < text_section->vma + bfd_get_section_size (text_section))
15444 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15445 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15446 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15448 /* The branch offset is too large. If this is an
15449 unconditional branch, and we are not generating PIC code,
15450 we can convert it to an absolute jump instruction. */
15451 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15452 insn = 0x0c000000; /* jal */
15454 insn = 0x08000000; /* j */
15455 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15457 fixP->fx_addsy = section_symbol (text_section);
15458 *valP += md_pcrel_from (fixP);
15459 md_number_to_chars ((char *) buf, insn, 4);
15463 /* If we got here, we have branch-relaxation disabled,
15464 and there's nothing we can do to fix this instruction
15465 without turning it into a longer sequence. */
15466 as_bad_where (fixP->fx_file, fixP->fx_line,
15467 _("Branch out of range"));
15471 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15472 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15473 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15474 /* We adjust the offset back to even. */
15475 if ((*valP & 0x1) != 0)
15478 if (! fixP->fx_done)
15481 /* Should never visit here, because we keep the relocation. */
15485 case BFD_RELOC_VTABLE_INHERIT:
15488 && !S_IS_DEFINED (fixP->fx_addsy)
15489 && !S_IS_WEAK (fixP->fx_addsy))
15490 S_SET_WEAK (fixP->fx_addsy);
15493 case BFD_RELOC_VTABLE_ENTRY:
15501 /* Remember value for tc_gen_reloc. */
15502 fixP->fx_addnumber = *valP;
15512 name = input_line_pointer;
15513 c = get_symbol_end ();
15514 p = (symbolS *) symbol_find_or_make (name);
15515 *input_line_pointer = c;
15519 /* Align the current frag to a given power of two. If a particular
15520 fill byte should be used, FILL points to an integer that contains
15521 that byte, otherwise FILL is null.
15523 The MIPS assembler also automatically adjusts any preceding
15527 mips_align (int to, int *fill, symbolS *label)
15529 mips_emit_delays ();
15530 mips_record_compressed_mode ();
15531 if (fill == NULL && subseg_text_p (now_seg))
15532 frag_align_code (to, 0);
15534 frag_align (to, fill ? *fill : 0, 0);
15535 record_alignment (now_seg, to);
15538 gas_assert (S_GET_SEGMENT (label) == now_seg);
15539 symbol_set_frag (label, frag_now);
15540 S_SET_VALUE (label, (valueT) frag_now_fix ());
15544 /* Align to a given power of two. .align 0 turns off the automatic
15545 alignment used by the data creating pseudo-ops. */
15548 s_align (int x ATTRIBUTE_UNUSED)
15550 int temp, fill_value, *fill_ptr;
15551 long max_alignment = 28;
15553 /* o Note that the assembler pulls down any immediately preceding label
15554 to the aligned address.
15555 o It's not documented but auto alignment is reinstated by
15556 a .align pseudo instruction.
15557 o Note also that after auto alignment is turned off the mips assembler
15558 issues an error on attempt to assemble an improperly aligned data item.
15561 temp = get_absolute_expression ();
15562 if (temp > max_alignment)
15563 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15566 as_warn (_("Alignment negative: 0 assumed."));
15569 if (*input_line_pointer == ',')
15571 ++input_line_pointer;
15572 fill_value = get_absolute_expression ();
15573 fill_ptr = &fill_value;
15579 segment_info_type *si = seg_info (now_seg);
15580 struct insn_label_list *l = si->label_list;
15581 /* Auto alignment should be switched on by next section change. */
15583 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
15590 demand_empty_rest_of_line ();
15594 s_change_sec (int sec)
15599 /* The ELF backend needs to know that we are changing sections, so
15600 that .previous works correctly. We could do something like check
15601 for an obj_section_change_hook macro, but that might be confusing
15602 as it would not be appropriate to use it in the section changing
15603 functions in read.c, since obj-elf.c intercepts those. FIXME:
15604 This should be cleaner, somehow. */
15606 obj_elf_section_change_hook ();
15609 mips_emit_delays ();
15620 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15621 demand_empty_rest_of_line ();
15625 seg = subseg_new (RDATA_SECTION_NAME,
15626 (subsegT) get_absolute_expression ());
15629 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15630 | SEC_READONLY | SEC_RELOC
15632 if (strncmp (TARGET_OS, "elf", 3) != 0)
15633 record_alignment (seg, 4);
15635 demand_empty_rest_of_line ();
15639 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15642 bfd_set_section_flags (stdoutput, seg,
15643 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15644 if (strncmp (TARGET_OS, "elf", 3) != 0)
15645 record_alignment (seg, 4);
15647 demand_empty_rest_of_line ();
15651 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15654 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15655 if (strncmp (TARGET_OS, "elf", 3) != 0)
15656 record_alignment (seg, 4);
15658 demand_empty_rest_of_line ();
15666 s_change_section (int ignore ATTRIBUTE_UNUSED)
15669 char *section_name;
15674 int section_entry_size;
15675 int section_alignment;
15680 section_name = input_line_pointer;
15681 c = get_symbol_end ();
15683 next_c = *(input_line_pointer + 1);
15685 /* Do we have .section Name<,"flags">? */
15686 if (c != ',' || (c == ',' && next_c == '"'))
15688 /* just after name is now '\0'. */
15689 *input_line_pointer = c;
15690 input_line_pointer = section_name;
15691 obj_elf_section (ignore);
15694 input_line_pointer++;
15696 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15698 section_type = get_absolute_expression ();
15701 if (*input_line_pointer++ == ',')
15702 section_flag = get_absolute_expression ();
15705 if (*input_line_pointer++ == ',')
15706 section_entry_size = get_absolute_expression ();
15708 section_entry_size = 0;
15709 if (*input_line_pointer++ == ',')
15710 section_alignment = get_absolute_expression ();
15712 section_alignment = 0;
15713 /* FIXME: really ignore? */
15714 (void) section_alignment;
15716 section_name = xstrdup (section_name);
15718 /* When using the generic form of .section (as implemented by obj-elf.c),
15719 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15720 traditionally had to fall back on the more common @progbits instead.
15722 There's nothing really harmful in this, since bfd will correct
15723 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15724 means that, for backwards compatibility, the special_section entries
15725 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15727 Even so, we shouldn't force users of the MIPS .section syntax to
15728 incorrectly label the sections as SHT_PROGBITS. The best compromise
15729 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15730 generic type-checking code. */
15731 if (section_type == SHT_MIPS_DWARF)
15732 section_type = SHT_PROGBITS;
15734 obj_elf_change_section (section_name, section_type, section_flag,
15735 section_entry_size, 0, 0, 0);
15737 if (now_seg->name != section_name)
15738 free (section_name);
15739 #endif /* OBJ_ELF */
15743 mips_enable_auto_align (void)
15749 s_cons (int log_size)
15751 segment_info_type *si = seg_info (now_seg);
15752 struct insn_label_list *l = si->label_list;
15755 label = l != NULL ? l->label : NULL;
15756 mips_emit_delays ();
15757 if (log_size > 0 && auto_align)
15758 mips_align (log_size, 0, label);
15759 cons (1 << log_size);
15760 mips_clear_insn_labels ();
15764 s_float_cons (int type)
15766 segment_info_type *si = seg_info (now_seg);
15767 struct insn_label_list *l = si->label_list;
15770 label = l != NULL ? l->label : NULL;
15772 mips_emit_delays ();
15777 mips_align (3, 0, label);
15779 mips_align (2, 0, label);
15783 mips_clear_insn_labels ();
15786 /* Handle .globl. We need to override it because on Irix 5 you are
15789 where foo is an undefined symbol, to mean that foo should be
15790 considered to be the address of a function. */
15793 s_mips_globl (int x ATTRIBUTE_UNUSED)
15802 name = input_line_pointer;
15803 c = get_symbol_end ();
15804 symbolP = symbol_find_or_make (name);
15805 S_SET_EXTERNAL (symbolP);
15807 *input_line_pointer = c;
15808 SKIP_WHITESPACE ();
15810 /* On Irix 5, every global symbol that is not explicitly labelled as
15811 being a function is apparently labelled as being an object. */
15814 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15815 && (*input_line_pointer != ','))
15820 secname = input_line_pointer;
15821 c = get_symbol_end ();
15822 sec = bfd_get_section_by_name (stdoutput, secname);
15824 as_bad (_("%s: no such section"), secname);
15825 *input_line_pointer = c;
15827 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15828 flag = BSF_FUNCTION;
15831 symbol_get_bfdsym (symbolP)->flags |= flag;
15833 c = *input_line_pointer;
15836 input_line_pointer++;
15837 SKIP_WHITESPACE ();
15838 if (is_end_of_line[(unsigned char) *input_line_pointer])
15844 demand_empty_rest_of_line ();
15848 s_option (int x ATTRIBUTE_UNUSED)
15853 opt = input_line_pointer;
15854 c = get_symbol_end ();
15858 /* FIXME: What does this mean? */
15860 else if (strncmp (opt, "pic", 3) == 0)
15864 i = atoi (opt + 3);
15869 mips_pic = SVR4_PIC;
15870 mips_abicalls = TRUE;
15873 as_bad (_(".option pic%d not supported"), i);
15875 if (mips_pic == SVR4_PIC)
15877 if (g_switch_seen && g_switch_value != 0)
15878 as_warn (_("-G may not be used with SVR4 PIC code"));
15879 g_switch_value = 0;
15880 bfd_set_gp_size (stdoutput, 0);
15884 as_warn (_("Unrecognized option \"%s\""), opt);
15886 *input_line_pointer = c;
15887 demand_empty_rest_of_line ();
15890 /* This structure is used to hold a stack of .set values. */
15892 struct mips_option_stack
15894 struct mips_option_stack *next;
15895 struct mips_set_options options;
15898 static struct mips_option_stack *mips_opts_stack;
15900 /* Handle the .set pseudo-op. */
15903 s_mipsset (int x ATTRIBUTE_UNUSED)
15905 char *name = input_line_pointer, ch;
15907 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15908 ++input_line_pointer;
15909 ch = *input_line_pointer;
15910 *input_line_pointer = '\0';
15912 if (strcmp (name, "reorder") == 0)
15914 if (mips_opts.noreorder)
15917 else if (strcmp (name, "noreorder") == 0)
15919 if (!mips_opts.noreorder)
15920 start_noreorder ();
15922 else if (strncmp (name, "at=", 3) == 0)
15924 char *s = name + 3;
15926 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15927 as_bad (_("Unrecognized register name `%s'"), s);
15929 else if (strcmp (name, "at") == 0)
15931 mips_opts.at = ATREG;
15933 else if (strcmp (name, "noat") == 0)
15935 mips_opts.at = ZERO;
15937 else if (strcmp (name, "macro") == 0)
15939 mips_opts.warn_about_macros = 0;
15941 else if (strcmp (name, "nomacro") == 0)
15943 if (mips_opts.noreorder == 0)
15944 as_bad (_("`noreorder' must be set before `nomacro'"));
15945 mips_opts.warn_about_macros = 1;
15947 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15949 mips_opts.nomove = 0;
15951 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15953 mips_opts.nomove = 1;
15955 else if (strcmp (name, "bopt") == 0)
15957 mips_opts.nobopt = 0;
15959 else if (strcmp (name, "nobopt") == 0)
15961 mips_opts.nobopt = 1;
15963 else if (strcmp (name, "gp=default") == 0)
15964 mips_opts.gp32 = file_mips_gp32;
15965 else if (strcmp (name, "gp=32") == 0)
15966 mips_opts.gp32 = 1;
15967 else if (strcmp (name, "gp=64") == 0)
15969 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
15970 as_warn (_("%s isa does not support 64-bit registers"),
15971 mips_cpu_info_from_isa (mips_opts.isa)->name);
15972 mips_opts.gp32 = 0;
15974 else if (strcmp (name, "fp=default") == 0)
15975 mips_opts.fp32 = file_mips_fp32;
15976 else if (strcmp (name, "fp=32") == 0)
15977 mips_opts.fp32 = 1;
15978 else if (strcmp (name, "fp=64") == 0)
15980 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15981 as_warn (_("%s isa does not support 64-bit floating point registers"),
15982 mips_cpu_info_from_isa (mips_opts.isa)->name);
15983 mips_opts.fp32 = 0;
15985 else if (strcmp (name, "softfloat") == 0)
15986 mips_opts.soft_float = 1;
15987 else if (strcmp (name, "hardfloat") == 0)
15988 mips_opts.soft_float = 0;
15989 else if (strcmp (name, "singlefloat") == 0)
15990 mips_opts.single_float = 1;
15991 else if (strcmp (name, "doublefloat") == 0)
15992 mips_opts.single_float = 0;
15993 else if (strcmp (name, "mips16") == 0
15994 || strcmp (name, "MIPS-16") == 0)
15996 if (mips_opts.micromips == 1)
15997 as_fatal (_("`mips16' cannot be used with `micromips'"));
15998 mips_opts.mips16 = 1;
16000 else if (strcmp (name, "nomips16") == 0
16001 || strcmp (name, "noMIPS-16") == 0)
16002 mips_opts.mips16 = 0;
16003 else if (strcmp (name, "micromips") == 0)
16005 if (mips_opts.mips16 == 1)
16006 as_fatal (_("`micromips' cannot be used with `mips16'"));
16007 mips_opts.micromips = 1;
16009 else if (strcmp (name, "nomicromips") == 0)
16010 mips_opts.micromips = 0;
16011 else if (strcmp (name, "smartmips") == 0)
16013 if (!ISA_SUPPORTS_SMARTMIPS)
16014 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16015 mips_cpu_info_from_isa (mips_opts.isa)->name);
16016 mips_opts.ase_smartmips = 1;
16018 else if (strcmp (name, "nosmartmips") == 0)
16019 mips_opts.ase_smartmips = 0;
16020 else if (strcmp (name, "mips3d") == 0)
16021 mips_opts.ase_mips3d = 1;
16022 else if (strcmp (name, "nomips3d") == 0)
16023 mips_opts.ase_mips3d = 0;
16024 else if (strcmp (name, "mdmx") == 0)
16025 mips_opts.ase_mdmx = 1;
16026 else if (strcmp (name, "nomdmx") == 0)
16027 mips_opts.ase_mdmx = 0;
16028 else if (strcmp (name, "dsp") == 0)
16030 if (!ISA_SUPPORTS_DSP_ASE)
16031 as_warn (_("%s ISA does not support DSP ASE"),
16032 mips_cpu_info_from_isa (mips_opts.isa)->name);
16033 mips_opts.ase_dsp = 1;
16034 mips_opts.ase_dspr2 = 0;
16036 else if (strcmp (name, "nodsp") == 0)
16038 mips_opts.ase_dsp = 0;
16039 mips_opts.ase_dspr2 = 0;
16041 else if (strcmp (name, "dspr2") == 0)
16043 if (!ISA_SUPPORTS_DSPR2_ASE)
16044 as_warn (_("%s ISA does not support DSP R2 ASE"),
16045 mips_cpu_info_from_isa (mips_opts.isa)->name);
16046 mips_opts.ase_dspr2 = 1;
16047 mips_opts.ase_dsp = 1;
16049 else if (strcmp (name, "nodspr2") == 0)
16051 mips_opts.ase_dspr2 = 0;
16052 mips_opts.ase_dsp = 0;
16054 else if (strcmp (name, "mt") == 0)
16056 if (!ISA_SUPPORTS_MT_ASE)
16057 as_warn (_("%s ISA does not support MT ASE"),
16058 mips_cpu_info_from_isa (mips_opts.isa)->name);
16059 mips_opts.ase_mt = 1;
16061 else if (strcmp (name, "nomt") == 0)
16062 mips_opts.ase_mt = 0;
16063 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16067 /* Permit the user to change the ISA and architecture on the fly.
16068 Needless to say, misuse can cause serious problems. */
16069 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16072 mips_opts.isa = file_mips_isa;
16073 mips_opts.arch = file_mips_arch;
16075 else if (strncmp (name, "arch=", 5) == 0)
16077 const struct mips_cpu_info *p;
16079 p = mips_parse_cpu("internal use", name + 5);
16081 as_bad (_("unknown architecture %s"), name + 5);
16084 mips_opts.arch = p->cpu;
16085 mips_opts.isa = p->isa;
16088 else if (strncmp (name, "mips", 4) == 0)
16090 const struct mips_cpu_info *p;
16092 p = mips_parse_cpu("internal use", name);
16094 as_bad (_("unknown ISA level %s"), name + 4);
16097 mips_opts.arch = p->cpu;
16098 mips_opts.isa = p->isa;
16102 as_bad (_("unknown ISA or architecture %s"), name);
16104 switch (mips_opts.isa)
16112 mips_opts.gp32 = 1;
16113 mips_opts.fp32 = 1;
16120 mips_opts.gp32 = 0;
16121 mips_opts.fp32 = 0;
16124 as_bad (_("unknown ISA level %s"), name + 4);
16129 mips_opts.gp32 = file_mips_gp32;
16130 mips_opts.fp32 = file_mips_fp32;
16133 else if (strcmp (name, "autoextend") == 0)
16134 mips_opts.noautoextend = 0;
16135 else if (strcmp (name, "noautoextend") == 0)
16136 mips_opts.noautoextend = 1;
16137 else if (strcmp (name, "push") == 0)
16139 struct mips_option_stack *s;
16141 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16142 s->next = mips_opts_stack;
16143 s->options = mips_opts;
16144 mips_opts_stack = s;
16146 else if (strcmp (name, "pop") == 0)
16148 struct mips_option_stack *s;
16150 s = mips_opts_stack;
16152 as_bad (_(".set pop with no .set push"));
16155 /* If we're changing the reorder mode we need to handle
16156 delay slots correctly. */
16157 if (s->options.noreorder && ! mips_opts.noreorder)
16158 start_noreorder ();
16159 else if (! s->options.noreorder && mips_opts.noreorder)
16162 mips_opts = s->options;
16163 mips_opts_stack = s->next;
16167 else if (strcmp (name, "sym32") == 0)
16168 mips_opts.sym32 = TRUE;
16169 else if (strcmp (name, "nosym32") == 0)
16170 mips_opts.sym32 = FALSE;
16171 else if (strchr (name, ','))
16173 /* Generic ".set" directive; use the generic handler. */
16174 *input_line_pointer = ch;
16175 input_line_pointer = name;
16181 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16183 *input_line_pointer = ch;
16184 demand_empty_rest_of_line ();
16187 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16188 .option pic2. It means to generate SVR4 PIC calls. */
16191 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16193 mips_pic = SVR4_PIC;
16194 mips_abicalls = TRUE;
16196 if (g_switch_seen && g_switch_value != 0)
16197 as_warn (_("-G may not be used with SVR4 PIC code"));
16198 g_switch_value = 0;
16200 bfd_set_gp_size (stdoutput, 0);
16201 demand_empty_rest_of_line ();
16204 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16205 PIC code. It sets the $gp register for the function based on the
16206 function address, which is in the register named in the argument.
16207 This uses a relocation against _gp_disp, which is handled specially
16208 by the linker. The result is:
16209 lui $gp,%hi(_gp_disp)
16210 addiu $gp,$gp,%lo(_gp_disp)
16211 addu $gp,$gp,.cpload argument
16212 The .cpload argument is normally $25 == $t9.
16214 The -mno-shared option changes this to:
16215 lui $gp,%hi(__gnu_local_gp)
16216 addiu $gp,$gp,%lo(__gnu_local_gp)
16217 and the argument is ignored. This saves an instruction, but the
16218 resulting code is not position independent; it uses an absolute
16219 address for __gnu_local_gp. Thus code assembled with -mno-shared
16220 can go into an ordinary executable, but not into a shared library. */
16223 s_cpload (int ignore ATTRIBUTE_UNUSED)
16229 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16230 .cpload is ignored. */
16231 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16237 /* .cpload should be in a .set noreorder section. */
16238 if (mips_opts.noreorder == 0)
16239 as_warn (_(".cpload not in noreorder section"));
16241 reg = tc_get_register (0);
16243 /* If we need to produce a 64-bit address, we are better off using
16244 the default instruction sequence. */
16245 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16247 ex.X_op = O_symbol;
16248 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16250 ex.X_op_symbol = NULL;
16251 ex.X_add_number = 0;
16253 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16254 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16257 macro_build_lui (&ex, mips_gp_register);
16258 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16259 mips_gp_register, BFD_RELOC_LO16);
16261 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16262 mips_gp_register, reg);
16265 demand_empty_rest_of_line ();
16268 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16269 .cpsetup $reg1, offset|$reg2, label
16271 If offset is given, this results in:
16272 sd $gp, offset($sp)
16273 lui $gp, %hi(%neg(%gp_rel(label)))
16274 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16275 daddu $gp, $gp, $reg1
16277 If $reg2 is given, this results in:
16278 daddu $reg2, $gp, $0
16279 lui $gp, %hi(%neg(%gp_rel(label)))
16280 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16281 daddu $gp, $gp, $reg1
16282 $reg1 is normally $25 == $t9.
16284 The -mno-shared option replaces the last three instructions with
16286 addiu $gp,$gp,%lo(_gp) */
16289 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16291 expressionS ex_off;
16292 expressionS ex_sym;
16295 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16296 We also need NewABI support. */
16297 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16303 reg1 = tc_get_register (0);
16304 SKIP_WHITESPACE ();
16305 if (*input_line_pointer != ',')
16307 as_bad (_("missing argument separator ',' for .cpsetup"));
16311 ++input_line_pointer;
16312 SKIP_WHITESPACE ();
16313 if (*input_line_pointer == '$')
16315 mips_cpreturn_register = tc_get_register (0);
16316 mips_cpreturn_offset = -1;
16320 mips_cpreturn_offset = get_absolute_expression ();
16321 mips_cpreturn_register = -1;
16323 SKIP_WHITESPACE ();
16324 if (*input_line_pointer != ',')
16326 as_bad (_("missing argument separator ',' for .cpsetup"));
16330 ++input_line_pointer;
16331 SKIP_WHITESPACE ();
16332 expression (&ex_sym);
16335 if (mips_cpreturn_register == -1)
16337 ex_off.X_op = O_constant;
16338 ex_off.X_add_symbol = NULL;
16339 ex_off.X_op_symbol = NULL;
16340 ex_off.X_add_number = mips_cpreturn_offset;
16342 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16343 BFD_RELOC_LO16, SP);
16346 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16347 mips_gp_register, 0);
16349 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16351 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16352 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16355 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16356 mips_gp_register, -1, BFD_RELOC_GPREL16,
16357 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16359 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16360 mips_gp_register, reg1);
16366 ex.X_op = O_symbol;
16367 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16368 ex.X_op_symbol = NULL;
16369 ex.X_add_number = 0;
16371 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16372 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16374 macro_build_lui (&ex, mips_gp_register);
16375 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16376 mips_gp_register, BFD_RELOC_LO16);
16381 demand_empty_rest_of_line ();
16385 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16387 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16388 .cplocal is ignored. */
16389 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16395 mips_gp_register = tc_get_register (0);
16396 demand_empty_rest_of_line ();
16399 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16400 offset from $sp. The offset is remembered, and after making a PIC
16401 call $gp is restored from that location. */
16404 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16408 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16409 .cprestore is ignored. */
16410 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16416 mips_cprestore_offset = get_absolute_expression ();
16417 mips_cprestore_valid = 1;
16419 ex.X_op = O_constant;
16420 ex.X_add_symbol = NULL;
16421 ex.X_op_symbol = NULL;
16422 ex.X_add_number = mips_cprestore_offset;
16425 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16426 SP, HAVE_64BIT_ADDRESSES);
16429 demand_empty_rest_of_line ();
16432 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16433 was given in the preceding .cpsetup, it results in:
16434 ld $gp, offset($sp)
16436 If a register $reg2 was given there, it results in:
16437 daddu $gp, $reg2, $0 */
16440 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16444 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16445 We also need NewABI support. */
16446 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16453 if (mips_cpreturn_register == -1)
16455 ex.X_op = O_constant;
16456 ex.X_add_symbol = NULL;
16457 ex.X_op_symbol = NULL;
16458 ex.X_add_number = mips_cpreturn_offset;
16460 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16463 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16464 mips_cpreturn_register, 0);
16467 demand_empty_rest_of_line ();
16470 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16471 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16472 use in DWARF debug information. */
16475 s_dtprel_internal (size_t bytes)
16482 if (ex.X_op != O_symbol)
16484 as_bad (_("Unsupported use of %s"), (bytes == 8
16487 ignore_rest_of_line ();
16490 p = frag_more (bytes);
16491 md_number_to_chars (p, 0, bytes);
16492 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16494 ? BFD_RELOC_MIPS_TLS_DTPREL64
16495 : BFD_RELOC_MIPS_TLS_DTPREL32));
16497 demand_empty_rest_of_line ();
16500 /* Handle .dtprelword. */
16503 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16505 s_dtprel_internal (4);
16508 /* Handle .dtpreldword. */
16511 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16513 s_dtprel_internal (8);
16516 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16517 code. It sets the offset to use in gp_rel relocations. */
16520 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16522 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16523 We also need NewABI support. */
16524 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16530 mips_gprel_offset = get_absolute_expression ();
16532 demand_empty_rest_of_line ();
16535 /* Handle the .gpword pseudo-op. This is used when generating PIC
16536 code. It generates a 32 bit GP relative reloc. */
16539 s_gpword (int ignore ATTRIBUTE_UNUSED)
16541 segment_info_type *si;
16542 struct insn_label_list *l;
16547 /* When not generating PIC code, this is treated as .word. */
16548 if (mips_pic != SVR4_PIC)
16554 si = seg_info (now_seg);
16555 l = si->label_list;
16556 label = l != NULL ? l->label : NULL;
16557 mips_emit_delays ();
16559 mips_align (2, 0, label);
16562 mips_clear_insn_labels ();
16564 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16566 as_bad (_("Unsupported use of .gpword"));
16567 ignore_rest_of_line ();
16571 md_number_to_chars (p, 0, 4);
16572 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16573 BFD_RELOC_GPREL32);
16575 demand_empty_rest_of_line ();
16579 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16581 segment_info_type *si;
16582 struct insn_label_list *l;
16587 /* When not generating PIC code, this is treated as .dword. */
16588 if (mips_pic != SVR4_PIC)
16594 si = seg_info (now_seg);
16595 l = si->label_list;
16596 label = l != NULL ? l->label : NULL;
16597 mips_emit_delays ();
16599 mips_align (3, 0, label);
16602 mips_clear_insn_labels ();
16604 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16606 as_bad (_("Unsupported use of .gpdword"));
16607 ignore_rest_of_line ();
16611 md_number_to_chars (p, 0, 8);
16612 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16613 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16615 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16616 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16617 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16619 demand_empty_rest_of_line ();
16622 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16623 tables in SVR4 PIC code. */
16626 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16630 /* This is ignored when not generating SVR4 PIC code. */
16631 if (mips_pic != SVR4_PIC)
16637 /* Add $gp to the register named as an argument. */
16639 reg = tc_get_register (0);
16640 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16643 demand_empty_rest_of_line ();
16646 /* Handle the .insn pseudo-op. This marks instruction labels in
16647 mips16/micromips mode. This permits the linker to handle them specially,
16648 such as generating jalx instructions when needed. We also make
16649 them odd for the duration of the assembly, in order to generate the
16650 right sort of code. We will make them even in the adjust_symtab
16651 routine, while leaving them marked. This is convenient for the
16652 debugger and the disassembler. The linker knows to make them odd
16656 s_insn (int ignore ATTRIBUTE_UNUSED)
16658 mips_mark_labels ();
16660 demand_empty_rest_of_line ();
16663 /* Handle a .stabn directive. We need these in order to mark a label
16664 as being a mips16 text label correctly. Sometimes the compiler
16665 will emit a label, followed by a .stabn, and then switch sections.
16666 If the label and .stabn are in mips16 mode, then the label is
16667 really a mips16 text label. */
16670 s_mips_stab (int type)
16673 mips_mark_labels ();
16678 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16681 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16688 name = input_line_pointer;
16689 c = get_symbol_end ();
16690 symbolP = symbol_find_or_make (name);
16691 S_SET_WEAK (symbolP);
16692 *input_line_pointer = c;
16694 SKIP_WHITESPACE ();
16696 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16698 if (S_IS_DEFINED (symbolP))
16700 as_bad (_("ignoring attempt to redefine symbol %s"),
16701 S_GET_NAME (symbolP));
16702 ignore_rest_of_line ();
16706 if (*input_line_pointer == ',')
16708 ++input_line_pointer;
16709 SKIP_WHITESPACE ();
16713 if (exp.X_op != O_symbol)
16715 as_bad (_("bad .weakext directive"));
16716 ignore_rest_of_line ();
16719 symbol_set_value_expression (symbolP, &exp);
16722 demand_empty_rest_of_line ();
16725 /* Parse a register string into a number. Called from the ECOFF code
16726 to parse .frame. The argument is non-zero if this is the frame
16727 register, so that we can record it in mips_frame_reg. */
16730 tc_get_register (int frame)
16734 SKIP_WHITESPACE ();
16735 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16739 mips_frame_reg = reg != 0 ? reg : SP;
16740 mips_frame_reg_valid = 1;
16741 mips_cprestore_valid = 0;
16747 md_section_align (asection *seg, valueT addr)
16749 int align = bfd_get_section_alignment (stdoutput, seg);
16753 /* We don't need to align ELF sections to the full alignment.
16754 However, Irix 5 may prefer that we align them at least to a 16
16755 byte boundary. We don't bother to align the sections if we
16756 are targeted for an embedded system. */
16757 if (strncmp (TARGET_OS, "elf", 3) == 0)
16763 return ((addr + (1 << align) - 1) & (-1 << align));
16766 /* Utility routine, called from above as well. If called while the
16767 input file is still being read, it's only an approximation. (For
16768 example, a symbol may later become defined which appeared to be
16769 undefined earlier.) */
16772 nopic_need_relax (symbolS *sym, int before_relaxing)
16777 if (g_switch_value > 0)
16779 const char *symname;
16782 /* Find out whether this symbol can be referenced off the $gp
16783 register. It can be if it is smaller than the -G size or if
16784 it is in the .sdata or .sbss section. Certain symbols can
16785 not be referenced off the $gp, although it appears as though
16787 symname = S_GET_NAME (sym);
16788 if (symname != (const char *) NULL
16789 && (strcmp (symname, "eprol") == 0
16790 || strcmp (symname, "etext") == 0
16791 || strcmp (symname, "_gp") == 0
16792 || strcmp (symname, "edata") == 0
16793 || strcmp (symname, "_fbss") == 0
16794 || strcmp (symname, "_fdata") == 0
16795 || strcmp (symname, "_ftext") == 0
16796 || strcmp (symname, "end") == 0
16797 || strcmp (symname, "_gp_disp") == 0))
16799 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16801 #ifndef NO_ECOFF_DEBUGGING
16802 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16803 && (symbol_get_obj (sym)->ecoff_extern_size
16804 <= g_switch_value))
16806 /* We must defer this decision until after the whole
16807 file has been read, since there might be a .extern
16808 after the first use of this symbol. */
16809 || (before_relaxing
16810 #ifndef NO_ECOFF_DEBUGGING
16811 && symbol_get_obj (sym)->ecoff_extern_size == 0
16813 && S_GET_VALUE (sym) == 0)
16814 || (S_GET_VALUE (sym) != 0
16815 && S_GET_VALUE (sym) <= g_switch_value)))
16819 const char *segname;
16821 segname = segment_name (S_GET_SEGMENT (sym));
16822 gas_assert (strcmp (segname, ".lit8") != 0
16823 && strcmp (segname, ".lit4") != 0);
16824 change = (strcmp (segname, ".sdata") != 0
16825 && strcmp (segname, ".sbss") != 0
16826 && strncmp (segname, ".sdata.", 7) != 0
16827 && strncmp (segname, ".sbss.", 6) != 0
16828 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16829 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16834 /* We are not optimizing for the $gp register. */
16839 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16842 pic_need_relax (symbolS *sym, asection *segtype)
16846 /* Handle the case of a symbol equated to another symbol. */
16847 while (symbol_equated_reloc_p (sym))
16851 /* It's possible to get a loop here in a badly written program. */
16852 n = symbol_get_value_expression (sym)->X_add_symbol;
16858 if (symbol_section_p (sym))
16861 symsec = S_GET_SEGMENT (sym);
16863 /* This must duplicate the test in adjust_reloc_syms. */
16864 return (symsec != &bfd_und_section
16865 && symsec != &bfd_abs_section
16866 && !bfd_is_com_section (symsec)
16867 && !s_is_linkonce (sym, segtype)
16869 /* A global or weak symbol is treated as external. */
16870 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
16876 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16877 extended opcode. SEC is the section the frag is in. */
16880 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16883 const struct mips16_immed_operand *op;
16885 int mintiny, maxtiny;
16889 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16891 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16894 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16895 op = mips16_immed_operands;
16896 while (op->type != type)
16899 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
16904 if (type == '<' || type == '>' || type == '[' || type == ']')
16907 maxtiny = 1 << op->nbits;
16912 maxtiny = (1 << op->nbits) - 1;
16917 mintiny = - (1 << (op->nbits - 1));
16918 maxtiny = (1 << (op->nbits - 1)) - 1;
16921 sym_frag = symbol_get_frag (fragp->fr_symbol);
16922 val = S_GET_VALUE (fragp->fr_symbol);
16923 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16929 /* We won't have the section when we are called from
16930 mips_relax_frag. However, we will always have been called
16931 from md_estimate_size_before_relax first. If this is a
16932 branch to a different section, we mark it as such. If SEC is
16933 NULL, and the frag is not marked, then it must be a branch to
16934 the same section. */
16937 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16942 /* Must have been called from md_estimate_size_before_relax. */
16945 fragp->fr_subtype =
16946 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16948 /* FIXME: We should support this, and let the linker
16949 catch branches and loads that are out of range. */
16950 as_bad_where (fragp->fr_file, fragp->fr_line,
16951 _("unsupported PC relative reference to different section"));
16955 if (fragp != sym_frag && sym_frag->fr_address == 0)
16956 /* Assume non-extended on the first relaxation pass.
16957 The address we have calculated will be bogus if this is
16958 a forward branch to another frag, as the forward frag
16959 will have fr_address == 0. */
16963 /* In this case, we know for sure that the symbol fragment is in
16964 the same section. If the relax_marker of the symbol fragment
16965 differs from the relax_marker of this fragment, we have not
16966 yet adjusted the symbol fragment fr_address. We want to add
16967 in STRETCH in order to get a better estimate of the address.
16968 This particularly matters because of the shift bits. */
16970 && sym_frag->relax_marker != fragp->relax_marker)
16974 /* Adjust stretch for any alignment frag. Note that if have
16975 been expanding the earlier code, the symbol may be
16976 defined in what appears to be an earlier frag. FIXME:
16977 This doesn't handle the fr_subtype field, which specifies
16978 a maximum number of bytes to skip when doing an
16980 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16982 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16985 stretch = - ((- stretch)
16986 & ~ ((1 << (int) f->fr_offset) - 1));
16988 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16997 addr = fragp->fr_address + fragp->fr_fix;
16999 /* The base address rules are complicated. The base address of
17000 a branch is the following instruction. The base address of a
17001 PC relative load or add is the instruction itself, but if it
17002 is in a delay slot (in which case it can not be extended) use
17003 the address of the instruction whose delay slot it is in. */
17004 if (type == 'p' || type == 'q')
17008 /* If we are currently assuming that this frag should be
17009 extended, then, the current address is two bytes
17011 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17014 /* Ignore the low bit in the target, since it will be set
17015 for a text label. */
17016 if ((val & 1) != 0)
17019 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17021 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17024 val -= addr & ~ ((1 << op->shift) - 1);
17026 /* Branch offsets have an implicit 0 in the lowest bit. */
17027 if (type == 'p' || type == 'q')
17030 /* If any of the shifted bits are set, we must use an extended
17031 opcode. If the address depends on the size of this
17032 instruction, this can lead to a loop, so we arrange to always
17033 use an extended opcode. We only check this when we are in
17034 the main relaxation loop, when SEC is NULL. */
17035 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17037 fragp->fr_subtype =
17038 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17042 /* If we are about to mark a frag as extended because the value
17043 is precisely maxtiny + 1, then there is a chance of an
17044 infinite loop as in the following code:
17049 In this case when the la is extended, foo is 0x3fc bytes
17050 away, so the la can be shrunk, but then foo is 0x400 away, so
17051 the la must be extended. To avoid this loop, we mark the
17052 frag as extended if it was small, and is about to become
17053 extended with a value of maxtiny + 1. */
17054 if (val == ((maxtiny + 1) << op->shift)
17055 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17058 fragp->fr_subtype =
17059 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17063 else if (symsec != absolute_section && sec != NULL)
17064 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17066 if ((val & ((1 << op->shift) - 1)) != 0
17067 || val < (mintiny << op->shift)
17068 || val > (maxtiny << op->shift))
17074 /* Compute the length of a branch sequence, and adjust the
17075 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17076 worst-case length is computed, with UPDATE being used to indicate
17077 whether an unconditional (-1), branch-likely (+1) or regular (0)
17078 branch is to be computed. */
17080 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17082 bfd_boolean toofar;
17086 && S_IS_DEFINED (fragp->fr_symbol)
17087 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17092 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17094 addr = fragp->fr_address + fragp->fr_fix + 4;
17098 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17101 /* If the symbol is not defined or it's in a different segment,
17102 assume the user knows what's going on and emit a short
17108 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17110 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17111 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17112 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17113 RELAX_BRANCH_LINK (fragp->fr_subtype),
17119 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17122 if (mips_pic != NO_PIC)
17124 /* Additional space for PIC loading of target address. */
17126 if (mips_opts.isa == ISA_MIPS1)
17127 /* Additional space for $at-stabilizing nop. */
17131 /* If branch is conditional. */
17132 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17139 /* Compute the length of a branch sequence, and adjust the
17140 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17141 worst-case length is computed, with UPDATE being used to indicate
17142 whether an unconditional (-1), or regular (0) branch is to be
17146 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17148 bfd_boolean toofar;
17152 && S_IS_DEFINED (fragp->fr_symbol)
17153 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17158 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17159 /* Ignore the low bit in the target, since it will be set
17160 for a text label. */
17161 if ((val & 1) != 0)
17164 addr = fragp->fr_address + fragp->fr_fix + 4;
17168 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17171 /* If the symbol is not defined or it's in a different segment,
17172 assume the user knows what's going on and emit a short
17178 if (fragp && update
17179 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17180 fragp->fr_subtype = (toofar
17181 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17182 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17187 bfd_boolean compact_known = fragp != NULL;
17188 bfd_boolean compact = FALSE;
17189 bfd_boolean uncond;
17192 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17194 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17196 uncond = update < 0;
17198 /* If label is out of range, we turn branch <br>:
17200 <br> label # 4 bytes
17206 nop # 2 bytes if compact && !PIC
17209 if (mips_pic == NO_PIC && (!compact_known || compact))
17212 /* If assembling PIC code, we further turn:
17218 lw/ld at, %got(label)(gp) # 4 bytes
17219 d/addiu at, %lo(label) # 4 bytes
17222 if (mips_pic != NO_PIC)
17225 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17227 <brneg> 0f # 4 bytes
17228 nop # 2 bytes if !compact
17231 length += (compact_known && compact) ? 4 : 6;
17237 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17238 bit accordingly. */
17241 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17243 bfd_boolean toofar;
17246 && S_IS_DEFINED (fragp->fr_symbol)
17247 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17253 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17254 /* Ignore the low bit in the target, since it will be set
17255 for a text label. */
17256 if ((val & 1) != 0)
17259 /* Assume this is a 2-byte branch. */
17260 addr = fragp->fr_address + fragp->fr_fix + 2;
17262 /* We try to avoid the infinite loop by not adding 2 more bytes for
17267 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17269 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17270 else if (type == 'E')
17271 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17276 /* If the symbol is not defined or it's in a different segment,
17277 we emit a normal 32-bit branch. */
17280 if (fragp && update
17281 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17283 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17284 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17292 /* Estimate the size of a frag before relaxing. Unless this is the
17293 mips16, we are not really relaxing here, and the final size is
17294 encoded in the subtype information. For the mips16, we have to
17295 decide whether we are using an extended opcode or not. */
17298 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17302 if (RELAX_BRANCH_P (fragp->fr_subtype))
17305 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17307 return fragp->fr_var;
17310 if (RELAX_MIPS16_P (fragp->fr_subtype))
17311 /* We don't want to modify the EXTENDED bit here; it might get us
17312 into infinite loops. We change it only in mips_relax_frag(). */
17313 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17315 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17319 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17320 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17321 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17322 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17323 fragp->fr_var = length;
17328 if (mips_pic == NO_PIC)
17329 change = nopic_need_relax (fragp->fr_symbol, 0);
17330 else if (mips_pic == SVR4_PIC)
17331 change = pic_need_relax (fragp->fr_symbol, segtype);
17332 else if (mips_pic == VXWORKS_PIC)
17333 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17340 fragp->fr_subtype |= RELAX_USE_SECOND;
17341 return -RELAX_FIRST (fragp->fr_subtype);
17344 return -RELAX_SECOND (fragp->fr_subtype);
17347 /* This is called to see whether a reloc against a defined symbol
17348 should be converted into a reloc against a section. */
17351 mips_fix_adjustable (fixS *fixp)
17353 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17354 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17357 if (fixp->fx_addsy == NULL)
17360 /* If symbol SYM is in a mergeable section, relocations of the form
17361 SYM + 0 can usually be made section-relative. The mergeable data
17362 is then identified by the section offset rather than by the symbol.
17364 However, if we're generating REL LO16 relocations, the offset is split
17365 between the LO16 and parterning high part relocation. The linker will
17366 need to recalculate the complete offset in order to correctly identify
17369 The linker has traditionally not looked for the parterning high part
17370 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17371 placed anywhere. Rather than break backwards compatibility by changing
17372 this, it seems better not to force the issue, and instead keep the
17373 original symbol. This will work with either linker behavior. */
17374 if ((lo16_reloc_p (fixp->fx_r_type)
17375 || reloc_needs_lo_p (fixp->fx_r_type))
17376 && HAVE_IN_PLACE_ADDENDS
17377 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17380 /* There is no place to store an in-place offset for JALR relocations.
17381 Likewise an in-range offset of PC-relative relocations may overflow
17382 the in-place relocatable field if recalculated against the start
17383 address of the symbol's containing section. */
17384 if (HAVE_IN_PLACE_ADDENDS
17385 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17389 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17390 to a floating-point stub. The same is true for non-R_MIPS16_26
17391 relocations against MIPS16 functions; in this case, the stub becomes
17392 the function's canonical address.
17394 Floating-point stubs are stored in unique .mips16.call.* or
17395 .mips16.fn.* sections. If a stub T for function F is in section S,
17396 the first relocation in section S must be against F; this is how the
17397 linker determines the target function. All relocations that might
17398 resolve to T must also be against F. We therefore have the following
17399 restrictions, which are given in an intentionally-redundant way:
17401 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17404 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17405 if that stub might be used.
17407 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17410 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17411 that stub might be used.
17413 There is a further restriction:
17415 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17416 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17417 targets with in-place addends; the relocation field cannot
17418 encode the low bit.
17420 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17421 against a MIPS16 symbol. We deal with (5) by by not reducing any
17422 such relocations on REL targets.
17424 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17425 relocation against some symbol R, no relocation against R may be
17426 reduced. (Note that this deals with (2) as well as (1) because
17427 relocations against global symbols will never be reduced on ELF
17428 targets.) This approach is a little simpler than trying to detect
17429 stub sections, and gives the "all or nothing" per-symbol consistency
17430 that we have for MIPS16 symbols. */
17432 && fixp->fx_subsy == NULL
17433 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17434 || *symbol_get_tc (fixp->fx_addsy)
17435 || (HAVE_IN_PLACE_ADDENDS
17436 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17437 && jmp_reloc_p (fixp->fx_r_type))))
17444 /* Translate internal representation of relocation info to BFD target
17448 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17450 static arelent *retval[4];
17452 bfd_reloc_code_real_type code;
17454 memset (retval, 0, sizeof(retval));
17455 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17456 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17457 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17458 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17460 if (fixp->fx_pcrel)
17462 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17463 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17464 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17465 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17467 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17468 Relocations want only the symbol offset. */
17469 reloc->addend = fixp->fx_addnumber + reloc->address;
17472 /* A gruesome hack which is a result of the gruesome gas
17473 reloc handling. What's worse, for COFF (as opposed to
17474 ECOFF), we might need yet another copy of reloc->address.
17475 See bfd_install_relocation. */
17476 reloc->addend += reloc->address;
17480 reloc->addend = fixp->fx_addnumber;
17482 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17483 entry to be used in the relocation's section offset. */
17484 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17486 reloc->address = reloc->addend;
17490 code = fixp->fx_r_type;
17492 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17493 if (reloc->howto == NULL)
17495 as_bad_where (fixp->fx_file, fixp->fx_line,
17496 _("Can not represent %s relocation in this object file format"),
17497 bfd_get_reloc_code_name (code));
17504 /* Relax a machine dependent frag. This returns the amount by which
17505 the current size of the frag should change. */
17508 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17510 if (RELAX_BRANCH_P (fragp->fr_subtype))
17512 offsetT old_var = fragp->fr_var;
17514 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17516 return fragp->fr_var - old_var;
17519 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17521 offsetT old_var = fragp->fr_var;
17522 offsetT new_var = 4;
17524 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17525 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17526 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17527 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17528 fragp->fr_var = new_var;
17530 return new_var - old_var;
17533 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17536 if (mips16_extended_frag (fragp, NULL, stretch))
17538 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17540 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17545 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17547 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17554 /* Convert a machine dependent frag. */
17557 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17559 if (RELAX_BRANCH_P (fragp->fr_subtype))
17562 unsigned long insn;
17566 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17568 if (target_big_endian)
17569 insn = bfd_getb32 (buf);
17571 insn = bfd_getl32 (buf);
17573 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17575 /* We generate a fixup instead of applying it right now
17576 because, if there are linker relaxations, we're going to
17577 need the relocations. */
17578 exp.X_op = O_symbol;
17579 exp.X_add_symbol = fragp->fr_symbol;
17580 exp.X_add_number = fragp->fr_offset;
17582 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17583 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17584 fixp->fx_file = fragp->fr_file;
17585 fixp->fx_line = fragp->fr_line;
17587 md_number_to_chars ((char *) buf, insn, 4);
17594 as_warn_where (fragp->fr_file, fragp->fr_line,
17595 _("Relaxed out-of-range branch into a jump"));
17597 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17600 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17602 /* Reverse the branch. */
17603 switch ((insn >> 28) & 0xf)
17606 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17607 have the condition reversed by tweaking a single
17608 bit, and their opcodes all have 0x4???????. */
17609 gas_assert ((insn & 0xf1000000) == 0x41000000);
17610 insn ^= 0x00010000;
17614 /* bltz 0x04000000 bgez 0x04010000
17615 bltzal 0x04100000 bgezal 0x04110000 */
17616 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17617 insn ^= 0x00010000;
17621 /* beq 0x10000000 bne 0x14000000
17622 blez 0x18000000 bgtz 0x1c000000 */
17623 insn ^= 0x04000000;
17631 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17633 /* Clear the and-link bit. */
17634 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17636 /* bltzal 0x04100000 bgezal 0x04110000
17637 bltzall 0x04120000 bgezall 0x04130000 */
17638 insn &= ~0x00100000;
17641 /* Branch over the branch (if the branch was likely) or the
17642 full jump (not likely case). Compute the offset from the
17643 current instruction to branch to. */
17644 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17648 /* How many bytes in instructions we've already emitted? */
17649 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17650 /* How many bytes in instructions from here to the end? */
17651 i = fragp->fr_var - i;
17653 /* Convert to instruction count. */
17655 /* Branch counts from the next instruction. */
17658 /* Branch over the jump. */
17659 md_number_to_chars ((char *) buf, insn, 4);
17663 md_number_to_chars ((char *) buf, 0, 4);
17666 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17668 /* beql $0, $0, 2f */
17670 /* Compute the PC offset from the current instruction to
17671 the end of the variable frag. */
17672 /* How many bytes in instructions we've already emitted? */
17673 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17674 /* How many bytes in instructions from here to the end? */
17675 i = fragp->fr_var - i;
17676 /* Convert to instruction count. */
17678 /* Don't decrement i, because we want to branch over the
17682 md_number_to_chars ((char *) buf, insn, 4);
17685 md_number_to_chars ((char *) buf, 0, 4);
17690 if (mips_pic == NO_PIC)
17693 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17694 ? 0x0c000000 : 0x08000000);
17695 exp.X_op = O_symbol;
17696 exp.X_add_symbol = fragp->fr_symbol;
17697 exp.X_add_number = fragp->fr_offset;
17699 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17700 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17701 fixp->fx_file = fragp->fr_file;
17702 fixp->fx_line = fragp->fr_line;
17704 md_number_to_chars ((char *) buf, insn, 4);
17709 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17711 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17712 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17713 insn |= at << OP_SH_RT;
17714 exp.X_op = O_symbol;
17715 exp.X_add_symbol = fragp->fr_symbol;
17716 exp.X_add_number = fragp->fr_offset;
17718 if (fragp->fr_offset)
17720 exp.X_add_symbol = make_expr_symbol (&exp);
17721 exp.X_add_number = 0;
17724 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17725 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17726 fixp->fx_file = fragp->fr_file;
17727 fixp->fx_line = fragp->fr_line;
17729 md_number_to_chars ((char *) buf, insn, 4);
17732 if (mips_opts.isa == ISA_MIPS1)
17735 md_number_to_chars ((char *) buf, 0, 4);
17739 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17740 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17741 insn |= at << OP_SH_RS | at << OP_SH_RT;
17743 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17744 4, &exp, FALSE, BFD_RELOC_LO16);
17745 fixp->fx_file = fragp->fr_file;
17746 fixp->fx_line = fragp->fr_line;
17748 md_number_to_chars ((char *) buf, insn, 4);
17752 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17756 insn |= at << OP_SH_RS;
17758 md_number_to_chars ((char *) buf, insn, 4);
17763 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17764 + fragp->fr_fix + fragp->fr_var);
17766 fragp->fr_fix += fragp->fr_var;
17771 /* Relax microMIPS branches. */
17772 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17774 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17775 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17776 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17777 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17778 bfd_boolean short_ds;
17779 unsigned long insn;
17783 exp.X_op = O_symbol;
17784 exp.X_add_symbol = fragp->fr_symbol;
17785 exp.X_add_number = fragp->fr_offset;
17787 fragp->fr_fix += fragp->fr_var;
17789 /* Handle 16-bit branches that fit or are forced to fit. */
17790 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17792 /* We generate a fixup instead of applying it right now,
17793 because if there is linker relaxation, we're going to
17794 need the relocations. */
17796 fixp = fix_new_exp (fragp,
17797 buf - (bfd_byte *) fragp->fr_literal,
17799 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17800 else if (type == 'E')
17801 fixp = fix_new_exp (fragp,
17802 buf - (bfd_byte *) fragp->fr_literal,
17804 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17808 fixp->fx_file = fragp->fr_file;
17809 fixp->fx_line = fragp->fr_line;
17811 /* These relocations can have an addend that won't fit in
17813 fixp->fx_no_overflow = 1;
17818 /* Handle 32-bit branches that fit or are forced to fit. */
17819 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17820 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17822 /* We generate a fixup instead of applying it right now,
17823 because if there is linker relaxation, we're going to
17824 need the relocations. */
17825 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17826 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17827 fixp->fx_file = fragp->fr_file;
17828 fixp->fx_line = fragp->fr_line;
17834 /* Relax 16-bit branches to 32-bit branches. */
17837 if (target_big_endian)
17838 insn = bfd_getb16 (buf);
17840 insn = bfd_getl16 (buf);
17842 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17843 insn = 0x94000000; /* beq */
17844 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17846 unsigned long regno;
17848 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17849 regno = micromips_to_32_reg_d_map [regno];
17850 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17851 insn |= regno << MICROMIPSOP_SH_RS;
17856 /* Nothing else to do, just write it out. */
17857 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17858 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17860 md_number_to_chars ((char *) buf, insn >> 16, 2);
17862 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17865 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17872 unsigned long next;
17874 if (target_big_endian)
17876 insn = bfd_getb16 (buf);
17877 next = bfd_getb16 (buf + 2);
17881 insn = bfd_getl16 (buf);
17882 next = bfd_getl16 (buf + 2);
17884 insn = (insn << 16) | next;
17887 /* Relax 32-bit branches to a sequence of instructions. */
17888 as_warn_where (fragp->fr_file, fragp->fr_line,
17889 _("Relaxed out-of-range branch into a jump"));
17891 /* Set the short-delay-slot bit. */
17892 short_ds = al && (insn & 0x02000000) != 0;
17894 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17898 /* Reverse the branch. */
17899 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17900 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17901 insn ^= 0x20000000;
17902 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17903 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17904 || (insn & 0xffe00000) == 0x40800000 /* blez */
17905 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17906 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17907 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17908 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17909 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17910 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17911 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17912 insn ^= 0x00400000;
17913 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17914 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17915 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17916 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17917 insn ^= 0x00200000;
17923 /* Clear the and-link and short-delay-slot bits. */
17924 gas_assert ((insn & 0xfda00000) == 0x40200000);
17926 /* bltzal 0x40200000 bgezal 0x40600000 */
17927 /* bltzals 0x42200000 bgezals 0x42600000 */
17928 insn &= ~0x02200000;
17931 /* Make a label at the end for use with the branch. */
17932 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17933 micromips_label_inc ();
17934 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
17936 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17940 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
17941 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17942 fixp->fx_file = fragp->fr_file;
17943 fixp->fx_line = fragp->fr_line;
17945 /* Branch over the jump. */
17946 md_number_to_chars ((char *) buf, insn >> 16, 2);
17948 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17955 md_number_to_chars ((char *) buf, insn, 2);
17960 if (mips_pic == NO_PIC)
17962 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17964 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17965 insn = al ? jal : 0xd4000000;
17967 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17968 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
17969 fixp->fx_file = fragp->fr_file;
17970 fixp->fx_line = fragp->fr_line;
17972 md_number_to_chars ((char *) buf, insn >> 16, 2);
17974 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17981 md_number_to_chars ((char *) buf, insn, 2);
17987 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17988 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17989 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17991 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17992 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17993 insn |= at << MICROMIPSOP_SH_RT;
17995 if (exp.X_add_number)
17997 exp.X_add_symbol = make_expr_symbol (&exp);
17998 exp.X_add_number = 0;
18001 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18002 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18003 fixp->fx_file = fragp->fr_file;
18004 fixp->fx_line = fragp->fr_line;
18006 md_number_to_chars ((char *) buf, insn >> 16, 2);
18008 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18011 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18012 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18013 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18015 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18016 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18017 fixp->fx_file = fragp->fr_file;
18018 fixp->fx_line = fragp->fr_line;
18020 md_number_to_chars ((char *) buf, insn >> 16, 2);
18022 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18025 /* jr/jrc/jalr/jalrs $at */
18026 insn = al ? jalr : jr;
18027 insn |= at << MICROMIPSOP_SH_MJ;
18029 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18033 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18037 if (RELAX_MIPS16_P (fragp->fr_subtype))
18040 const struct mips16_immed_operand *op;
18041 bfd_boolean small, ext;
18044 unsigned long insn;
18045 bfd_boolean use_extend;
18046 unsigned short extend;
18048 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18049 op = mips16_immed_operands;
18050 while (op->type != type)
18053 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18064 val = resolve_symbol_value (fragp->fr_symbol);
18069 addr = fragp->fr_address + fragp->fr_fix;
18071 /* The rules for the base address of a PC relative reloc are
18072 complicated; see mips16_extended_frag. */
18073 if (type == 'p' || type == 'q')
18078 /* Ignore the low bit in the target, since it will be
18079 set for a text label. */
18080 if ((val & 1) != 0)
18083 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18085 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18088 addr &= ~ (addressT) ((1 << op->shift) - 1);
18091 /* Make sure the section winds up with the alignment we have
18094 record_alignment (asec, op->shift);
18098 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18099 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18100 as_warn_where (fragp->fr_file, fragp->fr_line,
18101 _("extended instruction in delay slot"));
18103 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18105 if (target_big_endian)
18106 insn = bfd_getb16 (buf);
18108 insn = bfd_getl16 (buf);
18110 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18111 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18112 small, ext, &insn, &use_extend, &extend);
18116 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18117 fragp->fr_fix += 2;
18121 md_number_to_chars ((char *) buf, insn, 2);
18122 fragp->fr_fix += 2;
18127 relax_substateT subtype = fragp->fr_subtype;
18128 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18129 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18133 first = RELAX_FIRST (subtype);
18134 second = RELAX_SECOND (subtype);
18135 fixp = (fixS *) fragp->fr_opcode;
18137 /* If the delay slot chosen does not match the size of the instruction,
18138 then emit a warning. */
18139 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18140 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18145 s = subtype & (RELAX_DELAY_SLOT_16BIT
18146 | RELAX_DELAY_SLOT_SIZE_FIRST
18147 | RELAX_DELAY_SLOT_SIZE_SECOND);
18148 msg = macro_warning (s);
18150 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18154 /* Possibly emit a warning if we've chosen the longer option. */
18155 if (use_second == second_longer)
18161 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18162 msg = macro_warning (s);
18164 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18168 /* Go through all the fixups for the first sequence. Disable them
18169 (by marking them as done) if we're going to use the second
18170 sequence instead. */
18172 && fixp->fx_frag == fragp
18173 && fixp->fx_where < fragp->fr_fix - second)
18175 if (subtype & RELAX_USE_SECOND)
18177 fixp = fixp->fx_next;
18180 /* Go through the fixups for the second sequence. Disable them if
18181 we're going to use the first sequence, otherwise adjust their
18182 addresses to account for the relaxation. */
18183 while (fixp && fixp->fx_frag == fragp)
18185 if (subtype & RELAX_USE_SECOND)
18186 fixp->fx_where -= first;
18189 fixp = fixp->fx_next;
18192 /* Now modify the frag contents. */
18193 if (subtype & RELAX_USE_SECOND)
18197 start = fragp->fr_literal + fragp->fr_fix - first - second;
18198 memmove (start, start + first, second);
18199 fragp->fr_fix -= first;
18202 fragp->fr_fix -= second;
18208 /* This function is called after the relocs have been generated.
18209 We've been storing mips16 text labels as odd. Here we convert them
18210 back to even for the convenience of the debugger. */
18213 mips_frob_file_after_relocs (void)
18216 unsigned int count, i;
18221 syms = bfd_get_outsymbols (stdoutput);
18222 count = bfd_get_symcount (stdoutput);
18223 for (i = 0; i < count; i++, syms++)
18224 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18225 && ((*syms)->value & 1) != 0)
18227 (*syms)->value &= ~1;
18228 /* If the symbol has an odd size, it was probably computed
18229 incorrectly, so adjust that as well. */
18230 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18231 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18237 /* This function is called whenever a label is defined, including fake
18238 labels instantiated off the dot special symbol. It is used when
18239 handling branch delays; if a branch has a label, we assume we cannot
18240 move it. This also bumps the value of the symbol by 1 in compressed
18244 mips_record_label (symbolS *sym)
18246 segment_info_type *si = seg_info (now_seg);
18247 struct insn_label_list *l;
18249 if (free_insn_labels == NULL)
18250 l = (struct insn_label_list *) xmalloc (sizeof *l);
18253 l = free_insn_labels;
18254 free_insn_labels = l->next;
18258 l->next = si->label_list;
18259 si->label_list = l;
18262 /* This function is called as tc_frob_label() whenever a label is defined
18263 and adds a DWARF-2 record we only want for true labels. */
18266 mips_define_label (symbolS *sym)
18268 mips_record_label (sym);
18270 dwarf2_emit_label (sym);
18274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18276 /* Some special processing for a MIPS ELF file. */
18279 mips_elf_final_processing (void)
18281 /* Write out the register information. */
18282 if (mips_abi != N64_ABI)
18286 s.ri_gprmask = mips_gprmask;
18287 s.ri_cprmask[0] = mips_cprmask[0];
18288 s.ri_cprmask[1] = mips_cprmask[1];
18289 s.ri_cprmask[2] = mips_cprmask[2];
18290 s.ri_cprmask[3] = mips_cprmask[3];
18291 /* The gp_value field is set by the MIPS ELF backend. */
18293 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18294 ((Elf32_External_RegInfo *)
18295 mips_regmask_frag));
18299 Elf64_Internal_RegInfo s;
18301 s.ri_gprmask = mips_gprmask;
18303 s.ri_cprmask[0] = mips_cprmask[0];
18304 s.ri_cprmask[1] = mips_cprmask[1];
18305 s.ri_cprmask[2] = mips_cprmask[2];
18306 s.ri_cprmask[3] = mips_cprmask[3];
18307 /* The gp_value field is set by the MIPS ELF backend. */
18309 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18310 ((Elf64_External_RegInfo *)
18311 mips_regmask_frag));
18314 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18315 sort of BFD interface for this. */
18316 if (mips_any_noreorder)
18317 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18318 if (mips_pic != NO_PIC)
18320 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18321 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18324 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18326 /* Set MIPS ELF flags for ASEs. */
18327 /* We may need to define a new flag for DSP ASE, and set this flag when
18328 file_ase_dsp is true. */
18329 /* Same for DSP R2. */
18330 /* We may need to define a new flag for MT ASE, and set this flag when
18331 file_ase_mt is true. */
18332 if (file_ase_mips16)
18333 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18334 if (file_ase_micromips)
18335 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18336 #if 0 /* XXX FIXME */
18337 if (file_ase_mips3d)
18338 elf_elfheader (stdoutput)->e_flags |= ???;
18341 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18343 /* Set the MIPS ELF ABI flags. */
18344 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18345 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18346 else if (mips_abi == O64_ABI)
18347 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18348 else if (mips_abi == EABI_ABI)
18350 if (!file_mips_gp32)
18351 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18353 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18355 else if (mips_abi == N32_ABI)
18356 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18358 /* Nothing to do for N64_ABI. */
18360 if (mips_32bitmode)
18361 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18363 #if 0 /* XXX FIXME */
18364 /* 32 bit code with 64 bit FP registers. */
18365 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18366 elf_elfheader (stdoutput)->e_flags |= ???;
18370 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18372 typedef struct proc {
18374 symbolS *func_end_sym;
18375 unsigned long reg_mask;
18376 unsigned long reg_offset;
18377 unsigned long fpreg_mask;
18378 unsigned long fpreg_offset;
18379 unsigned long frame_offset;
18380 unsigned long frame_reg;
18381 unsigned long pc_reg;
18384 static procS cur_proc;
18385 static procS *cur_proc_ptr;
18386 static int numprocs;
18388 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18389 as "2", and a normal nop as "0". */
18391 #define NOP_OPCODE_MIPS 0
18392 #define NOP_OPCODE_MIPS16 1
18393 #define NOP_OPCODE_MICROMIPS 2
18396 mips_nop_opcode (void)
18398 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18399 return NOP_OPCODE_MICROMIPS;
18400 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18401 return NOP_OPCODE_MIPS16;
18403 return NOP_OPCODE_MIPS;
18406 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18407 32-bit microMIPS NOPs here (if applicable). */
18410 mips_handle_align (fragS *fragp)
18414 int bytes, size, excess;
18417 if (fragp->fr_type != rs_align_code)
18420 p = fragp->fr_literal + fragp->fr_fix;
18422 switch (nop_opcode)
18424 case NOP_OPCODE_MICROMIPS:
18425 opcode = micromips_nop32_insn.insn_opcode;
18428 case NOP_OPCODE_MIPS16:
18429 opcode = mips16_nop_insn.insn_opcode;
18432 case NOP_OPCODE_MIPS:
18434 opcode = nop_insn.insn_opcode;
18439 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18440 excess = bytes % size;
18442 /* Handle the leading part if we're not inserting a whole number of
18443 instructions, and make it the end of the fixed part of the frag.
18444 Try to fit in a short microMIPS NOP if applicable and possible,
18445 and use zeroes otherwise. */
18446 gas_assert (excess < 4);
18447 fragp->fr_fix += excess;
18452 /* Fall through. */
18454 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18456 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18461 /* Fall through. */
18464 /* Fall through. */
18469 md_number_to_chars (p, opcode, size);
18470 fragp->fr_var = size;
18474 md_obj_begin (void)
18481 /* Check for premature end, nesting errors, etc. */
18483 as_warn (_("missing .end at end of assembly"));
18492 if (*input_line_pointer == '-')
18494 ++input_line_pointer;
18497 if (!ISDIGIT (*input_line_pointer))
18498 as_bad (_("expected simple number"));
18499 if (input_line_pointer[0] == '0')
18501 if (input_line_pointer[1] == 'x')
18503 input_line_pointer += 2;
18504 while (ISXDIGIT (*input_line_pointer))
18507 val |= hex_value (*input_line_pointer++);
18509 return negative ? -val : val;
18513 ++input_line_pointer;
18514 while (ISDIGIT (*input_line_pointer))
18517 val |= *input_line_pointer++ - '0';
18519 return negative ? -val : val;
18522 if (!ISDIGIT (*input_line_pointer))
18524 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18525 *input_line_pointer, *input_line_pointer);
18526 as_warn (_("invalid number"));
18529 while (ISDIGIT (*input_line_pointer))
18532 val += *input_line_pointer++ - '0';
18534 return negative ? -val : val;
18537 /* The .file directive; just like the usual .file directive, but there
18538 is an initial number which is the ECOFF file index. In the non-ECOFF
18539 case .file implies DWARF-2. */
18542 s_mips_file (int x ATTRIBUTE_UNUSED)
18544 static int first_file_directive = 0;
18546 if (ECOFF_DEBUGGING)
18555 filename = dwarf2_directive_file (0);
18557 /* Versions of GCC up to 3.1 start files with a ".file"
18558 directive even for stabs output. Make sure that this
18559 ".file" is handled. Note that you need a version of GCC
18560 after 3.1 in order to support DWARF-2 on MIPS. */
18561 if (filename != NULL && ! first_file_directive)
18563 (void) new_logical_line (filename, -1);
18564 s_app_file_string (filename, 0);
18566 first_file_directive = 1;
18570 /* The .loc directive, implying DWARF-2. */
18573 s_mips_loc (int x ATTRIBUTE_UNUSED)
18575 if (!ECOFF_DEBUGGING)
18576 dwarf2_directive_loc (0);
18579 /* The .end directive. */
18582 s_mips_end (int x ATTRIBUTE_UNUSED)
18586 /* Following functions need their own .frame and .cprestore directives. */
18587 mips_frame_reg_valid = 0;
18588 mips_cprestore_valid = 0;
18590 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18593 demand_empty_rest_of_line ();
18598 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18599 as_warn (_(".end not in text section"));
18603 as_warn (_(".end directive without a preceding .ent directive."));
18604 demand_empty_rest_of_line ();
18610 gas_assert (S_GET_NAME (p));
18611 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18612 as_warn (_(".end symbol does not match .ent symbol."));
18614 if (debug_type == DEBUG_STABS)
18615 stabs_generate_asm_endfunc (S_GET_NAME (p),
18619 as_warn (_(".end directive missing or unknown symbol"));
18622 /* Create an expression to calculate the size of the function. */
18623 if (p && cur_proc_ptr)
18625 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18626 expressionS *exp = xmalloc (sizeof (expressionS));
18629 exp->X_op = O_subtract;
18630 exp->X_add_symbol = symbol_temp_new_now ();
18631 exp->X_op_symbol = p;
18632 exp->X_add_number = 0;
18634 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18637 /* Generate a .pdr section. */
18638 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18640 segT saved_seg = now_seg;
18641 subsegT saved_subseg = now_subseg;
18645 #ifdef md_flush_pending_output
18646 md_flush_pending_output ();
18649 gas_assert (pdr_seg);
18650 subseg_set (pdr_seg, 0);
18652 /* Write the symbol. */
18653 exp.X_op = O_symbol;
18654 exp.X_add_symbol = p;
18655 exp.X_add_number = 0;
18656 emit_expr (&exp, 4);
18658 fragp = frag_more (7 * 4);
18660 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18661 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18662 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18663 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18664 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18665 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18666 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18668 subseg_set (saved_seg, saved_subseg);
18670 #endif /* OBJ_ELF */
18672 cur_proc_ptr = NULL;
18675 /* The .aent and .ent directives. */
18678 s_mips_ent (int aent)
18682 symbolP = get_symbol ();
18683 if (*input_line_pointer == ',')
18684 ++input_line_pointer;
18685 SKIP_WHITESPACE ();
18686 if (ISDIGIT (*input_line_pointer)
18687 || *input_line_pointer == '-')
18690 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18691 as_warn (_(".ent or .aent not in text section."));
18693 if (!aent && cur_proc_ptr)
18694 as_warn (_("missing .end"));
18698 /* This function needs its own .frame and .cprestore directives. */
18699 mips_frame_reg_valid = 0;
18700 mips_cprestore_valid = 0;
18702 cur_proc_ptr = &cur_proc;
18703 memset (cur_proc_ptr, '\0', sizeof (procS));
18705 cur_proc_ptr->func_sym = symbolP;
18709 if (debug_type == DEBUG_STABS)
18710 stabs_generate_asm_func (S_GET_NAME (symbolP),
18711 S_GET_NAME (symbolP));
18714 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18716 demand_empty_rest_of_line ();
18719 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18720 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18721 s_mips_frame is used so that we can set the PDR information correctly.
18722 We can't use the ecoff routines because they make reference to the ecoff
18723 symbol table (in the mdebug section). */
18726 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18729 if (IS_ELF && !ECOFF_DEBUGGING)
18733 if (cur_proc_ptr == (procS *) NULL)
18735 as_warn (_(".frame outside of .ent"));
18736 demand_empty_rest_of_line ();
18740 cur_proc_ptr->frame_reg = tc_get_register (1);
18742 SKIP_WHITESPACE ();
18743 if (*input_line_pointer++ != ','
18744 || get_absolute_expression_and_terminator (&val) != ',')
18746 as_warn (_("Bad .frame directive"));
18747 --input_line_pointer;
18748 demand_empty_rest_of_line ();
18752 cur_proc_ptr->frame_offset = val;
18753 cur_proc_ptr->pc_reg = tc_get_register (0);
18755 demand_empty_rest_of_line ();
18758 #endif /* OBJ_ELF */
18762 /* The .fmask and .mask directives. If the mdebug section is present
18763 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18764 embedded targets, s_mips_mask is used so that we can set the PDR
18765 information correctly. We can't use the ecoff routines because they
18766 make reference to the ecoff symbol table (in the mdebug section). */
18769 s_mips_mask (int reg_type)
18772 if (IS_ELF && !ECOFF_DEBUGGING)
18776 if (cur_proc_ptr == (procS *) NULL)
18778 as_warn (_(".mask/.fmask outside of .ent"));
18779 demand_empty_rest_of_line ();
18783 if (get_absolute_expression_and_terminator (&mask) != ',')
18785 as_warn (_("Bad .mask/.fmask directive"));
18786 --input_line_pointer;
18787 demand_empty_rest_of_line ();
18791 off = get_absolute_expression ();
18793 if (reg_type == 'F')
18795 cur_proc_ptr->fpreg_mask = mask;
18796 cur_proc_ptr->fpreg_offset = off;
18800 cur_proc_ptr->reg_mask = mask;
18801 cur_proc_ptr->reg_offset = off;
18804 demand_empty_rest_of_line ();
18807 #endif /* OBJ_ELF */
18808 s_ignore (reg_type);
18811 /* A table describing all the processors gas knows about. Names are
18812 matched in the order listed.
18814 To ease comparison, please keep this table in the same order as
18815 gcc's mips_cpu_info_table[]. */
18816 static const struct mips_cpu_info mips_cpu_info_table[] =
18818 /* Entries for generic ISAs */
18819 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18820 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18821 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18822 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18823 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18824 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18825 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18826 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18827 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18830 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18831 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18832 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18835 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
18838 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18839 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18840 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18841 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18842 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18843 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18844 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18845 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18846 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18847 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18848 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18849 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
18850 /* ST Microelectronics Loongson 2E and 2F cores */
18851 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18852 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
18855 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18856 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18857 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
18858 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18859 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
18860 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18861 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18862 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18863 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18864 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18865 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18866 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18867 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18868 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18869 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
18872 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18873 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18874 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18875 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18877 /* MIPS 32 Release 2 */
18878 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18879 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18880 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18881 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18882 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18883 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18884 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18885 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18886 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18887 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18888 /* Deprecated forms of the above. */
18889 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18890 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18891 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18892 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18893 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18894 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18895 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18896 /* Deprecated forms of the above. */
18897 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18898 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18899 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18900 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18901 ISA_MIPS32R2, CPU_MIPS32R2 },
18902 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18903 ISA_MIPS32R2, CPU_MIPS32R2 },
18904 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18905 ISA_MIPS32R2, CPU_MIPS32R2 },
18906 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18907 ISA_MIPS32R2, CPU_MIPS32R2 },
18908 /* Deprecated forms of the above. */
18909 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18910 ISA_MIPS32R2, CPU_MIPS32R2 },
18911 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18912 ISA_MIPS32R2, CPU_MIPS32R2 },
18913 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18914 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18915 ISA_MIPS32R2, CPU_MIPS32R2 },
18916 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18917 ISA_MIPS32R2, CPU_MIPS32R2 },
18918 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18919 ISA_MIPS32R2, CPU_MIPS32R2 },
18920 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18921 ISA_MIPS32R2, CPU_MIPS32R2 },
18922 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18923 ISA_MIPS32R2, CPU_MIPS32R2 },
18924 /* Deprecated forms of the above. */
18925 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18926 ISA_MIPS32R2, CPU_MIPS32R2 },
18927 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18928 ISA_MIPS32R2, CPU_MIPS32R2 },
18929 /* 1004K cores are multiprocessor versions of the 34K. */
18930 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18931 ISA_MIPS32R2, CPU_MIPS32R2 },
18932 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18933 ISA_MIPS32R2, CPU_MIPS32R2 },
18934 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18935 ISA_MIPS32R2, CPU_MIPS32R2 },
18936 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18937 ISA_MIPS32R2, CPU_MIPS32R2 },
18940 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
18941 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
18942 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18943 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18945 /* Broadcom SB-1 CPU core */
18946 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18947 ISA_MIPS64, CPU_SB1 },
18948 /* Broadcom SB-1A CPU core */
18949 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18950 ISA_MIPS64, CPU_SB1 },
18952 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
18954 /* MIPS 64 Release 2 */
18956 /* Cavium Networks Octeon CPU core */
18957 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
18960 { "xlr", 0, ISA_MIPS64, CPU_XLR },
18967 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18968 with a final "000" replaced by "k". Ignore case.
18970 Note: this function is shared between GCC and GAS. */
18973 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18975 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18976 given++, canonical++;
18978 return ((*given == 0 && *canonical == 0)
18979 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18983 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18984 CPU name. We've traditionally allowed a lot of variation here.
18986 Note: this function is shared between GCC and GAS. */
18989 mips_matching_cpu_name_p (const char *canonical, const char *given)
18991 /* First see if the name matches exactly, or with a final "000"
18992 turned into "k". */
18993 if (mips_strict_matching_cpu_name_p (canonical, given))
18996 /* If not, try comparing based on numerical designation alone.
18997 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18998 if (TOLOWER (*given) == 'r')
19000 if (!ISDIGIT (*given))
19003 /* Skip over some well-known prefixes in the canonical name,
19004 hoping to find a number there too. */
19005 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19007 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19009 else if (TOLOWER (canonical[0]) == 'r')
19012 return mips_strict_matching_cpu_name_p (canonical, given);
19016 /* Parse an option that takes the name of a processor as its argument.
19017 OPTION is the name of the option and CPU_STRING is the argument.
19018 Return the corresponding processor enumeration if the CPU_STRING is
19019 recognized, otherwise report an error and return null.
19021 A similar function exists in GCC. */
19023 static const struct mips_cpu_info *
19024 mips_parse_cpu (const char *option, const char *cpu_string)
19026 const struct mips_cpu_info *p;
19028 /* 'from-abi' selects the most compatible architecture for the given
19029 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19030 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19031 version. Look first at the -mgp options, if given, otherwise base
19032 the choice on MIPS_DEFAULT_64BIT.
19034 Treat NO_ABI like the EABIs. One reason to do this is that the
19035 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19036 architecture. This code picks MIPS I for 'mips' and MIPS III for
19037 'mips64', just as we did in the days before 'from-abi'. */
19038 if (strcasecmp (cpu_string, "from-abi") == 0)
19040 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19041 return mips_cpu_info_from_isa (ISA_MIPS1);
19043 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19044 return mips_cpu_info_from_isa (ISA_MIPS3);
19046 if (file_mips_gp32 >= 0)
19047 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19049 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19054 /* 'default' has traditionally been a no-op. Probably not very useful. */
19055 if (strcasecmp (cpu_string, "default") == 0)
19058 for (p = mips_cpu_info_table; p->name != 0; p++)
19059 if (mips_matching_cpu_name_p (p->name, cpu_string))
19062 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19066 /* Return the canonical processor information for ISA (a member of the
19067 ISA_MIPS* enumeration). */
19069 static const struct mips_cpu_info *
19070 mips_cpu_info_from_isa (int isa)
19074 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19075 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19076 && isa == mips_cpu_info_table[i].isa)
19077 return (&mips_cpu_info_table[i]);
19082 static const struct mips_cpu_info *
19083 mips_cpu_info_from_arch (int arch)
19087 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19088 if (arch == mips_cpu_info_table[i].cpu)
19089 return (&mips_cpu_info_table[i]);
19095 show (FILE *stream, const char *string, int *col_p, int *first_p)
19099 fprintf (stream, "%24s", "");
19104 fprintf (stream, ", ");
19108 if (*col_p + strlen (string) > 72)
19110 fprintf (stream, "\n%24s", "");
19114 fprintf (stream, "%s", string);
19115 *col_p += strlen (string);
19121 md_show_usage (FILE *stream)
19126 fprintf (stream, _("\
19128 -EB generate big endian output\n\
19129 -EL generate little endian output\n\
19130 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19131 -G NUM allow referencing objects up to NUM bytes\n\
19132 implicitly with the gp register [default 8]\n"));
19133 fprintf (stream, _("\
19134 -mips1 generate MIPS ISA I instructions\n\
19135 -mips2 generate MIPS ISA II instructions\n\
19136 -mips3 generate MIPS ISA III instructions\n\
19137 -mips4 generate MIPS ISA IV instructions\n\
19138 -mips5 generate MIPS ISA V instructions\n\
19139 -mips32 generate MIPS32 ISA instructions\n\
19140 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19141 -mips64 generate MIPS64 ISA instructions\n\
19142 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19143 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19147 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19148 show (stream, mips_cpu_info_table[i].name, &column, &first);
19149 show (stream, "from-abi", &column, &first);
19150 fputc ('\n', stream);
19152 fprintf (stream, _("\
19153 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19154 -no-mCPU don't generate code specific to CPU.\n\
19155 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19159 show (stream, "3900", &column, &first);
19160 show (stream, "4010", &column, &first);
19161 show (stream, "4100", &column, &first);
19162 show (stream, "4650", &column, &first);
19163 fputc ('\n', stream);
19165 fprintf (stream, _("\
19166 -mips16 generate mips16 instructions\n\
19167 -no-mips16 do not generate mips16 instructions\n"));
19168 fprintf (stream, _("\
19169 -mmicromips generate microMIPS instructions\n\
19170 -mno-micromips do not generate microMIPS instructions\n"));
19171 fprintf (stream, _("\
19172 -msmartmips generate smartmips instructions\n\
19173 -mno-smartmips do not generate smartmips instructions\n"));
19174 fprintf (stream, _("\
19175 -mdsp generate DSP instructions\n\
19176 -mno-dsp do not generate DSP instructions\n"));
19177 fprintf (stream, _("\
19178 -mdspr2 generate DSP R2 instructions\n\
19179 -mno-dspr2 do not generate DSP R2 instructions\n"));
19180 fprintf (stream, _("\
19181 -mmt generate MT instructions\n\
19182 -mno-mt do not generate MT instructions\n"));
19183 fprintf (stream, _("\
19184 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19185 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19186 -mfix-vr4120 work around certain VR4120 errata\n\
19187 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19188 -mfix-24k insert a nop after ERET and DERET instructions\n\
19189 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19190 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19191 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19192 -msym32 assume all symbols have 32-bit values\n\
19193 -O0 remove unneeded NOPs, do not swap branches\n\
19194 -O remove unneeded NOPs and swap branches\n\
19195 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19196 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19197 fprintf (stream, _("\
19198 -mhard-float allow floating-point instructions\n\
19199 -msoft-float do not allow floating-point instructions\n\
19200 -msingle-float only allow 32-bit floating-point operations\n\
19201 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19202 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19205 fprintf (stream, _("\
19206 -KPIC, -call_shared generate SVR4 position independent code\n\
19207 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19208 -mvxworks-pic generate VxWorks position independent code\n\
19209 -non_shared do not generate code that can operate with DSOs\n\
19210 -xgot assume a 32 bit GOT\n\
19211 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19212 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19213 position dependent (non shared) code\n\
19214 -mabi=ABI create ABI conformant object file for:\n"));
19218 show (stream, "32", &column, &first);
19219 show (stream, "o64", &column, &first);
19220 show (stream, "n32", &column, &first);
19221 show (stream, "64", &column, &first);
19222 show (stream, "eabi", &column, &first);
19224 fputc ('\n', stream);
19226 fprintf (stream, _("\
19227 -32 create o32 ABI object file (default)\n\
19228 -n32 create n32 ABI object file\n\
19229 -64 create 64 ABI object file\n"));
19235 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19237 if (HAVE_64BIT_SYMBOLS)
19238 return dwarf2_format_64bit_irix;
19240 return dwarf2_format_32bit;
19245 mips_dwarf2_addr_size (void)
19247 if (HAVE_64BIT_OBJECTS)
19253 /* Standard calling conventions leave the CFA at SP on entry. */
19255 mips_cfi_frame_initial_instructions (void)
19257 cfi_add_CFA_def_cfa_register (SP);
19261 tc_mips_regname_to_dw2regnum (char *regname)
19263 unsigned int regnum = -1;
19266 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))