1 /* Common target dependent code for GDB on ARM systems.
3 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose.
86 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
87 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
89 #define MSYMBOL_SET_SPECIAL(msym) \
90 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
93 #define MSYMBOL_IS_SPECIAL(msym) \
94 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
96 /* The list of available "set arm ..." and "show arm ..." commands. */
97 static struct cmd_list_element *setarmcmdlist = NULL;
98 static struct cmd_list_element *showarmcmdlist = NULL;
100 /* The type of floating-point to use. Keep this in sync with enum
101 arm_float_model, and the help string in _initialize_arm_tdep. */
102 static const char *fp_model_strings[] =
111 /* A variable that can be configured by the user. */
112 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
113 static const char *current_fp_model = "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options;
118 /* We have more registers than the disassembler as gdb can print the value
119 of special registers as well.
120 The general register names are overwritten by whatever is being used by
121 the disassembler at the moment. We also adjust the case of cpsr and fps. */
123 /* Initial value: Register names used in ARM's ISA documentation. */
124 static char * arm_register_name_strings[] =
125 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
126 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
127 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
128 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
129 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
130 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
131 "fps", "cpsr" }; /* 24 25 */
132 static char **arm_register_names = arm_register_name_strings;
134 /* Valid register name styles. */
135 static const char **valid_disassembly_styles;
137 /* Disassembly style to use. Default to "std" register names. */
138 static const char *disassembly_style;
139 /* Index to that option in the opcodes table. */
140 static int current_option;
142 /* This is used to keep the bfd arch_info in sync with the disassembly
144 static void set_disassembly_style_sfunc(char *, int,
145 struct cmd_list_element *);
146 static void set_disassembly_style (void);
148 static void convert_from_extended (const struct floatformat *, const void *,
150 static void convert_to_extended (const struct floatformat *, void *,
153 struct arm_prologue_cache
155 /* The stack pointer at the time this frame was created; i.e. the
156 caller's stack pointer when this function was called. It is used
157 to identify this frame. */
160 /* The frame base for this frame is just prev_sp + frame offset -
161 frame size. FRAMESIZE is the size of this stack frame, and
162 FRAMEOFFSET if the initial offset from the stack pointer (this
163 frame's stack pointer, not PREV_SP) to the frame base. */
168 /* The register used to hold the frame pointer for this frame. */
171 /* Saved register offsets. */
172 struct trad_frame_saved_reg *saved_regs;
175 /* Addresses for calling Thumb functions have the bit 0 set.
176 Here are some macros to test, set, or clear bit 0 of addresses. */
177 #define IS_THUMB_ADDR(addr) ((addr) & 1)
178 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
179 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
181 /* Set to true if the 32-bit mode is in use. */
185 /* Flag set by arm_fix_call_dummy that tells whether the target
186 function is a Thumb function. This flag is checked by
187 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
188 its use in valops.c) to pass the function address as an additional
191 static int target_is_thumb;
193 /* Flag set by arm_fix_call_dummy that tells whether the calling
194 function is a Thumb function. This flag is checked by
197 static int caller_is_thumb;
199 /* Determine if the program counter specified in MEMADDR is in a Thumb
203 arm_pc_is_thumb (CORE_ADDR memaddr)
205 struct minimal_symbol *sym;
207 /* If bit 0 of the address is set, assume this is a Thumb address. */
208 if (IS_THUMB_ADDR (memaddr))
211 /* Thumb functions have a "special" bit set in minimal symbols. */
212 sym = lookup_minimal_symbol_by_pc (memaddr);
215 return (MSYMBOL_IS_SPECIAL (sym));
223 /* Determine if the program counter specified in MEMADDR is in a call
224 dummy being called from a Thumb function. */
227 arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
229 CORE_ADDR sp = read_sp ();
231 /* FIXME: Until we switch for the new call dummy macros, this heuristic
232 is the best we can do. We are trying to determine if the pc is on
233 the stack, which (hopefully) will only happen in a call dummy.
234 We hope the current stack pointer is not so far alway from the dummy
235 frame location (true if we have not pushed large data structures or
236 gone too many levels deep) and that our 1024 is not enough to consider
237 code regions as part of the stack (true for most practical purposes). */
238 if (deprecated_pc_in_call_dummy (memaddr))
239 return caller_is_thumb;
244 /* Remove useless bits from addresses in a running program. */
246 arm_addr_bits_remove (CORE_ADDR val)
249 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
251 return (val & 0x03fffffc);
254 /* When reading symbols, we need to zap the low bit of the address,
255 which may be set to 1 for Thumb functions. */
257 arm_smash_text_address (CORE_ADDR val)
262 /* Immediately after a function call, return the saved pc. Can't
263 always go through the frames for this because on some machines the
264 new frame is not set up until the new function executes some
268 arm_saved_pc_after_call (struct frame_info *frame)
270 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
273 /* A typical Thumb prologue looks like this:
277 Sometimes the latter instruction may be replaced by:
285 or, on tpcs, like this:
292 There is always one instruction of three classes:
297 When we have found at least one of each class we are done with the prolog.
298 Note that the "sub sp, #NN" before the push does not count.
302 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
304 CORE_ADDR current_pc;
306 bit 0 - push { rlist }
307 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
308 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
312 for (current_pc = pc;
313 current_pc + 2 < func_end && current_pc < pc + 40;
316 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
318 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
320 findmask |= 1; /* push found */
322 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
325 if ((findmask & 1) == 0) /* before push ? */
328 findmask |= 4; /* add/sub sp found */
330 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
332 findmask |= 2; /* setting of r7 found */
334 else if (insn == 0x466f) /* mov r7, sp */
336 findmask |= 2; /* setting of r7 found */
338 else if (findmask == (4+2+1))
340 /* We have found one of each type of prologue instruction */
344 /* Something in the prolog that we don't care about or some
345 instruction from outside the prolog scheduled here for
353 /* Advance the PC across any function entry prologue instructions to
354 reach some "real" code.
356 The APCS (ARM Procedure Call Standard) defines the following
360 [stmfd sp!, {a1,a2,a3,a4}]
361 stmfd sp!, {...,fp,ip,lr,pc}
362 [stfe f7, [sp, #-12]!]
363 [stfe f6, [sp, #-12]!]
364 [stfe f5, [sp, #-12]!]
365 [stfe f4, [sp, #-12]!]
366 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
369 arm_skip_prologue (CORE_ADDR pc)
373 CORE_ADDR func_addr, func_end = 0;
375 struct symtab_and_line sal;
377 /* If we're in a dummy frame, don't even try to skip the prologue. */
378 if (deprecated_pc_in_call_dummy (pc))
381 /* See what the symbol table says. */
383 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
387 /* Found a function. */
388 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
389 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
391 /* Don't use this trick for assembly source files. */
392 sal = find_pc_line (func_addr, 0);
393 if ((sal.line != 0) && (sal.end < func_end))
398 /* Check if this is Thumb code. */
399 if (arm_pc_is_thumb (pc))
400 return thumb_skip_prologue (pc, func_end);
402 /* Can't find the prologue end in the symbol table, try it the hard way
403 by disassembling the instructions. */
405 /* Like arm_scan_prologue, stop no later than pc + 64. */
406 if (func_end == 0 || func_end > pc + 64)
409 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
411 inst = read_memory_integer (skip_pc, 4);
413 /* "mov ip, sp" is no longer a required part of the prologue. */
414 if (inst == 0xe1a0c00d) /* mov ip, sp */
417 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
420 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
423 /* Some prologues begin with "str lr, [sp, #-4]!". */
424 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
427 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
430 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
433 /* Any insns after this point may float into the code, if it makes
434 for better instruction scheduling, so we skip them only if we
435 find them, but still consider the function to be frame-ful. */
437 /* We may have either one sfmfd instruction here, or several stfe
438 insns, depending on the version of floating point code we
440 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
443 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
446 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
449 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
452 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
453 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
454 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
457 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
458 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
459 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
462 /* Un-recognized instruction; stop scanning. */
466 return skip_pc; /* End of prologue */
470 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
471 This function decodes a Thumb function prologue to determine:
472 1) the size of the stack frame
473 2) which registers are saved on it
474 3) the offsets of saved regs
475 4) the offset from the stack pointer to the frame pointer
477 A typical Thumb function prologue would create this stack frame
478 (offsets relative to FP)
479 old SP -> 24 stack parameters
482 R7 -> 0 local variables (16 bytes)
483 SP -> -12 additional stack space (12 bytes)
484 The frame size would thus be 36 bytes, and the frame offset would be
485 12 bytes. The frame register is R7.
487 The comments for thumb_skip_prolog() describe the algorithm we use
488 to detect the end of the prolog. */
492 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
494 CORE_ADDR prologue_start;
495 CORE_ADDR prologue_end;
496 CORE_ADDR current_pc;
497 /* Which register has been copied to register n? */
500 bit 0 - push { rlist }
501 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
502 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
507 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
509 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
511 if (sal.line == 0) /* no line info, use current PC */
512 prologue_end = prev_pc;
513 else if (sal.end < prologue_end) /* next line begins after fn end */
514 prologue_end = sal.end; /* (probably means no prologue) */
517 /* We're in the boondocks: allow for
518 16 pushes, an add, and "mv fp,sp". */
519 prologue_end = prologue_start + 40;
521 prologue_end = min (prologue_end, prev_pc);
523 /* Initialize the saved register map. When register H is copied to
524 register L, we will put H in saved_reg[L]. */
525 for (i = 0; i < 16; i++)
528 /* Search the prologue looking for instructions that set up the
529 frame pointer, adjust the stack pointer, and save registers.
530 Do this until all basic prolog instructions are found. */
532 cache->framesize = 0;
533 for (current_pc = prologue_start;
534 (current_pc < prologue_end) && ((findmask & 7) != 7);
541 insn = read_memory_unsigned_integer (current_pc, 2);
543 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
546 findmask |= 1; /* push found */
547 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
548 whether to save LR (R14). */
549 mask = (insn & 0xff) | ((insn & 0x100) << 6);
551 /* Calculate offsets of saved R0-R7 and LR. */
552 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
553 if (mask & (1 << regno))
555 cache->framesize += 4;
556 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
557 /* Reset saved register map. */
558 saved_reg[regno] = regno;
561 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
564 if ((findmask & 1) == 0) /* before push? */
567 findmask |= 4; /* add/sub sp found */
569 offset = (insn & 0x7f) << 2; /* get scaled offset */
570 if (insn & 0x80) /* is it signed? (==subtracting) */
572 cache->frameoffset += offset;
575 cache->framesize -= offset;
577 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
579 findmask |= 2; /* setting of r7 found */
580 cache->framereg = THUMB_FP_REGNUM;
581 /* get scaled offset */
582 cache->frameoffset = (insn & 0xff) << 2;
584 else if (insn == 0x466f) /* mov r7, sp */
586 findmask |= 2; /* setting of r7 found */
587 cache->framereg = THUMB_FP_REGNUM;
588 cache->frameoffset = 0;
589 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
591 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
593 int lo_reg = insn & 7; /* dest. register (r0-r7) */
594 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
595 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
598 /* Something in the prolog that we don't care about or some
599 instruction from outside the prolog scheduled here for
605 /* This function decodes an ARM function prologue to determine:
606 1) the size of the stack frame
607 2) which registers are saved on it
608 3) the offsets of saved regs
609 4) the offset from the stack pointer to the frame pointer
610 This information is stored in the "extra" fields of the frame_info.
612 There are two basic forms for the ARM prologue. The fixed argument
613 function call will look like:
616 stmfd sp!, {fp, ip, lr, pc}
620 Which would create this stack frame (offsets relative to FP):
621 IP -> 4 (caller's stack)
622 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
623 -4 LR (return address in caller)
624 -8 IP (copy of caller's SP)
626 SP -> -28 Local variables
628 The frame size would thus be 32 bytes, and the frame offset would be
629 28 bytes. The stmfd call can also save any of the vN registers it
630 plans to use, which increases the frame size accordingly.
632 Note: The stored PC is 8 off of the STMFD instruction that stored it
633 because the ARM Store instructions always store PC + 8 when you read
636 A variable argument function call will look like:
639 stmfd sp!, {a1, a2, a3, a4}
640 stmfd sp!, {fp, ip, lr, pc}
643 Which would create this stack frame (offsets relative to FP):
644 IP -> 20 (caller's stack)
649 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
650 -4 LR (return address in caller)
651 -8 IP (copy of caller's SP)
653 SP -> -28 Local variables
655 The frame size would thus be 48 bytes, and the frame offset would be
658 There is another potential complication, which is that the optimizer
659 will try to separate the store of fp in the "stmfd" instruction from
660 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
661 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
663 Also, note, the original version of the ARM toolchain claimed that there
666 instruction at the end of the prologue. I have never seen GCC produce
667 this, and the ARM docs don't mention it. We still test for it below in
673 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
675 int regno, sp_offset, fp_offset, ip_offset;
676 CORE_ADDR prologue_start, prologue_end, current_pc;
677 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
679 /* Assume there is no frame until proven otherwise. */
680 cache->framereg = ARM_SP_REGNUM;
681 cache->framesize = 0;
682 cache->frameoffset = 0;
684 /* Check for Thumb prologue. */
685 if (arm_pc_is_thumb (prev_pc))
687 thumb_scan_prologue (prev_pc, cache);
691 /* Find the function prologue. If we can't find the function in
692 the symbol table, peek in the stack frame to find the PC. */
693 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
695 /* One way to find the end of the prologue (which works well
696 for unoptimized code) is to do the following:
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
701 prologue_end = prev_pc;
702 else if (sal.end < prologue_end)
703 prologue_end = sal.end;
705 This mechanism is very accurate so long as the optimizer
706 doesn't move any instructions from the function body into the
707 prologue. If this happens, sal.end will be the last
708 instruction in the first hunk of prologue code just before
709 the first instruction that the scheduler has moved from
710 the body to the prologue.
712 In order to make sure that we scan all of the prologue
713 instructions, we use a slightly less accurate mechanism which
714 may scan more than necessary. To help compensate for this
715 lack of accuracy, the prologue scanning loop below contains
716 several clauses which'll cause the loop to terminate early if
717 an implausible prologue instruction is encountered.
723 is a suitable endpoint since it accounts for the largest
724 possible prologue plus up to five instructions inserted by
727 if (prologue_end > prologue_start + 64)
729 prologue_end = prologue_start + 64; /* See above. */
734 /* We have no symbol information. Our only option is to assume this
735 function has a standard stack frame and the normal frame register.
736 Then, we can find the value of our frame pointer on entrance to
737 the callee (or at the present moment if this is the innermost frame).
738 The value stored there should be the address of the stmfd + 8. */
740 LONGEST return_value;
742 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
743 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
747 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
748 prologue_end = prologue_start + 64; /* See above. */
752 if (prev_pc < prologue_end)
753 prologue_end = prev_pc;
755 /* Now search the prologue looking for instructions that set up the
756 frame pointer, adjust the stack pointer, and save registers.
758 Be careful, however, and if it doesn't look like a prologue,
759 don't try to scan it. If, for instance, a frameless function
760 begins with stmfd sp!, then we will tell ourselves there is
761 a frame, which will confuse stack traceback, as well as "finish"
762 and other operations that rely on a knowledge of the stack
765 In the APCS, the prologue should start with "mov ip, sp" so
766 if we don't see this as the first insn, we will stop.
768 [Note: This doesn't seem to be true any longer, so it's now an
769 optional part of the prologue. - Kevin Buettner, 2001-11-20]
771 [Note further: The "mov ip,sp" only seems to be missing in
772 frameless functions at optimization level "-O2" or above,
773 in which case it is often (but not always) replaced by
774 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
776 sp_offset = fp_offset = ip_offset = 0;
778 for (current_pc = prologue_start;
779 current_pc < prologue_end;
782 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
784 if (insn == 0xe1a0c00d) /* mov ip, sp */
789 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
791 unsigned imm = insn & 0xff; /* immediate value */
792 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
793 imm = (imm >> rot) | (imm << (32 - rot));
797 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
799 unsigned imm = insn & 0xff; /* immediate value */
800 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
801 imm = (imm >> rot) | (imm << (32 - rot));
805 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
808 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
811 else if ((insn & 0xffff0000) == 0xe92d0000)
812 /* stmfd sp!, {..., fp, ip, lr, pc}
814 stmfd sp!, {a1, a2, a3, a4} */
816 int mask = insn & 0xffff;
818 /* Calculate offsets of saved registers. */
819 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
820 if (mask & (1 << regno))
823 cache->saved_regs[regno].addr = sp_offset;
826 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
827 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
828 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
830 /* No need to add this to saved_regs -- it's just an arg reg. */
833 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
834 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
835 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
837 /* No need to add this to saved_regs -- it's just an arg reg. */
840 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
842 unsigned imm = insn & 0xff; /* immediate value */
843 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
844 imm = (imm >> rot) | (imm << (32 - rot));
845 fp_offset = -imm + ip_offset;
846 cache->framereg = ARM_FP_REGNUM;
848 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
850 unsigned imm = insn & 0xff; /* immediate value */
851 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
852 imm = (imm >> rot) | (imm << (32 - rot));
855 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
858 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
859 cache->saved_regs[regno].addr = sp_offset;
861 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
864 unsigned int fp_start_reg, fp_bound_reg;
866 if ((insn & 0x800) == 0x800) /* N0 is set */
868 if ((insn & 0x40000) == 0x40000) /* N1 is set */
875 if ((insn & 0x40000) == 0x40000) /* N1 is set */
881 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
882 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
883 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
886 cache->saved_regs[fp_start_reg++].addr = sp_offset;
889 else if ((insn & 0xf0000000) != 0xe0000000)
890 break; /* Condition not true, exit early */
891 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
892 break; /* Don't scan past a block load */
894 /* The optimizer might shove anything into the prologue,
895 so we just skip what we don't recognize. */
899 /* The frame size is just the negative of the offset (from the
900 original SP) of the last thing thing we pushed on the stack.
901 The frame offset is [new FP] - [new SP]. */
902 cache->framesize = -sp_offset;
903 if (cache->framereg == ARM_FP_REGNUM)
904 cache->frameoffset = fp_offset - sp_offset;
906 cache->frameoffset = 0;
909 static struct arm_prologue_cache *
910 arm_make_prologue_cache (struct frame_info *next_frame)
913 struct arm_prologue_cache *cache;
914 CORE_ADDR unwound_fp;
916 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
917 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
919 arm_scan_prologue (next_frame, cache);
921 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
925 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
927 /* Calculate actual addresses of saved registers using offsets
928 determined by arm_scan_prologue. */
929 for (reg = 0; reg < NUM_REGS; reg++)
930 if (trad_frame_addr_p (cache->saved_regs, reg))
931 cache->saved_regs[reg].addr += cache->prev_sp;
936 /* Our frame ID for a normal frame is the current function's starting PC
937 and the caller's SP when we were called. */
940 arm_prologue_this_id (struct frame_info *next_frame,
942 struct frame_id *this_id)
944 struct arm_prologue_cache *cache;
948 if (*this_cache == NULL)
949 *this_cache = arm_make_prologue_cache (next_frame);
952 func = frame_func_unwind (next_frame);
954 /* This is meant to halt the backtrace at "_start". Make sure we
955 don't halt it at a generic dummy frame. */
956 if (func <= LOWEST_PC)
959 /* If we've hit a wall, stop. */
960 if (cache->prev_sp == 0)
963 id = frame_id_build (cache->prev_sp, func);
968 arm_prologue_prev_register (struct frame_info *next_frame,
972 enum lval_type *lvalp,
977 struct arm_prologue_cache *cache;
979 if (*this_cache == NULL)
980 *this_cache = arm_make_prologue_cache (next_frame);
983 /* If we are asked to unwind the PC, then we need to return the LR
984 instead. The saved value of PC points into this frame's
985 prologue, not the next frame's resume location. */
986 if (prev_regnum == ARM_PC_REGNUM)
987 prev_regnum = ARM_LR_REGNUM;
989 /* SP is generally not saved to the stack, but this frame is
990 identified by NEXT_FRAME's stack pointer at the time of the call.
991 The value was already reconstructed into PREV_SP. */
992 if (prev_regnum == ARM_SP_REGNUM)
996 store_unsigned_integer (valuep, 4, cache->prev_sp);
1000 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
1001 optimized, lvalp, addrp, realnump, valuep);
1004 struct frame_unwind arm_prologue_unwind = {
1006 arm_prologue_this_id,
1007 arm_prologue_prev_register
1010 static const struct frame_unwind *
1011 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
1013 return &arm_prologue_unwind;
1016 static struct arm_prologue_cache *
1017 arm_make_stub_cache (struct frame_info *next_frame)
1020 struct arm_prologue_cache *cache;
1021 CORE_ADDR unwound_fp;
1023 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
1024 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1026 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1031 /* Our frame ID for a stub frame is the current SP and LR. */
1034 arm_stub_this_id (struct frame_info *next_frame,
1036 struct frame_id *this_id)
1038 struct arm_prologue_cache *cache;
1040 if (*this_cache == NULL)
1041 *this_cache = arm_make_stub_cache (next_frame);
1042 cache = *this_cache;
1044 *this_id = frame_id_build (cache->prev_sp,
1045 frame_pc_unwind (next_frame));
1048 struct frame_unwind arm_stub_unwind = {
1051 arm_prologue_prev_register
1054 static const struct frame_unwind *
1055 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1059 if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL)
1060 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1061 return &arm_stub_unwind;
1067 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1069 struct arm_prologue_cache *cache;
1071 if (*this_cache == NULL)
1072 *this_cache = arm_make_prologue_cache (next_frame);
1073 cache = *this_cache;
1075 return cache->prev_sp + cache->frameoffset - cache->framesize;
1078 struct frame_base arm_normal_base = {
1079 &arm_prologue_unwind,
1080 arm_normal_frame_base,
1081 arm_normal_frame_base,
1082 arm_normal_frame_base
1085 static struct arm_prologue_cache *
1086 arm_make_sigtramp_cache (struct frame_info *next_frame)
1088 struct arm_prologue_cache *cache;
1091 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
1093 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1095 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1097 for (reg = 0; reg < NUM_REGS; reg++)
1098 cache->saved_regs[reg].addr
1099 = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp,
1100 frame_pc_unwind (next_frame), reg);
1102 /* FIXME: What about thumb mode? */
1103 cache->framereg = ARM_SP_REGNUM;
1105 = read_memory_integer (cache->saved_regs[cache->framereg].addr,
1106 register_size (current_gdbarch, cache->framereg));
1112 arm_sigtramp_this_id (struct frame_info *next_frame,
1114 struct frame_id *this_id)
1116 struct arm_prologue_cache *cache;
1118 if (*this_cache == NULL)
1119 *this_cache = arm_make_sigtramp_cache (next_frame);
1120 cache = *this_cache;
1122 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1123 the sigtramp frame; the PC should be the beginning of the trampoline. */
1124 *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame));
1128 arm_sigtramp_prev_register (struct frame_info *next_frame,
1132 enum lval_type *lvalp,
1137 struct arm_prologue_cache *cache;
1139 if (*this_cache == NULL)
1140 *this_cache = arm_make_sigtramp_cache (next_frame);
1141 cache = *this_cache;
1143 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
1144 optimized, lvalp, addrp, realnump, valuep);
1147 struct frame_unwind arm_sigtramp_unwind = {
1149 arm_sigtramp_this_id,
1150 arm_sigtramp_prev_register
1153 static const struct frame_unwind *
1154 arm_sigtramp_unwind_sniffer (struct frame_info *next_frame)
1156 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1157 && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0))
1158 return &arm_sigtramp_unwind;
1163 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1164 dummy frame. The frame ID's base needs to match the TOS value
1165 saved by save_dummy_frame_tos() and returned from
1166 arm_push_dummy_call, and the PC needs to match the dummy frame's
1169 static struct frame_id
1170 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1172 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1173 frame_pc_unwind (next_frame));
1176 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1177 be used to construct the previous frame's ID, after looking up the
1178 containing function). */
1181 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1184 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1185 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1189 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1191 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1194 /* When arguments must be pushed onto the stack, they go on in reverse
1195 order. The code below implements a FILO (stack) to do this. */
1200 struct stack_item *prev;
1204 static struct stack_item *
1205 push_stack_item (struct stack_item *prev, void *contents, int len)
1207 struct stack_item *si;
1208 si = xmalloc (sizeof (struct stack_item));
1209 si->data = xmalloc (len);
1212 memcpy (si->data, contents, len);
1216 static struct stack_item *
1217 pop_stack_item (struct stack_item *si)
1219 struct stack_item *dead = si;
1226 /* We currently only support passing parameters in integer registers. This
1227 conforms with GCC's default model. Several other variants exist and
1228 we should probably support some of them based on the selected ABI. */
1231 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1232 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1233 struct value **args, CORE_ADDR sp, int struct_return,
1234 CORE_ADDR struct_addr)
1239 struct stack_item *si = NULL;
1241 /* Set the return address. For the ARM, the return breakpoint is
1242 always at BP_ADDR. */
1243 /* XXX Fix for Thumb. */
1244 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1246 /* Walk through the list of args and determine how large a temporary
1247 stack is required. Need to take care here as structs may be
1248 passed on the stack, and we have to to push them. */
1251 argreg = ARM_A1_REGNUM;
1254 /* Some platforms require a double-word aligned stack. Make sure sp
1255 is correctly aligned before we start. We always do this even if
1256 it isn't really needed -- it can never hurt things. */
1257 sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1);
1259 /* The struct_return pointer occupies the first parameter
1260 passing register. */
1264 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1265 REGISTER_NAME (argreg), paddr (struct_addr));
1266 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1270 for (argnum = 0; argnum < nargs; argnum++)
1273 struct type *arg_type;
1274 struct type *target_type;
1275 enum type_code typecode;
1278 arg_type = check_typedef (value_type (args[argnum]));
1279 len = TYPE_LENGTH (arg_type);
1280 target_type = TYPE_TARGET_TYPE (arg_type);
1281 typecode = TYPE_CODE (arg_type);
1282 val = value_contents_writeable (args[argnum]);
1284 /* If the argument is a pointer to a function, and it is a
1285 Thumb function, create a LOCAL copy of the value and set
1286 the THUMB bit in it. */
1287 if (TYPE_CODE_PTR == typecode
1288 && target_type != NULL
1289 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1291 CORE_ADDR regval = extract_unsigned_integer (val, len);
1292 if (arm_pc_is_thumb (regval))
1295 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1299 /* Copy the argument to general registers or the stack in
1300 register-sized pieces. Large arguments are split between
1301 registers and stack. */
1304 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1306 if (argreg <= ARM_LAST_ARG_REGNUM)
1308 /* The argument is being passed in a general purpose
1310 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1312 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1313 argnum, REGISTER_NAME (argreg),
1314 phex (regval, DEPRECATED_REGISTER_SIZE));
1315 regcache_cooked_write_unsigned (regcache, argreg, regval);
1320 /* Push the arguments onto the stack. */
1322 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1324 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1325 nstack += DEPRECATED_REGISTER_SIZE;
1332 /* If we have an odd number of words to push, then decrement the stack
1333 by one word now, so first stack argument will be dword aligned. */
1340 write_memory (sp, si->data, si->len);
1341 si = pop_stack_item (si);
1344 /* Finally, update teh SP register. */
1345 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1351 print_fpu_flags (int flags)
1353 if (flags & (1 << 0))
1354 fputs ("IVO ", stdout);
1355 if (flags & (1 << 1))
1356 fputs ("DVZ ", stdout);
1357 if (flags & (1 << 2))
1358 fputs ("OFL ", stdout);
1359 if (flags & (1 << 3))
1360 fputs ("UFL ", stdout);
1361 if (flags & (1 << 4))
1362 fputs ("INX ", stdout);
1366 /* Print interesting information about the floating point processor
1367 (if present) or emulator. */
1369 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1370 struct frame_info *frame, const char *args)
1372 unsigned long status = read_register (ARM_FPS_REGNUM);
1375 type = (status >> 24) & 127;
1376 if (status & (1 << 31))
1377 printf (_("Hardware FPU type %d\n"), type);
1379 printf (_("Software FPU type %d\n"), type);
1380 /* i18n: [floating point unit] mask */
1381 fputs (_("mask: "), stdout);
1382 print_fpu_flags (status >> 16);
1383 /* i18n: [floating point unit] flags */
1384 fputs (_("flags: "), stdout);
1385 print_fpu_flags (status);
1388 /* Return the GDB type object for the "standard" data type of data in
1391 static struct type *
1392 arm_register_type (struct gdbarch *gdbarch, int regnum)
1394 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1396 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1397 return builtin_type_arm_ext_big;
1399 return builtin_type_arm_ext_littlebyte_bigword;
1402 return builtin_type_int32;
1405 /* Index within `registers' of the first byte of the space for
1409 arm_register_byte (int regnum)
1411 if (regnum < ARM_F0_REGNUM)
1412 return regnum * INT_REGISTER_SIZE;
1413 else if (regnum < ARM_PS_REGNUM)
1414 return (NUM_GREGS * INT_REGISTER_SIZE
1415 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1417 return (NUM_GREGS * INT_REGISTER_SIZE
1418 + NUM_FREGS * FP_REGISTER_SIZE
1419 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1422 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1424 arm_register_sim_regno (int regnum)
1427 gdb_assert (reg >= 0 && reg < NUM_REGS);
1429 if (reg < NUM_GREGS)
1430 return SIM_ARM_R0_REGNUM + reg;
1433 if (reg < NUM_FREGS)
1434 return SIM_ARM_FP0_REGNUM + reg;
1437 if (reg < NUM_SREGS)
1438 return SIM_ARM_FPS_REGNUM + reg;
1441 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1444 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1445 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1446 It is thought that this is is the floating-point register format on
1447 little-endian systems. */
1450 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1454 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1455 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1457 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1459 floatformat_from_doublest (fmt, &d, dbl);
1463 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1466 floatformat_to_doublest (fmt, ptr, &d);
1467 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1468 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1470 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1475 condition_true (unsigned long cond, unsigned long status_reg)
1477 if (cond == INST_AL || cond == INST_NV)
1483 return ((status_reg & FLAG_Z) != 0);
1485 return ((status_reg & FLAG_Z) == 0);
1487 return ((status_reg & FLAG_C) != 0);
1489 return ((status_reg & FLAG_C) == 0);
1491 return ((status_reg & FLAG_N) != 0);
1493 return ((status_reg & FLAG_N) == 0);
1495 return ((status_reg & FLAG_V) != 0);
1497 return ((status_reg & FLAG_V) == 0);
1499 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1501 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1503 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1505 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1507 return (((status_reg & FLAG_Z) == 0) &&
1508 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1510 return (((status_reg & FLAG_Z) != 0) ||
1511 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1516 /* Support routines for single stepping. Calculate the next PC value. */
1517 #define submask(x) ((1L << ((x) + 1)) - 1)
1518 #define bit(obj,st) (((obj) >> (st)) & 1)
1519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1520 #define sbits(obj,st,fn) \
1521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1522 #define BranchDest(addr,instr) \
1523 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1526 static unsigned long
1527 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1528 unsigned long status_reg)
1530 unsigned long res, shift;
1531 int rm = bits (inst, 0, 3);
1532 unsigned long shifttype = bits (inst, 5, 6);
1536 int rs = bits (inst, 8, 11);
1537 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1540 shift = bits (inst, 7, 11);
1543 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1544 + (bit (inst, 4) ? 12 : 8))
1545 : read_register (rm));
1550 res = shift >= 32 ? 0 : res << shift;
1554 res = shift >= 32 ? 0 : res >> shift;
1560 res = ((res & 0x80000000L)
1561 ? ~((~res) >> shift) : res >> shift);
1564 case 3: /* ROR/RRX */
1567 res = (res >> 1) | (carry ? 0x80000000L : 0);
1569 res = (res >> shift) | (res << (32 - shift));
1573 return res & 0xffffffff;
1576 /* Return number of 1-bits in VAL. */
1579 bitcount (unsigned long val)
1582 for (nbits = 0; val != 0; nbits++)
1583 val &= val - 1; /* delete rightmost 1-bit in val */
1588 thumb_get_next_pc (CORE_ADDR pc)
1590 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1591 unsigned short inst1 = read_memory_integer (pc, 2);
1592 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1593 unsigned long offset;
1595 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1599 /* Fetch the saved PC from the stack. It's stored above
1600 all of the other registers. */
1601 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1602 sp = read_register (ARM_SP_REGNUM);
1603 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1604 nextpc = ADDR_BITS_REMOVE (nextpc);
1606 error (_("Infinite loop detected"));
1608 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1610 unsigned long status = read_register (ARM_PS_REGNUM);
1611 unsigned long cond = bits (inst1, 8, 11);
1612 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1613 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1615 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1617 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1619 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1621 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1622 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1623 nextpc = pc_val + offset;
1624 /* For BLX make sure to clear the low bits. */
1625 if (bits (inst2, 11, 12) == 1)
1626 nextpc = nextpc & 0xfffffffc;
1628 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1630 if (bits (inst1, 3, 6) == 0x0f)
1633 nextpc = read_register (bits (inst1, 3, 6));
1635 nextpc = ADDR_BITS_REMOVE (nextpc);
1637 error (_("Infinite loop detected"));
1644 arm_get_next_pc (CORE_ADDR pc)
1646 unsigned long pc_val;
1647 unsigned long this_instr;
1648 unsigned long status;
1651 if (arm_pc_is_thumb (pc))
1652 return thumb_get_next_pc (pc);
1654 pc_val = (unsigned long) pc;
1655 this_instr = read_memory_integer (pc, 4);
1656 status = read_register (ARM_PS_REGNUM);
1657 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1659 if (condition_true (bits (this_instr, 28, 31), status))
1661 switch (bits (this_instr, 24, 27))
1664 case 0x1: /* data processing */
1668 unsigned long operand1, operand2, result = 0;
1672 if (bits (this_instr, 12, 15) != 15)
1675 if (bits (this_instr, 22, 25) == 0
1676 && bits (this_instr, 4, 7) == 9) /* multiply */
1677 error (_("Invalid update to pc in instruction"));
1679 /* BX <reg>, BLX <reg> */
1680 if (bits (this_instr, 4, 28) == 0x12fff1
1681 || bits (this_instr, 4, 28) == 0x12fff3)
1683 rn = bits (this_instr, 0, 3);
1684 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1685 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1688 error (_("Infinite loop detected"));
1693 /* Multiply into PC */
1694 c = (status & FLAG_C) ? 1 : 0;
1695 rn = bits (this_instr, 16, 19);
1696 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1698 if (bit (this_instr, 25))
1700 unsigned long immval = bits (this_instr, 0, 7);
1701 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1702 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1705 else /* operand 2 is a shifted register */
1706 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1708 switch (bits (this_instr, 21, 24))
1711 result = operand1 & operand2;
1715 result = operand1 ^ operand2;
1719 result = operand1 - operand2;
1723 result = operand2 - operand1;
1727 result = operand1 + operand2;
1731 result = operand1 + operand2 + c;
1735 result = operand1 - operand2 + c;
1739 result = operand2 - operand1 + c;
1745 case 0xb: /* tst, teq, cmp, cmn */
1746 result = (unsigned long) nextpc;
1750 result = operand1 | operand2;
1754 /* Always step into a function. */
1759 result = operand1 & ~operand2;
1766 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1769 error (_("Infinite loop detected"));
1774 case 0x5: /* data transfer */
1777 if (bit (this_instr, 20))
1780 if (bits (this_instr, 12, 15) == 15)
1786 if (bit (this_instr, 22))
1787 error (_("Invalid update to pc in instruction"));
1789 /* byte write to PC */
1790 rn = bits (this_instr, 16, 19);
1791 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1792 if (bit (this_instr, 24))
1795 int c = (status & FLAG_C) ? 1 : 0;
1796 unsigned long offset =
1797 (bit (this_instr, 25)
1798 ? shifted_reg_val (this_instr, c, pc_val, status)
1799 : bits (this_instr, 0, 11));
1801 if (bit (this_instr, 23))
1806 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1809 nextpc = ADDR_BITS_REMOVE (nextpc);
1812 error (_("Infinite loop detected"));
1818 case 0x9: /* block transfer */
1819 if (bit (this_instr, 20))
1822 if (bit (this_instr, 15))
1827 if (bit (this_instr, 23))
1830 unsigned long reglist = bits (this_instr, 0, 14);
1831 offset = bitcount (reglist) * 4;
1832 if (bit (this_instr, 24)) /* pre */
1835 else if (bit (this_instr, 24))
1839 unsigned long rn_val =
1840 read_register (bits (this_instr, 16, 19));
1842 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1846 nextpc = ADDR_BITS_REMOVE (nextpc);
1848 error (_("Infinite loop detected"));
1853 case 0xb: /* branch & link */
1854 case 0xa: /* branch */
1856 nextpc = BranchDest (pc, this_instr);
1859 if (bits (this_instr, 28, 31) == INST_NV)
1860 nextpc |= bit (this_instr, 24) << 1;
1862 nextpc = ADDR_BITS_REMOVE (nextpc);
1864 error (_("Infinite loop detected"));
1870 case 0xe: /* coproc ops */
1875 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1883 /* single_step() is called just before we want to resume the inferior,
1884 if we want to single-step it but there is no hardware or kernel
1885 single-step support. We find the target of the coming instruction
1888 single_step() is also called just after the inferior stops. If we
1889 had set up a simulated single-step, we undo our damage. */
1892 arm_software_single_step (enum target_signal sig, int insert_bpt)
1894 static int next_pc; /* State between setting and unsetting. */
1895 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
1899 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1900 target_insert_breakpoint (next_pc, break_mem);
1903 target_remove_breakpoint (next_pc, break_mem);
1906 #include "bfd-in2.h"
1907 #include "libcoff.h"
1910 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1912 if (arm_pc_is_thumb (memaddr))
1914 static asymbol *asym;
1915 static combined_entry_type ce;
1916 static struct coff_symbol_struct csym;
1917 static struct bfd fake_bfd;
1918 static bfd_target fake_target;
1920 if (csym.native == NULL)
1922 /* Create a fake symbol vector containing a Thumb symbol.
1923 This is solely so that the code in print_insn_little_arm()
1924 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1925 the presence of a Thumb symbol and switch to decoding
1926 Thumb instructions. */
1928 fake_target.flavour = bfd_target_coff_flavour;
1929 fake_bfd.xvec = &fake_target;
1930 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1932 csym.symbol.the_bfd = &fake_bfd;
1933 csym.symbol.name = "fake";
1934 asym = (asymbol *) & csym;
1937 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1938 info->symbols = &asym;
1941 info->symbols = NULL;
1943 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1944 return print_insn_big_arm (memaddr, info);
1946 return print_insn_little_arm (memaddr, info);
1949 /* The following define instruction sequences that will cause ARM
1950 cpu's to take an undefined instruction trap. These are used to
1951 signal a breakpoint to GDB.
1953 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1954 modes. A different instruction is required for each mode. The ARM
1955 cpu's can also be big or little endian. Thus four different
1956 instructions are needed to support all cases.
1958 Note: ARMv4 defines several new instructions that will take the
1959 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1960 not in fact add the new instructions. The new undefined
1961 instructions in ARMv4 are all instructions that had no defined
1962 behaviour in earlier chips. There is no guarantee that they will
1963 raise an exception, but may be treated as NOP's. In practice, it
1964 may only safe to rely on instructions matching:
1966 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1967 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1968 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1970 Even this may only true if the condition predicate is true. The
1971 following use a condition predicate of ALWAYS so it is always TRUE.
1973 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1974 and NetBSD all use a software interrupt rather than an undefined
1975 instruction to force a trap. This can be handled by by the
1976 abi-specific code during establishment of the gdbarch vector. */
1979 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1980 override these definitions. */
1981 #ifndef ARM_LE_BREAKPOINT
1982 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1984 #ifndef ARM_BE_BREAKPOINT
1985 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1987 #ifndef THUMB_LE_BREAKPOINT
1988 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1990 #ifndef THUMB_BE_BREAKPOINT
1991 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1994 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1995 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1996 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1997 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1999 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2000 the program counter value to determine whether a 16-bit or 32-bit
2001 breakpoint should be used. It returns a pointer to a string of
2002 bytes that encode a breakpoint instruction, stores the length of
2003 the string to *lenptr, and adjusts the program counter (if
2004 necessary) to point to the actual memory location where the
2005 breakpoint should be inserted. */
2007 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2008 breakpoints and storing their handles instread of what was in
2009 memory. It is nice that this is the same size as a handle -
2010 otherwise remote-rdp will have to change. */
2012 static const unsigned char *
2013 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2015 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2017 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
2019 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2020 *lenptr = tdep->thumb_breakpoint_size;
2021 return tdep->thumb_breakpoint;
2025 *lenptr = tdep->arm_breakpoint_size;
2026 return tdep->arm_breakpoint;
2030 /* Extract from an array REGBUF containing the (raw) register state a
2031 function return value of type TYPE, and copy that, in virtual
2032 format, into VALBUF. */
2035 arm_extract_return_value (struct type *type,
2036 struct regcache *regs,
2039 bfd_byte *valbuf = dst;
2041 if (TYPE_CODE_FLT == TYPE_CODE (type))
2043 switch (arm_get_fp_model (current_gdbarch))
2047 /* The value is in register F0 in internal format. We need to
2048 extract the raw value and then convert it to the desired
2050 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2052 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2053 convert_from_extended (floatformat_from_type (type), tmpbuf,
2058 case ARM_FLOAT_SOFT_FPA:
2059 case ARM_FLOAT_SOFT_VFP:
2060 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2061 if (TYPE_LENGTH (type) > 4)
2062 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2063 valbuf + INT_REGISTER_SIZE);
2068 (__FILE__, __LINE__,
2069 _("arm_extract_return_value: Floating point model not supported"));
2073 else if (TYPE_CODE (type) == TYPE_CODE_INT
2074 || TYPE_CODE (type) == TYPE_CODE_CHAR
2075 || TYPE_CODE (type) == TYPE_CODE_BOOL
2076 || TYPE_CODE (type) == TYPE_CODE_PTR
2077 || TYPE_CODE (type) == TYPE_CODE_REF
2078 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2080 /* If the the type is a plain integer, then the access is
2081 straight-forward. Otherwise we have to play around a bit more. */
2082 int len = TYPE_LENGTH (type);
2083 int regno = ARM_A1_REGNUM;
2088 /* By using store_unsigned_integer we avoid having to do
2089 anything special for small big-endian values. */
2090 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2091 store_unsigned_integer (valbuf,
2092 (len > INT_REGISTER_SIZE
2093 ? INT_REGISTER_SIZE : len),
2095 len -= INT_REGISTER_SIZE;
2096 valbuf += INT_REGISTER_SIZE;
2101 /* For a structure or union the behaviour is as if the value had
2102 been stored to word-aligned memory and then loaded into
2103 registers with 32-bit load instruction(s). */
2104 int len = TYPE_LENGTH (type);
2105 int regno = ARM_A1_REGNUM;
2106 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2110 regcache_cooked_read (regs, regno++, tmpbuf);
2111 memcpy (valbuf, tmpbuf,
2112 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2113 len -= INT_REGISTER_SIZE;
2114 valbuf += INT_REGISTER_SIZE;
2119 /* Extract from an array REGBUF containing the (raw) register state
2120 the address in which a function should return its structure value. */
2123 arm_extract_struct_value_address (struct regcache *regcache)
2127 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2131 /* Will a function return an aggregate type in memory or in a
2132 register? Return 0 if an aggregate type can be returned in a
2133 register, 1 if it must be returned in memory. */
2136 arm_use_struct_convention (int gcc_p, struct type *type)
2139 enum type_code code;
2141 CHECK_TYPEDEF (type);
2143 /* In the ARM ABI, "integer" like aggregate types are returned in
2144 registers. For an aggregate type to be integer like, its size
2145 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2146 offset of each addressable subfield must be zero. Note that bit
2147 fields are not addressable, and all addressable subfields of
2148 unions always start at offset zero.
2150 This function is based on the behaviour of GCC 2.95.1.
2151 See: gcc/arm.c: arm_return_in_memory() for details.
2153 Note: All versions of GCC before GCC 2.95.2 do not set up the
2154 parameters correctly for a function returning the following
2155 structure: struct { float f;}; This should be returned in memory,
2156 not a register. Richard Earnshaw sent me a patch, but I do not
2157 know of any way to detect if a function like the above has been
2158 compiled with the correct calling convention. */
2160 /* All aggregate types that won't fit in a register must be returned
2162 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2167 /* The only aggregate types that can be returned in a register are
2168 structs and unions. Arrays must be returned in memory. */
2169 code = TYPE_CODE (type);
2170 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2175 /* Assume all other aggregate types can be returned in a register.
2176 Run a check for structures, unions and arrays. */
2179 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2182 /* Need to check if this struct/union is "integer" like. For
2183 this to be true, its size must be less than or equal to
2184 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2185 subfield must be zero. Note that bit fields are not
2186 addressable, and unions always start at offset zero. If any
2187 of the subfields is a floating point type, the struct/union
2188 cannot be an integer type. */
2190 /* For each field in the object, check:
2191 1) Is it FP? --> yes, nRc = 1;
2192 2) Is it addressable (bitpos != 0) and
2193 not packed (bitsize == 0)?
2197 for (i = 0; i < TYPE_NFIELDS (type); i++)
2199 enum type_code field_type_code;
2200 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2202 /* Is it a floating point type field? */
2203 if (field_type_code == TYPE_CODE_FLT)
2209 /* If bitpos != 0, then we have to care about it. */
2210 if (TYPE_FIELD_BITPOS (type, i) != 0)
2212 /* Bitfields are not addressable. If the field bitsize is
2213 zero, then the field is not packed. Hence it cannot be
2214 a bitfield or any other packed type. */
2215 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2227 /* Write into appropriate registers a function return value of type
2228 TYPE, given in virtual format. */
2231 arm_store_return_value (struct type *type, struct regcache *regs,
2234 const bfd_byte *valbuf = src;
2236 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2238 char buf[MAX_REGISTER_SIZE];
2240 switch (arm_get_fp_model (current_gdbarch))
2244 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2245 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2248 case ARM_FLOAT_SOFT_FPA:
2249 case ARM_FLOAT_SOFT_VFP:
2250 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2251 if (TYPE_LENGTH (type) > 4)
2252 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2253 valbuf + INT_REGISTER_SIZE);
2258 (__FILE__, __LINE__,
2259 _("arm_store_return_value: Floating point model not supported"));
2263 else if (TYPE_CODE (type) == TYPE_CODE_INT
2264 || TYPE_CODE (type) == TYPE_CODE_CHAR
2265 || TYPE_CODE (type) == TYPE_CODE_BOOL
2266 || TYPE_CODE (type) == TYPE_CODE_PTR
2267 || TYPE_CODE (type) == TYPE_CODE_REF
2268 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2270 if (TYPE_LENGTH (type) <= 4)
2272 /* Values of one word or less are zero/sign-extended and
2274 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2275 LONGEST val = unpack_long (type, valbuf);
2277 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2278 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2282 /* Integral values greater than one word are stored in consecutive
2283 registers starting with r0. This will always be a multiple of
2284 the regiser size. */
2285 int len = TYPE_LENGTH (type);
2286 int regno = ARM_A1_REGNUM;
2290 regcache_cooked_write (regs, regno++, valbuf);
2291 len -= INT_REGISTER_SIZE;
2292 valbuf += INT_REGISTER_SIZE;
2298 /* For a structure or union the behaviour is as if the value had
2299 been stored to word-aligned memory and then loaded into
2300 registers with 32-bit load instruction(s). */
2301 int len = TYPE_LENGTH (type);
2302 int regno = ARM_A1_REGNUM;
2303 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2307 memcpy (tmpbuf, valbuf,
2308 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2309 regcache_cooked_write (regs, regno++, tmpbuf);
2310 len -= INT_REGISTER_SIZE;
2311 valbuf += INT_REGISTER_SIZE;
2317 arm_get_longjmp_target (CORE_ADDR *pc)
2320 char buf[INT_REGISTER_SIZE];
2321 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2323 jb_addr = read_register (ARM_A1_REGNUM);
2325 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2329 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2333 /* Return non-zero if the PC is inside a thumb call thunk. */
2336 arm_in_call_stub (CORE_ADDR pc, char *name)
2338 CORE_ADDR start_addr;
2340 /* Find the starting address of the function containing the PC. If
2341 the caller didn't give us a name, look it up at the same time. */
2342 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2346 return strncmp (name, "_call_via_r", 11) == 0;
2349 /* If PC is in a Thumb call or return stub, return the address of the
2350 target PC, which is in a register. The thunk functions are called
2351 _called_via_xx, where x is the register name. The possible names
2352 are r0-r9, sl, fp, ip, sp, and lr. */
2355 arm_skip_stub (CORE_ADDR pc)
2358 CORE_ADDR start_addr;
2360 /* Find the starting address and name of the function containing the PC. */
2361 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2364 /* Call thunks always start with "_call_via_". */
2365 if (strncmp (name, "_call_via_", 10) == 0)
2367 /* Use the name suffix to determine which register contains the
2369 static char *table[15] =
2370 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2371 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2375 for (regno = 0; regno <= 14; regno++)
2376 if (strcmp (&name[10], table[regno]) == 0)
2377 return read_register (regno);
2380 return 0; /* not a stub */
2384 set_arm_command (char *args, int from_tty)
2386 printf_unfiltered (_("\
2387 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2388 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2392 show_arm_command (char *args, int from_tty)
2394 cmd_show_list (showarmcmdlist, from_tty, "");
2397 enum arm_float_model
2398 arm_get_fp_model (struct gdbarch *gdbarch)
2400 if (arm_fp_model == ARM_FLOAT_AUTO)
2401 return gdbarch_tdep (gdbarch)->fp_model;
2403 return arm_fp_model;
2407 arm_set_fp (struct gdbarch *gdbarch)
2409 enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
2411 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2412 && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
2414 set_gdbarch_double_format (gdbarch,
2415 &floatformat_ieee_double_littlebyte_bigword);
2416 set_gdbarch_long_double_format
2417 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2421 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2422 set_gdbarch_long_double_format (gdbarch,
2423 &floatformat_ieee_double_little);
2428 set_fp_model_sfunc (char *args, int from_tty,
2429 struct cmd_list_element *c)
2431 enum arm_float_model fp_model;
2433 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2434 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2436 arm_fp_model = fp_model;
2440 if (fp_model == ARM_FLOAT_LAST)
2441 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2444 if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2445 arm_set_fp (current_gdbarch);
2449 show_fp_model (struct ui_file *file, int from_tty,
2450 struct cmd_list_element *c, const char *value)
2452 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2454 deprecated_show_value_hack (file, from_tty, c, value);
2455 if (arm_fp_model == ARM_FLOAT_AUTO
2456 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2457 /* i18n: "the default [floating point model] for the current ABI..." */
2458 printf_filtered (_(" - the default for the current ABI is \"%s\".\n"),
2459 fp_model_strings[tdep->fp_model]);
2462 /* If the user changes the register disassembly style used for info
2463 register and other commands, we have to also switch the style used
2464 in opcodes for disassembly output. This function is run in the "set
2465 arm disassembly" command, and does that. */
2468 set_disassembly_style_sfunc (char *args, int from_tty,
2469 struct cmd_list_element *c)
2471 set_disassembly_style ();
2474 /* Return the ARM register name corresponding to register I. */
2476 arm_register_name (int i)
2478 return arm_register_names[i];
2482 set_disassembly_style (void)
2484 const char *setname, *setdesc, **regnames;
2487 /* Find the style that the user wants in the opcodes table. */
2489 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2490 while ((disassembly_style != setname)
2491 && (current < num_disassembly_options))
2492 get_arm_regnames (++current, &setname, &setdesc, ®names);
2493 current_option = current;
2495 /* Fill our copy. */
2496 for (j = 0; j < numregs; j++)
2497 arm_register_names[j] = (char *) regnames[j];
2500 if (isupper (*regnames[ARM_PC_REGNUM]))
2502 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2503 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2507 arm_register_names[ARM_FPS_REGNUM] = "fps";
2508 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2511 /* Synchronize the disassembler. */
2512 set_arm_regname_option (current);
2515 /* Test whether the coff symbol specific value corresponds to a Thumb
2519 coff_sym_is_thumb (int val)
2521 return (val == C_THUMBEXT ||
2522 val == C_THUMBSTAT ||
2523 val == C_THUMBEXTFUNC ||
2524 val == C_THUMBSTATFUNC ||
2525 val == C_THUMBLABEL);
2528 /* arm_coff_make_msymbol_special()
2529 arm_elf_make_msymbol_special()
2531 These functions test whether the COFF or ELF symbol corresponds to
2532 an address in thumb code, and set a "special" bit in a minimal
2533 symbol to indicate that it does. */
2536 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2538 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2540 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2542 MSYMBOL_SET_SPECIAL (msym);
2546 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2548 if (coff_sym_is_thumb (val))
2549 MSYMBOL_SET_SPECIAL (msym);
2553 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2555 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2557 /* If necessary, set the T bit. */
2560 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2561 if (arm_pc_is_thumb (pc))
2562 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2564 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2568 static enum gdb_osabi
2569 arm_elf_osabi_sniffer (bfd *abfd)
2571 unsigned int elfosabi, eflags;
2572 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2574 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2579 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2580 file are conforming to the base specification for that machine
2581 (there are no OS-specific extensions). In order to determine the
2582 real OS in use we must look for OS notes that have been added. */
2583 bfd_map_over_sections (abfd,
2584 generic_elf_osabi_sniff_abi_tag_sections,
2586 if (osabi == GDB_OSABI_UNKNOWN)
2588 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2589 field for more information. */
2590 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2593 case EF_ARM_EABI_VER1:
2594 osabi = GDB_OSABI_ARM_EABI_V1;
2597 case EF_ARM_EABI_VER2:
2598 osabi = GDB_OSABI_ARM_EABI_V2;
2601 case EF_ARM_EABI_UNKNOWN:
2602 /* Assume GNU tools. */
2603 osabi = GDB_OSABI_ARM_APCS;
2607 internal_error (__FILE__, __LINE__,
2609 arm_elf_osabi_sniffer: Unknown ARM EABI version 0x%x"),
2616 /* GNU tools use this value. Check note sections in this case,
2618 bfd_map_over_sections (abfd,
2619 generic_elf_osabi_sniff_abi_tag_sections,
2621 if (osabi == GDB_OSABI_UNKNOWN)
2623 /* Assume APCS ABI. */
2624 osabi = GDB_OSABI_ARM_APCS;
2628 case ELFOSABI_FREEBSD:
2629 osabi = GDB_OSABI_FREEBSD_ELF;
2632 case ELFOSABI_NETBSD:
2633 osabi = GDB_OSABI_NETBSD_ELF;
2636 case ELFOSABI_LINUX:
2637 osabi = GDB_OSABI_LINUX;
2645 /* Initialize the current architecture based on INFO. If possible,
2646 re-use an architecture from ARCHES, which is a list of
2647 architectures already created during this debugging session.
2649 Called e.g. at program startup, when reading a core file, and when
2650 reading a binary file. */
2652 static struct gdbarch *
2653 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2655 struct gdbarch_tdep *tdep;
2656 struct gdbarch *gdbarch;
2658 /* Try to deterimine the ABI of the object we are loading. */
2660 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
2662 switch (bfd_get_flavour (info.abfd))
2664 case bfd_target_aout_flavour:
2665 /* Assume it's an old APCS-style ABI. */
2666 info.osabi = GDB_OSABI_ARM_APCS;
2669 case bfd_target_coff_flavour:
2670 /* Assume it's an old APCS-style ABI. */
2672 info.osabi = GDB_OSABI_ARM_APCS;
2676 /* Leave it as "unknown". */
2681 /* If there is already a candidate, use it. */
2682 arches = gdbarch_list_lookup_by_info (arches, &info);
2684 return arches->gdbarch;
2686 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2687 gdbarch = gdbarch_alloc (&info, tdep);
2689 /* We used to default to FPA for generic ARM, but almost nobody uses that
2690 now, and we now provide a way for the user to force the model. So
2691 default to the most useful variant. */
2692 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
2695 switch (info.byte_order)
2697 case BFD_ENDIAN_BIG:
2698 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2699 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2700 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2701 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2705 case BFD_ENDIAN_LITTLE:
2706 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2707 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2708 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2709 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2714 internal_error (__FILE__, __LINE__,
2715 _("arm_gdbarch_init: bad byte order for float format"));
2718 /* On ARM targets char defaults to unsigned. */
2719 set_gdbarch_char_signed (gdbarch, 0);
2721 /* This should be low enough for everything. */
2722 tdep->lowest_pc = 0x20;
2723 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2725 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2727 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2729 /* Frame handling. */
2730 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2731 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2732 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2734 frame_base_set_default (gdbarch, &arm_normal_base);
2736 /* Address manipulation. */
2737 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2738 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2740 /* Advance PC across function entry code. */
2741 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2743 /* Get the PC when a frame might not be available. */
2744 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2746 /* The stack grows downward. */
2747 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2749 /* Breakpoint manipulation. */
2750 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2752 /* Information about registers, etc. */
2753 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2754 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2755 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2756 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2757 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2758 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2759 set_gdbarch_register_type (gdbarch, arm_register_type);
2761 /* Internal <-> external register number maps. */
2762 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2764 /* Integer registers are 4 bytes. */
2765 set_gdbarch_deprecated_register_size (gdbarch, 4);
2766 set_gdbarch_register_name (gdbarch, arm_register_name);
2768 /* Returning results. */
2769 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2770 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2771 set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention);
2772 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address);
2774 /* Single stepping. */
2775 /* XXX For an RDI target we should ask the target if it can single-step. */
2776 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2779 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2781 /* Minsymbol frobbing. */
2782 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2783 set_gdbarch_coff_make_msymbol_special (gdbarch,
2784 arm_coff_make_msymbol_special);
2786 /* Hook in the ABI-specific overrides, if they have been registered. */
2787 gdbarch_init_osabi (info, gdbarch);
2789 /* Add some default predicates. */
2790 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
2791 frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer);
2792 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2794 /* Now we have tuned the configuration, set a few final things,
2795 based on what the OS ABI has told us. */
2797 if (tdep->jb_pc >= 0)
2798 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2800 /* Floating point sizes and format. */
2801 switch (info.byte_order)
2803 case BFD_ENDIAN_BIG:
2804 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2805 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2806 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2810 case BFD_ENDIAN_LITTLE:
2811 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2812 arm_set_fp (gdbarch);
2816 internal_error (__FILE__, __LINE__,
2817 _("arm_gdbarch_init: bad byte order for float format"));
2824 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2826 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2831 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2832 (unsigned long) tdep->lowest_pc);
2836 arm_init_abi_eabi_v1 (struct gdbarch_info info,
2837 struct gdbarch *gdbarch)
2843 arm_init_abi_eabi_v2 (struct gdbarch_info info,
2844 struct gdbarch *gdbarch)
2850 arm_init_abi_apcs (struct gdbarch_info info,
2851 struct gdbarch *gdbarch)
2856 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2859 _initialize_arm_tdep (void)
2861 struct ui_file *stb;
2863 struct cmd_list_element *new_set, *new_show;
2864 const char *setname;
2865 const char *setdesc;
2866 const char **regnames;
2868 static char *helptext;
2869 char regdesc[1024], *rdptr = regdesc;
2870 size_t rest = sizeof (regdesc);
2872 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2874 /* Register an ELF OS ABI sniffer for ARM binaries. */
2875 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2876 bfd_target_elf_flavour,
2877 arm_elf_osabi_sniffer);
2879 /* Register some ABI variants for embedded systems. */
2880 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
2881 arm_init_abi_eabi_v1);
2882 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
2883 arm_init_abi_eabi_v2);
2884 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
2887 /* Get the number of possible sets of register names defined in opcodes. */
2888 num_disassembly_options = get_arm_regname_num_options ();
2890 /* Add root prefix command for all "set arm"/"show arm" commands. */
2891 add_prefix_cmd ("arm", no_class, set_arm_command,
2892 _("Various ARM-specific commands."),
2893 &setarmcmdlist, "set arm ", 0, &setlist);
2895 add_prefix_cmd ("arm", no_class, show_arm_command,
2896 _("Various ARM-specific commands."),
2897 &showarmcmdlist, "show arm ", 0, &showlist);
2899 /* Sync the opcode insn printer with our register viewer. */
2900 parse_arm_disassembler_option ("reg-names-std");
2902 /* Initialize the array that will be passed to
2903 add_setshow_enum_cmd(). */
2904 valid_disassembly_styles
2905 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2906 for (i = 0; i < num_disassembly_options; i++)
2908 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2909 valid_disassembly_styles[i] = setname;
2910 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
2913 /* Copy the default names (if found) and synchronize disassembler. */
2914 if (!strcmp (setname, "std"))
2916 disassembly_style = setname;
2918 for (j = 0; j < numregs; j++)
2919 arm_register_names[j] = (char *) regnames[j];
2920 set_arm_regname_option (i);
2923 /* Mark the end of valid options. */
2924 valid_disassembly_styles[num_disassembly_options] = NULL;
2926 /* Create the help text. */
2927 stb = mem_fileopen ();
2928 fprintf_unfiltered (stb, "%s%s%s",
2929 _("The valid values are:\n"),
2931 _("The default is \"std\"."));
2932 helptext = ui_file_xstrdup (stb, &length);
2933 ui_file_delete (stb);
2935 add_setshow_enum_cmd("disassembler", no_class,
2936 valid_disassembly_styles, &disassembly_style,
2937 _("Set the disassembly style."),
2938 _("Show the disassembly style."),
2940 set_disassembly_style_sfunc,
2941 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
2942 &setarmcmdlist, &showarmcmdlist);
2944 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2945 _("Set usage of ARM 32-bit mode."),
2946 _("Show usage of ARM 32-bit mode."),
2947 _("When off, a 26-bit PC will be used."),
2949 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2950 &setarmcmdlist, &showarmcmdlist);
2952 /* Add a command to allow the user to force the FPU model. */
2953 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2954 _("Set the floating point type."),
2955 _("Show the floating point type."),
2956 _("auto - Determine the FP typefrom the OS-ABI.\n\
2957 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2958 fpa - FPA co-processor (GCC compiled).\n\
2959 softvfp - Software FP with pure-endian doubles.\n\
2960 vfp - VFP co-processor."),
2961 set_fp_model_sfunc, show_fp_model,
2962 &setarmcmdlist, &showarmcmdlist);
2964 /* Debugging flag. */
2965 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2966 _("Set ARM debugging."),
2967 _("Show ARM debugging."),
2968 _("When on, arm-specific debugging is enabled."),
2970 NULL, /* FIXME: i18n: "ARM debugging is %s. */
2971 &setdebuglist, &showdebuglist);