1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
48 #include "gdb/sim-arm.h"
51 #include "coff/internal.h"
54 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
72 /* The list of available "set arm ..." and "show arm ..." commands. */
73 static struct cmd_list_element *setarmcmdlist = NULL;
74 static struct cmd_list_element *showarmcmdlist = NULL;
76 /* The type of floating-point to use. Keep this in sync with enum
77 arm_float_model, and the help string in _initialize_arm_tdep. */
78 static const char *fp_model_strings[] =
88 /* A variable that can be configured by the user. */
89 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
90 static const char *current_fp_model = "auto";
92 /* The ABI to use. Keep this in sync with arm_abi_kind. */
93 static const char *arm_abi_strings[] =
101 /* A variable that can be configured by the user. */
102 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
103 static const char *arm_abi_string = "auto";
105 /* Number of different reg name sets (options). */
106 static int num_disassembly_options;
108 /* The standard register names, and all the valid aliases for them. */
113 } arm_register_aliases[] = {
114 /* Basic register numbers. */
131 /* Synonyms (argument and variable registers). */
144 /* Other platform-specific names for r9. */
152 /* Names used by GCC (not listed in the ARM EABI). */
155 /* A special name from the older ATPCS. */
159 static const char *const arm_register_names[] =
160 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
161 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
162 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
163 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
164 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
165 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
166 "fps", "cpsr" }; /* 24 25 */
168 /* Valid register name styles. */
169 static const char **valid_disassembly_styles;
171 /* Disassembly style to use. Default to "std" register names. */
172 static const char *disassembly_style;
174 /* This is used to keep the bfd arch_info in sync with the disassembly
176 static void set_disassembly_style_sfunc(char *, int,
177 struct cmd_list_element *);
178 static void set_disassembly_style (void);
180 static void convert_from_extended (const struct floatformat *, const void *,
182 static void convert_to_extended (const struct floatformat *, void *,
185 struct arm_prologue_cache
187 /* The stack pointer at the time this frame was created; i.e. the
188 caller's stack pointer when this function was called. It is used
189 to identify this frame. */
192 /* The frame base for this frame is just prev_sp + frame offset -
193 frame size. FRAMESIZE is the size of this stack frame, and
194 FRAMEOFFSET if the initial offset from the stack pointer (this
195 frame's stack pointer, not PREV_SP) to the frame base. */
200 /* The register used to hold the frame pointer for this frame. */
203 /* Saved register offsets. */
204 struct trad_frame_saved_reg *saved_regs;
207 /* Addresses for calling Thumb functions have the bit 0 set.
208 Here are some macros to test, set, or clear bit 0 of addresses. */
209 #define IS_THUMB_ADDR(addr) ((addr) & 1)
210 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
211 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
213 /* Set to true if the 32-bit mode is in use. */
217 /* Determine if the program counter specified in MEMADDR is in a Thumb
221 arm_pc_is_thumb (CORE_ADDR memaddr)
223 struct minimal_symbol *sym;
225 /* If bit 0 of the address is set, assume this is a Thumb address. */
226 if (IS_THUMB_ADDR (memaddr))
229 /* Thumb functions have a "special" bit set in minimal symbols. */
230 sym = lookup_minimal_symbol_by_pc (memaddr);
233 return (MSYMBOL_IS_SPECIAL (sym));
241 /* Remove useless bits from addresses in a running program. */
243 arm_addr_bits_remove (CORE_ADDR val)
246 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
248 return (val & 0x03fffffc);
251 /* When reading symbols, we need to zap the low bit of the address,
252 which may be set to 1 for Thumb functions. */
254 arm_smash_text_address (CORE_ADDR val)
259 /* Analyze a Thumb prologue, looking for a recognizable stack frame
260 and frame pointer. Scan until we encounter a store that could
261 clobber the stack frame unexpectedly, or an unknown instruction. */
264 thumb_analyze_prologue (struct gdbarch *gdbarch,
265 CORE_ADDR start, CORE_ADDR limit,
266 struct arm_prologue_cache *cache)
270 struct pv_area *stack;
271 struct cleanup *back_to;
274 for (i = 0; i < 16; i++)
275 regs[i] = pv_register (i, 0);
276 stack = make_pv_area (ARM_SP_REGNUM);
277 back_to = make_cleanup_free_pv_area (stack);
279 /* The call instruction saved PC in LR, and the current PC is not
280 interesting. Due to this file's conventions, we want the value
281 of LR at this function's entry, not at the call site, so we do
282 not record the save of the PC - when the ARM prologue analyzer
283 has also been converted to the pv mechanism, we could record the
284 save here and remove the hack in prev_register. */
285 regs[ARM_PC_REGNUM] = pv_unknown ();
287 while (start < limit)
291 insn = read_memory_unsigned_integer (start, 2);
293 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
299 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
300 whether to save LR (R14). */
301 mask = (insn & 0xff) | ((insn & 0x100) << 6);
303 /* Calculate offsets of saved R0-R7 and LR. */
304 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
305 if (mask & (1 << regno))
307 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
313 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
315 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
321 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
324 offset = (insn & 0x7f) << 2; /* get scaled offset */
325 if (insn & 0x80) /* Check for SUB. */
326 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
329 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
332 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
333 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
335 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
337 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
338 int src_reg = (insn & 0x78) >> 3;
339 regs[dst_reg] = regs[src_reg];
341 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
343 /* Handle stores to the stack. Normally pushes are used,
344 but with GCC -mtpcs-frame, there may be other stores
345 in the prologue to create the frame. */
346 int regno = (insn >> 8) & 0x7;
349 offset = (insn & 0xff) << 2;
350 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
352 if (pv_area_store_would_trash (stack, addr))
355 pv_area_store (stack, addr, 4, regs[regno]);
359 /* We don't know what this instruction is. We're finished
360 scanning. NOTE: Recognizing more safe-to-ignore
361 instructions here will improve support for optimized
371 do_cleanups (back_to);
375 /* frameoffset is unused for this unwinder. */
376 cache->frameoffset = 0;
378 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
380 /* Frame pointer is fp. Frame size is constant. */
381 cache->framereg = ARM_FP_REGNUM;
382 cache->framesize = -regs[ARM_FP_REGNUM].k;
384 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
386 /* Frame pointer is r7. Frame size is constant. */
387 cache->framereg = THUMB_FP_REGNUM;
388 cache->framesize = -regs[THUMB_FP_REGNUM].k;
390 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
392 /* Try the stack pointer... this is a bit desperate. */
393 cache->framereg = ARM_SP_REGNUM;
394 cache->framesize = -regs[ARM_SP_REGNUM].k;
398 /* We're just out of luck. We don't know where the frame is. */
399 cache->framereg = -1;
400 cache->framesize = 0;
403 for (i = 0; i < 16; i++)
404 if (pv_area_find_reg (stack, gdbarch, i, &offset))
405 cache->saved_regs[i].addr = offset;
407 do_cleanups (back_to);
411 /* Advance the PC across any function entry prologue instructions to
412 reach some "real" code.
414 The APCS (ARM Procedure Call Standard) defines the following
418 [stmfd sp!, {a1,a2,a3,a4}]
419 stmfd sp!, {...,fp,ip,lr,pc}
420 [stfe f7, [sp, #-12]!]
421 [stfe f6, [sp, #-12]!]
422 [stfe f5, [sp, #-12]!]
423 [stfe f4, [sp, #-12]!]
424 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
427 arm_skip_prologue (CORE_ADDR pc)
431 CORE_ADDR func_addr, func_end = 0;
433 struct symtab_and_line sal;
435 /* If we're in a dummy frame, don't even try to skip the prologue. */
436 if (deprecated_pc_in_call_dummy (pc))
439 /* See what the symbol table says. */
441 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
445 /* Found a function. */
446 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
447 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
449 /* Don't use this trick for assembly source files. */
450 sal = find_pc_line (func_addr, 0);
451 if ((sal.line != 0) && (sal.end < func_end))
456 /* Can't find the prologue end in the symbol table, try it the hard way
457 by disassembling the instructions. */
459 /* Like arm_scan_prologue, stop no later than pc + 64. */
460 if (func_end == 0 || func_end > pc + 64)
463 /* Check if this is Thumb code. */
464 if (arm_pc_is_thumb (pc))
465 return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL);
467 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
469 inst = read_memory_unsigned_integer (skip_pc, 4);
471 /* "mov ip, sp" is no longer a required part of the prologue. */
472 if (inst == 0xe1a0c00d) /* mov ip, sp */
475 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
478 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
481 /* Some prologues begin with "str lr, [sp, #-4]!". */
482 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
485 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
488 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
491 /* Any insns after this point may float into the code, if it makes
492 for better instruction scheduling, so we skip them only if we
493 find them, but still consider the function to be frame-ful. */
495 /* We may have either one sfmfd instruction here, or several stfe
496 insns, depending on the version of floating point code we
498 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
501 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
504 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
507 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
510 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
511 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
512 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
515 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
516 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
517 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
520 /* Un-recognized instruction; stop scanning. */
524 return skip_pc; /* End of prologue */
528 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
529 This function decodes a Thumb function prologue to determine:
530 1) the size of the stack frame
531 2) which registers are saved on it
532 3) the offsets of saved regs
533 4) the offset from the stack pointer to the frame pointer
535 A typical Thumb function prologue would create this stack frame
536 (offsets relative to FP)
537 old SP -> 24 stack parameters
540 R7 -> 0 local variables (16 bytes)
541 SP -> -12 additional stack space (12 bytes)
542 The frame size would thus be 36 bytes, and the frame offset would be
543 12 bytes. The frame register is R7.
545 The comments for thumb_skip_prolog() describe the algorithm we use
546 to detect the end of the prolog. */
550 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
552 CORE_ADDR prologue_start;
553 CORE_ADDR prologue_end;
554 CORE_ADDR current_pc;
555 /* Which register has been copied to register n? */
558 bit 0 - push { rlist }
559 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
560 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
565 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
567 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
569 if (sal.line == 0) /* no line info, use current PC */
570 prologue_end = prev_pc;
571 else if (sal.end < prologue_end) /* next line begins after fn end */
572 prologue_end = sal.end; /* (probably means no prologue) */
575 /* We're in the boondocks: we have no idea where the start of the
579 prologue_end = min (prologue_end, prev_pc);
581 thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end,
585 /* This function decodes an ARM function prologue to determine:
586 1) the size of the stack frame
587 2) which registers are saved on it
588 3) the offsets of saved regs
589 4) the offset from the stack pointer to the frame pointer
590 This information is stored in the "extra" fields of the frame_info.
592 There are two basic forms for the ARM prologue. The fixed argument
593 function call will look like:
596 stmfd sp!, {fp, ip, lr, pc}
600 Which would create this stack frame (offsets relative to FP):
601 IP -> 4 (caller's stack)
602 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
603 -4 LR (return address in caller)
604 -8 IP (copy of caller's SP)
606 SP -> -28 Local variables
608 The frame size would thus be 32 bytes, and the frame offset would be
609 28 bytes. The stmfd call can also save any of the vN registers it
610 plans to use, which increases the frame size accordingly.
612 Note: The stored PC is 8 off of the STMFD instruction that stored it
613 because the ARM Store instructions always store PC + 8 when you read
616 A variable argument function call will look like:
619 stmfd sp!, {a1, a2, a3, a4}
620 stmfd sp!, {fp, ip, lr, pc}
623 Which would create this stack frame (offsets relative to FP):
624 IP -> 20 (caller's stack)
629 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
630 -4 LR (return address in caller)
631 -8 IP (copy of caller's SP)
633 SP -> -28 Local variables
635 The frame size would thus be 48 bytes, and the frame offset would be
638 There is another potential complication, which is that the optimizer
639 will try to separate the store of fp in the "stmfd" instruction from
640 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
641 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
643 Also, note, the original version of the ARM toolchain claimed that there
646 instruction at the end of the prologue. I have never seen GCC produce
647 this, and the ARM docs don't mention it. We still test for it below in
653 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
655 int regno, sp_offset, fp_offset, ip_offset;
656 CORE_ADDR prologue_start, prologue_end, current_pc;
657 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
659 /* Assume there is no frame until proven otherwise. */
660 cache->framereg = ARM_SP_REGNUM;
661 cache->framesize = 0;
662 cache->frameoffset = 0;
664 /* Check for Thumb prologue. */
665 if (arm_pc_is_thumb (prev_pc))
667 thumb_scan_prologue (prev_pc, cache);
671 /* Find the function prologue. If we can't find the function in
672 the symbol table, peek in the stack frame to find the PC. */
673 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
675 /* One way to find the end of the prologue (which works well
676 for unoptimized code) is to do the following:
678 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
681 prologue_end = prev_pc;
682 else if (sal.end < prologue_end)
683 prologue_end = sal.end;
685 This mechanism is very accurate so long as the optimizer
686 doesn't move any instructions from the function body into the
687 prologue. If this happens, sal.end will be the last
688 instruction in the first hunk of prologue code just before
689 the first instruction that the scheduler has moved from
690 the body to the prologue.
692 In order to make sure that we scan all of the prologue
693 instructions, we use a slightly less accurate mechanism which
694 may scan more than necessary. To help compensate for this
695 lack of accuracy, the prologue scanning loop below contains
696 several clauses which'll cause the loop to terminate early if
697 an implausible prologue instruction is encountered.
703 is a suitable endpoint since it accounts for the largest
704 possible prologue plus up to five instructions inserted by
707 if (prologue_end > prologue_start + 64)
709 prologue_end = prologue_start + 64; /* See above. */
714 /* We have no symbol information. Our only option is to assume this
715 function has a standard stack frame and the normal frame register.
716 Then, we can find the value of our frame pointer on entrance to
717 the callee (or at the present moment if this is the innermost frame).
718 The value stored there should be the address of the stmfd + 8. */
720 LONGEST return_value;
722 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
723 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
727 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
728 prologue_end = prologue_start + 64; /* See above. */
732 if (prev_pc < prologue_end)
733 prologue_end = prev_pc;
735 /* Now search the prologue looking for instructions that set up the
736 frame pointer, adjust the stack pointer, and save registers.
738 Be careful, however, and if it doesn't look like a prologue,
739 don't try to scan it. If, for instance, a frameless function
740 begins with stmfd sp!, then we will tell ourselves there is
741 a frame, which will confuse stack traceback, as well as "finish"
742 and other operations that rely on a knowledge of the stack
745 In the APCS, the prologue should start with "mov ip, sp" so
746 if we don't see this as the first insn, we will stop.
748 [Note: This doesn't seem to be true any longer, so it's now an
749 optional part of the prologue. - Kevin Buettner, 2001-11-20]
751 [Note further: The "mov ip,sp" only seems to be missing in
752 frameless functions at optimization level "-O2" or above,
753 in which case it is often (but not always) replaced by
754 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
756 sp_offset = fp_offset = ip_offset = 0;
758 for (current_pc = prologue_start;
759 current_pc < prologue_end;
762 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
764 if (insn == 0xe1a0c00d) /* mov ip, sp */
769 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
771 unsigned imm = insn & 0xff; /* immediate value */
772 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
773 imm = (imm >> rot) | (imm << (32 - rot));
777 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
779 unsigned imm = insn & 0xff; /* immediate value */
780 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
781 imm = (imm >> rot) | (imm << (32 - rot));
785 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
788 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
791 else if ((insn & 0xffff0000) == 0xe92d0000)
792 /* stmfd sp!, {..., fp, ip, lr, pc}
794 stmfd sp!, {a1, a2, a3, a4} */
796 int mask = insn & 0xffff;
798 /* Calculate offsets of saved registers. */
799 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
800 if (mask & (1 << regno))
803 cache->saved_regs[regno].addr = sp_offset;
806 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
807 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
808 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
810 /* No need to add this to saved_regs -- it's just an arg reg. */
813 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
814 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
815 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
817 /* No need to add this to saved_regs -- it's just an arg reg. */
820 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
822 unsigned imm = insn & 0xff; /* immediate value */
823 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
824 imm = (imm >> rot) | (imm << (32 - rot));
825 fp_offset = -imm + ip_offset;
826 cache->framereg = ARM_FP_REGNUM;
828 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
830 unsigned imm = insn & 0xff; /* immediate value */
831 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
832 imm = (imm >> rot) | (imm << (32 - rot));
835 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
838 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
839 cache->saved_regs[regno].addr = sp_offset;
841 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
844 unsigned int fp_start_reg, fp_bound_reg;
846 if ((insn & 0x800) == 0x800) /* N0 is set */
848 if ((insn & 0x40000) == 0x40000) /* N1 is set */
855 if ((insn & 0x40000) == 0x40000) /* N1 is set */
861 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
862 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
863 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
866 cache->saved_regs[fp_start_reg++].addr = sp_offset;
869 else if ((insn & 0xf0000000) != 0xe0000000)
870 break; /* Condition not true, exit early */
871 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
872 break; /* Don't scan past a block load */
874 /* The optimizer might shove anything into the prologue,
875 so we just skip what we don't recognize. */
879 /* The frame size is just the negative of the offset (from the
880 original SP) of the last thing thing we pushed on the stack.
881 The frame offset is [new FP] - [new SP]. */
882 cache->framesize = -sp_offset;
883 if (cache->framereg == ARM_FP_REGNUM)
884 cache->frameoffset = fp_offset - sp_offset;
886 cache->frameoffset = 0;
889 static struct arm_prologue_cache *
890 arm_make_prologue_cache (struct frame_info *next_frame)
893 struct arm_prologue_cache *cache;
894 CORE_ADDR unwound_fp;
896 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
897 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
899 arm_scan_prologue (next_frame, cache);
901 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
905 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
907 /* Calculate actual addresses of saved registers using offsets
908 determined by arm_scan_prologue. */
909 for (reg = 0; reg < NUM_REGS; reg++)
910 if (trad_frame_addr_p (cache->saved_regs, reg))
911 cache->saved_regs[reg].addr += cache->prev_sp;
916 /* Our frame ID for a normal frame is the current function's starting PC
917 and the caller's SP when we were called. */
920 arm_prologue_this_id (struct frame_info *next_frame,
922 struct frame_id *this_id)
924 struct arm_prologue_cache *cache;
928 if (*this_cache == NULL)
929 *this_cache = arm_make_prologue_cache (next_frame);
932 func = frame_func_unwind (next_frame);
934 /* This is meant to halt the backtrace at "_start". Make sure we
935 don't halt it at a generic dummy frame. */
936 if (func <= LOWEST_PC)
939 /* If we've hit a wall, stop. */
940 if (cache->prev_sp == 0)
943 id = frame_id_build (cache->prev_sp, func);
948 arm_prologue_prev_register (struct frame_info *next_frame,
952 enum lval_type *lvalp,
957 struct arm_prologue_cache *cache;
959 if (*this_cache == NULL)
960 *this_cache = arm_make_prologue_cache (next_frame);
963 /* If we are asked to unwind the PC, then we need to return the LR
964 instead. The saved value of PC points into this frame's
965 prologue, not the next frame's resume location. */
966 if (prev_regnum == ARM_PC_REGNUM)
967 prev_regnum = ARM_LR_REGNUM;
969 /* SP is generally not saved to the stack, but this frame is
970 identified by NEXT_FRAME's stack pointer at the time of the call.
971 The value was already reconstructed into PREV_SP. */
972 if (prev_regnum == ARM_SP_REGNUM)
976 store_unsigned_integer (valuep, 4, cache->prev_sp);
980 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
981 optimized, lvalp, addrp, realnump, valuep);
984 struct frame_unwind arm_prologue_unwind = {
986 arm_prologue_this_id,
987 arm_prologue_prev_register
990 static const struct frame_unwind *
991 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
993 return &arm_prologue_unwind;
996 static struct arm_prologue_cache *
997 arm_make_stub_cache (struct frame_info *next_frame)
1000 struct arm_prologue_cache *cache;
1001 CORE_ADDR unwound_fp;
1003 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1004 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1006 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1011 /* Our frame ID for a stub frame is the current SP and LR. */
1014 arm_stub_this_id (struct frame_info *next_frame,
1016 struct frame_id *this_id)
1018 struct arm_prologue_cache *cache;
1020 if (*this_cache == NULL)
1021 *this_cache = arm_make_stub_cache (next_frame);
1022 cache = *this_cache;
1024 *this_id = frame_id_build (cache->prev_sp,
1025 frame_pc_unwind (next_frame));
1028 struct frame_unwind arm_stub_unwind = {
1031 arm_prologue_prev_register
1034 static const struct frame_unwind *
1035 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1039 if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL)
1040 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1041 return &arm_stub_unwind;
1047 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1049 struct arm_prologue_cache *cache;
1051 if (*this_cache == NULL)
1052 *this_cache = arm_make_prologue_cache (next_frame);
1053 cache = *this_cache;
1055 return cache->prev_sp + cache->frameoffset - cache->framesize;
1058 struct frame_base arm_normal_base = {
1059 &arm_prologue_unwind,
1060 arm_normal_frame_base,
1061 arm_normal_frame_base,
1062 arm_normal_frame_base
1065 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1066 dummy frame. The frame ID's base needs to match the TOS value
1067 saved by save_dummy_frame_tos() and returned from
1068 arm_push_dummy_call, and the PC needs to match the dummy frame's
1071 static struct frame_id
1072 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1074 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1075 frame_pc_unwind (next_frame));
1078 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1079 be used to construct the previous frame's ID, after looking up the
1080 containing function). */
1083 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1086 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1087 return arm_addr_bits_remove (pc);
1091 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1093 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1096 /* When arguments must be pushed onto the stack, they go on in reverse
1097 order. The code below implements a FILO (stack) to do this. */
1102 struct stack_item *prev;
1106 static struct stack_item *
1107 push_stack_item (struct stack_item *prev, void *contents, int len)
1109 struct stack_item *si;
1110 si = xmalloc (sizeof (struct stack_item));
1111 si->data = xmalloc (len);
1114 memcpy (si->data, contents, len);
1118 static struct stack_item *
1119 pop_stack_item (struct stack_item *si)
1121 struct stack_item *dead = si;
1129 /* Return the alignment (in bytes) of the given type. */
1132 arm_type_align (struct type *t)
1138 t = check_typedef (t);
1139 switch (TYPE_CODE (t))
1142 /* Should never happen. */
1143 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1147 case TYPE_CODE_ENUM:
1151 case TYPE_CODE_RANGE:
1152 case TYPE_CODE_BITSTRING:
1154 case TYPE_CODE_CHAR:
1155 case TYPE_CODE_BOOL:
1156 return TYPE_LENGTH (t);
1158 case TYPE_CODE_ARRAY:
1159 case TYPE_CODE_COMPLEX:
1160 /* TODO: What about vector types? */
1161 return arm_type_align (TYPE_TARGET_TYPE (t));
1163 case TYPE_CODE_STRUCT:
1164 case TYPE_CODE_UNION:
1166 for (n = 0; n < TYPE_NFIELDS (t); n++)
1168 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1176 /* We currently only support passing parameters in integer registers. This
1177 conforms with GCC's default model. Several other variants exist and
1178 we should probably support some of them based on the selected ABI. */
1181 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1182 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1183 struct value **args, CORE_ADDR sp, int struct_return,
1184 CORE_ADDR struct_addr)
1189 struct stack_item *si = NULL;
1191 /* Set the return address. For the ARM, the return breakpoint is
1192 always at BP_ADDR. */
1193 /* XXX Fix for Thumb. */
1194 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1196 /* Walk through the list of args and determine how large a temporary
1197 stack is required. Need to take care here as structs may be
1198 passed on the stack, and we have to to push them. */
1201 argreg = ARM_A1_REGNUM;
1204 /* The struct_return pointer occupies the first parameter
1205 passing register. */
1209 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1210 REGISTER_NAME (argreg), paddr (struct_addr));
1211 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1215 for (argnum = 0; argnum < nargs; argnum++)
1218 struct type *arg_type;
1219 struct type *target_type;
1220 enum type_code typecode;
1224 arg_type = check_typedef (value_type (args[argnum]));
1225 len = TYPE_LENGTH (arg_type);
1226 target_type = TYPE_TARGET_TYPE (arg_type);
1227 typecode = TYPE_CODE (arg_type);
1228 val = value_contents_writeable (args[argnum]);
1230 align = arm_type_align (arg_type);
1231 /* Round alignment up to a whole number of words. */
1232 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1233 /* Different ABIs have different maximum alignments. */
1234 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1236 /* The APCS ABI only requires word alignment. */
1237 align = INT_REGISTER_SIZE;
1241 /* The AAPCS requires at most doubleword alignment. */
1242 if (align > INT_REGISTER_SIZE * 2)
1243 align = INT_REGISTER_SIZE * 2;
1246 /* Push stack padding for dowubleword alignment. */
1247 if (nstack & (align - 1))
1249 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1250 nstack += INT_REGISTER_SIZE;
1253 /* Doubleword aligned quantities must go in even register pairs. */
1254 if (argreg <= ARM_LAST_ARG_REGNUM
1255 && align > INT_REGISTER_SIZE
1259 /* If the argument is a pointer to a function, and it is a
1260 Thumb function, create a LOCAL copy of the value and set
1261 the THUMB bit in it. */
1262 if (TYPE_CODE_PTR == typecode
1263 && target_type != NULL
1264 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1266 CORE_ADDR regval = extract_unsigned_integer (val, len);
1267 if (arm_pc_is_thumb (regval))
1270 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1274 /* Copy the argument to general registers or the stack in
1275 register-sized pieces. Large arguments are split between
1276 registers and stack. */
1279 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1281 if (argreg <= ARM_LAST_ARG_REGNUM)
1283 /* The argument is being passed in a general purpose
1285 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1287 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1288 argnum, REGISTER_NAME (argreg),
1289 phex (regval, DEPRECATED_REGISTER_SIZE));
1290 regcache_cooked_write_unsigned (regcache, argreg, regval);
1295 /* Push the arguments onto the stack. */
1297 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1299 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1300 nstack += DEPRECATED_REGISTER_SIZE;
1307 /* If we have an odd number of words to push, then decrement the stack
1308 by one word now, so first stack argument will be dword aligned. */
1315 write_memory (sp, si->data, si->len);
1316 si = pop_stack_item (si);
1319 /* Finally, update teh SP register. */
1320 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1326 /* Always align the frame to an 8-byte boundary. This is required on
1327 some platforms and harmless on the rest. */
1330 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1332 /* Align the stack to eight bytes. */
1333 return sp & ~ (CORE_ADDR) 7;
1337 print_fpu_flags (int flags)
1339 if (flags & (1 << 0))
1340 fputs ("IVO ", stdout);
1341 if (flags & (1 << 1))
1342 fputs ("DVZ ", stdout);
1343 if (flags & (1 << 2))
1344 fputs ("OFL ", stdout);
1345 if (flags & (1 << 3))
1346 fputs ("UFL ", stdout);
1347 if (flags & (1 << 4))
1348 fputs ("INX ", stdout);
1352 /* Print interesting information about the floating point processor
1353 (if present) or emulator. */
1355 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1356 struct frame_info *frame, const char *args)
1358 unsigned long status = read_register (ARM_FPS_REGNUM);
1361 type = (status >> 24) & 127;
1362 if (status & (1 << 31))
1363 printf (_("Hardware FPU type %d\n"), type);
1365 printf (_("Software FPU type %d\n"), type);
1366 /* i18n: [floating point unit] mask */
1367 fputs (_("mask: "), stdout);
1368 print_fpu_flags (status >> 16);
1369 /* i18n: [floating point unit] flags */
1370 fputs (_("flags: "), stdout);
1371 print_fpu_flags (status);
1374 /* Return the GDB type object for the "standard" data type of data in
1377 static struct type *
1378 arm_register_type (struct gdbarch *gdbarch, int regnum)
1380 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1381 return builtin_type_arm_ext;
1382 else if (regnum == ARM_SP_REGNUM)
1383 return builtin_type_void_data_ptr;
1384 else if (regnum == ARM_PC_REGNUM)
1385 return builtin_type_void_func_ptr;
1387 return builtin_type_uint32;
1390 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1392 arm_register_sim_regno (int regnum)
1395 gdb_assert (reg >= 0 && reg < NUM_REGS);
1397 if (reg < NUM_GREGS)
1398 return SIM_ARM_R0_REGNUM + reg;
1401 if (reg < NUM_FREGS)
1402 return SIM_ARM_FP0_REGNUM + reg;
1405 if (reg < NUM_SREGS)
1406 return SIM_ARM_FPS_REGNUM + reg;
1409 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1412 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1413 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1414 It is thought that this is is the floating-point register format on
1415 little-endian systems. */
1418 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1422 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1423 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1425 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1427 floatformat_from_doublest (fmt, &d, dbl);
1431 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1434 floatformat_to_doublest (fmt, ptr, &d);
1435 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1436 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1438 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1443 condition_true (unsigned long cond, unsigned long status_reg)
1445 if (cond == INST_AL || cond == INST_NV)
1451 return ((status_reg & FLAG_Z) != 0);
1453 return ((status_reg & FLAG_Z) == 0);
1455 return ((status_reg & FLAG_C) != 0);
1457 return ((status_reg & FLAG_C) == 0);
1459 return ((status_reg & FLAG_N) != 0);
1461 return ((status_reg & FLAG_N) == 0);
1463 return ((status_reg & FLAG_V) != 0);
1465 return ((status_reg & FLAG_V) == 0);
1467 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1469 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1471 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1473 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1475 return (((status_reg & FLAG_Z) == 0) &&
1476 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1478 return (((status_reg & FLAG_Z) != 0) ||
1479 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1484 /* Support routines for single stepping. Calculate the next PC value. */
1485 #define submask(x) ((1L << ((x) + 1)) - 1)
1486 #define bit(obj,st) (((obj) >> (st)) & 1)
1487 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1488 #define sbits(obj,st,fn) \
1489 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1490 #define BranchDest(addr,instr) \
1491 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1494 static unsigned long
1495 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1496 unsigned long status_reg)
1498 unsigned long res, shift;
1499 int rm = bits (inst, 0, 3);
1500 unsigned long shifttype = bits (inst, 5, 6);
1504 int rs = bits (inst, 8, 11);
1505 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1508 shift = bits (inst, 7, 11);
1511 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1512 + (bit (inst, 4) ? 12 : 8))
1513 : read_register (rm));
1518 res = shift >= 32 ? 0 : res << shift;
1522 res = shift >= 32 ? 0 : res >> shift;
1528 res = ((res & 0x80000000L)
1529 ? ~((~res) >> shift) : res >> shift);
1532 case 3: /* ROR/RRX */
1535 res = (res >> 1) | (carry ? 0x80000000L : 0);
1537 res = (res >> shift) | (res << (32 - shift));
1541 return res & 0xffffffff;
1544 /* Return number of 1-bits in VAL. */
1547 bitcount (unsigned long val)
1550 for (nbits = 0; val != 0; nbits++)
1551 val &= val - 1; /* delete rightmost 1-bit in val */
1556 thumb_get_next_pc (CORE_ADDR pc)
1558 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1559 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1560 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1561 unsigned long offset;
1563 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1567 /* Fetch the saved PC from the stack. It's stored above
1568 all of the other registers. */
1569 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1570 sp = read_register (ARM_SP_REGNUM);
1571 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1572 nextpc = ADDR_BITS_REMOVE (nextpc);
1574 error (_("Infinite loop detected"));
1576 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1578 unsigned long status = read_register (ARM_PS_REGNUM);
1579 unsigned long cond = bits (inst1, 8, 11);
1580 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1581 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1583 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1585 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1587 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1589 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1590 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1591 nextpc = pc_val + offset;
1592 /* For BLX make sure to clear the low bits. */
1593 if (bits (inst2, 11, 12) == 1)
1594 nextpc = nextpc & 0xfffffffc;
1596 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1598 if (bits (inst1, 3, 6) == 0x0f)
1601 nextpc = read_register (bits (inst1, 3, 6));
1603 nextpc = ADDR_BITS_REMOVE (nextpc);
1605 error (_("Infinite loop detected"));
1612 arm_get_next_pc (CORE_ADDR pc)
1614 unsigned long pc_val;
1615 unsigned long this_instr;
1616 unsigned long status;
1619 if (arm_pc_is_thumb (pc))
1620 return thumb_get_next_pc (pc);
1622 pc_val = (unsigned long) pc;
1623 this_instr = read_memory_unsigned_integer (pc, 4);
1624 status = read_register (ARM_PS_REGNUM);
1625 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1627 if (condition_true (bits (this_instr, 28, 31), status))
1629 switch (bits (this_instr, 24, 27))
1632 case 0x1: /* data processing */
1636 unsigned long operand1, operand2, result = 0;
1640 if (bits (this_instr, 12, 15) != 15)
1643 if (bits (this_instr, 22, 25) == 0
1644 && bits (this_instr, 4, 7) == 9) /* multiply */
1645 error (_("Invalid update to pc in instruction"));
1647 /* BX <reg>, BLX <reg> */
1648 if (bits (this_instr, 4, 27) == 0x12fff1
1649 || bits (this_instr, 4, 27) == 0x12fff3)
1651 rn = bits (this_instr, 0, 3);
1652 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1653 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1656 error (_("Infinite loop detected"));
1661 /* Multiply into PC */
1662 c = (status & FLAG_C) ? 1 : 0;
1663 rn = bits (this_instr, 16, 19);
1664 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1666 if (bit (this_instr, 25))
1668 unsigned long immval = bits (this_instr, 0, 7);
1669 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1670 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1673 else /* operand 2 is a shifted register */
1674 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1676 switch (bits (this_instr, 21, 24))
1679 result = operand1 & operand2;
1683 result = operand1 ^ operand2;
1687 result = operand1 - operand2;
1691 result = operand2 - operand1;
1695 result = operand1 + operand2;
1699 result = operand1 + operand2 + c;
1703 result = operand1 - operand2 + c;
1707 result = operand2 - operand1 + c;
1713 case 0xb: /* tst, teq, cmp, cmn */
1714 result = (unsigned long) nextpc;
1718 result = operand1 | operand2;
1722 /* Always step into a function. */
1727 result = operand1 & ~operand2;
1734 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1737 error (_("Infinite loop detected"));
1742 case 0x5: /* data transfer */
1745 if (bit (this_instr, 20))
1748 if (bits (this_instr, 12, 15) == 15)
1754 if (bit (this_instr, 22))
1755 error (_("Invalid update to pc in instruction"));
1757 /* byte write to PC */
1758 rn = bits (this_instr, 16, 19);
1759 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1760 if (bit (this_instr, 24))
1763 int c = (status & FLAG_C) ? 1 : 0;
1764 unsigned long offset =
1765 (bit (this_instr, 25)
1766 ? shifted_reg_val (this_instr, c, pc_val, status)
1767 : bits (this_instr, 0, 11));
1769 if (bit (this_instr, 23))
1774 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1777 nextpc = ADDR_BITS_REMOVE (nextpc);
1780 error (_("Infinite loop detected"));
1786 case 0x9: /* block transfer */
1787 if (bit (this_instr, 20))
1790 if (bit (this_instr, 15))
1795 if (bit (this_instr, 23))
1798 unsigned long reglist = bits (this_instr, 0, 14);
1799 offset = bitcount (reglist) * 4;
1800 if (bit (this_instr, 24)) /* pre */
1803 else if (bit (this_instr, 24))
1807 unsigned long rn_val =
1808 read_register (bits (this_instr, 16, 19));
1810 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1814 nextpc = ADDR_BITS_REMOVE (nextpc);
1816 error (_("Infinite loop detected"));
1821 case 0xb: /* branch & link */
1822 case 0xa: /* branch */
1824 nextpc = BranchDest (pc, this_instr);
1827 if (bits (this_instr, 28, 31) == INST_NV)
1828 nextpc |= bit (this_instr, 24) << 1;
1830 nextpc = ADDR_BITS_REMOVE (nextpc);
1832 error (_("Infinite loop detected"));
1838 case 0xe: /* coproc ops */
1843 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1851 /* single_step() is called just before we want to resume the inferior,
1852 if we want to single-step it but there is no hardware or kernel
1853 single-step support. We find the target of the coming instruction
1856 single_step() is also called just after the inferior stops. If we
1857 had set up a simulated single-step, we undo our damage. */
1860 arm_software_single_step (enum target_signal sig, int insert_bpt)
1862 /* NOTE: This may insert the wrong breakpoint instruction when
1863 single-stepping over a mode-changing instruction, if the
1864 CPSR heuristics are used. */
1868 CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1870 insert_single_step_breakpoint (next_pc);
1873 remove_single_step_breakpoints ();
1876 #include "bfd-in2.h"
1877 #include "libcoff.h"
1880 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1882 if (arm_pc_is_thumb (memaddr))
1884 static asymbol *asym;
1885 static combined_entry_type ce;
1886 static struct coff_symbol_struct csym;
1887 static struct bfd fake_bfd;
1888 static bfd_target fake_target;
1890 if (csym.native == NULL)
1892 /* Create a fake symbol vector containing a Thumb symbol.
1893 This is solely so that the code in print_insn_little_arm()
1894 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1895 the presence of a Thumb symbol and switch to decoding
1896 Thumb instructions. */
1898 fake_target.flavour = bfd_target_coff_flavour;
1899 fake_bfd.xvec = &fake_target;
1900 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1902 csym.symbol.the_bfd = &fake_bfd;
1903 csym.symbol.name = "fake";
1904 asym = (asymbol *) & csym;
1907 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1908 info->symbols = &asym;
1911 info->symbols = NULL;
1913 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1914 return print_insn_big_arm (memaddr, info);
1916 return print_insn_little_arm (memaddr, info);
1919 /* The following define instruction sequences that will cause ARM
1920 cpu's to take an undefined instruction trap. These are used to
1921 signal a breakpoint to GDB.
1923 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1924 modes. A different instruction is required for each mode. The ARM
1925 cpu's can also be big or little endian. Thus four different
1926 instructions are needed to support all cases.
1928 Note: ARMv4 defines several new instructions that will take the
1929 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1930 not in fact add the new instructions. The new undefined
1931 instructions in ARMv4 are all instructions that had no defined
1932 behaviour in earlier chips. There is no guarantee that they will
1933 raise an exception, but may be treated as NOP's. In practice, it
1934 may only safe to rely on instructions matching:
1936 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1937 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1938 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1940 Even this may only true if the condition predicate is true. The
1941 following use a condition predicate of ALWAYS so it is always TRUE.
1943 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1944 and NetBSD all use a software interrupt rather than an undefined
1945 instruction to force a trap. This can be handled by by the
1946 abi-specific code during establishment of the gdbarch vector. */
1949 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1950 override these definitions. */
1951 #ifndef ARM_LE_BREAKPOINT
1952 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1954 #ifndef ARM_BE_BREAKPOINT
1955 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1957 #ifndef THUMB_LE_BREAKPOINT
1958 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1960 #ifndef THUMB_BE_BREAKPOINT
1961 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1964 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1965 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1966 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1967 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1969 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1970 the program counter value to determine whether a 16-bit or 32-bit
1971 breakpoint should be used. It returns a pointer to a string of
1972 bytes that encode a breakpoint instruction, stores the length of
1973 the string to *lenptr, and adjusts the program counter (if
1974 necessary) to point to the actual memory location where the
1975 breakpoint should be inserted. */
1977 static const unsigned char *
1978 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1980 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1982 if (arm_pc_is_thumb (*pcptr))
1984 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1985 *lenptr = tdep->thumb_breakpoint_size;
1986 return tdep->thumb_breakpoint;
1990 *lenptr = tdep->arm_breakpoint_size;
1991 return tdep->arm_breakpoint;
1995 /* Extract from an array REGBUF containing the (raw) register state a
1996 function return value of type TYPE, and copy that, in virtual
1997 format, into VALBUF. */
2000 arm_extract_return_value (struct type *type, struct regcache *regs,
2003 if (TYPE_CODE_FLT == TYPE_CODE (type))
2005 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2009 /* The value is in register F0 in internal format. We need to
2010 extract the raw value and then convert it to the desired
2012 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2014 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2015 convert_from_extended (floatformat_from_type (type), tmpbuf,
2020 case ARM_FLOAT_SOFT_FPA:
2021 case ARM_FLOAT_SOFT_VFP:
2022 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2023 if (TYPE_LENGTH (type) > 4)
2024 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2025 valbuf + INT_REGISTER_SIZE);
2030 (__FILE__, __LINE__,
2031 _("arm_extract_return_value: Floating point model not supported"));
2035 else if (TYPE_CODE (type) == TYPE_CODE_INT
2036 || TYPE_CODE (type) == TYPE_CODE_CHAR
2037 || TYPE_CODE (type) == TYPE_CODE_BOOL
2038 || TYPE_CODE (type) == TYPE_CODE_PTR
2039 || TYPE_CODE (type) == TYPE_CODE_REF
2040 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2042 /* If the the type is a plain integer, then the access is
2043 straight-forward. Otherwise we have to play around a bit more. */
2044 int len = TYPE_LENGTH (type);
2045 int regno = ARM_A1_REGNUM;
2050 /* By using store_unsigned_integer we avoid having to do
2051 anything special for small big-endian values. */
2052 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2053 store_unsigned_integer (valbuf,
2054 (len > INT_REGISTER_SIZE
2055 ? INT_REGISTER_SIZE : len),
2057 len -= INT_REGISTER_SIZE;
2058 valbuf += INT_REGISTER_SIZE;
2063 /* For a structure or union the behaviour is as if the value had
2064 been stored to word-aligned memory and then loaded into
2065 registers with 32-bit load instruction(s). */
2066 int len = TYPE_LENGTH (type);
2067 int regno = ARM_A1_REGNUM;
2068 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2072 regcache_cooked_read (regs, regno++, tmpbuf);
2073 memcpy (valbuf, tmpbuf,
2074 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2075 len -= INT_REGISTER_SIZE;
2076 valbuf += INT_REGISTER_SIZE;
2082 /* Will a function return an aggregate type in memory or in a
2083 register? Return 0 if an aggregate type can be returned in a
2084 register, 1 if it must be returned in memory. */
2087 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2090 enum type_code code;
2092 CHECK_TYPEDEF (type);
2094 /* In the ARM ABI, "integer" like aggregate types are returned in
2095 registers. For an aggregate type to be integer like, its size
2096 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2097 offset of each addressable subfield must be zero. Note that bit
2098 fields are not addressable, and all addressable subfields of
2099 unions always start at offset zero.
2101 This function is based on the behaviour of GCC 2.95.1.
2102 See: gcc/arm.c: arm_return_in_memory() for details.
2104 Note: All versions of GCC before GCC 2.95.2 do not set up the
2105 parameters correctly for a function returning the following
2106 structure: struct { float f;}; This should be returned in memory,
2107 not a register. Richard Earnshaw sent me a patch, but I do not
2108 know of any way to detect if a function like the above has been
2109 compiled with the correct calling convention. */
2111 /* All aggregate types that won't fit in a register must be returned
2113 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2118 /* The AAPCS says all aggregates not larger than a word are returned
2120 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2123 /* The only aggregate types that can be returned in a register are
2124 structs and unions. Arrays must be returned in memory. */
2125 code = TYPE_CODE (type);
2126 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2131 /* Assume all other aggregate types can be returned in a register.
2132 Run a check for structures, unions and arrays. */
2135 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2138 /* Need to check if this struct/union is "integer" like. For
2139 this to be true, its size must be less than or equal to
2140 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2141 subfield must be zero. Note that bit fields are not
2142 addressable, and unions always start at offset zero. If any
2143 of the subfields is a floating point type, the struct/union
2144 cannot be an integer type. */
2146 /* For each field in the object, check:
2147 1) Is it FP? --> yes, nRc = 1;
2148 2) Is it addressable (bitpos != 0) and
2149 not packed (bitsize == 0)?
2153 for (i = 0; i < TYPE_NFIELDS (type); i++)
2155 enum type_code field_type_code;
2156 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2158 /* Is it a floating point type field? */
2159 if (field_type_code == TYPE_CODE_FLT)
2165 /* If bitpos != 0, then we have to care about it. */
2166 if (TYPE_FIELD_BITPOS (type, i) != 0)
2168 /* Bitfields are not addressable. If the field bitsize is
2169 zero, then the field is not packed. Hence it cannot be
2170 a bitfield or any other packed type. */
2171 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2183 /* Write into appropriate registers a function return value of type
2184 TYPE, given in virtual format. */
2187 arm_store_return_value (struct type *type, struct regcache *regs,
2188 const gdb_byte *valbuf)
2190 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2192 char buf[MAX_REGISTER_SIZE];
2194 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2198 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2199 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2202 case ARM_FLOAT_SOFT_FPA:
2203 case ARM_FLOAT_SOFT_VFP:
2204 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2205 if (TYPE_LENGTH (type) > 4)
2206 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2207 valbuf + INT_REGISTER_SIZE);
2212 (__FILE__, __LINE__,
2213 _("arm_store_return_value: Floating point model not supported"));
2217 else if (TYPE_CODE (type) == TYPE_CODE_INT
2218 || TYPE_CODE (type) == TYPE_CODE_CHAR
2219 || TYPE_CODE (type) == TYPE_CODE_BOOL
2220 || TYPE_CODE (type) == TYPE_CODE_PTR
2221 || TYPE_CODE (type) == TYPE_CODE_REF
2222 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2224 if (TYPE_LENGTH (type) <= 4)
2226 /* Values of one word or less are zero/sign-extended and
2228 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2229 LONGEST val = unpack_long (type, valbuf);
2231 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2232 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2236 /* Integral values greater than one word are stored in consecutive
2237 registers starting with r0. This will always be a multiple of
2238 the regiser size. */
2239 int len = TYPE_LENGTH (type);
2240 int regno = ARM_A1_REGNUM;
2244 regcache_cooked_write (regs, regno++, valbuf);
2245 len -= INT_REGISTER_SIZE;
2246 valbuf += INT_REGISTER_SIZE;
2252 /* For a structure or union the behaviour is as if the value had
2253 been stored to word-aligned memory and then loaded into
2254 registers with 32-bit load instruction(s). */
2255 int len = TYPE_LENGTH (type);
2256 int regno = ARM_A1_REGNUM;
2257 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2261 memcpy (tmpbuf, valbuf,
2262 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2263 regcache_cooked_write (regs, regno++, tmpbuf);
2264 len -= INT_REGISTER_SIZE;
2265 valbuf += INT_REGISTER_SIZE;
2271 /* Handle function return values. */
2273 static enum return_value_convention
2274 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2275 struct regcache *regcache, gdb_byte *readbuf,
2276 const gdb_byte *writebuf)
2278 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2280 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2281 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2282 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2284 if (tdep->struct_return == pcc_struct_return
2285 || arm_return_in_memory (gdbarch, valtype))
2286 return RETURN_VALUE_STRUCT_CONVENTION;
2290 arm_store_return_value (valtype, regcache, writebuf);
2293 arm_extract_return_value (valtype, regcache, readbuf);
2295 return RETURN_VALUE_REGISTER_CONVENTION;
2300 arm_get_longjmp_target (CORE_ADDR *pc)
2303 char buf[INT_REGISTER_SIZE];
2304 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2306 jb_addr = read_register (ARM_A1_REGNUM);
2308 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2312 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2316 /* Return non-zero if the PC is inside a thumb call thunk. */
2319 arm_in_call_stub (CORE_ADDR pc, char *name)
2321 CORE_ADDR start_addr;
2323 /* Find the starting address of the function containing the PC. If
2324 the caller didn't give us a name, look it up at the same time. */
2325 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2329 return strncmp (name, "_call_via_r", 11) == 0;
2332 /* If PC is in a Thumb call or return stub, return the address of the
2333 target PC, which is in a register. The thunk functions are called
2334 _called_via_xx, where x is the register name. The possible names
2335 are r0-r9, sl, fp, ip, sp, and lr. */
2338 arm_skip_stub (CORE_ADDR pc)
2341 CORE_ADDR start_addr;
2343 /* Find the starting address and name of the function containing the PC. */
2344 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2347 /* Call thunks always start with "_call_via_". */
2348 if (strncmp (name, "_call_via_", 10) == 0)
2350 /* Use the name suffix to determine which register contains the
2352 static char *table[15] =
2353 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2354 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2358 for (regno = 0; regno <= 14; regno++)
2359 if (strcmp (&name[10], table[regno]) == 0)
2360 return read_register (regno);
2363 return 0; /* not a stub */
2367 set_arm_command (char *args, int from_tty)
2369 printf_unfiltered (_("\
2370 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2371 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2375 show_arm_command (char *args, int from_tty)
2377 cmd_show_list (showarmcmdlist, from_tty, "");
2381 arm_update_current_architecture (void)
2383 struct gdbarch_info info;
2385 /* If the current architecture is not ARM, we have nothing to do. */
2386 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2389 /* Update the architecture. */
2390 gdbarch_info_init (&info);
2392 if (!gdbarch_update_p (info))
2393 internal_error (__FILE__, __LINE__, "could not update architecture");
2397 set_fp_model_sfunc (char *args, int from_tty,
2398 struct cmd_list_element *c)
2400 enum arm_float_model fp_model;
2402 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2403 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2405 arm_fp_model = fp_model;
2409 if (fp_model == ARM_FLOAT_LAST)
2410 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2413 arm_update_current_architecture ();
2417 show_fp_model (struct ui_file *file, int from_tty,
2418 struct cmd_list_element *c, const char *value)
2420 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2422 if (arm_fp_model == ARM_FLOAT_AUTO
2423 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2424 fprintf_filtered (file, _("\
2425 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2426 fp_model_strings[tdep->fp_model]);
2428 fprintf_filtered (file, _("\
2429 The current ARM floating point model is \"%s\".\n"),
2430 fp_model_strings[arm_fp_model]);
2434 arm_set_abi (char *args, int from_tty,
2435 struct cmd_list_element *c)
2437 enum arm_abi_kind arm_abi;
2439 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2440 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2442 arm_abi_global = arm_abi;
2446 if (arm_abi == ARM_ABI_LAST)
2447 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2450 arm_update_current_architecture ();
2454 arm_show_abi (struct ui_file *file, int from_tty,
2455 struct cmd_list_element *c, const char *value)
2457 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2459 if (arm_abi_global == ARM_ABI_AUTO
2460 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2461 fprintf_filtered (file, _("\
2462 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2463 arm_abi_strings[tdep->arm_abi]);
2465 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2469 /* If the user changes the register disassembly style used for info
2470 register and other commands, we have to also switch the style used
2471 in opcodes for disassembly output. This function is run in the "set
2472 arm disassembly" command, and does that. */
2475 set_disassembly_style_sfunc (char *args, int from_tty,
2476 struct cmd_list_element *c)
2478 set_disassembly_style ();
2481 /* Return the ARM register name corresponding to register I. */
2483 arm_register_name (int i)
2485 return arm_register_names[i];
2489 set_disassembly_style (void)
2493 /* Find the style that the user wants. */
2494 for (current = 0; current < num_disassembly_options; current++)
2495 if (disassembly_style == valid_disassembly_styles[current])
2497 gdb_assert (current < num_disassembly_options);
2499 /* Synchronize the disassembler. */
2500 set_arm_regname_option (current);
2503 /* Test whether the coff symbol specific value corresponds to a Thumb
2507 coff_sym_is_thumb (int val)
2509 return (val == C_THUMBEXT ||
2510 val == C_THUMBSTAT ||
2511 val == C_THUMBEXTFUNC ||
2512 val == C_THUMBSTATFUNC ||
2513 val == C_THUMBLABEL);
2516 /* arm_coff_make_msymbol_special()
2517 arm_elf_make_msymbol_special()
2519 These functions test whether the COFF or ELF symbol corresponds to
2520 an address in thumb code, and set a "special" bit in a minimal
2521 symbol to indicate that it does. */
2524 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2526 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2528 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2530 MSYMBOL_SET_SPECIAL (msym);
2534 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2536 if (coff_sym_is_thumb (val))
2537 MSYMBOL_SET_SPECIAL (msym);
2541 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2543 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2545 /* If necessary, set the T bit. */
2548 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2549 if (arm_pc_is_thumb (pc))
2550 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2552 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2556 static struct value *
2557 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2559 const int *reg_p = baton;
2560 return value_of_register (*reg_p, frame);
2563 static enum gdb_osabi
2564 arm_elf_osabi_sniffer (bfd *abfd)
2566 unsigned int elfosabi;
2567 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2569 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2571 if (elfosabi == ELFOSABI_ARM)
2572 /* GNU tools use this value. Check note sections in this case,
2574 bfd_map_over_sections (abfd,
2575 generic_elf_osabi_sniff_abi_tag_sections,
2578 /* Anything else will be handled by the generic ELF sniffer. */
2583 /* Initialize the current architecture based on INFO. If possible,
2584 re-use an architecture from ARCHES, which is a list of
2585 architectures already created during this debugging session.
2587 Called e.g. at program startup, when reading a core file, and when
2588 reading a binary file. */
2590 static struct gdbarch *
2591 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2593 struct gdbarch_tdep *tdep;
2594 struct gdbarch *gdbarch;
2595 struct gdbarch_list *best_arch;
2596 enum arm_abi_kind arm_abi = arm_abi_global;
2597 enum arm_float_model fp_model = arm_fp_model;
2598 struct tdesc_arch_data *tdesc_data = NULL;
2601 /* Check any target description for validity. */
2602 if (tdesc_has_registers (info.target_desc))
2604 /* For most registers we require GDB's default names; but also allow
2605 the numeric names for sp / lr / pc, as a convenience. */
2606 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2607 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2608 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2610 const struct tdesc_feature *feature;
2613 feature = tdesc_find_feature (info.target_desc,
2614 "org.gnu.gdb.arm.core");
2615 if (feature == NULL)
2618 tdesc_data = tdesc_data_alloc ();
2621 for (i = 0; i < ARM_SP_REGNUM; i++)
2622 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2623 arm_register_names[i]);
2624 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2627 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2630 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2633 valid_p &= tdesc_numbered_register (feature, tdesc_data,
2634 ARM_PS_REGNUM, "cpsr");
2638 tdesc_data_cleanup (tdesc_data);
2642 feature = tdesc_find_feature (info.target_desc,
2643 "org.gnu.gdb.arm.fpa");
2644 if (feature != NULL)
2647 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
2648 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2649 arm_register_names[i]);
2652 tdesc_data_cleanup (tdesc_data);
2658 /* If we have an object to base this architecture on, try to determine
2661 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2663 int ei_osabi, e_flags;
2665 switch (bfd_get_flavour (info.abfd))
2667 case bfd_target_aout_flavour:
2668 /* Assume it's an old APCS-style ABI. */
2669 arm_abi = ARM_ABI_APCS;
2672 case bfd_target_coff_flavour:
2673 /* Assume it's an old APCS-style ABI. */
2675 arm_abi = ARM_ABI_APCS;
2678 case bfd_target_elf_flavour:
2679 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2680 e_flags = elf_elfheader (info.abfd)->e_flags;
2682 if (ei_osabi == ELFOSABI_ARM)
2684 /* GNU tools used to use this value, but do not for EABI
2685 objects. There's nowhere to tag an EABI version
2686 anyway, so assume APCS. */
2687 arm_abi = ARM_ABI_APCS;
2689 else if (ei_osabi == ELFOSABI_NONE)
2691 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2695 case EF_ARM_EABI_UNKNOWN:
2696 /* Assume GNU tools. */
2697 arm_abi = ARM_ABI_APCS;
2700 case EF_ARM_EABI_VER4:
2701 case EF_ARM_EABI_VER5:
2702 arm_abi = ARM_ABI_AAPCS;
2703 /* EABI binaries default to VFP float ordering. */
2704 if (fp_model == ARM_FLOAT_AUTO)
2705 fp_model = ARM_FLOAT_SOFT_VFP;
2709 /* Leave it as "auto". */
2710 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2715 if (fp_model == ARM_FLOAT_AUTO)
2717 int e_flags = elf_elfheader (info.abfd)->e_flags;
2719 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2722 /* Leave it as "auto". Strictly speaking this case
2723 means FPA, but almost nobody uses that now, and
2724 many toolchains fail to set the appropriate bits
2725 for the floating-point model they use. */
2727 case EF_ARM_SOFT_FLOAT:
2728 fp_model = ARM_FLOAT_SOFT_FPA;
2730 case EF_ARM_VFP_FLOAT:
2731 fp_model = ARM_FLOAT_VFP;
2733 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2734 fp_model = ARM_FLOAT_SOFT_VFP;
2741 /* Leave it as "auto". */
2746 /* Now that we have inferred any architecture settings that we
2747 can, try to inherit from the last ARM ABI. */
2750 if (arm_abi == ARM_ABI_AUTO)
2751 arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi;
2753 if (fp_model == ARM_FLOAT_AUTO)
2754 fp_model = gdbarch_tdep (arches->gdbarch)->fp_model;
2758 /* There was no prior ARM architecture; fill in default values. */
2760 if (arm_abi == ARM_ABI_AUTO)
2761 arm_abi = ARM_ABI_APCS;
2763 /* We used to default to FPA for generic ARM, but almost nobody
2764 uses that now, and we now provide a way for the user to force
2765 the model. So default to the most useful variant. */
2766 if (fp_model == ARM_FLOAT_AUTO)
2767 fp_model = ARM_FLOAT_SOFT_FPA;
2770 /* If there is already a candidate, use it. */
2771 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2773 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2775 if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2778 if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2781 /* Found a match. */
2785 if (best_arch != NULL)
2787 if (tdesc_data != NULL)
2788 tdesc_data_cleanup (tdesc_data);
2789 return best_arch->gdbarch;
2792 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2793 gdbarch = gdbarch_alloc (&info, tdep);
2795 /* Record additional information about the architecture we are defining.
2796 These are gdbarch discriminators, like the OSABI. */
2797 tdep->arm_abi = arm_abi;
2798 tdep->fp_model = fp_model;
2801 switch (info.byte_order)
2803 case BFD_ENDIAN_BIG:
2804 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2805 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2806 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2807 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2811 case BFD_ENDIAN_LITTLE:
2812 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2813 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2814 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2815 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2820 internal_error (__FILE__, __LINE__,
2821 _("arm_gdbarch_init: bad byte order for float format"));
2824 /* On ARM targets char defaults to unsigned. */
2825 set_gdbarch_char_signed (gdbarch, 0);
2827 /* This should be low enough for everything. */
2828 tdep->lowest_pc = 0x20;
2829 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2831 /* The default, for both APCS and AAPCS, is to return small
2832 structures in registers. */
2833 tdep->struct_return = reg_struct_return;
2835 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2836 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2838 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2840 /* Frame handling. */
2841 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2842 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2843 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2845 frame_base_set_default (gdbarch, &arm_normal_base);
2847 /* Address manipulation. */
2848 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2849 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2851 /* Advance PC across function entry code. */
2852 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2854 /* The stack grows downward. */
2855 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2857 /* Breakpoint manipulation. */
2858 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2860 /* Information about registers, etc. */
2861 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2862 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2863 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2864 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2865 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2866 set_gdbarch_register_type (gdbarch, arm_register_type);
2868 /* Internal <-> external register number maps. */
2869 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2871 /* Integer registers are 4 bytes. */
2872 set_gdbarch_deprecated_register_size (gdbarch, 4);
2873 set_gdbarch_register_name (gdbarch, arm_register_name);
2875 /* Returning results. */
2876 set_gdbarch_return_value (gdbarch, arm_return_value);
2878 /* Single stepping. */
2879 /* XXX For an RDI target we should ask the target if it can single-step. */
2880 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2883 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2885 /* Minsymbol frobbing. */
2886 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2887 set_gdbarch_coff_make_msymbol_special (gdbarch,
2888 arm_coff_make_msymbol_special);
2890 /* Virtual tables. */
2891 set_gdbarch_vbit_in_delta (gdbarch, 1);
2893 /* Hook in the ABI-specific overrides, if they have been registered. */
2894 gdbarch_init_osabi (info, gdbarch);
2896 /* Add some default predicates. */
2897 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
2898 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2899 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2901 /* Now we have tuned the configuration, set a few final things,
2902 based on what the OS ABI has told us. */
2904 if (tdep->jb_pc >= 0)
2905 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2907 /* Floating point sizes and format. */
2908 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2909 if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)
2911 set_gdbarch_double_format
2912 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
2913 set_gdbarch_long_double_format
2914 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
2918 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2919 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2923 tdesc_use_registers (gdbarch, tdesc_data);
2925 /* Add standard register aliases. We add aliases even for those
2926 nanes which are used by the current architecture - it's simpler,
2927 and does no harm, since nothing ever lists user registers. */
2928 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
2929 user_reg_add (gdbarch, arm_register_aliases[i].name,
2930 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
2936 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2938 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2943 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2944 (unsigned long) tdep->lowest_pc);
2947 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2950 _initialize_arm_tdep (void)
2952 struct ui_file *stb;
2954 struct cmd_list_element *new_set, *new_show;
2955 const char *setname;
2956 const char *setdesc;
2957 const char *const *regnames;
2959 static char *helptext;
2960 char regdesc[1024], *rdptr = regdesc;
2961 size_t rest = sizeof (regdesc);
2963 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2965 /* Register an ELF OS ABI sniffer for ARM binaries. */
2966 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2967 bfd_target_elf_flavour,
2968 arm_elf_osabi_sniffer);
2970 /* Get the number of possible sets of register names defined in opcodes. */
2971 num_disassembly_options = get_arm_regname_num_options ();
2973 /* Add root prefix command for all "set arm"/"show arm" commands. */
2974 add_prefix_cmd ("arm", no_class, set_arm_command,
2975 _("Various ARM-specific commands."),
2976 &setarmcmdlist, "set arm ", 0, &setlist);
2978 add_prefix_cmd ("arm", no_class, show_arm_command,
2979 _("Various ARM-specific commands."),
2980 &showarmcmdlist, "show arm ", 0, &showlist);
2982 /* Sync the opcode insn printer with our register viewer. */
2983 parse_arm_disassembler_option ("reg-names-std");
2985 /* Initialize the array that will be passed to
2986 add_setshow_enum_cmd(). */
2987 valid_disassembly_styles
2988 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2989 for (i = 0; i < num_disassembly_options; i++)
2991 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2992 valid_disassembly_styles[i] = setname;
2993 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
2996 /* When we find the default names, tell the disassembler to use
2998 if (!strcmp (setname, "std"))
3000 disassembly_style = setname;
3001 set_arm_regname_option (i);
3004 /* Mark the end of valid options. */
3005 valid_disassembly_styles[num_disassembly_options] = NULL;
3007 /* Create the help text. */
3008 stb = mem_fileopen ();
3009 fprintf_unfiltered (stb, "%s%s%s",
3010 _("The valid values are:\n"),
3012 _("The default is \"std\"."));
3013 helptext = ui_file_xstrdup (stb, &length);
3014 ui_file_delete (stb);
3016 add_setshow_enum_cmd("disassembler", no_class,
3017 valid_disassembly_styles, &disassembly_style,
3018 _("Set the disassembly style."),
3019 _("Show the disassembly style."),
3021 set_disassembly_style_sfunc,
3022 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3023 &setarmcmdlist, &showarmcmdlist);
3025 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3026 _("Set usage of ARM 32-bit mode."),
3027 _("Show usage of ARM 32-bit mode."),
3028 _("When off, a 26-bit PC will be used."),
3030 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3031 &setarmcmdlist, &showarmcmdlist);
3033 /* Add a command to allow the user to force the FPU model. */
3034 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3035 _("Set the floating point type."),
3036 _("Show the floating point type."),
3037 _("auto - Determine the FP typefrom the OS-ABI.\n\
3038 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3039 fpa - FPA co-processor (GCC compiled).\n\
3040 softvfp - Software FP with pure-endian doubles.\n\
3041 vfp - VFP co-processor."),
3042 set_fp_model_sfunc, show_fp_model,
3043 &setarmcmdlist, &showarmcmdlist);
3045 /* Add a command to allow the user to force the ABI. */
3046 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3049 NULL, arm_set_abi, arm_show_abi,
3050 &setarmcmdlist, &showarmcmdlist);
3052 /* Debugging flag. */
3053 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3054 _("Set ARM debugging."),
3055 _("Show ARM debugging."),
3056 _("When on, arm-specific debugging is enabled."),
3058 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3059 &setdebuglist, &showdebuglist);