1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element *setarmcmdlist = NULL;
72 static struct cmd_list_element *showarmcmdlist = NULL;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
88 static const char *current_fp_model = "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
101 static const char *arm_abi_string = "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options;
106 /* We have more registers than the disassembler as gdb can print the value
107 of special registers as well.
108 The general register names are overwritten by whatever is being used by
109 the disassembler at the moment. We also adjust the case of cpsr and fps. */
111 /* Initial value: Register names used in ARM's ISA documentation. */
112 static char * arm_register_name_strings[] =
113 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
114 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
115 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
116 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
117 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
118 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
119 "fps", "cpsr" }; /* 24 25 */
120 static char **arm_register_names = arm_register_name_strings;
122 /* Valid register name styles. */
123 static const char **valid_disassembly_styles;
125 /* Disassembly style to use. Default to "std" register names. */
126 static const char *disassembly_style;
127 /* Index to that option in the opcodes table. */
128 static int current_option;
130 /* This is used to keep the bfd arch_info in sync with the disassembly
132 static void set_disassembly_style_sfunc(char *, int,
133 struct cmd_list_element *);
134 static void set_disassembly_style (void);
136 static void convert_from_extended (const struct floatformat *, const void *,
138 static void convert_to_extended (const struct floatformat *, void *,
141 struct arm_prologue_cache
143 /* The stack pointer at the time this frame was created; i.e. the
144 caller's stack pointer when this function was called. It is used
145 to identify this frame. */
148 /* The frame base for this frame is just prev_sp + frame offset -
149 frame size. FRAMESIZE is the size of this stack frame, and
150 FRAMEOFFSET if the initial offset from the stack pointer (this
151 frame's stack pointer, not PREV_SP) to the frame base. */
156 /* The register used to hold the frame pointer for this frame. */
159 /* Saved register offsets. */
160 struct trad_frame_saved_reg *saved_regs;
163 /* Addresses for calling Thumb functions have the bit 0 set.
164 Here are some macros to test, set, or clear bit 0 of addresses. */
165 #define IS_THUMB_ADDR(addr) ((addr) & 1)
166 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
167 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
169 /* Set to true if the 32-bit mode is in use. */
173 /* Determine if the program counter specified in MEMADDR is in a Thumb
177 arm_pc_is_thumb (CORE_ADDR memaddr)
179 struct minimal_symbol *sym;
181 /* If bit 0 of the address is set, assume this is a Thumb address. */
182 if (IS_THUMB_ADDR (memaddr))
185 /* Thumb functions have a "special" bit set in minimal symbols. */
186 sym = lookup_minimal_symbol_by_pc (memaddr);
189 return (MSYMBOL_IS_SPECIAL (sym));
197 /* Remove useless bits from addresses in a running program. */
199 arm_addr_bits_remove (CORE_ADDR val)
202 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
204 return (val & 0x03fffffc);
207 /* When reading symbols, we need to zap the low bit of the address,
208 which may be set to 1 for Thumb functions. */
210 arm_smash_text_address (CORE_ADDR val)
215 /* Analyze a Thumb prologue, looking for a recognizable stack frame
216 and frame pointer. Scan until we encounter a store that could
217 clobber the stack frame unexpectedly, or an unknown instruction. */
220 thumb_analyze_prologue (struct gdbarch *gdbarch,
221 CORE_ADDR start, CORE_ADDR limit,
222 struct arm_prologue_cache *cache)
226 struct pv_area *stack;
227 struct cleanup *back_to;
230 for (i = 0; i < 16; i++)
231 regs[i] = pv_register (i, 0);
232 stack = make_pv_area (ARM_SP_REGNUM);
233 back_to = make_cleanup_free_pv_area (stack);
235 /* The call instruction saved PC in LR, and the current PC is not
236 interesting. Due to this file's conventions, we want the value
237 of LR at this function's entry, not at the call site, so we do
238 not record the save of the PC - when the ARM prologue analyzer
239 has also been converted to the pv mechanism, we could record the
240 save here and remove the hack in prev_register. */
241 regs[ARM_PC_REGNUM] = pv_unknown ();
243 while (start < limit)
247 insn = read_memory_unsigned_integer (start, 2);
249 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
255 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
256 whether to save LR (R14). */
257 mask = (insn & 0xff) | ((insn & 0x100) << 6);
259 /* Calculate offsets of saved R0-R7 and LR. */
260 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
261 if (mask & (1 << regno))
263 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
269 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
271 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
277 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
280 offset = (insn & 0x7f) << 2; /* get scaled offset */
281 if (insn & 0x80) /* Check for SUB. */
282 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
285 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
288 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
289 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
291 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
293 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
294 int src_reg = (insn & 0x78) >> 3;
295 regs[dst_reg] = regs[src_reg];
297 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
299 /* Handle stores to the stack. Normally pushes are used,
300 but with GCC -mtpcs-frame, there may be other stores
301 in the prologue to create the frame. */
302 int regno = (insn >> 8) & 0x7;
305 offset = (insn & 0xff) << 2;
306 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
308 if (pv_area_store_would_trash (stack, addr))
311 pv_area_store (stack, addr, 4, regs[regno]);
315 /* We don't know what this instruction is. We're finished
316 scanning. NOTE: Recognizing more safe-to-ignore
317 instructions here will improve support for optimized
327 do_cleanups (back_to);
331 /* frameoffset is unused for this unwinder. */
332 cache->frameoffset = 0;
334 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
336 /* Frame pointer is fp. Frame size is constant. */
337 cache->framereg = ARM_FP_REGNUM;
338 cache->framesize = -regs[ARM_FP_REGNUM].k;
340 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
342 /* Frame pointer is r7. Frame size is constant. */
343 cache->framereg = THUMB_FP_REGNUM;
344 cache->framesize = -regs[THUMB_FP_REGNUM].k;
346 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
348 /* Try the stack pointer... this is a bit desperate. */
349 cache->framereg = ARM_SP_REGNUM;
350 cache->framesize = -regs[ARM_SP_REGNUM].k;
354 /* We're just out of luck. We don't know where the frame is. */
355 cache->framereg = -1;
356 cache->framesize = 0;
359 for (i = 0; i < 16; i++)
360 if (pv_area_find_reg (stack, gdbarch, i, &offset))
361 cache->saved_regs[i].addr = offset;
363 do_cleanups (back_to);
367 /* Advance the PC across any function entry prologue instructions to
368 reach some "real" code.
370 The APCS (ARM Procedure Call Standard) defines the following
374 [stmfd sp!, {a1,a2,a3,a4}]
375 stmfd sp!, {...,fp,ip,lr,pc}
376 [stfe f7, [sp, #-12]!]
377 [stfe f6, [sp, #-12]!]
378 [stfe f5, [sp, #-12]!]
379 [stfe f4, [sp, #-12]!]
380 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
383 arm_skip_prologue (CORE_ADDR pc)
387 CORE_ADDR func_addr, func_end = 0;
389 struct symtab_and_line sal;
391 /* If we're in a dummy frame, don't even try to skip the prologue. */
392 if (deprecated_pc_in_call_dummy (pc))
395 /* See what the symbol table says. */
397 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
401 /* Found a function. */
402 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
403 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
405 /* Don't use this trick for assembly source files. */
406 sal = find_pc_line (func_addr, 0);
407 if ((sal.line != 0) && (sal.end < func_end))
412 /* Can't find the prologue end in the symbol table, try it the hard way
413 by disassembling the instructions. */
415 /* Like arm_scan_prologue, stop no later than pc + 64. */
416 if (func_end == 0 || func_end > pc + 64)
419 /* Check if this is Thumb code. */
420 if (arm_pc_is_thumb (pc))
421 return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL);
423 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
425 inst = read_memory_unsigned_integer (skip_pc, 4);
427 /* "mov ip, sp" is no longer a required part of the prologue. */
428 if (inst == 0xe1a0c00d) /* mov ip, sp */
431 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
434 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
437 /* Some prologues begin with "str lr, [sp, #-4]!". */
438 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
441 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
444 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
447 /* Any insns after this point may float into the code, if it makes
448 for better instruction scheduling, so we skip them only if we
449 find them, but still consider the function to be frame-ful. */
451 /* We may have either one sfmfd instruction here, or several stfe
452 insns, depending on the version of floating point code we
454 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
457 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
460 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
463 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
466 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
467 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
468 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
471 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
472 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
473 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
476 /* Un-recognized instruction; stop scanning. */
480 return skip_pc; /* End of prologue */
484 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
485 This function decodes a Thumb function prologue to determine:
486 1) the size of the stack frame
487 2) which registers are saved on it
488 3) the offsets of saved regs
489 4) the offset from the stack pointer to the frame pointer
491 A typical Thumb function prologue would create this stack frame
492 (offsets relative to FP)
493 old SP -> 24 stack parameters
496 R7 -> 0 local variables (16 bytes)
497 SP -> -12 additional stack space (12 bytes)
498 The frame size would thus be 36 bytes, and the frame offset would be
499 12 bytes. The frame register is R7.
501 The comments for thumb_skip_prolog() describe the algorithm we use
502 to detect the end of the prolog. */
506 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
508 CORE_ADDR prologue_start;
509 CORE_ADDR prologue_end;
510 CORE_ADDR current_pc;
511 /* Which register has been copied to register n? */
514 bit 0 - push { rlist }
515 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
516 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
521 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
523 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
525 if (sal.line == 0) /* no line info, use current PC */
526 prologue_end = prev_pc;
527 else if (sal.end < prologue_end) /* next line begins after fn end */
528 prologue_end = sal.end; /* (probably means no prologue) */
531 /* We're in the boondocks: we have no idea where the start of the
535 prologue_end = min (prologue_end, prev_pc);
537 thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end,
541 /* This function decodes an ARM function prologue to determine:
542 1) the size of the stack frame
543 2) which registers are saved on it
544 3) the offsets of saved regs
545 4) the offset from the stack pointer to the frame pointer
546 This information is stored in the "extra" fields of the frame_info.
548 There are two basic forms for the ARM prologue. The fixed argument
549 function call will look like:
552 stmfd sp!, {fp, ip, lr, pc}
556 Which would create this stack frame (offsets relative to FP):
557 IP -> 4 (caller's stack)
558 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
559 -4 LR (return address in caller)
560 -8 IP (copy of caller's SP)
562 SP -> -28 Local variables
564 The frame size would thus be 32 bytes, and the frame offset would be
565 28 bytes. The stmfd call can also save any of the vN registers it
566 plans to use, which increases the frame size accordingly.
568 Note: The stored PC is 8 off of the STMFD instruction that stored it
569 because the ARM Store instructions always store PC + 8 when you read
572 A variable argument function call will look like:
575 stmfd sp!, {a1, a2, a3, a4}
576 stmfd sp!, {fp, ip, lr, pc}
579 Which would create this stack frame (offsets relative to FP):
580 IP -> 20 (caller's stack)
585 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
586 -4 LR (return address in caller)
587 -8 IP (copy of caller's SP)
589 SP -> -28 Local variables
591 The frame size would thus be 48 bytes, and the frame offset would be
594 There is another potential complication, which is that the optimizer
595 will try to separate the store of fp in the "stmfd" instruction from
596 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
597 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
599 Also, note, the original version of the ARM toolchain claimed that there
602 instruction at the end of the prologue. I have never seen GCC produce
603 this, and the ARM docs don't mention it. We still test for it below in
609 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
611 int regno, sp_offset, fp_offset, ip_offset;
612 CORE_ADDR prologue_start, prologue_end, current_pc;
613 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
615 /* Assume there is no frame until proven otherwise. */
616 cache->framereg = ARM_SP_REGNUM;
617 cache->framesize = 0;
618 cache->frameoffset = 0;
620 /* Check for Thumb prologue. */
621 if (arm_pc_is_thumb (prev_pc))
623 thumb_scan_prologue (prev_pc, cache);
627 /* Find the function prologue. If we can't find the function in
628 the symbol table, peek in the stack frame to find the PC. */
629 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
631 /* One way to find the end of the prologue (which works well
632 for unoptimized code) is to do the following:
634 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
637 prologue_end = prev_pc;
638 else if (sal.end < prologue_end)
639 prologue_end = sal.end;
641 This mechanism is very accurate so long as the optimizer
642 doesn't move any instructions from the function body into the
643 prologue. If this happens, sal.end will be the last
644 instruction in the first hunk of prologue code just before
645 the first instruction that the scheduler has moved from
646 the body to the prologue.
648 In order to make sure that we scan all of the prologue
649 instructions, we use a slightly less accurate mechanism which
650 may scan more than necessary. To help compensate for this
651 lack of accuracy, the prologue scanning loop below contains
652 several clauses which'll cause the loop to terminate early if
653 an implausible prologue instruction is encountered.
659 is a suitable endpoint since it accounts for the largest
660 possible prologue plus up to five instructions inserted by
663 if (prologue_end > prologue_start + 64)
665 prologue_end = prologue_start + 64; /* See above. */
670 /* We have no symbol information. Our only option is to assume this
671 function has a standard stack frame and the normal frame register.
672 Then, we can find the value of our frame pointer on entrance to
673 the callee (or at the present moment if this is the innermost frame).
674 The value stored there should be the address of the stmfd + 8. */
676 LONGEST return_value;
678 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
679 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
683 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
684 prologue_end = prologue_start + 64; /* See above. */
688 if (prev_pc < prologue_end)
689 prologue_end = prev_pc;
691 /* Now search the prologue looking for instructions that set up the
692 frame pointer, adjust the stack pointer, and save registers.
694 Be careful, however, and if it doesn't look like a prologue,
695 don't try to scan it. If, for instance, a frameless function
696 begins with stmfd sp!, then we will tell ourselves there is
697 a frame, which will confuse stack traceback, as well as "finish"
698 and other operations that rely on a knowledge of the stack
701 In the APCS, the prologue should start with "mov ip, sp" so
702 if we don't see this as the first insn, we will stop.
704 [Note: This doesn't seem to be true any longer, so it's now an
705 optional part of the prologue. - Kevin Buettner, 2001-11-20]
707 [Note further: The "mov ip,sp" only seems to be missing in
708 frameless functions at optimization level "-O2" or above,
709 in which case it is often (but not always) replaced by
710 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
712 sp_offset = fp_offset = ip_offset = 0;
714 for (current_pc = prologue_start;
715 current_pc < prologue_end;
718 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
720 if (insn == 0xe1a0c00d) /* mov ip, sp */
725 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
727 unsigned imm = insn & 0xff; /* immediate value */
728 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
729 imm = (imm >> rot) | (imm << (32 - rot));
733 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
735 unsigned imm = insn & 0xff; /* immediate value */
736 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
737 imm = (imm >> rot) | (imm << (32 - rot));
741 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
744 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
747 else if ((insn & 0xffff0000) == 0xe92d0000)
748 /* stmfd sp!, {..., fp, ip, lr, pc}
750 stmfd sp!, {a1, a2, a3, a4} */
752 int mask = insn & 0xffff;
754 /* Calculate offsets of saved registers. */
755 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
756 if (mask & (1 << regno))
759 cache->saved_regs[regno].addr = sp_offset;
762 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
763 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
764 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
766 /* No need to add this to saved_regs -- it's just an arg reg. */
769 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
770 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
771 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
773 /* No need to add this to saved_regs -- it's just an arg reg. */
776 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
778 unsigned imm = insn & 0xff; /* immediate value */
779 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
780 imm = (imm >> rot) | (imm << (32 - rot));
781 fp_offset = -imm + ip_offset;
782 cache->framereg = ARM_FP_REGNUM;
784 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
786 unsigned imm = insn & 0xff; /* immediate value */
787 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
788 imm = (imm >> rot) | (imm << (32 - rot));
791 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
794 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
795 cache->saved_regs[regno].addr = sp_offset;
797 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
800 unsigned int fp_start_reg, fp_bound_reg;
802 if ((insn & 0x800) == 0x800) /* N0 is set */
804 if ((insn & 0x40000) == 0x40000) /* N1 is set */
811 if ((insn & 0x40000) == 0x40000) /* N1 is set */
817 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
818 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
819 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
822 cache->saved_regs[fp_start_reg++].addr = sp_offset;
825 else if ((insn & 0xf0000000) != 0xe0000000)
826 break; /* Condition not true, exit early */
827 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
828 break; /* Don't scan past a block load */
830 /* The optimizer might shove anything into the prologue,
831 so we just skip what we don't recognize. */
835 /* The frame size is just the negative of the offset (from the
836 original SP) of the last thing thing we pushed on the stack.
837 The frame offset is [new FP] - [new SP]. */
838 cache->framesize = -sp_offset;
839 if (cache->framereg == ARM_FP_REGNUM)
840 cache->frameoffset = fp_offset - sp_offset;
842 cache->frameoffset = 0;
845 static struct arm_prologue_cache *
846 arm_make_prologue_cache (struct frame_info *next_frame)
849 struct arm_prologue_cache *cache;
850 CORE_ADDR unwound_fp;
852 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
853 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
855 arm_scan_prologue (next_frame, cache);
857 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
861 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
863 /* Calculate actual addresses of saved registers using offsets
864 determined by arm_scan_prologue. */
865 for (reg = 0; reg < NUM_REGS; reg++)
866 if (trad_frame_addr_p (cache->saved_regs, reg))
867 cache->saved_regs[reg].addr += cache->prev_sp;
872 /* Our frame ID for a normal frame is the current function's starting PC
873 and the caller's SP when we were called. */
876 arm_prologue_this_id (struct frame_info *next_frame,
878 struct frame_id *this_id)
880 struct arm_prologue_cache *cache;
884 if (*this_cache == NULL)
885 *this_cache = arm_make_prologue_cache (next_frame);
888 func = frame_func_unwind (next_frame);
890 /* This is meant to halt the backtrace at "_start". Make sure we
891 don't halt it at a generic dummy frame. */
892 if (func <= LOWEST_PC)
895 /* If we've hit a wall, stop. */
896 if (cache->prev_sp == 0)
899 id = frame_id_build (cache->prev_sp, func);
904 arm_prologue_prev_register (struct frame_info *next_frame,
908 enum lval_type *lvalp,
913 struct arm_prologue_cache *cache;
915 if (*this_cache == NULL)
916 *this_cache = arm_make_prologue_cache (next_frame);
919 /* If we are asked to unwind the PC, then we need to return the LR
920 instead. The saved value of PC points into this frame's
921 prologue, not the next frame's resume location. */
922 if (prev_regnum == ARM_PC_REGNUM)
923 prev_regnum = ARM_LR_REGNUM;
925 /* SP is generally not saved to the stack, but this frame is
926 identified by NEXT_FRAME's stack pointer at the time of the call.
927 The value was already reconstructed into PREV_SP. */
928 if (prev_regnum == ARM_SP_REGNUM)
932 store_unsigned_integer (valuep, 4, cache->prev_sp);
936 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
937 optimized, lvalp, addrp, realnump, valuep);
940 struct frame_unwind arm_prologue_unwind = {
942 arm_prologue_this_id,
943 arm_prologue_prev_register
946 static const struct frame_unwind *
947 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
949 return &arm_prologue_unwind;
952 static struct arm_prologue_cache *
953 arm_make_stub_cache (struct frame_info *next_frame)
956 struct arm_prologue_cache *cache;
957 CORE_ADDR unwound_fp;
959 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
960 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
962 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
967 /* Our frame ID for a stub frame is the current SP and LR. */
970 arm_stub_this_id (struct frame_info *next_frame,
972 struct frame_id *this_id)
974 struct arm_prologue_cache *cache;
976 if (*this_cache == NULL)
977 *this_cache = arm_make_stub_cache (next_frame);
980 *this_id = frame_id_build (cache->prev_sp,
981 frame_pc_unwind (next_frame));
984 struct frame_unwind arm_stub_unwind = {
987 arm_prologue_prev_register
990 static const struct frame_unwind *
991 arm_stub_unwind_sniffer (struct frame_info *next_frame)
995 if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL)
996 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
997 return &arm_stub_unwind;
1003 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1005 struct arm_prologue_cache *cache;
1007 if (*this_cache == NULL)
1008 *this_cache = arm_make_prologue_cache (next_frame);
1009 cache = *this_cache;
1011 return cache->prev_sp + cache->frameoffset - cache->framesize;
1014 struct frame_base arm_normal_base = {
1015 &arm_prologue_unwind,
1016 arm_normal_frame_base,
1017 arm_normal_frame_base,
1018 arm_normal_frame_base
1021 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1022 dummy frame. The frame ID's base needs to match the TOS value
1023 saved by save_dummy_frame_tos() and returned from
1024 arm_push_dummy_call, and the PC needs to match the dummy frame's
1027 static struct frame_id
1028 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1030 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1031 frame_pc_unwind (next_frame));
1034 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1035 be used to construct the previous frame's ID, after looking up the
1036 containing function). */
1039 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1042 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1043 return arm_addr_bits_remove (pc);
1047 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1049 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1052 /* When arguments must be pushed onto the stack, they go on in reverse
1053 order. The code below implements a FILO (stack) to do this. */
1058 struct stack_item *prev;
1062 static struct stack_item *
1063 push_stack_item (struct stack_item *prev, void *contents, int len)
1065 struct stack_item *si;
1066 si = xmalloc (sizeof (struct stack_item));
1067 si->data = xmalloc (len);
1070 memcpy (si->data, contents, len);
1074 static struct stack_item *
1075 pop_stack_item (struct stack_item *si)
1077 struct stack_item *dead = si;
1085 /* Return the alignment (in bytes) of the given type. */
1088 arm_type_align (struct type *t)
1094 t = check_typedef (t);
1095 switch (TYPE_CODE (t))
1098 /* Should never happen. */
1099 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1103 case TYPE_CODE_ENUM:
1107 case TYPE_CODE_RANGE:
1108 case TYPE_CODE_BITSTRING:
1110 case TYPE_CODE_CHAR:
1111 case TYPE_CODE_BOOL:
1112 return TYPE_LENGTH (t);
1114 case TYPE_CODE_ARRAY:
1115 case TYPE_CODE_COMPLEX:
1116 /* TODO: What about vector types? */
1117 return arm_type_align (TYPE_TARGET_TYPE (t));
1119 case TYPE_CODE_STRUCT:
1120 case TYPE_CODE_UNION:
1122 for (n = 0; n < TYPE_NFIELDS (t); n++)
1124 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1132 /* We currently only support passing parameters in integer registers. This
1133 conforms with GCC's default model. Several other variants exist and
1134 we should probably support some of them based on the selected ABI. */
1137 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1138 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1139 struct value **args, CORE_ADDR sp, int struct_return,
1140 CORE_ADDR struct_addr)
1145 struct stack_item *si = NULL;
1147 /* Set the return address. For the ARM, the return breakpoint is
1148 always at BP_ADDR. */
1149 /* XXX Fix for Thumb. */
1150 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1152 /* Walk through the list of args and determine how large a temporary
1153 stack is required. Need to take care here as structs may be
1154 passed on the stack, and we have to to push them. */
1157 argreg = ARM_A1_REGNUM;
1160 /* The struct_return pointer occupies the first parameter
1161 passing register. */
1165 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1166 REGISTER_NAME (argreg), paddr (struct_addr));
1167 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1171 for (argnum = 0; argnum < nargs; argnum++)
1174 struct type *arg_type;
1175 struct type *target_type;
1176 enum type_code typecode;
1180 arg_type = check_typedef (value_type (args[argnum]));
1181 len = TYPE_LENGTH (arg_type);
1182 target_type = TYPE_TARGET_TYPE (arg_type);
1183 typecode = TYPE_CODE (arg_type);
1184 val = value_contents_writeable (args[argnum]);
1186 align = arm_type_align (arg_type);
1187 /* Round alignment up to a whole number of words. */
1188 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1189 /* Different ABIs have different maximum alignments. */
1190 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1192 /* The APCS ABI only requires word alignment. */
1193 align = INT_REGISTER_SIZE;
1197 /* The AAPCS requires at most doubleword alignment. */
1198 if (align > INT_REGISTER_SIZE * 2)
1199 align = INT_REGISTER_SIZE * 2;
1202 /* Push stack padding for dowubleword alignment. */
1203 if (nstack & (align - 1))
1205 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1206 nstack += INT_REGISTER_SIZE;
1209 /* Doubleword aligned quantities must go in even register pairs. */
1210 if (argreg <= ARM_LAST_ARG_REGNUM
1211 && align > INT_REGISTER_SIZE
1215 /* If the argument is a pointer to a function, and it is a
1216 Thumb function, create a LOCAL copy of the value and set
1217 the THUMB bit in it. */
1218 if (TYPE_CODE_PTR == typecode
1219 && target_type != NULL
1220 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1222 CORE_ADDR regval = extract_unsigned_integer (val, len);
1223 if (arm_pc_is_thumb (regval))
1226 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1230 /* Copy the argument to general registers or the stack in
1231 register-sized pieces. Large arguments are split between
1232 registers and stack. */
1235 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1237 if (argreg <= ARM_LAST_ARG_REGNUM)
1239 /* The argument is being passed in a general purpose
1241 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1243 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1244 argnum, REGISTER_NAME (argreg),
1245 phex (regval, DEPRECATED_REGISTER_SIZE));
1246 regcache_cooked_write_unsigned (regcache, argreg, regval);
1251 /* Push the arguments onto the stack. */
1253 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1255 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1256 nstack += DEPRECATED_REGISTER_SIZE;
1263 /* If we have an odd number of words to push, then decrement the stack
1264 by one word now, so first stack argument will be dword aligned. */
1271 write_memory (sp, si->data, si->len);
1272 si = pop_stack_item (si);
1275 /* Finally, update teh SP register. */
1276 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1282 /* Always align the frame to an 8-byte boundary. This is required on
1283 some platforms and harmless on the rest. */
1286 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1288 /* Align the stack to eight bytes. */
1289 return sp & ~ (CORE_ADDR) 7;
1293 print_fpu_flags (int flags)
1295 if (flags & (1 << 0))
1296 fputs ("IVO ", stdout);
1297 if (flags & (1 << 1))
1298 fputs ("DVZ ", stdout);
1299 if (flags & (1 << 2))
1300 fputs ("OFL ", stdout);
1301 if (flags & (1 << 3))
1302 fputs ("UFL ", stdout);
1303 if (flags & (1 << 4))
1304 fputs ("INX ", stdout);
1308 /* Print interesting information about the floating point processor
1309 (if present) or emulator. */
1311 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1312 struct frame_info *frame, const char *args)
1314 unsigned long status = read_register (ARM_FPS_REGNUM);
1317 type = (status >> 24) & 127;
1318 if (status & (1 << 31))
1319 printf (_("Hardware FPU type %d\n"), type);
1321 printf (_("Software FPU type %d\n"), type);
1322 /* i18n: [floating point unit] mask */
1323 fputs (_("mask: "), stdout);
1324 print_fpu_flags (status >> 16);
1325 /* i18n: [floating point unit] flags */
1326 fputs (_("flags: "), stdout);
1327 print_fpu_flags (status);
1330 /* Return the GDB type object for the "standard" data type of data in
1333 static struct type *
1334 arm_register_type (struct gdbarch *gdbarch, int regnum)
1336 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1337 return builtin_type_arm_ext;
1338 else if (regnum == ARM_SP_REGNUM)
1339 return builtin_type_void_data_ptr;
1340 else if (regnum == ARM_PC_REGNUM)
1341 return builtin_type_void_func_ptr;
1343 return builtin_type_uint32;
1346 /* Index within `registers' of the first byte of the space for
1350 arm_register_byte (int regnum)
1352 if (regnum < ARM_F0_REGNUM)
1353 return regnum * INT_REGISTER_SIZE;
1354 else if (regnum < ARM_PS_REGNUM)
1355 return (NUM_GREGS * INT_REGISTER_SIZE
1356 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1358 return (NUM_GREGS * INT_REGISTER_SIZE
1359 + NUM_FREGS * FP_REGISTER_SIZE
1360 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1363 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1365 arm_register_sim_regno (int regnum)
1368 gdb_assert (reg >= 0 && reg < NUM_REGS);
1370 if (reg < NUM_GREGS)
1371 return SIM_ARM_R0_REGNUM + reg;
1374 if (reg < NUM_FREGS)
1375 return SIM_ARM_FP0_REGNUM + reg;
1378 if (reg < NUM_SREGS)
1379 return SIM_ARM_FPS_REGNUM + reg;
1382 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1385 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1386 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1387 It is thought that this is is the floating-point register format on
1388 little-endian systems. */
1391 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1395 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1396 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1398 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1400 floatformat_from_doublest (fmt, &d, dbl);
1404 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1407 floatformat_to_doublest (fmt, ptr, &d);
1408 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1409 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1411 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1416 condition_true (unsigned long cond, unsigned long status_reg)
1418 if (cond == INST_AL || cond == INST_NV)
1424 return ((status_reg & FLAG_Z) != 0);
1426 return ((status_reg & FLAG_Z) == 0);
1428 return ((status_reg & FLAG_C) != 0);
1430 return ((status_reg & FLAG_C) == 0);
1432 return ((status_reg & FLAG_N) != 0);
1434 return ((status_reg & FLAG_N) == 0);
1436 return ((status_reg & FLAG_V) != 0);
1438 return ((status_reg & FLAG_V) == 0);
1440 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1442 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1444 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1446 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1448 return (((status_reg & FLAG_Z) == 0) &&
1449 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1451 return (((status_reg & FLAG_Z) != 0) ||
1452 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1457 /* Support routines for single stepping. Calculate the next PC value. */
1458 #define submask(x) ((1L << ((x) + 1)) - 1)
1459 #define bit(obj,st) (((obj) >> (st)) & 1)
1460 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1461 #define sbits(obj,st,fn) \
1462 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1463 #define BranchDest(addr,instr) \
1464 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1467 static unsigned long
1468 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1469 unsigned long status_reg)
1471 unsigned long res, shift;
1472 int rm = bits (inst, 0, 3);
1473 unsigned long shifttype = bits (inst, 5, 6);
1477 int rs = bits (inst, 8, 11);
1478 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1481 shift = bits (inst, 7, 11);
1484 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1485 + (bit (inst, 4) ? 12 : 8))
1486 : read_register (rm));
1491 res = shift >= 32 ? 0 : res << shift;
1495 res = shift >= 32 ? 0 : res >> shift;
1501 res = ((res & 0x80000000L)
1502 ? ~((~res) >> shift) : res >> shift);
1505 case 3: /* ROR/RRX */
1508 res = (res >> 1) | (carry ? 0x80000000L : 0);
1510 res = (res >> shift) | (res << (32 - shift));
1514 return res & 0xffffffff;
1517 /* Return number of 1-bits in VAL. */
1520 bitcount (unsigned long val)
1523 for (nbits = 0; val != 0; nbits++)
1524 val &= val - 1; /* delete rightmost 1-bit in val */
1529 thumb_get_next_pc (CORE_ADDR pc)
1531 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1532 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1533 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1534 unsigned long offset;
1536 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1540 /* Fetch the saved PC from the stack. It's stored above
1541 all of the other registers. */
1542 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1543 sp = read_register (ARM_SP_REGNUM);
1544 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1545 nextpc = ADDR_BITS_REMOVE (nextpc);
1547 error (_("Infinite loop detected"));
1549 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1551 unsigned long status = read_register (ARM_PS_REGNUM);
1552 unsigned long cond = bits (inst1, 8, 11);
1553 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1554 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1556 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1558 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1560 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1562 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1563 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1564 nextpc = pc_val + offset;
1565 /* For BLX make sure to clear the low bits. */
1566 if (bits (inst2, 11, 12) == 1)
1567 nextpc = nextpc & 0xfffffffc;
1569 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1571 if (bits (inst1, 3, 6) == 0x0f)
1574 nextpc = read_register (bits (inst1, 3, 6));
1576 nextpc = ADDR_BITS_REMOVE (nextpc);
1578 error (_("Infinite loop detected"));
1585 arm_get_next_pc (CORE_ADDR pc)
1587 unsigned long pc_val;
1588 unsigned long this_instr;
1589 unsigned long status;
1592 if (arm_pc_is_thumb (pc))
1593 return thumb_get_next_pc (pc);
1595 pc_val = (unsigned long) pc;
1596 this_instr = read_memory_unsigned_integer (pc, 4);
1597 status = read_register (ARM_PS_REGNUM);
1598 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1600 if (condition_true (bits (this_instr, 28, 31), status))
1602 switch (bits (this_instr, 24, 27))
1605 case 0x1: /* data processing */
1609 unsigned long operand1, operand2, result = 0;
1613 if (bits (this_instr, 12, 15) != 15)
1616 if (bits (this_instr, 22, 25) == 0
1617 && bits (this_instr, 4, 7) == 9) /* multiply */
1618 error (_("Invalid update to pc in instruction"));
1620 /* BX <reg>, BLX <reg> */
1621 if (bits (this_instr, 4, 27) == 0x12fff1
1622 || bits (this_instr, 4, 27) == 0x12fff3)
1624 rn = bits (this_instr, 0, 3);
1625 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1626 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1629 error (_("Infinite loop detected"));
1634 /* Multiply into PC */
1635 c = (status & FLAG_C) ? 1 : 0;
1636 rn = bits (this_instr, 16, 19);
1637 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1639 if (bit (this_instr, 25))
1641 unsigned long immval = bits (this_instr, 0, 7);
1642 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1643 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1646 else /* operand 2 is a shifted register */
1647 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1649 switch (bits (this_instr, 21, 24))
1652 result = operand1 & operand2;
1656 result = operand1 ^ operand2;
1660 result = operand1 - operand2;
1664 result = operand2 - operand1;
1668 result = operand1 + operand2;
1672 result = operand1 + operand2 + c;
1676 result = operand1 - operand2 + c;
1680 result = operand2 - operand1 + c;
1686 case 0xb: /* tst, teq, cmp, cmn */
1687 result = (unsigned long) nextpc;
1691 result = operand1 | operand2;
1695 /* Always step into a function. */
1700 result = operand1 & ~operand2;
1707 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1710 error (_("Infinite loop detected"));
1715 case 0x5: /* data transfer */
1718 if (bit (this_instr, 20))
1721 if (bits (this_instr, 12, 15) == 15)
1727 if (bit (this_instr, 22))
1728 error (_("Invalid update to pc in instruction"));
1730 /* byte write to PC */
1731 rn = bits (this_instr, 16, 19);
1732 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1733 if (bit (this_instr, 24))
1736 int c = (status & FLAG_C) ? 1 : 0;
1737 unsigned long offset =
1738 (bit (this_instr, 25)
1739 ? shifted_reg_val (this_instr, c, pc_val, status)
1740 : bits (this_instr, 0, 11));
1742 if (bit (this_instr, 23))
1747 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1750 nextpc = ADDR_BITS_REMOVE (nextpc);
1753 error (_("Infinite loop detected"));
1759 case 0x9: /* block transfer */
1760 if (bit (this_instr, 20))
1763 if (bit (this_instr, 15))
1768 if (bit (this_instr, 23))
1771 unsigned long reglist = bits (this_instr, 0, 14);
1772 offset = bitcount (reglist) * 4;
1773 if (bit (this_instr, 24)) /* pre */
1776 else if (bit (this_instr, 24))
1780 unsigned long rn_val =
1781 read_register (bits (this_instr, 16, 19));
1783 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1787 nextpc = ADDR_BITS_REMOVE (nextpc);
1789 error (_("Infinite loop detected"));
1794 case 0xb: /* branch & link */
1795 case 0xa: /* branch */
1797 nextpc = BranchDest (pc, this_instr);
1800 if (bits (this_instr, 28, 31) == INST_NV)
1801 nextpc |= bit (this_instr, 24) << 1;
1803 nextpc = ADDR_BITS_REMOVE (nextpc);
1805 error (_("Infinite loop detected"));
1811 case 0xe: /* coproc ops */
1816 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1824 /* single_step() is called just before we want to resume the inferior,
1825 if we want to single-step it but there is no hardware or kernel
1826 single-step support. We find the target of the coming instruction
1829 single_step() is also called just after the inferior stops. If we
1830 had set up a simulated single-step, we undo our damage. */
1833 arm_software_single_step (enum target_signal sig, int insert_bpt)
1835 /* NOTE: This may insert the wrong breakpoint instruction when
1836 single-stepping over a mode-changing instruction, if the
1837 CPSR heuristics are used. */
1841 CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1843 insert_single_step_breakpoint (next_pc);
1846 remove_single_step_breakpoints ();
1849 #include "bfd-in2.h"
1850 #include "libcoff.h"
1853 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1855 if (arm_pc_is_thumb (memaddr))
1857 static asymbol *asym;
1858 static combined_entry_type ce;
1859 static struct coff_symbol_struct csym;
1860 static struct bfd fake_bfd;
1861 static bfd_target fake_target;
1863 if (csym.native == NULL)
1865 /* Create a fake symbol vector containing a Thumb symbol.
1866 This is solely so that the code in print_insn_little_arm()
1867 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1868 the presence of a Thumb symbol and switch to decoding
1869 Thumb instructions. */
1871 fake_target.flavour = bfd_target_coff_flavour;
1872 fake_bfd.xvec = &fake_target;
1873 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1875 csym.symbol.the_bfd = &fake_bfd;
1876 csym.symbol.name = "fake";
1877 asym = (asymbol *) & csym;
1880 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1881 info->symbols = &asym;
1884 info->symbols = NULL;
1886 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1887 return print_insn_big_arm (memaddr, info);
1889 return print_insn_little_arm (memaddr, info);
1892 /* The following define instruction sequences that will cause ARM
1893 cpu's to take an undefined instruction trap. These are used to
1894 signal a breakpoint to GDB.
1896 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1897 modes. A different instruction is required for each mode. The ARM
1898 cpu's can also be big or little endian. Thus four different
1899 instructions are needed to support all cases.
1901 Note: ARMv4 defines several new instructions that will take the
1902 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1903 not in fact add the new instructions. The new undefined
1904 instructions in ARMv4 are all instructions that had no defined
1905 behaviour in earlier chips. There is no guarantee that they will
1906 raise an exception, but may be treated as NOP's. In practice, it
1907 may only safe to rely on instructions matching:
1909 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1910 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1911 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1913 Even this may only true if the condition predicate is true. The
1914 following use a condition predicate of ALWAYS so it is always TRUE.
1916 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1917 and NetBSD all use a software interrupt rather than an undefined
1918 instruction to force a trap. This can be handled by by the
1919 abi-specific code during establishment of the gdbarch vector. */
1922 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1923 override these definitions. */
1924 #ifndef ARM_LE_BREAKPOINT
1925 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1927 #ifndef ARM_BE_BREAKPOINT
1928 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1930 #ifndef THUMB_LE_BREAKPOINT
1931 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1933 #ifndef THUMB_BE_BREAKPOINT
1934 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1937 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1938 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1939 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1940 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1942 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1943 the program counter value to determine whether a 16-bit or 32-bit
1944 breakpoint should be used. It returns a pointer to a string of
1945 bytes that encode a breakpoint instruction, stores the length of
1946 the string to *lenptr, and adjusts the program counter (if
1947 necessary) to point to the actual memory location where the
1948 breakpoint should be inserted. */
1950 static const unsigned char *
1951 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1953 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1955 if (arm_pc_is_thumb (*pcptr))
1957 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1958 *lenptr = tdep->thumb_breakpoint_size;
1959 return tdep->thumb_breakpoint;
1963 *lenptr = tdep->arm_breakpoint_size;
1964 return tdep->arm_breakpoint;
1968 /* Extract from an array REGBUF containing the (raw) register state a
1969 function return value of type TYPE, and copy that, in virtual
1970 format, into VALBUF. */
1973 arm_extract_return_value (struct type *type, struct regcache *regs,
1976 if (TYPE_CODE_FLT == TYPE_CODE (type))
1978 switch (gdbarch_tdep (current_gdbarch)->fp_model)
1982 /* The value is in register F0 in internal format. We need to
1983 extract the raw value and then convert it to the desired
1985 bfd_byte tmpbuf[FP_REGISTER_SIZE];
1987 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
1988 convert_from_extended (floatformat_from_type (type), tmpbuf,
1993 case ARM_FLOAT_SOFT_FPA:
1994 case ARM_FLOAT_SOFT_VFP:
1995 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
1996 if (TYPE_LENGTH (type) > 4)
1997 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
1998 valbuf + INT_REGISTER_SIZE);
2003 (__FILE__, __LINE__,
2004 _("arm_extract_return_value: Floating point model not supported"));
2008 else if (TYPE_CODE (type) == TYPE_CODE_INT
2009 || TYPE_CODE (type) == TYPE_CODE_CHAR
2010 || TYPE_CODE (type) == TYPE_CODE_BOOL
2011 || TYPE_CODE (type) == TYPE_CODE_PTR
2012 || TYPE_CODE (type) == TYPE_CODE_REF
2013 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2015 /* If the the type is a plain integer, then the access is
2016 straight-forward. Otherwise we have to play around a bit more. */
2017 int len = TYPE_LENGTH (type);
2018 int regno = ARM_A1_REGNUM;
2023 /* By using store_unsigned_integer we avoid having to do
2024 anything special for small big-endian values. */
2025 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2026 store_unsigned_integer (valbuf,
2027 (len > INT_REGISTER_SIZE
2028 ? INT_REGISTER_SIZE : len),
2030 len -= INT_REGISTER_SIZE;
2031 valbuf += INT_REGISTER_SIZE;
2036 /* For a structure or union the behaviour is as if the value had
2037 been stored to word-aligned memory and then loaded into
2038 registers with 32-bit load instruction(s). */
2039 int len = TYPE_LENGTH (type);
2040 int regno = ARM_A1_REGNUM;
2041 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2045 regcache_cooked_read (regs, regno++, tmpbuf);
2046 memcpy (valbuf, tmpbuf,
2047 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2048 len -= INT_REGISTER_SIZE;
2049 valbuf += INT_REGISTER_SIZE;
2055 /* Will a function return an aggregate type in memory or in a
2056 register? Return 0 if an aggregate type can be returned in a
2057 register, 1 if it must be returned in memory. */
2060 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2063 enum type_code code;
2065 CHECK_TYPEDEF (type);
2067 /* In the ARM ABI, "integer" like aggregate types are returned in
2068 registers. For an aggregate type to be integer like, its size
2069 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2070 offset of each addressable subfield must be zero. Note that bit
2071 fields are not addressable, and all addressable subfields of
2072 unions always start at offset zero.
2074 This function is based on the behaviour of GCC 2.95.1.
2075 See: gcc/arm.c: arm_return_in_memory() for details.
2077 Note: All versions of GCC before GCC 2.95.2 do not set up the
2078 parameters correctly for a function returning the following
2079 structure: struct { float f;}; This should be returned in memory,
2080 not a register. Richard Earnshaw sent me a patch, but I do not
2081 know of any way to detect if a function like the above has been
2082 compiled with the correct calling convention. */
2084 /* All aggregate types that won't fit in a register must be returned
2086 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2091 /* The AAPCS says all aggregates not larger than a word are returned
2093 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2096 /* The only aggregate types that can be returned in a register are
2097 structs and unions. Arrays must be returned in memory. */
2098 code = TYPE_CODE (type);
2099 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2104 /* Assume all other aggregate types can be returned in a register.
2105 Run a check for structures, unions and arrays. */
2108 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2111 /* Need to check if this struct/union is "integer" like. For
2112 this to be true, its size must be less than or equal to
2113 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2114 subfield must be zero. Note that bit fields are not
2115 addressable, and unions always start at offset zero. If any
2116 of the subfields is a floating point type, the struct/union
2117 cannot be an integer type. */
2119 /* For each field in the object, check:
2120 1) Is it FP? --> yes, nRc = 1;
2121 2) Is it addressable (bitpos != 0) and
2122 not packed (bitsize == 0)?
2126 for (i = 0; i < TYPE_NFIELDS (type); i++)
2128 enum type_code field_type_code;
2129 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2131 /* Is it a floating point type field? */
2132 if (field_type_code == TYPE_CODE_FLT)
2138 /* If bitpos != 0, then we have to care about it. */
2139 if (TYPE_FIELD_BITPOS (type, i) != 0)
2141 /* Bitfields are not addressable. If the field bitsize is
2142 zero, then the field is not packed. Hence it cannot be
2143 a bitfield or any other packed type. */
2144 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2156 /* Write into appropriate registers a function return value of type
2157 TYPE, given in virtual format. */
2160 arm_store_return_value (struct type *type, struct regcache *regs,
2161 const gdb_byte *valbuf)
2163 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2165 char buf[MAX_REGISTER_SIZE];
2167 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2171 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2172 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2175 case ARM_FLOAT_SOFT_FPA:
2176 case ARM_FLOAT_SOFT_VFP:
2177 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2178 if (TYPE_LENGTH (type) > 4)
2179 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2180 valbuf + INT_REGISTER_SIZE);
2185 (__FILE__, __LINE__,
2186 _("arm_store_return_value: Floating point model not supported"));
2190 else if (TYPE_CODE (type) == TYPE_CODE_INT
2191 || TYPE_CODE (type) == TYPE_CODE_CHAR
2192 || TYPE_CODE (type) == TYPE_CODE_BOOL
2193 || TYPE_CODE (type) == TYPE_CODE_PTR
2194 || TYPE_CODE (type) == TYPE_CODE_REF
2195 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2197 if (TYPE_LENGTH (type) <= 4)
2199 /* Values of one word or less are zero/sign-extended and
2201 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2202 LONGEST val = unpack_long (type, valbuf);
2204 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2205 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2209 /* Integral values greater than one word are stored in consecutive
2210 registers starting with r0. This will always be a multiple of
2211 the regiser size. */
2212 int len = TYPE_LENGTH (type);
2213 int regno = ARM_A1_REGNUM;
2217 regcache_cooked_write (regs, regno++, valbuf);
2218 len -= INT_REGISTER_SIZE;
2219 valbuf += INT_REGISTER_SIZE;
2225 /* For a structure or union the behaviour is as if the value had
2226 been stored to word-aligned memory and then loaded into
2227 registers with 32-bit load instruction(s). */
2228 int len = TYPE_LENGTH (type);
2229 int regno = ARM_A1_REGNUM;
2230 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2234 memcpy (tmpbuf, valbuf,
2235 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2236 regcache_cooked_write (regs, regno++, tmpbuf);
2237 len -= INT_REGISTER_SIZE;
2238 valbuf += INT_REGISTER_SIZE;
2244 /* Handle function return values. */
2246 static enum return_value_convention
2247 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2248 struct regcache *regcache, gdb_byte *readbuf,
2249 const gdb_byte *writebuf)
2251 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2253 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2254 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2255 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2257 if (tdep->struct_return == pcc_struct_return
2258 || arm_return_in_memory (gdbarch, valtype))
2259 return RETURN_VALUE_STRUCT_CONVENTION;
2263 arm_store_return_value (valtype, regcache, writebuf);
2266 arm_extract_return_value (valtype, regcache, readbuf);
2268 return RETURN_VALUE_REGISTER_CONVENTION;
2273 arm_get_longjmp_target (CORE_ADDR *pc)
2276 char buf[INT_REGISTER_SIZE];
2277 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2279 jb_addr = read_register (ARM_A1_REGNUM);
2281 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2285 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2289 /* Return non-zero if the PC is inside a thumb call thunk. */
2292 arm_in_call_stub (CORE_ADDR pc, char *name)
2294 CORE_ADDR start_addr;
2296 /* Find the starting address of the function containing the PC. If
2297 the caller didn't give us a name, look it up at the same time. */
2298 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2302 return strncmp (name, "_call_via_r", 11) == 0;
2305 /* If PC is in a Thumb call or return stub, return the address of the
2306 target PC, which is in a register. The thunk functions are called
2307 _called_via_xx, where x is the register name. The possible names
2308 are r0-r9, sl, fp, ip, sp, and lr. */
2311 arm_skip_stub (CORE_ADDR pc)
2314 CORE_ADDR start_addr;
2316 /* Find the starting address and name of the function containing the PC. */
2317 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2320 /* Call thunks always start with "_call_via_". */
2321 if (strncmp (name, "_call_via_", 10) == 0)
2323 /* Use the name suffix to determine which register contains the
2325 static char *table[15] =
2326 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2327 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2331 for (regno = 0; regno <= 14; regno++)
2332 if (strcmp (&name[10], table[regno]) == 0)
2333 return read_register (regno);
2336 return 0; /* not a stub */
2340 set_arm_command (char *args, int from_tty)
2342 printf_unfiltered (_("\
2343 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2344 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2348 show_arm_command (char *args, int from_tty)
2350 cmd_show_list (showarmcmdlist, from_tty, "");
2354 arm_update_current_architecture (void)
2356 struct gdbarch_info info;
2358 /* If the current architecture is not ARM, we have nothing to do. */
2359 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2362 /* Update the architecture. */
2363 gdbarch_info_init (&info);
2365 if (!gdbarch_update_p (info))
2366 internal_error (__FILE__, __LINE__, "could not update architecture");
2370 set_fp_model_sfunc (char *args, int from_tty,
2371 struct cmd_list_element *c)
2373 enum arm_float_model fp_model;
2375 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2376 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2378 arm_fp_model = fp_model;
2382 if (fp_model == ARM_FLOAT_LAST)
2383 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2386 arm_update_current_architecture ();
2390 show_fp_model (struct ui_file *file, int from_tty,
2391 struct cmd_list_element *c, const char *value)
2393 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2395 if (arm_fp_model == ARM_FLOAT_AUTO
2396 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2397 fprintf_filtered (file, _("\
2398 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2399 fp_model_strings[tdep->fp_model]);
2401 fprintf_filtered (file, _("\
2402 The current ARM floating point model is \"%s\".\n"),
2403 fp_model_strings[arm_fp_model]);
2407 arm_set_abi (char *args, int from_tty,
2408 struct cmd_list_element *c)
2410 enum arm_abi_kind arm_abi;
2412 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2413 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2415 arm_abi_global = arm_abi;
2419 if (arm_abi == ARM_ABI_LAST)
2420 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2423 arm_update_current_architecture ();
2427 arm_show_abi (struct ui_file *file, int from_tty,
2428 struct cmd_list_element *c, const char *value)
2430 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2432 if (arm_abi_global == ARM_ABI_AUTO
2433 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2434 fprintf_filtered (file, _("\
2435 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2436 arm_abi_strings[tdep->arm_abi]);
2438 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2442 /* If the user changes the register disassembly style used for info
2443 register and other commands, we have to also switch the style used
2444 in opcodes for disassembly output. This function is run in the "set
2445 arm disassembly" command, and does that. */
2448 set_disassembly_style_sfunc (char *args, int from_tty,
2449 struct cmd_list_element *c)
2451 set_disassembly_style ();
2454 /* Return the ARM register name corresponding to register I. */
2456 arm_register_name (int i)
2458 return arm_register_names[i];
2462 set_disassembly_style (void)
2464 const char *setname, *setdesc, *const *regnames;
2467 /* Find the style that the user wants in the opcodes table. */
2469 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2470 while ((disassembly_style != setname)
2471 && (current < num_disassembly_options))
2472 get_arm_regnames (++current, &setname, &setdesc, ®names);
2473 current_option = current;
2475 /* Fill our copy. */
2476 for (j = 0; j < numregs; j++)
2477 arm_register_names[j] = (char *) regnames[j];
2480 if (isupper (*regnames[ARM_PC_REGNUM]))
2482 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2483 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2487 arm_register_names[ARM_FPS_REGNUM] = "fps";
2488 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2491 /* Synchronize the disassembler. */
2492 set_arm_regname_option (current);
2495 /* Test whether the coff symbol specific value corresponds to a Thumb
2499 coff_sym_is_thumb (int val)
2501 return (val == C_THUMBEXT ||
2502 val == C_THUMBSTAT ||
2503 val == C_THUMBEXTFUNC ||
2504 val == C_THUMBSTATFUNC ||
2505 val == C_THUMBLABEL);
2508 /* arm_coff_make_msymbol_special()
2509 arm_elf_make_msymbol_special()
2511 These functions test whether the COFF or ELF symbol corresponds to
2512 an address in thumb code, and set a "special" bit in a minimal
2513 symbol to indicate that it does. */
2516 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2518 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2520 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2522 MSYMBOL_SET_SPECIAL (msym);
2526 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2528 if (coff_sym_is_thumb (val))
2529 MSYMBOL_SET_SPECIAL (msym);
2533 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2535 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2537 /* If necessary, set the T bit. */
2540 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2541 if (arm_pc_is_thumb (pc))
2542 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2544 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2548 static enum gdb_osabi
2549 arm_elf_osabi_sniffer (bfd *abfd)
2551 unsigned int elfosabi;
2552 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2554 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2556 if (elfosabi == ELFOSABI_ARM)
2557 /* GNU tools use this value. Check note sections in this case,
2559 bfd_map_over_sections (abfd,
2560 generic_elf_osabi_sniff_abi_tag_sections,
2563 /* Anything else will be handled by the generic ELF sniffer. */
2568 /* Initialize the current architecture based on INFO. If possible,
2569 re-use an architecture from ARCHES, which is a list of
2570 architectures already created during this debugging session.
2572 Called e.g. at program startup, when reading a core file, and when
2573 reading a binary file. */
2575 static struct gdbarch *
2576 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2578 struct gdbarch_tdep *tdep;
2579 struct gdbarch *gdbarch;
2580 struct gdbarch_list *best_arch;
2581 enum arm_abi_kind arm_abi = arm_abi_global;
2582 enum arm_float_model fp_model = arm_fp_model;
2584 /* If we have an object to base this architecture on, try to determine
2587 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2589 int ei_osabi, e_flags;
2591 switch (bfd_get_flavour (info.abfd))
2593 case bfd_target_aout_flavour:
2594 /* Assume it's an old APCS-style ABI. */
2595 arm_abi = ARM_ABI_APCS;
2598 case bfd_target_coff_flavour:
2599 /* Assume it's an old APCS-style ABI. */
2601 arm_abi = ARM_ABI_APCS;
2604 case bfd_target_elf_flavour:
2605 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2606 e_flags = elf_elfheader (info.abfd)->e_flags;
2608 if (ei_osabi == ELFOSABI_ARM)
2610 /* GNU tools used to use this value, but do not for EABI
2611 objects. There's nowhere to tag an EABI version
2612 anyway, so assume APCS. */
2613 arm_abi = ARM_ABI_APCS;
2615 else if (ei_osabi == ELFOSABI_NONE)
2617 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2621 case EF_ARM_EABI_UNKNOWN:
2622 /* Assume GNU tools. */
2623 arm_abi = ARM_ABI_APCS;
2626 case EF_ARM_EABI_VER4:
2627 case EF_ARM_EABI_VER5:
2628 arm_abi = ARM_ABI_AAPCS;
2629 /* EABI binaries default to VFP float ordering. */
2630 if (fp_model == ARM_FLOAT_AUTO)
2631 fp_model = ARM_FLOAT_SOFT_VFP;
2635 /* Leave it as "auto". */
2636 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2641 if (fp_model == ARM_FLOAT_AUTO)
2643 int e_flags = elf_elfheader (info.abfd)->e_flags;
2645 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2648 /* Leave it as "auto". Strictly speaking this case
2649 means FPA, but almost nobody uses that now, and
2650 many toolchains fail to set the appropriate bits
2651 for the floating-point model they use. */
2653 case EF_ARM_SOFT_FLOAT:
2654 fp_model = ARM_FLOAT_SOFT_FPA;
2656 case EF_ARM_VFP_FLOAT:
2657 fp_model = ARM_FLOAT_VFP;
2659 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2660 fp_model = ARM_FLOAT_SOFT_VFP;
2667 /* Leave it as "auto". */
2672 /* Now that we have inferred any architecture settings that we
2673 can, try to inherit from the last ARM ABI. */
2676 if (arm_abi == ARM_ABI_AUTO)
2677 arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi;
2679 if (fp_model == ARM_FLOAT_AUTO)
2680 fp_model = gdbarch_tdep (arches->gdbarch)->fp_model;
2684 /* There was no prior ARM architecture; fill in default values. */
2686 if (arm_abi == ARM_ABI_AUTO)
2687 arm_abi = ARM_ABI_APCS;
2689 /* We used to default to FPA for generic ARM, but almost nobody
2690 uses that now, and we now provide a way for the user to force
2691 the model. So default to the most useful variant. */
2692 if (fp_model == ARM_FLOAT_AUTO)
2693 fp_model = ARM_FLOAT_SOFT_FPA;
2696 /* If there is already a candidate, use it. */
2697 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2699 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2701 if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2704 if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2707 /* Found a match. */
2711 if (best_arch != NULL)
2712 return best_arch->gdbarch;
2714 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2715 gdbarch = gdbarch_alloc (&info, tdep);
2717 /* Record additional information about the architecture we are defining.
2718 These are gdbarch discriminators, like the OSABI. */
2719 tdep->arm_abi = arm_abi;
2720 tdep->fp_model = fp_model;
2723 switch (info.byte_order)
2725 case BFD_ENDIAN_BIG:
2726 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2727 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2728 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2729 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2733 case BFD_ENDIAN_LITTLE:
2734 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2735 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2736 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2737 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2742 internal_error (__FILE__, __LINE__,
2743 _("arm_gdbarch_init: bad byte order for float format"));
2746 /* On ARM targets char defaults to unsigned. */
2747 set_gdbarch_char_signed (gdbarch, 0);
2749 /* This should be low enough for everything. */
2750 tdep->lowest_pc = 0x20;
2751 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2753 /* The default, for both APCS and AAPCS, is to return small
2754 structures in registers. */
2755 tdep->struct_return = reg_struct_return;
2757 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2758 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2760 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2762 /* Frame handling. */
2763 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2764 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2765 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2767 frame_base_set_default (gdbarch, &arm_normal_base);
2769 /* Address manipulation. */
2770 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2771 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2773 /* Advance PC across function entry code. */
2774 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2776 /* The stack grows downward. */
2777 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2779 /* Breakpoint manipulation. */
2780 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2782 /* Information about registers, etc. */
2783 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2784 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2785 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2786 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2787 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2788 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2789 set_gdbarch_register_type (gdbarch, arm_register_type);
2791 /* Internal <-> external register number maps. */
2792 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2794 /* Integer registers are 4 bytes. */
2795 set_gdbarch_deprecated_register_size (gdbarch, 4);
2796 set_gdbarch_register_name (gdbarch, arm_register_name);
2798 /* Returning results. */
2799 set_gdbarch_return_value (gdbarch, arm_return_value);
2801 /* Single stepping. */
2802 /* XXX For an RDI target we should ask the target if it can single-step. */
2803 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2806 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2808 /* Minsymbol frobbing. */
2809 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2810 set_gdbarch_coff_make_msymbol_special (gdbarch,
2811 arm_coff_make_msymbol_special);
2813 /* Virtual tables. */
2814 set_gdbarch_vbit_in_delta (gdbarch, 1);
2816 /* Hook in the ABI-specific overrides, if they have been registered. */
2817 gdbarch_init_osabi (info, gdbarch);
2819 /* Add some default predicates. */
2820 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
2821 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2822 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2824 /* Now we have tuned the configuration, set a few final things,
2825 based on what the OS ABI has told us. */
2827 if (tdep->jb_pc >= 0)
2828 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2830 /* Floating point sizes and format. */
2831 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2832 if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)
2834 set_gdbarch_double_format
2835 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
2836 set_gdbarch_long_double_format
2837 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
2841 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2842 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2849 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2851 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2856 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2857 (unsigned long) tdep->lowest_pc);
2860 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2863 _initialize_arm_tdep (void)
2865 struct ui_file *stb;
2867 struct cmd_list_element *new_set, *new_show;
2868 const char *setname;
2869 const char *setdesc;
2870 const char *const *regnames;
2872 static char *helptext;
2873 char regdesc[1024], *rdptr = regdesc;
2874 size_t rest = sizeof (regdesc);
2876 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2878 /* Register an ELF OS ABI sniffer for ARM binaries. */
2879 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2880 bfd_target_elf_flavour,
2881 arm_elf_osabi_sniffer);
2883 /* Get the number of possible sets of register names defined in opcodes. */
2884 num_disassembly_options = get_arm_regname_num_options ();
2886 /* Add root prefix command for all "set arm"/"show arm" commands. */
2887 add_prefix_cmd ("arm", no_class, set_arm_command,
2888 _("Various ARM-specific commands."),
2889 &setarmcmdlist, "set arm ", 0, &setlist);
2891 add_prefix_cmd ("arm", no_class, show_arm_command,
2892 _("Various ARM-specific commands."),
2893 &showarmcmdlist, "show arm ", 0, &showlist);
2895 /* Sync the opcode insn printer with our register viewer. */
2896 parse_arm_disassembler_option ("reg-names-std");
2898 /* Initialize the array that will be passed to
2899 add_setshow_enum_cmd(). */
2900 valid_disassembly_styles
2901 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2902 for (i = 0; i < num_disassembly_options; i++)
2904 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2905 valid_disassembly_styles[i] = setname;
2906 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
2909 /* Copy the default names (if found) and synchronize disassembler. */
2910 if (!strcmp (setname, "std"))
2912 disassembly_style = setname;
2914 for (j = 0; j < numregs; j++)
2915 arm_register_names[j] = (char *) regnames[j];
2916 set_arm_regname_option (i);
2919 /* Mark the end of valid options. */
2920 valid_disassembly_styles[num_disassembly_options] = NULL;
2922 /* Create the help text. */
2923 stb = mem_fileopen ();
2924 fprintf_unfiltered (stb, "%s%s%s",
2925 _("The valid values are:\n"),
2927 _("The default is \"std\"."));
2928 helptext = ui_file_xstrdup (stb, &length);
2929 ui_file_delete (stb);
2931 add_setshow_enum_cmd("disassembler", no_class,
2932 valid_disassembly_styles, &disassembly_style,
2933 _("Set the disassembly style."),
2934 _("Show the disassembly style."),
2936 set_disassembly_style_sfunc,
2937 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
2938 &setarmcmdlist, &showarmcmdlist);
2940 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2941 _("Set usage of ARM 32-bit mode."),
2942 _("Show usage of ARM 32-bit mode."),
2943 _("When off, a 26-bit PC will be used."),
2945 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2946 &setarmcmdlist, &showarmcmdlist);
2948 /* Add a command to allow the user to force the FPU model. */
2949 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2950 _("Set the floating point type."),
2951 _("Show the floating point type."),
2952 _("auto - Determine the FP typefrom the OS-ABI.\n\
2953 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2954 fpa - FPA co-processor (GCC compiled).\n\
2955 softvfp - Software FP with pure-endian doubles.\n\
2956 vfp - VFP co-processor."),
2957 set_fp_model_sfunc, show_fp_model,
2958 &setarmcmdlist, &showarmcmdlist);
2960 /* Add a command to allow the user to force the ABI. */
2961 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
2964 NULL, arm_set_abi, arm_show_abi,
2965 &setarmcmdlist, &showarmcmdlist);
2967 /* Debugging flag. */
2968 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2969 _("Set ARM debugging."),
2970 _("Show ARM debugging."),
2971 _("When on, arm-specific debugging is enabled."),
2973 NULL, /* FIXME: i18n: "ARM debugging is %s. */
2974 &setdebuglist, &showdebuglist);