1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data *arm_objfile_data_key;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
80 DEF_VEC_O(arm_mapping_symbol_s);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s) **section_maps;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element *setarmcmdlist = NULL;
89 static struct cmd_list_element *showarmcmdlist = NULL;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
105 static const char *current_fp_model = "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
118 static const char *arm_abi_string = "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings[] =
128 static const char *arm_fallback_mode_string = "auto";
129 static const char *arm_force_mode_string = "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element *);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat *, const void *,
208 static void convert_to_extended (const struct floatformat *, void *,
211 struct arm_prologue_cache
213 /* The stack pointer at the time this frame was created; i.e. the
214 caller's stack pointer when this function was called. It is used
215 to identify this frame. */
218 /* The frame base for this frame is just prev_sp - frame size.
219 FRAMESIZE is the distance from the frame pointer to the
220 initial stack pointer. */
224 /* The register used to hold the frame pointer for this frame. */
227 /* Saved register offsets. */
228 struct trad_frame_saved_reg *saved_regs;
231 /* Addresses for calling Thumb functions have the bit 0 set.
232 Here are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_THUMB_ADDR(addr) ((addr) & 1)
234 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
237 /* Set to true if the 32-bit mode is in use. */
241 /* Determine if FRAME is executing in Thumb mode. */
244 arm_frame_is_thumb (struct frame_info *frame)
248 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
249 directly (from a signal frame or dummy frame) or by interpreting
250 the saved LR (from a prologue or DWARF frame). So consult it and
251 trust the unwinders. */
252 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
254 return (cpsr & CPSR_T) != 0;
257 /* Callback for VEC_lower_bound. */
260 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
261 const struct arm_mapping_symbol *rhs)
263 return lhs->value < rhs->value;
266 /* Determine if the program counter specified in MEMADDR is in a Thumb
267 function. This function should be called for addresses unrelated to
268 any executing frame; otherwise, prefer arm_frame_is_thumb. */
271 arm_pc_is_thumb (CORE_ADDR memaddr)
273 struct obj_section *sec;
274 struct minimal_symbol *sym;
276 /* If bit 0 of the address is set, assume this is a Thumb address. */
277 if (IS_THUMB_ADDR (memaddr))
280 /* If the user wants to override the symbol table, let him. */
281 if (strcmp (arm_force_mode_string, "arm") == 0)
283 if (strcmp (arm_force_mode_string, "thumb") == 0)
286 /* If there are mapping symbols, consult them. */
287 sec = find_pc_section (memaddr);
290 struct arm_per_objfile *data;
291 VEC(arm_mapping_symbol_s) *map;
292 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
296 data = objfile_data (sec->objfile, arm_objfile_data_key);
299 map = data->section_maps[sec->the_bfd_section->index];
300 if (!VEC_empty (arm_mapping_symbol_s, map))
302 struct arm_mapping_symbol *map_sym;
304 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
305 arm_compare_mapping_symbols);
307 /* VEC_lower_bound finds the earliest ordered insertion
308 point. If the following symbol starts at this exact
309 address, we use that; otherwise, the preceding
310 mapping symbol covers this address. */
311 if (idx < VEC_length (arm_mapping_symbol_s, map))
313 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
314 if (map_sym->value == map_key.value)
315 return map_sym->type == 't';
320 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
321 return map_sym->type == 't';
327 /* Thumb functions have a "special" bit set in minimal symbols. */
328 sym = lookup_minimal_symbol_by_pc (memaddr);
330 return (MSYMBOL_IS_SPECIAL (sym));
332 /* If the user wants to override the fallback mode, let them. */
333 if (strcmp (arm_fallback_mode_string, "arm") == 0)
335 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
338 /* If we couldn't find any symbol, but we're talking to a running
339 target, then trust the current value of $cpsr. This lets
340 "display/i $pc" always show the correct mode (though if there is
341 a symbol table we will not reach here, so it still may not be
342 displayed in the mode it will be executed). */
343 if (target_has_registers)
344 return arm_frame_is_thumb (get_current_frame ());
346 /* Otherwise we're out of luck; we assume ARM. */
350 /* Remove useless bits from addresses in a running program. */
352 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
355 return UNMAKE_THUMB_ADDR (val);
357 return (val & 0x03fffffc);
360 /* When reading symbols, we need to zap the low bit of the address,
361 which may be set to 1 for Thumb functions. */
363 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
368 /* Analyze a Thumb prologue, looking for a recognizable stack frame
369 and frame pointer. Scan until we encounter a store that could
370 clobber the stack frame unexpectedly, or an unknown instruction. */
373 thumb_analyze_prologue (struct gdbarch *gdbarch,
374 CORE_ADDR start, CORE_ADDR limit,
375 struct arm_prologue_cache *cache)
377 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
380 struct pv_area *stack;
381 struct cleanup *back_to;
384 for (i = 0; i < 16; i++)
385 regs[i] = pv_register (i, 0);
386 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
387 back_to = make_cleanup_free_pv_area (stack);
389 while (start < limit)
393 insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
395 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
400 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
403 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
404 whether to save LR (R14). */
405 mask = (insn & 0xff) | ((insn & 0x100) << 6);
407 /* Calculate offsets of saved R0-R7 and LR. */
408 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
409 if (mask & (1 << regno))
411 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
413 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
416 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
419 offset = (insn & 0x7f) << 2; /* get scaled offset */
420 if (insn & 0x80) /* Check for SUB. */
421 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
424 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
427 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
428 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
430 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
432 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
433 int src_reg = (insn & 0x78) >> 3;
434 regs[dst_reg] = regs[src_reg];
436 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
438 /* Handle stores to the stack. Normally pushes are used,
439 but with GCC -mtpcs-frame, there may be other stores
440 in the prologue to create the frame. */
441 int regno = (insn >> 8) & 0x7;
444 offset = (insn & 0xff) << 2;
445 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
447 if (pv_area_store_would_trash (stack, addr))
450 pv_area_store (stack, addr, 4, regs[regno]);
454 /* We don't know what this instruction is. We're finished
455 scanning. NOTE: Recognizing more safe-to-ignore
456 instructions here will improve support for optimized
466 do_cleanups (back_to);
470 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
472 /* Frame pointer is fp. Frame size is constant. */
473 cache->framereg = ARM_FP_REGNUM;
474 cache->framesize = -regs[ARM_FP_REGNUM].k;
476 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
478 /* Frame pointer is r7. Frame size is constant. */
479 cache->framereg = THUMB_FP_REGNUM;
480 cache->framesize = -regs[THUMB_FP_REGNUM].k;
482 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
484 /* Try the stack pointer... this is a bit desperate. */
485 cache->framereg = ARM_SP_REGNUM;
486 cache->framesize = -regs[ARM_SP_REGNUM].k;
490 /* We're just out of luck. We don't know where the frame is. */
491 cache->framereg = -1;
492 cache->framesize = 0;
495 for (i = 0; i < 16; i++)
496 if (pv_area_find_reg (stack, gdbarch, i, &offset))
497 cache->saved_regs[i].addr = offset;
499 do_cleanups (back_to);
503 /* Advance the PC across any function entry prologue instructions to
504 reach some "real" code.
506 The APCS (ARM Procedure Call Standard) defines the following
510 [stmfd sp!, {a1,a2,a3,a4}]
511 stmfd sp!, {...,fp,ip,lr,pc}
512 [stfe f7, [sp, #-12]!]
513 [stfe f6, [sp, #-12]!]
514 [stfe f5, [sp, #-12]!]
515 [stfe f4, [sp, #-12]!]
516 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
519 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
521 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
524 CORE_ADDR func_addr, limit_pc;
525 struct symtab_and_line sal;
527 /* If we're in a dummy frame, don't even try to skip the prologue. */
528 if (deprecated_pc_in_call_dummy (gdbarch, pc))
531 /* See if we can determine the end of the prologue via the symbol table.
532 If so, then return either PC, or the PC after the prologue, whichever
534 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
536 CORE_ADDR post_prologue_pc
537 = skip_prologue_using_sal (gdbarch, func_addr);
538 if (post_prologue_pc != 0)
539 return max (pc, post_prologue_pc);
542 /* Can't determine prologue from the symbol table, need to examine
545 /* Find an upper limit on the function prologue using the debug
546 information. If the debug information could not be used to provide
547 that bound, then use an arbitrary large number as the upper bound. */
548 /* Like arm_scan_prologue, stop no later than pc + 64. */
549 limit_pc = skip_prologue_using_sal (gdbarch, pc);
551 limit_pc = pc + 64; /* Magic. */
554 /* Check if this is Thumb code. */
555 if (arm_pc_is_thumb (pc))
556 return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
558 for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
560 inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code);
562 /* "mov ip, sp" is no longer a required part of the prologue. */
563 if (inst == 0xe1a0c00d) /* mov ip, sp */
566 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
569 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
572 /* Some prologues begin with "str lr, [sp, #-4]!". */
573 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
576 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
579 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
582 /* Any insns after this point may float into the code, if it makes
583 for better instruction scheduling, so we skip them only if we
584 find them, but still consider the function to be frame-ful. */
586 /* We may have either one sfmfd instruction here, or several stfe
587 insns, depending on the version of floating point code we
589 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
592 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
595 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
598 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
601 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
602 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
603 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
606 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
607 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
608 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
611 /* Un-recognized instruction; stop scanning. */
615 return skip_pc; /* End of prologue */
619 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
620 This function decodes a Thumb function prologue to determine:
621 1) the size of the stack frame
622 2) which registers are saved on it
623 3) the offsets of saved regs
624 4) the offset from the stack pointer to the frame pointer
626 A typical Thumb function prologue would create this stack frame
627 (offsets relative to FP)
628 old SP -> 24 stack parameters
631 R7 -> 0 local variables (16 bytes)
632 SP -> -12 additional stack space (12 bytes)
633 The frame size would thus be 36 bytes, and the frame offset would be
634 12 bytes. The frame register is R7.
636 The comments for thumb_skip_prolog() describe the algorithm we use
637 to detect the end of the prolog. */
641 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
642 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
644 CORE_ADDR prologue_start;
645 CORE_ADDR prologue_end;
646 CORE_ADDR current_pc;
648 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
651 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
653 if (sal.line == 0) /* no line info, use current PC */
654 prologue_end = prev_pc;
655 else if (sal.end < prologue_end) /* next line begins after fn end */
656 prologue_end = sal.end; /* (probably means no prologue) */
659 /* We're in the boondocks: we have no idea where the start of the
663 prologue_end = min (prologue_end, prev_pc);
665 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
668 /* This function decodes an ARM function prologue to determine:
669 1) the size of the stack frame
670 2) which registers are saved on it
671 3) the offsets of saved regs
672 4) the offset from the stack pointer to the frame pointer
673 This information is stored in the "extra" fields of the frame_info.
675 There are two basic forms for the ARM prologue. The fixed argument
676 function call will look like:
679 stmfd sp!, {fp, ip, lr, pc}
683 Which would create this stack frame (offsets relative to FP):
684 IP -> 4 (caller's stack)
685 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
686 -4 LR (return address in caller)
687 -8 IP (copy of caller's SP)
689 SP -> -28 Local variables
691 The frame size would thus be 32 bytes, and the frame offset would be
692 28 bytes. The stmfd call can also save any of the vN registers it
693 plans to use, which increases the frame size accordingly.
695 Note: The stored PC is 8 off of the STMFD instruction that stored it
696 because the ARM Store instructions always store PC + 8 when you read
699 A variable argument function call will look like:
702 stmfd sp!, {a1, a2, a3, a4}
703 stmfd sp!, {fp, ip, lr, pc}
706 Which would create this stack frame (offsets relative to FP):
707 IP -> 20 (caller's stack)
712 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
713 -4 LR (return address in caller)
714 -8 IP (copy of caller's SP)
716 SP -> -28 Local variables
718 The frame size would thus be 48 bytes, and the frame offset would be
721 There is another potential complication, which is that the optimizer
722 will try to separate the store of fp in the "stmfd" instruction from
723 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
724 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
726 Also, note, the original version of the ARM toolchain claimed that there
729 instruction at the end of the prologue. I have never seen GCC produce
730 this, and the ARM docs don't mention it. We still test for it below in
736 arm_scan_prologue (struct frame_info *this_frame,
737 struct arm_prologue_cache *cache)
739 struct gdbarch *gdbarch = get_frame_arch (this_frame);
740 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
741 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
743 CORE_ADDR prologue_start, prologue_end, current_pc;
744 CORE_ADDR prev_pc = get_frame_pc (this_frame);
745 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
746 pv_t regs[ARM_FPS_REGNUM];
747 struct pv_area *stack;
748 struct cleanup *back_to;
751 /* Assume there is no frame until proven otherwise. */
752 cache->framereg = ARM_SP_REGNUM;
753 cache->framesize = 0;
755 /* Check for Thumb prologue. */
756 if (arm_frame_is_thumb (this_frame))
758 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
762 /* Find the function prologue. If we can't find the function in
763 the symbol table, peek in the stack frame to find the PC. */
764 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
767 /* One way to find the end of the prologue (which works well
768 for unoptimized code) is to do the following:
770 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
773 prologue_end = prev_pc;
774 else if (sal.end < prologue_end)
775 prologue_end = sal.end;
777 This mechanism is very accurate so long as the optimizer
778 doesn't move any instructions from the function body into the
779 prologue. If this happens, sal.end will be the last
780 instruction in the first hunk of prologue code just before
781 the first instruction that the scheduler has moved from
782 the body to the prologue.
784 In order to make sure that we scan all of the prologue
785 instructions, we use a slightly less accurate mechanism which
786 may scan more than necessary. To help compensate for this
787 lack of accuracy, the prologue scanning loop below contains
788 several clauses which'll cause the loop to terminate early if
789 an implausible prologue instruction is encountered.
795 is a suitable endpoint since it accounts for the largest
796 possible prologue plus up to five instructions inserted by
799 if (prologue_end > prologue_start + 64)
801 prologue_end = prologue_start + 64; /* See above. */
806 /* We have no symbol information. Our only option is to assume this
807 function has a standard stack frame and the normal frame register.
808 Then, we can find the value of our frame pointer on entrance to
809 the callee (or at the present moment if this is the innermost frame).
810 The value stored there should be the address of the stmfd + 8. */
812 LONGEST return_value;
814 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
815 if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
819 prologue_start = gdbarch_addr_bits_remove
820 (gdbarch, return_value) - 8;
821 prologue_end = prologue_start + 64; /* See above. */
825 if (prev_pc < prologue_end)
826 prologue_end = prev_pc;
828 /* Now search the prologue looking for instructions that set up the
829 frame pointer, adjust the stack pointer, and save registers.
831 Be careful, however, and if it doesn't look like a prologue,
832 don't try to scan it. If, for instance, a frameless function
833 begins with stmfd sp!, then we will tell ourselves there is
834 a frame, which will confuse stack traceback, as well as "finish"
835 and other operations that rely on a knowledge of the stack
838 In the APCS, the prologue should start with "mov ip, sp" so
839 if we don't see this as the first insn, we will stop.
841 [Note: This doesn't seem to be true any longer, so it's now an
842 optional part of the prologue. - Kevin Buettner, 2001-11-20]
844 [Note further: The "mov ip,sp" only seems to be missing in
845 frameless functions at optimization level "-O2" or above,
846 in which case it is often (but not always) replaced by
847 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
849 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
850 regs[regno] = pv_register (regno, 0);
851 stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
852 back_to = make_cleanup_free_pv_area (stack);
854 for (current_pc = prologue_start;
855 current_pc < prologue_end;
859 = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
861 if (insn == 0xe1a0c00d) /* mov ip, sp */
863 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
866 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
868 unsigned imm = insn & 0xff; /* immediate value */
869 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
870 imm = (imm >> rot) | (imm << (32 - rot));
871 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
874 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
876 unsigned imm = insn & 0xff; /* immediate value */
877 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
878 imm = (imm >> rot) | (imm << (32 - rot));
879 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
882 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
884 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
886 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
887 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
890 else if ((insn & 0xffff0000) == 0xe92d0000)
891 /* stmfd sp!, {..., fp, ip, lr, pc}
893 stmfd sp!, {a1, a2, a3, a4} */
895 int mask = insn & 0xffff;
897 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
900 /* Calculate offsets of saved registers. */
901 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
902 if (mask & (1 << regno))
904 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
905 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
908 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
909 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
910 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
912 /* No need to add this to saved_regs -- it's just an arg reg. */
915 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
916 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
917 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
919 /* No need to add this to saved_regs -- it's just an arg reg. */
922 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
924 unsigned imm = insn & 0xff; /* immediate value */
925 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
926 imm = (imm >> rot) | (imm << (32 - rot));
927 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
929 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
931 unsigned imm = insn & 0xff; /* immediate value */
932 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
933 imm = (imm >> rot) | (imm << (32 - rot));
934 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
936 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
937 && gdbarch_tdep (gdbarch)->have_fpa_registers)
939 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
942 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
943 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
944 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
946 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
947 && gdbarch_tdep (gdbarch)->have_fpa_registers)
950 unsigned int fp_start_reg, fp_bound_reg;
952 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
955 if ((insn & 0x800) == 0x800) /* N0 is set */
957 if ((insn & 0x40000) == 0x40000) /* N1 is set */
964 if ((insn & 0x40000) == 0x40000) /* N1 is set */
970 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
971 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
972 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
974 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
975 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
976 regs[fp_start_reg++]);
979 else if ((insn & 0xf0000000) != 0xe0000000)
980 break; /* Condition not true, exit early */
981 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
982 break; /* Don't scan past a block load */
984 /* The optimizer might shove anything into the prologue,
985 so we just skip what we don't recognize. */
989 /* The frame size is just the distance from the frame register
990 to the original stack pointer. */
991 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
993 /* Frame pointer is fp. */
994 cache->framereg = ARM_FP_REGNUM;
995 cache->framesize = -regs[ARM_FP_REGNUM].k;
997 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
999 /* Try the stack pointer... this is a bit desperate. */
1000 cache->framereg = ARM_SP_REGNUM;
1001 cache->framesize = -regs[ARM_SP_REGNUM].k;
1005 /* We're just out of luck. We don't know where the frame is. */
1006 cache->framereg = -1;
1007 cache->framesize = 0;
1010 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1011 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1012 cache->saved_regs[regno].addr = offset;
1014 do_cleanups (back_to);
1017 static struct arm_prologue_cache *
1018 arm_make_prologue_cache (struct frame_info *this_frame)
1021 struct arm_prologue_cache *cache;
1022 CORE_ADDR unwound_fp;
1024 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1025 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1027 arm_scan_prologue (this_frame, cache);
1029 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1030 if (unwound_fp == 0)
1033 cache->prev_sp = unwound_fp + cache->framesize;
1035 /* Calculate actual addresses of saved registers using offsets
1036 determined by arm_scan_prologue. */
1037 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1038 if (trad_frame_addr_p (cache->saved_regs, reg))
1039 cache->saved_regs[reg].addr += cache->prev_sp;
1044 /* Our frame ID for a normal frame is the current function's starting PC
1045 and the caller's SP when we were called. */
1048 arm_prologue_this_id (struct frame_info *this_frame,
1050 struct frame_id *this_id)
1052 struct arm_prologue_cache *cache;
1056 if (*this_cache == NULL)
1057 *this_cache = arm_make_prologue_cache (this_frame);
1058 cache = *this_cache;
1060 /* This is meant to halt the backtrace at "_start". */
1061 pc = get_frame_pc (this_frame);
1062 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1065 /* If we've hit a wall, stop. */
1066 if (cache->prev_sp == 0)
1069 func = get_frame_func (this_frame);
1070 id = frame_id_build (cache->prev_sp, func);
1074 static struct value *
1075 arm_prologue_prev_register (struct frame_info *this_frame,
1079 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1080 struct arm_prologue_cache *cache;
1082 if (*this_cache == NULL)
1083 *this_cache = arm_make_prologue_cache (this_frame);
1084 cache = *this_cache;
1086 /* If we are asked to unwind the PC, then we need to return the LR
1087 instead. The prologue may save PC, but it will point into this
1088 frame's prologue, not the next frame's resume location. Also
1089 strip the saved T bit. A valid LR may have the low bit set, but
1090 a valid PC never does. */
1091 if (prev_regnum == ARM_PC_REGNUM)
1095 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1096 return frame_unwind_got_constant (this_frame, prev_regnum,
1097 arm_addr_bits_remove (gdbarch, lr));
1100 /* SP is generally not saved to the stack, but this frame is
1101 identified by the next frame's stack pointer at the time of the call.
1102 The value was already reconstructed into PREV_SP. */
1103 if (prev_regnum == ARM_SP_REGNUM)
1104 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1106 /* The CPSR may have been changed by the call instruction and by the
1107 called function. The only bit we can reconstruct is the T bit,
1108 by checking the low bit of LR as of the call. This is a reliable
1109 indicator of Thumb-ness except for some ARM v4T pre-interworking
1110 Thumb code, which could get away with a clear low bit as long as
1111 the called function did not use bx. Guess that all other
1112 bits are unchanged; the condition flags are presumably lost,
1113 but the processor status is likely valid. */
1114 if (prev_regnum == ARM_PS_REGNUM)
1118 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1119 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1120 if (IS_THUMB_ADDR (lr))
1124 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1127 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1131 struct frame_unwind arm_prologue_unwind = {
1133 arm_prologue_this_id,
1134 arm_prologue_prev_register,
1136 default_frame_sniffer
1139 static struct arm_prologue_cache *
1140 arm_make_stub_cache (struct frame_info *this_frame)
1143 struct arm_prologue_cache *cache;
1144 CORE_ADDR unwound_fp;
1146 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1147 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1149 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
1154 /* Our frame ID for a stub frame is the current SP and LR. */
1157 arm_stub_this_id (struct frame_info *this_frame,
1159 struct frame_id *this_id)
1161 struct arm_prologue_cache *cache;
1163 if (*this_cache == NULL)
1164 *this_cache = arm_make_stub_cache (this_frame);
1165 cache = *this_cache;
1167 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
1171 arm_stub_unwind_sniffer (const struct frame_unwind *self,
1172 struct frame_info *this_frame,
1173 void **this_prologue_cache)
1175 CORE_ADDR addr_in_block;
1178 addr_in_block = get_frame_address_in_block (this_frame);
1179 if (in_plt_section (addr_in_block, NULL)
1180 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1186 struct frame_unwind arm_stub_unwind = {
1189 arm_prologue_prev_register,
1191 arm_stub_unwind_sniffer
1195 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1197 struct arm_prologue_cache *cache;
1199 if (*this_cache == NULL)
1200 *this_cache = arm_make_prologue_cache (this_frame);
1201 cache = *this_cache;
1203 return cache->prev_sp - cache->framesize;
1206 struct frame_base arm_normal_base = {
1207 &arm_prologue_unwind,
1208 arm_normal_frame_base,
1209 arm_normal_frame_base,
1210 arm_normal_frame_base
1213 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1214 dummy frame. The frame ID's base needs to match the TOS value
1215 saved by save_dummy_frame_tos() and returned from
1216 arm_push_dummy_call, and the PC needs to match the dummy frame's
1219 static struct frame_id
1220 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1222 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1223 get_frame_pc (this_frame));
1226 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1227 be used to construct the previous frame's ID, after looking up the
1228 containing function). */
1231 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1234 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1235 return arm_addr_bits_remove (gdbarch, pc);
1239 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1241 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1244 static struct value *
1245 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1248 struct gdbarch * gdbarch = get_frame_arch (this_frame);
1254 /* The PC is normally copied from the return column, which
1255 describes saves of LR. However, that version may have an
1256 extra bit set to indicate Thumb state. The bit is not
1258 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1259 return frame_unwind_got_constant (this_frame, regnum,
1260 arm_addr_bits_remove (gdbarch, lr));
1263 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1264 cpsr = get_frame_register_unsigned (this_frame, regnum);
1265 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1266 if (IS_THUMB_ADDR (lr))
1270 return frame_unwind_got_constant (this_frame, regnum, cpsr);
1273 internal_error (__FILE__, __LINE__,
1274 _("Unexpected register %d"), regnum);
1279 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1280 struct dwarf2_frame_state_reg *reg,
1281 struct frame_info *this_frame)
1287 reg->how = DWARF2_FRAME_REG_FN;
1288 reg->loc.fn = arm_dwarf2_prev_register;
1291 reg->how = DWARF2_FRAME_REG_CFA;
1296 /* When arguments must be pushed onto the stack, they go on in reverse
1297 order. The code below implements a FILO (stack) to do this. */
1302 struct stack_item *prev;
1306 static struct stack_item *
1307 push_stack_item (struct stack_item *prev, void *contents, int len)
1309 struct stack_item *si;
1310 si = xmalloc (sizeof (struct stack_item));
1311 si->data = xmalloc (len);
1314 memcpy (si->data, contents, len);
1318 static struct stack_item *
1319 pop_stack_item (struct stack_item *si)
1321 struct stack_item *dead = si;
1329 /* Return the alignment (in bytes) of the given type. */
1332 arm_type_align (struct type *t)
1338 t = check_typedef (t);
1339 switch (TYPE_CODE (t))
1342 /* Should never happen. */
1343 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1347 case TYPE_CODE_ENUM:
1351 case TYPE_CODE_RANGE:
1352 case TYPE_CODE_BITSTRING:
1354 case TYPE_CODE_CHAR:
1355 case TYPE_CODE_BOOL:
1356 return TYPE_LENGTH (t);
1358 case TYPE_CODE_ARRAY:
1359 case TYPE_CODE_COMPLEX:
1360 /* TODO: What about vector types? */
1361 return arm_type_align (TYPE_TARGET_TYPE (t));
1363 case TYPE_CODE_STRUCT:
1364 case TYPE_CODE_UNION:
1366 for (n = 0; n < TYPE_NFIELDS (t); n++)
1368 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1376 /* Possible base types for a candidate for passing and returning in
1379 enum arm_vfp_cprc_base_type
1388 /* The length of one element of base type B. */
1391 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b)
1395 case VFP_CPRC_SINGLE:
1397 case VFP_CPRC_DOUBLE:
1399 case VFP_CPRC_VEC64:
1401 case VFP_CPRC_VEC128:
1404 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
1409 /* The character ('s', 'd' or 'q') for the type of VFP register used
1410 for passing base type B. */
1413 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b)
1417 case VFP_CPRC_SINGLE:
1419 case VFP_CPRC_DOUBLE:
1421 case VFP_CPRC_VEC64:
1423 case VFP_CPRC_VEC128:
1426 internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."),
1431 /* Determine whether T may be part of a candidate for passing and
1432 returning in VFP registers, ignoring the limit on the total number
1433 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1434 classification of the first valid component found; if it is not
1435 VFP_CPRC_UNKNOWN, all components must have the same classification
1436 as *BASE_TYPE. If it is found that T contains a type not permitted
1437 for passing and returning in VFP registers, a type differently
1438 classified from *BASE_TYPE, or two types differently classified
1439 from each other, return -1, otherwise return the total number of
1440 base-type elements found (possibly 0 in an empty structure or
1441 array). Vectors and complex types are not currently supported,
1442 matching the generic AAPCS support. */
1445 arm_vfp_cprc_sub_candidate (struct type *t,
1446 enum arm_vfp_cprc_base_type *base_type)
1448 t = check_typedef (t);
1449 switch (TYPE_CODE (t))
1452 switch (TYPE_LENGTH (t))
1455 if (*base_type == VFP_CPRC_UNKNOWN)
1456 *base_type = VFP_CPRC_SINGLE;
1457 else if (*base_type != VFP_CPRC_SINGLE)
1462 if (*base_type == VFP_CPRC_UNKNOWN)
1463 *base_type = VFP_CPRC_DOUBLE;
1464 else if (*base_type != VFP_CPRC_DOUBLE)
1473 case TYPE_CODE_ARRAY:
1477 count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type);
1480 if (TYPE_LENGTH (t) == 0)
1482 gdb_assert (count == 0);
1485 else if (count == 0)
1487 unitlen = arm_vfp_cprc_unit_length (*base_type);
1488 gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0);
1489 return TYPE_LENGTH (t) / unitlen;
1493 case TYPE_CODE_STRUCT:
1498 for (i = 0; i < TYPE_NFIELDS (t); i++)
1500 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
1502 if (sub_count == -1)
1506 if (TYPE_LENGTH (t) == 0)
1508 gdb_assert (count == 0);
1511 else if (count == 0)
1513 unitlen = arm_vfp_cprc_unit_length (*base_type);
1514 if (TYPE_LENGTH (t) != unitlen * count)
1519 case TYPE_CODE_UNION:
1524 for (i = 0; i < TYPE_NFIELDS (t); i++)
1526 int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i),
1528 if (sub_count == -1)
1530 count = (count > sub_count ? count : sub_count);
1532 if (TYPE_LENGTH (t) == 0)
1534 gdb_assert (count == 0);
1537 else if (count == 0)
1539 unitlen = arm_vfp_cprc_unit_length (*base_type);
1540 if (TYPE_LENGTH (t) != unitlen * count)
1552 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1553 if passed to or returned from a non-variadic function with the VFP
1554 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1555 *BASE_TYPE to the base type for T and *COUNT to the number of
1556 elements of that base type before returning. */
1559 arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type,
1562 enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN;
1563 int c = arm_vfp_cprc_sub_candidate (t, &b);
1564 if (c <= 0 || c > 4)
1571 /* Return 1 if the VFP ABI should be used for passing arguments to and
1572 returning values from a function of type FUNC_TYPE, 0
1576 arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type)
1578 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1579 /* Variadic functions always use the base ABI. Assume that functions
1580 without debug info are not variadic. */
1581 if (func_type && TYPE_VARARGS (check_typedef (func_type)))
1583 /* The VFP ABI is only supported as a variant of AAPCS. */
1584 if (tdep->arm_abi != ARM_ABI_AAPCS)
1586 return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP;
1589 /* We currently only support passing parameters in integer registers, which
1590 conforms with GCC's default model, and VFP argument passing following
1591 the VFP variant of AAPCS. Several other variants exist and
1592 we should probably support some of them based on the selected ABI. */
1595 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1596 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1597 struct value **args, CORE_ADDR sp, int struct_return,
1598 CORE_ADDR struct_addr)
1600 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1604 struct stack_item *si = NULL;
1607 unsigned vfp_regs_free = (1 << 16) - 1;
1609 /* Determine the type of this function and whether the VFP ABI
1611 ftype = check_typedef (value_type (function));
1612 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
1613 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
1614 use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype);
1616 /* Set the return address. For the ARM, the return breakpoint is
1617 always at BP_ADDR. */
1618 /* XXX Fix for Thumb. */
1619 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1621 /* Walk through the list of args and determine how large a temporary
1622 stack is required. Need to take care here as structs may be
1623 passed on the stack, and we have to to push them. */
1626 argreg = ARM_A1_REGNUM;
1629 /* The struct_return pointer occupies the first parameter
1630 passing register. */
1634 fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
1635 gdbarch_register_name (gdbarch, argreg),
1636 paddress (gdbarch, struct_addr));
1637 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1641 for (argnum = 0; argnum < nargs; argnum++)
1644 struct type *arg_type;
1645 struct type *target_type;
1646 enum type_code typecode;
1649 enum arm_vfp_cprc_base_type vfp_base_type;
1651 int may_use_core_reg = 1;
1653 arg_type = check_typedef (value_type (args[argnum]));
1654 len = TYPE_LENGTH (arg_type);
1655 target_type = TYPE_TARGET_TYPE (arg_type);
1656 typecode = TYPE_CODE (arg_type);
1657 val = value_contents_writeable (args[argnum]);
1659 align = arm_type_align (arg_type);
1660 /* Round alignment up to a whole number of words. */
1661 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1662 /* Different ABIs have different maximum alignments. */
1663 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1665 /* The APCS ABI only requires word alignment. */
1666 align = INT_REGISTER_SIZE;
1670 /* The AAPCS requires at most doubleword alignment. */
1671 if (align > INT_REGISTER_SIZE * 2)
1672 align = INT_REGISTER_SIZE * 2;
1676 && arm_vfp_call_candidate (arg_type, &vfp_base_type,
1684 /* Because this is a CPRC it cannot go in a core register or
1685 cause a core register to be skipped for alignment.
1686 Either it goes in VFP registers and the rest of this loop
1687 iteration is skipped for this argument, or it goes on the
1688 stack (and the stack alignment code is correct for this
1690 may_use_core_reg = 0;
1692 unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
1693 shift = unit_length / 4;
1694 mask = (1 << (shift * vfp_base_count)) - 1;
1695 for (regno = 0; regno < 16; regno += shift)
1696 if (((vfp_regs_free >> regno) & mask) == mask)
1705 vfp_regs_free &= ~(mask << regno);
1706 reg_scaled = regno / shift;
1707 reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
1708 for (i = 0; i < vfp_base_count; i++)
1712 sprintf (name_buf, "%c%d", reg_char, reg_scaled + i);
1713 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
1715 regcache_cooked_write (regcache, regnum,
1716 val + i * unit_length);
1722 /* This CPRC could not go in VFP registers, so all VFP
1723 registers are now marked as used. */
1728 /* Push stack padding for dowubleword alignment. */
1729 if (nstack & (align - 1))
1731 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1732 nstack += INT_REGISTER_SIZE;
1735 /* Doubleword aligned quantities must go in even register pairs. */
1736 if (may_use_core_reg
1737 && argreg <= ARM_LAST_ARG_REGNUM
1738 && align > INT_REGISTER_SIZE
1742 /* If the argument is a pointer to a function, and it is a
1743 Thumb function, create a LOCAL copy of the value and set
1744 the THUMB bit in it. */
1745 if (TYPE_CODE_PTR == typecode
1746 && target_type != NULL
1747 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1749 CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order);
1750 if (arm_pc_is_thumb (regval))
1753 store_unsigned_integer (val, len, byte_order,
1754 MAKE_THUMB_ADDR (regval));
1758 /* Copy the argument to general registers or the stack in
1759 register-sized pieces. Large arguments are split between
1760 registers and stack. */
1763 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1765 if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM)
1767 /* The argument is being passed in a general purpose
1770 = extract_unsigned_integer (val, partial_len, byte_order);
1771 if (byte_order == BFD_ENDIAN_BIG)
1772 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1774 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1776 gdbarch_register_name
1778 phex (regval, INT_REGISTER_SIZE));
1779 regcache_cooked_write_unsigned (regcache, argreg, regval);
1784 /* Push the arguments onto the stack. */
1786 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1788 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1789 nstack += INT_REGISTER_SIZE;
1796 /* If we have an odd number of words to push, then decrement the stack
1797 by one word now, so first stack argument will be dword aligned. */
1804 write_memory (sp, si->data, si->len);
1805 si = pop_stack_item (si);
1808 /* Finally, update teh SP register. */
1809 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1815 /* Always align the frame to an 8-byte boundary. This is required on
1816 some platforms and harmless on the rest. */
1819 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1821 /* Align the stack to eight bytes. */
1822 return sp & ~ (CORE_ADDR) 7;
1826 print_fpu_flags (int flags)
1828 if (flags & (1 << 0))
1829 fputs ("IVO ", stdout);
1830 if (flags & (1 << 1))
1831 fputs ("DVZ ", stdout);
1832 if (flags & (1 << 2))
1833 fputs ("OFL ", stdout);
1834 if (flags & (1 << 3))
1835 fputs ("UFL ", stdout);
1836 if (flags & (1 << 4))
1837 fputs ("INX ", stdout);
1841 /* Print interesting information about the floating point processor
1842 (if present) or emulator. */
1844 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1845 struct frame_info *frame, const char *args)
1847 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1850 type = (status >> 24) & 127;
1851 if (status & (1 << 31))
1852 printf (_("Hardware FPU type %d\n"), type);
1854 printf (_("Software FPU type %d\n"), type);
1855 /* i18n: [floating point unit] mask */
1856 fputs (_("mask: "), stdout);
1857 print_fpu_flags (status >> 16);
1858 /* i18n: [floating point unit] flags */
1859 fputs (_("flags: "), stdout);
1860 print_fpu_flags (status);
1863 /* Construct the ARM extended floating point type. */
1864 static struct type *
1865 arm_ext_type (struct gdbarch *gdbarch)
1867 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1869 if (!tdep->arm_ext_type)
1871 = arch_float_type (gdbarch, -1, "builtin_type_arm_ext",
1872 floatformats_arm_ext);
1874 return tdep->arm_ext_type;
1877 /* Return the GDB type object for the "standard" data type of data in
1880 static struct type *
1881 arm_register_type (struct gdbarch *gdbarch, int regnum)
1883 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1884 return arm_ext_type (gdbarch);
1885 else if (regnum == ARM_SP_REGNUM)
1886 return builtin_type (gdbarch)->builtin_data_ptr;
1887 else if (regnum == ARM_PC_REGNUM)
1888 return builtin_type (gdbarch)->builtin_func_ptr;
1889 else if (regnum >= ARRAY_SIZE (arm_register_names))
1890 /* These registers are only supported on targets which supply
1891 an XML description. */
1892 return builtin_type (gdbarch)->builtin_int0;
1894 return builtin_type (gdbarch)->builtin_uint32;
1897 /* Map a DWARF register REGNUM onto the appropriate GDB register
1901 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1903 /* Core integer regs. */
1904 if (reg >= 0 && reg <= 15)
1907 /* Legacy FPA encoding. These were once used in a way which
1908 overlapped with VFP register numbering, so their use is
1909 discouraged, but GDB doesn't support the ARM toolchain
1910 which used them for VFP. */
1911 if (reg >= 16 && reg <= 23)
1912 return ARM_F0_REGNUM + reg - 16;
1914 /* New assignments for the FPA registers. */
1915 if (reg >= 96 && reg <= 103)
1916 return ARM_F0_REGNUM + reg - 96;
1918 /* WMMX register assignments. */
1919 if (reg >= 104 && reg <= 111)
1920 return ARM_WCGR0_REGNUM + reg - 104;
1922 if (reg >= 112 && reg <= 127)
1923 return ARM_WR0_REGNUM + reg - 112;
1925 if (reg >= 192 && reg <= 199)
1926 return ARM_WC0_REGNUM + reg - 192;
1931 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1933 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1936 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
1938 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1939 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1941 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1942 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1944 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1945 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1947 if (reg < NUM_GREGS)
1948 return SIM_ARM_R0_REGNUM + reg;
1951 if (reg < NUM_FREGS)
1952 return SIM_ARM_FP0_REGNUM + reg;
1955 if (reg < NUM_SREGS)
1956 return SIM_ARM_FPS_REGNUM + reg;
1959 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1962 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1963 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1964 It is thought that this is is the floating-point register format on
1965 little-endian systems. */
1968 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1969 void *dbl, int endianess)
1973 if (endianess == BFD_ENDIAN_BIG)
1974 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1976 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1978 floatformat_from_doublest (fmt, &d, dbl);
1982 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1987 floatformat_to_doublest (fmt, ptr, &d);
1988 if (endianess == BFD_ENDIAN_BIG)
1989 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1991 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1996 condition_true (unsigned long cond, unsigned long status_reg)
1998 if (cond == INST_AL || cond == INST_NV)
2004 return ((status_reg & FLAG_Z) != 0);
2006 return ((status_reg & FLAG_Z) == 0);
2008 return ((status_reg & FLAG_C) != 0);
2010 return ((status_reg & FLAG_C) == 0);
2012 return ((status_reg & FLAG_N) != 0);
2014 return ((status_reg & FLAG_N) == 0);
2016 return ((status_reg & FLAG_V) != 0);
2018 return ((status_reg & FLAG_V) == 0);
2020 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
2022 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
2024 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
2026 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
2028 return (((status_reg & FLAG_Z) == 0) &&
2029 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
2031 return (((status_reg & FLAG_Z) != 0) ||
2032 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
2037 /* Support routines for single stepping. Calculate the next PC value. */
2038 #define submask(x) ((1L << ((x) + 1)) - 1)
2039 #define bit(obj,st) (((obj) >> (st)) & 1)
2040 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
2041 #define sbits(obj,st,fn) \
2042 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
2043 #define BranchDest(addr,instr) \
2044 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
2047 static unsigned long
2048 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
2049 unsigned long pc_val, unsigned long status_reg)
2051 unsigned long res, shift;
2052 int rm = bits (inst, 0, 3);
2053 unsigned long shifttype = bits (inst, 5, 6);
2057 int rs = bits (inst, 8, 11);
2058 shift = (rs == 15 ? pc_val + 8
2059 : get_frame_register_unsigned (frame, rs)) & 0xFF;
2062 shift = bits (inst, 7, 11);
2065 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
2066 + (bit (inst, 4) ? 12 : 8))
2067 : get_frame_register_unsigned (frame, rm));
2072 res = shift >= 32 ? 0 : res << shift;
2076 res = shift >= 32 ? 0 : res >> shift;
2082 res = ((res & 0x80000000L)
2083 ? ~((~res) >> shift) : res >> shift);
2086 case 3: /* ROR/RRX */
2089 res = (res >> 1) | (carry ? 0x80000000L : 0);
2091 res = (res >> shift) | (res << (32 - shift));
2095 return res & 0xffffffff;
2098 /* Return number of 1-bits in VAL. */
2101 bitcount (unsigned long val)
2104 for (nbits = 0; val != 0; nbits++)
2105 val &= val - 1; /* delete rightmost 1-bit in val */
2110 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
2112 struct gdbarch *gdbarch = get_frame_arch (frame);
2113 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2114 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2115 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
2116 unsigned short inst1;
2117 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
2118 unsigned long offset;
2120 inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
2122 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
2126 /* Fetch the saved PC from the stack. It's stored above
2127 all of the other registers. */
2128 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
2129 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
2130 nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order);
2131 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2133 error (_("Infinite loop detected"));
2135 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
2137 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
2138 unsigned long cond = bits (inst1, 8, 11);
2139 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
2140 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
2142 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
2144 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
2146 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
2148 unsigned short inst2;
2149 inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
2150 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
2151 nextpc = pc_val + offset;
2152 /* For BLX make sure to clear the low bits. */
2153 if (bits (inst2, 11, 12) == 1)
2154 nextpc = nextpc & 0xfffffffc;
2156 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
2158 if (bits (inst1, 3, 6) == 0x0f)
2161 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
2163 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2165 error (_("Infinite loop detected"));
2172 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
2174 struct gdbarch *gdbarch = get_frame_arch (frame);
2175 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2176 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2177 unsigned long pc_val;
2178 unsigned long this_instr;
2179 unsigned long status;
2182 if (arm_frame_is_thumb (frame))
2183 return thumb_get_next_pc (frame, pc);
2185 pc_val = (unsigned long) pc;
2186 this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
2188 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
2189 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
2191 if (bits (this_instr, 28, 31) == INST_NV)
2192 switch (bits (this_instr, 24, 27))
2197 /* Branch with Link and change to Thumb. */
2198 nextpc = BranchDest (pc, this_instr);
2199 nextpc |= bit (this_instr, 24) << 1;
2201 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2203 error (_("Infinite loop detected"));
2209 /* Coprocessor register transfer. */
2210 if (bits (this_instr, 12, 15) == 15)
2211 error (_("Invalid update to pc in instruction"));
2214 else if (condition_true (bits (this_instr, 28, 31), status))
2216 switch (bits (this_instr, 24, 27))
2219 case 0x1: /* data processing */
2223 unsigned long operand1, operand2, result = 0;
2227 if (bits (this_instr, 12, 15) != 15)
2230 if (bits (this_instr, 22, 25) == 0
2231 && bits (this_instr, 4, 7) == 9) /* multiply */
2232 error (_("Invalid update to pc in instruction"));
2234 /* BX <reg>, BLX <reg> */
2235 if (bits (this_instr, 4, 27) == 0x12fff1
2236 || bits (this_instr, 4, 27) == 0x12fff3)
2238 rn = bits (this_instr, 0, 3);
2239 result = (rn == 15) ? pc_val + 8
2240 : get_frame_register_unsigned (frame, rn);
2241 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2245 error (_("Infinite loop detected"));
2250 /* Multiply into PC */
2251 c = (status & FLAG_C) ? 1 : 0;
2252 rn = bits (this_instr, 16, 19);
2253 operand1 = (rn == 15) ? pc_val + 8
2254 : get_frame_register_unsigned (frame, rn);
2256 if (bit (this_instr, 25))
2258 unsigned long immval = bits (this_instr, 0, 7);
2259 unsigned long rotate = 2 * bits (this_instr, 8, 11);
2260 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
2263 else /* operand 2 is a shifted register */
2264 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
2266 switch (bits (this_instr, 21, 24))
2269 result = operand1 & operand2;
2273 result = operand1 ^ operand2;
2277 result = operand1 - operand2;
2281 result = operand2 - operand1;
2285 result = operand1 + operand2;
2289 result = operand1 + operand2 + c;
2293 result = operand1 - operand2 + c;
2297 result = operand2 - operand1 + c;
2303 case 0xb: /* tst, teq, cmp, cmn */
2304 result = (unsigned long) nextpc;
2308 result = operand1 | operand2;
2312 /* Always step into a function. */
2317 result = operand1 & ~operand2;
2324 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2328 error (_("Infinite loop detected"));
2333 case 0x5: /* data transfer */
2336 if (bit (this_instr, 20))
2339 if (bits (this_instr, 12, 15) == 15)
2345 if (bit (this_instr, 22))
2346 error (_("Invalid update to pc in instruction"));
2348 /* byte write to PC */
2349 rn = bits (this_instr, 16, 19);
2350 base = (rn == 15) ? pc_val + 8
2351 : get_frame_register_unsigned (frame, rn);
2352 if (bit (this_instr, 24))
2355 int c = (status & FLAG_C) ? 1 : 0;
2356 unsigned long offset =
2357 (bit (this_instr, 25)
2358 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
2359 : bits (this_instr, 0, 11));
2361 if (bit (this_instr, 23))
2366 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
2369 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2372 error (_("Infinite loop detected"));
2378 case 0x9: /* block transfer */
2379 if (bit (this_instr, 20))
2382 if (bit (this_instr, 15))
2387 if (bit (this_instr, 23))
2390 unsigned long reglist = bits (this_instr, 0, 14);
2391 offset = bitcount (reglist) * 4;
2392 if (bit (this_instr, 24)) /* pre */
2395 else if (bit (this_instr, 24))
2399 unsigned long rn_val =
2400 get_frame_register_unsigned (frame,
2401 bits (this_instr, 16, 19));
2403 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2407 nextpc = gdbarch_addr_bits_remove
2410 error (_("Infinite loop detected"));
2415 case 0xb: /* branch & link */
2416 case 0xa: /* branch */
2418 nextpc = BranchDest (pc, this_instr);
2420 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2422 error (_("Infinite loop detected"));
2428 case 0xe: /* coproc ops */
2433 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
2441 /* single_step() is called just before we want to resume the inferior,
2442 if we want to single-step it but there is no hardware or kernel
2443 single-step support. We find the target of the coming instruction
2444 and breakpoint it. */
2447 arm_software_single_step (struct frame_info *frame)
2449 struct gdbarch *gdbarch = get_frame_arch (frame);
2451 /* NOTE: This may insert the wrong breakpoint instruction when
2452 single-stepping over a mode-changing instruction, if the
2453 CPSR heuristics are used. */
2455 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
2456 insert_single_step_breakpoint (gdbarch, next_pc);
2461 #include "bfd-in2.h"
2462 #include "libcoff.h"
2465 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2467 if (arm_pc_is_thumb (memaddr))
2469 static asymbol *asym;
2470 static combined_entry_type ce;
2471 static struct coff_symbol_struct csym;
2472 static struct bfd fake_bfd;
2473 static bfd_target fake_target;
2475 if (csym.native == NULL)
2477 /* Create a fake symbol vector containing a Thumb symbol.
2478 This is solely so that the code in print_insn_little_arm()
2479 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2480 the presence of a Thumb symbol and switch to decoding
2481 Thumb instructions. */
2483 fake_target.flavour = bfd_target_coff_flavour;
2484 fake_bfd.xvec = &fake_target;
2485 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2487 csym.symbol.the_bfd = &fake_bfd;
2488 csym.symbol.name = "fake";
2489 asym = (asymbol *) & csym;
2492 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2493 info->symbols = &asym;
2496 info->symbols = NULL;
2498 if (info->endian == BFD_ENDIAN_BIG)
2499 return print_insn_big_arm (memaddr, info);
2501 return print_insn_little_arm (memaddr, info);
2504 /* The following define instruction sequences that will cause ARM
2505 cpu's to take an undefined instruction trap. These are used to
2506 signal a breakpoint to GDB.
2508 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2509 modes. A different instruction is required for each mode. The ARM
2510 cpu's can also be big or little endian. Thus four different
2511 instructions are needed to support all cases.
2513 Note: ARMv4 defines several new instructions that will take the
2514 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2515 not in fact add the new instructions. The new undefined
2516 instructions in ARMv4 are all instructions that had no defined
2517 behaviour in earlier chips. There is no guarantee that they will
2518 raise an exception, but may be treated as NOP's. In practice, it
2519 may only safe to rely on instructions matching:
2521 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2522 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2523 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2525 Even this may only true if the condition predicate is true. The
2526 following use a condition predicate of ALWAYS so it is always TRUE.
2528 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2529 and NetBSD all use a software interrupt rather than an undefined
2530 instruction to force a trap. This can be handled by by the
2531 abi-specific code during establishment of the gdbarch vector. */
2533 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2534 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2535 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2536 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2538 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2539 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2540 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2541 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2543 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2544 the program counter value to determine whether a 16-bit or 32-bit
2545 breakpoint should be used. It returns a pointer to a string of
2546 bytes that encode a breakpoint instruction, stores the length of
2547 the string to *lenptr, and adjusts the program counter (if
2548 necessary) to point to the actual memory location where the
2549 breakpoint should be inserted. */
2551 static const unsigned char *
2552 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
2554 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2556 if (arm_pc_is_thumb (*pcptr))
2558 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2559 *lenptr = tdep->thumb_breakpoint_size;
2560 return tdep->thumb_breakpoint;
2564 *lenptr = tdep->arm_breakpoint_size;
2565 return tdep->arm_breakpoint;
2569 /* Extract from an array REGBUF containing the (raw) register state a
2570 function return value of type TYPE, and copy that, in virtual
2571 format, into VALBUF. */
2574 arm_extract_return_value (struct type *type, struct regcache *regs,
2577 struct gdbarch *gdbarch = get_regcache_arch (regs);
2578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2580 if (TYPE_CODE_FLT == TYPE_CODE (type))
2582 switch (gdbarch_tdep (gdbarch)->fp_model)
2586 /* The value is in register F0 in internal format. We need to
2587 extract the raw value and then convert it to the desired
2589 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2591 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2592 convert_from_extended (floatformat_from_type (type), tmpbuf,
2593 valbuf, gdbarch_byte_order (gdbarch));
2597 case ARM_FLOAT_SOFT_FPA:
2598 case ARM_FLOAT_SOFT_VFP:
2599 /* ARM_FLOAT_VFP can arise if this is a variadic function so
2600 not using the VFP ABI code. */
2602 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2603 if (TYPE_LENGTH (type) > 4)
2604 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2605 valbuf + INT_REGISTER_SIZE);
2610 (__FILE__, __LINE__,
2611 _("arm_extract_return_value: Floating point model not supported"));
2615 else if (TYPE_CODE (type) == TYPE_CODE_INT
2616 || TYPE_CODE (type) == TYPE_CODE_CHAR
2617 || TYPE_CODE (type) == TYPE_CODE_BOOL
2618 || TYPE_CODE (type) == TYPE_CODE_PTR
2619 || TYPE_CODE (type) == TYPE_CODE_REF
2620 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2622 /* If the the type is a plain integer, then the access is
2623 straight-forward. Otherwise we have to play around a bit more. */
2624 int len = TYPE_LENGTH (type);
2625 int regno = ARM_A1_REGNUM;
2630 /* By using store_unsigned_integer we avoid having to do
2631 anything special for small big-endian values. */
2632 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2633 store_unsigned_integer (valbuf,
2634 (len > INT_REGISTER_SIZE
2635 ? INT_REGISTER_SIZE : len),
2637 len -= INT_REGISTER_SIZE;
2638 valbuf += INT_REGISTER_SIZE;
2643 /* For a structure or union the behaviour is as if the value had
2644 been stored to word-aligned memory and then loaded into
2645 registers with 32-bit load instruction(s). */
2646 int len = TYPE_LENGTH (type);
2647 int regno = ARM_A1_REGNUM;
2648 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2652 regcache_cooked_read (regs, regno++, tmpbuf);
2653 memcpy (valbuf, tmpbuf,
2654 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2655 len -= INT_REGISTER_SIZE;
2656 valbuf += INT_REGISTER_SIZE;
2662 /* Will a function return an aggregate type in memory or in a
2663 register? Return 0 if an aggregate type can be returned in a
2664 register, 1 if it must be returned in memory. */
2667 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2670 enum type_code code;
2672 CHECK_TYPEDEF (type);
2674 /* In the ARM ABI, "integer" like aggregate types are returned in
2675 registers. For an aggregate type to be integer like, its size
2676 must be less than or equal to INT_REGISTER_SIZE and the
2677 offset of each addressable subfield must be zero. Note that bit
2678 fields are not addressable, and all addressable subfields of
2679 unions always start at offset zero.
2681 This function is based on the behaviour of GCC 2.95.1.
2682 See: gcc/arm.c: arm_return_in_memory() for details.
2684 Note: All versions of GCC before GCC 2.95.2 do not set up the
2685 parameters correctly for a function returning the following
2686 structure: struct { float f;}; This should be returned in memory,
2687 not a register. Richard Earnshaw sent me a patch, but I do not
2688 know of any way to detect if a function like the above has been
2689 compiled with the correct calling convention. */
2691 /* All aggregate types that won't fit in a register must be returned
2693 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2698 /* The AAPCS says all aggregates not larger than a word are returned
2700 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2703 /* The only aggregate types that can be returned in a register are
2704 structs and unions. Arrays must be returned in memory. */
2705 code = TYPE_CODE (type);
2706 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2711 /* Assume all other aggregate types can be returned in a register.
2712 Run a check for structures, unions and arrays. */
2715 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2718 /* Need to check if this struct/union is "integer" like. For
2719 this to be true, its size must be less than or equal to
2720 INT_REGISTER_SIZE and the offset of each addressable
2721 subfield must be zero. Note that bit fields are not
2722 addressable, and unions always start at offset zero. If any
2723 of the subfields is a floating point type, the struct/union
2724 cannot be an integer type. */
2726 /* For each field in the object, check:
2727 1) Is it FP? --> yes, nRc = 1;
2728 2) Is it addressable (bitpos != 0) and
2729 not packed (bitsize == 0)?
2733 for (i = 0; i < TYPE_NFIELDS (type); i++)
2735 enum type_code field_type_code;
2736 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2738 /* Is it a floating point type field? */
2739 if (field_type_code == TYPE_CODE_FLT)
2745 /* If bitpos != 0, then we have to care about it. */
2746 if (TYPE_FIELD_BITPOS (type, i) != 0)
2748 /* Bitfields are not addressable. If the field bitsize is
2749 zero, then the field is not packed. Hence it cannot be
2750 a bitfield or any other packed type. */
2751 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2763 /* Write into appropriate registers a function return value of type
2764 TYPE, given in virtual format. */
2767 arm_store_return_value (struct type *type, struct regcache *regs,
2768 const gdb_byte *valbuf)
2770 struct gdbarch *gdbarch = get_regcache_arch (regs);
2771 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2773 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2775 char buf[MAX_REGISTER_SIZE];
2777 switch (gdbarch_tdep (gdbarch)->fp_model)
2781 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2782 gdbarch_byte_order (gdbarch));
2783 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2786 case ARM_FLOAT_SOFT_FPA:
2787 case ARM_FLOAT_SOFT_VFP:
2788 /* ARM_FLOAT_VFP can arise if this is a variadic function so
2789 not using the VFP ABI code. */
2791 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2792 if (TYPE_LENGTH (type) > 4)
2793 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2794 valbuf + INT_REGISTER_SIZE);
2799 (__FILE__, __LINE__,
2800 _("arm_store_return_value: Floating point model not supported"));
2804 else if (TYPE_CODE (type) == TYPE_CODE_INT
2805 || TYPE_CODE (type) == TYPE_CODE_CHAR
2806 || TYPE_CODE (type) == TYPE_CODE_BOOL
2807 || TYPE_CODE (type) == TYPE_CODE_PTR
2808 || TYPE_CODE (type) == TYPE_CODE_REF
2809 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2811 if (TYPE_LENGTH (type) <= 4)
2813 /* Values of one word or less are zero/sign-extended and
2815 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2816 LONGEST val = unpack_long (type, valbuf);
2818 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
2819 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2823 /* Integral values greater than one word are stored in consecutive
2824 registers starting with r0. This will always be a multiple of
2825 the regiser size. */
2826 int len = TYPE_LENGTH (type);
2827 int regno = ARM_A1_REGNUM;
2831 regcache_cooked_write (regs, regno++, valbuf);
2832 len -= INT_REGISTER_SIZE;
2833 valbuf += INT_REGISTER_SIZE;
2839 /* For a structure or union the behaviour is as if the value had
2840 been stored to word-aligned memory and then loaded into
2841 registers with 32-bit load instruction(s). */
2842 int len = TYPE_LENGTH (type);
2843 int regno = ARM_A1_REGNUM;
2844 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2848 memcpy (tmpbuf, valbuf,
2849 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2850 regcache_cooked_write (regs, regno++, tmpbuf);
2851 len -= INT_REGISTER_SIZE;
2852 valbuf += INT_REGISTER_SIZE;
2858 /* Handle function return values. */
2860 static enum return_value_convention
2861 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2862 struct type *valtype, struct regcache *regcache,
2863 gdb_byte *readbuf, const gdb_byte *writebuf)
2865 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2866 enum arm_vfp_cprc_base_type vfp_base_type;
2869 if (arm_vfp_abi_for_function (gdbarch, func_type)
2870 && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count))
2872 int reg_char = arm_vfp_cprc_reg_char (vfp_base_type);
2873 int unit_length = arm_vfp_cprc_unit_length (vfp_base_type);
2875 for (i = 0; i < vfp_base_count; i++)
2879 sprintf (name_buf, "%c%d", reg_char, i);
2880 regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
2883 regcache_cooked_write (regcache, regnum,
2884 writebuf + i * unit_length);
2886 regcache_cooked_read (regcache, regnum,
2887 readbuf + i * unit_length);
2889 return RETURN_VALUE_REGISTER_CONVENTION;
2892 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2893 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2894 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2896 if (tdep->struct_return == pcc_struct_return
2897 || arm_return_in_memory (gdbarch, valtype))
2898 return RETURN_VALUE_STRUCT_CONVENTION;
2902 arm_store_return_value (valtype, regcache, writebuf);
2905 arm_extract_return_value (valtype, regcache, readbuf);
2907 return RETURN_VALUE_REGISTER_CONVENTION;
2912 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2914 struct gdbarch *gdbarch = get_frame_arch (frame);
2915 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2916 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2918 char buf[INT_REGISTER_SIZE];
2920 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2922 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2926 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
2930 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2931 return the target PC. Otherwise return 0. */
2934 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2938 CORE_ADDR start_addr;
2940 /* Find the starting address and name of the function containing the PC. */
2941 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2944 /* If PC is in a Thumb call or return stub, return the address of the
2945 target PC, which is in a register. The thunk functions are called
2946 _call_via_xx, where x is the register name. The possible names
2947 are r0-r9, sl, fp, ip, sp, and lr. */
2948 if (strncmp (name, "_call_via_", 10) == 0)
2950 /* Use the name suffix to determine which register contains the
2952 static char *table[15] =
2953 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2954 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2957 int offset = strlen (name) - 2;
2959 for (regno = 0; regno <= 14; regno++)
2960 if (strcmp (&name[offset], table[regno]) == 0)
2961 return get_frame_register_unsigned (frame, regno);
2964 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2965 non-interworking calls to foo. We could decode the stubs
2966 to find the target but it's easier to use the symbol table. */
2967 namelen = strlen (name);
2968 if (name[0] == '_' && name[1] == '_'
2969 && ((namelen > 2 + strlen ("_from_thumb")
2970 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2971 strlen ("_from_thumb")) == 0)
2972 || (namelen > 2 + strlen ("_from_arm")
2973 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2974 strlen ("_from_arm")) == 0)))
2977 int target_len = namelen - 2;
2978 struct minimal_symbol *minsym;
2979 struct objfile *objfile;
2980 struct obj_section *sec;
2982 if (name[namelen - 1] == 'b')
2983 target_len -= strlen ("_from_thumb");
2985 target_len -= strlen ("_from_arm");
2987 target_name = alloca (target_len + 1);
2988 memcpy (target_name, name + 2, target_len);
2989 target_name[target_len] = '\0';
2991 sec = find_pc_section (pc);
2992 objfile = (sec == NULL) ? NULL : sec->objfile;
2993 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2995 return SYMBOL_VALUE_ADDRESS (minsym);
3000 return 0; /* not a stub */
3004 set_arm_command (char *args, int from_tty)
3006 printf_unfiltered (_("\
3007 \"set arm\" must be followed by an apporpriate subcommand.\n"));
3008 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
3012 show_arm_command (char *args, int from_tty)
3014 cmd_show_list (showarmcmdlist, from_tty, "");
3018 arm_update_current_architecture (void)
3020 struct gdbarch_info info;
3022 /* If the current architecture is not ARM, we have nothing to do. */
3023 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
3026 /* Update the architecture. */
3027 gdbarch_info_init (&info);
3029 if (!gdbarch_update_p (info))
3030 internal_error (__FILE__, __LINE__, "could not update architecture");
3034 set_fp_model_sfunc (char *args, int from_tty,
3035 struct cmd_list_element *c)
3037 enum arm_float_model fp_model;
3039 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
3040 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
3042 arm_fp_model = fp_model;
3046 if (fp_model == ARM_FLOAT_LAST)
3047 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
3050 arm_update_current_architecture ();
3054 show_fp_model (struct ui_file *file, int from_tty,
3055 struct cmd_list_element *c, const char *value)
3057 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
3059 if (arm_fp_model == ARM_FLOAT_AUTO
3060 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
3061 fprintf_filtered (file, _("\
3062 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
3063 fp_model_strings[tdep->fp_model]);
3065 fprintf_filtered (file, _("\
3066 The current ARM floating point model is \"%s\".\n"),
3067 fp_model_strings[arm_fp_model]);
3071 arm_set_abi (char *args, int from_tty,
3072 struct cmd_list_element *c)
3074 enum arm_abi_kind arm_abi;
3076 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
3077 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
3079 arm_abi_global = arm_abi;
3083 if (arm_abi == ARM_ABI_LAST)
3084 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
3087 arm_update_current_architecture ();
3091 arm_show_abi (struct ui_file *file, int from_tty,
3092 struct cmd_list_element *c, const char *value)
3094 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
3096 if (arm_abi_global == ARM_ABI_AUTO
3097 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
3098 fprintf_filtered (file, _("\
3099 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
3100 arm_abi_strings[tdep->arm_abi]);
3102 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
3107 arm_show_fallback_mode (struct ui_file *file, int from_tty,
3108 struct cmd_list_element *c, const char *value)
3110 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
3112 fprintf_filtered (file, _("\
3113 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
3114 arm_fallback_mode_string);
3118 arm_show_force_mode (struct ui_file *file, int from_tty,
3119 struct cmd_list_element *c, const char *value)
3121 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
3123 fprintf_filtered (file, _("\
3124 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
3125 arm_force_mode_string);
3128 /* If the user changes the register disassembly style used for info
3129 register and other commands, we have to also switch the style used
3130 in opcodes for disassembly output. This function is run in the "set
3131 arm disassembly" command, and does that. */
3134 set_disassembly_style_sfunc (char *args, int from_tty,
3135 struct cmd_list_element *c)
3137 set_disassembly_style ();
3140 /* Return the ARM register name corresponding to register I. */
3142 arm_register_name (struct gdbarch *gdbarch, int i)
3144 if (i >= ARRAY_SIZE (arm_register_names))
3145 /* These registers are only supported on targets which supply
3146 an XML description. */
3149 return arm_register_names[i];
3153 set_disassembly_style (void)
3157 /* Find the style that the user wants. */
3158 for (current = 0; current < num_disassembly_options; current++)
3159 if (disassembly_style == valid_disassembly_styles[current])
3161 gdb_assert (current < num_disassembly_options);
3163 /* Synchronize the disassembler. */
3164 set_arm_regname_option (current);
3167 /* Test whether the coff symbol specific value corresponds to a Thumb
3171 coff_sym_is_thumb (int val)
3173 return (val == C_THUMBEXT ||
3174 val == C_THUMBSTAT ||
3175 val == C_THUMBEXTFUNC ||
3176 val == C_THUMBSTATFUNC ||
3177 val == C_THUMBLABEL);
3180 /* arm_coff_make_msymbol_special()
3181 arm_elf_make_msymbol_special()
3183 These functions test whether the COFF or ELF symbol corresponds to
3184 an address in thumb code, and set a "special" bit in a minimal
3185 symbol to indicate that it does. */
3188 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
3190 /* Thumb symbols are of type STT_LOPROC, (synonymous with
3192 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
3194 MSYMBOL_SET_SPECIAL (msym);
3198 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
3200 if (coff_sym_is_thumb (val))
3201 MSYMBOL_SET_SPECIAL (msym);
3205 arm_objfile_data_cleanup (struct objfile *objfile, void *arg)
3207 struct arm_per_objfile *data = arg;
3210 for (i = 0; i < objfile->obfd->section_count; i++)
3211 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
3215 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
3218 const char *name = bfd_asymbol_name (sym);
3219 struct arm_per_objfile *data;
3220 VEC(arm_mapping_symbol_s) **map_p;
3221 struct arm_mapping_symbol new_map_sym;
3223 gdb_assert (name[0] == '$');
3224 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
3227 data = objfile_data (objfile, arm_objfile_data_key);
3230 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
3231 struct arm_per_objfile);
3232 set_objfile_data (objfile, arm_objfile_data_key, data);
3233 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
3234 objfile->obfd->section_count,
3235 VEC(arm_mapping_symbol_s) *);
3237 map_p = &data->section_maps[bfd_get_section (sym)->index];
3239 new_map_sym.value = sym->value;
3240 new_map_sym.type = name[1];
3242 /* Assume that most mapping symbols appear in order of increasing
3243 value. If they were randomly distributed, it would be faster to
3244 always push here and then sort at first use. */
3245 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
3247 struct arm_mapping_symbol *prev_map_sym;
3249 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
3250 if (prev_map_sym->value >= sym->value)
3253 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
3254 arm_compare_mapping_symbols);
3255 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
3260 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
3264 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
3266 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
3268 /* If necessary, set the T bit. */
3272 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
3273 if (arm_pc_is_thumb (pc))
3274 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
3276 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
3277 val & ~(ULONGEST) CPSR_T);
3281 static struct value *
3282 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
3284 const int *reg_p = baton;
3285 return value_of_register (*reg_p, frame);
3288 static enum gdb_osabi
3289 arm_elf_osabi_sniffer (bfd *abfd)
3291 unsigned int elfosabi;
3292 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
3294 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
3296 if (elfosabi == ELFOSABI_ARM)
3297 /* GNU tools use this value. Check note sections in this case,
3299 bfd_map_over_sections (abfd,
3300 generic_elf_osabi_sniff_abi_tag_sections,
3303 /* Anything else will be handled by the generic ELF sniffer. */
3308 /* Initialize the current architecture based on INFO. If possible,
3309 re-use an architecture from ARCHES, which is a list of
3310 architectures already created during this debugging session.
3312 Called e.g. at program startup, when reading a core file, and when
3313 reading a binary file. */
3315 static struct gdbarch *
3316 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3318 struct gdbarch_tdep *tdep;
3319 struct gdbarch *gdbarch;
3320 struct gdbarch_list *best_arch;
3321 enum arm_abi_kind arm_abi = arm_abi_global;
3322 enum arm_float_model fp_model = arm_fp_model;
3323 struct tdesc_arch_data *tdesc_data = NULL;
3325 int have_fpa_registers = 1;
3327 /* Check any target description for validity. */
3328 if (tdesc_has_registers (info.target_desc))
3330 /* For most registers we require GDB's default names; but also allow
3331 the numeric names for sp / lr / pc, as a convenience. */
3332 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
3333 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
3334 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
3336 const struct tdesc_feature *feature;
3339 feature = tdesc_find_feature (info.target_desc,
3340 "org.gnu.gdb.arm.core");
3341 if (feature == NULL)
3344 tdesc_data = tdesc_data_alloc ();
3347 for (i = 0; i < ARM_SP_REGNUM; i++)
3348 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3349 arm_register_names[i]);
3350 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3353 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3356 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3359 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3360 ARM_PS_REGNUM, "cpsr");
3364 tdesc_data_cleanup (tdesc_data);
3368 feature = tdesc_find_feature (info.target_desc,
3369 "org.gnu.gdb.arm.fpa");
3370 if (feature != NULL)
3373 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
3374 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3375 arm_register_names[i]);
3378 tdesc_data_cleanup (tdesc_data);
3383 have_fpa_registers = 0;
3385 feature = tdesc_find_feature (info.target_desc,
3386 "org.gnu.gdb.xscale.iwmmxt");
3387 if (feature != NULL)
3389 static const char *const iwmmxt_names[] = {
3390 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3391 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3392 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3393 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3397 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
3399 &= tdesc_numbered_register (feature, tdesc_data, i,
3400 iwmmxt_names[i - ARM_WR0_REGNUM]);
3402 /* Check for the control registers, but do not fail if they
3404 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
3405 tdesc_numbered_register (feature, tdesc_data, i,
3406 iwmmxt_names[i - ARM_WR0_REGNUM]);
3408 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
3410 &= tdesc_numbered_register (feature, tdesc_data, i,
3411 iwmmxt_names[i - ARM_WR0_REGNUM]);
3415 tdesc_data_cleanup (tdesc_data);
3421 /* If we have an object to base this architecture on, try to determine
3424 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
3426 int ei_osabi, e_flags;
3428 switch (bfd_get_flavour (info.abfd))
3430 case bfd_target_aout_flavour:
3431 /* Assume it's an old APCS-style ABI. */
3432 arm_abi = ARM_ABI_APCS;
3435 case bfd_target_coff_flavour:
3436 /* Assume it's an old APCS-style ABI. */
3438 arm_abi = ARM_ABI_APCS;
3441 case bfd_target_elf_flavour:
3442 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
3443 e_flags = elf_elfheader (info.abfd)->e_flags;
3445 if (ei_osabi == ELFOSABI_ARM)
3447 /* GNU tools used to use this value, but do not for EABI
3448 objects. There's nowhere to tag an EABI version
3449 anyway, so assume APCS. */
3450 arm_abi = ARM_ABI_APCS;
3452 else if (ei_osabi == ELFOSABI_NONE)
3454 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
3458 case EF_ARM_EABI_UNKNOWN:
3459 /* Assume GNU tools. */
3460 arm_abi = ARM_ABI_APCS;
3463 case EF_ARM_EABI_VER4:
3464 case EF_ARM_EABI_VER5:
3465 arm_abi = ARM_ABI_AAPCS;
3466 /* EABI binaries default to VFP float ordering.
3467 They may also contain build attributes that can
3468 be used to identify if the VFP argument-passing
3470 if (fp_model == ARM_FLOAT_AUTO)
3473 switch (bfd_elf_get_obj_attr_int (info.abfd,
3478 /* "The user intended FP parameter/result
3479 passing to conform to AAPCS, base
3481 fp_model = ARM_FLOAT_SOFT_VFP;
3484 /* "The user intended FP parameter/result
3485 passing to conform to AAPCS, VFP
3487 fp_model = ARM_FLOAT_VFP;
3490 /* "The user intended FP parameter/result
3491 passing to conform to tool chain-specific
3492 conventions" - we don't know any such
3493 conventions, so leave it as "auto". */
3496 /* Attribute value not mentioned in the
3497 October 2008 ABI, so leave it as
3502 fp_model = ARM_FLOAT_SOFT_VFP;
3508 /* Leave it as "auto". */
3509 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
3514 if (fp_model == ARM_FLOAT_AUTO)
3516 int e_flags = elf_elfheader (info.abfd)->e_flags;
3518 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
3521 /* Leave it as "auto". Strictly speaking this case
3522 means FPA, but almost nobody uses that now, and
3523 many toolchains fail to set the appropriate bits
3524 for the floating-point model they use. */
3526 case EF_ARM_SOFT_FLOAT:
3527 fp_model = ARM_FLOAT_SOFT_FPA;
3529 case EF_ARM_VFP_FLOAT:
3530 fp_model = ARM_FLOAT_VFP;
3532 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
3533 fp_model = ARM_FLOAT_SOFT_VFP;
3538 if (e_flags & EF_ARM_BE8)
3539 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3544 /* Leave it as "auto". */
3549 /* If there is already a candidate, use it. */
3550 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3552 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3554 if (arm_abi != ARM_ABI_AUTO
3555 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
3558 if (fp_model != ARM_FLOAT_AUTO
3559 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
3562 /* Found a match. */
3566 if (best_arch != NULL)
3568 if (tdesc_data != NULL)
3569 tdesc_data_cleanup (tdesc_data);
3570 return best_arch->gdbarch;
3573 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
3574 gdbarch = gdbarch_alloc (&info, tdep);
3576 /* Record additional information about the architecture we are defining.
3577 These are gdbarch discriminators, like the OSABI. */
3578 tdep->arm_abi = arm_abi;
3579 tdep->fp_model = fp_model;
3580 tdep->have_fpa_registers = have_fpa_registers;
3583 switch (info.byte_order_for_code)
3585 case BFD_ENDIAN_BIG:
3586 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3587 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3588 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3589 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3593 case BFD_ENDIAN_LITTLE:
3594 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3595 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3596 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3597 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3602 internal_error (__FILE__, __LINE__,
3603 _("arm_gdbarch_init: bad byte order for float format"));
3606 /* On ARM targets char defaults to unsigned. */
3607 set_gdbarch_char_signed (gdbarch, 0);
3609 /* This should be low enough for everything. */
3610 tdep->lowest_pc = 0x20;
3611 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3613 /* The default, for both APCS and AAPCS, is to return small
3614 structures in registers. */
3615 tdep->struct_return = reg_struct_return;
3617 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
3618 set_gdbarch_frame_align (gdbarch, arm_frame_align);
3620 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3622 /* Frame handling. */
3623 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
3624 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3625 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3627 frame_base_set_default (gdbarch, &arm_normal_base);
3629 /* Address manipulation. */
3630 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3631 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3633 /* Advance PC across function entry code. */
3634 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3636 /* Skip trampolines. */
3637 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3639 /* The stack grows downward. */
3640 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3642 /* Breakpoint manipulation. */
3643 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3645 /* Information about registers, etc. */
3646 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3647 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3648 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3649 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3650 set_gdbarch_register_type (gdbarch, arm_register_type);
3652 /* This "info float" is FPA-specific. Use the generic version if we
3654 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3655 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3657 /* Internal <-> external register number maps. */
3658 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3659 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3661 set_gdbarch_register_name (gdbarch, arm_register_name);
3663 /* Returning results. */
3664 set_gdbarch_return_value (gdbarch, arm_return_value);
3667 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3669 /* Minsymbol frobbing. */
3670 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3671 set_gdbarch_coff_make_msymbol_special (gdbarch,
3672 arm_coff_make_msymbol_special);
3673 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
3675 /* Virtual tables. */
3676 set_gdbarch_vbit_in_delta (gdbarch, 1);
3678 /* Hook in the ABI-specific overrides, if they have been registered. */
3679 gdbarch_init_osabi (info, gdbarch);
3681 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3683 /* Add some default predicates. */
3684 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3685 dwarf2_append_unwinders (gdbarch);
3686 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
3688 /* Now we have tuned the configuration, set a few final things,
3689 based on what the OS ABI has told us. */
3691 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3692 binaries are always marked. */
3693 if (tdep->arm_abi == ARM_ABI_AUTO)
3694 tdep->arm_abi = ARM_ABI_APCS;
3696 /* We used to default to FPA for generic ARM, but almost nobody
3697 uses that now, and we now provide a way for the user to force
3698 the model. So default to the most useful variant. */
3699 if (tdep->fp_model == ARM_FLOAT_AUTO)
3700 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3702 if (tdep->jb_pc >= 0)
3703 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3705 /* Floating point sizes and format. */
3706 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3707 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3709 set_gdbarch_double_format
3710 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3711 set_gdbarch_long_double_format
3712 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3716 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3717 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3721 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3723 /* Add standard register aliases. We add aliases even for those
3724 nanes which are used by the current architecture - it's simpler,
3725 and does no harm, since nothing ever lists user registers. */
3726 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3727 user_reg_add (gdbarch, arm_register_aliases[i].name,
3728 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3734 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3736 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3741 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3742 (unsigned long) tdep->lowest_pc);
3745 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3748 _initialize_arm_tdep (void)
3750 struct ui_file *stb;
3752 struct cmd_list_element *new_set, *new_show;
3753 const char *setname;
3754 const char *setdesc;
3755 const char *const *regnames;
3757 static char *helptext;
3758 char regdesc[1024], *rdptr = regdesc;
3759 size_t rest = sizeof (regdesc);
3761 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3763 arm_objfile_data_key
3764 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup);
3766 /* Register an ELF OS ABI sniffer for ARM binaries. */
3767 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3768 bfd_target_elf_flavour,
3769 arm_elf_osabi_sniffer);
3771 /* Get the number of possible sets of register names defined in opcodes. */
3772 num_disassembly_options = get_arm_regname_num_options ();
3774 /* Add root prefix command for all "set arm"/"show arm" commands. */
3775 add_prefix_cmd ("arm", no_class, set_arm_command,
3776 _("Various ARM-specific commands."),
3777 &setarmcmdlist, "set arm ", 0, &setlist);
3779 add_prefix_cmd ("arm", no_class, show_arm_command,
3780 _("Various ARM-specific commands."),
3781 &showarmcmdlist, "show arm ", 0, &showlist);
3783 /* Sync the opcode insn printer with our register viewer. */
3784 parse_arm_disassembler_option ("reg-names-std");
3786 /* Initialize the array that will be passed to
3787 add_setshow_enum_cmd(). */
3788 valid_disassembly_styles
3789 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3790 for (i = 0; i < num_disassembly_options; i++)
3792 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3793 valid_disassembly_styles[i] = setname;
3794 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3797 /* When we find the default names, tell the disassembler to use
3799 if (!strcmp (setname, "std"))
3801 disassembly_style = setname;
3802 set_arm_regname_option (i);
3805 /* Mark the end of valid options. */
3806 valid_disassembly_styles[num_disassembly_options] = NULL;
3808 /* Create the help text. */
3809 stb = mem_fileopen ();
3810 fprintf_unfiltered (stb, "%s%s%s",
3811 _("The valid values are:\n"),
3813 _("The default is \"std\"."));
3814 helptext = ui_file_xstrdup (stb, &length);
3815 ui_file_delete (stb);
3817 add_setshow_enum_cmd("disassembler", no_class,
3818 valid_disassembly_styles, &disassembly_style,
3819 _("Set the disassembly style."),
3820 _("Show the disassembly style."),
3822 set_disassembly_style_sfunc,
3823 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3824 &setarmcmdlist, &showarmcmdlist);
3826 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3827 _("Set usage of ARM 32-bit mode."),
3828 _("Show usage of ARM 32-bit mode."),
3829 _("When off, a 26-bit PC will be used."),
3831 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3832 &setarmcmdlist, &showarmcmdlist);
3834 /* Add a command to allow the user to force the FPU model. */
3835 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3836 _("Set the floating point type."),
3837 _("Show the floating point type."),
3838 _("auto - Determine the FP typefrom the OS-ABI.\n\
3839 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3840 fpa - FPA co-processor (GCC compiled).\n\
3841 softvfp - Software FP with pure-endian doubles.\n\
3842 vfp - VFP co-processor."),
3843 set_fp_model_sfunc, show_fp_model,
3844 &setarmcmdlist, &showarmcmdlist);
3846 /* Add a command to allow the user to force the ABI. */
3847 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3850 NULL, arm_set_abi, arm_show_abi,
3851 &setarmcmdlist, &showarmcmdlist);
3853 /* Add two commands to allow the user to force the assumed
3855 add_setshow_enum_cmd ("fallback-mode", class_support,
3856 arm_mode_strings, &arm_fallback_mode_string,
3857 _("Set the mode assumed when symbols are unavailable."),
3858 _("Show the mode assumed when symbols are unavailable."),
3859 NULL, NULL, arm_show_fallback_mode,
3860 &setarmcmdlist, &showarmcmdlist);
3861 add_setshow_enum_cmd ("force-mode", class_support,
3862 arm_mode_strings, &arm_force_mode_string,
3863 _("Set the mode assumed even when symbols are available."),
3864 _("Show the mode assumed even when symbols are available."),
3865 NULL, NULL, arm_show_force_mode,
3866 &setarmcmdlist, &showarmcmdlist);
3868 /* Debugging flag. */
3869 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3870 _("Set ARM debugging."),
3871 _("Show ARM debugging."),
3872 _("When on, arm-specific debugging is enabled."),
3874 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3875 &setdebuglist, &showdebuglist);