1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper () */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
33 #include "arch-utils.h"
35 #include "frame-unwind.h"
36 #include "frame-base.h"
37 #include "trad-frame.h"
39 #include "dwarf2-frame.h"
41 #include "prologue-value.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element *setarmcmdlist = NULL;
72 static struct cmd_list_element *showarmcmdlist = NULL;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
88 static const char *current_fp_model = "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
101 static const char *arm_abi_string = "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options;
106 /* The standard register names, and all the valid aliases for them. */
111 } arm_register_aliases[] = {
112 /* Basic register numbers. */
129 /* Synonyms (argument and variable registers). */
142 /* Other platform-specific names for r9. */
150 /* Names used by GCC (not listed in the ARM EABI). */
153 /* A special name from the older ATPCS. */
157 static const char *const arm_register_names[] =
158 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
159 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
160 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
161 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
162 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
163 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
164 "fps", "cpsr" }; /* 24 25 */
166 /* Valid register name styles. */
167 static const char **valid_disassembly_styles;
169 /* Disassembly style to use. Default to "std" register names. */
170 static const char *disassembly_style;
172 /* This is used to keep the bfd arch_info in sync with the disassembly
174 static void set_disassembly_style_sfunc(char *, int,
175 struct cmd_list_element *);
176 static void set_disassembly_style (void);
178 static void convert_from_extended (const struct floatformat *, const void *,
180 static void convert_to_extended (const struct floatformat *, void *,
183 struct arm_prologue_cache
185 /* The stack pointer at the time this frame was created; i.e. the
186 caller's stack pointer when this function was called. It is used
187 to identify this frame. */
190 /* The frame base for this frame is just prev_sp - frame size.
191 FRAMESIZE is the distance from the frame pointer to the
192 initial stack pointer. */
196 /* The register used to hold the frame pointer for this frame. */
199 /* Saved register offsets. */
200 struct trad_frame_saved_reg *saved_regs;
203 /* Addresses for calling Thumb functions have the bit 0 set.
204 Here are some macros to test, set, or clear bit 0 of addresses. */
205 #define IS_THUMB_ADDR(addr) ((addr) & 1)
206 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
207 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
209 /* Set to true if the 32-bit mode is in use. */
213 /* Determine if the program counter specified in MEMADDR is in a Thumb
217 arm_pc_is_thumb (CORE_ADDR memaddr)
219 struct minimal_symbol *sym;
221 /* If bit 0 of the address is set, assume this is a Thumb address. */
222 if (IS_THUMB_ADDR (memaddr))
225 /* Thumb functions have a "special" bit set in minimal symbols. */
226 sym = lookup_minimal_symbol_by_pc (memaddr);
229 return (MSYMBOL_IS_SPECIAL (sym));
237 /* Remove useless bits from addresses in a running program. */
239 arm_addr_bits_remove (CORE_ADDR val)
242 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
244 return (val & 0x03fffffc);
247 /* When reading symbols, we need to zap the low bit of the address,
248 which may be set to 1 for Thumb functions. */
250 arm_smash_text_address (CORE_ADDR val)
255 /* Analyze a Thumb prologue, looking for a recognizable stack frame
256 and frame pointer. Scan until we encounter a store that could
257 clobber the stack frame unexpectedly, or an unknown instruction. */
260 thumb_analyze_prologue (struct gdbarch *gdbarch,
261 CORE_ADDR start, CORE_ADDR limit,
262 struct arm_prologue_cache *cache)
266 struct pv_area *stack;
267 struct cleanup *back_to;
270 for (i = 0; i < 16; i++)
271 regs[i] = pv_register (i, 0);
272 stack = make_pv_area (ARM_SP_REGNUM);
273 back_to = make_cleanup_free_pv_area (stack);
275 /* The call instruction saved PC in LR, and the current PC is not
276 interesting. Due to this file's conventions, we want the value
277 of LR at this function's entry, not at the call site, so we do
278 not record the save of the PC - when the ARM prologue analyzer
279 has also been converted to the pv mechanism, we could record the
280 save here and remove the hack in prev_register. */
281 regs[ARM_PC_REGNUM] = pv_unknown ();
283 while (start < limit)
287 insn = read_memory_unsigned_integer (start, 2);
289 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
294 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
297 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
298 whether to save LR (R14). */
299 mask = (insn & 0xff) | ((insn & 0x100) << 6);
301 /* Calculate offsets of saved R0-R7 and LR. */
302 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
303 if (mask & (1 << regno))
305 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
307 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
310 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
313 offset = (insn & 0x7f) << 2; /* get scaled offset */
314 if (insn & 0x80) /* Check for SUB. */
315 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
318 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
321 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
322 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
324 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
326 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
327 int src_reg = (insn & 0x78) >> 3;
328 regs[dst_reg] = regs[src_reg];
330 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
332 /* Handle stores to the stack. Normally pushes are used,
333 but with GCC -mtpcs-frame, there may be other stores
334 in the prologue to create the frame. */
335 int regno = (insn >> 8) & 0x7;
338 offset = (insn & 0xff) << 2;
339 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
341 if (pv_area_store_would_trash (stack, addr))
344 pv_area_store (stack, addr, 4, regs[regno]);
348 /* We don't know what this instruction is. We're finished
349 scanning. NOTE: Recognizing more safe-to-ignore
350 instructions here will improve support for optimized
360 do_cleanups (back_to);
364 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
366 /* Frame pointer is fp. Frame size is constant. */
367 cache->framereg = ARM_FP_REGNUM;
368 cache->framesize = -regs[ARM_FP_REGNUM].k;
370 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
372 /* Frame pointer is r7. Frame size is constant. */
373 cache->framereg = THUMB_FP_REGNUM;
374 cache->framesize = -regs[THUMB_FP_REGNUM].k;
376 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
378 /* Try the stack pointer... this is a bit desperate. */
379 cache->framereg = ARM_SP_REGNUM;
380 cache->framesize = -regs[ARM_SP_REGNUM].k;
384 /* We're just out of luck. We don't know where the frame is. */
385 cache->framereg = -1;
386 cache->framesize = 0;
389 for (i = 0; i < 16; i++)
390 if (pv_area_find_reg (stack, gdbarch, i, &offset))
391 cache->saved_regs[i].addr = offset;
393 do_cleanups (back_to);
397 /* Advance the PC across any function entry prologue instructions to
398 reach some "real" code.
400 The APCS (ARM Procedure Call Standard) defines the following
404 [stmfd sp!, {a1,a2,a3,a4}]
405 stmfd sp!, {...,fp,ip,lr,pc}
406 [stfe f7, [sp, #-12]!]
407 [stfe f6, [sp, #-12]!]
408 [stfe f5, [sp, #-12]!]
409 [stfe f4, [sp, #-12]!]
410 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
413 arm_skip_prologue (CORE_ADDR pc)
417 CORE_ADDR func_addr, func_end = 0;
419 struct symtab_and_line sal;
421 /* If we're in a dummy frame, don't even try to skip the prologue. */
422 if (deprecated_pc_in_call_dummy (pc))
425 /* See what the symbol table says. */
427 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
431 /* Found a function. */
432 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
433 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
435 /* Don't use this trick for assembly source files. */
436 sal = find_pc_line (func_addr, 0);
437 if ((sal.line != 0) && (sal.end < func_end))
442 /* Can't find the prologue end in the symbol table, try it the hard way
443 by disassembling the instructions. */
445 /* Like arm_scan_prologue, stop no later than pc + 64. */
446 if (func_end == 0 || func_end > pc + 64)
449 /* Check if this is Thumb code. */
450 if (arm_pc_is_thumb (pc))
451 return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL);
453 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
455 inst = read_memory_unsigned_integer (skip_pc, 4);
457 /* "mov ip, sp" is no longer a required part of the prologue. */
458 if (inst == 0xe1a0c00d) /* mov ip, sp */
461 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
464 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
467 /* Some prologues begin with "str lr, [sp, #-4]!". */
468 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
471 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
474 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
477 /* Any insns after this point may float into the code, if it makes
478 for better instruction scheduling, so we skip them only if we
479 find them, but still consider the function to be frame-ful. */
481 /* We may have either one sfmfd instruction here, or several stfe
482 insns, depending on the version of floating point code we
484 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
487 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
490 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
493 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
496 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
497 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
498 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
501 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
502 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
503 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
506 /* Un-recognized instruction; stop scanning. */
510 return skip_pc; /* End of prologue */
514 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
515 This function decodes a Thumb function prologue to determine:
516 1) the size of the stack frame
517 2) which registers are saved on it
518 3) the offsets of saved regs
519 4) the offset from the stack pointer to the frame pointer
521 A typical Thumb function prologue would create this stack frame
522 (offsets relative to FP)
523 old SP -> 24 stack parameters
526 R7 -> 0 local variables (16 bytes)
527 SP -> -12 additional stack space (12 bytes)
528 The frame size would thus be 36 bytes, and the frame offset would be
529 12 bytes. The frame register is R7.
531 The comments for thumb_skip_prolog() describe the algorithm we use
532 to detect the end of the prolog. */
536 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
538 CORE_ADDR prologue_start;
539 CORE_ADDR prologue_end;
540 CORE_ADDR current_pc;
541 /* Which register has been copied to register n? */
544 bit 0 - push { rlist }
545 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
546 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
551 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
553 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
555 if (sal.line == 0) /* no line info, use current PC */
556 prologue_end = prev_pc;
557 else if (sal.end < prologue_end) /* next line begins after fn end */
558 prologue_end = sal.end; /* (probably means no prologue) */
561 /* We're in the boondocks: we have no idea where the start of the
565 prologue_end = min (prologue_end, prev_pc);
567 thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end,
571 /* This function decodes an ARM function prologue to determine:
572 1) the size of the stack frame
573 2) which registers are saved on it
574 3) the offsets of saved regs
575 4) the offset from the stack pointer to the frame pointer
576 This information is stored in the "extra" fields of the frame_info.
578 There are two basic forms for the ARM prologue. The fixed argument
579 function call will look like:
582 stmfd sp!, {fp, ip, lr, pc}
586 Which would create this stack frame (offsets relative to FP):
587 IP -> 4 (caller's stack)
588 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
589 -4 LR (return address in caller)
590 -8 IP (copy of caller's SP)
592 SP -> -28 Local variables
594 The frame size would thus be 32 bytes, and the frame offset would be
595 28 bytes. The stmfd call can also save any of the vN registers it
596 plans to use, which increases the frame size accordingly.
598 Note: The stored PC is 8 off of the STMFD instruction that stored it
599 because the ARM Store instructions always store PC + 8 when you read
602 A variable argument function call will look like:
605 stmfd sp!, {a1, a2, a3, a4}
606 stmfd sp!, {fp, ip, lr, pc}
609 Which would create this stack frame (offsets relative to FP):
610 IP -> 20 (caller's stack)
615 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
616 -4 LR (return address in caller)
617 -8 IP (copy of caller's SP)
619 SP -> -28 Local variables
621 The frame size would thus be 48 bytes, and the frame offset would be
624 There is another potential complication, which is that the optimizer
625 will try to separate the store of fp in the "stmfd" instruction from
626 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
627 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
629 Also, note, the original version of the ARM toolchain claimed that there
632 instruction at the end of the prologue. I have never seen GCC produce
633 this, and the ARM docs don't mention it. We still test for it below in
639 arm_scan_prologue (struct frame_info *next_frame,
640 struct arm_prologue_cache *cache)
642 struct gdbarch *gdbarch = get_frame_arch (next_frame);
644 CORE_ADDR prologue_start, prologue_end, current_pc;
645 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
646 pv_t regs[ARM_FPS_REGNUM];
647 struct pv_area *stack;
648 struct cleanup *back_to;
651 /* Assume there is no frame until proven otherwise. */
652 cache->framereg = ARM_SP_REGNUM;
653 cache->framesize = 0;
655 /* Check for Thumb prologue. */
656 if (arm_pc_is_thumb (prev_pc))
658 thumb_scan_prologue (prev_pc, cache);
662 /* Find the function prologue. If we can't find the function in
663 the symbol table, peek in the stack frame to find the PC. */
664 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
666 /* One way to find the end of the prologue (which works well
667 for unoptimized code) is to do the following:
669 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
672 prologue_end = prev_pc;
673 else if (sal.end < prologue_end)
674 prologue_end = sal.end;
676 This mechanism is very accurate so long as the optimizer
677 doesn't move any instructions from the function body into the
678 prologue. If this happens, sal.end will be the last
679 instruction in the first hunk of prologue code just before
680 the first instruction that the scheduler has moved from
681 the body to the prologue.
683 In order to make sure that we scan all of the prologue
684 instructions, we use a slightly less accurate mechanism which
685 may scan more than necessary. To help compensate for this
686 lack of accuracy, the prologue scanning loop below contains
687 several clauses which'll cause the loop to terminate early if
688 an implausible prologue instruction is encountered.
694 is a suitable endpoint since it accounts for the largest
695 possible prologue plus up to five instructions inserted by
698 if (prologue_end > prologue_start + 64)
700 prologue_end = prologue_start + 64; /* See above. */
705 /* We have no symbol information. Our only option is to assume this
706 function has a standard stack frame and the normal frame register.
707 Then, we can find the value of our frame pointer on entrance to
708 the callee (or at the present moment if this is the innermost frame).
709 The value stored there should be the address of the stmfd + 8. */
711 LONGEST return_value;
713 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
714 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
718 prologue_start = gdbarch_addr_bits_remove
719 (gdbarch, return_value) - 8;
720 prologue_end = prologue_start + 64; /* See above. */
724 if (prev_pc < prologue_end)
725 prologue_end = prev_pc;
727 /* Now search the prologue looking for instructions that set up the
728 frame pointer, adjust the stack pointer, and save registers.
730 Be careful, however, and if it doesn't look like a prologue,
731 don't try to scan it. If, for instance, a frameless function
732 begins with stmfd sp!, then we will tell ourselves there is
733 a frame, which will confuse stack traceback, as well as "finish"
734 and other operations that rely on a knowledge of the stack
737 In the APCS, the prologue should start with "mov ip, sp" so
738 if we don't see this as the first insn, we will stop.
740 [Note: This doesn't seem to be true any longer, so it's now an
741 optional part of the prologue. - Kevin Buettner, 2001-11-20]
743 [Note further: The "mov ip,sp" only seems to be missing in
744 frameless functions at optimization level "-O2" or above,
745 in which case it is often (but not always) replaced by
746 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
748 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
749 regs[regno] = pv_register (regno, 0);
750 stack = make_pv_area (ARM_SP_REGNUM);
751 back_to = make_cleanup_free_pv_area (stack);
753 regs[ARM_PC_REGNUM] = pv_unknown ();
755 for (current_pc = prologue_start;
756 current_pc < prologue_end;
759 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
761 if (insn == 0xe1a0c00d) /* mov ip, sp */
763 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
766 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
768 unsigned imm = insn & 0xff; /* immediate value */
769 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
770 imm = (imm >> rot) | (imm << (32 - rot));
771 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
774 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
776 unsigned imm = insn & 0xff; /* immediate value */
777 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
778 imm = (imm >> rot) | (imm << (32 - rot));
779 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
782 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
784 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
786 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
787 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
790 else if ((insn & 0xffff0000) == 0xe92d0000)
791 /* stmfd sp!, {..., fp, ip, lr, pc}
793 stmfd sp!, {a1, a2, a3, a4} */
795 int mask = insn & 0xffff;
797 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
800 /* Calculate offsets of saved registers. */
801 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
802 if (mask & (1 << regno))
804 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
805 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
808 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
809 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
810 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
812 /* No need to add this to saved_regs -- it's just an arg reg. */
815 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
816 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
817 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
819 /* No need to add this to saved_regs -- it's just an arg reg. */
822 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
824 unsigned imm = insn & 0xff; /* immediate value */
825 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
826 imm = (imm >> rot) | (imm << (32 - rot));
827 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
829 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
831 unsigned imm = insn & 0xff; /* immediate value */
832 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
833 imm = (imm >> rot) | (imm << (32 - rot));
834 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
836 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
837 && gdbarch_tdep (gdbarch)->have_fpa_registers)
839 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
842 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
843 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
844 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
846 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
847 && gdbarch_tdep (gdbarch)->have_fpa_registers)
850 unsigned int fp_start_reg, fp_bound_reg;
852 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
855 if ((insn & 0x800) == 0x800) /* N0 is set */
857 if ((insn & 0x40000) == 0x40000) /* N1 is set */
864 if ((insn & 0x40000) == 0x40000) /* N1 is set */
870 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
871 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
872 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
874 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
875 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
876 regs[fp_start_reg++]);
879 else if ((insn & 0xf0000000) != 0xe0000000)
880 break; /* Condition not true, exit early */
881 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
882 break; /* Don't scan past a block load */
884 /* The optimizer might shove anything into the prologue,
885 so we just skip what we don't recognize. */
889 /* The frame size is just the distance from the frame register
890 to the original stack pointer. */
891 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
893 /* Frame pointer is fp. */
894 cache->framereg = ARM_FP_REGNUM;
895 cache->framesize = -regs[ARM_FP_REGNUM].k;
897 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
899 /* Try the stack pointer... this is a bit desperate. */
900 cache->framereg = ARM_SP_REGNUM;
901 cache->framesize = -regs[ARM_SP_REGNUM].k;
905 /* We're just out of luck. We don't know where the frame is. */
906 cache->framereg = -1;
907 cache->framesize = 0;
910 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
911 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
912 cache->saved_regs[regno].addr = offset;
914 do_cleanups (back_to);
917 static struct arm_prologue_cache *
918 arm_make_prologue_cache (struct frame_info *next_frame)
921 struct arm_prologue_cache *cache;
922 CORE_ADDR unwound_fp;
924 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
925 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
927 arm_scan_prologue (next_frame, cache);
929 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
933 cache->prev_sp = unwound_fp + cache->framesize;
935 /* Calculate actual addresses of saved registers using offsets
936 determined by arm_scan_prologue. */
937 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (next_frame)); reg++)
938 if (trad_frame_addr_p (cache->saved_regs, reg))
939 cache->saved_regs[reg].addr += cache->prev_sp;
944 /* Our frame ID for a normal frame is the current function's starting PC
945 and the caller's SP when we were called. */
948 arm_prologue_this_id (struct frame_info *next_frame,
950 struct frame_id *this_id)
952 struct arm_prologue_cache *cache;
956 if (*this_cache == NULL)
957 *this_cache = arm_make_prologue_cache (next_frame);
960 func = frame_func_unwind (next_frame, NORMAL_FRAME);
962 /* This is meant to halt the backtrace at "_start". Make sure we
963 don't halt it at a generic dummy frame. */
964 if (func <= LOWEST_PC)
967 /* If we've hit a wall, stop. */
968 if (cache->prev_sp == 0)
971 id = frame_id_build (cache->prev_sp, func);
976 arm_prologue_prev_register (struct frame_info *next_frame,
980 enum lval_type *lvalp,
985 struct arm_prologue_cache *cache;
987 if (*this_cache == NULL)
988 *this_cache = arm_make_prologue_cache (next_frame);
991 /* If we are asked to unwind the PC, then we need to return the LR
992 instead. The saved value of PC points into this frame's
993 prologue, not the next frame's resume location. */
994 if (prev_regnum == ARM_PC_REGNUM)
995 prev_regnum = ARM_LR_REGNUM;
997 /* SP is generally not saved to the stack, but this frame is
998 identified by NEXT_FRAME's stack pointer at the time of the call.
999 The value was already reconstructed into PREV_SP. */
1000 if (prev_regnum == ARM_SP_REGNUM)
1004 store_unsigned_integer (valuep, 4, cache->prev_sp);
1008 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
1009 optimized, lvalp, addrp, realnump, valuep);
1012 struct frame_unwind arm_prologue_unwind = {
1014 arm_prologue_this_id,
1015 arm_prologue_prev_register
1018 static const struct frame_unwind *
1019 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
1021 return &arm_prologue_unwind;
1024 static struct arm_prologue_cache *
1025 arm_make_stub_cache (struct frame_info *next_frame)
1028 struct arm_prologue_cache *cache;
1029 CORE_ADDR unwound_fp;
1031 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1032 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1034 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1039 /* Our frame ID for a stub frame is the current SP and LR. */
1042 arm_stub_this_id (struct frame_info *next_frame,
1044 struct frame_id *this_id)
1046 struct arm_prologue_cache *cache;
1048 if (*this_cache == NULL)
1049 *this_cache = arm_make_stub_cache (next_frame);
1050 cache = *this_cache;
1052 *this_id = frame_id_build (cache->prev_sp,
1053 frame_pc_unwind (next_frame));
1056 struct frame_unwind arm_stub_unwind = {
1059 arm_prologue_prev_register
1062 static const struct frame_unwind *
1063 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1065 CORE_ADDR addr_in_block;
1068 addr_in_block = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1069 if (in_plt_section (addr_in_block, NULL)
1070 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1071 return &arm_stub_unwind;
1077 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1079 struct arm_prologue_cache *cache;
1081 if (*this_cache == NULL)
1082 *this_cache = arm_make_prologue_cache (next_frame);
1083 cache = *this_cache;
1085 return cache->prev_sp - cache->framesize;
1088 struct frame_base arm_normal_base = {
1089 &arm_prologue_unwind,
1090 arm_normal_frame_base,
1091 arm_normal_frame_base,
1092 arm_normal_frame_base
1095 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1096 dummy frame. The frame ID's base needs to match the TOS value
1097 saved by save_dummy_frame_tos() and returned from
1098 arm_push_dummy_call, and the PC needs to match the dummy frame's
1101 static struct frame_id
1102 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1104 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1105 frame_pc_unwind (next_frame));
1108 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1109 be used to construct the previous frame's ID, after looking up the
1110 containing function). */
1113 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1116 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1117 return arm_addr_bits_remove (pc);
1121 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1123 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1126 /* When arguments must be pushed onto the stack, they go on in reverse
1127 order. The code below implements a FILO (stack) to do this. */
1132 struct stack_item *prev;
1136 static struct stack_item *
1137 push_stack_item (struct stack_item *prev, void *contents, int len)
1139 struct stack_item *si;
1140 si = xmalloc (sizeof (struct stack_item));
1141 si->data = xmalloc (len);
1144 memcpy (si->data, contents, len);
1148 static struct stack_item *
1149 pop_stack_item (struct stack_item *si)
1151 struct stack_item *dead = si;
1159 /* Return the alignment (in bytes) of the given type. */
1162 arm_type_align (struct type *t)
1168 t = check_typedef (t);
1169 switch (TYPE_CODE (t))
1172 /* Should never happen. */
1173 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1177 case TYPE_CODE_ENUM:
1181 case TYPE_CODE_RANGE:
1182 case TYPE_CODE_BITSTRING:
1184 case TYPE_CODE_CHAR:
1185 case TYPE_CODE_BOOL:
1186 return TYPE_LENGTH (t);
1188 case TYPE_CODE_ARRAY:
1189 case TYPE_CODE_COMPLEX:
1190 /* TODO: What about vector types? */
1191 return arm_type_align (TYPE_TARGET_TYPE (t));
1193 case TYPE_CODE_STRUCT:
1194 case TYPE_CODE_UNION:
1196 for (n = 0; n < TYPE_NFIELDS (t); n++)
1198 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1206 /* We currently only support passing parameters in integer registers. This
1207 conforms with GCC's default model. Several other variants exist and
1208 we should probably support some of them based on the selected ABI. */
1211 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1212 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1213 struct value **args, CORE_ADDR sp, int struct_return,
1214 CORE_ADDR struct_addr)
1219 struct stack_item *si = NULL;
1221 /* Set the return address. For the ARM, the return breakpoint is
1222 always at BP_ADDR. */
1223 /* XXX Fix for Thumb. */
1224 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1226 /* Walk through the list of args and determine how large a temporary
1227 stack is required. Need to take care here as structs may be
1228 passed on the stack, and we have to to push them. */
1231 argreg = ARM_A1_REGNUM;
1234 /* The struct_return pointer occupies the first parameter
1235 passing register. */
1239 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1240 gdbarch_register_name (gdbarch, argreg),
1241 paddr (struct_addr));
1242 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1246 for (argnum = 0; argnum < nargs; argnum++)
1249 struct type *arg_type;
1250 struct type *target_type;
1251 enum type_code typecode;
1255 arg_type = check_typedef (value_type (args[argnum]));
1256 len = TYPE_LENGTH (arg_type);
1257 target_type = TYPE_TARGET_TYPE (arg_type);
1258 typecode = TYPE_CODE (arg_type);
1259 val = value_contents_writeable (args[argnum]);
1261 align = arm_type_align (arg_type);
1262 /* Round alignment up to a whole number of words. */
1263 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1264 /* Different ABIs have different maximum alignments. */
1265 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1267 /* The APCS ABI only requires word alignment. */
1268 align = INT_REGISTER_SIZE;
1272 /* The AAPCS requires at most doubleword alignment. */
1273 if (align > INT_REGISTER_SIZE * 2)
1274 align = INT_REGISTER_SIZE * 2;
1277 /* Push stack padding for dowubleword alignment. */
1278 if (nstack & (align - 1))
1280 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1281 nstack += INT_REGISTER_SIZE;
1284 /* Doubleword aligned quantities must go in even register pairs. */
1285 if (argreg <= ARM_LAST_ARG_REGNUM
1286 && align > INT_REGISTER_SIZE
1290 /* If the argument is a pointer to a function, and it is a
1291 Thumb function, create a LOCAL copy of the value and set
1292 the THUMB bit in it. */
1293 if (TYPE_CODE_PTR == typecode
1294 && target_type != NULL
1295 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1297 CORE_ADDR regval = extract_unsigned_integer (val, len);
1298 if (arm_pc_is_thumb (regval))
1301 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1305 /* Copy the argument to general registers or the stack in
1306 register-sized pieces. Large arguments are split between
1307 registers and stack. */
1310 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1312 if (argreg <= ARM_LAST_ARG_REGNUM)
1314 /* The argument is being passed in a general purpose
1316 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1317 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1318 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1320 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1322 gdbarch_register_name
1324 phex (regval, INT_REGISTER_SIZE));
1325 regcache_cooked_write_unsigned (regcache, argreg, regval);
1330 /* Push the arguments onto the stack. */
1332 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1334 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1335 nstack += INT_REGISTER_SIZE;
1342 /* If we have an odd number of words to push, then decrement the stack
1343 by one word now, so first stack argument will be dword aligned. */
1350 write_memory (sp, si->data, si->len);
1351 si = pop_stack_item (si);
1354 /* Finally, update teh SP register. */
1355 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1361 /* Always align the frame to an 8-byte boundary. This is required on
1362 some platforms and harmless on the rest. */
1365 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1367 /* Align the stack to eight bytes. */
1368 return sp & ~ (CORE_ADDR) 7;
1372 print_fpu_flags (int flags)
1374 if (flags & (1 << 0))
1375 fputs ("IVO ", stdout);
1376 if (flags & (1 << 1))
1377 fputs ("DVZ ", stdout);
1378 if (flags & (1 << 2))
1379 fputs ("OFL ", stdout);
1380 if (flags & (1 << 3))
1381 fputs ("UFL ", stdout);
1382 if (flags & (1 << 4))
1383 fputs ("INX ", stdout);
1387 /* Print interesting information about the floating point processor
1388 (if present) or emulator. */
1390 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1391 struct frame_info *frame, const char *args)
1393 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1396 type = (status >> 24) & 127;
1397 if (status & (1 << 31))
1398 printf (_("Hardware FPU type %d\n"), type);
1400 printf (_("Software FPU type %d\n"), type);
1401 /* i18n: [floating point unit] mask */
1402 fputs (_("mask: "), stdout);
1403 print_fpu_flags (status >> 16);
1404 /* i18n: [floating point unit] flags */
1405 fputs (_("flags: "), stdout);
1406 print_fpu_flags (status);
1409 /* Return the GDB type object for the "standard" data type of data in
1412 static struct type *
1413 arm_register_type (struct gdbarch *gdbarch, int regnum)
1415 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1416 return builtin_type_arm_ext;
1417 else if (regnum == ARM_SP_REGNUM)
1418 return builtin_type_void_data_ptr;
1419 else if (regnum == ARM_PC_REGNUM)
1420 return builtin_type_void_func_ptr;
1421 else if (regnum >= ARRAY_SIZE (arm_register_names))
1422 /* These registers are only supported on targets which supply
1423 an XML description. */
1424 return builtin_type_int0;
1426 return builtin_type_uint32;
1429 /* Map a DWARF register REGNUM onto the appropriate GDB register
1433 arm_dwarf_reg_to_regnum (int reg)
1435 /* Core integer regs. */
1436 if (reg >= 0 && reg <= 15)
1439 /* Legacy FPA encoding. These were once used in a way which
1440 overlapped with VFP register numbering, so their use is
1441 discouraged, but GDB doesn't support the ARM toolchain
1442 which used them for VFP. */
1443 if (reg >= 16 && reg <= 23)
1444 return ARM_F0_REGNUM + reg - 16;
1446 /* New assignments for the FPA registers. */
1447 if (reg >= 96 && reg <= 103)
1448 return ARM_F0_REGNUM + reg - 96;
1450 /* WMMX register assignments. */
1451 if (reg >= 104 && reg <= 111)
1452 return ARM_WCGR0_REGNUM + reg - 104;
1454 if (reg >= 112 && reg <= 127)
1455 return ARM_WR0_REGNUM + reg - 112;
1457 if (reg >= 192 && reg <= 199)
1458 return ARM_WC0_REGNUM + reg - 192;
1463 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1465 arm_register_sim_regno (int regnum)
1468 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (current_gdbarch));
1470 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1471 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1473 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1474 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1476 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1477 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1479 if (reg < NUM_GREGS)
1480 return SIM_ARM_R0_REGNUM + reg;
1483 if (reg < NUM_FREGS)
1484 return SIM_ARM_FP0_REGNUM + reg;
1487 if (reg < NUM_SREGS)
1488 return SIM_ARM_FPS_REGNUM + reg;
1491 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1494 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1495 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1496 It is thought that this is is the floating-point register format on
1497 little-endian systems. */
1500 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1504 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1505 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1507 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1509 floatformat_from_doublest (fmt, &d, dbl);
1513 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1516 floatformat_to_doublest (fmt, ptr, &d);
1517 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1518 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1520 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1525 condition_true (unsigned long cond, unsigned long status_reg)
1527 if (cond == INST_AL || cond == INST_NV)
1533 return ((status_reg & FLAG_Z) != 0);
1535 return ((status_reg & FLAG_Z) == 0);
1537 return ((status_reg & FLAG_C) != 0);
1539 return ((status_reg & FLAG_C) == 0);
1541 return ((status_reg & FLAG_N) != 0);
1543 return ((status_reg & FLAG_N) == 0);
1545 return ((status_reg & FLAG_V) != 0);
1547 return ((status_reg & FLAG_V) == 0);
1549 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1551 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1553 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1555 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1557 return (((status_reg & FLAG_Z) == 0) &&
1558 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1560 return (((status_reg & FLAG_Z) != 0) ||
1561 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1566 /* Support routines for single stepping. Calculate the next PC value. */
1567 #define submask(x) ((1L << ((x) + 1)) - 1)
1568 #define bit(obj,st) (((obj) >> (st)) & 1)
1569 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1570 #define sbits(obj,st,fn) \
1571 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1572 #define BranchDest(addr,instr) \
1573 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1576 static unsigned long
1577 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1578 unsigned long pc_val, unsigned long status_reg)
1580 unsigned long res, shift;
1581 int rm = bits (inst, 0, 3);
1582 unsigned long shifttype = bits (inst, 5, 6);
1586 int rs = bits (inst, 8, 11);
1587 shift = (rs == 15 ? pc_val + 8
1588 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1591 shift = bits (inst, 7, 11);
1594 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1595 + (bit (inst, 4) ? 12 : 8))
1596 : get_frame_register_unsigned (frame, rm));
1601 res = shift >= 32 ? 0 : res << shift;
1605 res = shift >= 32 ? 0 : res >> shift;
1611 res = ((res & 0x80000000L)
1612 ? ~((~res) >> shift) : res >> shift);
1615 case 3: /* ROR/RRX */
1618 res = (res >> 1) | (carry ? 0x80000000L : 0);
1620 res = (res >> shift) | (res << (32 - shift));
1624 return res & 0xffffffff;
1627 /* Return number of 1-bits in VAL. */
1630 bitcount (unsigned long val)
1633 for (nbits = 0; val != 0; nbits++)
1634 val &= val - 1; /* delete rightmost 1-bit in val */
1639 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1641 struct gdbarch *gdbarch = get_frame_arch (frame);
1642 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1643 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1644 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1645 unsigned long offset;
1647 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1651 /* Fetch the saved PC from the stack. It's stored above
1652 all of the other registers. */
1653 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1654 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1655 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1656 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1658 error (_("Infinite loop detected"));
1660 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1662 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1663 unsigned long cond = bits (inst1, 8, 11);
1664 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1665 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1667 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1669 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1671 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1673 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1674 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1675 nextpc = pc_val + offset;
1676 /* For BLX make sure to clear the low bits. */
1677 if (bits (inst2, 11, 12) == 1)
1678 nextpc = nextpc & 0xfffffffc;
1680 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1682 if (bits (inst1, 3, 6) == 0x0f)
1685 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1687 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1689 error (_("Infinite loop detected"));
1696 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1698 struct gdbarch *gdbarch = get_frame_arch (frame);
1699 unsigned long pc_val;
1700 unsigned long this_instr;
1701 unsigned long status;
1704 if (arm_pc_is_thumb (pc))
1705 return thumb_get_next_pc (frame, pc);
1707 pc_val = (unsigned long) pc;
1708 this_instr = read_memory_unsigned_integer (pc, 4);
1709 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1710 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1712 if (bits (this_instr, 28, 31) == INST_NV)
1713 switch (bits (this_instr, 24, 27))
1718 /* Branch with Link and change to Thumb. */
1719 nextpc = BranchDest (pc, this_instr);
1720 nextpc |= bit (this_instr, 24) << 1;
1722 nextpc = gdbarch_addr_bits_remove (current_gdbarch, nextpc);
1724 error (_("Infinite loop detected"));
1730 /* Coprocessor register transfer. */
1731 if (bits (this_instr, 12, 15) == 15)
1732 error (_("Invalid update to pc in instruction"));
1735 else if (condition_true (bits (this_instr, 28, 31), status))
1737 switch (bits (this_instr, 24, 27))
1740 case 0x1: /* data processing */
1744 unsigned long operand1, operand2, result = 0;
1748 if (bits (this_instr, 12, 15) != 15)
1751 if (bits (this_instr, 22, 25) == 0
1752 && bits (this_instr, 4, 7) == 9) /* multiply */
1753 error (_("Invalid update to pc in instruction"));
1755 /* BX <reg>, BLX <reg> */
1756 if (bits (this_instr, 4, 27) == 0x12fff1
1757 || bits (this_instr, 4, 27) == 0x12fff3)
1759 rn = bits (this_instr, 0, 3);
1760 result = (rn == 15) ? pc_val + 8
1761 : get_frame_register_unsigned (frame, rn);
1762 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1766 error (_("Infinite loop detected"));
1771 /* Multiply into PC */
1772 c = (status & FLAG_C) ? 1 : 0;
1773 rn = bits (this_instr, 16, 19);
1774 operand1 = (rn == 15) ? pc_val + 8
1775 : get_frame_register_unsigned (frame, rn);
1777 if (bit (this_instr, 25))
1779 unsigned long immval = bits (this_instr, 0, 7);
1780 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1781 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1784 else /* operand 2 is a shifted register */
1785 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1787 switch (bits (this_instr, 21, 24))
1790 result = operand1 & operand2;
1794 result = operand1 ^ operand2;
1798 result = operand1 - operand2;
1802 result = operand2 - operand1;
1806 result = operand1 + operand2;
1810 result = operand1 + operand2 + c;
1814 result = operand1 - operand2 + c;
1818 result = operand2 - operand1 + c;
1824 case 0xb: /* tst, teq, cmp, cmn */
1825 result = (unsigned long) nextpc;
1829 result = operand1 | operand2;
1833 /* Always step into a function. */
1838 result = operand1 & ~operand2;
1845 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1849 error (_("Infinite loop detected"));
1854 case 0x5: /* data transfer */
1857 if (bit (this_instr, 20))
1860 if (bits (this_instr, 12, 15) == 15)
1866 if (bit (this_instr, 22))
1867 error (_("Invalid update to pc in instruction"));
1869 /* byte write to PC */
1870 rn = bits (this_instr, 16, 19);
1871 base = (rn == 15) ? pc_val + 8
1872 : get_frame_register_unsigned (frame, rn);
1873 if (bit (this_instr, 24))
1876 int c = (status & FLAG_C) ? 1 : 0;
1877 unsigned long offset =
1878 (bit (this_instr, 25)
1879 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
1880 : bits (this_instr, 0, 11));
1882 if (bit (this_instr, 23))
1887 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1890 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1893 error (_("Infinite loop detected"));
1899 case 0x9: /* block transfer */
1900 if (bit (this_instr, 20))
1903 if (bit (this_instr, 15))
1908 if (bit (this_instr, 23))
1911 unsigned long reglist = bits (this_instr, 0, 14);
1912 offset = bitcount (reglist) * 4;
1913 if (bit (this_instr, 24)) /* pre */
1916 else if (bit (this_instr, 24))
1920 unsigned long rn_val =
1921 get_frame_register_unsigned (frame,
1922 bits (this_instr, 16, 19));
1924 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1928 nextpc = gdbarch_addr_bits_remove
1931 error (_("Infinite loop detected"));
1936 case 0xb: /* branch & link */
1937 case 0xa: /* branch */
1939 nextpc = BranchDest (pc, this_instr);
1941 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1943 error (_("Infinite loop detected"));
1949 case 0xe: /* coproc ops */
1954 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1962 /* single_step() is called just before we want to resume the inferior,
1963 if we want to single-step it but there is no hardware or kernel
1964 single-step support. We find the target of the coming instruction
1965 and breakpoint it. */
1968 arm_software_single_step (struct frame_info *frame)
1970 /* NOTE: This may insert the wrong breakpoint instruction when
1971 single-stepping over a mode-changing instruction, if the
1972 CPSR heuristics are used. */
1974 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
1975 insert_single_step_breakpoint (next_pc);
1980 #include "bfd-in2.h"
1981 #include "libcoff.h"
1984 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1986 if (arm_pc_is_thumb (memaddr))
1988 static asymbol *asym;
1989 static combined_entry_type ce;
1990 static struct coff_symbol_struct csym;
1991 static struct bfd fake_bfd;
1992 static bfd_target fake_target;
1994 if (csym.native == NULL)
1996 /* Create a fake symbol vector containing a Thumb symbol.
1997 This is solely so that the code in print_insn_little_arm()
1998 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1999 the presence of a Thumb symbol and switch to decoding
2000 Thumb instructions. */
2002 fake_target.flavour = bfd_target_coff_flavour;
2003 fake_bfd.xvec = &fake_target;
2004 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2006 csym.symbol.the_bfd = &fake_bfd;
2007 csym.symbol.name = "fake";
2008 asym = (asymbol *) & csym;
2011 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2012 info->symbols = &asym;
2015 info->symbols = NULL;
2017 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
2018 return print_insn_big_arm (memaddr, info);
2020 return print_insn_little_arm (memaddr, info);
2023 /* The following define instruction sequences that will cause ARM
2024 cpu's to take an undefined instruction trap. These are used to
2025 signal a breakpoint to GDB.
2027 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2028 modes. A different instruction is required for each mode. The ARM
2029 cpu's can also be big or little endian. Thus four different
2030 instructions are needed to support all cases.
2032 Note: ARMv4 defines several new instructions that will take the
2033 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2034 not in fact add the new instructions. The new undefined
2035 instructions in ARMv4 are all instructions that had no defined
2036 behaviour in earlier chips. There is no guarantee that they will
2037 raise an exception, but may be treated as NOP's. In practice, it
2038 may only safe to rely on instructions matching:
2040 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2041 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2042 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2044 Even this may only true if the condition predicate is true. The
2045 following use a condition predicate of ALWAYS so it is always TRUE.
2047 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2048 and NetBSD all use a software interrupt rather than an undefined
2049 instruction to force a trap. This can be handled by by the
2050 abi-specific code during establishment of the gdbarch vector. */
2052 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2053 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2054 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2055 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2057 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2058 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2059 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2060 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2062 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2063 the program counter value to determine whether a 16-bit or 32-bit
2064 breakpoint should be used. It returns a pointer to a string of
2065 bytes that encode a breakpoint instruction, stores the length of
2066 the string to *lenptr, and adjusts the program counter (if
2067 necessary) to point to the actual memory location where the
2068 breakpoint should be inserted. */
2070 static const unsigned char *
2071 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2073 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2075 if (arm_pc_is_thumb (*pcptr))
2077 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2078 *lenptr = tdep->thumb_breakpoint_size;
2079 return tdep->thumb_breakpoint;
2083 *lenptr = tdep->arm_breakpoint_size;
2084 return tdep->arm_breakpoint;
2088 /* Extract from an array REGBUF containing the (raw) register state a
2089 function return value of type TYPE, and copy that, in virtual
2090 format, into VALBUF. */
2093 arm_extract_return_value (struct type *type, struct regcache *regs,
2096 if (TYPE_CODE_FLT == TYPE_CODE (type))
2098 switch (gdbarch_tdep (get_regcache_arch (regs))->fp_model)
2102 /* The value is in register F0 in internal format. We need to
2103 extract the raw value and then convert it to the desired
2105 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2107 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2108 convert_from_extended (floatformat_from_type (type), tmpbuf,
2113 case ARM_FLOAT_SOFT_FPA:
2114 case ARM_FLOAT_SOFT_VFP:
2115 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2116 if (TYPE_LENGTH (type) > 4)
2117 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2118 valbuf + INT_REGISTER_SIZE);
2123 (__FILE__, __LINE__,
2124 _("arm_extract_return_value: Floating point model not supported"));
2128 else if (TYPE_CODE (type) == TYPE_CODE_INT
2129 || TYPE_CODE (type) == TYPE_CODE_CHAR
2130 || TYPE_CODE (type) == TYPE_CODE_BOOL
2131 || TYPE_CODE (type) == TYPE_CODE_PTR
2132 || TYPE_CODE (type) == TYPE_CODE_REF
2133 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2135 /* If the the type is a plain integer, then the access is
2136 straight-forward. Otherwise we have to play around a bit more. */
2137 int len = TYPE_LENGTH (type);
2138 int regno = ARM_A1_REGNUM;
2143 /* By using store_unsigned_integer we avoid having to do
2144 anything special for small big-endian values. */
2145 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2146 store_unsigned_integer (valbuf,
2147 (len > INT_REGISTER_SIZE
2148 ? INT_REGISTER_SIZE : len),
2150 len -= INT_REGISTER_SIZE;
2151 valbuf += INT_REGISTER_SIZE;
2156 /* For a structure or union the behaviour is as if the value had
2157 been stored to word-aligned memory and then loaded into
2158 registers with 32-bit load instruction(s). */
2159 int len = TYPE_LENGTH (type);
2160 int regno = ARM_A1_REGNUM;
2161 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2165 regcache_cooked_read (regs, regno++, tmpbuf);
2166 memcpy (valbuf, tmpbuf,
2167 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2168 len -= INT_REGISTER_SIZE;
2169 valbuf += INT_REGISTER_SIZE;
2175 /* Will a function return an aggregate type in memory or in a
2176 register? Return 0 if an aggregate type can be returned in a
2177 register, 1 if it must be returned in memory. */
2180 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2183 enum type_code code;
2185 CHECK_TYPEDEF (type);
2187 /* In the ARM ABI, "integer" like aggregate types are returned in
2188 registers. For an aggregate type to be integer like, its size
2189 must be less than or equal to INT_REGISTER_SIZE and the
2190 offset of each addressable subfield must be zero. Note that bit
2191 fields are not addressable, and all addressable subfields of
2192 unions always start at offset zero.
2194 This function is based on the behaviour of GCC 2.95.1.
2195 See: gcc/arm.c: arm_return_in_memory() for details.
2197 Note: All versions of GCC before GCC 2.95.2 do not set up the
2198 parameters correctly for a function returning the following
2199 structure: struct { float f;}; This should be returned in memory,
2200 not a register. Richard Earnshaw sent me a patch, but I do not
2201 know of any way to detect if a function like the above has been
2202 compiled with the correct calling convention. */
2204 /* All aggregate types that won't fit in a register must be returned
2206 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2211 /* The AAPCS says all aggregates not larger than a word are returned
2213 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2216 /* The only aggregate types that can be returned in a register are
2217 structs and unions. Arrays must be returned in memory. */
2218 code = TYPE_CODE (type);
2219 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2224 /* Assume all other aggregate types can be returned in a register.
2225 Run a check for structures, unions and arrays. */
2228 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2231 /* Need to check if this struct/union is "integer" like. For
2232 this to be true, its size must be less than or equal to
2233 INT_REGISTER_SIZE and the offset of each addressable
2234 subfield must be zero. Note that bit fields are not
2235 addressable, and unions always start at offset zero. If any
2236 of the subfields is a floating point type, the struct/union
2237 cannot be an integer type. */
2239 /* For each field in the object, check:
2240 1) Is it FP? --> yes, nRc = 1;
2241 2) Is it addressable (bitpos != 0) and
2242 not packed (bitsize == 0)?
2246 for (i = 0; i < TYPE_NFIELDS (type); i++)
2248 enum type_code field_type_code;
2249 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2251 /* Is it a floating point type field? */
2252 if (field_type_code == TYPE_CODE_FLT)
2258 /* If bitpos != 0, then we have to care about it. */
2259 if (TYPE_FIELD_BITPOS (type, i) != 0)
2261 /* Bitfields are not addressable. If the field bitsize is
2262 zero, then the field is not packed. Hence it cannot be
2263 a bitfield or any other packed type. */
2264 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2276 /* Write into appropriate registers a function return value of type
2277 TYPE, given in virtual format. */
2280 arm_store_return_value (struct type *type, struct regcache *regs,
2281 const gdb_byte *valbuf)
2283 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2285 char buf[MAX_REGISTER_SIZE];
2287 switch (gdbarch_tdep (get_regcache_arch (regs))->fp_model)
2291 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2292 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2295 case ARM_FLOAT_SOFT_FPA:
2296 case ARM_FLOAT_SOFT_VFP:
2297 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2298 if (TYPE_LENGTH (type) > 4)
2299 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2300 valbuf + INT_REGISTER_SIZE);
2305 (__FILE__, __LINE__,
2306 _("arm_store_return_value: Floating point model not supported"));
2310 else if (TYPE_CODE (type) == TYPE_CODE_INT
2311 || TYPE_CODE (type) == TYPE_CODE_CHAR
2312 || TYPE_CODE (type) == TYPE_CODE_BOOL
2313 || TYPE_CODE (type) == TYPE_CODE_PTR
2314 || TYPE_CODE (type) == TYPE_CODE_REF
2315 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2317 if (TYPE_LENGTH (type) <= 4)
2319 /* Values of one word or less are zero/sign-extended and
2321 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2322 LONGEST val = unpack_long (type, valbuf);
2324 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2325 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2329 /* Integral values greater than one word are stored in consecutive
2330 registers starting with r0. This will always be a multiple of
2331 the regiser size. */
2332 int len = TYPE_LENGTH (type);
2333 int regno = ARM_A1_REGNUM;
2337 regcache_cooked_write (regs, regno++, valbuf);
2338 len -= INT_REGISTER_SIZE;
2339 valbuf += INT_REGISTER_SIZE;
2345 /* For a structure or union the behaviour is as if the value had
2346 been stored to word-aligned memory and then loaded into
2347 registers with 32-bit load instruction(s). */
2348 int len = TYPE_LENGTH (type);
2349 int regno = ARM_A1_REGNUM;
2350 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2354 memcpy (tmpbuf, valbuf,
2355 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2356 regcache_cooked_write (regs, regno++, tmpbuf);
2357 len -= INT_REGISTER_SIZE;
2358 valbuf += INT_REGISTER_SIZE;
2364 /* Handle function return values. */
2366 static enum return_value_convention
2367 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2368 struct regcache *regcache, gdb_byte *readbuf,
2369 const gdb_byte *writebuf)
2371 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2373 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2374 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2375 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2377 if (tdep->struct_return == pcc_struct_return
2378 || arm_return_in_memory (gdbarch, valtype))
2379 return RETURN_VALUE_STRUCT_CONVENTION;
2383 arm_store_return_value (valtype, regcache, writebuf);
2386 arm_extract_return_value (valtype, regcache, readbuf);
2388 return RETURN_VALUE_REGISTER_CONVENTION;
2393 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2396 char buf[INT_REGISTER_SIZE];
2397 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2399 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2401 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2405 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2409 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2410 return the target PC. Otherwise return 0. */
2413 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2417 CORE_ADDR start_addr;
2419 /* Find the starting address and name of the function containing the PC. */
2420 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2423 /* If PC is in a Thumb call or return stub, return the address of the
2424 target PC, which is in a register. The thunk functions are called
2425 _call_via_xx, where x is the register name. The possible names
2426 are r0-r9, sl, fp, ip, sp, and lr. */
2427 if (strncmp (name, "_call_via_", 10) == 0)
2429 /* Use the name suffix to determine which register contains the
2431 static char *table[15] =
2432 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2433 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2436 int offset = strlen (name) - 2;
2438 for (regno = 0; regno <= 14; regno++)
2439 if (strcmp (&name[offset], table[regno]) == 0)
2440 return get_frame_register_unsigned (frame, regno);
2443 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2444 non-interworking calls to foo. We could decode the stubs
2445 to find the target but it's easier to use the symbol table. */
2446 namelen = strlen (name);
2447 if (name[0] == '_' && name[1] == '_'
2448 && ((namelen > 2 + strlen ("_from_thumb")
2449 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2450 strlen ("_from_thumb")) == 0)
2451 || (namelen > 2 + strlen ("_from_arm")
2452 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2453 strlen ("_from_arm")) == 0)))
2456 int target_len = namelen - 2;
2457 struct minimal_symbol *minsym;
2458 struct objfile *objfile;
2459 struct obj_section *sec;
2461 if (name[namelen - 1] == 'b')
2462 target_len -= strlen ("_from_thumb");
2464 target_len -= strlen ("_from_arm");
2466 target_name = alloca (target_len + 1);
2467 memcpy (target_name, name + 2, target_len);
2468 target_name[target_len] = '\0';
2470 sec = find_pc_section (pc);
2471 objfile = (sec == NULL) ? NULL : sec->objfile;
2472 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2474 return SYMBOL_VALUE_ADDRESS (minsym);
2479 return 0; /* not a stub */
2483 set_arm_command (char *args, int from_tty)
2485 printf_unfiltered (_("\
2486 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2487 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2491 show_arm_command (char *args, int from_tty)
2493 cmd_show_list (showarmcmdlist, from_tty, "");
2497 arm_update_current_architecture (void)
2499 struct gdbarch_info info;
2501 /* If the current architecture is not ARM, we have nothing to do. */
2502 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2505 /* Update the architecture. */
2506 gdbarch_info_init (&info);
2508 if (!gdbarch_update_p (info))
2509 internal_error (__FILE__, __LINE__, "could not update architecture");
2513 set_fp_model_sfunc (char *args, int from_tty,
2514 struct cmd_list_element *c)
2516 enum arm_float_model fp_model;
2518 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2519 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2521 arm_fp_model = fp_model;
2525 if (fp_model == ARM_FLOAT_LAST)
2526 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2529 arm_update_current_architecture ();
2533 show_fp_model (struct ui_file *file, int from_tty,
2534 struct cmd_list_element *c, const char *value)
2536 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2538 if (arm_fp_model == ARM_FLOAT_AUTO
2539 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2540 fprintf_filtered (file, _("\
2541 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2542 fp_model_strings[tdep->fp_model]);
2544 fprintf_filtered (file, _("\
2545 The current ARM floating point model is \"%s\".\n"),
2546 fp_model_strings[arm_fp_model]);
2550 arm_set_abi (char *args, int from_tty,
2551 struct cmd_list_element *c)
2553 enum arm_abi_kind arm_abi;
2555 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2556 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2558 arm_abi_global = arm_abi;
2562 if (arm_abi == ARM_ABI_LAST)
2563 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2566 arm_update_current_architecture ();
2570 arm_show_abi (struct ui_file *file, int from_tty,
2571 struct cmd_list_element *c, const char *value)
2573 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2575 if (arm_abi_global == ARM_ABI_AUTO
2576 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2577 fprintf_filtered (file, _("\
2578 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2579 arm_abi_strings[tdep->arm_abi]);
2581 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2585 /* If the user changes the register disassembly style used for info
2586 register and other commands, we have to also switch the style used
2587 in opcodes for disassembly output. This function is run in the "set
2588 arm disassembly" command, and does that. */
2591 set_disassembly_style_sfunc (char *args, int from_tty,
2592 struct cmd_list_element *c)
2594 set_disassembly_style ();
2597 /* Return the ARM register name corresponding to register I. */
2599 arm_register_name (int i)
2601 if (i >= ARRAY_SIZE (arm_register_names))
2602 /* These registers are only supported on targets which supply
2603 an XML description. */
2606 return arm_register_names[i];
2610 set_disassembly_style (void)
2614 /* Find the style that the user wants. */
2615 for (current = 0; current < num_disassembly_options; current++)
2616 if (disassembly_style == valid_disassembly_styles[current])
2618 gdb_assert (current < num_disassembly_options);
2620 /* Synchronize the disassembler. */
2621 set_arm_regname_option (current);
2624 /* Test whether the coff symbol specific value corresponds to a Thumb
2628 coff_sym_is_thumb (int val)
2630 return (val == C_THUMBEXT ||
2631 val == C_THUMBSTAT ||
2632 val == C_THUMBEXTFUNC ||
2633 val == C_THUMBSTATFUNC ||
2634 val == C_THUMBLABEL);
2637 /* arm_coff_make_msymbol_special()
2638 arm_elf_make_msymbol_special()
2640 These functions test whether the COFF or ELF symbol corresponds to
2641 an address in thumb code, and set a "special" bit in a minimal
2642 symbol to indicate that it does. */
2645 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2647 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2649 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2651 MSYMBOL_SET_SPECIAL (msym);
2655 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2657 if (coff_sym_is_thumb (val))
2658 MSYMBOL_SET_SPECIAL (msym);
2662 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2664 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2666 /* If necessary, set the T bit. */
2670 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2671 if (arm_pc_is_thumb (pc))
2672 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | 0x20);
2674 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2675 val & ~(ULONGEST) 0x20);
2679 static struct value *
2680 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2682 const int *reg_p = baton;
2683 return value_of_register (*reg_p, frame);
2686 static enum gdb_osabi
2687 arm_elf_osabi_sniffer (bfd *abfd)
2689 unsigned int elfosabi;
2690 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2692 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2694 if (elfosabi == ELFOSABI_ARM)
2695 /* GNU tools use this value. Check note sections in this case,
2697 bfd_map_over_sections (abfd,
2698 generic_elf_osabi_sniff_abi_tag_sections,
2701 /* Anything else will be handled by the generic ELF sniffer. */
2706 /* Initialize the current architecture based on INFO. If possible,
2707 re-use an architecture from ARCHES, which is a list of
2708 architectures already created during this debugging session.
2710 Called e.g. at program startup, when reading a core file, and when
2711 reading a binary file. */
2713 static struct gdbarch *
2714 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2716 struct gdbarch_tdep *tdep;
2717 struct gdbarch *gdbarch;
2718 struct gdbarch_list *best_arch;
2719 enum arm_abi_kind arm_abi = arm_abi_global;
2720 enum arm_float_model fp_model = arm_fp_model;
2721 struct tdesc_arch_data *tdesc_data = NULL;
2723 int have_fpa_registers = 1;
2725 /* Check any target description for validity. */
2726 if (tdesc_has_registers (info.target_desc))
2728 /* For most registers we require GDB's default names; but also allow
2729 the numeric names for sp / lr / pc, as a convenience. */
2730 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2731 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2732 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2734 const struct tdesc_feature *feature;
2737 feature = tdesc_find_feature (info.target_desc,
2738 "org.gnu.gdb.arm.core");
2739 if (feature == NULL)
2742 tdesc_data = tdesc_data_alloc ();
2745 for (i = 0; i < ARM_SP_REGNUM; i++)
2746 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2747 arm_register_names[i]);
2748 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2751 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2754 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2757 valid_p &= tdesc_numbered_register (feature, tdesc_data,
2758 ARM_PS_REGNUM, "cpsr");
2762 tdesc_data_cleanup (tdesc_data);
2766 feature = tdesc_find_feature (info.target_desc,
2767 "org.gnu.gdb.arm.fpa");
2768 if (feature != NULL)
2771 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
2772 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2773 arm_register_names[i]);
2776 tdesc_data_cleanup (tdesc_data);
2781 have_fpa_registers = 0;
2783 feature = tdesc_find_feature (info.target_desc,
2784 "org.gnu.gdb.xscale.iwmmxt");
2785 if (feature != NULL)
2787 static const char *const iwmmxt_names[] = {
2788 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2789 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2790 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2791 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2795 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
2797 &= tdesc_numbered_register (feature, tdesc_data, i,
2798 iwmmxt_names[i - ARM_WR0_REGNUM]);
2800 /* Check for the control registers, but do not fail if they
2802 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
2803 tdesc_numbered_register (feature, tdesc_data, i,
2804 iwmmxt_names[i - ARM_WR0_REGNUM]);
2806 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
2808 &= tdesc_numbered_register (feature, tdesc_data, i,
2809 iwmmxt_names[i - ARM_WR0_REGNUM]);
2813 tdesc_data_cleanup (tdesc_data);
2819 /* If we have an object to base this architecture on, try to determine
2822 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2824 int ei_osabi, e_flags;
2826 switch (bfd_get_flavour (info.abfd))
2828 case bfd_target_aout_flavour:
2829 /* Assume it's an old APCS-style ABI. */
2830 arm_abi = ARM_ABI_APCS;
2833 case bfd_target_coff_flavour:
2834 /* Assume it's an old APCS-style ABI. */
2836 arm_abi = ARM_ABI_APCS;
2839 case bfd_target_elf_flavour:
2840 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2841 e_flags = elf_elfheader (info.abfd)->e_flags;
2843 if (ei_osabi == ELFOSABI_ARM)
2845 /* GNU tools used to use this value, but do not for EABI
2846 objects. There's nowhere to tag an EABI version
2847 anyway, so assume APCS. */
2848 arm_abi = ARM_ABI_APCS;
2850 else if (ei_osabi == ELFOSABI_NONE)
2852 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2856 case EF_ARM_EABI_UNKNOWN:
2857 /* Assume GNU tools. */
2858 arm_abi = ARM_ABI_APCS;
2861 case EF_ARM_EABI_VER4:
2862 case EF_ARM_EABI_VER5:
2863 arm_abi = ARM_ABI_AAPCS;
2864 /* EABI binaries default to VFP float ordering. */
2865 if (fp_model == ARM_FLOAT_AUTO)
2866 fp_model = ARM_FLOAT_SOFT_VFP;
2870 /* Leave it as "auto". */
2871 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2876 if (fp_model == ARM_FLOAT_AUTO)
2878 int e_flags = elf_elfheader (info.abfd)->e_flags;
2880 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2883 /* Leave it as "auto". Strictly speaking this case
2884 means FPA, but almost nobody uses that now, and
2885 many toolchains fail to set the appropriate bits
2886 for the floating-point model they use. */
2888 case EF_ARM_SOFT_FLOAT:
2889 fp_model = ARM_FLOAT_SOFT_FPA;
2891 case EF_ARM_VFP_FLOAT:
2892 fp_model = ARM_FLOAT_VFP;
2894 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2895 fp_model = ARM_FLOAT_SOFT_VFP;
2902 /* Leave it as "auto". */
2907 /* If there is already a candidate, use it. */
2908 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2910 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2912 if (arm_abi != ARM_ABI_AUTO
2913 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2916 if (fp_model != ARM_FLOAT_AUTO
2917 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2920 /* Found a match. */
2924 if (best_arch != NULL)
2926 if (tdesc_data != NULL)
2927 tdesc_data_cleanup (tdesc_data);
2928 return best_arch->gdbarch;
2931 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2932 gdbarch = gdbarch_alloc (&info, tdep);
2934 /* Record additional information about the architecture we are defining.
2935 These are gdbarch discriminators, like the OSABI. */
2936 tdep->arm_abi = arm_abi;
2937 tdep->fp_model = fp_model;
2938 tdep->have_fpa_registers = have_fpa_registers;
2941 switch (info.byte_order)
2943 case BFD_ENDIAN_BIG:
2944 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2945 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2946 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2947 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2951 case BFD_ENDIAN_LITTLE:
2952 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2953 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2954 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2955 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2960 internal_error (__FILE__, __LINE__,
2961 _("arm_gdbarch_init: bad byte order for float format"));
2964 /* On ARM targets char defaults to unsigned. */
2965 set_gdbarch_char_signed (gdbarch, 0);
2967 /* This should be low enough for everything. */
2968 tdep->lowest_pc = 0x20;
2969 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2971 /* The default, for both APCS and AAPCS, is to return small
2972 structures in registers. */
2973 tdep->struct_return = reg_struct_return;
2975 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2976 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2978 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2980 /* Frame handling. */
2981 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2982 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2983 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2985 frame_base_set_default (gdbarch, &arm_normal_base);
2987 /* Address manipulation. */
2988 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2989 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2991 /* Advance PC across function entry code. */
2992 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2994 /* Skip trampolines. */
2995 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
2997 /* The stack grows downward. */
2998 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3000 /* Breakpoint manipulation. */
3001 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3003 /* Information about registers, etc. */
3004 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3005 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3006 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3007 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3008 set_gdbarch_register_type (gdbarch, arm_register_type);
3010 /* This "info float" is FPA-specific. Use the generic version if we
3012 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3013 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3015 /* Internal <-> external register number maps. */
3016 set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3017 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3018 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3020 set_gdbarch_register_name (gdbarch, arm_register_name);
3022 /* Returning results. */
3023 set_gdbarch_return_value (gdbarch, arm_return_value);
3026 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3028 /* Minsymbol frobbing. */
3029 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3030 set_gdbarch_coff_make_msymbol_special (gdbarch,
3031 arm_coff_make_msymbol_special);
3033 /* Virtual tables. */
3034 set_gdbarch_vbit_in_delta (gdbarch, 1);
3036 /* Hook in the ABI-specific overrides, if they have been registered. */
3037 gdbarch_init_osabi (info, gdbarch);
3039 /* Add some default predicates. */
3040 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
3041 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3042 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
3044 /* Now we have tuned the configuration, set a few final things,
3045 based on what the OS ABI has told us. */
3047 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3048 binaries are always marked. */
3049 if (tdep->arm_abi == ARM_ABI_AUTO)
3050 tdep->arm_abi = ARM_ABI_APCS;
3052 /* We used to default to FPA for generic ARM, but almost nobody
3053 uses that now, and we now provide a way for the user to force
3054 the model. So default to the most useful variant. */
3055 if (tdep->fp_model == ARM_FLOAT_AUTO)
3056 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3058 if (tdep->jb_pc >= 0)
3059 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3061 /* Floating point sizes and format. */
3062 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3063 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3065 set_gdbarch_double_format
3066 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3067 set_gdbarch_long_double_format
3068 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3072 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3073 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3077 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3079 /* Add standard register aliases. We add aliases even for those
3080 nanes which are used by the current architecture - it's simpler,
3081 and does no harm, since nothing ever lists user registers. */
3082 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3083 user_reg_add (gdbarch, arm_register_aliases[i].name,
3084 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3090 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3092 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3097 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3098 (unsigned long) tdep->lowest_pc);
3101 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3104 _initialize_arm_tdep (void)
3106 struct ui_file *stb;
3108 struct cmd_list_element *new_set, *new_show;
3109 const char *setname;
3110 const char *setdesc;
3111 const char *const *regnames;
3113 static char *helptext;
3114 char regdesc[1024], *rdptr = regdesc;
3115 size_t rest = sizeof (regdesc);
3117 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3119 /* Register an ELF OS ABI sniffer for ARM binaries. */
3120 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3121 bfd_target_elf_flavour,
3122 arm_elf_osabi_sniffer);
3124 /* Get the number of possible sets of register names defined in opcodes. */
3125 num_disassembly_options = get_arm_regname_num_options ();
3127 /* Add root prefix command for all "set arm"/"show arm" commands. */
3128 add_prefix_cmd ("arm", no_class, set_arm_command,
3129 _("Various ARM-specific commands."),
3130 &setarmcmdlist, "set arm ", 0, &setlist);
3132 add_prefix_cmd ("arm", no_class, show_arm_command,
3133 _("Various ARM-specific commands."),
3134 &showarmcmdlist, "show arm ", 0, &showlist);
3136 /* Sync the opcode insn printer with our register viewer. */
3137 parse_arm_disassembler_option ("reg-names-std");
3139 /* Initialize the array that will be passed to
3140 add_setshow_enum_cmd(). */
3141 valid_disassembly_styles
3142 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3143 for (i = 0; i < num_disassembly_options; i++)
3145 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3146 valid_disassembly_styles[i] = setname;
3147 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3150 /* When we find the default names, tell the disassembler to use
3152 if (!strcmp (setname, "std"))
3154 disassembly_style = setname;
3155 set_arm_regname_option (i);
3158 /* Mark the end of valid options. */
3159 valid_disassembly_styles[num_disassembly_options] = NULL;
3161 /* Create the help text. */
3162 stb = mem_fileopen ();
3163 fprintf_unfiltered (stb, "%s%s%s",
3164 _("The valid values are:\n"),
3166 _("The default is \"std\"."));
3167 helptext = ui_file_xstrdup (stb, &length);
3168 ui_file_delete (stb);
3170 add_setshow_enum_cmd("disassembler", no_class,
3171 valid_disassembly_styles, &disassembly_style,
3172 _("Set the disassembly style."),
3173 _("Show the disassembly style."),
3175 set_disassembly_style_sfunc,
3176 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3177 &setarmcmdlist, &showarmcmdlist);
3179 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3180 _("Set usage of ARM 32-bit mode."),
3181 _("Show usage of ARM 32-bit mode."),
3182 _("When off, a 26-bit PC will be used."),
3184 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3185 &setarmcmdlist, &showarmcmdlist);
3187 /* Add a command to allow the user to force the FPU model. */
3188 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3189 _("Set the floating point type."),
3190 _("Show the floating point type."),
3191 _("auto - Determine the FP typefrom the OS-ABI.\n\
3192 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3193 fpa - FPA co-processor (GCC compiled).\n\
3194 softvfp - Software FP with pure-endian doubles.\n\
3195 vfp - VFP co-processor."),
3196 set_fp_model_sfunc, show_fp_model,
3197 &setarmcmdlist, &showarmcmdlist);
3199 /* Add a command to allow the user to force the ABI. */
3200 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3203 NULL, arm_set_abi, arm_show_abi,
3204 &setarmcmdlist, &showarmcmdlist);
3206 /* Debugging flag. */
3207 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3208 _("Set ARM debugging."),
3209 _("Show ARM debugging."),
3210 _("When on, arm-specific debugging is enabled."),
3212 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3213 &setdebuglist, &showdebuglist);