1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
57 /* Macros for setting and testing a bit in a minimal symbol that marks
58 it as Thumb function. The MSB of the minimal symbol's "info" field
59 is used for this purpose.
61 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
62 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64 #define MSYMBOL_SET_SPECIAL(msym) \
65 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71 /* The list of available "set arm ..." and "show arm ..." commands. */
72 static struct cmd_list_element *setarmcmdlist = NULL;
73 static struct cmd_list_element *showarmcmdlist = NULL;
75 /* The type of floating-point to use. Keep this in sync with enum
76 arm_float_model, and the help string in _initialize_arm_tdep. */
77 static const char *fp_model_strings[] =
87 /* A variable that can be configured by the user. */
88 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
89 static const char *current_fp_model = "auto";
91 /* The ABI to use. Keep this in sync with arm_abi_kind. */
92 static const char *arm_abi_strings[] =
100 /* A variable that can be configured by the user. */
101 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
102 static const char *arm_abi_string = "auto";
104 /* The execution mode to assume. */
105 static const char *arm_mode_strings[] =
112 static const char *arm_fallback_mode_string = "auto";
113 static const char *arm_force_mode_string = "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options;
118 /* The standard register names, and all the valid aliases for them. */
123 } arm_register_aliases[] = {
124 /* Basic register numbers. */
141 /* Synonyms (argument and variable registers). */
154 /* Other platform-specific names for r9. */
162 /* Names used by GCC (not listed in the ARM EABI). */
165 /* A special name from the older ATPCS. */
169 static const char *const arm_register_names[] =
170 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
171 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
172 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
173 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
174 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
175 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
176 "fps", "cpsr" }; /* 24 25 */
178 /* Valid register name styles. */
179 static const char **valid_disassembly_styles;
181 /* Disassembly style to use. Default to "std" register names. */
182 static const char *disassembly_style;
184 /* This is used to keep the bfd arch_info in sync with the disassembly
186 static void set_disassembly_style_sfunc(char *, int,
187 struct cmd_list_element *);
188 static void set_disassembly_style (void);
190 static void convert_from_extended (const struct floatformat *, const void *,
192 static void convert_to_extended (const struct floatformat *, void *,
195 struct arm_prologue_cache
197 /* The stack pointer at the time this frame was created; i.e. the
198 caller's stack pointer when this function was called. It is used
199 to identify this frame. */
202 /* The frame base for this frame is just prev_sp - frame size.
203 FRAMESIZE is the distance from the frame pointer to the
204 initial stack pointer. */
208 /* The register used to hold the frame pointer for this frame. */
211 /* Saved register offsets. */
212 struct trad_frame_saved_reg *saved_regs;
215 /* Addresses for calling Thumb functions have the bit 0 set.
216 Here are some macros to test, set, or clear bit 0 of addresses. */
217 #define IS_THUMB_ADDR(addr) ((addr) & 1)
218 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
219 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
221 /* Set to true if the 32-bit mode is in use. */
225 /* Determine if FRAME is executing in Thumb mode. */
228 arm_frame_is_thumb (struct frame_info *frame)
232 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
233 directly (from a signal frame or dummy frame) or by interpreting
234 the saved LR (from a prologue or DWARF frame). So consult it and
235 trust the unwinders. */
236 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
238 return (cpsr & CPSR_T) != 0;
241 /* Determine if the program counter specified in MEMADDR is in a Thumb
242 function. This function should be called for addresses unrelated to
243 any executing frame; otherwise, prefer arm_frame_is_thumb. */
246 arm_pc_is_thumb (CORE_ADDR memaddr)
248 struct minimal_symbol *sym;
250 /* If bit 0 of the address is set, assume this is a Thumb address. */
251 if (IS_THUMB_ADDR (memaddr))
254 /* If the user wants to override the symbol table, let him. */
255 if (strcmp (arm_force_mode_string, "arm") == 0)
257 if (strcmp (arm_force_mode_string, "thumb") == 0)
260 /* Thumb functions have a "special" bit set in minimal symbols. */
261 sym = lookup_minimal_symbol_by_pc (memaddr);
263 return (MSYMBOL_IS_SPECIAL (sym));
265 /* If the user wants to override the fallback mode, let them. */
266 if (strcmp (arm_fallback_mode_string, "arm") == 0)
268 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
271 /* If we couldn't find any symbol, but we're talking to a running
272 target, then trust the current value of $cpsr. This lets
273 "display/i $pc" always show the correct mode (though if there is
274 a symbol table we will not reach here, so it still may not be
275 displayed in the mode it will be executed). */
276 if (target_has_registers)
277 return arm_frame_is_thumb (get_current_frame ());
279 /* Otherwise we're out of luck; we assume ARM. */
283 /* Remove useless bits from addresses in a running program. */
285 arm_addr_bits_remove (CORE_ADDR val)
288 return UNMAKE_THUMB_ADDR (val);
290 return (val & 0x03fffffc);
293 /* When reading symbols, we need to zap the low bit of the address,
294 which may be set to 1 for Thumb functions. */
296 arm_smash_text_address (CORE_ADDR val)
301 /* Analyze a Thumb prologue, looking for a recognizable stack frame
302 and frame pointer. Scan until we encounter a store that could
303 clobber the stack frame unexpectedly, or an unknown instruction. */
306 thumb_analyze_prologue (struct gdbarch *gdbarch,
307 CORE_ADDR start, CORE_ADDR limit,
308 struct arm_prologue_cache *cache)
312 struct pv_area *stack;
313 struct cleanup *back_to;
316 for (i = 0; i < 16; i++)
317 regs[i] = pv_register (i, 0);
318 stack = make_pv_area (ARM_SP_REGNUM);
319 back_to = make_cleanup_free_pv_area (stack);
321 while (start < limit)
325 insn = read_memory_unsigned_integer (start, 2);
327 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
332 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
335 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
336 whether to save LR (R14). */
337 mask = (insn & 0xff) | ((insn & 0x100) << 6);
339 /* Calculate offsets of saved R0-R7 and LR. */
340 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
341 if (mask & (1 << regno))
343 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
345 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
348 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
351 offset = (insn & 0x7f) << 2; /* get scaled offset */
352 if (insn & 0x80) /* Check for SUB. */
353 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
356 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
359 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
360 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
362 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
364 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
365 int src_reg = (insn & 0x78) >> 3;
366 regs[dst_reg] = regs[src_reg];
368 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
370 /* Handle stores to the stack. Normally pushes are used,
371 but with GCC -mtpcs-frame, there may be other stores
372 in the prologue to create the frame. */
373 int regno = (insn >> 8) & 0x7;
376 offset = (insn & 0xff) << 2;
377 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
379 if (pv_area_store_would_trash (stack, addr))
382 pv_area_store (stack, addr, 4, regs[regno]);
386 /* We don't know what this instruction is. We're finished
387 scanning. NOTE: Recognizing more safe-to-ignore
388 instructions here will improve support for optimized
398 do_cleanups (back_to);
402 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
404 /* Frame pointer is fp. Frame size is constant. */
405 cache->framereg = ARM_FP_REGNUM;
406 cache->framesize = -regs[ARM_FP_REGNUM].k;
408 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
410 /* Frame pointer is r7. Frame size is constant. */
411 cache->framereg = THUMB_FP_REGNUM;
412 cache->framesize = -regs[THUMB_FP_REGNUM].k;
414 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
416 /* Try the stack pointer... this is a bit desperate. */
417 cache->framereg = ARM_SP_REGNUM;
418 cache->framesize = -regs[ARM_SP_REGNUM].k;
422 /* We're just out of luck. We don't know where the frame is. */
423 cache->framereg = -1;
424 cache->framesize = 0;
427 for (i = 0; i < 16; i++)
428 if (pv_area_find_reg (stack, gdbarch, i, &offset))
429 cache->saved_regs[i].addr = offset;
431 do_cleanups (back_to);
435 /* Advance the PC across any function entry prologue instructions to
436 reach some "real" code.
438 The APCS (ARM Procedure Call Standard) defines the following
442 [stmfd sp!, {a1,a2,a3,a4}]
443 stmfd sp!, {...,fp,ip,lr,pc}
444 [stfe f7, [sp, #-12]!]
445 [stfe f6, [sp, #-12]!]
446 [stfe f5, [sp, #-12]!]
447 [stfe f4, [sp, #-12]!]
448 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
451 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
455 CORE_ADDR func_addr, func_end = 0;
457 struct symtab_and_line sal;
459 /* If we're in a dummy frame, don't even try to skip the prologue. */
460 if (deprecated_pc_in_call_dummy (pc))
463 /* See what the symbol table says. */
465 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
469 /* Found a function. */
470 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
471 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
473 /* Don't use this trick for assembly source files. */
474 sal = find_pc_line (func_addr, 0);
475 if ((sal.line != 0) && (sal.end < func_end))
480 /* Can't find the prologue end in the symbol table, try it the hard way
481 by disassembling the instructions. */
483 /* Like arm_scan_prologue, stop no later than pc + 64. */
484 if (func_end == 0 || func_end > pc + 64)
487 /* Check if this is Thumb code. */
488 if (arm_pc_is_thumb (pc))
489 return thumb_analyze_prologue (gdbarch, pc, func_end, NULL);
491 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
493 inst = read_memory_unsigned_integer (skip_pc, 4);
495 /* "mov ip, sp" is no longer a required part of the prologue. */
496 if (inst == 0xe1a0c00d) /* mov ip, sp */
499 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
502 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
505 /* Some prologues begin with "str lr, [sp, #-4]!". */
506 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
509 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
512 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
515 /* Any insns after this point may float into the code, if it makes
516 for better instruction scheduling, so we skip them only if we
517 find them, but still consider the function to be frame-ful. */
519 /* We may have either one sfmfd instruction here, or several stfe
520 insns, depending on the version of floating point code we
522 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
525 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
528 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
531 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
534 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
535 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
536 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
539 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
540 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
541 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
544 /* Un-recognized instruction; stop scanning. */
548 return skip_pc; /* End of prologue */
552 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
553 This function decodes a Thumb function prologue to determine:
554 1) the size of the stack frame
555 2) which registers are saved on it
556 3) the offsets of saved regs
557 4) the offset from the stack pointer to the frame pointer
559 A typical Thumb function prologue would create this stack frame
560 (offsets relative to FP)
561 old SP -> 24 stack parameters
564 R7 -> 0 local variables (16 bytes)
565 SP -> -12 additional stack space (12 bytes)
566 The frame size would thus be 36 bytes, and the frame offset would be
567 12 bytes. The frame register is R7.
569 The comments for thumb_skip_prolog() describe the algorithm we use
570 to detect the end of the prolog. */
574 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
575 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
577 CORE_ADDR prologue_start;
578 CORE_ADDR prologue_end;
579 CORE_ADDR current_pc;
581 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
584 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
586 if (sal.line == 0) /* no line info, use current PC */
587 prologue_end = prev_pc;
588 else if (sal.end < prologue_end) /* next line begins after fn end */
589 prologue_end = sal.end; /* (probably means no prologue) */
592 /* We're in the boondocks: we have no idea where the start of the
596 prologue_end = min (prologue_end, prev_pc);
598 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
601 /* This function decodes an ARM function prologue to determine:
602 1) the size of the stack frame
603 2) which registers are saved on it
604 3) the offsets of saved regs
605 4) the offset from the stack pointer to the frame pointer
606 This information is stored in the "extra" fields of the frame_info.
608 There are two basic forms for the ARM prologue. The fixed argument
609 function call will look like:
612 stmfd sp!, {fp, ip, lr, pc}
616 Which would create this stack frame (offsets relative to FP):
617 IP -> 4 (caller's stack)
618 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
619 -4 LR (return address in caller)
620 -8 IP (copy of caller's SP)
622 SP -> -28 Local variables
624 The frame size would thus be 32 bytes, and the frame offset would be
625 28 bytes. The stmfd call can also save any of the vN registers it
626 plans to use, which increases the frame size accordingly.
628 Note: The stored PC is 8 off of the STMFD instruction that stored it
629 because the ARM Store instructions always store PC + 8 when you read
632 A variable argument function call will look like:
635 stmfd sp!, {a1, a2, a3, a4}
636 stmfd sp!, {fp, ip, lr, pc}
639 Which would create this stack frame (offsets relative to FP):
640 IP -> 20 (caller's stack)
645 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
646 -4 LR (return address in caller)
647 -8 IP (copy of caller's SP)
649 SP -> -28 Local variables
651 The frame size would thus be 48 bytes, and the frame offset would be
654 There is another potential complication, which is that the optimizer
655 will try to separate the store of fp in the "stmfd" instruction from
656 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
657 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
659 Also, note, the original version of the ARM toolchain claimed that there
662 instruction at the end of the prologue. I have never seen GCC produce
663 this, and the ARM docs don't mention it. We still test for it below in
669 arm_scan_prologue (struct frame_info *this_frame,
670 struct arm_prologue_cache *cache)
672 struct gdbarch *gdbarch = get_frame_arch (this_frame);
674 CORE_ADDR prologue_start, prologue_end, current_pc;
675 CORE_ADDR prev_pc = get_frame_pc (this_frame);
676 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
677 pv_t regs[ARM_FPS_REGNUM];
678 struct pv_area *stack;
679 struct cleanup *back_to;
682 /* Assume there is no frame until proven otherwise. */
683 cache->framereg = ARM_SP_REGNUM;
684 cache->framesize = 0;
686 /* Check for Thumb prologue. */
687 if (arm_frame_is_thumb (this_frame))
689 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
693 /* Find the function prologue. If we can't find the function in
694 the symbol table, peek in the stack frame to find the PC. */
695 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
698 /* One way to find the end of the prologue (which works well
699 for unoptimized code) is to do the following:
701 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
704 prologue_end = prev_pc;
705 else if (sal.end < prologue_end)
706 prologue_end = sal.end;
708 This mechanism is very accurate so long as the optimizer
709 doesn't move any instructions from the function body into the
710 prologue. If this happens, sal.end will be the last
711 instruction in the first hunk of prologue code just before
712 the first instruction that the scheduler has moved from
713 the body to the prologue.
715 In order to make sure that we scan all of the prologue
716 instructions, we use a slightly less accurate mechanism which
717 may scan more than necessary. To help compensate for this
718 lack of accuracy, the prologue scanning loop below contains
719 several clauses which'll cause the loop to terminate early if
720 an implausible prologue instruction is encountered.
726 is a suitable endpoint since it accounts for the largest
727 possible prologue plus up to five instructions inserted by
730 if (prologue_end > prologue_start + 64)
732 prologue_end = prologue_start + 64; /* See above. */
737 /* We have no symbol information. Our only option is to assume this
738 function has a standard stack frame and the normal frame register.
739 Then, we can find the value of our frame pointer on entrance to
740 the callee (or at the present moment if this is the innermost frame).
741 The value stored there should be the address of the stmfd + 8. */
743 LONGEST return_value;
745 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
746 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
750 prologue_start = gdbarch_addr_bits_remove
751 (gdbarch, return_value) - 8;
752 prologue_end = prologue_start + 64; /* See above. */
756 if (prev_pc < prologue_end)
757 prologue_end = prev_pc;
759 /* Now search the prologue looking for instructions that set up the
760 frame pointer, adjust the stack pointer, and save registers.
762 Be careful, however, and if it doesn't look like a prologue,
763 don't try to scan it. If, for instance, a frameless function
764 begins with stmfd sp!, then we will tell ourselves there is
765 a frame, which will confuse stack traceback, as well as "finish"
766 and other operations that rely on a knowledge of the stack
769 In the APCS, the prologue should start with "mov ip, sp" so
770 if we don't see this as the first insn, we will stop.
772 [Note: This doesn't seem to be true any longer, so it's now an
773 optional part of the prologue. - Kevin Buettner, 2001-11-20]
775 [Note further: The "mov ip,sp" only seems to be missing in
776 frameless functions at optimization level "-O2" or above,
777 in which case it is often (but not always) replaced by
778 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
780 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
781 regs[regno] = pv_register (regno, 0);
782 stack = make_pv_area (ARM_SP_REGNUM);
783 back_to = make_cleanup_free_pv_area (stack);
785 for (current_pc = prologue_start;
786 current_pc < prologue_end;
789 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
791 if (insn == 0xe1a0c00d) /* mov ip, sp */
793 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
796 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
798 unsigned imm = insn & 0xff; /* immediate value */
799 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
800 imm = (imm >> rot) | (imm << (32 - rot));
801 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
804 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
806 unsigned imm = insn & 0xff; /* immediate value */
807 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
808 imm = (imm >> rot) | (imm << (32 - rot));
809 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
812 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
814 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
816 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
817 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
820 else if ((insn & 0xffff0000) == 0xe92d0000)
821 /* stmfd sp!, {..., fp, ip, lr, pc}
823 stmfd sp!, {a1, a2, a3, a4} */
825 int mask = insn & 0xffff;
827 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
830 /* Calculate offsets of saved registers. */
831 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
832 if (mask & (1 << regno))
834 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
835 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
838 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
839 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
840 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
842 /* No need to add this to saved_regs -- it's just an arg reg. */
845 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
846 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
847 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
849 /* No need to add this to saved_regs -- it's just an arg reg. */
852 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
854 unsigned imm = insn & 0xff; /* immediate value */
855 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
856 imm = (imm >> rot) | (imm << (32 - rot));
857 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
859 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
861 unsigned imm = insn & 0xff; /* immediate value */
862 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
863 imm = (imm >> rot) | (imm << (32 - rot));
864 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
866 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
867 && gdbarch_tdep (gdbarch)->have_fpa_registers)
869 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
872 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
873 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
874 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
876 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
877 && gdbarch_tdep (gdbarch)->have_fpa_registers)
880 unsigned int fp_start_reg, fp_bound_reg;
882 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
885 if ((insn & 0x800) == 0x800) /* N0 is set */
887 if ((insn & 0x40000) == 0x40000) /* N1 is set */
894 if ((insn & 0x40000) == 0x40000) /* N1 is set */
900 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
901 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
902 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
904 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
905 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
906 regs[fp_start_reg++]);
909 else if ((insn & 0xf0000000) != 0xe0000000)
910 break; /* Condition not true, exit early */
911 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
912 break; /* Don't scan past a block load */
914 /* The optimizer might shove anything into the prologue,
915 so we just skip what we don't recognize. */
919 /* The frame size is just the distance from the frame register
920 to the original stack pointer. */
921 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
923 /* Frame pointer is fp. */
924 cache->framereg = ARM_FP_REGNUM;
925 cache->framesize = -regs[ARM_FP_REGNUM].k;
927 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
929 /* Try the stack pointer... this is a bit desperate. */
930 cache->framereg = ARM_SP_REGNUM;
931 cache->framesize = -regs[ARM_SP_REGNUM].k;
935 /* We're just out of luck. We don't know where the frame is. */
936 cache->framereg = -1;
937 cache->framesize = 0;
940 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
941 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
942 cache->saved_regs[regno].addr = offset;
944 do_cleanups (back_to);
947 static struct arm_prologue_cache *
948 arm_make_prologue_cache (struct frame_info *this_frame)
951 struct arm_prologue_cache *cache;
952 CORE_ADDR unwound_fp;
954 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
955 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
957 arm_scan_prologue (this_frame, cache);
959 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
963 cache->prev_sp = unwound_fp + cache->framesize;
965 /* Calculate actual addresses of saved registers using offsets
966 determined by arm_scan_prologue. */
967 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
968 if (trad_frame_addr_p (cache->saved_regs, reg))
969 cache->saved_regs[reg].addr += cache->prev_sp;
974 /* Our frame ID for a normal frame is the current function's starting PC
975 and the caller's SP when we were called. */
978 arm_prologue_this_id (struct frame_info *this_frame,
980 struct frame_id *this_id)
982 struct arm_prologue_cache *cache;
986 if (*this_cache == NULL)
987 *this_cache = arm_make_prologue_cache (this_frame);
990 func = get_frame_func (this_frame);
992 /* This is meant to halt the backtrace at "_start". Make sure we
993 don't halt it at a generic dummy frame. */
994 if (func <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
997 /* If we've hit a wall, stop. */
998 if (cache->prev_sp == 0)
1001 id = frame_id_build (cache->prev_sp, func);
1005 static struct value *
1006 arm_prologue_prev_register (struct frame_info *this_frame,
1010 struct arm_prologue_cache *cache;
1012 if (*this_cache == NULL)
1013 *this_cache = arm_make_prologue_cache (this_frame);
1014 cache = *this_cache;
1016 /* If we are asked to unwind the PC, then we need to return the LR
1017 instead. The prologue may save PC, but it will point into this
1018 frame's prologue, not the next frame's resume location. Also
1019 strip the saved T bit. A valid LR may have the low bit set, but
1020 a valid PC never does. */
1021 if (prev_regnum == ARM_PC_REGNUM)
1025 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1026 return frame_unwind_got_constant (this_frame, prev_regnum,
1027 arm_addr_bits_remove (lr));
1030 /* SP is generally not saved to the stack, but this frame is
1031 identified by the next frame's stack pointer at the time of the call.
1032 The value was already reconstructed into PREV_SP. */
1033 if (prev_regnum == ARM_SP_REGNUM)
1034 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1036 /* The CPSR may have been changed by the call instruction and by the
1037 called function. The only bit we can reconstruct is the T bit,
1038 by checking the low bit of LR as of the call. This is a reliable
1039 indicator of Thumb-ness except for some ARM v4T pre-interworking
1040 Thumb code, which could get away with a clear low bit as long as
1041 the called function did not use bx. Guess that all other
1042 bits are unchanged; the condition flags are presumably lost,
1043 but the processor status is likely valid. */
1044 if (prev_regnum == ARM_PS_REGNUM)
1048 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1049 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1050 if (IS_THUMB_ADDR (lr))
1054 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1057 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1061 struct frame_unwind arm_prologue_unwind = {
1063 arm_prologue_this_id,
1064 arm_prologue_prev_register,
1066 default_frame_sniffer
1069 static struct arm_prologue_cache *
1070 arm_make_stub_cache (struct frame_info *this_frame)
1073 struct arm_prologue_cache *cache;
1074 CORE_ADDR unwound_fp;
1076 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1077 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1079 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
1084 /* Our frame ID for a stub frame is the current SP and LR. */
1087 arm_stub_this_id (struct frame_info *this_frame,
1089 struct frame_id *this_id)
1091 struct arm_prologue_cache *cache;
1093 if (*this_cache == NULL)
1094 *this_cache = arm_make_stub_cache (this_frame);
1095 cache = *this_cache;
1097 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
1101 arm_stub_unwind_sniffer (const struct frame_unwind *self,
1102 struct frame_info *this_frame,
1103 void **this_prologue_cache)
1105 CORE_ADDR addr_in_block;
1108 addr_in_block = get_frame_address_in_block (this_frame);
1109 if (in_plt_section (addr_in_block, NULL)
1110 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1116 struct frame_unwind arm_stub_unwind = {
1119 arm_prologue_prev_register,
1121 arm_stub_unwind_sniffer
1125 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1127 struct arm_prologue_cache *cache;
1129 if (*this_cache == NULL)
1130 *this_cache = arm_make_prologue_cache (this_frame);
1131 cache = *this_cache;
1133 return cache->prev_sp - cache->framesize;
1136 struct frame_base arm_normal_base = {
1137 &arm_prologue_unwind,
1138 arm_normal_frame_base,
1139 arm_normal_frame_base,
1140 arm_normal_frame_base
1143 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1144 dummy frame. The frame ID's base needs to match the TOS value
1145 saved by save_dummy_frame_tos() and returned from
1146 arm_push_dummy_call, and the PC needs to match the dummy frame's
1149 static struct frame_id
1150 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1152 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1153 get_frame_pc (this_frame));
1156 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1157 be used to construct the previous frame's ID, after looking up the
1158 containing function). */
1161 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1164 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1165 return arm_addr_bits_remove (pc);
1169 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1171 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1174 static struct value *
1175 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1183 /* The PC is normally copied from the return column, which
1184 describes saves of LR. However, that version may have an
1185 extra bit set to indicate Thumb state. The bit is not
1187 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1188 return frame_unwind_got_constant (this_frame, regnum,
1189 arm_addr_bits_remove (lr));
1192 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1193 cpsr = get_frame_register_unsigned (this_frame, regnum);
1194 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1195 if (IS_THUMB_ADDR (lr))
1199 return frame_unwind_got_constant (this_frame, regnum, cpsr);
1202 internal_error (__FILE__, __LINE__,
1203 _("Unexpected register %d"), regnum);
1208 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1209 struct dwarf2_frame_state_reg *reg,
1210 struct frame_info *this_frame)
1216 reg->how = DWARF2_FRAME_REG_FN;
1217 reg->loc.fn = arm_dwarf2_prev_register;
1220 reg->how = DWARF2_FRAME_REG_CFA;
1225 /* When arguments must be pushed onto the stack, they go on in reverse
1226 order. The code below implements a FILO (stack) to do this. */
1231 struct stack_item *prev;
1235 static struct stack_item *
1236 push_stack_item (struct stack_item *prev, void *contents, int len)
1238 struct stack_item *si;
1239 si = xmalloc (sizeof (struct stack_item));
1240 si->data = xmalloc (len);
1243 memcpy (si->data, contents, len);
1247 static struct stack_item *
1248 pop_stack_item (struct stack_item *si)
1250 struct stack_item *dead = si;
1258 /* Return the alignment (in bytes) of the given type. */
1261 arm_type_align (struct type *t)
1267 t = check_typedef (t);
1268 switch (TYPE_CODE (t))
1271 /* Should never happen. */
1272 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1276 case TYPE_CODE_ENUM:
1280 case TYPE_CODE_RANGE:
1281 case TYPE_CODE_BITSTRING:
1283 case TYPE_CODE_CHAR:
1284 case TYPE_CODE_BOOL:
1285 return TYPE_LENGTH (t);
1287 case TYPE_CODE_ARRAY:
1288 case TYPE_CODE_COMPLEX:
1289 /* TODO: What about vector types? */
1290 return arm_type_align (TYPE_TARGET_TYPE (t));
1292 case TYPE_CODE_STRUCT:
1293 case TYPE_CODE_UNION:
1295 for (n = 0; n < TYPE_NFIELDS (t); n++)
1297 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1305 /* We currently only support passing parameters in integer registers. This
1306 conforms with GCC's default model. Several other variants exist and
1307 we should probably support some of them based on the selected ABI. */
1310 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1311 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1312 struct value **args, CORE_ADDR sp, int struct_return,
1313 CORE_ADDR struct_addr)
1318 struct stack_item *si = NULL;
1320 /* Set the return address. For the ARM, the return breakpoint is
1321 always at BP_ADDR. */
1322 /* XXX Fix for Thumb. */
1323 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1325 /* Walk through the list of args and determine how large a temporary
1326 stack is required. Need to take care here as structs may be
1327 passed on the stack, and we have to to push them. */
1330 argreg = ARM_A1_REGNUM;
1333 /* The struct_return pointer occupies the first parameter
1334 passing register. */
1338 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1339 gdbarch_register_name (gdbarch, argreg),
1340 paddr (struct_addr));
1341 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1345 for (argnum = 0; argnum < nargs; argnum++)
1348 struct type *arg_type;
1349 struct type *target_type;
1350 enum type_code typecode;
1354 arg_type = check_typedef (value_type (args[argnum]));
1355 len = TYPE_LENGTH (arg_type);
1356 target_type = TYPE_TARGET_TYPE (arg_type);
1357 typecode = TYPE_CODE (arg_type);
1358 val = value_contents_writeable (args[argnum]);
1360 align = arm_type_align (arg_type);
1361 /* Round alignment up to a whole number of words. */
1362 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1363 /* Different ABIs have different maximum alignments. */
1364 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1366 /* The APCS ABI only requires word alignment. */
1367 align = INT_REGISTER_SIZE;
1371 /* The AAPCS requires at most doubleword alignment. */
1372 if (align > INT_REGISTER_SIZE * 2)
1373 align = INT_REGISTER_SIZE * 2;
1376 /* Push stack padding for dowubleword alignment. */
1377 if (nstack & (align - 1))
1379 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1380 nstack += INT_REGISTER_SIZE;
1383 /* Doubleword aligned quantities must go in even register pairs. */
1384 if (argreg <= ARM_LAST_ARG_REGNUM
1385 && align > INT_REGISTER_SIZE
1389 /* If the argument is a pointer to a function, and it is a
1390 Thumb function, create a LOCAL copy of the value and set
1391 the THUMB bit in it. */
1392 if (TYPE_CODE_PTR == typecode
1393 && target_type != NULL
1394 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1396 CORE_ADDR regval = extract_unsigned_integer (val, len);
1397 if (arm_pc_is_thumb (regval))
1400 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1404 /* Copy the argument to general registers or the stack in
1405 register-sized pieces. Large arguments are split between
1406 registers and stack. */
1409 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1411 if (argreg <= ARM_LAST_ARG_REGNUM)
1413 /* The argument is being passed in a general purpose
1415 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1416 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1417 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1419 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1421 gdbarch_register_name
1423 phex (regval, INT_REGISTER_SIZE));
1424 regcache_cooked_write_unsigned (regcache, argreg, regval);
1429 /* Push the arguments onto the stack. */
1431 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1433 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1434 nstack += INT_REGISTER_SIZE;
1441 /* If we have an odd number of words to push, then decrement the stack
1442 by one word now, so first stack argument will be dword aligned. */
1449 write_memory (sp, si->data, si->len);
1450 si = pop_stack_item (si);
1453 /* Finally, update teh SP register. */
1454 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1460 /* Always align the frame to an 8-byte boundary. This is required on
1461 some platforms and harmless on the rest. */
1464 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1466 /* Align the stack to eight bytes. */
1467 return sp & ~ (CORE_ADDR) 7;
1471 print_fpu_flags (int flags)
1473 if (flags & (1 << 0))
1474 fputs ("IVO ", stdout);
1475 if (flags & (1 << 1))
1476 fputs ("DVZ ", stdout);
1477 if (flags & (1 << 2))
1478 fputs ("OFL ", stdout);
1479 if (flags & (1 << 3))
1480 fputs ("UFL ", stdout);
1481 if (flags & (1 << 4))
1482 fputs ("INX ", stdout);
1486 /* Print interesting information about the floating point processor
1487 (if present) or emulator. */
1489 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1490 struct frame_info *frame, const char *args)
1492 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1495 type = (status >> 24) & 127;
1496 if (status & (1 << 31))
1497 printf (_("Hardware FPU type %d\n"), type);
1499 printf (_("Software FPU type %d\n"), type);
1500 /* i18n: [floating point unit] mask */
1501 fputs (_("mask: "), stdout);
1502 print_fpu_flags (status >> 16);
1503 /* i18n: [floating point unit] flags */
1504 fputs (_("flags: "), stdout);
1505 print_fpu_flags (status);
1508 /* Return the GDB type object for the "standard" data type of data in
1511 static struct type *
1512 arm_register_type (struct gdbarch *gdbarch, int regnum)
1514 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1515 return builtin_type_arm_ext;
1516 else if (regnum == ARM_SP_REGNUM)
1517 return builtin_type_void_data_ptr;
1518 else if (regnum == ARM_PC_REGNUM)
1519 return builtin_type_void_func_ptr;
1520 else if (regnum >= ARRAY_SIZE (arm_register_names))
1521 /* These registers are only supported on targets which supply
1522 an XML description. */
1523 return builtin_type_int0;
1525 return builtin_type_uint32;
1528 /* Map a DWARF register REGNUM onto the appropriate GDB register
1532 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1534 /* Core integer regs. */
1535 if (reg >= 0 && reg <= 15)
1538 /* Legacy FPA encoding. These were once used in a way which
1539 overlapped with VFP register numbering, so their use is
1540 discouraged, but GDB doesn't support the ARM toolchain
1541 which used them for VFP. */
1542 if (reg >= 16 && reg <= 23)
1543 return ARM_F0_REGNUM + reg - 16;
1545 /* New assignments for the FPA registers. */
1546 if (reg >= 96 && reg <= 103)
1547 return ARM_F0_REGNUM + reg - 96;
1549 /* WMMX register assignments. */
1550 if (reg >= 104 && reg <= 111)
1551 return ARM_WCGR0_REGNUM + reg - 104;
1553 if (reg >= 112 && reg <= 127)
1554 return ARM_WR0_REGNUM + reg - 112;
1556 if (reg >= 192 && reg <= 199)
1557 return ARM_WC0_REGNUM + reg - 192;
1562 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1564 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1567 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
1569 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1570 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1572 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1573 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1575 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1576 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1578 if (reg < NUM_GREGS)
1579 return SIM_ARM_R0_REGNUM + reg;
1582 if (reg < NUM_FREGS)
1583 return SIM_ARM_FP0_REGNUM + reg;
1586 if (reg < NUM_SREGS)
1587 return SIM_ARM_FPS_REGNUM + reg;
1590 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1593 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1594 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1595 It is thought that this is is the floating-point register format on
1596 little-endian systems. */
1599 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1600 void *dbl, int endianess)
1604 if (endianess == BFD_ENDIAN_BIG)
1605 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1607 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1609 floatformat_from_doublest (fmt, &d, dbl);
1613 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1618 floatformat_to_doublest (fmt, ptr, &d);
1619 if (endianess == BFD_ENDIAN_BIG)
1620 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1622 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1627 condition_true (unsigned long cond, unsigned long status_reg)
1629 if (cond == INST_AL || cond == INST_NV)
1635 return ((status_reg & FLAG_Z) != 0);
1637 return ((status_reg & FLAG_Z) == 0);
1639 return ((status_reg & FLAG_C) != 0);
1641 return ((status_reg & FLAG_C) == 0);
1643 return ((status_reg & FLAG_N) != 0);
1645 return ((status_reg & FLAG_N) == 0);
1647 return ((status_reg & FLAG_V) != 0);
1649 return ((status_reg & FLAG_V) == 0);
1651 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1653 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1655 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1657 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1659 return (((status_reg & FLAG_Z) == 0) &&
1660 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1662 return (((status_reg & FLAG_Z) != 0) ||
1663 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1668 /* Support routines for single stepping. Calculate the next PC value. */
1669 #define submask(x) ((1L << ((x) + 1)) - 1)
1670 #define bit(obj,st) (((obj) >> (st)) & 1)
1671 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1672 #define sbits(obj,st,fn) \
1673 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1674 #define BranchDest(addr,instr) \
1675 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1678 static unsigned long
1679 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1680 unsigned long pc_val, unsigned long status_reg)
1682 unsigned long res, shift;
1683 int rm = bits (inst, 0, 3);
1684 unsigned long shifttype = bits (inst, 5, 6);
1688 int rs = bits (inst, 8, 11);
1689 shift = (rs == 15 ? pc_val + 8
1690 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1693 shift = bits (inst, 7, 11);
1696 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1697 + (bit (inst, 4) ? 12 : 8))
1698 : get_frame_register_unsigned (frame, rm));
1703 res = shift >= 32 ? 0 : res << shift;
1707 res = shift >= 32 ? 0 : res >> shift;
1713 res = ((res & 0x80000000L)
1714 ? ~((~res) >> shift) : res >> shift);
1717 case 3: /* ROR/RRX */
1720 res = (res >> 1) | (carry ? 0x80000000L : 0);
1722 res = (res >> shift) | (res << (32 - shift));
1726 return res & 0xffffffff;
1729 /* Return number of 1-bits in VAL. */
1732 bitcount (unsigned long val)
1735 for (nbits = 0; val != 0; nbits++)
1736 val &= val - 1; /* delete rightmost 1-bit in val */
1741 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1743 struct gdbarch *gdbarch = get_frame_arch (frame);
1744 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1745 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1746 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1747 unsigned long offset;
1749 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1753 /* Fetch the saved PC from the stack. It's stored above
1754 all of the other registers. */
1755 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1756 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1757 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1758 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1760 error (_("Infinite loop detected"));
1762 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1764 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1765 unsigned long cond = bits (inst1, 8, 11);
1766 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1767 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1769 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1771 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1773 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1775 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1776 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1777 nextpc = pc_val + offset;
1778 /* For BLX make sure to clear the low bits. */
1779 if (bits (inst2, 11, 12) == 1)
1780 nextpc = nextpc & 0xfffffffc;
1782 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1784 if (bits (inst1, 3, 6) == 0x0f)
1787 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1789 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1791 error (_("Infinite loop detected"));
1798 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1800 struct gdbarch *gdbarch = get_frame_arch (frame);
1801 unsigned long pc_val;
1802 unsigned long this_instr;
1803 unsigned long status;
1806 if (arm_frame_is_thumb (frame))
1807 return thumb_get_next_pc (frame, pc);
1809 pc_val = (unsigned long) pc;
1810 this_instr = read_memory_unsigned_integer (pc, 4);
1811 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1812 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1814 if (bits (this_instr, 28, 31) == INST_NV)
1815 switch (bits (this_instr, 24, 27))
1820 /* Branch with Link and change to Thumb. */
1821 nextpc = BranchDest (pc, this_instr);
1822 nextpc |= bit (this_instr, 24) << 1;
1824 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1826 error (_("Infinite loop detected"));
1832 /* Coprocessor register transfer. */
1833 if (bits (this_instr, 12, 15) == 15)
1834 error (_("Invalid update to pc in instruction"));
1837 else if (condition_true (bits (this_instr, 28, 31), status))
1839 switch (bits (this_instr, 24, 27))
1842 case 0x1: /* data processing */
1846 unsigned long operand1, operand2, result = 0;
1850 if (bits (this_instr, 12, 15) != 15)
1853 if (bits (this_instr, 22, 25) == 0
1854 && bits (this_instr, 4, 7) == 9) /* multiply */
1855 error (_("Invalid update to pc in instruction"));
1857 /* BX <reg>, BLX <reg> */
1858 if (bits (this_instr, 4, 27) == 0x12fff1
1859 || bits (this_instr, 4, 27) == 0x12fff3)
1861 rn = bits (this_instr, 0, 3);
1862 result = (rn == 15) ? pc_val + 8
1863 : get_frame_register_unsigned (frame, rn);
1864 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1868 error (_("Infinite loop detected"));
1873 /* Multiply into PC */
1874 c = (status & FLAG_C) ? 1 : 0;
1875 rn = bits (this_instr, 16, 19);
1876 operand1 = (rn == 15) ? pc_val + 8
1877 : get_frame_register_unsigned (frame, rn);
1879 if (bit (this_instr, 25))
1881 unsigned long immval = bits (this_instr, 0, 7);
1882 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1883 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1886 else /* operand 2 is a shifted register */
1887 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1889 switch (bits (this_instr, 21, 24))
1892 result = operand1 & operand2;
1896 result = operand1 ^ operand2;
1900 result = operand1 - operand2;
1904 result = operand2 - operand1;
1908 result = operand1 + operand2;
1912 result = operand1 + operand2 + c;
1916 result = operand1 - operand2 + c;
1920 result = operand2 - operand1 + c;
1926 case 0xb: /* tst, teq, cmp, cmn */
1927 result = (unsigned long) nextpc;
1931 result = operand1 | operand2;
1935 /* Always step into a function. */
1940 result = operand1 & ~operand2;
1947 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1951 error (_("Infinite loop detected"));
1956 case 0x5: /* data transfer */
1959 if (bit (this_instr, 20))
1962 if (bits (this_instr, 12, 15) == 15)
1968 if (bit (this_instr, 22))
1969 error (_("Invalid update to pc in instruction"));
1971 /* byte write to PC */
1972 rn = bits (this_instr, 16, 19);
1973 base = (rn == 15) ? pc_val + 8
1974 : get_frame_register_unsigned (frame, rn);
1975 if (bit (this_instr, 24))
1978 int c = (status & FLAG_C) ? 1 : 0;
1979 unsigned long offset =
1980 (bit (this_instr, 25)
1981 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
1982 : bits (this_instr, 0, 11));
1984 if (bit (this_instr, 23))
1989 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1992 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1995 error (_("Infinite loop detected"));
2001 case 0x9: /* block transfer */
2002 if (bit (this_instr, 20))
2005 if (bit (this_instr, 15))
2010 if (bit (this_instr, 23))
2013 unsigned long reglist = bits (this_instr, 0, 14);
2014 offset = bitcount (reglist) * 4;
2015 if (bit (this_instr, 24)) /* pre */
2018 else if (bit (this_instr, 24))
2022 unsigned long rn_val =
2023 get_frame_register_unsigned (frame,
2024 bits (this_instr, 16, 19));
2026 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2030 nextpc = gdbarch_addr_bits_remove
2033 error (_("Infinite loop detected"));
2038 case 0xb: /* branch & link */
2039 case 0xa: /* branch */
2041 nextpc = BranchDest (pc, this_instr);
2043 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2045 error (_("Infinite loop detected"));
2051 case 0xe: /* coproc ops */
2056 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
2064 /* single_step() is called just before we want to resume the inferior,
2065 if we want to single-step it but there is no hardware or kernel
2066 single-step support. We find the target of the coming instruction
2067 and breakpoint it. */
2070 arm_software_single_step (struct frame_info *frame)
2072 /* NOTE: This may insert the wrong breakpoint instruction when
2073 single-stepping over a mode-changing instruction, if the
2074 CPSR heuristics are used. */
2076 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
2077 insert_single_step_breakpoint (next_pc);
2082 #include "bfd-in2.h"
2083 #include "libcoff.h"
2086 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2088 if (arm_pc_is_thumb (memaddr))
2090 static asymbol *asym;
2091 static combined_entry_type ce;
2092 static struct coff_symbol_struct csym;
2093 static struct bfd fake_bfd;
2094 static bfd_target fake_target;
2096 if (csym.native == NULL)
2098 /* Create a fake symbol vector containing a Thumb symbol.
2099 This is solely so that the code in print_insn_little_arm()
2100 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2101 the presence of a Thumb symbol and switch to decoding
2102 Thumb instructions. */
2104 fake_target.flavour = bfd_target_coff_flavour;
2105 fake_bfd.xvec = &fake_target;
2106 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2108 csym.symbol.the_bfd = &fake_bfd;
2109 csym.symbol.name = "fake";
2110 asym = (asymbol *) & csym;
2113 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2114 info->symbols = &asym;
2117 info->symbols = NULL;
2119 if (info->endian == BFD_ENDIAN_BIG)
2120 return print_insn_big_arm (memaddr, info);
2122 return print_insn_little_arm (memaddr, info);
2125 /* The following define instruction sequences that will cause ARM
2126 cpu's to take an undefined instruction trap. These are used to
2127 signal a breakpoint to GDB.
2129 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2130 modes. A different instruction is required for each mode. The ARM
2131 cpu's can also be big or little endian. Thus four different
2132 instructions are needed to support all cases.
2134 Note: ARMv4 defines several new instructions that will take the
2135 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2136 not in fact add the new instructions. The new undefined
2137 instructions in ARMv4 are all instructions that had no defined
2138 behaviour in earlier chips. There is no guarantee that they will
2139 raise an exception, but may be treated as NOP's. In practice, it
2140 may only safe to rely on instructions matching:
2142 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2143 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2144 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2146 Even this may only true if the condition predicate is true. The
2147 following use a condition predicate of ALWAYS so it is always TRUE.
2149 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2150 and NetBSD all use a software interrupt rather than an undefined
2151 instruction to force a trap. This can be handled by by the
2152 abi-specific code during establishment of the gdbarch vector. */
2154 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2155 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2156 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2157 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2159 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2160 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2161 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2162 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2164 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2165 the program counter value to determine whether a 16-bit or 32-bit
2166 breakpoint should be used. It returns a pointer to a string of
2167 bytes that encode a breakpoint instruction, stores the length of
2168 the string to *lenptr, and adjusts the program counter (if
2169 necessary) to point to the actual memory location where the
2170 breakpoint should be inserted. */
2172 static const unsigned char *
2173 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
2175 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2177 if (arm_pc_is_thumb (*pcptr))
2179 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2180 *lenptr = tdep->thumb_breakpoint_size;
2181 return tdep->thumb_breakpoint;
2185 *lenptr = tdep->arm_breakpoint_size;
2186 return tdep->arm_breakpoint;
2190 /* Extract from an array REGBUF containing the (raw) register state a
2191 function return value of type TYPE, and copy that, in virtual
2192 format, into VALBUF. */
2195 arm_extract_return_value (struct type *type, struct regcache *regs,
2198 struct gdbarch *gdbarch = get_regcache_arch (regs);
2200 if (TYPE_CODE_FLT == TYPE_CODE (type))
2202 switch (gdbarch_tdep (gdbarch)->fp_model)
2206 /* The value is in register F0 in internal format. We need to
2207 extract the raw value and then convert it to the desired
2209 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2211 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2212 convert_from_extended (floatformat_from_type (type), tmpbuf,
2213 valbuf, gdbarch_byte_order (gdbarch));
2217 case ARM_FLOAT_SOFT_FPA:
2218 case ARM_FLOAT_SOFT_VFP:
2219 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2220 if (TYPE_LENGTH (type) > 4)
2221 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2222 valbuf + INT_REGISTER_SIZE);
2227 (__FILE__, __LINE__,
2228 _("arm_extract_return_value: Floating point model not supported"));
2232 else if (TYPE_CODE (type) == TYPE_CODE_INT
2233 || TYPE_CODE (type) == TYPE_CODE_CHAR
2234 || TYPE_CODE (type) == TYPE_CODE_BOOL
2235 || TYPE_CODE (type) == TYPE_CODE_PTR
2236 || TYPE_CODE (type) == TYPE_CODE_REF
2237 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2239 /* If the the type is a plain integer, then the access is
2240 straight-forward. Otherwise we have to play around a bit more. */
2241 int len = TYPE_LENGTH (type);
2242 int regno = ARM_A1_REGNUM;
2247 /* By using store_unsigned_integer we avoid having to do
2248 anything special for small big-endian values. */
2249 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2250 store_unsigned_integer (valbuf,
2251 (len > INT_REGISTER_SIZE
2252 ? INT_REGISTER_SIZE : len),
2254 len -= INT_REGISTER_SIZE;
2255 valbuf += INT_REGISTER_SIZE;
2260 /* For a structure or union the behaviour is as if the value had
2261 been stored to word-aligned memory and then loaded into
2262 registers with 32-bit load instruction(s). */
2263 int len = TYPE_LENGTH (type);
2264 int regno = ARM_A1_REGNUM;
2265 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2269 regcache_cooked_read (regs, regno++, tmpbuf);
2270 memcpy (valbuf, tmpbuf,
2271 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2272 len -= INT_REGISTER_SIZE;
2273 valbuf += INT_REGISTER_SIZE;
2279 /* Will a function return an aggregate type in memory or in a
2280 register? Return 0 if an aggregate type can be returned in a
2281 register, 1 if it must be returned in memory. */
2284 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2287 enum type_code code;
2289 CHECK_TYPEDEF (type);
2291 /* In the ARM ABI, "integer" like aggregate types are returned in
2292 registers. For an aggregate type to be integer like, its size
2293 must be less than or equal to INT_REGISTER_SIZE and the
2294 offset of each addressable subfield must be zero. Note that bit
2295 fields are not addressable, and all addressable subfields of
2296 unions always start at offset zero.
2298 This function is based on the behaviour of GCC 2.95.1.
2299 See: gcc/arm.c: arm_return_in_memory() for details.
2301 Note: All versions of GCC before GCC 2.95.2 do not set up the
2302 parameters correctly for a function returning the following
2303 structure: struct { float f;}; This should be returned in memory,
2304 not a register. Richard Earnshaw sent me a patch, but I do not
2305 know of any way to detect if a function like the above has been
2306 compiled with the correct calling convention. */
2308 /* All aggregate types that won't fit in a register must be returned
2310 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2315 /* The AAPCS says all aggregates not larger than a word are returned
2317 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2320 /* The only aggregate types that can be returned in a register are
2321 structs and unions. Arrays must be returned in memory. */
2322 code = TYPE_CODE (type);
2323 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2328 /* Assume all other aggregate types can be returned in a register.
2329 Run a check for structures, unions and arrays. */
2332 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2335 /* Need to check if this struct/union is "integer" like. For
2336 this to be true, its size must be less than or equal to
2337 INT_REGISTER_SIZE and the offset of each addressable
2338 subfield must be zero. Note that bit fields are not
2339 addressable, and unions always start at offset zero. If any
2340 of the subfields is a floating point type, the struct/union
2341 cannot be an integer type. */
2343 /* For each field in the object, check:
2344 1) Is it FP? --> yes, nRc = 1;
2345 2) Is it addressable (bitpos != 0) and
2346 not packed (bitsize == 0)?
2350 for (i = 0; i < TYPE_NFIELDS (type); i++)
2352 enum type_code field_type_code;
2353 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2355 /* Is it a floating point type field? */
2356 if (field_type_code == TYPE_CODE_FLT)
2362 /* If bitpos != 0, then we have to care about it. */
2363 if (TYPE_FIELD_BITPOS (type, i) != 0)
2365 /* Bitfields are not addressable. If the field bitsize is
2366 zero, then the field is not packed. Hence it cannot be
2367 a bitfield or any other packed type. */
2368 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2380 /* Write into appropriate registers a function return value of type
2381 TYPE, given in virtual format. */
2384 arm_store_return_value (struct type *type, struct regcache *regs,
2385 const gdb_byte *valbuf)
2387 struct gdbarch *gdbarch = get_regcache_arch (regs);
2389 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2391 char buf[MAX_REGISTER_SIZE];
2393 switch (gdbarch_tdep (gdbarch)->fp_model)
2397 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2398 gdbarch_byte_order (gdbarch));
2399 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2402 case ARM_FLOAT_SOFT_FPA:
2403 case ARM_FLOAT_SOFT_VFP:
2404 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2405 if (TYPE_LENGTH (type) > 4)
2406 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2407 valbuf + INT_REGISTER_SIZE);
2412 (__FILE__, __LINE__,
2413 _("arm_store_return_value: Floating point model not supported"));
2417 else if (TYPE_CODE (type) == TYPE_CODE_INT
2418 || TYPE_CODE (type) == TYPE_CODE_CHAR
2419 || TYPE_CODE (type) == TYPE_CODE_BOOL
2420 || TYPE_CODE (type) == TYPE_CODE_PTR
2421 || TYPE_CODE (type) == TYPE_CODE_REF
2422 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2424 if (TYPE_LENGTH (type) <= 4)
2426 /* Values of one word or less are zero/sign-extended and
2428 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2429 LONGEST val = unpack_long (type, valbuf);
2431 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2432 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2436 /* Integral values greater than one word are stored in consecutive
2437 registers starting with r0. This will always be a multiple of
2438 the regiser size. */
2439 int len = TYPE_LENGTH (type);
2440 int regno = ARM_A1_REGNUM;
2444 regcache_cooked_write (regs, regno++, valbuf);
2445 len -= INT_REGISTER_SIZE;
2446 valbuf += INT_REGISTER_SIZE;
2452 /* For a structure or union the behaviour is as if the value had
2453 been stored to word-aligned memory and then loaded into
2454 registers with 32-bit load instruction(s). */
2455 int len = TYPE_LENGTH (type);
2456 int regno = ARM_A1_REGNUM;
2457 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2461 memcpy (tmpbuf, valbuf,
2462 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2463 regcache_cooked_write (regs, regno++, tmpbuf);
2464 len -= INT_REGISTER_SIZE;
2465 valbuf += INT_REGISTER_SIZE;
2471 /* Handle function return values. */
2473 static enum return_value_convention
2474 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2475 struct type *valtype, struct regcache *regcache,
2476 gdb_byte *readbuf, const gdb_byte *writebuf)
2478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2480 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2481 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2482 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2484 if (tdep->struct_return == pcc_struct_return
2485 || arm_return_in_memory (gdbarch, valtype))
2486 return RETURN_VALUE_STRUCT_CONVENTION;
2490 arm_store_return_value (valtype, regcache, writebuf);
2493 arm_extract_return_value (valtype, regcache, readbuf);
2495 return RETURN_VALUE_REGISTER_CONVENTION;
2500 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2503 char buf[INT_REGISTER_SIZE];
2504 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2506 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2508 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2512 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2516 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2517 return the target PC. Otherwise return 0. */
2520 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2524 CORE_ADDR start_addr;
2526 /* Find the starting address and name of the function containing the PC. */
2527 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2530 /* If PC is in a Thumb call or return stub, return the address of the
2531 target PC, which is in a register. The thunk functions are called
2532 _call_via_xx, where x is the register name. The possible names
2533 are r0-r9, sl, fp, ip, sp, and lr. */
2534 if (strncmp (name, "_call_via_", 10) == 0)
2536 /* Use the name suffix to determine which register contains the
2538 static char *table[15] =
2539 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2540 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2543 int offset = strlen (name) - 2;
2545 for (regno = 0; regno <= 14; regno++)
2546 if (strcmp (&name[offset], table[regno]) == 0)
2547 return get_frame_register_unsigned (frame, regno);
2550 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2551 non-interworking calls to foo. We could decode the stubs
2552 to find the target but it's easier to use the symbol table. */
2553 namelen = strlen (name);
2554 if (name[0] == '_' && name[1] == '_'
2555 && ((namelen > 2 + strlen ("_from_thumb")
2556 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2557 strlen ("_from_thumb")) == 0)
2558 || (namelen > 2 + strlen ("_from_arm")
2559 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2560 strlen ("_from_arm")) == 0)))
2563 int target_len = namelen - 2;
2564 struct minimal_symbol *minsym;
2565 struct objfile *objfile;
2566 struct obj_section *sec;
2568 if (name[namelen - 1] == 'b')
2569 target_len -= strlen ("_from_thumb");
2571 target_len -= strlen ("_from_arm");
2573 target_name = alloca (target_len + 1);
2574 memcpy (target_name, name + 2, target_len);
2575 target_name[target_len] = '\0';
2577 sec = find_pc_section (pc);
2578 objfile = (sec == NULL) ? NULL : sec->objfile;
2579 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2581 return SYMBOL_VALUE_ADDRESS (minsym);
2586 return 0; /* not a stub */
2590 set_arm_command (char *args, int from_tty)
2592 printf_unfiltered (_("\
2593 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2594 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2598 show_arm_command (char *args, int from_tty)
2600 cmd_show_list (showarmcmdlist, from_tty, "");
2604 arm_update_current_architecture (void)
2606 struct gdbarch_info info;
2608 /* If the current architecture is not ARM, we have nothing to do. */
2609 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2612 /* Update the architecture. */
2613 gdbarch_info_init (&info);
2615 if (!gdbarch_update_p (info))
2616 internal_error (__FILE__, __LINE__, "could not update architecture");
2620 set_fp_model_sfunc (char *args, int from_tty,
2621 struct cmd_list_element *c)
2623 enum arm_float_model fp_model;
2625 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2626 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2628 arm_fp_model = fp_model;
2632 if (fp_model == ARM_FLOAT_LAST)
2633 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2636 arm_update_current_architecture ();
2640 show_fp_model (struct ui_file *file, int from_tty,
2641 struct cmd_list_element *c, const char *value)
2643 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2645 if (arm_fp_model == ARM_FLOAT_AUTO
2646 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2647 fprintf_filtered (file, _("\
2648 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2649 fp_model_strings[tdep->fp_model]);
2651 fprintf_filtered (file, _("\
2652 The current ARM floating point model is \"%s\".\n"),
2653 fp_model_strings[arm_fp_model]);
2657 arm_set_abi (char *args, int from_tty,
2658 struct cmd_list_element *c)
2660 enum arm_abi_kind arm_abi;
2662 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2663 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2665 arm_abi_global = arm_abi;
2669 if (arm_abi == ARM_ABI_LAST)
2670 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2673 arm_update_current_architecture ();
2677 arm_show_abi (struct ui_file *file, int from_tty,
2678 struct cmd_list_element *c, const char *value)
2680 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2682 if (arm_abi_global == ARM_ABI_AUTO
2683 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2684 fprintf_filtered (file, _("\
2685 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2686 arm_abi_strings[tdep->arm_abi]);
2688 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2693 arm_show_fallback_mode (struct ui_file *file, int from_tty,
2694 struct cmd_list_element *c, const char *value)
2696 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2698 fprintf_filtered (file, _("\
2699 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2700 arm_fallback_mode_string);
2704 arm_show_force_mode (struct ui_file *file, int from_tty,
2705 struct cmd_list_element *c, const char *value)
2707 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2709 fprintf_filtered (file, _("\
2710 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2711 arm_force_mode_string);
2714 /* If the user changes the register disassembly style used for info
2715 register and other commands, we have to also switch the style used
2716 in opcodes for disassembly output. This function is run in the "set
2717 arm disassembly" command, and does that. */
2720 set_disassembly_style_sfunc (char *args, int from_tty,
2721 struct cmd_list_element *c)
2723 set_disassembly_style ();
2726 /* Return the ARM register name corresponding to register I. */
2728 arm_register_name (struct gdbarch *gdbarch, int i)
2730 if (i >= ARRAY_SIZE (arm_register_names))
2731 /* These registers are only supported on targets which supply
2732 an XML description. */
2735 return arm_register_names[i];
2739 set_disassembly_style (void)
2743 /* Find the style that the user wants. */
2744 for (current = 0; current < num_disassembly_options; current++)
2745 if (disassembly_style == valid_disassembly_styles[current])
2747 gdb_assert (current < num_disassembly_options);
2749 /* Synchronize the disassembler. */
2750 set_arm_regname_option (current);
2753 /* Test whether the coff symbol specific value corresponds to a Thumb
2757 coff_sym_is_thumb (int val)
2759 return (val == C_THUMBEXT ||
2760 val == C_THUMBSTAT ||
2761 val == C_THUMBEXTFUNC ||
2762 val == C_THUMBSTATFUNC ||
2763 val == C_THUMBLABEL);
2766 /* arm_coff_make_msymbol_special()
2767 arm_elf_make_msymbol_special()
2769 These functions test whether the COFF or ELF symbol corresponds to
2770 an address in thumb code, and set a "special" bit in a minimal
2771 symbol to indicate that it does. */
2774 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2776 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2778 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2780 MSYMBOL_SET_SPECIAL (msym);
2784 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2786 if (coff_sym_is_thumb (val))
2787 MSYMBOL_SET_SPECIAL (msym);
2791 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2793 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2795 /* If necessary, set the T bit. */
2799 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2800 if (arm_pc_is_thumb (pc))
2801 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
2803 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2804 val & ~(ULONGEST) CPSR_T);
2808 static struct value *
2809 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2811 const int *reg_p = baton;
2812 return value_of_register (*reg_p, frame);
2815 static enum gdb_osabi
2816 arm_elf_osabi_sniffer (bfd *abfd)
2818 unsigned int elfosabi;
2819 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2821 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2823 if (elfosabi == ELFOSABI_ARM)
2824 /* GNU tools use this value. Check note sections in this case,
2826 bfd_map_over_sections (abfd,
2827 generic_elf_osabi_sniff_abi_tag_sections,
2830 /* Anything else will be handled by the generic ELF sniffer. */
2835 /* Initialize the current architecture based on INFO. If possible,
2836 re-use an architecture from ARCHES, which is a list of
2837 architectures already created during this debugging session.
2839 Called e.g. at program startup, when reading a core file, and when
2840 reading a binary file. */
2842 static struct gdbarch *
2843 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2845 struct gdbarch_tdep *tdep;
2846 struct gdbarch *gdbarch;
2847 struct gdbarch_list *best_arch;
2848 enum arm_abi_kind arm_abi = arm_abi_global;
2849 enum arm_float_model fp_model = arm_fp_model;
2850 struct tdesc_arch_data *tdesc_data = NULL;
2852 int have_fpa_registers = 1;
2854 /* Check any target description for validity. */
2855 if (tdesc_has_registers (info.target_desc))
2857 /* For most registers we require GDB's default names; but also allow
2858 the numeric names for sp / lr / pc, as a convenience. */
2859 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2860 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2861 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2863 const struct tdesc_feature *feature;
2866 feature = tdesc_find_feature (info.target_desc,
2867 "org.gnu.gdb.arm.core");
2868 if (feature == NULL)
2871 tdesc_data = tdesc_data_alloc ();
2874 for (i = 0; i < ARM_SP_REGNUM; i++)
2875 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2876 arm_register_names[i]);
2877 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2880 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2883 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2886 valid_p &= tdesc_numbered_register (feature, tdesc_data,
2887 ARM_PS_REGNUM, "cpsr");
2891 tdesc_data_cleanup (tdesc_data);
2895 feature = tdesc_find_feature (info.target_desc,
2896 "org.gnu.gdb.arm.fpa");
2897 if (feature != NULL)
2900 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
2901 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2902 arm_register_names[i]);
2905 tdesc_data_cleanup (tdesc_data);
2910 have_fpa_registers = 0;
2912 feature = tdesc_find_feature (info.target_desc,
2913 "org.gnu.gdb.xscale.iwmmxt");
2914 if (feature != NULL)
2916 static const char *const iwmmxt_names[] = {
2917 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2918 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2919 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2920 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2924 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
2926 &= tdesc_numbered_register (feature, tdesc_data, i,
2927 iwmmxt_names[i - ARM_WR0_REGNUM]);
2929 /* Check for the control registers, but do not fail if they
2931 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
2932 tdesc_numbered_register (feature, tdesc_data, i,
2933 iwmmxt_names[i - ARM_WR0_REGNUM]);
2935 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
2937 &= tdesc_numbered_register (feature, tdesc_data, i,
2938 iwmmxt_names[i - ARM_WR0_REGNUM]);
2942 tdesc_data_cleanup (tdesc_data);
2948 /* If we have an object to base this architecture on, try to determine
2951 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2953 int ei_osabi, e_flags;
2955 switch (bfd_get_flavour (info.abfd))
2957 case bfd_target_aout_flavour:
2958 /* Assume it's an old APCS-style ABI. */
2959 arm_abi = ARM_ABI_APCS;
2962 case bfd_target_coff_flavour:
2963 /* Assume it's an old APCS-style ABI. */
2965 arm_abi = ARM_ABI_APCS;
2968 case bfd_target_elf_flavour:
2969 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2970 e_flags = elf_elfheader (info.abfd)->e_flags;
2972 if (ei_osabi == ELFOSABI_ARM)
2974 /* GNU tools used to use this value, but do not for EABI
2975 objects. There's nowhere to tag an EABI version
2976 anyway, so assume APCS. */
2977 arm_abi = ARM_ABI_APCS;
2979 else if (ei_osabi == ELFOSABI_NONE)
2981 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2985 case EF_ARM_EABI_UNKNOWN:
2986 /* Assume GNU tools. */
2987 arm_abi = ARM_ABI_APCS;
2990 case EF_ARM_EABI_VER4:
2991 case EF_ARM_EABI_VER5:
2992 arm_abi = ARM_ABI_AAPCS;
2993 /* EABI binaries default to VFP float ordering. */
2994 if (fp_model == ARM_FLOAT_AUTO)
2995 fp_model = ARM_FLOAT_SOFT_VFP;
2999 /* Leave it as "auto". */
3000 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
3005 if (fp_model == ARM_FLOAT_AUTO)
3007 int e_flags = elf_elfheader (info.abfd)->e_flags;
3009 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
3012 /* Leave it as "auto". Strictly speaking this case
3013 means FPA, but almost nobody uses that now, and
3014 many toolchains fail to set the appropriate bits
3015 for the floating-point model they use. */
3017 case EF_ARM_SOFT_FLOAT:
3018 fp_model = ARM_FLOAT_SOFT_FPA;
3020 case EF_ARM_VFP_FLOAT:
3021 fp_model = ARM_FLOAT_VFP;
3023 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
3024 fp_model = ARM_FLOAT_SOFT_VFP;
3031 /* Leave it as "auto". */
3036 /* If there is already a candidate, use it. */
3037 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3039 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3041 if (arm_abi != ARM_ABI_AUTO
3042 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
3045 if (fp_model != ARM_FLOAT_AUTO
3046 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
3049 /* Found a match. */
3053 if (best_arch != NULL)
3055 if (tdesc_data != NULL)
3056 tdesc_data_cleanup (tdesc_data);
3057 return best_arch->gdbarch;
3060 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
3061 gdbarch = gdbarch_alloc (&info, tdep);
3063 /* Record additional information about the architecture we are defining.
3064 These are gdbarch discriminators, like the OSABI. */
3065 tdep->arm_abi = arm_abi;
3066 tdep->fp_model = fp_model;
3067 tdep->have_fpa_registers = have_fpa_registers;
3070 switch (info.byte_order)
3072 case BFD_ENDIAN_BIG:
3073 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3074 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3075 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3076 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3080 case BFD_ENDIAN_LITTLE:
3081 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3082 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3083 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3084 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3089 internal_error (__FILE__, __LINE__,
3090 _("arm_gdbarch_init: bad byte order for float format"));
3093 /* On ARM targets char defaults to unsigned. */
3094 set_gdbarch_char_signed (gdbarch, 0);
3096 /* This should be low enough for everything. */
3097 tdep->lowest_pc = 0x20;
3098 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3100 /* The default, for both APCS and AAPCS, is to return small
3101 structures in registers. */
3102 tdep->struct_return = reg_struct_return;
3104 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
3105 set_gdbarch_frame_align (gdbarch, arm_frame_align);
3107 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3109 /* Frame handling. */
3110 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
3111 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3112 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3114 frame_base_set_default (gdbarch, &arm_normal_base);
3116 /* Address manipulation. */
3117 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3118 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3120 /* Advance PC across function entry code. */
3121 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3123 /* Skip trampolines. */
3124 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3126 /* The stack grows downward. */
3127 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3129 /* Breakpoint manipulation. */
3130 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3132 /* Information about registers, etc. */
3133 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3134 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3135 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3136 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3137 set_gdbarch_register_type (gdbarch, arm_register_type);
3139 /* This "info float" is FPA-specific. Use the generic version if we
3141 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3142 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3144 /* Internal <-> external register number maps. */
3145 set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3146 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3147 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3149 set_gdbarch_register_name (gdbarch, arm_register_name);
3151 /* Returning results. */
3152 set_gdbarch_return_value (gdbarch, arm_return_value);
3155 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3157 /* Minsymbol frobbing. */
3158 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3159 set_gdbarch_coff_make_msymbol_special (gdbarch,
3160 arm_coff_make_msymbol_special);
3162 /* Virtual tables. */
3163 set_gdbarch_vbit_in_delta (gdbarch, 1);
3165 /* Hook in the ABI-specific overrides, if they have been registered. */
3166 gdbarch_init_osabi (info, gdbarch);
3168 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3170 /* Add some default predicates. */
3171 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3172 dwarf2_append_unwinders (gdbarch);
3173 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
3175 /* Now we have tuned the configuration, set a few final things,
3176 based on what the OS ABI has told us. */
3178 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3179 binaries are always marked. */
3180 if (tdep->arm_abi == ARM_ABI_AUTO)
3181 tdep->arm_abi = ARM_ABI_APCS;
3183 /* We used to default to FPA for generic ARM, but almost nobody
3184 uses that now, and we now provide a way for the user to force
3185 the model. So default to the most useful variant. */
3186 if (tdep->fp_model == ARM_FLOAT_AUTO)
3187 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3189 if (tdep->jb_pc >= 0)
3190 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3192 /* Floating point sizes and format. */
3193 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3194 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3196 set_gdbarch_double_format
3197 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3198 set_gdbarch_long_double_format
3199 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3203 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3204 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3208 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3210 /* Add standard register aliases. We add aliases even for those
3211 nanes which are used by the current architecture - it's simpler,
3212 and does no harm, since nothing ever lists user registers. */
3213 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3214 user_reg_add (gdbarch, arm_register_aliases[i].name,
3215 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3221 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3228 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3229 (unsigned long) tdep->lowest_pc);
3232 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3235 _initialize_arm_tdep (void)
3237 struct ui_file *stb;
3239 struct cmd_list_element *new_set, *new_show;
3240 const char *setname;
3241 const char *setdesc;
3242 const char *const *regnames;
3244 static char *helptext;
3245 char regdesc[1024], *rdptr = regdesc;
3246 size_t rest = sizeof (regdesc);
3248 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3250 /* Register an ELF OS ABI sniffer for ARM binaries. */
3251 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3252 bfd_target_elf_flavour,
3253 arm_elf_osabi_sniffer);
3255 /* Get the number of possible sets of register names defined in opcodes. */
3256 num_disassembly_options = get_arm_regname_num_options ();
3258 /* Add root prefix command for all "set arm"/"show arm" commands. */
3259 add_prefix_cmd ("arm", no_class, set_arm_command,
3260 _("Various ARM-specific commands."),
3261 &setarmcmdlist, "set arm ", 0, &setlist);
3263 add_prefix_cmd ("arm", no_class, show_arm_command,
3264 _("Various ARM-specific commands."),
3265 &showarmcmdlist, "show arm ", 0, &showlist);
3267 /* Sync the opcode insn printer with our register viewer. */
3268 parse_arm_disassembler_option ("reg-names-std");
3270 /* Initialize the array that will be passed to
3271 add_setshow_enum_cmd(). */
3272 valid_disassembly_styles
3273 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3274 for (i = 0; i < num_disassembly_options; i++)
3276 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3277 valid_disassembly_styles[i] = setname;
3278 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3281 /* When we find the default names, tell the disassembler to use
3283 if (!strcmp (setname, "std"))
3285 disassembly_style = setname;
3286 set_arm_regname_option (i);
3289 /* Mark the end of valid options. */
3290 valid_disassembly_styles[num_disassembly_options] = NULL;
3292 /* Create the help text. */
3293 stb = mem_fileopen ();
3294 fprintf_unfiltered (stb, "%s%s%s",
3295 _("The valid values are:\n"),
3297 _("The default is \"std\"."));
3298 helptext = ui_file_xstrdup (stb, &length);
3299 ui_file_delete (stb);
3301 add_setshow_enum_cmd("disassembler", no_class,
3302 valid_disassembly_styles, &disassembly_style,
3303 _("Set the disassembly style."),
3304 _("Show the disassembly style."),
3306 set_disassembly_style_sfunc,
3307 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3308 &setarmcmdlist, &showarmcmdlist);
3310 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3311 _("Set usage of ARM 32-bit mode."),
3312 _("Show usage of ARM 32-bit mode."),
3313 _("When off, a 26-bit PC will be used."),
3315 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3316 &setarmcmdlist, &showarmcmdlist);
3318 /* Add a command to allow the user to force the FPU model. */
3319 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3320 _("Set the floating point type."),
3321 _("Show the floating point type."),
3322 _("auto - Determine the FP typefrom the OS-ABI.\n\
3323 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3324 fpa - FPA co-processor (GCC compiled).\n\
3325 softvfp - Software FP with pure-endian doubles.\n\
3326 vfp - VFP co-processor."),
3327 set_fp_model_sfunc, show_fp_model,
3328 &setarmcmdlist, &showarmcmdlist);
3330 /* Add a command to allow the user to force the ABI. */
3331 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3334 NULL, arm_set_abi, arm_show_abi,
3335 &setarmcmdlist, &showarmcmdlist);
3337 /* Add two commands to allow the user to force the assumed
3339 add_setshow_enum_cmd ("fallback-mode", class_support,
3340 arm_mode_strings, &arm_fallback_mode_string,
3341 _("Set the mode assumed when symbols are unavailable."),
3342 _("Show the mode assumed when symbols are unavailable."),
3343 NULL, NULL, arm_show_fallback_mode,
3344 &setarmcmdlist, &showarmcmdlist);
3345 add_setshow_enum_cmd ("force-mode", class_support,
3346 arm_mode_strings, &arm_force_mode_string,
3347 _("Set the mode assumed even when symbols are available."),
3348 _("Show the mode assumed even when symbols are available."),
3349 NULL, NULL, arm_show_force_mode,
3350 &setarmcmdlist, &showarmcmdlist);
3352 /* Debugging flag. */
3353 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3354 _("Set ARM debugging."),
3355 _("Show ARM debugging."),
3356 _("When on, arm-specific debugging is enabled."),
3358 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3359 &setdebuglist, &showdebuglist);