1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
24 #include <ctype.h> /* XXX for isupper () */
31 #include "gdb_string.h"
32 #include "dis-asm.h" /* For register styles. */
36 #include "arch-utils.h"
38 #include "frame-unwind.h"
39 #include "frame-base.h"
40 #include "trad-frame.h"
42 #include "dwarf2-frame.h"
45 #include "gdb/sim-arm.h"
48 #include "coff/internal.h"
51 #include "gdb_assert.h"
55 /* Macros for setting and testing a bit in a minimal symbol that marks
56 it as Thumb function. The MSB of the minimal symbol's "info" field
57 is used for this purpose.
59 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
60 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
62 #define MSYMBOL_SET_SPECIAL(msym) \
63 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
66 #define MSYMBOL_IS_SPECIAL(msym) \
67 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
69 /* The list of available "set arm ..." and "show arm ..." commands. */
70 static struct cmd_list_element *setarmcmdlist = NULL;
71 static struct cmd_list_element *showarmcmdlist = NULL;
73 /* The type of floating-point to use. Keep this in sync with enum
74 arm_float_model, and the help string in _initialize_arm_tdep. */
75 static const char *fp_model_strings[] =
85 /* A variable that can be configured by the user. */
86 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
87 static const char *current_fp_model = "auto";
89 /* The ABI to use. Keep this in sync with arm_abi_kind. */
90 static const char *arm_abi_strings[] =
98 /* A variable that can be configured by the user. */
99 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
100 static const char *arm_abi_string = "auto";
102 /* Number of different reg name sets (options). */
103 static int num_disassembly_options;
105 /* We have more registers than the disassembler as gdb can print the value
106 of special registers as well.
107 The general register names are overwritten by whatever is being used by
108 the disassembler at the moment. We also adjust the case of cpsr and fps. */
110 /* Initial value: Register names used in ARM's ISA documentation. */
111 static char * arm_register_name_strings[] =
112 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
113 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
114 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
115 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
116 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
117 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
118 "fps", "cpsr" }; /* 24 25 */
119 static char **arm_register_names = arm_register_name_strings;
121 /* Valid register name styles. */
122 static const char **valid_disassembly_styles;
124 /* Disassembly style to use. Default to "std" register names. */
125 static const char *disassembly_style;
126 /* Index to that option in the opcodes table. */
127 static int current_option;
129 /* This is used to keep the bfd arch_info in sync with the disassembly
131 static void set_disassembly_style_sfunc(char *, int,
132 struct cmd_list_element *);
133 static void set_disassembly_style (void);
135 static void convert_from_extended (const struct floatformat *, const void *,
137 static void convert_to_extended (const struct floatformat *, void *,
140 struct arm_prologue_cache
142 /* The stack pointer at the time this frame was created; i.e. the
143 caller's stack pointer when this function was called. It is used
144 to identify this frame. */
147 /* The frame base for this frame is just prev_sp + frame offset -
148 frame size. FRAMESIZE is the size of this stack frame, and
149 FRAMEOFFSET if the initial offset from the stack pointer (this
150 frame's stack pointer, not PREV_SP) to the frame base. */
155 /* The register used to hold the frame pointer for this frame. */
158 /* Saved register offsets. */
159 struct trad_frame_saved_reg *saved_regs;
162 /* Addresses for calling Thumb functions have the bit 0 set.
163 Here are some macros to test, set, or clear bit 0 of addresses. */
164 #define IS_THUMB_ADDR(addr) ((addr) & 1)
165 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
166 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
168 /* Set to true if the 32-bit mode is in use. */
172 /* Determine if the program counter specified in MEMADDR is in a Thumb
176 arm_pc_is_thumb (CORE_ADDR memaddr)
178 struct minimal_symbol *sym;
180 /* If bit 0 of the address is set, assume this is a Thumb address. */
181 if (IS_THUMB_ADDR (memaddr))
184 /* Thumb functions have a "special" bit set in minimal symbols. */
185 sym = lookup_minimal_symbol_by_pc (memaddr);
188 return (MSYMBOL_IS_SPECIAL (sym));
196 /* Remove useless bits from addresses in a running program. */
198 arm_addr_bits_remove (CORE_ADDR val)
201 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
203 return (val & 0x03fffffc);
206 /* When reading symbols, we need to zap the low bit of the address,
207 which may be set to 1 for Thumb functions. */
209 arm_smash_text_address (CORE_ADDR val)
214 /* Immediately after a function call, return the saved pc. Can't
215 always go through the frames for this because on some machines the
216 new frame is not set up until the new function executes some
220 arm_saved_pc_after_call (struct frame_info *frame)
222 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
225 /* A typical Thumb prologue looks like this:
229 Sometimes the latter instruction may be replaced by:
237 or, on tpcs, like this:
244 There is always one instruction of three classes:
249 When we have found at least one of each class we are done with the prolog.
250 Note that the "sub sp, #NN" before the push does not count.
254 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
256 CORE_ADDR current_pc;
258 bit 0 - push { rlist }
259 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
260 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
264 for (current_pc = pc;
265 current_pc + 2 < func_end && current_pc < pc + 40;
268 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
270 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
272 findmask |= 1; /* push found */
274 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
277 if ((findmask & 1) == 0) /* before push ? */
280 findmask |= 4; /* add/sub sp found */
282 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
284 findmask |= 2; /* setting of r7 found */
286 else if (insn == 0x466f) /* mov r7, sp */
288 findmask |= 2; /* setting of r7 found */
290 else if (findmask == (4+2+1))
292 /* We have found one of each type of prologue instruction */
296 /* Something in the prolog that we don't care about or some
297 instruction from outside the prolog scheduled here for
305 /* Advance the PC across any function entry prologue instructions to
306 reach some "real" code.
308 The APCS (ARM Procedure Call Standard) defines the following
312 [stmfd sp!, {a1,a2,a3,a4}]
313 stmfd sp!, {...,fp,ip,lr,pc}
314 [stfe f7, [sp, #-12]!]
315 [stfe f6, [sp, #-12]!]
316 [stfe f5, [sp, #-12]!]
317 [stfe f4, [sp, #-12]!]
318 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
321 arm_skip_prologue (CORE_ADDR pc)
325 CORE_ADDR func_addr, func_end = 0;
327 struct symtab_and_line sal;
329 /* If we're in a dummy frame, don't even try to skip the prologue. */
330 if (deprecated_pc_in_call_dummy (pc))
333 /* See what the symbol table says. */
335 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
339 /* Found a function. */
340 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
341 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
343 /* Don't use this trick for assembly source files. */
344 sal = find_pc_line (func_addr, 0);
345 if ((sal.line != 0) && (sal.end < func_end))
350 /* Check if this is Thumb code. */
351 if (arm_pc_is_thumb (pc))
352 return thumb_skip_prologue (pc, func_end);
354 /* Can't find the prologue end in the symbol table, try it the hard way
355 by disassembling the instructions. */
357 /* Like arm_scan_prologue, stop no later than pc + 64. */
358 if (func_end == 0 || func_end > pc + 64)
361 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
363 inst = read_memory_unsigned_integer (skip_pc, 4);
365 /* "mov ip, sp" is no longer a required part of the prologue. */
366 if (inst == 0xe1a0c00d) /* mov ip, sp */
369 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
372 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
375 /* Some prologues begin with "str lr, [sp, #-4]!". */
376 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
379 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
382 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
385 /* Any insns after this point may float into the code, if it makes
386 for better instruction scheduling, so we skip them only if we
387 find them, but still consider the function to be frame-ful. */
389 /* We may have either one sfmfd instruction here, or several stfe
390 insns, depending on the version of floating point code we
392 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
395 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
398 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
401 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
404 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
405 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
406 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
409 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
410 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
411 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
414 /* Un-recognized instruction; stop scanning. */
418 return skip_pc; /* End of prologue */
422 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
423 This function decodes a Thumb function prologue to determine:
424 1) the size of the stack frame
425 2) which registers are saved on it
426 3) the offsets of saved regs
427 4) the offset from the stack pointer to the frame pointer
429 A typical Thumb function prologue would create this stack frame
430 (offsets relative to FP)
431 old SP -> 24 stack parameters
434 R7 -> 0 local variables (16 bytes)
435 SP -> -12 additional stack space (12 bytes)
436 The frame size would thus be 36 bytes, and the frame offset would be
437 12 bytes. The frame register is R7.
439 The comments for thumb_skip_prolog() describe the algorithm we use
440 to detect the end of the prolog. */
444 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
446 CORE_ADDR prologue_start;
447 CORE_ADDR prologue_end;
448 CORE_ADDR current_pc;
449 /* Which register has been copied to register n? */
452 bit 0 - push { rlist }
453 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
454 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
459 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
461 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
463 if (sal.line == 0) /* no line info, use current PC */
464 prologue_end = prev_pc;
465 else if (sal.end < prologue_end) /* next line begins after fn end */
466 prologue_end = sal.end; /* (probably means no prologue) */
469 /* We're in the boondocks: allow for
470 16 pushes, an add, and "mv fp,sp". */
471 prologue_end = prologue_start + 40;
473 prologue_end = min (prologue_end, prev_pc);
475 /* Initialize the saved register map. When register H is copied to
476 register L, we will put H in saved_reg[L]. */
477 for (i = 0; i < 16; i++)
480 /* Search the prologue looking for instructions that set up the
481 frame pointer, adjust the stack pointer, and save registers.
482 Do this until all basic prolog instructions are found. */
484 cache->framesize = 0;
485 for (current_pc = prologue_start;
486 (current_pc < prologue_end) && ((findmask & 7) != 7);
493 insn = read_memory_unsigned_integer (current_pc, 2);
495 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
498 findmask |= 1; /* push found */
499 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
500 whether to save LR (R14). */
501 mask = (insn & 0xff) | ((insn & 0x100) << 6);
503 /* Calculate offsets of saved R0-R7 and LR. */
504 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
505 if (mask & (1 << regno))
507 cache->framesize += 4;
508 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
509 /* Reset saved register map. */
510 saved_reg[regno] = regno;
513 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
516 if ((findmask & 1) == 0) /* before push? */
519 findmask |= 4; /* add/sub sp found */
521 offset = (insn & 0x7f) << 2; /* get scaled offset */
522 if (insn & 0x80) /* is it signed? (==subtracting) */
524 cache->frameoffset += offset;
527 cache->framesize -= offset;
529 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
531 findmask |= 2; /* setting of r7 found */
532 cache->framereg = THUMB_FP_REGNUM;
533 /* get scaled offset */
534 cache->frameoffset = (insn & 0xff) << 2;
536 else if (insn == 0x466f) /* mov r7, sp */
538 findmask |= 2; /* setting of r7 found */
539 cache->framereg = THUMB_FP_REGNUM;
540 cache->frameoffset = 0;
541 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
543 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
545 int lo_reg = insn & 7; /* dest. register (r0-r7) */
546 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
547 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
550 /* Something in the prolog that we don't care about or some
551 instruction from outside the prolog scheduled here for
557 /* This function decodes an ARM function prologue to determine:
558 1) the size of the stack frame
559 2) which registers are saved on it
560 3) the offsets of saved regs
561 4) the offset from the stack pointer to the frame pointer
562 This information is stored in the "extra" fields of the frame_info.
564 There are two basic forms for the ARM prologue. The fixed argument
565 function call will look like:
568 stmfd sp!, {fp, ip, lr, pc}
572 Which would create this stack frame (offsets relative to FP):
573 IP -> 4 (caller's stack)
574 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
575 -4 LR (return address in caller)
576 -8 IP (copy of caller's SP)
578 SP -> -28 Local variables
580 The frame size would thus be 32 bytes, and the frame offset would be
581 28 bytes. The stmfd call can also save any of the vN registers it
582 plans to use, which increases the frame size accordingly.
584 Note: The stored PC is 8 off of the STMFD instruction that stored it
585 because the ARM Store instructions always store PC + 8 when you read
588 A variable argument function call will look like:
591 stmfd sp!, {a1, a2, a3, a4}
592 stmfd sp!, {fp, ip, lr, pc}
595 Which would create this stack frame (offsets relative to FP):
596 IP -> 20 (caller's stack)
601 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
602 -4 LR (return address in caller)
603 -8 IP (copy of caller's SP)
605 SP -> -28 Local variables
607 The frame size would thus be 48 bytes, and the frame offset would be
610 There is another potential complication, which is that the optimizer
611 will try to separate the store of fp in the "stmfd" instruction from
612 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
613 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
615 Also, note, the original version of the ARM toolchain claimed that there
618 instruction at the end of the prologue. I have never seen GCC produce
619 this, and the ARM docs don't mention it. We still test for it below in
625 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
627 int regno, sp_offset, fp_offset, ip_offset;
628 CORE_ADDR prologue_start, prologue_end, current_pc;
629 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
631 /* Assume there is no frame until proven otherwise. */
632 cache->framereg = ARM_SP_REGNUM;
633 cache->framesize = 0;
634 cache->frameoffset = 0;
636 /* Check for Thumb prologue. */
637 if (arm_pc_is_thumb (prev_pc))
639 thumb_scan_prologue (prev_pc, cache);
643 /* Find the function prologue. If we can't find the function in
644 the symbol table, peek in the stack frame to find the PC. */
645 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
647 /* One way to find the end of the prologue (which works well
648 for unoptimized code) is to do the following:
650 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
653 prologue_end = prev_pc;
654 else if (sal.end < prologue_end)
655 prologue_end = sal.end;
657 This mechanism is very accurate so long as the optimizer
658 doesn't move any instructions from the function body into the
659 prologue. If this happens, sal.end will be the last
660 instruction in the first hunk of prologue code just before
661 the first instruction that the scheduler has moved from
662 the body to the prologue.
664 In order to make sure that we scan all of the prologue
665 instructions, we use a slightly less accurate mechanism which
666 may scan more than necessary. To help compensate for this
667 lack of accuracy, the prologue scanning loop below contains
668 several clauses which'll cause the loop to terminate early if
669 an implausible prologue instruction is encountered.
675 is a suitable endpoint since it accounts for the largest
676 possible prologue plus up to five instructions inserted by
679 if (prologue_end > prologue_start + 64)
681 prologue_end = prologue_start + 64; /* See above. */
686 /* We have no symbol information. Our only option is to assume this
687 function has a standard stack frame and the normal frame register.
688 Then, we can find the value of our frame pointer on entrance to
689 the callee (or at the present moment if this is the innermost frame).
690 The value stored there should be the address of the stmfd + 8. */
692 LONGEST return_value;
694 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
695 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
699 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
700 prologue_end = prologue_start + 64; /* See above. */
704 if (prev_pc < prologue_end)
705 prologue_end = prev_pc;
707 /* Now search the prologue looking for instructions that set up the
708 frame pointer, adjust the stack pointer, and save registers.
710 Be careful, however, and if it doesn't look like a prologue,
711 don't try to scan it. If, for instance, a frameless function
712 begins with stmfd sp!, then we will tell ourselves there is
713 a frame, which will confuse stack traceback, as well as "finish"
714 and other operations that rely on a knowledge of the stack
717 In the APCS, the prologue should start with "mov ip, sp" so
718 if we don't see this as the first insn, we will stop.
720 [Note: This doesn't seem to be true any longer, so it's now an
721 optional part of the prologue. - Kevin Buettner, 2001-11-20]
723 [Note further: The "mov ip,sp" only seems to be missing in
724 frameless functions at optimization level "-O2" or above,
725 in which case it is often (but not always) replaced by
726 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
728 sp_offset = fp_offset = ip_offset = 0;
730 for (current_pc = prologue_start;
731 current_pc < prologue_end;
734 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
736 if (insn == 0xe1a0c00d) /* mov ip, sp */
741 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
743 unsigned imm = insn & 0xff; /* immediate value */
744 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
745 imm = (imm >> rot) | (imm << (32 - rot));
749 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
751 unsigned imm = insn & 0xff; /* immediate value */
752 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
753 imm = (imm >> rot) | (imm << (32 - rot));
757 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
760 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
763 else if ((insn & 0xffff0000) == 0xe92d0000)
764 /* stmfd sp!, {..., fp, ip, lr, pc}
766 stmfd sp!, {a1, a2, a3, a4} */
768 int mask = insn & 0xffff;
770 /* Calculate offsets of saved registers. */
771 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
772 if (mask & (1 << regno))
775 cache->saved_regs[regno].addr = sp_offset;
778 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
779 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
780 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
782 /* No need to add this to saved_regs -- it's just an arg reg. */
785 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
786 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
787 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
789 /* No need to add this to saved_regs -- it's just an arg reg. */
792 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
794 unsigned imm = insn & 0xff; /* immediate value */
795 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
796 imm = (imm >> rot) | (imm << (32 - rot));
797 fp_offset = -imm + ip_offset;
798 cache->framereg = ARM_FP_REGNUM;
800 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
802 unsigned imm = insn & 0xff; /* immediate value */
803 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
804 imm = (imm >> rot) | (imm << (32 - rot));
807 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
810 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
811 cache->saved_regs[regno].addr = sp_offset;
813 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
816 unsigned int fp_start_reg, fp_bound_reg;
818 if ((insn & 0x800) == 0x800) /* N0 is set */
820 if ((insn & 0x40000) == 0x40000) /* N1 is set */
827 if ((insn & 0x40000) == 0x40000) /* N1 is set */
833 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
834 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
835 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
838 cache->saved_regs[fp_start_reg++].addr = sp_offset;
841 else if ((insn & 0xf0000000) != 0xe0000000)
842 break; /* Condition not true, exit early */
843 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
844 break; /* Don't scan past a block load */
846 /* The optimizer might shove anything into the prologue,
847 so we just skip what we don't recognize. */
851 /* The frame size is just the negative of the offset (from the
852 original SP) of the last thing thing we pushed on the stack.
853 The frame offset is [new FP] - [new SP]. */
854 cache->framesize = -sp_offset;
855 if (cache->framereg == ARM_FP_REGNUM)
856 cache->frameoffset = fp_offset - sp_offset;
858 cache->frameoffset = 0;
861 static struct arm_prologue_cache *
862 arm_make_prologue_cache (struct frame_info *next_frame)
865 struct arm_prologue_cache *cache;
866 CORE_ADDR unwound_fp;
868 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
869 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
871 arm_scan_prologue (next_frame, cache);
873 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
877 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
879 /* Calculate actual addresses of saved registers using offsets
880 determined by arm_scan_prologue. */
881 for (reg = 0; reg < NUM_REGS; reg++)
882 if (trad_frame_addr_p (cache->saved_regs, reg))
883 cache->saved_regs[reg].addr += cache->prev_sp;
888 /* Our frame ID for a normal frame is the current function's starting PC
889 and the caller's SP when we were called. */
892 arm_prologue_this_id (struct frame_info *next_frame,
894 struct frame_id *this_id)
896 struct arm_prologue_cache *cache;
900 if (*this_cache == NULL)
901 *this_cache = arm_make_prologue_cache (next_frame);
904 func = frame_func_unwind (next_frame);
906 /* This is meant to halt the backtrace at "_start". Make sure we
907 don't halt it at a generic dummy frame. */
908 if (func <= LOWEST_PC)
911 /* If we've hit a wall, stop. */
912 if (cache->prev_sp == 0)
915 id = frame_id_build (cache->prev_sp, func);
920 arm_prologue_prev_register (struct frame_info *next_frame,
924 enum lval_type *lvalp,
929 struct arm_prologue_cache *cache;
931 if (*this_cache == NULL)
932 *this_cache = arm_make_prologue_cache (next_frame);
935 /* If we are asked to unwind the PC, then we need to return the LR
936 instead. The saved value of PC points into this frame's
937 prologue, not the next frame's resume location. */
938 if (prev_regnum == ARM_PC_REGNUM)
939 prev_regnum = ARM_LR_REGNUM;
941 /* SP is generally not saved to the stack, but this frame is
942 identified by NEXT_FRAME's stack pointer at the time of the call.
943 The value was already reconstructed into PREV_SP. */
944 if (prev_regnum == ARM_SP_REGNUM)
948 store_unsigned_integer (valuep, 4, cache->prev_sp);
952 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
953 optimized, lvalp, addrp, realnump, valuep);
956 struct frame_unwind arm_prologue_unwind = {
958 arm_prologue_this_id,
959 arm_prologue_prev_register
962 static const struct frame_unwind *
963 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
965 return &arm_prologue_unwind;
968 static struct arm_prologue_cache *
969 arm_make_stub_cache (struct frame_info *next_frame)
972 struct arm_prologue_cache *cache;
973 CORE_ADDR unwound_fp;
975 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
976 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
978 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
983 /* Our frame ID for a stub frame is the current SP and LR. */
986 arm_stub_this_id (struct frame_info *next_frame,
988 struct frame_id *this_id)
990 struct arm_prologue_cache *cache;
992 if (*this_cache == NULL)
993 *this_cache = arm_make_stub_cache (next_frame);
996 *this_id = frame_id_build (cache->prev_sp,
997 frame_pc_unwind (next_frame));
1000 struct frame_unwind arm_stub_unwind = {
1003 arm_prologue_prev_register
1006 static const struct frame_unwind *
1007 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1011 if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL)
1012 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1013 return &arm_stub_unwind;
1019 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1021 struct arm_prologue_cache *cache;
1023 if (*this_cache == NULL)
1024 *this_cache = arm_make_prologue_cache (next_frame);
1025 cache = *this_cache;
1027 return cache->prev_sp + cache->frameoffset - cache->framesize;
1030 struct frame_base arm_normal_base = {
1031 &arm_prologue_unwind,
1032 arm_normal_frame_base,
1033 arm_normal_frame_base,
1034 arm_normal_frame_base
1037 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1038 dummy frame. The frame ID's base needs to match the TOS value
1039 saved by save_dummy_frame_tos() and returned from
1040 arm_push_dummy_call, and the PC needs to match the dummy frame's
1043 static struct frame_id
1044 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1046 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1047 frame_pc_unwind (next_frame));
1050 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1051 be used to construct the previous frame's ID, after looking up the
1052 containing function). */
1055 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1058 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1059 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1063 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1065 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1068 /* When arguments must be pushed onto the stack, they go on in reverse
1069 order. The code below implements a FILO (stack) to do this. */
1074 struct stack_item *prev;
1078 static struct stack_item *
1079 push_stack_item (struct stack_item *prev, void *contents, int len)
1081 struct stack_item *si;
1082 si = xmalloc (sizeof (struct stack_item));
1083 si->data = xmalloc (len);
1086 memcpy (si->data, contents, len);
1090 static struct stack_item *
1091 pop_stack_item (struct stack_item *si)
1093 struct stack_item *dead = si;
1101 /* Return the alignment (in bytes) of the given type. */
1104 arm_type_align (struct type *t)
1110 t = check_typedef (t);
1111 switch (TYPE_CODE (t))
1114 /* Should never happen. */
1115 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1119 case TYPE_CODE_ENUM:
1123 case TYPE_CODE_RANGE:
1124 case TYPE_CODE_BITSTRING:
1126 case TYPE_CODE_CHAR:
1127 case TYPE_CODE_BOOL:
1128 return TYPE_LENGTH (t);
1130 case TYPE_CODE_ARRAY:
1131 case TYPE_CODE_COMPLEX:
1132 /* TODO: What about vector types? */
1133 return arm_type_align (TYPE_TARGET_TYPE (t));
1135 case TYPE_CODE_STRUCT:
1136 case TYPE_CODE_UNION:
1138 for (n = 0; n < TYPE_NFIELDS (t); n++)
1140 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1148 /* We currently only support passing parameters in integer registers. This
1149 conforms with GCC's default model. Several other variants exist and
1150 we should probably support some of them based on the selected ABI. */
1153 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1154 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1155 struct value **args, CORE_ADDR sp, int struct_return,
1156 CORE_ADDR struct_addr)
1161 struct stack_item *si = NULL;
1163 /* Set the return address. For the ARM, the return breakpoint is
1164 always at BP_ADDR. */
1165 /* XXX Fix for Thumb. */
1166 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1168 /* Walk through the list of args and determine how large a temporary
1169 stack is required. Need to take care here as structs may be
1170 passed on the stack, and we have to to push them. */
1173 argreg = ARM_A1_REGNUM;
1176 /* The struct_return pointer occupies the first parameter
1177 passing register. */
1181 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1182 REGISTER_NAME (argreg), paddr (struct_addr));
1183 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1187 for (argnum = 0; argnum < nargs; argnum++)
1190 struct type *arg_type;
1191 struct type *target_type;
1192 enum type_code typecode;
1196 arg_type = check_typedef (value_type (args[argnum]));
1197 len = TYPE_LENGTH (arg_type);
1198 target_type = TYPE_TARGET_TYPE (arg_type);
1199 typecode = TYPE_CODE (arg_type);
1200 val = value_contents_writeable (args[argnum]);
1202 align = arm_type_align (arg_type);
1203 /* Round alignment up to a whole number of words. */
1204 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1205 /* Different ABIs have different maximum alignments. */
1206 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1208 /* The APCS ABI only requires word alignment. */
1209 align = INT_REGISTER_SIZE;
1213 /* The AAPCS requires at most doubleword alignment. */
1214 if (align > INT_REGISTER_SIZE * 2)
1215 align = INT_REGISTER_SIZE * 2;
1218 /* Push stack padding for dowubleword alignment. */
1219 if (nstack & (align - 1))
1221 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1222 nstack += INT_REGISTER_SIZE;
1225 /* Doubleword aligned quantities must go in even register pairs. */
1226 if (argreg <= ARM_LAST_ARG_REGNUM
1227 && align > INT_REGISTER_SIZE
1231 /* If the argument is a pointer to a function, and it is a
1232 Thumb function, create a LOCAL copy of the value and set
1233 the THUMB bit in it. */
1234 if (TYPE_CODE_PTR == typecode
1235 && target_type != NULL
1236 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1238 CORE_ADDR regval = extract_unsigned_integer (val, len);
1239 if (arm_pc_is_thumb (regval))
1242 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1246 /* Copy the argument to general registers or the stack in
1247 register-sized pieces. Large arguments are split between
1248 registers and stack. */
1251 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1253 if (argreg <= ARM_LAST_ARG_REGNUM)
1255 /* The argument is being passed in a general purpose
1257 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1259 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1260 argnum, REGISTER_NAME (argreg),
1261 phex (regval, DEPRECATED_REGISTER_SIZE));
1262 regcache_cooked_write_unsigned (regcache, argreg, regval);
1267 /* Push the arguments onto the stack. */
1269 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1271 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1272 nstack += DEPRECATED_REGISTER_SIZE;
1279 /* If we have an odd number of words to push, then decrement the stack
1280 by one word now, so first stack argument will be dword aligned. */
1287 write_memory (sp, si->data, si->len);
1288 si = pop_stack_item (si);
1291 /* Finally, update teh SP register. */
1292 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1298 /* Always align the frame to an 8-byte boundary. This is required on
1299 some platforms and harmless on the rest. */
1302 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1304 /* Align the stack to eight bytes. */
1305 return sp & ~ (CORE_ADDR) 7;
1309 print_fpu_flags (int flags)
1311 if (flags & (1 << 0))
1312 fputs ("IVO ", stdout);
1313 if (flags & (1 << 1))
1314 fputs ("DVZ ", stdout);
1315 if (flags & (1 << 2))
1316 fputs ("OFL ", stdout);
1317 if (flags & (1 << 3))
1318 fputs ("UFL ", stdout);
1319 if (flags & (1 << 4))
1320 fputs ("INX ", stdout);
1324 /* Print interesting information about the floating point processor
1325 (if present) or emulator. */
1327 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1328 struct frame_info *frame, const char *args)
1330 unsigned long status = read_register (ARM_FPS_REGNUM);
1333 type = (status >> 24) & 127;
1334 if (status & (1 << 31))
1335 printf (_("Hardware FPU type %d\n"), type);
1337 printf (_("Software FPU type %d\n"), type);
1338 /* i18n: [floating point unit] mask */
1339 fputs (_("mask: "), stdout);
1340 print_fpu_flags (status >> 16);
1341 /* i18n: [floating point unit] flags */
1342 fputs (_("flags: "), stdout);
1343 print_fpu_flags (status);
1346 /* Return the GDB type object for the "standard" data type of data in
1349 static struct type *
1350 arm_register_type (struct gdbarch *gdbarch, int regnum)
1352 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1354 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1355 return builtin_type_arm_ext_big;
1357 return builtin_type_arm_ext_littlebyte_bigword;
1360 return builtin_type_int32;
1363 /* Index within `registers' of the first byte of the space for
1367 arm_register_byte (int regnum)
1369 if (regnum < ARM_F0_REGNUM)
1370 return regnum * INT_REGISTER_SIZE;
1371 else if (regnum < ARM_PS_REGNUM)
1372 return (NUM_GREGS * INT_REGISTER_SIZE
1373 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1375 return (NUM_GREGS * INT_REGISTER_SIZE
1376 + NUM_FREGS * FP_REGISTER_SIZE
1377 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1380 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1382 arm_register_sim_regno (int regnum)
1385 gdb_assert (reg >= 0 && reg < NUM_REGS);
1387 if (reg < NUM_GREGS)
1388 return SIM_ARM_R0_REGNUM + reg;
1391 if (reg < NUM_FREGS)
1392 return SIM_ARM_FP0_REGNUM + reg;
1395 if (reg < NUM_SREGS)
1396 return SIM_ARM_FPS_REGNUM + reg;
1399 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1402 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1403 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1404 It is thought that this is is the floating-point register format on
1405 little-endian systems. */
1408 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1412 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1413 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1415 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1417 floatformat_from_doublest (fmt, &d, dbl);
1421 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1424 floatformat_to_doublest (fmt, ptr, &d);
1425 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1426 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1428 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1433 condition_true (unsigned long cond, unsigned long status_reg)
1435 if (cond == INST_AL || cond == INST_NV)
1441 return ((status_reg & FLAG_Z) != 0);
1443 return ((status_reg & FLAG_Z) == 0);
1445 return ((status_reg & FLAG_C) != 0);
1447 return ((status_reg & FLAG_C) == 0);
1449 return ((status_reg & FLAG_N) != 0);
1451 return ((status_reg & FLAG_N) == 0);
1453 return ((status_reg & FLAG_V) != 0);
1455 return ((status_reg & FLAG_V) == 0);
1457 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1459 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1461 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1463 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1465 return (((status_reg & FLAG_Z) == 0) &&
1466 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1468 return (((status_reg & FLAG_Z) != 0) ||
1469 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1474 /* Support routines for single stepping. Calculate the next PC value. */
1475 #define submask(x) ((1L << ((x) + 1)) - 1)
1476 #define bit(obj,st) (((obj) >> (st)) & 1)
1477 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1478 #define sbits(obj,st,fn) \
1479 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1480 #define BranchDest(addr,instr) \
1481 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1484 static unsigned long
1485 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1486 unsigned long status_reg)
1488 unsigned long res, shift;
1489 int rm = bits (inst, 0, 3);
1490 unsigned long shifttype = bits (inst, 5, 6);
1494 int rs = bits (inst, 8, 11);
1495 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1498 shift = bits (inst, 7, 11);
1501 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1502 + (bit (inst, 4) ? 12 : 8))
1503 : read_register (rm));
1508 res = shift >= 32 ? 0 : res << shift;
1512 res = shift >= 32 ? 0 : res >> shift;
1518 res = ((res & 0x80000000L)
1519 ? ~((~res) >> shift) : res >> shift);
1522 case 3: /* ROR/RRX */
1525 res = (res >> 1) | (carry ? 0x80000000L : 0);
1527 res = (res >> shift) | (res << (32 - shift));
1531 return res & 0xffffffff;
1534 /* Return number of 1-bits in VAL. */
1537 bitcount (unsigned long val)
1540 for (nbits = 0; val != 0; nbits++)
1541 val &= val - 1; /* delete rightmost 1-bit in val */
1546 thumb_get_next_pc (CORE_ADDR pc)
1548 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1549 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1550 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1551 unsigned long offset;
1553 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1557 /* Fetch the saved PC from the stack. It's stored above
1558 all of the other registers. */
1559 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1560 sp = read_register (ARM_SP_REGNUM);
1561 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1562 nextpc = ADDR_BITS_REMOVE (nextpc);
1564 error (_("Infinite loop detected"));
1566 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1568 unsigned long status = read_register (ARM_PS_REGNUM);
1569 unsigned long cond = bits (inst1, 8, 11);
1570 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1571 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1573 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1575 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1577 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1579 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1580 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1581 nextpc = pc_val + offset;
1582 /* For BLX make sure to clear the low bits. */
1583 if (bits (inst2, 11, 12) == 1)
1584 nextpc = nextpc & 0xfffffffc;
1586 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1588 if (bits (inst1, 3, 6) == 0x0f)
1591 nextpc = read_register (bits (inst1, 3, 6));
1593 nextpc = ADDR_BITS_REMOVE (nextpc);
1595 error (_("Infinite loop detected"));
1602 arm_get_next_pc (CORE_ADDR pc)
1604 unsigned long pc_val;
1605 unsigned long this_instr;
1606 unsigned long status;
1609 if (arm_pc_is_thumb (pc))
1610 return thumb_get_next_pc (pc);
1612 pc_val = (unsigned long) pc;
1613 this_instr = read_memory_unsigned_integer (pc, 4);
1614 status = read_register (ARM_PS_REGNUM);
1615 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1617 if (condition_true (bits (this_instr, 28, 31), status))
1619 switch (bits (this_instr, 24, 27))
1622 case 0x1: /* data processing */
1626 unsigned long operand1, operand2, result = 0;
1630 if (bits (this_instr, 12, 15) != 15)
1633 if (bits (this_instr, 22, 25) == 0
1634 && bits (this_instr, 4, 7) == 9) /* multiply */
1635 error (_("Invalid update to pc in instruction"));
1637 /* BX <reg>, BLX <reg> */
1638 if (bits (this_instr, 4, 28) == 0x12fff1
1639 || bits (this_instr, 4, 28) == 0x12fff3)
1641 rn = bits (this_instr, 0, 3);
1642 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1643 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1646 error (_("Infinite loop detected"));
1651 /* Multiply into PC */
1652 c = (status & FLAG_C) ? 1 : 0;
1653 rn = bits (this_instr, 16, 19);
1654 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1656 if (bit (this_instr, 25))
1658 unsigned long immval = bits (this_instr, 0, 7);
1659 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1660 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1663 else /* operand 2 is a shifted register */
1664 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1666 switch (bits (this_instr, 21, 24))
1669 result = operand1 & operand2;
1673 result = operand1 ^ operand2;
1677 result = operand1 - operand2;
1681 result = operand2 - operand1;
1685 result = operand1 + operand2;
1689 result = operand1 + operand2 + c;
1693 result = operand1 - operand2 + c;
1697 result = operand2 - operand1 + c;
1703 case 0xb: /* tst, teq, cmp, cmn */
1704 result = (unsigned long) nextpc;
1708 result = operand1 | operand2;
1712 /* Always step into a function. */
1717 result = operand1 & ~operand2;
1724 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1727 error (_("Infinite loop detected"));
1732 case 0x5: /* data transfer */
1735 if (bit (this_instr, 20))
1738 if (bits (this_instr, 12, 15) == 15)
1744 if (bit (this_instr, 22))
1745 error (_("Invalid update to pc in instruction"));
1747 /* byte write to PC */
1748 rn = bits (this_instr, 16, 19);
1749 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1750 if (bit (this_instr, 24))
1753 int c = (status & FLAG_C) ? 1 : 0;
1754 unsigned long offset =
1755 (bit (this_instr, 25)
1756 ? shifted_reg_val (this_instr, c, pc_val, status)
1757 : bits (this_instr, 0, 11));
1759 if (bit (this_instr, 23))
1764 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1767 nextpc = ADDR_BITS_REMOVE (nextpc);
1770 error (_("Infinite loop detected"));
1776 case 0x9: /* block transfer */
1777 if (bit (this_instr, 20))
1780 if (bit (this_instr, 15))
1785 if (bit (this_instr, 23))
1788 unsigned long reglist = bits (this_instr, 0, 14);
1789 offset = bitcount (reglist) * 4;
1790 if (bit (this_instr, 24)) /* pre */
1793 else if (bit (this_instr, 24))
1797 unsigned long rn_val =
1798 read_register (bits (this_instr, 16, 19));
1800 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1804 nextpc = ADDR_BITS_REMOVE (nextpc);
1806 error (_("Infinite loop detected"));
1811 case 0xb: /* branch & link */
1812 case 0xa: /* branch */
1814 nextpc = BranchDest (pc, this_instr);
1817 if (bits (this_instr, 28, 31) == INST_NV)
1818 nextpc |= bit (this_instr, 24) << 1;
1820 nextpc = ADDR_BITS_REMOVE (nextpc);
1822 error (_("Infinite loop detected"));
1828 case 0xe: /* coproc ops */
1833 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1841 /* single_step() is called just before we want to resume the inferior,
1842 if we want to single-step it but there is no hardware or kernel
1843 single-step support. We find the target of the coming instruction
1846 single_step() is also called just after the inferior stops. If we
1847 had set up a simulated single-step, we undo our damage. */
1850 arm_software_single_step (enum target_signal sig, int insert_bpt)
1852 static int next_pc; /* State between setting and unsetting. */
1853 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
1857 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1858 target_insert_breakpoint (next_pc, break_mem);
1861 target_remove_breakpoint (next_pc, break_mem);
1864 #include "bfd-in2.h"
1865 #include "libcoff.h"
1868 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1870 if (arm_pc_is_thumb (memaddr))
1872 static asymbol *asym;
1873 static combined_entry_type ce;
1874 static struct coff_symbol_struct csym;
1875 static struct bfd fake_bfd;
1876 static bfd_target fake_target;
1878 if (csym.native == NULL)
1880 /* Create a fake symbol vector containing a Thumb symbol.
1881 This is solely so that the code in print_insn_little_arm()
1882 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1883 the presence of a Thumb symbol and switch to decoding
1884 Thumb instructions. */
1886 fake_target.flavour = bfd_target_coff_flavour;
1887 fake_bfd.xvec = &fake_target;
1888 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1890 csym.symbol.the_bfd = &fake_bfd;
1891 csym.symbol.name = "fake";
1892 asym = (asymbol *) & csym;
1895 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1896 info->symbols = &asym;
1899 info->symbols = NULL;
1901 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1902 return print_insn_big_arm (memaddr, info);
1904 return print_insn_little_arm (memaddr, info);
1907 /* The following define instruction sequences that will cause ARM
1908 cpu's to take an undefined instruction trap. These are used to
1909 signal a breakpoint to GDB.
1911 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1912 modes. A different instruction is required for each mode. The ARM
1913 cpu's can also be big or little endian. Thus four different
1914 instructions are needed to support all cases.
1916 Note: ARMv4 defines several new instructions that will take the
1917 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1918 not in fact add the new instructions. The new undefined
1919 instructions in ARMv4 are all instructions that had no defined
1920 behaviour in earlier chips. There is no guarantee that they will
1921 raise an exception, but may be treated as NOP's. In practice, it
1922 may only safe to rely on instructions matching:
1924 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1925 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1926 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1928 Even this may only true if the condition predicate is true. The
1929 following use a condition predicate of ALWAYS so it is always TRUE.
1931 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1932 and NetBSD all use a software interrupt rather than an undefined
1933 instruction to force a trap. This can be handled by by the
1934 abi-specific code during establishment of the gdbarch vector. */
1937 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1938 override these definitions. */
1939 #ifndef ARM_LE_BREAKPOINT
1940 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1942 #ifndef ARM_BE_BREAKPOINT
1943 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1945 #ifndef THUMB_LE_BREAKPOINT
1946 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1948 #ifndef THUMB_BE_BREAKPOINT
1949 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1952 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1953 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1954 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1955 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1957 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1958 the program counter value to determine whether a 16-bit or 32-bit
1959 breakpoint should be used. It returns a pointer to a string of
1960 bytes that encode a breakpoint instruction, stores the length of
1961 the string to *lenptr, and adjusts the program counter (if
1962 necessary) to point to the actual memory location where the
1963 breakpoint should be inserted. */
1965 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1966 breakpoints and storing their handles instread of what was in
1967 memory. It is nice that this is the same size as a handle -
1968 otherwise remote-rdp will have to change. */
1970 static const unsigned char *
1971 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1973 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1975 if (arm_pc_is_thumb (*pcptr))
1977 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1978 *lenptr = tdep->thumb_breakpoint_size;
1979 return tdep->thumb_breakpoint;
1983 *lenptr = tdep->arm_breakpoint_size;
1984 return tdep->arm_breakpoint;
1988 /* Extract from an array REGBUF containing the (raw) register state a
1989 function return value of type TYPE, and copy that, in virtual
1990 format, into VALBUF. */
1993 arm_extract_return_value (struct type *type, struct regcache *regs,
1996 if (TYPE_CODE_FLT == TYPE_CODE (type))
1998 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2002 /* The value is in register F0 in internal format. We need to
2003 extract the raw value and then convert it to the desired
2005 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2007 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2008 convert_from_extended (floatformat_from_type (type), tmpbuf,
2013 case ARM_FLOAT_SOFT_FPA:
2014 case ARM_FLOAT_SOFT_VFP:
2015 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2016 if (TYPE_LENGTH (type) > 4)
2017 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2018 valbuf + INT_REGISTER_SIZE);
2023 (__FILE__, __LINE__,
2024 _("arm_extract_return_value: Floating point model not supported"));
2028 else if (TYPE_CODE (type) == TYPE_CODE_INT
2029 || TYPE_CODE (type) == TYPE_CODE_CHAR
2030 || TYPE_CODE (type) == TYPE_CODE_BOOL
2031 || TYPE_CODE (type) == TYPE_CODE_PTR
2032 || TYPE_CODE (type) == TYPE_CODE_REF
2033 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2035 /* If the the type is a plain integer, then the access is
2036 straight-forward. Otherwise we have to play around a bit more. */
2037 int len = TYPE_LENGTH (type);
2038 int regno = ARM_A1_REGNUM;
2043 /* By using store_unsigned_integer we avoid having to do
2044 anything special for small big-endian values. */
2045 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2046 store_unsigned_integer (valbuf,
2047 (len > INT_REGISTER_SIZE
2048 ? INT_REGISTER_SIZE : len),
2050 len -= INT_REGISTER_SIZE;
2051 valbuf += INT_REGISTER_SIZE;
2056 /* For a structure or union the behaviour is as if the value had
2057 been stored to word-aligned memory and then loaded into
2058 registers with 32-bit load instruction(s). */
2059 int len = TYPE_LENGTH (type);
2060 int regno = ARM_A1_REGNUM;
2061 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2065 regcache_cooked_read (regs, regno++, tmpbuf);
2066 memcpy (valbuf, tmpbuf,
2067 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2068 len -= INT_REGISTER_SIZE;
2069 valbuf += INT_REGISTER_SIZE;
2075 /* Will a function return an aggregate type in memory or in a
2076 register? Return 0 if an aggregate type can be returned in a
2077 register, 1 if it must be returned in memory. */
2080 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2083 enum type_code code;
2085 CHECK_TYPEDEF (type);
2087 /* In the ARM ABI, "integer" like aggregate types are returned in
2088 registers. For an aggregate type to be integer like, its size
2089 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2090 offset of each addressable subfield must be zero. Note that bit
2091 fields are not addressable, and all addressable subfields of
2092 unions always start at offset zero.
2094 This function is based on the behaviour of GCC 2.95.1.
2095 See: gcc/arm.c: arm_return_in_memory() for details.
2097 Note: All versions of GCC before GCC 2.95.2 do not set up the
2098 parameters correctly for a function returning the following
2099 structure: struct { float f;}; This should be returned in memory,
2100 not a register. Richard Earnshaw sent me a patch, but I do not
2101 know of any way to detect if a function like the above has been
2102 compiled with the correct calling convention. */
2104 /* All aggregate types that won't fit in a register must be returned
2106 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2111 /* The AAPCS says all aggregates not larger than a word are returned
2113 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2116 /* The only aggregate types that can be returned in a register are
2117 structs and unions. Arrays must be returned in memory. */
2118 code = TYPE_CODE (type);
2119 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2124 /* Assume all other aggregate types can be returned in a register.
2125 Run a check for structures, unions and arrays. */
2128 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2131 /* Need to check if this struct/union is "integer" like. For
2132 this to be true, its size must be less than or equal to
2133 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2134 subfield must be zero. Note that bit fields are not
2135 addressable, and unions always start at offset zero. If any
2136 of the subfields is a floating point type, the struct/union
2137 cannot be an integer type. */
2139 /* For each field in the object, check:
2140 1) Is it FP? --> yes, nRc = 1;
2141 2) Is it addressable (bitpos != 0) and
2142 not packed (bitsize == 0)?
2146 for (i = 0; i < TYPE_NFIELDS (type); i++)
2148 enum type_code field_type_code;
2149 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2151 /* Is it a floating point type field? */
2152 if (field_type_code == TYPE_CODE_FLT)
2158 /* If bitpos != 0, then we have to care about it. */
2159 if (TYPE_FIELD_BITPOS (type, i) != 0)
2161 /* Bitfields are not addressable. If the field bitsize is
2162 zero, then the field is not packed. Hence it cannot be
2163 a bitfield or any other packed type. */
2164 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2176 /* Write into appropriate registers a function return value of type
2177 TYPE, given in virtual format. */
2180 arm_store_return_value (struct type *type, struct regcache *regs,
2181 const gdb_byte *valbuf)
2183 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2185 char buf[MAX_REGISTER_SIZE];
2187 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2191 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2192 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2195 case ARM_FLOAT_SOFT_FPA:
2196 case ARM_FLOAT_SOFT_VFP:
2197 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2198 if (TYPE_LENGTH (type) > 4)
2199 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2200 valbuf + INT_REGISTER_SIZE);
2205 (__FILE__, __LINE__,
2206 _("arm_store_return_value: Floating point model not supported"));
2210 else if (TYPE_CODE (type) == TYPE_CODE_INT
2211 || TYPE_CODE (type) == TYPE_CODE_CHAR
2212 || TYPE_CODE (type) == TYPE_CODE_BOOL
2213 || TYPE_CODE (type) == TYPE_CODE_PTR
2214 || TYPE_CODE (type) == TYPE_CODE_REF
2215 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2217 if (TYPE_LENGTH (type) <= 4)
2219 /* Values of one word or less are zero/sign-extended and
2221 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2222 LONGEST val = unpack_long (type, valbuf);
2224 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2225 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2229 /* Integral values greater than one word are stored in consecutive
2230 registers starting with r0. This will always be a multiple of
2231 the regiser size. */
2232 int len = TYPE_LENGTH (type);
2233 int regno = ARM_A1_REGNUM;
2237 regcache_cooked_write (regs, regno++, valbuf);
2238 len -= INT_REGISTER_SIZE;
2239 valbuf += INT_REGISTER_SIZE;
2245 /* For a structure or union the behaviour is as if the value had
2246 been stored to word-aligned memory and then loaded into
2247 registers with 32-bit load instruction(s). */
2248 int len = TYPE_LENGTH (type);
2249 int regno = ARM_A1_REGNUM;
2250 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2254 memcpy (tmpbuf, valbuf,
2255 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2256 regcache_cooked_write (regs, regno++, tmpbuf);
2257 len -= INT_REGISTER_SIZE;
2258 valbuf += INT_REGISTER_SIZE;
2264 /* Handle function return values. */
2266 static enum return_value_convention
2267 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2268 struct regcache *regcache, gdb_byte *readbuf,
2269 const gdb_byte *writebuf)
2271 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2272 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2273 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2275 if (arm_return_in_memory (gdbarch, valtype))
2276 return RETURN_VALUE_STRUCT_CONVENTION;
2280 arm_store_return_value (valtype, regcache, writebuf);
2283 arm_extract_return_value (valtype, regcache, readbuf);
2285 return RETURN_VALUE_REGISTER_CONVENTION;
2290 arm_get_longjmp_target (CORE_ADDR *pc)
2293 char buf[INT_REGISTER_SIZE];
2294 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2296 jb_addr = read_register (ARM_A1_REGNUM);
2298 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2302 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2306 /* Return non-zero if the PC is inside a thumb call thunk. */
2309 arm_in_call_stub (CORE_ADDR pc, char *name)
2311 CORE_ADDR start_addr;
2313 /* Find the starting address of the function containing the PC. If
2314 the caller didn't give us a name, look it up at the same time. */
2315 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2319 return strncmp (name, "_call_via_r", 11) == 0;
2322 /* If PC is in a Thumb call or return stub, return the address of the
2323 target PC, which is in a register. The thunk functions are called
2324 _called_via_xx, where x is the register name. The possible names
2325 are r0-r9, sl, fp, ip, sp, and lr. */
2328 arm_skip_stub (CORE_ADDR pc)
2331 CORE_ADDR start_addr;
2333 /* Find the starting address and name of the function containing the PC. */
2334 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2337 /* Call thunks always start with "_call_via_". */
2338 if (strncmp (name, "_call_via_", 10) == 0)
2340 /* Use the name suffix to determine which register contains the
2342 static char *table[15] =
2343 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2344 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2348 for (regno = 0; regno <= 14; regno++)
2349 if (strcmp (&name[10], table[regno]) == 0)
2350 return read_register (regno);
2353 return 0; /* not a stub */
2357 set_arm_command (char *args, int from_tty)
2359 printf_unfiltered (_("\
2360 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2361 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2365 show_arm_command (char *args, int from_tty)
2367 cmd_show_list (showarmcmdlist, from_tty, "");
2371 arm_update_current_architecture (void)
2373 struct gdbarch_info info;
2375 /* If the current architecture is not ARM, we have nothing to do. */
2376 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2379 /* Update the architecture. */
2380 gdbarch_info_init (&info);
2382 if (!gdbarch_update_p (info))
2383 internal_error (__FILE__, __LINE__, "could not update architecture");
2387 set_fp_model_sfunc (char *args, int from_tty,
2388 struct cmd_list_element *c)
2390 enum arm_float_model fp_model;
2392 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2393 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2395 arm_fp_model = fp_model;
2399 if (fp_model == ARM_FLOAT_LAST)
2400 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2403 arm_update_current_architecture ();
2407 show_fp_model (struct ui_file *file, int from_tty,
2408 struct cmd_list_element *c, const char *value)
2410 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2412 if (arm_fp_model == ARM_FLOAT_AUTO
2413 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2414 fprintf_filtered (file, _("\
2415 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2416 fp_model_strings[tdep->fp_model]);
2418 fprintf_filtered (file, _("\
2419 The current ARM floating point model is \"%s\".\n"),
2420 fp_model_strings[arm_fp_model]);
2424 arm_set_abi (char *args, int from_tty,
2425 struct cmd_list_element *c)
2427 enum arm_abi_kind arm_abi;
2429 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2430 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2432 arm_abi_global = arm_abi;
2436 if (arm_abi == ARM_ABI_LAST)
2437 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2440 arm_update_current_architecture ();
2444 arm_show_abi (struct ui_file *file, int from_tty,
2445 struct cmd_list_element *c, const char *value)
2447 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2449 if (arm_abi_global == ARM_ABI_AUTO
2450 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2451 fprintf_filtered (file, _("\
2452 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2453 arm_abi_strings[tdep->arm_abi]);
2455 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2459 /* If the user changes the register disassembly style used for info
2460 register and other commands, we have to also switch the style used
2461 in opcodes for disassembly output. This function is run in the "set
2462 arm disassembly" command, and does that. */
2465 set_disassembly_style_sfunc (char *args, int from_tty,
2466 struct cmd_list_element *c)
2468 set_disassembly_style ();
2471 /* Return the ARM register name corresponding to register I. */
2473 arm_register_name (int i)
2475 return arm_register_names[i];
2479 set_disassembly_style (void)
2481 const char *setname, *setdesc, *const *regnames;
2484 /* Find the style that the user wants in the opcodes table. */
2486 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2487 while ((disassembly_style != setname)
2488 && (current < num_disassembly_options))
2489 get_arm_regnames (++current, &setname, &setdesc, ®names);
2490 current_option = current;
2492 /* Fill our copy. */
2493 for (j = 0; j < numregs; j++)
2494 arm_register_names[j] = (char *) regnames[j];
2497 if (isupper (*regnames[ARM_PC_REGNUM]))
2499 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2500 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2504 arm_register_names[ARM_FPS_REGNUM] = "fps";
2505 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2508 /* Synchronize the disassembler. */
2509 set_arm_regname_option (current);
2512 /* Test whether the coff symbol specific value corresponds to a Thumb
2516 coff_sym_is_thumb (int val)
2518 return (val == C_THUMBEXT ||
2519 val == C_THUMBSTAT ||
2520 val == C_THUMBEXTFUNC ||
2521 val == C_THUMBSTATFUNC ||
2522 val == C_THUMBLABEL);
2525 /* arm_coff_make_msymbol_special()
2526 arm_elf_make_msymbol_special()
2528 These functions test whether the COFF or ELF symbol corresponds to
2529 an address in thumb code, and set a "special" bit in a minimal
2530 symbol to indicate that it does. */
2533 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2535 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2537 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2539 MSYMBOL_SET_SPECIAL (msym);
2543 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2545 if (coff_sym_is_thumb (val))
2546 MSYMBOL_SET_SPECIAL (msym);
2550 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2552 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2554 /* If necessary, set the T bit. */
2557 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2558 if (arm_pc_is_thumb (pc))
2559 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2561 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2565 static enum gdb_osabi
2566 arm_elf_osabi_sniffer (bfd *abfd)
2568 unsigned int elfosabi;
2569 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2571 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2573 if (elfosabi == ELFOSABI_ARM)
2574 /* GNU tools use this value. Check note sections in this case,
2576 bfd_map_over_sections (abfd,
2577 generic_elf_osabi_sniff_abi_tag_sections,
2580 /* Anything else will be handled by the generic ELF sniffer. */
2585 /* Initialize the current architecture based on INFO. If possible,
2586 re-use an architecture from ARCHES, which is a list of
2587 architectures already created during this debugging session.
2589 Called e.g. at program startup, when reading a core file, and when
2590 reading a binary file. */
2592 static struct gdbarch *
2593 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2595 struct gdbarch_tdep *tdep;
2596 struct gdbarch *gdbarch;
2597 struct gdbarch_list *best_arch;
2598 enum arm_abi_kind arm_abi = arm_abi_global;
2599 enum arm_float_model fp_model = arm_fp_model;
2601 /* If we have an object to base this architecture on, try to determine
2604 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2608 switch (bfd_get_flavour (info.abfd))
2610 case bfd_target_aout_flavour:
2611 /* Assume it's an old APCS-style ABI. */
2612 arm_abi = ARM_ABI_APCS;
2615 case bfd_target_coff_flavour:
2616 /* Assume it's an old APCS-style ABI. */
2618 arm_abi = ARM_ABI_APCS;
2621 case bfd_target_elf_flavour:
2622 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2623 if (ei_osabi == ELFOSABI_ARM)
2625 /* GNU tools used to use this value, but do not for EABI
2626 objects. There's nowhere to tag an EABI version anyway,
2628 arm_abi = ARM_ABI_APCS;
2630 else if (ei_osabi == ELFOSABI_NONE)
2632 int e_flags, eabi_ver;
2634 e_flags = elf_elfheader (info.abfd)->e_flags;
2635 eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2639 case EF_ARM_EABI_UNKNOWN:
2640 /* Assume GNU tools. */
2641 arm_abi = ARM_ABI_APCS;
2644 case EF_ARM_EABI_VER4:
2645 arm_abi = ARM_ABI_AAPCS;
2646 /* EABI binaries default to VFP float ordering. */
2647 if (fp_model == ARM_FLOAT_AUTO)
2648 fp_model = ARM_FLOAT_SOFT_VFP;
2652 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2653 arm_abi = ARM_ABI_APCS;
2660 /* Leave it as "auto". */
2665 /* Now that we have inferred any architecture settings that we
2666 can, try to inherit from the last ARM ABI. */
2669 if (arm_abi == ARM_ABI_AUTO)
2670 arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi;
2672 if (fp_model == ARM_FLOAT_AUTO)
2673 fp_model = gdbarch_tdep (arches->gdbarch)->fp_model;
2677 /* There was no prior ARM architecture; fill in default values. */
2679 if (arm_abi == ARM_ABI_AUTO)
2680 arm_abi = ARM_ABI_APCS;
2682 /* We used to default to FPA for generic ARM, but almost nobody
2683 uses that now, and we now provide a way for the user to force
2684 the model. So default to the most useful variant. */
2685 if (fp_model == ARM_FLOAT_AUTO)
2686 fp_model = ARM_FLOAT_SOFT_FPA;
2689 /* If there is already a candidate, use it. */
2690 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2692 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2694 if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2697 if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2700 /* Found a match. */
2704 if (best_arch != NULL)
2705 return best_arch->gdbarch;
2707 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2708 gdbarch = gdbarch_alloc (&info, tdep);
2710 /* Record additional information about the architecture we are defining.
2711 These are gdbarch discriminators, like the OSABI. */
2712 tdep->arm_abi = arm_abi;
2713 tdep->fp_model = fp_model;
2716 switch (info.byte_order)
2718 case BFD_ENDIAN_BIG:
2719 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2720 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2721 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2722 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2726 case BFD_ENDIAN_LITTLE:
2727 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2728 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2729 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2730 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2735 internal_error (__FILE__, __LINE__,
2736 _("arm_gdbarch_init: bad byte order for float format"));
2739 /* On ARM targets char defaults to unsigned. */
2740 set_gdbarch_char_signed (gdbarch, 0);
2742 /* This should be low enough for everything. */
2743 tdep->lowest_pc = 0x20;
2744 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2746 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2747 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2749 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2751 /* Frame handling. */
2752 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2753 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2754 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2756 frame_base_set_default (gdbarch, &arm_normal_base);
2758 /* Address manipulation. */
2759 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2760 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2762 /* Advance PC across function entry code. */
2763 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2765 /* Get the PC when a frame might not be available. */
2766 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2768 /* The stack grows downward. */
2769 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2771 /* Breakpoint manipulation. */
2772 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2774 /* Information about registers, etc. */
2775 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2776 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2777 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2778 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2779 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2780 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2781 set_gdbarch_register_type (gdbarch, arm_register_type);
2783 /* Internal <-> external register number maps. */
2784 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2786 /* Integer registers are 4 bytes. */
2787 set_gdbarch_deprecated_register_size (gdbarch, 4);
2788 set_gdbarch_register_name (gdbarch, arm_register_name);
2790 /* Returning results. */
2791 set_gdbarch_return_value (gdbarch, arm_return_value);
2793 /* Single stepping. */
2794 /* XXX For an RDI target we should ask the target if it can single-step. */
2795 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2798 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2800 /* Minsymbol frobbing. */
2801 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2802 set_gdbarch_coff_make_msymbol_special (gdbarch,
2803 arm_coff_make_msymbol_special);
2805 /* Hook in the ABI-specific overrides, if they have been registered. */
2806 gdbarch_init_osabi (info, gdbarch);
2808 /* Add some default predicates. */
2809 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
2810 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2811 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2813 /* Now we have tuned the configuration, set a few final things,
2814 based on what the OS ABI has told us. */
2816 if (tdep->jb_pc >= 0)
2817 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2819 /* Floating point sizes and format. */
2820 switch (info.byte_order)
2822 case BFD_ENDIAN_BIG:
2823 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2824 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2825 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2828 case BFD_ENDIAN_LITTLE:
2829 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2830 if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)
2832 set_gdbarch_double_format
2833 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2834 set_gdbarch_long_double_format
2835 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2839 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2840 set_gdbarch_long_double_format (gdbarch,
2841 &floatformat_ieee_double_little);
2846 internal_error (__FILE__, __LINE__,
2847 _("arm_gdbarch_init: bad byte order for float format"));
2854 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2856 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2861 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2862 (unsigned long) tdep->lowest_pc);
2865 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2868 _initialize_arm_tdep (void)
2870 struct ui_file *stb;
2872 struct cmd_list_element *new_set, *new_show;
2873 const char *setname;
2874 const char *setdesc;
2875 const char *const *regnames;
2877 static char *helptext;
2878 char regdesc[1024], *rdptr = regdesc;
2879 size_t rest = sizeof (regdesc);
2881 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2883 /* Register an ELF OS ABI sniffer for ARM binaries. */
2884 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2885 bfd_target_elf_flavour,
2886 arm_elf_osabi_sniffer);
2888 /* Get the number of possible sets of register names defined in opcodes. */
2889 num_disassembly_options = get_arm_regname_num_options ();
2891 /* Add root prefix command for all "set arm"/"show arm" commands. */
2892 add_prefix_cmd ("arm", no_class, set_arm_command,
2893 _("Various ARM-specific commands."),
2894 &setarmcmdlist, "set arm ", 0, &setlist);
2896 add_prefix_cmd ("arm", no_class, show_arm_command,
2897 _("Various ARM-specific commands."),
2898 &showarmcmdlist, "show arm ", 0, &showlist);
2900 /* Sync the opcode insn printer with our register viewer. */
2901 parse_arm_disassembler_option ("reg-names-std");
2903 /* Initialize the array that will be passed to
2904 add_setshow_enum_cmd(). */
2905 valid_disassembly_styles
2906 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2907 for (i = 0; i < num_disassembly_options; i++)
2909 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2910 valid_disassembly_styles[i] = setname;
2911 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
2914 /* Copy the default names (if found) and synchronize disassembler. */
2915 if (!strcmp (setname, "std"))
2917 disassembly_style = setname;
2919 for (j = 0; j < numregs; j++)
2920 arm_register_names[j] = (char *) regnames[j];
2921 set_arm_regname_option (i);
2924 /* Mark the end of valid options. */
2925 valid_disassembly_styles[num_disassembly_options] = NULL;
2927 /* Create the help text. */
2928 stb = mem_fileopen ();
2929 fprintf_unfiltered (stb, "%s%s%s",
2930 _("The valid values are:\n"),
2932 _("The default is \"std\"."));
2933 helptext = ui_file_xstrdup (stb, &length);
2934 ui_file_delete (stb);
2936 add_setshow_enum_cmd("disassembler", no_class,
2937 valid_disassembly_styles, &disassembly_style,
2938 _("Set the disassembly style."),
2939 _("Show the disassembly style."),
2941 set_disassembly_style_sfunc,
2942 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
2943 &setarmcmdlist, &showarmcmdlist);
2945 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2946 _("Set usage of ARM 32-bit mode."),
2947 _("Show usage of ARM 32-bit mode."),
2948 _("When off, a 26-bit PC will be used."),
2950 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2951 &setarmcmdlist, &showarmcmdlist);
2953 /* Add a command to allow the user to force the FPU model. */
2954 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2955 _("Set the floating point type."),
2956 _("Show the floating point type."),
2957 _("auto - Determine the FP typefrom the OS-ABI.\n\
2958 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2959 fpa - FPA co-processor (GCC compiled).\n\
2960 softvfp - Software FP with pure-endian doubles.\n\
2961 vfp - VFP co-processor."),
2962 set_fp_model_sfunc, show_fp_model,
2963 &setarmcmdlist, &showarmcmdlist);
2965 /* Add a command to allow the user to force the ABI. */
2966 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
2969 NULL, arm_set_abi, arm_show_abi,
2970 &setarmcmdlist, &showarmcmdlist);
2972 /* Debugging flag. */
2973 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2974 _("Set ARM debugging."),
2975 _("Show ARM debugging."),
2976 _("When on, arm-specific debugging is enabled."),
2978 NULL, /* FIXME: i18n: "ARM debugging is %s. */
2979 &setdebuglist, &showdebuglist);