1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
72 /* Per-objfile data used for mapping symbols. */
73 static const struct objfile_data *arm_objfile_data_key;
75 struct arm_mapping_symbol
80 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
81 DEF_VEC_O(arm_mapping_symbol_s);
83 struct arm_per_objfile
85 VEC(arm_mapping_symbol_s) **section_maps;
88 /* The list of available "set arm ..." and "show arm ..." commands. */
89 static struct cmd_list_element *setarmcmdlist = NULL;
90 static struct cmd_list_element *showarmcmdlist = NULL;
92 /* The type of floating-point to use. Keep this in sync with enum
93 arm_float_model, and the help string in _initialize_arm_tdep. */
94 static const char *fp_model_strings[] =
104 /* A variable that can be configured by the user. */
105 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
106 static const char *current_fp_model = "auto";
108 /* The ABI to use. Keep this in sync with arm_abi_kind. */
109 static const char *arm_abi_strings[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
119 static const char *arm_abi_string = "auto";
121 /* The execution mode to assume. */
122 static const char *arm_mode_strings[] =
129 static const char *arm_fallback_mode_string = "auto";
130 static const char *arm_force_mode_string = "auto";
132 /* Number of different reg name sets (options). */
133 static int num_disassembly_options;
135 /* The standard register names, and all the valid aliases for them. */
140 } arm_register_aliases[] = {
141 /* Basic register numbers. */
158 /* Synonyms (argument and variable registers). */
171 /* Other platform-specific names for r9. */
179 /* Names used by GCC (not listed in the ARM EABI). */
182 /* A special name from the older ATPCS. */
186 static const char *const arm_register_names[] =
187 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
188 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
189 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
190 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
191 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
192 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
193 "fps", "cpsr" }; /* 24 25 */
195 /* Valid register name styles. */
196 static const char **valid_disassembly_styles;
198 /* Disassembly style to use. Default to "std" register names. */
199 static const char *disassembly_style;
201 /* This is used to keep the bfd arch_info in sync with the disassembly
203 static void set_disassembly_style_sfunc(char *, int,
204 struct cmd_list_element *);
205 static void set_disassembly_style (void);
207 static void convert_from_extended (const struct floatformat *, const void *,
209 static void convert_to_extended (const struct floatformat *, void *,
212 struct arm_prologue_cache
214 /* The stack pointer at the time this frame was created; i.e. the
215 caller's stack pointer when this function was called. It is used
216 to identify this frame. */
219 /* The frame base for this frame is just prev_sp - frame size.
220 FRAMESIZE is the distance from the frame pointer to the
221 initial stack pointer. */
225 /* The register used to hold the frame pointer for this frame. */
228 /* Saved register offsets. */
229 struct trad_frame_saved_reg *saved_regs;
232 /* Addresses for calling Thumb functions have the bit 0 set.
233 Here are some macros to test, set, or clear bit 0 of addresses. */
234 #define IS_THUMB_ADDR(addr) ((addr) & 1)
235 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
236 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
238 /* Set to true if the 32-bit mode is in use. */
242 /* Determine if FRAME is executing in Thumb mode. */
245 arm_frame_is_thumb (struct frame_info *frame)
249 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
250 directly (from a signal frame or dummy frame) or by interpreting
251 the saved LR (from a prologue or DWARF frame). So consult it and
252 trust the unwinders. */
253 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
255 return (cpsr & CPSR_T) != 0;
258 /* Callback for VEC_lower_bound. */
261 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
262 const struct arm_mapping_symbol *rhs)
264 return lhs->value < rhs->value;
267 /* Determine if the program counter specified in MEMADDR is in a Thumb
268 function. This function should be called for addresses unrelated to
269 any executing frame; otherwise, prefer arm_frame_is_thumb. */
272 arm_pc_is_thumb (CORE_ADDR memaddr)
274 struct obj_section *sec;
275 struct minimal_symbol *sym;
277 /* If bit 0 of the address is set, assume this is a Thumb address. */
278 if (IS_THUMB_ADDR (memaddr))
281 /* If the user wants to override the symbol table, let him. */
282 if (strcmp (arm_force_mode_string, "arm") == 0)
284 if (strcmp (arm_force_mode_string, "thumb") == 0)
287 /* If there are mapping symbols, consult them. */
288 sec = find_pc_section (memaddr);
291 struct arm_per_objfile *data;
292 VEC(arm_mapping_symbol_s) *map;
293 struct arm_mapping_symbol map_key = { memaddr - sec->addr, 0 };
296 data = objfile_data (sec->objfile, arm_objfile_data_key);
299 map = data->section_maps[sec->the_bfd_section->index];
300 if (!VEC_empty (arm_mapping_symbol_s, map))
302 struct arm_mapping_symbol *map_sym;
304 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
305 arm_compare_mapping_symbols);
307 /* VEC_lower_bound finds the earliest ordered insertion
308 point. If the following symbol starts at this exact
309 address, we use that; otherwise, the preceding
310 mapping symbol covers this address. */
311 if (idx < VEC_length (arm_mapping_symbol_s, map))
313 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
314 if (map_sym->value == map_key.value)
315 return map_sym->type == 't';
320 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
321 return map_sym->type == 't';
327 /* Thumb functions have a "special" bit set in minimal symbols. */
328 sym = lookup_minimal_symbol_by_pc (memaddr);
330 return (MSYMBOL_IS_SPECIAL (sym));
332 /* If the user wants to override the fallback mode, let them. */
333 if (strcmp (arm_fallback_mode_string, "arm") == 0)
335 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
338 /* If we couldn't find any symbol, but we're talking to a running
339 target, then trust the current value of $cpsr. This lets
340 "display/i $pc" always show the correct mode (though if there is
341 a symbol table we will not reach here, so it still may not be
342 displayed in the mode it will be executed). */
343 if (target_has_registers)
344 return arm_frame_is_thumb (get_current_frame ());
346 /* Otherwise we're out of luck; we assume ARM. */
350 /* Remove useless bits from addresses in a running program. */
352 arm_addr_bits_remove (CORE_ADDR val)
355 return UNMAKE_THUMB_ADDR (val);
357 return (val & 0x03fffffc);
360 /* When reading symbols, we need to zap the low bit of the address,
361 which may be set to 1 for Thumb functions. */
363 arm_smash_text_address (CORE_ADDR val)
368 /* Analyze a Thumb prologue, looking for a recognizable stack frame
369 and frame pointer. Scan until we encounter a store that could
370 clobber the stack frame unexpectedly, or an unknown instruction. */
373 thumb_analyze_prologue (struct gdbarch *gdbarch,
374 CORE_ADDR start, CORE_ADDR limit,
375 struct arm_prologue_cache *cache)
379 struct pv_area *stack;
380 struct cleanup *back_to;
383 for (i = 0; i < 16; i++)
384 regs[i] = pv_register (i, 0);
385 stack = make_pv_area (ARM_SP_REGNUM);
386 back_to = make_cleanup_free_pv_area (stack);
388 while (start < limit)
392 insn = read_memory_unsigned_integer (start, 2);
394 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
399 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
402 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
403 whether to save LR (R14). */
404 mask = (insn & 0xff) | ((insn & 0x100) << 6);
406 /* Calculate offsets of saved R0-R7 and LR. */
407 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
408 if (mask & (1 << regno))
410 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
412 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
415 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
418 offset = (insn & 0x7f) << 2; /* get scaled offset */
419 if (insn & 0x80) /* Check for SUB. */
420 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
423 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
426 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
427 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
429 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
431 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
432 int src_reg = (insn & 0x78) >> 3;
433 regs[dst_reg] = regs[src_reg];
435 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
437 /* Handle stores to the stack. Normally pushes are used,
438 but with GCC -mtpcs-frame, there may be other stores
439 in the prologue to create the frame. */
440 int regno = (insn >> 8) & 0x7;
443 offset = (insn & 0xff) << 2;
444 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
446 if (pv_area_store_would_trash (stack, addr))
449 pv_area_store (stack, addr, 4, regs[regno]);
453 /* We don't know what this instruction is. We're finished
454 scanning. NOTE: Recognizing more safe-to-ignore
455 instructions here will improve support for optimized
465 do_cleanups (back_to);
469 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
471 /* Frame pointer is fp. Frame size is constant. */
472 cache->framereg = ARM_FP_REGNUM;
473 cache->framesize = -regs[ARM_FP_REGNUM].k;
475 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
477 /* Frame pointer is r7. Frame size is constant. */
478 cache->framereg = THUMB_FP_REGNUM;
479 cache->framesize = -regs[THUMB_FP_REGNUM].k;
481 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
483 /* Try the stack pointer... this is a bit desperate. */
484 cache->framereg = ARM_SP_REGNUM;
485 cache->framesize = -regs[ARM_SP_REGNUM].k;
489 /* We're just out of luck. We don't know where the frame is. */
490 cache->framereg = -1;
491 cache->framesize = 0;
494 for (i = 0; i < 16; i++)
495 if (pv_area_find_reg (stack, gdbarch, i, &offset))
496 cache->saved_regs[i].addr = offset;
498 do_cleanups (back_to);
502 /* Advance the PC across any function entry prologue instructions to
503 reach some "real" code.
505 The APCS (ARM Procedure Call Standard) defines the following
509 [stmfd sp!, {a1,a2,a3,a4}]
510 stmfd sp!, {...,fp,ip,lr,pc}
511 [stfe f7, [sp, #-12]!]
512 [stfe f6, [sp, #-12]!]
513 [stfe f5, [sp, #-12]!]
514 [stfe f4, [sp, #-12]!]
515 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
518 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
522 CORE_ADDR func_addr, func_end = 0;
524 struct symtab_and_line sal;
526 /* If we're in a dummy frame, don't even try to skip the prologue. */
527 if (deprecated_pc_in_call_dummy (pc))
530 /* See what the symbol table says. */
532 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
536 /* Found a function. */
537 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
538 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
540 /* Don't use this trick for assembly source files. */
541 sal = find_pc_line (func_addr, 0);
542 if ((sal.line != 0) && (sal.end < func_end))
547 /* Can't find the prologue end in the symbol table, try it the hard way
548 by disassembling the instructions. */
550 /* Like arm_scan_prologue, stop no later than pc + 64. */
551 if (func_end == 0 || func_end > pc + 64)
554 /* Check if this is Thumb code. */
555 if (arm_pc_is_thumb (pc))
556 return thumb_analyze_prologue (gdbarch, pc, func_end, NULL);
558 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
560 inst = read_memory_unsigned_integer (skip_pc, 4);
562 /* "mov ip, sp" is no longer a required part of the prologue. */
563 if (inst == 0xe1a0c00d) /* mov ip, sp */
566 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
569 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
572 /* Some prologues begin with "str lr, [sp, #-4]!". */
573 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
576 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
579 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
582 /* Any insns after this point may float into the code, if it makes
583 for better instruction scheduling, so we skip them only if we
584 find them, but still consider the function to be frame-ful. */
586 /* We may have either one sfmfd instruction here, or several stfe
587 insns, depending on the version of floating point code we
589 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
592 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
595 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
598 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
601 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
602 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
603 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
606 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
607 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
608 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
611 /* Un-recognized instruction; stop scanning. */
615 return skip_pc; /* End of prologue */
619 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
620 This function decodes a Thumb function prologue to determine:
621 1) the size of the stack frame
622 2) which registers are saved on it
623 3) the offsets of saved regs
624 4) the offset from the stack pointer to the frame pointer
626 A typical Thumb function prologue would create this stack frame
627 (offsets relative to FP)
628 old SP -> 24 stack parameters
631 R7 -> 0 local variables (16 bytes)
632 SP -> -12 additional stack space (12 bytes)
633 The frame size would thus be 36 bytes, and the frame offset would be
634 12 bytes. The frame register is R7.
636 The comments for thumb_skip_prolog() describe the algorithm we use
637 to detect the end of the prolog. */
641 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
642 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
644 CORE_ADDR prologue_start;
645 CORE_ADDR prologue_end;
646 CORE_ADDR current_pc;
648 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
651 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
653 if (sal.line == 0) /* no line info, use current PC */
654 prologue_end = prev_pc;
655 else if (sal.end < prologue_end) /* next line begins after fn end */
656 prologue_end = sal.end; /* (probably means no prologue) */
659 /* We're in the boondocks: we have no idea where the start of the
663 prologue_end = min (prologue_end, prev_pc);
665 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
668 /* This function decodes an ARM function prologue to determine:
669 1) the size of the stack frame
670 2) which registers are saved on it
671 3) the offsets of saved regs
672 4) the offset from the stack pointer to the frame pointer
673 This information is stored in the "extra" fields of the frame_info.
675 There are two basic forms for the ARM prologue. The fixed argument
676 function call will look like:
679 stmfd sp!, {fp, ip, lr, pc}
683 Which would create this stack frame (offsets relative to FP):
684 IP -> 4 (caller's stack)
685 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
686 -4 LR (return address in caller)
687 -8 IP (copy of caller's SP)
689 SP -> -28 Local variables
691 The frame size would thus be 32 bytes, and the frame offset would be
692 28 bytes. The stmfd call can also save any of the vN registers it
693 plans to use, which increases the frame size accordingly.
695 Note: The stored PC is 8 off of the STMFD instruction that stored it
696 because the ARM Store instructions always store PC + 8 when you read
699 A variable argument function call will look like:
702 stmfd sp!, {a1, a2, a3, a4}
703 stmfd sp!, {fp, ip, lr, pc}
706 Which would create this stack frame (offsets relative to FP):
707 IP -> 20 (caller's stack)
712 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
713 -4 LR (return address in caller)
714 -8 IP (copy of caller's SP)
716 SP -> -28 Local variables
718 The frame size would thus be 48 bytes, and the frame offset would be
721 There is another potential complication, which is that the optimizer
722 will try to separate the store of fp in the "stmfd" instruction from
723 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
724 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
726 Also, note, the original version of the ARM toolchain claimed that there
729 instruction at the end of the prologue. I have never seen GCC produce
730 this, and the ARM docs don't mention it. We still test for it below in
736 arm_scan_prologue (struct frame_info *this_frame,
737 struct arm_prologue_cache *cache)
739 struct gdbarch *gdbarch = get_frame_arch (this_frame);
741 CORE_ADDR prologue_start, prologue_end, current_pc;
742 CORE_ADDR prev_pc = get_frame_pc (this_frame);
743 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
744 pv_t regs[ARM_FPS_REGNUM];
745 struct pv_area *stack;
746 struct cleanup *back_to;
749 /* Assume there is no frame until proven otherwise. */
750 cache->framereg = ARM_SP_REGNUM;
751 cache->framesize = 0;
753 /* Check for Thumb prologue. */
754 if (arm_frame_is_thumb (this_frame))
756 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
760 /* Find the function prologue. If we can't find the function in
761 the symbol table, peek in the stack frame to find the PC. */
762 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
765 /* One way to find the end of the prologue (which works well
766 for unoptimized code) is to do the following:
768 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
771 prologue_end = prev_pc;
772 else if (sal.end < prologue_end)
773 prologue_end = sal.end;
775 This mechanism is very accurate so long as the optimizer
776 doesn't move any instructions from the function body into the
777 prologue. If this happens, sal.end will be the last
778 instruction in the first hunk of prologue code just before
779 the first instruction that the scheduler has moved from
780 the body to the prologue.
782 In order to make sure that we scan all of the prologue
783 instructions, we use a slightly less accurate mechanism which
784 may scan more than necessary. To help compensate for this
785 lack of accuracy, the prologue scanning loop below contains
786 several clauses which'll cause the loop to terminate early if
787 an implausible prologue instruction is encountered.
793 is a suitable endpoint since it accounts for the largest
794 possible prologue plus up to five instructions inserted by
797 if (prologue_end > prologue_start + 64)
799 prologue_end = prologue_start + 64; /* See above. */
804 /* We have no symbol information. Our only option is to assume this
805 function has a standard stack frame and the normal frame register.
806 Then, we can find the value of our frame pointer on entrance to
807 the callee (or at the present moment if this is the innermost frame).
808 The value stored there should be the address of the stmfd + 8. */
810 LONGEST return_value;
812 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
813 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
817 prologue_start = gdbarch_addr_bits_remove
818 (gdbarch, return_value) - 8;
819 prologue_end = prologue_start + 64; /* See above. */
823 if (prev_pc < prologue_end)
824 prologue_end = prev_pc;
826 /* Now search the prologue looking for instructions that set up the
827 frame pointer, adjust the stack pointer, and save registers.
829 Be careful, however, and if it doesn't look like a prologue,
830 don't try to scan it. If, for instance, a frameless function
831 begins with stmfd sp!, then we will tell ourselves there is
832 a frame, which will confuse stack traceback, as well as "finish"
833 and other operations that rely on a knowledge of the stack
836 In the APCS, the prologue should start with "mov ip, sp" so
837 if we don't see this as the first insn, we will stop.
839 [Note: This doesn't seem to be true any longer, so it's now an
840 optional part of the prologue. - Kevin Buettner, 2001-11-20]
842 [Note further: The "mov ip,sp" only seems to be missing in
843 frameless functions at optimization level "-O2" or above,
844 in which case it is often (but not always) replaced by
845 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
847 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
848 regs[regno] = pv_register (regno, 0);
849 stack = make_pv_area (ARM_SP_REGNUM);
850 back_to = make_cleanup_free_pv_area (stack);
852 for (current_pc = prologue_start;
853 current_pc < prologue_end;
856 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
858 if (insn == 0xe1a0c00d) /* mov ip, sp */
860 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
863 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
865 unsigned imm = insn & 0xff; /* immediate value */
866 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
867 imm = (imm >> rot) | (imm << (32 - rot));
868 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
871 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
873 unsigned imm = insn & 0xff; /* immediate value */
874 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
875 imm = (imm >> rot) | (imm << (32 - rot));
876 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
879 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
881 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
883 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
884 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
887 else if ((insn & 0xffff0000) == 0xe92d0000)
888 /* stmfd sp!, {..., fp, ip, lr, pc}
890 stmfd sp!, {a1, a2, a3, a4} */
892 int mask = insn & 0xffff;
894 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
897 /* Calculate offsets of saved registers. */
898 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
899 if (mask & (1 << regno))
901 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
902 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
905 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
906 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
907 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
909 /* No need to add this to saved_regs -- it's just an arg reg. */
912 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
913 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
914 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
916 /* No need to add this to saved_regs -- it's just an arg reg. */
919 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
921 unsigned imm = insn & 0xff; /* immediate value */
922 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
923 imm = (imm >> rot) | (imm << (32 - rot));
924 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
926 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
928 unsigned imm = insn & 0xff; /* immediate value */
929 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
930 imm = (imm >> rot) | (imm << (32 - rot));
931 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
933 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
934 && gdbarch_tdep (gdbarch)->have_fpa_registers)
936 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
939 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
940 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
941 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
943 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
944 && gdbarch_tdep (gdbarch)->have_fpa_registers)
947 unsigned int fp_start_reg, fp_bound_reg;
949 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
952 if ((insn & 0x800) == 0x800) /* N0 is set */
954 if ((insn & 0x40000) == 0x40000) /* N1 is set */
961 if ((insn & 0x40000) == 0x40000) /* N1 is set */
967 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
968 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
969 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
971 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
972 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
973 regs[fp_start_reg++]);
976 else if ((insn & 0xf0000000) != 0xe0000000)
977 break; /* Condition not true, exit early */
978 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
979 break; /* Don't scan past a block load */
981 /* The optimizer might shove anything into the prologue,
982 so we just skip what we don't recognize. */
986 /* The frame size is just the distance from the frame register
987 to the original stack pointer. */
988 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
990 /* Frame pointer is fp. */
991 cache->framereg = ARM_FP_REGNUM;
992 cache->framesize = -regs[ARM_FP_REGNUM].k;
994 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
996 /* Try the stack pointer... this is a bit desperate. */
997 cache->framereg = ARM_SP_REGNUM;
998 cache->framesize = -regs[ARM_SP_REGNUM].k;
1002 /* We're just out of luck. We don't know where the frame is. */
1003 cache->framereg = -1;
1004 cache->framesize = 0;
1007 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1008 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1009 cache->saved_regs[regno].addr = offset;
1011 do_cleanups (back_to);
1014 static struct arm_prologue_cache *
1015 arm_make_prologue_cache (struct frame_info *this_frame)
1018 struct arm_prologue_cache *cache;
1019 CORE_ADDR unwound_fp;
1021 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1022 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1024 arm_scan_prologue (this_frame, cache);
1026 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1027 if (unwound_fp == 0)
1030 cache->prev_sp = unwound_fp + cache->framesize;
1032 /* Calculate actual addresses of saved registers using offsets
1033 determined by arm_scan_prologue. */
1034 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1035 if (trad_frame_addr_p (cache->saved_regs, reg))
1036 cache->saved_regs[reg].addr += cache->prev_sp;
1041 /* Our frame ID for a normal frame is the current function's starting PC
1042 and the caller's SP when we were called. */
1045 arm_prologue_this_id (struct frame_info *this_frame,
1047 struct frame_id *this_id)
1049 struct arm_prologue_cache *cache;
1053 if (*this_cache == NULL)
1054 *this_cache = arm_make_prologue_cache (this_frame);
1055 cache = *this_cache;
1057 /* This is meant to halt the backtrace at "_start". */
1058 pc = get_frame_pc (this_frame);
1059 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1062 /* If we've hit a wall, stop. */
1063 if (cache->prev_sp == 0)
1066 func = get_frame_func (this_frame);
1067 id = frame_id_build (cache->prev_sp, func);
1071 static struct value *
1072 arm_prologue_prev_register (struct frame_info *this_frame,
1076 struct arm_prologue_cache *cache;
1078 if (*this_cache == NULL)
1079 *this_cache = arm_make_prologue_cache (this_frame);
1080 cache = *this_cache;
1082 /* If we are asked to unwind the PC, then we need to return the LR
1083 instead. The prologue may save PC, but it will point into this
1084 frame's prologue, not the next frame's resume location. Also
1085 strip the saved T bit. A valid LR may have the low bit set, but
1086 a valid PC never does. */
1087 if (prev_regnum == ARM_PC_REGNUM)
1091 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1092 return frame_unwind_got_constant (this_frame, prev_regnum,
1093 arm_addr_bits_remove (lr));
1096 /* SP is generally not saved to the stack, but this frame is
1097 identified by the next frame's stack pointer at the time of the call.
1098 The value was already reconstructed into PREV_SP. */
1099 if (prev_regnum == ARM_SP_REGNUM)
1100 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1102 /* The CPSR may have been changed by the call instruction and by the
1103 called function. The only bit we can reconstruct is the T bit,
1104 by checking the low bit of LR as of the call. This is a reliable
1105 indicator of Thumb-ness except for some ARM v4T pre-interworking
1106 Thumb code, which could get away with a clear low bit as long as
1107 the called function did not use bx. Guess that all other
1108 bits are unchanged; the condition flags are presumably lost,
1109 but the processor status is likely valid. */
1110 if (prev_regnum == ARM_PS_REGNUM)
1114 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1115 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1116 if (IS_THUMB_ADDR (lr))
1120 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1123 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1127 struct frame_unwind arm_prologue_unwind = {
1129 arm_prologue_this_id,
1130 arm_prologue_prev_register,
1132 default_frame_sniffer
1135 static struct arm_prologue_cache *
1136 arm_make_stub_cache (struct frame_info *this_frame)
1139 struct arm_prologue_cache *cache;
1140 CORE_ADDR unwound_fp;
1142 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1143 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1145 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
1150 /* Our frame ID for a stub frame is the current SP and LR. */
1153 arm_stub_this_id (struct frame_info *this_frame,
1155 struct frame_id *this_id)
1157 struct arm_prologue_cache *cache;
1159 if (*this_cache == NULL)
1160 *this_cache = arm_make_stub_cache (this_frame);
1161 cache = *this_cache;
1163 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
1167 arm_stub_unwind_sniffer (const struct frame_unwind *self,
1168 struct frame_info *this_frame,
1169 void **this_prologue_cache)
1171 CORE_ADDR addr_in_block;
1174 addr_in_block = get_frame_address_in_block (this_frame);
1175 if (in_plt_section (addr_in_block, NULL)
1176 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1182 struct frame_unwind arm_stub_unwind = {
1185 arm_prologue_prev_register,
1187 arm_stub_unwind_sniffer
1191 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1193 struct arm_prologue_cache *cache;
1195 if (*this_cache == NULL)
1196 *this_cache = arm_make_prologue_cache (this_frame);
1197 cache = *this_cache;
1199 return cache->prev_sp - cache->framesize;
1202 struct frame_base arm_normal_base = {
1203 &arm_prologue_unwind,
1204 arm_normal_frame_base,
1205 arm_normal_frame_base,
1206 arm_normal_frame_base
1209 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1210 dummy frame. The frame ID's base needs to match the TOS value
1211 saved by save_dummy_frame_tos() and returned from
1212 arm_push_dummy_call, and the PC needs to match the dummy frame's
1215 static struct frame_id
1216 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1218 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1219 get_frame_pc (this_frame));
1222 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1223 be used to construct the previous frame's ID, after looking up the
1224 containing function). */
1227 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1230 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1231 return arm_addr_bits_remove (pc);
1235 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1237 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1240 static struct value *
1241 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1249 /* The PC is normally copied from the return column, which
1250 describes saves of LR. However, that version may have an
1251 extra bit set to indicate Thumb state. The bit is not
1253 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1254 return frame_unwind_got_constant (this_frame, regnum,
1255 arm_addr_bits_remove (lr));
1258 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1259 cpsr = get_frame_register_unsigned (this_frame, regnum);
1260 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1261 if (IS_THUMB_ADDR (lr))
1265 return frame_unwind_got_constant (this_frame, regnum, cpsr);
1268 internal_error (__FILE__, __LINE__,
1269 _("Unexpected register %d"), regnum);
1274 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1275 struct dwarf2_frame_state_reg *reg,
1276 struct frame_info *this_frame)
1282 reg->how = DWARF2_FRAME_REG_FN;
1283 reg->loc.fn = arm_dwarf2_prev_register;
1286 reg->how = DWARF2_FRAME_REG_CFA;
1291 /* When arguments must be pushed onto the stack, they go on in reverse
1292 order. The code below implements a FILO (stack) to do this. */
1297 struct stack_item *prev;
1301 static struct stack_item *
1302 push_stack_item (struct stack_item *prev, void *contents, int len)
1304 struct stack_item *si;
1305 si = xmalloc (sizeof (struct stack_item));
1306 si->data = xmalloc (len);
1309 memcpy (si->data, contents, len);
1313 static struct stack_item *
1314 pop_stack_item (struct stack_item *si)
1316 struct stack_item *dead = si;
1324 /* Return the alignment (in bytes) of the given type. */
1327 arm_type_align (struct type *t)
1333 t = check_typedef (t);
1334 switch (TYPE_CODE (t))
1337 /* Should never happen. */
1338 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1342 case TYPE_CODE_ENUM:
1346 case TYPE_CODE_RANGE:
1347 case TYPE_CODE_BITSTRING:
1349 case TYPE_CODE_CHAR:
1350 case TYPE_CODE_BOOL:
1351 return TYPE_LENGTH (t);
1353 case TYPE_CODE_ARRAY:
1354 case TYPE_CODE_COMPLEX:
1355 /* TODO: What about vector types? */
1356 return arm_type_align (TYPE_TARGET_TYPE (t));
1358 case TYPE_CODE_STRUCT:
1359 case TYPE_CODE_UNION:
1361 for (n = 0; n < TYPE_NFIELDS (t); n++)
1363 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1371 /* We currently only support passing parameters in integer registers. This
1372 conforms with GCC's default model. Several other variants exist and
1373 we should probably support some of them based on the selected ABI. */
1376 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1377 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1378 struct value **args, CORE_ADDR sp, int struct_return,
1379 CORE_ADDR struct_addr)
1384 struct stack_item *si = NULL;
1386 /* Set the return address. For the ARM, the return breakpoint is
1387 always at BP_ADDR. */
1388 /* XXX Fix for Thumb. */
1389 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1391 /* Walk through the list of args and determine how large a temporary
1392 stack is required. Need to take care here as structs may be
1393 passed on the stack, and we have to to push them. */
1396 argreg = ARM_A1_REGNUM;
1399 /* The struct_return pointer occupies the first parameter
1400 passing register. */
1404 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1405 gdbarch_register_name (gdbarch, argreg),
1406 paddr (struct_addr));
1407 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1411 for (argnum = 0; argnum < nargs; argnum++)
1414 struct type *arg_type;
1415 struct type *target_type;
1416 enum type_code typecode;
1420 arg_type = check_typedef (value_type (args[argnum]));
1421 len = TYPE_LENGTH (arg_type);
1422 target_type = TYPE_TARGET_TYPE (arg_type);
1423 typecode = TYPE_CODE (arg_type);
1424 val = value_contents_writeable (args[argnum]);
1426 align = arm_type_align (arg_type);
1427 /* Round alignment up to a whole number of words. */
1428 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1429 /* Different ABIs have different maximum alignments. */
1430 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1432 /* The APCS ABI only requires word alignment. */
1433 align = INT_REGISTER_SIZE;
1437 /* The AAPCS requires at most doubleword alignment. */
1438 if (align > INT_REGISTER_SIZE * 2)
1439 align = INT_REGISTER_SIZE * 2;
1442 /* Push stack padding for dowubleword alignment. */
1443 if (nstack & (align - 1))
1445 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1446 nstack += INT_REGISTER_SIZE;
1449 /* Doubleword aligned quantities must go in even register pairs. */
1450 if (argreg <= ARM_LAST_ARG_REGNUM
1451 && align > INT_REGISTER_SIZE
1455 /* If the argument is a pointer to a function, and it is a
1456 Thumb function, create a LOCAL copy of the value and set
1457 the THUMB bit in it. */
1458 if (TYPE_CODE_PTR == typecode
1459 && target_type != NULL
1460 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1462 CORE_ADDR regval = extract_unsigned_integer (val, len);
1463 if (arm_pc_is_thumb (regval))
1466 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1470 /* Copy the argument to general registers or the stack in
1471 register-sized pieces. Large arguments are split between
1472 registers and stack. */
1475 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1477 if (argreg <= ARM_LAST_ARG_REGNUM)
1479 /* The argument is being passed in a general purpose
1481 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1482 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1483 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1485 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1487 gdbarch_register_name
1489 phex (regval, INT_REGISTER_SIZE));
1490 regcache_cooked_write_unsigned (regcache, argreg, regval);
1495 /* Push the arguments onto the stack. */
1497 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1499 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1500 nstack += INT_REGISTER_SIZE;
1507 /* If we have an odd number of words to push, then decrement the stack
1508 by one word now, so first stack argument will be dword aligned. */
1515 write_memory (sp, si->data, si->len);
1516 si = pop_stack_item (si);
1519 /* Finally, update teh SP register. */
1520 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1526 /* Always align the frame to an 8-byte boundary. This is required on
1527 some platforms and harmless on the rest. */
1530 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1532 /* Align the stack to eight bytes. */
1533 return sp & ~ (CORE_ADDR) 7;
1537 print_fpu_flags (int flags)
1539 if (flags & (1 << 0))
1540 fputs ("IVO ", stdout);
1541 if (flags & (1 << 1))
1542 fputs ("DVZ ", stdout);
1543 if (flags & (1 << 2))
1544 fputs ("OFL ", stdout);
1545 if (flags & (1 << 3))
1546 fputs ("UFL ", stdout);
1547 if (flags & (1 << 4))
1548 fputs ("INX ", stdout);
1552 /* Print interesting information about the floating point processor
1553 (if present) or emulator. */
1555 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1556 struct frame_info *frame, const char *args)
1558 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1561 type = (status >> 24) & 127;
1562 if (status & (1 << 31))
1563 printf (_("Hardware FPU type %d\n"), type);
1565 printf (_("Software FPU type %d\n"), type);
1566 /* i18n: [floating point unit] mask */
1567 fputs (_("mask: "), stdout);
1568 print_fpu_flags (status >> 16);
1569 /* i18n: [floating point unit] flags */
1570 fputs (_("flags: "), stdout);
1571 print_fpu_flags (status);
1574 /* Return the GDB type object for the "standard" data type of data in
1577 static struct type *
1578 arm_register_type (struct gdbarch *gdbarch, int regnum)
1580 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1581 return builtin_type_arm_ext;
1582 else if (regnum == ARM_SP_REGNUM)
1583 return builtin_type_void_data_ptr;
1584 else if (regnum == ARM_PC_REGNUM)
1585 return builtin_type_void_func_ptr;
1586 else if (regnum >= ARRAY_SIZE (arm_register_names))
1587 /* These registers are only supported on targets which supply
1588 an XML description. */
1589 return builtin_type_int0;
1591 return builtin_type_uint32;
1594 /* Map a DWARF register REGNUM onto the appropriate GDB register
1598 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1600 /* Core integer regs. */
1601 if (reg >= 0 && reg <= 15)
1604 /* Legacy FPA encoding. These were once used in a way which
1605 overlapped with VFP register numbering, so their use is
1606 discouraged, but GDB doesn't support the ARM toolchain
1607 which used them for VFP. */
1608 if (reg >= 16 && reg <= 23)
1609 return ARM_F0_REGNUM + reg - 16;
1611 /* New assignments for the FPA registers. */
1612 if (reg >= 96 && reg <= 103)
1613 return ARM_F0_REGNUM + reg - 96;
1615 /* WMMX register assignments. */
1616 if (reg >= 104 && reg <= 111)
1617 return ARM_WCGR0_REGNUM + reg - 104;
1619 if (reg >= 112 && reg <= 127)
1620 return ARM_WR0_REGNUM + reg - 112;
1622 if (reg >= 192 && reg <= 199)
1623 return ARM_WC0_REGNUM + reg - 192;
1628 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1630 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1633 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
1635 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1636 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1638 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1639 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1641 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1642 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1644 if (reg < NUM_GREGS)
1645 return SIM_ARM_R0_REGNUM + reg;
1648 if (reg < NUM_FREGS)
1649 return SIM_ARM_FP0_REGNUM + reg;
1652 if (reg < NUM_SREGS)
1653 return SIM_ARM_FPS_REGNUM + reg;
1656 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1659 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1660 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1661 It is thought that this is is the floating-point register format on
1662 little-endian systems. */
1665 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1666 void *dbl, int endianess)
1670 if (endianess == BFD_ENDIAN_BIG)
1671 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1673 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1675 floatformat_from_doublest (fmt, &d, dbl);
1679 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1684 floatformat_to_doublest (fmt, ptr, &d);
1685 if (endianess == BFD_ENDIAN_BIG)
1686 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1688 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1693 condition_true (unsigned long cond, unsigned long status_reg)
1695 if (cond == INST_AL || cond == INST_NV)
1701 return ((status_reg & FLAG_Z) != 0);
1703 return ((status_reg & FLAG_Z) == 0);
1705 return ((status_reg & FLAG_C) != 0);
1707 return ((status_reg & FLAG_C) == 0);
1709 return ((status_reg & FLAG_N) != 0);
1711 return ((status_reg & FLAG_N) == 0);
1713 return ((status_reg & FLAG_V) != 0);
1715 return ((status_reg & FLAG_V) == 0);
1717 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1719 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1721 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1723 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1725 return (((status_reg & FLAG_Z) == 0) &&
1726 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1728 return (((status_reg & FLAG_Z) != 0) ||
1729 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1734 /* Support routines for single stepping. Calculate the next PC value. */
1735 #define submask(x) ((1L << ((x) + 1)) - 1)
1736 #define bit(obj,st) (((obj) >> (st)) & 1)
1737 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1738 #define sbits(obj,st,fn) \
1739 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1740 #define BranchDest(addr,instr) \
1741 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1744 static unsigned long
1745 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1746 unsigned long pc_val, unsigned long status_reg)
1748 unsigned long res, shift;
1749 int rm = bits (inst, 0, 3);
1750 unsigned long shifttype = bits (inst, 5, 6);
1754 int rs = bits (inst, 8, 11);
1755 shift = (rs == 15 ? pc_val + 8
1756 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1759 shift = bits (inst, 7, 11);
1762 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1763 + (bit (inst, 4) ? 12 : 8))
1764 : get_frame_register_unsigned (frame, rm));
1769 res = shift >= 32 ? 0 : res << shift;
1773 res = shift >= 32 ? 0 : res >> shift;
1779 res = ((res & 0x80000000L)
1780 ? ~((~res) >> shift) : res >> shift);
1783 case 3: /* ROR/RRX */
1786 res = (res >> 1) | (carry ? 0x80000000L : 0);
1788 res = (res >> shift) | (res << (32 - shift));
1792 return res & 0xffffffff;
1795 /* Return number of 1-bits in VAL. */
1798 bitcount (unsigned long val)
1801 for (nbits = 0; val != 0; nbits++)
1802 val &= val - 1; /* delete rightmost 1-bit in val */
1807 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1809 struct gdbarch *gdbarch = get_frame_arch (frame);
1810 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1811 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1812 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1813 unsigned long offset;
1815 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1819 /* Fetch the saved PC from the stack. It's stored above
1820 all of the other registers. */
1821 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1822 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1823 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1824 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1826 error (_("Infinite loop detected"));
1828 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1830 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1831 unsigned long cond = bits (inst1, 8, 11);
1832 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1833 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1835 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1837 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1839 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1841 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1842 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1843 nextpc = pc_val + offset;
1844 /* For BLX make sure to clear the low bits. */
1845 if (bits (inst2, 11, 12) == 1)
1846 nextpc = nextpc & 0xfffffffc;
1848 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1850 if (bits (inst1, 3, 6) == 0x0f)
1853 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1855 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1857 error (_("Infinite loop detected"));
1864 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1866 struct gdbarch *gdbarch = get_frame_arch (frame);
1867 unsigned long pc_val;
1868 unsigned long this_instr;
1869 unsigned long status;
1872 if (arm_frame_is_thumb (frame))
1873 return thumb_get_next_pc (frame, pc);
1875 pc_val = (unsigned long) pc;
1876 this_instr = read_memory_unsigned_integer (pc, 4);
1877 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1878 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1880 if (bits (this_instr, 28, 31) == INST_NV)
1881 switch (bits (this_instr, 24, 27))
1886 /* Branch with Link and change to Thumb. */
1887 nextpc = BranchDest (pc, this_instr);
1888 nextpc |= bit (this_instr, 24) << 1;
1890 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1892 error (_("Infinite loop detected"));
1898 /* Coprocessor register transfer. */
1899 if (bits (this_instr, 12, 15) == 15)
1900 error (_("Invalid update to pc in instruction"));
1903 else if (condition_true (bits (this_instr, 28, 31), status))
1905 switch (bits (this_instr, 24, 27))
1908 case 0x1: /* data processing */
1912 unsigned long operand1, operand2, result = 0;
1916 if (bits (this_instr, 12, 15) != 15)
1919 if (bits (this_instr, 22, 25) == 0
1920 && bits (this_instr, 4, 7) == 9) /* multiply */
1921 error (_("Invalid update to pc in instruction"));
1923 /* BX <reg>, BLX <reg> */
1924 if (bits (this_instr, 4, 27) == 0x12fff1
1925 || bits (this_instr, 4, 27) == 0x12fff3)
1927 rn = bits (this_instr, 0, 3);
1928 result = (rn == 15) ? pc_val + 8
1929 : get_frame_register_unsigned (frame, rn);
1930 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1934 error (_("Infinite loop detected"));
1939 /* Multiply into PC */
1940 c = (status & FLAG_C) ? 1 : 0;
1941 rn = bits (this_instr, 16, 19);
1942 operand1 = (rn == 15) ? pc_val + 8
1943 : get_frame_register_unsigned (frame, rn);
1945 if (bit (this_instr, 25))
1947 unsigned long immval = bits (this_instr, 0, 7);
1948 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1949 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1952 else /* operand 2 is a shifted register */
1953 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1955 switch (bits (this_instr, 21, 24))
1958 result = operand1 & operand2;
1962 result = operand1 ^ operand2;
1966 result = operand1 - operand2;
1970 result = operand2 - operand1;
1974 result = operand1 + operand2;
1978 result = operand1 + operand2 + c;
1982 result = operand1 - operand2 + c;
1986 result = operand2 - operand1 + c;
1992 case 0xb: /* tst, teq, cmp, cmn */
1993 result = (unsigned long) nextpc;
1997 result = operand1 | operand2;
2001 /* Always step into a function. */
2006 result = operand1 & ~operand2;
2013 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2017 error (_("Infinite loop detected"));
2022 case 0x5: /* data transfer */
2025 if (bit (this_instr, 20))
2028 if (bits (this_instr, 12, 15) == 15)
2034 if (bit (this_instr, 22))
2035 error (_("Invalid update to pc in instruction"));
2037 /* byte write to PC */
2038 rn = bits (this_instr, 16, 19);
2039 base = (rn == 15) ? pc_val + 8
2040 : get_frame_register_unsigned (frame, rn);
2041 if (bit (this_instr, 24))
2044 int c = (status & FLAG_C) ? 1 : 0;
2045 unsigned long offset =
2046 (bit (this_instr, 25)
2047 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
2048 : bits (this_instr, 0, 11));
2050 if (bit (this_instr, 23))
2055 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
2058 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2061 error (_("Infinite loop detected"));
2067 case 0x9: /* block transfer */
2068 if (bit (this_instr, 20))
2071 if (bit (this_instr, 15))
2076 if (bit (this_instr, 23))
2079 unsigned long reglist = bits (this_instr, 0, 14);
2080 offset = bitcount (reglist) * 4;
2081 if (bit (this_instr, 24)) /* pre */
2084 else if (bit (this_instr, 24))
2088 unsigned long rn_val =
2089 get_frame_register_unsigned (frame,
2090 bits (this_instr, 16, 19));
2092 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2096 nextpc = gdbarch_addr_bits_remove
2099 error (_("Infinite loop detected"));
2104 case 0xb: /* branch & link */
2105 case 0xa: /* branch */
2107 nextpc = BranchDest (pc, this_instr);
2109 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2111 error (_("Infinite loop detected"));
2117 case 0xe: /* coproc ops */
2122 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
2130 /* single_step() is called just before we want to resume the inferior,
2131 if we want to single-step it but there is no hardware or kernel
2132 single-step support. We find the target of the coming instruction
2133 and breakpoint it. */
2136 arm_software_single_step (struct frame_info *frame)
2138 /* NOTE: This may insert the wrong breakpoint instruction when
2139 single-stepping over a mode-changing instruction, if the
2140 CPSR heuristics are used. */
2142 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
2143 insert_single_step_breakpoint (next_pc);
2148 #include "bfd-in2.h"
2149 #include "libcoff.h"
2152 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2154 if (arm_pc_is_thumb (memaddr))
2156 static asymbol *asym;
2157 static combined_entry_type ce;
2158 static struct coff_symbol_struct csym;
2159 static struct bfd fake_bfd;
2160 static bfd_target fake_target;
2162 if (csym.native == NULL)
2164 /* Create a fake symbol vector containing a Thumb symbol.
2165 This is solely so that the code in print_insn_little_arm()
2166 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2167 the presence of a Thumb symbol and switch to decoding
2168 Thumb instructions. */
2170 fake_target.flavour = bfd_target_coff_flavour;
2171 fake_bfd.xvec = &fake_target;
2172 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2174 csym.symbol.the_bfd = &fake_bfd;
2175 csym.symbol.name = "fake";
2176 asym = (asymbol *) & csym;
2179 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2180 info->symbols = &asym;
2183 info->symbols = NULL;
2185 if (info->endian == BFD_ENDIAN_BIG)
2186 return print_insn_big_arm (memaddr, info);
2188 return print_insn_little_arm (memaddr, info);
2191 /* The following define instruction sequences that will cause ARM
2192 cpu's to take an undefined instruction trap. These are used to
2193 signal a breakpoint to GDB.
2195 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2196 modes. A different instruction is required for each mode. The ARM
2197 cpu's can also be big or little endian. Thus four different
2198 instructions are needed to support all cases.
2200 Note: ARMv4 defines several new instructions that will take the
2201 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2202 not in fact add the new instructions. The new undefined
2203 instructions in ARMv4 are all instructions that had no defined
2204 behaviour in earlier chips. There is no guarantee that they will
2205 raise an exception, but may be treated as NOP's. In practice, it
2206 may only safe to rely on instructions matching:
2208 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2209 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2210 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2212 Even this may only true if the condition predicate is true. The
2213 following use a condition predicate of ALWAYS so it is always TRUE.
2215 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2216 and NetBSD all use a software interrupt rather than an undefined
2217 instruction to force a trap. This can be handled by by the
2218 abi-specific code during establishment of the gdbarch vector. */
2220 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2221 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2222 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2223 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2225 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2226 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2227 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2228 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2230 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2231 the program counter value to determine whether a 16-bit or 32-bit
2232 breakpoint should be used. It returns a pointer to a string of
2233 bytes that encode a breakpoint instruction, stores the length of
2234 the string to *lenptr, and adjusts the program counter (if
2235 necessary) to point to the actual memory location where the
2236 breakpoint should be inserted. */
2238 static const unsigned char *
2239 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
2241 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2243 if (arm_pc_is_thumb (*pcptr))
2245 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2246 *lenptr = tdep->thumb_breakpoint_size;
2247 return tdep->thumb_breakpoint;
2251 *lenptr = tdep->arm_breakpoint_size;
2252 return tdep->arm_breakpoint;
2256 /* Extract from an array REGBUF containing the (raw) register state a
2257 function return value of type TYPE, and copy that, in virtual
2258 format, into VALBUF. */
2261 arm_extract_return_value (struct type *type, struct regcache *regs,
2264 struct gdbarch *gdbarch = get_regcache_arch (regs);
2266 if (TYPE_CODE_FLT == TYPE_CODE (type))
2268 switch (gdbarch_tdep (gdbarch)->fp_model)
2272 /* The value is in register F0 in internal format. We need to
2273 extract the raw value and then convert it to the desired
2275 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2277 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2278 convert_from_extended (floatformat_from_type (type), tmpbuf,
2279 valbuf, gdbarch_byte_order (gdbarch));
2283 case ARM_FLOAT_SOFT_FPA:
2284 case ARM_FLOAT_SOFT_VFP:
2285 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2286 if (TYPE_LENGTH (type) > 4)
2287 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2288 valbuf + INT_REGISTER_SIZE);
2293 (__FILE__, __LINE__,
2294 _("arm_extract_return_value: Floating point model not supported"));
2298 else if (TYPE_CODE (type) == TYPE_CODE_INT
2299 || TYPE_CODE (type) == TYPE_CODE_CHAR
2300 || TYPE_CODE (type) == TYPE_CODE_BOOL
2301 || TYPE_CODE (type) == TYPE_CODE_PTR
2302 || TYPE_CODE (type) == TYPE_CODE_REF
2303 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2305 /* If the the type is a plain integer, then the access is
2306 straight-forward. Otherwise we have to play around a bit more. */
2307 int len = TYPE_LENGTH (type);
2308 int regno = ARM_A1_REGNUM;
2313 /* By using store_unsigned_integer we avoid having to do
2314 anything special for small big-endian values. */
2315 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2316 store_unsigned_integer (valbuf,
2317 (len > INT_REGISTER_SIZE
2318 ? INT_REGISTER_SIZE : len),
2320 len -= INT_REGISTER_SIZE;
2321 valbuf += INT_REGISTER_SIZE;
2326 /* For a structure or union the behaviour is as if the value had
2327 been stored to word-aligned memory and then loaded into
2328 registers with 32-bit load instruction(s). */
2329 int len = TYPE_LENGTH (type);
2330 int regno = ARM_A1_REGNUM;
2331 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2335 regcache_cooked_read (regs, regno++, tmpbuf);
2336 memcpy (valbuf, tmpbuf,
2337 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2338 len -= INT_REGISTER_SIZE;
2339 valbuf += INT_REGISTER_SIZE;
2345 /* Will a function return an aggregate type in memory or in a
2346 register? Return 0 if an aggregate type can be returned in a
2347 register, 1 if it must be returned in memory. */
2350 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2353 enum type_code code;
2355 CHECK_TYPEDEF (type);
2357 /* In the ARM ABI, "integer" like aggregate types are returned in
2358 registers. For an aggregate type to be integer like, its size
2359 must be less than or equal to INT_REGISTER_SIZE and the
2360 offset of each addressable subfield must be zero. Note that bit
2361 fields are not addressable, and all addressable subfields of
2362 unions always start at offset zero.
2364 This function is based on the behaviour of GCC 2.95.1.
2365 See: gcc/arm.c: arm_return_in_memory() for details.
2367 Note: All versions of GCC before GCC 2.95.2 do not set up the
2368 parameters correctly for a function returning the following
2369 structure: struct { float f;}; This should be returned in memory,
2370 not a register. Richard Earnshaw sent me a patch, but I do not
2371 know of any way to detect if a function like the above has been
2372 compiled with the correct calling convention. */
2374 /* All aggregate types that won't fit in a register must be returned
2376 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2381 /* The AAPCS says all aggregates not larger than a word are returned
2383 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2386 /* The only aggregate types that can be returned in a register are
2387 structs and unions. Arrays must be returned in memory. */
2388 code = TYPE_CODE (type);
2389 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2394 /* Assume all other aggregate types can be returned in a register.
2395 Run a check for structures, unions and arrays. */
2398 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2401 /* Need to check if this struct/union is "integer" like. For
2402 this to be true, its size must be less than or equal to
2403 INT_REGISTER_SIZE and the offset of each addressable
2404 subfield must be zero. Note that bit fields are not
2405 addressable, and unions always start at offset zero. If any
2406 of the subfields is a floating point type, the struct/union
2407 cannot be an integer type. */
2409 /* For each field in the object, check:
2410 1) Is it FP? --> yes, nRc = 1;
2411 2) Is it addressable (bitpos != 0) and
2412 not packed (bitsize == 0)?
2416 for (i = 0; i < TYPE_NFIELDS (type); i++)
2418 enum type_code field_type_code;
2419 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2421 /* Is it a floating point type field? */
2422 if (field_type_code == TYPE_CODE_FLT)
2428 /* If bitpos != 0, then we have to care about it. */
2429 if (TYPE_FIELD_BITPOS (type, i) != 0)
2431 /* Bitfields are not addressable. If the field bitsize is
2432 zero, then the field is not packed. Hence it cannot be
2433 a bitfield or any other packed type. */
2434 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2446 /* Write into appropriate registers a function return value of type
2447 TYPE, given in virtual format. */
2450 arm_store_return_value (struct type *type, struct regcache *regs,
2451 const gdb_byte *valbuf)
2453 struct gdbarch *gdbarch = get_regcache_arch (regs);
2455 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2457 char buf[MAX_REGISTER_SIZE];
2459 switch (gdbarch_tdep (gdbarch)->fp_model)
2463 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2464 gdbarch_byte_order (gdbarch));
2465 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2468 case ARM_FLOAT_SOFT_FPA:
2469 case ARM_FLOAT_SOFT_VFP:
2470 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2471 if (TYPE_LENGTH (type) > 4)
2472 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2473 valbuf + INT_REGISTER_SIZE);
2478 (__FILE__, __LINE__,
2479 _("arm_store_return_value: Floating point model not supported"));
2483 else if (TYPE_CODE (type) == TYPE_CODE_INT
2484 || TYPE_CODE (type) == TYPE_CODE_CHAR
2485 || TYPE_CODE (type) == TYPE_CODE_BOOL
2486 || TYPE_CODE (type) == TYPE_CODE_PTR
2487 || TYPE_CODE (type) == TYPE_CODE_REF
2488 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2490 if (TYPE_LENGTH (type) <= 4)
2492 /* Values of one word or less are zero/sign-extended and
2494 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2495 LONGEST val = unpack_long (type, valbuf);
2497 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2498 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2502 /* Integral values greater than one word are stored in consecutive
2503 registers starting with r0. This will always be a multiple of
2504 the regiser size. */
2505 int len = TYPE_LENGTH (type);
2506 int regno = ARM_A1_REGNUM;
2510 regcache_cooked_write (regs, regno++, valbuf);
2511 len -= INT_REGISTER_SIZE;
2512 valbuf += INT_REGISTER_SIZE;
2518 /* For a structure or union the behaviour is as if the value had
2519 been stored to word-aligned memory and then loaded into
2520 registers with 32-bit load instruction(s). */
2521 int len = TYPE_LENGTH (type);
2522 int regno = ARM_A1_REGNUM;
2523 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2527 memcpy (tmpbuf, valbuf,
2528 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2529 regcache_cooked_write (regs, regno++, tmpbuf);
2530 len -= INT_REGISTER_SIZE;
2531 valbuf += INT_REGISTER_SIZE;
2537 /* Handle function return values. */
2539 static enum return_value_convention
2540 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2541 struct type *valtype, struct regcache *regcache,
2542 gdb_byte *readbuf, const gdb_byte *writebuf)
2544 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2546 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2547 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2548 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2550 if (tdep->struct_return == pcc_struct_return
2551 || arm_return_in_memory (gdbarch, valtype))
2552 return RETURN_VALUE_STRUCT_CONVENTION;
2556 arm_store_return_value (valtype, regcache, writebuf);
2559 arm_extract_return_value (valtype, regcache, readbuf);
2561 return RETURN_VALUE_REGISTER_CONVENTION;
2566 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2569 char buf[INT_REGISTER_SIZE];
2570 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2572 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2574 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2578 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2582 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2583 return the target PC. Otherwise return 0. */
2586 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2590 CORE_ADDR start_addr;
2592 /* Find the starting address and name of the function containing the PC. */
2593 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2596 /* If PC is in a Thumb call or return stub, return the address of the
2597 target PC, which is in a register. The thunk functions are called
2598 _call_via_xx, where x is the register name. The possible names
2599 are r0-r9, sl, fp, ip, sp, and lr. */
2600 if (strncmp (name, "_call_via_", 10) == 0)
2602 /* Use the name suffix to determine which register contains the
2604 static char *table[15] =
2605 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2606 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2609 int offset = strlen (name) - 2;
2611 for (regno = 0; regno <= 14; regno++)
2612 if (strcmp (&name[offset], table[regno]) == 0)
2613 return get_frame_register_unsigned (frame, regno);
2616 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2617 non-interworking calls to foo. We could decode the stubs
2618 to find the target but it's easier to use the symbol table. */
2619 namelen = strlen (name);
2620 if (name[0] == '_' && name[1] == '_'
2621 && ((namelen > 2 + strlen ("_from_thumb")
2622 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2623 strlen ("_from_thumb")) == 0)
2624 || (namelen > 2 + strlen ("_from_arm")
2625 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2626 strlen ("_from_arm")) == 0)))
2629 int target_len = namelen - 2;
2630 struct minimal_symbol *minsym;
2631 struct objfile *objfile;
2632 struct obj_section *sec;
2634 if (name[namelen - 1] == 'b')
2635 target_len -= strlen ("_from_thumb");
2637 target_len -= strlen ("_from_arm");
2639 target_name = alloca (target_len + 1);
2640 memcpy (target_name, name + 2, target_len);
2641 target_name[target_len] = '\0';
2643 sec = find_pc_section (pc);
2644 objfile = (sec == NULL) ? NULL : sec->objfile;
2645 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2647 return SYMBOL_VALUE_ADDRESS (minsym);
2652 return 0; /* not a stub */
2656 set_arm_command (char *args, int from_tty)
2658 printf_unfiltered (_("\
2659 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2660 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2664 show_arm_command (char *args, int from_tty)
2666 cmd_show_list (showarmcmdlist, from_tty, "");
2670 arm_update_current_architecture (void)
2672 struct gdbarch_info info;
2674 /* If the current architecture is not ARM, we have nothing to do. */
2675 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2678 /* Update the architecture. */
2679 gdbarch_info_init (&info);
2681 if (!gdbarch_update_p (info))
2682 internal_error (__FILE__, __LINE__, "could not update architecture");
2686 set_fp_model_sfunc (char *args, int from_tty,
2687 struct cmd_list_element *c)
2689 enum arm_float_model fp_model;
2691 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2692 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2694 arm_fp_model = fp_model;
2698 if (fp_model == ARM_FLOAT_LAST)
2699 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2702 arm_update_current_architecture ();
2706 show_fp_model (struct ui_file *file, int from_tty,
2707 struct cmd_list_element *c, const char *value)
2709 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2711 if (arm_fp_model == ARM_FLOAT_AUTO
2712 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2713 fprintf_filtered (file, _("\
2714 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2715 fp_model_strings[tdep->fp_model]);
2717 fprintf_filtered (file, _("\
2718 The current ARM floating point model is \"%s\".\n"),
2719 fp_model_strings[arm_fp_model]);
2723 arm_set_abi (char *args, int from_tty,
2724 struct cmd_list_element *c)
2726 enum arm_abi_kind arm_abi;
2728 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2729 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2731 arm_abi_global = arm_abi;
2735 if (arm_abi == ARM_ABI_LAST)
2736 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2739 arm_update_current_architecture ();
2743 arm_show_abi (struct ui_file *file, int from_tty,
2744 struct cmd_list_element *c, const char *value)
2746 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2748 if (arm_abi_global == ARM_ABI_AUTO
2749 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2750 fprintf_filtered (file, _("\
2751 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2752 arm_abi_strings[tdep->arm_abi]);
2754 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2759 arm_show_fallback_mode (struct ui_file *file, int from_tty,
2760 struct cmd_list_element *c, const char *value)
2762 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2764 fprintf_filtered (file, _("\
2765 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2766 arm_fallback_mode_string);
2770 arm_show_force_mode (struct ui_file *file, int from_tty,
2771 struct cmd_list_element *c, const char *value)
2773 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2775 fprintf_filtered (file, _("\
2776 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2777 arm_force_mode_string);
2780 /* If the user changes the register disassembly style used for info
2781 register and other commands, we have to also switch the style used
2782 in opcodes for disassembly output. This function is run in the "set
2783 arm disassembly" command, and does that. */
2786 set_disassembly_style_sfunc (char *args, int from_tty,
2787 struct cmd_list_element *c)
2789 set_disassembly_style ();
2792 /* Return the ARM register name corresponding to register I. */
2794 arm_register_name (struct gdbarch *gdbarch, int i)
2796 if (i >= ARRAY_SIZE (arm_register_names))
2797 /* These registers are only supported on targets which supply
2798 an XML description. */
2801 return arm_register_names[i];
2805 set_disassembly_style (void)
2809 /* Find the style that the user wants. */
2810 for (current = 0; current < num_disassembly_options; current++)
2811 if (disassembly_style == valid_disassembly_styles[current])
2813 gdb_assert (current < num_disassembly_options);
2815 /* Synchronize the disassembler. */
2816 set_arm_regname_option (current);
2819 /* Test whether the coff symbol specific value corresponds to a Thumb
2823 coff_sym_is_thumb (int val)
2825 return (val == C_THUMBEXT ||
2826 val == C_THUMBSTAT ||
2827 val == C_THUMBEXTFUNC ||
2828 val == C_THUMBSTATFUNC ||
2829 val == C_THUMBLABEL);
2832 /* arm_coff_make_msymbol_special()
2833 arm_elf_make_msymbol_special()
2835 These functions test whether the COFF or ELF symbol corresponds to
2836 an address in thumb code, and set a "special" bit in a minimal
2837 symbol to indicate that it does. */
2840 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2842 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2844 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2846 MSYMBOL_SET_SPECIAL (msym);
2850 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2852 if (coff_sym_is_thumb (val))
2853 MSYMBOL_SET_SPECIAL (msym);
2857 arm_objfile_data_cleanup (struct objfile *objfile, void *arg)
2859 struct arm_per_objfile *data = arg;
2862 for (i = 0; i < objfile->obfd->section_count; i++)
2863 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
2867 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
2870 const char *name = bfd_asymbol_name (sym);
2871 struct arm_per_objfile *data;
2872 VEC(arm_mapping_symbol_s) **map_p;
2873 struct arm_mapping_symbol new_map_sym;
2875 gdb_assert (name[0] == '$');
2876 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
2879 data = objfile_data (objfile, arm_objfile_data_key);
2882 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
2883 struct arm_per_objfile);
2884 set_objfile_data (objfile, arm_objfile_data_key, data);
2885 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2886 objfile->obfd->section_count,
2887 VEC(arm_mapping_symbol_s) *);
2889 map_p = &data->section_maps[bfd_get_section (sym)->index];
2891 new_map_sym.value = sym->value;
2892 new_map_sym.type = name[1];
2894 /* Assume that most mapping symbols appear in order of increasing
2895 value. If they were randomly distributed, it would be faster to
2896 always push here and then sort at first use. */
2897 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
2899 struct arm_mapping_symbol *prev_map_sym;
2901 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
2902 if (prev_map_sym->value >= sym->value)
2905 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
2906 arm_compare_mapping_symbols);
2907 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
2912 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
2916 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2918 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2920 /* If necessary, set the T bit. */
2924 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2925 if (arm_pc_is_thumb (pc))
2926 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
2928 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2929 val & ~(ULONGEST) CPSR_T);
2933 static struct value *
2934 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2936 const int *reg_p = baton;
2937 return value_of_register (*reg_p, frame);
2940 static enum gdb_osabi
2941 arm_elf_osabi_sniffer (bfd *abfd)
2943 unsigned int elfosabi;
2944 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2946 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2948 if (elfosabi == ELFOSABI_ARM)
2949 /* GNU tools use this value. Check note sections in this case,
2951 bfd_map_over_sections (abfd,
2952 generic_elf_osabi_sniff_abi_tag_sections,
2955 /* Anything else will be handled by the generic ELF sniffer. */
2960 /* Initialize the current architecture based on INFO. If possible,
2961 re-use an architecture from ARCHES, which is a list of
2962 architectures already created during this debugging session.
2964 Called e.g. at program startup, when reading a core file, and when
2965 reading a binary file. */
2967 static struct gdbarch *
2968 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2970 struct gdbarch_tdep *tdep;
2971 struct gdbarch *gdbarch;
2972 struct gdbarch_list *best_arch;
2973 enum arm_abi_kind arm_abi = arm_abi_global;
2974 enum arm_float_model fp_model = arm_fp_model;
2975 struct tdesc_arch_data *tdesc_data = NULL;
2977 int have_fpa_registers = 1;
2979 /* Check any target description for validity. */
2980 if (tdesc_has_registers (info.target_desc))
2982 /* For most registers we require GDB's default names; but also allow
2983 the numeric names for sp / lr / pc, as a convenience. */
2984 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2985 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2986 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2988 const struct tdesc_feature *feature;
2991 feature = tdesc_find_feature (info.target_desc,
2992 "org.gnu.gdb.arm.core");
2993 if (feature == NULL)
2996 tdesc_data = tdesc_data_alloc ();
2999 for (i = 0; i < ARM_SP_REGNUM; i++)
3000 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3001 arm_register_names[i]);
3002 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3005 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3008 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3011 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3012 ARM_PS_REGNUM, "cpsr");
3016 tdesc_data_cleanup (tdesc_data);
3020 feature = tdesc_find_feature (info.target_desc,
3021 "org.gnu.gdb.arm.fpa");
3022 if (feature != NULL)
3025 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
3026 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3027 arm_register_names[i]);
3030 tdesc_data_cleanup (tdesc_data);
3035 have_fpa_registers = 0;
3037 feature = tdesc_find_feature (info.target_desc,
3038 "org.gnu.gdb.xscale.iwmmxt");
3039 if (feature != NULL)
3041 static const char *const iwmmxt_names[] = {
3042 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3043 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3044 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3045 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3049 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
3051 &= tdesc_numbered_register (feature, tdesc_data, i,
3052 iwmmxt_names[i - ARM_WR0_REGNUM]);
3054 /* Check for the control registers, but do not fail if they
3056 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
3057 tdesc_numbered_register (feature, tdesc_data, i,
3058 iwmmxt_names[i - ARM_WR0_REGNUM]);
3060 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
3062 &= tdesc_numbered_register (feature, tdesc_data, i,
3063 iwmmxt_names[i - ARM_WR0_REGNUM]);
3067 tdesc_data_cleanup (tdesc_data);
3073 /* If we have an object to base this architecture on, try to determine
3076 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
3078 int ei_osabi, e_flags;
3080 switch (bfd_get_flavour (info.abfd))
3082 case bfd_target_aout_flavour:
3083 /* Assume it's an old APCS-style ABI. */
3084 arm_abi = ARM_ABI_APCS;
3087 case bfd_target_coff_flavour:
3088 /* Assume it's an old APCS-style ABI. */
3090 arm_abi = ARM_ABI_APCS;
3093 case bfd_target_elf_flavour:
3094 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
3095 e_flags = elf_elfheader (info.abfd)->e_flags;
3097 if (ei_osabi == ELFOSABI_ARM)
3099 /* GNU tools used to use this value, but do not for EABI
3100 objects. There's nowhere to tag an EABI version
3101 anyway, so assume APCS. */
3102 arm_abi = ARM_ABI_APCS;
3104 else if (ei_osabi == ELFOSABI_NONE)
3106 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
3110 case EF_ARM_EABI_UNKNOWN:
3111 /* Assume GNU tools. */
3112 arm_abi = ARM_ABI_APCS;
3115 case EF_ARM_EABI_VER4:
3116 case EF_ARM_EABI_VER5:
3117 arm_abi = ARM_ABI_AAPCS;
3118 /* EABI binaries default to VFP float ordering. */
3119 if (fp_model == ARM_FLOAT_AUTO)
3120 fp_model = ARM_FLOAT_SOFT_VFP;
3124 /* Leave it as "auto". */
3125 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
3130 if (fp_model == ARM_FLOAT_AUTO)
3132 int e_flags = elf_elfheader (info.abfd)->e_flags;
3134 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
3137 /* Leave it as "auto". Strictly speaking this case
3138 means FPA, but almost nobody uses that now, and
3139 many toolchains fail to set the appropriate bits
3140 for the floating-point model they use. */
3142 case EF_ARM_SOFT_FLOAT:
3143 fp_model = ARM_FLOAT_SOFT_FPA;
3145 case EF_ARM_VFP_FLOAT:
3146 fp_model = ARM_FLOAT_VFP;
3148 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
3149 fp_model = ARM_FLOAT_SOFT_VFP;
3156 /* Leave it as "auto". */
3161 /* If there is already a candidate, use it. */
3162 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3164 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3166 if (arm_abi != ARM_ABI_AUTO
3167 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
3170 if (fp_model != ARM_FLOAT_AUTO
3171 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
3174 /* Found a match. */
3178 if (best_arch != NULL)
3180 if (tdesc_data != NULL)
3181 tdesc_data_cleanup (tdesc_data);
3182 return best_arch->gdbarch;
3185 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
3186 gdbarch = gdbarch_alloc (&info, tdep);
3188 /* Record additional information about the architecture we are defining.
3189 These are gdbarch discriminators, like the OSABI. */
3190 tdep->arm_abi = arm_abi;
3191 tdep->fp_model = fp_model;
3192 tdep->have_fpa_registers = have_fpa_registers;
3195 switch (info.byte_order)
3197 case BFD_ENDIAN_BIG:
3198 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3199 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3200 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3201 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3205 case BFD_ENDIAN_LITTLE:
3206 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3207 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3208 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3209 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3214 internal_error (__FILE__, __LINE__,
3215 _("arm_gdbarch_init: bad byte order for float format"));
3218 /* On ARM targets char defaults to unsigned. */
3219 set_gdbarch_char_signed (gdbarch, 0);
3221 /* This should be low enough for everything. */
3222 tdep->lowest_pc = 0x20;
3223 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3225 /* The default, for both APCS and AAPCS, is to return small
3226 structures in registers. */
3227 tdep->struct_return = reg_struct_return;
3229 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
3230 set_gdbarch_frame_align (gdbarch, arm_frame_align);
3232 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3234 /* Frame handling. */
3235 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
3236 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3237 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3239 frame_base_set_default (gdbarch, &arm_normal_base);
3241 /* Address manipulation. */
3242 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3243 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3245 /* Advance PC across function entry code. */
3246 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3248 /* Skip trampolines. */
3249 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3251 /* The stack grows downward. */
3252 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3254 /* Breakpoint manipulation. */
3255 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3257 /* Information about registers, etc. */
3258 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3259 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3260 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3261 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3262 set_gdbarch_register_type (gdbarch, arm_register_type);
3264 /* This "info float" is FPA-specific. Use the generic version if we
3266 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3267 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3269 /* Internal <-> external register number maps. */
3270 set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3271 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3272 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3274 set_gdbarch_register_name (gdbarch, arm_register_name);
3276 /* Returning results. */
3277 set_gdbarch_return_value (gdbarch, arm_return_value);
3280 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3282 /* Minsymbol frobbing. */
3283 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3284 set_gdbarch_coff_make_msymbol_special (gdbarch,
3285 arm_coff_make_msymbol_special);
3286 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
3288 /* Virtual tables. */
3289 set_gdbarch_vbit_in_delta (gdbarch, 1);
3291 /* Hook in the ABI-specific overrides, if they have been registered. */
3292 gdbarch_init_osabi (info, gdbarch);
3294 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3296 /* Add some default predicates. */
3297 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3298 dwarf2_append_unwinders (gdbarch);
3299 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
3301 /* Now we have tuned the configuration, set a few final things,
3302 based on what the OS ABI has told us. */
3304 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3305 binaries are always marked. */
3306 if (tdep->arm_abi == ARM_ABI_AUTO)
3307 tdep->arm_abi = ARM_ABI_APCS;
3309 /* We used to default to FPA for generic ARM, but almost nobody
3310 uses that now, and we now provide a way for the user to force
3311 the model. So default to the most useful variant. */
3312 if (tdep->fp_model == ARM_FLOAT_AUTO)
3313 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3315 if (tdep->jb_pc >= 0)
3316 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3318 /* Floating point sizes and format. */
3319 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3320 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3322 set_gdbarch_double_format
3323 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3324 set_gdbarch_long_double_format
3325 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3329 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3330 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3334 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3336 /* Add standard register aliases. We add aliases even for those
3337 nanes which are used by the current architecture - it's simpler,
3338 and does no harm, since nothing ever lists user registers. */
3339 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3340 user_reg_add (gdbarch, arm_register_aliases[i].name,
3341 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3347 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3349 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3354 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3355 (unsigned long) tdep->lowest_pc);
3358 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3361 _initialize_arm_tdep (void)
3363 struct ui_file *stb;
3365 struct cmd_list_element *new_set, *new_show;
3366 const char *setname;
3367 const char *setdesc;
3368 const char *const *regnames;
3370 static char *helptext;
3371 char regdesc[1024], *rdptr = regdesc;
3372 size_t rest = sizeof (regdesc);
3374 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3376 arm_objfile_data_key
3377 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup);
3379 /* Register an ELF OS ABI sniffer for ARM binaries. */
3380 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3381 bfd_target_elf_flavour,
3382 arm_elf_osabi_sniffer);
3384 /* Get the number of possible sets of register names defined in opcodes. */
3385 num_disassembly_options = get_arm_regname_num_options ();
3387 /* Add root prefix command for all "set arm"/"show arm" commands. */
3388 add_prefix_cmd ("arm", no_class, set_arm_command,
3389 _("Various ARM-specific commands."),
3390 &setarmcmdlist, "set arm ", 0, &setlist);
3392 add_prefix_cmd ("arm", no_class, show_arm_command,
3393 _("Various ARM-specific commands."),
3394 &showarmcmdlist, "show arm ", 0, &showlist);
3396 /* Sync the opcode insn printer with our register viewer. */
3397 parse_arm_disassembler_option ("reg-names-std");
3399 /* Initialize the array that will be passed to
3400 add_setshow_enum_cmd(). */
3401 valid_disassembly_styles
3402 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3403 for (i = 0; i < num_disassembly_options; i++)
3405 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3406 valid_disassembly_styles[i] = setname;
3407 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3410 /* When we find the default names, tell the disassembler to use
3412 if (!strcmp (setname, "std"))
3414 disassembly_style = setname;
3415 set_arm_regname_option (i);
3418 /* Mark the end of valid options. */
3419 valid_disassembly_styles[num_disassembly_options] = NULL;
3421 /* Create the help text. */
3422 stb = mem_fileopen ();
3423 fprintf_unfiltered (stb, "%s%s%s",
3424 _("The valid values are:\n"),
3426 _("The default is \"std\"."));
3427 helptext = ui_file_xstrdup (stb, &length);
3428 ui_file_delete (stb);
3430 add_setshow_enum_cmd("disassembler", no_class,
3431 valid_disassembly_styles, &disassembly_style,
3432 _("Set the disassembly style."),
3433 _("Show the disassembly style."),
3435 set_disassembly_style_sfunc,
3436 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3437 &setarmcmdlist, &showarmcmdlist);
3439 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3440 _("Set usage of ARM 32-bit mode."),
3441 _("Show usage of ARM 32-bit mode."),
3442 _("When off, a 26-bit PC will be used."),
3444 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3445 &setarmcmdlist, &showarmcmdlist);
3447 /* Add a command to allow the user to force the FPU model. */
3448 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3449 _("Set the floating point type."),
3450 _("Show the floating point type."),
3451 _("auto - Determine the FP typefrom the OS-ABI.\n\
3452 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3453 fpa - FPA co-processor (GCC compiled).\n\
3454 softvfp - Software FP with pure-endian doubles.\n\
3455 vfp - VFP co-processor."),
3456 set_fp_model_sfunc, show_fp_model,
3457 &setarmcmdlist, &showarmcmdlist);
3459 /* Add a command to allow the user to force the ABI. */
3460 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3463 NULL, arm_set_abi, arm_show_abi,
3464 &setarmcmdlist, &showarmcmdlist);
3466 /* Add two commands to allow the user to force the assumed
3468 add_setshow_enum_cmd ("fallback-mode", class_support,
3469 arm_mode_strings, &arm_fallback_mode_string,
3470 _("Set the mode assumed when symbols are unavailable."),
3471 _("Show the mode assumed when symbols are unavailable."),
3472 NULL, NULL, arm_show_fallback_mode,
3473 &setarmcmdlist, &showarmcmdlist);
3474 add_setshow_enum_cmd ("force-mode", class_support,
3475 arm_mode_strings, &arm_force_mode_string,
3476 _("Set the mode assumed even when symbols are available."),
3477 _("Show the mode assumed even when symbols are available."),
3478 NULL, NULL, arm_show_force_mode,
3479 &setarmcmdlist, &showarmcmdlist);
3481 /* Debugging flag. */
3482 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3483 _("Set ARM debugging."),
3484 _("Show ARM debugging."),
3485 _("When on, arm-specific debugging is enabled."),
3487 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3488 &setdebuglist, &showdebuglist);