1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
24 #include <ctype.h> /* XXX for isupper () */
31 #include "gdb_string.h"
32 #include "dis-asm.h" /* For register styles. */
36 #include "arch-utils.h"
38 #include "frame-unwind.h"
39 #include "frame-base.h"
40 #include "trad-frame.h"
42 #include "dwarf2-frame.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element *setarmcmdlist = NULL;
72 static struct cmd_list_element *showarmcmdlist = NULL;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
88 static const char *current_fp_model = "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
101 static const char *arm_abi_string = "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options;
106 /* We have more registers than the disassembler as gdb can print the value
107 of special registers as well.
108 The general register names are overwritten by whatever is being used by
109 the disassembler at the moment. We also adjust the case of cpsr and fps. */
111 /* Initial value: Register names used in ARM's ISA documentation. */
112 static char * arm_register_name_strings[] =
113 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
114 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
115 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
116 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
117 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
118 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
119 "fps", "cpsr" }; /* 24 25 */
120 static char **arm_register_names = arm_register_name_strings;
122 /* Valid register name styles. */
123 static const char **valid_disassembly_styles;
125 /* Disassembly style to use. Default to "std" register names. */
126 static const char *disassembly_style;
127 /* Index to that option in the opcodes table. */
128 static int current_option;
130 /* This is used to keep the bfd arch_info in sync with the disassembly
132 static void set_disassembly_style_sfunc(char *, int,
133 struct cmd_list_element *);
134 static void set_disassembly_style (void);
136 static void convert_from_extended (const struct floatformat *, const void *,
138 static void convert_to_extended (const struct floatformat *, void *,
141 struct arm_prologue_cache
143 /* The stack pointer at the time this frame was created; i.e. the
144 caller's stack pointer when this function was called. It is used
145 to identify this frame. */
148 /* The frame base for this frame is just prev_sp + frame offset -
149 frame size. FRAMESIZE is the size of this stack frame, and
150 FRAMEOFFSET if the initial offset from the stack pointer (this
151 frame's stack pointer, not PREV_SP) to the frame base. */
156 /* The register used to hold the frame pointer for this frame. */
159 /* Saved register offsets. */
160 struct trad_frame_saved_reg *saved_regs;
163 /* Addresses for calling Thumb functions have the bit 0 set.
164 Here are some macros to test, set, or clear bit 0 of addresses. */
165 #define IS_THUMB_ADDR(addr) ((addr) & 1)
166 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
167 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
169 /* Set to true if the 32-bit mode is in use. */
173 /* Determine if the program counter specified in MEMADDR is in a Thumb
177 arm_pc_is_thumb (CORE_ADDR memaddr)
179 struct minimal_symbol *sym;
181 /* If bit 0 of the address is set, assume this is a Thumb address. */
182 if (IS_THUMB_ADDR (memaddr))
185 /* Thumb functions have a "special" bit set in minimal symbols. */
186 sym = lookup_minimal_symbol_by_pc (memaddr);
189 return (MSYMBOL_IS_SPECIAL (sym));
197 /* Remove useless bits from addresses in a running program. */
199 arm_addr_bits_remove (CORE_ADDR val)
202 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
204 return (val & 0x03fffffc);
207 /* When reading symbols, we need to zap the low bit of the address,
208 which may be set to 1 for Thumb functions. */
210 arm_smash_text_address (CORE_ADDR val)
215 /* A typical Thumb prologue looks like this:
219 Sometimes the latter instruction may be replaced by:
227 or, on tpcs, like this:
234 There is always one instruction of three classes:
239 When we have found at least one of each class we are done with the prolog.
240 Note that the "sub sp, #NN" before the push does not count.
244 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
246 CORE_ADDR current_pc;
248 bit 0 - push { rlist }
249 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
250 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
254 for (current_pc = pc;
255 current_pc + 2 < func_end && current_pc < pc + 40;
258 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
260 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
262 findmask |= 1; /* push found */
264 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
267 if ((findmask & 1) == 0) /* before push ? */
270 findmask |= 4; /* add/sub sp found */
272 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
274 findmask |= 2; /* setting of r7 found */
276 else if (insn == 0x466f) /* mov r7, sp */
278 findmask |= 2; /* setting of r7 found */
280 else if (findmask == (4+2+1))
282 /* We have found one of each type of prologue instruction */
286 /* Something in the prolog that we don't care about or some
287 instruction from outside the prolog scheduled here for
295 /* Advance the PC across any function entry prologue instructions to
296 reach some "real" code.
298 The APCS (ARM Procedure Call Standard) defines the following
302 [stmfd sp!, {a1,a2,a3,a4}]
303 stmfd sp!, {...,fp,ip,lr,pc}
304 [stfe f7, [sp, #-12]!]
305 [stfe f6, [sp, #-12]!]
306 [stfe f5, [sp, #-12]!]
307 [stfe f4, [sp, #-12]!]
308 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
311 arm_skip_prologue (CORE_ADDR pc)
315 CORE_ADDR func_addr, func_end = 0;
317 struct symtab_and_line sal;
319 /* If we're in a dummy frame, don't even try to skip the prologue. */
320 if (deprecated_pc_in_call_dummy (pc))
323 /* See what the symbol table says. */
325 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
329 /* Found a function. */
330 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
331 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
333 /* Don't use this trick for assembly source files. */
334 sal = find_pc_line (func_addr, 0);
335 if ((sal.line != 0) && (sal.end < func_end))
340 /* Check if this is Thumb code. */
341 if (arm_pc_is_thumb (pc))
342 return thumb_skip_prologue (pc, func_end);
344 /* Can't find the prologue end in the symbol table, try it the hard way
345 by disassembling the instructions. */
347 /* Like arm_scan_prologue, stop no later than pc + 64. */
348 if (func_end == 0 || func_end > pc + 64)
351 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
353 inst = read_memory_unsigned_integer (skip_pc, 4);
355 /* "mov ip, sp" is no longer a required part of the prologue. */
356 if (inst == 0xe1a0c00d) /* mov ip, sp */
359 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
362 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
365 /* Some prologues begin with "str lr, [sp, #-4]!". */
366 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
369 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
372 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
375 /* Any insns after this point may float into the code, if it makes
376 for better instruction scheduling, so we skip them only if we
377 find them, but still consider the function to be frame-ful. */
379 /* We may have either one sfmfd instruction here, or several stfe
380 insns, depending on the version of floating point code we
382 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
385 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
388 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
391 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
394 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
395 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
396 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
399 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
400 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
401 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
404 /* Un-recognized instruction; stop scanning. */
408 return skip_pc; /* End of prologue */
412 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
413 This function decodes a Thumb function prologue to determine:
414 1) the size of the stack frame
415 2) which registers are saved on it
416 3) the offsets of saved regs
417 4) the offset from the stack pointer to the frame pointer
419 A typical Thumb function prologue would create this stack frame
420 (offsets relative to FP)
421 old SP -> 24 stack parameters
424 R7 -> 0 local variables (16 bytes)
425 SP -> -12 additional stack space (12 bytes)
426 The frame size would thus be 36 bytes, and the frame offset would be
427 12 bytes. The frame register is R7.
429 The comments for thumb_skip_prolog() describe the algorithm we use
430 to detect the end of the prolog. */
434 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
436 CORE_ADDR prologue_start;
437 CORE_ADDR prologue_end;
438 CORE_ADDR current_pc;
439 /* Which register has been copied to register n? */
442 bit 0 - push { rlist }
443 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
444 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
449 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
451 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
453 if (sal.line == 0) /* no line info, use current PC */
454 prologue_end = prev_pc;
455 else if (sal.end < prologue_end) /* next line begins after fn end */
456 prologue_end = sal.end; /* (probably means no prologue) */
459 /* We're in the boondocks: we have no idea where the start of the
463 prologue_end = min (prologue_end, prev_pc);
465 /* Initialize the saved register map. When register H is copied to
466 register L, we will put H in saved_reg[L]. */
467 for (i = 0; i < 16; i++)
470 /* Search the prologue looking for instructions that set up the
471 frame pointer, adjust the stack pointer, and save registers.
472 Do this until all basic prolog instructions are found. */
474 cache->framesize = 0;
475 for (current_pc = prologue_start;
476 (current_pc < prologue_end) && ((findmask & 7) != 7);
483 insn = read_memory_unsigned_integer (current_pc, 2);
485 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
488 findmask |= 1; /* push found */
489 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
490 whether to save LR (R14). */
491 mask = (insn & 0xff) | ((insn & 0x100) << 6);
493 /* Calculate offsets of saved R0-R7 and LR. */
494 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
495 if (mask & (1 << regno))
497 cache->framesize += 4;
498 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
499 /* Reset saved register map. */
500 saved_reg[regno] = regno;
503 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
506 if ((findmask & 1) == 0) /* before push? */
509 findmask |= 4; /* add/sub sp found */
511 offset = (insn & 0x7f) << 2; /* get scaled offset */
512 if (insn & 0x80) /* is it signed? (==subtracting) */
514 cache->frameoffset += offset;
517 cache->framesize -= offset;
519 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
521 findmask |= 2; /* setting of r7 found */
522 cache->framereg = THUMB_FP_REGNUM;
523 /* get scaled offset */
524 cache->frameoffset = (insn & 0xff) << 2;
526 else if (insn == 0x466f) /* mov r7, sp */
528 findmask |= 2; /* setting of r7 found */
529 cache->framereg = THUMB_FP_REGNUM;
530 cache->frameoffset = 0;
531 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
533 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
535 int lo_reg = insn & 7; /* dest. register (r0-r7) */
536 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
537 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
540 /* Something in the prolog that we don't care about or some
541 instruction from outside the prolog scheduled here for
547 /* This function decodes an ARM function prologue to determine:
548 1) the size of the stack frame
549 2) which registers are saved on it
550 3) the offsets of saved regs
551 4) the offset from the stack pointer to the frame pointer
552 This information is stored in the "extra" fields of the frame_info.
554 There are two basic forms for the ARM prologue. The fixed argument
555 function call will look like:
558 stmfd sp!, {fp, ip, lr, pc}
562 Which would create this stack frame (offsets relative to FP):
563 IP -> 4 (caller's stack)
564 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
565 -4 LR (return address in caller)
566 -8 IP (copy of caller's SP)
568 SP -> -28 Local variables
570 The frame size would thus be 32 bytes, and the frame offset would be
571 28 bytes. The stmfd call can also save any of the vN registers it
572 plans to use, which increases the frame size accordingly.
574 Note: The stored PC is 8 off of the STMFD instruction that stored it
575 because the ARM Store instructions always store PC + 8 when you read
578 A variable argument function call will look like:
581 stmfd sp!, {a1, a2, a3, a4}
582 stmfd sp!, {fp, ip, lr, pc}
585 Which would create this stack frame (offsets relative to FP):
586 IP -> 20 (caller's stack)
591 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
592 -4 LR (return address in caller)
593 -8 IP (copy of caller's SP)
595 SP -> -28 Local variables
597 The frame size would thus be 48 bytes, and the frame offset would be
600 There is another potential complication, which is that the optimizer
601 will try to separate the store of fp in the "stmfd" instruction from
602 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
603 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
605 Also, note, the original version of the ARM toolchain claimed that there
608 instruction at the end of the prologue. I have never seen GCC produce
609 this, and the ARM docs don't mention it. We still test for it below in
615 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
617 int regno, sp_offset, fp_offset, ip_offset;
618 CORE_ADDR prologue_start, prologue_end, current_pc;
619 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
621 /* Assume there is no frame until proven otherwise. */
622 cache->framereg = ARM_SP_REGNUM;
623 cache->framesize = 0;
624 cache->frameoffset = 0;
626 /* Check for Thumb prologue. */
627 if (arm_pc_is_thumb (prev_pc))
629 thumb_scan_prologue (prev_pc, cache);
633 /* Find the function prologue. If we can't find the function in
634 the symbol table, peek in the stack frame to find the PC. */
635 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
637 /* One way to find the end of the prologue (which works well
638 for unoptimized code) is to do the following:
640 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
643 prologue_end = prev_pc;
644 else if (sal.end < prologue_end)
645 prologue_end = sal.end;
647 This mechanism is very accurate so long as the optimizer
648 doesn't move any instructions from the function body into the
649 prologue. If this happens, sal.end will be the last
650 instruction in the first hunk of prologue code just before
651 the first instruction that the scheduler has moved from
652 the body to the prologue.
654 In order to make sure that we scan all of the prologue
655 instructions, we use a slightly less accurate mechanism which
656 may scan more than necessary. To help compensate for this
657 lack of accuracy, the prologue scanning loop below contains
658 several clauses which'll cause the loop to terminate early if
659 an implausible prologue instruction is encountered.
665 is a suitable endpoint since it accounts for the largest
666 possible prologue plus up to five instructions inserted by
669 if (prologue_end > prologue_start + 64)
671 prologue_end = prologue_start + 64; /* See above. */
676 /* We have no symbol information. Our only option is to assume this
677 function has a standard stack frame and the normal frame register.
678 Then, we can find the value of our frame pointer on entrance to
679 the callee (or at the present moment if this is the innermost frame).
680 The value stored there should be the address of the stmfd + 8. */
682 LONGEST return_value;
684 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
685 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
689 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
690 prologue_end = prologue_start + 64; /* See above. */
694 if (prev_pc < prologue_end)
695 prologue_end = prev_pc;
697 /* Now search the prologue looking for instructions that set up the
698 frame pointer, adjust the stack pointer, and save registers.
700 Be careful, however, and if it doesn't look like a prologue,
701 don't try to scan it. If, for instance, a frameless function
702 begins with stmfd sp!, then we will tell ourselves there is
703 a frame, which will confuse stack traceback, as well as "finish"
704 and other operations that rely on a knowledge of the stack
707 In the APCS, the prologue should start with "mov ip, sp" so
708 if we don't see this as the first insn, we will stop.
710 [Note: This doesn't seem to be true any longer, so it's now an
711 optional part of the prologue. - Kevin Buettner, 2001-11-20]
713 [Note further: The "mov ip,sp" only seems to be missing in
714 frameless functions at optimization level "-O2" or above,
715 in which case it is often (but not always) replaced by
716 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
718 sp_offset = fp_offset = ip_offset = 0;
720 for (current_pc = prologue_start;
721 current_pc < prologue_end;
724 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
726 if (insn == 0xe1a0c00d) /* mov ip, sp */
731 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
733 unsigned imm = insn & 0xff; /* immediate value */
734 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
735 imm = (imm >> rot) | (imm << (32 - rot));
739 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
741 unsigned imm = insn & 0xff; /* immediate value */
742 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
743 imm = (imm >> rot) | (imm << (32 - rot));
747 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
750 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
753 else if ((insn & 0xffff0000) == 0xe92d0000)
754 /* stmfd sp!, {..., fp, ip, lr, pc}
756 stmfd sp!, {a1, a2, a3, a4} */
758 int mask = insn & 0xffff;
760 /* Calculate offsets of saved registers. */
761 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
762 if (mask & (1 << regno))
765 cache->saved_regs[regno].addr = sp_offset;
768 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
769 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
770 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
772 /* No need to add this to saved_regs -- it's just an arg reg. */
775 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
776 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
777 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
779 /* No need to add this to saved_regs -- it's just an arg reg. */
782 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
784 unsigned imm = insn & 0xff; /* immediate value */
785 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
786 imm = (imm >> rot) | (imm << (32 - rot));
787 fp_offset = -imm + ip_offset;
788 cache->framereg = ARM_FP_REGNUM;
790 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
792 unsigned imm = insn & 0xff; /* immediate value */
793 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
794 imm = (imm >> rot) | (imm << (32 - rot));
797 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
800 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
801 cache->saved_regs[regno].addr = sp_offset;
803 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
806 unsigned int fp_start_reg, fp_bound_reg;
808 if ((insn & 0x800) == 0x800) /* N0 is set */
810 if ((insn & 0x40000) == 0x40000) /* N1 is set */
817 if ((insn & 0x40000) == 0x40000) /* N1 is set */
823 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
824 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
825 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
828 cache->saved_regs[fp_start_reg++].addr = sp_offset;
831 else if ((insn & 0xf0000000) != 0xe0000000)
832 break; /* Condition not true, exit early */
833 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
834 break; /* Don't scan past a block load */
836 /* The optimizer might shove anything into the prologue,
837 so we just skip what we don't recognize. */
841 /* The frame size is just the negative of the offset (from the
842 original SP) of the last thing thing we pushed on the stack.
843 The frame offset is [new FP] - [new SP]. */
844 cache->framesize = -sp_offset;
845 if (cache->framereg == ARM_FP_REGNUM)
846 cache->frameoffset = fp_offset - sp_offset;
848 cache->frameoffset = 0;
851 static struct arm_prologue_cache *
852 arm_make_prologue_cache (struct frame_info *next_frame)
855 struct arm_prologue_cache *cache;
856 CORE_ADDR unwound_fp;
858 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
859 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
861 arm_scan_prologue (next_frame, cache);
863 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
867 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
869 /* Calculate actual addresses of saved registers using offsets
870 determined by arm_scan_prologue. */
871 for (reg = 0; reg < NUM_REGS; reg++)
872 if (trad_frame_addr_p (cache->saved_regs, reg))
873 cache->saved_regs[reg].addr += cache->prev_sp;
878 /* Our frame ID for a normal frame is the current function's starting PC
879 and the caller's SP when we were called. */
882 arm_prologue_this_id (struct frame_info *next_frame,
884 struct frame_id *this_id)
886 struct arm_prologue_cache *cache;
890 if (*this_cache == NULL)
891 *this_cache = arm_make_prologue_cache (next_frame);
894 func = frame_func_unwind (next_frame);
896 /* This is meant to halt the backtrace at "_start". Make sure we
897 don't halt it at a generic dummy frame. */
898 if (func <= LOWEST_PC)
901 /* If we've hit a wall, stop. */
902 if (cache->prev_sp == 0)
905 id = frame_id_build (cache->prev_sp, func);
910 arm_prologue_prev_register (struct frame_info *next_frame,
914 enum lval_type *lvalp,
919 struct arm_prologue_cache *cache;
921 if (*this_cache == NULL)
922 *this_cache = arm_make_prologue_cache (next_frame);
925 /* If we are asked to unwind the PC, then we need to return the LR
926 instead. The saved value of PC points into this frame's
927 prologue, not the next frame's resume location. */
928 if (prev_regnum == ARM_PC_REGNUM)
929 prev_regnum = ARM_LR_REGNUM;
931 /* SP is generally not saved to the stack, but this frame is
932 identified by NEXT_FRAME's stack pointer at the time of the call.
933 The value was already reconstructed into PREV_SP. */
934 if (prev_regnum == ARM_SP_REGNUM)
938 store_unsigned_integer (valuep, 4, cache->prev_sp);
942 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
943 optimized, lvalp, addrp, realnump, valuep);
946 struct frame_unwind arm_prologue_unwind = {
948 arm_prologue_this_id,
949 arm_prologue_prev_register
952 static const struct frame_unwind *
953 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
955 return &arm_prologue_unwind;
958 static struct arm_prologue_cache *
959 arm_make_stub_cache (struct frame_info *next_frame)
962 struct arm_prologue_cache *cache;
963 CORE_ADDR unwound_fp;
965 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
966 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
968 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
973 /* Our frame ID for a stub frame is the current SP and LR. */
976 arm_stub_this_id (struct frame_info *next_frame,
978 struct frame_id *this_id)
980 struct arm_prologue_cache *cache;
982 if (*this_cache == NULL)
983 *this_cache = arm_make_stub_cache (next_frame);
986 *this_id = frame_id_build (cache->prev_sp,
987 frame_pc_unwind (next_frame));
990 struct frame_unwind arm_stub_unwind = {
993 arm_prologue_prev_register
996 static const struct frame_unwind *
997 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1001 if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL)
1002 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1003 return &arm_stub_unwind;
1009 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1011 struct arm_prologue_cache *cache;
1013 if (*this_cache == NULL)
1014 *this_cache = arm_make_prologue_cache (next_frame);
1015 cache = *this_cache;
1017 return cache->prev_sp + cache->frameoffset - cache->framesize;
1020 struct frame_base arm_normal_base = {
1021 &arm_prologue_unwind,
1022 arm_normal_frame_base,
1023 arm_normal_frame_base,
1024 arm_normal_frame_base
1027 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1028 dummy frame. The frame ID's base needs to match the TOS value
1029 saved by save_dummy_frame_tos() and returned from
1030 arm_push_dummy_call, and the PC needs to match the dummy frame's
1033 static struct frame_id
1034 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1036 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1037 frame_pc_unwind (next_frame));
1040 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1041 be used to construct the previous frame's ID, after looking up the
1042 containing function). */
1045 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1048 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1049 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1053 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1055 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1058 /* When arguments must be pushed onto the stack, they go on in reverse
1059 order. The code below implements a FILO (stack) to do this. */
1064 struct stack_item *prev;
1068 static struct stack_item *
1069 push_stack_item (struct stack_item *prev, void *contents, int len)
1071 struct stack_item *si;
1072 si = xmalloc (sizeof (struct stack_item));
1073 si->data = xmalloc (len);
1076 memcpy (si->data, contents, len);
1080 static struct stack_item *
1081 pop_stack_item (struct stack_item *si)
1083 struct stack_item *dead = si;
1091 /* Return the alignment (in bytes) of the given type. */
1094 arm_type_align (struct type *t)
1100 t = check_typedef (t);
1101 switch (TYPE_CODE (t))
1104 /* Should never happen. */
1105 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1109 case TYPE_CODE_ENUM:
1113 case TYPE_CODE_RANGE:
1114 case TYPE_CODE_BITSTRING:
1116 case TYPE_CODE_CHAR:
1117 case TYPE_CODE_BOOL:
1118 return TYPE_LENGTH (t);
1120 case TYPE_CODE_ARRAY:
1121 case TYPE_CODE_COMPLEX:
1122 /* TODO: What about vector types? */
1123 return arm_type_align (TYPE_TARGET_TYPE (t));
1125 case TYPE_CODE_STRUCT:
1126 case TYPE_CODE_UNION:
1128 for (n = 0; n < TYPE_NFIELDS (t); n++)
1130 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1138 /* We currently only support passing parameters in integer registers. This
1139 conforms with GCC's default model. Several other variants exist and
1140 we should probably support some of them based on the selected ABI. */
1143 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1144 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1145 struct value **args, CORE_ADDR sp, int struct_return,
1146 CORE_ADDR struct_addr)
1151 struct stack_item *si = NULL;
1153 /* Set the return address. For the ARM, the return breakpoint is
1154 always at BP_ADDR. */
1155 /* XXX Fix for Thumb. */
1156 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1158 /* Walk through the list of args and determine how large a temporary
1159 stack is required. Need to take care here as structs may be
1160 passed on the stack, and we have to to push them. */
1163 argreg = ARM_A1_REGNUM;
1166 /* The struct_return pointer occupies the first parameter
1167 passing register. */
1171 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1172 REGISTER_NAME (argreg), paddr (struct_addr));
1173 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1177 for (argnum = 0; argnum < nargs; argnum++)
1180 struct type *arg_type;
1181 struct type *target_type;
1182 enum type_code typecode;
1186 arg_type = check_typedef (value_type (args[argnum]));
1187 len = TYPE_LENGTH (arg_type);
1188 target_type = TYPE_TARGET_TYPE (arg_type);
1189 typecode = TYPE_CODE (arg_type);
1190 val = value_contents_writeable (args[argnum]);
1192 align = arm_type_align (arg_type);
1193 /* Round alignment up to a whole number of words. */
1194 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1195 /* Different ABIs have different maximum alignments. */
1196 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1198 /* The APCS ABI only requires word alignment. */
1199 align = INT_REGISTER_SIZE;
1203 /* The AAPCS requires at most doubleword alignment. */
1204 if (align > INT_REGISTER_SIZE * 2)
1205 align = INT_REGISTER_SIZE * 2;
1208 /* Push stack padding for dowubleword alignment. */
1209 if (nstack & (align - 1))
1211 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1212 nstack += INT_REGISTER_SIZE;
1215 /* Doubleword aligned quantities must go in even register pairs. */
1216 if (argreg <= ARM_LAST_ARG_REGNUM
1217 && align > INT_REGISTER_SIZE
1221 /* If the argument is a pointer to a function, and it is a
1222 Thumb function, create a LOCAL copy of the value and set
1223 the THUMB bit in it. */
1224 if (TYPE_CODE_PTR == typecode
1225 && target_type != NULL
1226 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1228 CORE_ADDR regval = extract_unsigned_integer (val, len);
1229 if (arm_pc_is_thumb (regval))
1232 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1236 /* Copy the argument to general registers or the stack in
1237 register-sized pieces. Large arguments are split between
1238 registers and stack. */
1241 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1243 if (argreg <= ARM_LAST_ARG_REGNUM)
1245 /* The argument is being passed in a general purpose
1247 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1249 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1250 argnum, REGISTER_NAME (argreg),
1251 phex (regval, DEPRECATED_REGISTER_SIZE));
1252 regcache_cooked_write_unsigned (regcache, argreg, regval);
1257 /* Push the arguments onto the stack. */
1259 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1261 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1262 nstack += DEPRECATED_REGISTER_SIZE;
1269 /* If we have an odd number of words to push, then decrement the stack
1270 by one word now, so first stack argument will be dword aligned. */
1277 write_memory (sp, si->data, si->len);
1278 si = pop_stack_item (si);
1281 /* Finally, update teh SP register. */
1282 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1288 /* Always align the frame to an 8-byte boundary. This is required on
1289 some platforms and harmless on the rest. */
1292 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1294 /* Align the stack to eight bytes. */
1295 return sp & ~ (CORE_ADDR) 7;
1299 print_fpu_flags (int flags)
1301 if (flags & (1 << 0))
1302 fputs ("IVO ", stdout);
1303 if (flags & (1 << 1))
1304 fputs ("DVZ ", stdout);
1305 if (flags & (1 << 2))
1306 fputs ("OFL ", stdout);
1307 if (flags & (1 << 3))
1308 fputs ("UFL ", stdout);
1309 if (flags & (1 << 4))
1310 fputs ("INX ", stdout);
1314 /* Print interesting information about the floating point processor
1315 (if present) or emulator. */
1317 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1318 struct frame_info *frame, const char *args)
1320 unsigned long status = read_register (ARM_FPS_REGNUM);
1323 type = (status >> 24) & 127;
1324 if (status & (1 << 31))
1325 printf (_("Hardware FPU type %d\n"), type);
1327 printf (_("Software FPU type %d\n"), type);
1328 /* i18n: [floating point unit] mask */
1329 fputs (_("mask: "), stdout);
1330 print_fpu_flags (status >> 16);
1331 /* i18n: [floating point unit] flags */
1332 fputs (_("flags: "), stdout);
1333 print_fpu_flags (status);
1336 /* Return the GDB type object for the "standard" data type of data in
1339 static struct type *
1340 arm_register_type (struct gdbarch *gdbarch, int regnum)
1342 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1344 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1345 return builtin_type_arm_ext_big;
1347 return builtin_type_arm_ext_littlebyte_bigword;
1349 else if (regnum == ARM_SP_REGNUM)
1350 return builtin_type_void_data_ptr;
1351 else if (regnum == ARM_PC_REGNUM)
1352 return builtin_type_void_func_ptr;
1354 return builtin_type_uint32;
1357 /* Index within `registers' of the first byte of the space for
1361 arm_register_byte (int regnum)
1363 if (regnum < ARM_F0_REGNUM)
1364 return regnum * INT_REGISTER_SIZE;
1365 else if (regnum < ARM_PS_REGNUM)
1366 return (NUM_GREGS * INT_REGISTER_SIZE
1367 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1369 return (NUM_GREGS * INT_REGISTER_SIZE
1370 + NUM_FREGS * FP_REGISTER_SIZE
1371 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1374 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1376 arm_register_sim_regno (int regnum)
1379 gdb_assert (reg >= 0 && reg < NUM_REGS);
1381 if (reg < NUM_GREGS)
1382 return SIM_ARM_R0_REGNUM + reg;
1385 if (reg < NUM_FREGS)
1386 return SIM_ARM_FP0_REGNUM + reg;
1389 if (reg < NUM_SREGS)
1390 return SIM_ARM_FPS_REGNUM + reg;
1393 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1396 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1397 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1398 It is thought that this is is the floating-point register format on
1399 little-endian systems. */
1402 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1406 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1407 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1409 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1411 floatformat_from_doublest (fmt, &d, dbl);
1415 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1418 floatformat_to_doublest (fmt, ptr, &d);
1419 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1420 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1422 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1427 condition_true (unsigned long cond, unsigned long status_reg)
1429 if (cond == INST_AL || cond == INST_NV)
1435 return ((status_reg & FLAG_Z) != 0);
1437 return ((status_reg & FLAG_Z) == 0);
1439 return ((status_reg & FLAG_C) != 0);
1441 return ((status_reg & FLAG_C) == 0);
1443 return ((status_reg & FLAG_N) != 0);
1445 return ((status_reg & FLAG_N) == 0);
1447 return ((status_reg & FLAG_V) != 0);
1449 return ((status_reg & FLAG_V) == 0);
1451 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1453 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1455 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1457 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1459 return (((status_reg & FLAG_Z) == 0) &&
1460 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1462 return (((status_reg & FLAG_Z) != 0) ||
1463 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1468 /* Support routines for single stepping. Calculate the next PC value. */
1469 #define submask(x) ((1L << ((x) + 1)) - 1)
1470 #define bit(obj,st) (((obj) >> (st)) & 1)
1471 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1472 #define sbits(obj,st,fn) \
1473 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1474 #define BranchDest(addr,instr) \
1475 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1478 static unsigned long
1479 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1480 unsigned long status_reg)
1482 unsigned long res, shift;
1483 int rm = bits (inst, 0, 3);
1484 unsigned long shifttype = bits (inst, 5, 6);
1488 int rs = bits (inst, 8, 11);
1489 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1492 shift = bits (inst, 7, 11);
1495 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1496 + (bit (inst, 4) ? 12 : 8))
1497 : read_register (rm));
1502 res = shift >= 32 ? 0 : res << shift;
1506 res = shift >= 32 ? 0 : res >> shift;
1512 res = ((res & 0x80000000L)
1513 ? ~((~res) >> shift) : res >> shift);
1516 case 3: /* ROR/RRX */
1519 res = (res >> 1) | (carry ? 0x80000000L : 0);
1521 res = (res >> shift) | (res << (32 - shift));
1525 return res & 0xffffffff;
1528 /* Return number of 1-bits in VAL. */
1531 bitcount (unsigned long val)
1534 for (nbits = 0; val != 0; nbits++)
1535 val &= val - 1; /* delete rightmost 1-bit in val */
1540 thumb_get_next_pc (CORE_ADDR pc)
1542 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1543 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1544 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1545 unsigned long offset;
1547 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1551 /* Fetch the saved PC from the stack. It's stored above
1552 all of the other registers. */
1553 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1554 sp = read_register (ARM_SP_REGNUM);
1555 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1556 nextpc = ADDR_BITS_REMOVE (nextpc);
1558 error (_("Infinite loop detected"));
1560 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1562 unsigned long status = read_register (ARM_PS_REGNUM);
1563 unsigned long cond = bits (inst1, 8, 11);
1564 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1565 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1567 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1569 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1571 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1573 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1574 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1575 nextpc = pc_val + offset;
1576 /* For BLX make sure to clear the low bits. */
1577 if (bits (inst2, 11, 12) == 1)
1578 nextpc = nextpc & 0xfffffffc;
1580 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1582 if (bits (inst1, 3, 6) == 0x0f)
1585 nextpc = read_register (bits (inst1, 3, 6));
1587 nextpc = ADDR_BITS_REMOVE (nextpc);
1589 error (_("Infinite loop detected"));
1596 arm_get_next_pc (CORE_ADDR pc)
1598 unsigned long pc_val;
1599 unsigned long this_instr;
1600 unsigned long status;
1603 if (arm_pc_is_thumb (pc))
1604 return thumb_get_next_pc (pc);
1606 pc_val = (unsigned long) pc;
1607 this_instr = read_memory_unsigned_integer (pc, 4);
1608 status = read_register (ARM_PS_REGNUM);
1609 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1611 if (condition_true (bits (this_instr, 28, 31), status))
1613 switch (bits (this_instr, 24, 27))
1616 case 0x1: /* data processing */
1620 unsigned long operand1, operand2, result = 0;
1624 if (bits (this_instr, 12, 15) != 15)
1627 if (bits (this_instr, 22, 25) == 0
1628 && bits (this_instr, 4, 7) == 9) /* multiply */
1629 error (_("Invalid update to pc in instruction"));
1631 /* BX <reg>, BLX <reg> */
1632 if (bits (this_instr, 4, 28) == 0x12fff1
1633 || bits (this_instr, 4, 28) == 0x12fff3)
1635 rn = bits (this_instr, 0, 3);
1636 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1637 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1640 error (_("Infinite loop detected"));
1645 /* Multiply into PC */
1646 c = (status & FLAG_C) ? 1 : 0;
1647 rn = bits (this_instr, 16, 19);
1648 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1650 if (bit (this_instr, 25))
1652 unsigned long immval = bits (this_instr, 0, 7);
1653 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1654 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1657 else /* operand 2 is a shifted register */
1658 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1660 switch (bits (this_instr, 21, 24))
1663 result = operand1 & operand2;
1667 result = operand1 ^ operand2;
1671 result = operand1 - operand2;
1675 result = operand2 - operand1;
1679 result = operand1 + operand2;
1683 result = operand1 + operand2 + c;
1687 result = operand1 - operand2 + c;
1691 result = operand2 - operand1 + c;
1697 case 0xb: /* tst, teq, cmp, cmn */
1698 result = (unsigned long) nextpc;
1702 result = operand1 | operand2;
1706 /* Always step into a function. */
1711 result = operand1 & ~operand2;
1718 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1721 error (_("Infinite loop detected"));
1726 case 0x5: /* data transfer */
1729 if (bit (this_instr, 20))
1732 if (bits (this_instr, 12, 15) == 15)
1738 if (bit (this_instr, 22))
1739 error (_("Invalid update to pc in instruction"));
1741 /* byte write to PC */
1742 rn = bits (this_instr, 16, 19);
1743 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1744 if (bit (this_instr, 24))
1747 int c = (status & FLAG_C) ? 1 : 0;
1748 unsigned long offset =
1749 (bit (this_instr, 25)
1750 ? shifted_reg_val (this_instr, c, pc_val, status)
1751 : bits (this_instr, 0, 11));
1753 if (bit (this_instr, 23))
1758 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1761 nextpc = ADDR_BITS_REMOVE (nextpc);
1764 error (_("Infinite loop detected"));
1770 case 0x9: /* block transfer */
1771 if (bit (this_instr, 20))
1774 if (bit (this_instr, 15))
1779 if (bit (this_instr, 23))
1782 unsigned long reglist = bits (this_instr, 0, 14);
1783 offset = bitcount (reglist) * 4;
1784 if (bit (this_instr, 24)) /* pre */
1787 else if (bit (this_instr, 24))
1791 unsigned long rn_val =
1792 read_register (bits (this_instr, 16, 19));
1794 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1798 nextpc = ADDR_BITS_REMOVE (nextpc);
1800 error (_("Infinite loop detected"));
1805 case 0xb: /* branch & link */
1806 case 0xa: /* branch */
1808 nextpc = BranchDest (pc, this_instr);
1811 if (bits (this_instr, 28, 31) == INST_NV)
1812 nextpc |= bit (this_instr, 24) << 1;
1814 nextpc = ADDR_BITS_REMOVE (nextpc);
1816 error (_("Infinite loop detected"));
1822 case 0xe: /* coproc ops */
1827 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1835 /* single_step() is called just before we want to resume the inferior,
1836 if we want to single-step it but there is no hardware or kernel
1837 single-step support. We find the target of the coming instruction
1840 single_step() is also called just after the inferior stops. If we
1841 had set up a simulated single-step, we undo our damage. */
1844 arm_software_single_step (enum target_signal sig, int insert_bpt)
1846 /* NOTE: This may insert the wrong breakpoint instruction when
1847 single-stepping over a mode-changing instruction, if the
1848 CPSR heuristics are used. */
1852 CORE_ADDR next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1854 insert_single_step_breakpoint (next_pc);
1857 remove_single_step_breakpoints ();
1860 #include "bfd-in2.h"
1861 #include "libcoff.h"
1864 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1866 if (arm_pc_is_thumb (memaddr))
1868 static asymbol *asym;
1869 static combined_entry_type ce;
1870 static struct coff_symbol_struct csym;
1871 static struct bfd fake_bfd;
1872 static bfd_target fake_target;
1874 if (csym.native == NULL)
1876 /* Create a fake symbol vector containing a Thumb symbol.
1877 This is solely so that the code in print_insn_little_arm()
1878 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1879 the presence of a Thumb symbol and switch to decoding
1880 Thumb instructions. */
1882 fake_target.flavour = bfd_target_coff_flavour;
1883 fake_bfd.xvec = &fake_target;
1884 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1886 csym.symbol.the_bfd = &fake_bfd;
1887 csym.symbol.name = "fake";
1888 asym = (asymbol *) & csym;
1891 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1892 info->symbols = &asym;
1895 info->symbols = NULL;
1897 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1898 return print_insn_big_arm (memaddr, info);
1900 return print_insn_little_arm (memaddr, info);
1903 /* The following define instruction sequences that will cause ARM
1904 cpu's to take an undefined instruction trap. These are used to
1905 signal a breakpoint to GDB.
1907 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1908 modes. A different instruction is required for each mode. The ARM
1909 cpu's can also be big or little endian. Thus four different
1910 instructions are needed to support all cases.
1912 Note: ARMv4 defines several new instructions that will take the
1913 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1914 not in fact add the new instructions. The new undefined
1915 instructions in ARMv4 are all instructions that had no defined
1916 behaviour in earlier chips. There is no guarantee that they will
1917 raise an exception, but may be treated as NOP's. In practice, it
1918 may only safe to rely on instructions matching:
1920 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1921 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1922 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1924 Even this may only true if the condition predicate is true. The
1925 following use a condition predicate of ALWAYS so it is always TRUE.
1927 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1928 and NetBSD all use a software interrupt rather than an undefined
1929 instruction to force a trap. This can be handled by by the
1930 abi-specific code during establishment of the gdbarch vector. */
1933 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1934 override these definitions. */
1935 #ifndef ARM_LE_BREAKPOINT
1936 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1938 #ifndef ARM_BE_BREAKPOINT
1939 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1941 #ifndef THUMB_LE_BREAKPOINT
1942 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1944 #ifndef THUMB_BE_BREAKPOINT
1945 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1948 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1949 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1950 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1951 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1953 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1954 the program counter value to determine whether a 16-bit or 32-bit
1955 breakpoint should be used. It returns a pointer to a string of
1956 bytes that encode a breakpoint instruction, stores the length of
1957 the string to *lenptr, and adjusts the program counter (if
1958 necessary) to point to the actual memory location where the
1959 breakpoint should be inserted. */
1961 static const unsigned char *
1962 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1964 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1966 if (arm_pc_is_thumb (*pcptr))
1968 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1969 *lenptr = tdep->thumb_breakpoint_size;
1970 return tdep->thumb_breakpoint;
1974 *lenptr = tdep->arm_breakpoint_size;
1975 return tdep->arm_breakpoint;
1979 /* Extract from an array REGBUF containing the (raw) register state a
1980 function return value of type TYPE, and copy that, in virtual
1981 format, into VALBUF. */
1984 arm_extract_return_value (struct type *type, struct regcache *regs,
1987 if (TYPE_CODE_FLT == TYPE_CODE (type))
1989 switch (gdbarch_tdep (current_gdbarch)->fp_model)
1993 /* The value is in register F0 in internal format. We need to
1994 extract the raw value and then convert it to the desired
1996 bfd_byte tmpbuf[FP_REGISTER_SIZE];
1998 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
1999 convert_from_extended (floatformat_from_type (type), tmpbuf,
2004 case ARM_FLOAT_SOFT_FPA:
2005 case ARM_FLOAT_SOFT_VFP:
2006 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2007 if (TYPE_LENGTH (type) > 4)
2008 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2009 valbuf + INT_REGISTER_SIZE);
2014 (__FILE__, __LINE__,
2015 _("arm_extract_return_value: Floating point model not supported"));
2019 else if (TYPE_CODE (type) == TYPE_CODE_INT
2020 || TYPE_CODE (type) == TYPE_CODE_CHAR
2021 || TYPE_CODE (type) == TYPE_CODE_BOOL
2022 || TYPE_CODE (type) == TYPE_CODE_PTR
2023 || TYPE_CODE (type) == TYPE_CODE_REF
2024 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2026 /* If the the type is a plain integer, then the access is
2027 straight-forward. Otherwise we have to play around a bit more. */
2028 int len = TYPE_LENGTH (type);
2029 int regno = ARM_A1_REGNUM;
2034 /* By using store_unsigned_integer we avoid having to do
2035 anything special for small big-endian values. */
2036 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2037 store_unsigned_integer (valbuf,
2038 (len > INT_REGISTER_SIZE
2039 ? INT_REGISTER_SIZE : len),
2041 len -= INT_REGISTER_SIZE;
2042 valbuf += INT_REGISTER_SIZE;
2047 /* For a structure or union the behaviour is as if the value had
2048 been stored to word-aligned memory and then loaded into
2049 registers with 32-bit load instruction(s). */
2050 int len = TYPE_LENGTH (type);
2051 int regno = ARM_A1_REGNUM;
2052 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2056 regcache_cooked_read (regs, regno++, tmpbuf);
2057 memcpy (valbuf, tmpbuf,
2058 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2059 len -= INT_REGISTER_SIZE;
2060 valbuf += INT_REGISTER_SIZE;
2066 /* Will a function return an aggregate type in memory or in a
2067 register? Return 0 if an aggregate type can be returned in a
2068 register, 1 if it must be returned in memory. */
2071 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2074 enum type_code code;
2076 CHECK_TYPEDEF (type);
2078 /* In the ARM ABI, "integer" like aggregate types are returned in
2079 registers. For an aggregate type to be integer like, its size
2080 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2081 offset of each addressable subfield must be zero. Note that bit
2082 fields are not addressable, and all addressable subfields of
2083 unions always start at offset zero.
2085 This function is based on the behaviour of GCC 2.95.1.
2086 See: gcc/arm.c: arm_return_in_memory() for details.
2088 Note: All versions of GCC before GCC 2.95.2 do not set up the
2089 parameters correctly for a function returning the following
2090 structure: struct { float f;}; This should be returned in memory,
2091 not a register. Richard Earnshaw sent me a patch, but I do not
2092 know of any way to detect if a function like the above has been
2093 compiled with the correct calling convention. */
2095 /* All aggregate types that won't fit in a register must be returned
2097 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2102 /* The AAPCS says all aggregates not larger than a word are returned
2104 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2107 /* The only aggregate types that can be returned in a register are
2108 structs and unions. Arrays must be returned in memory. */
2109 code = TYPE_CODE (type);
2110 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2115 /* Assume all other aggregate types can be returned in a register.
2116 Run a check for structures, unions and arrays. */
2119 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2122 /* Need to check if this struct/union is "integer" like. For
2123 this to be true, its size must be less than or equal to
2124 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2125 subfield must be zero. Note that bit fields are not
2126 addressable, and unions always start at offset zero. If any
2127 of the subfields is a floating point type, the struct/union
2128 cannot be an integer type. */
2130 /* For each field in the object, check:
2131 1) Is it FP? --> yes, nRc = 1;
2132 2) Is it addressable (bitpos != 0) and
2133 not packed (bitsize == 0)?
2137 for (i = 0; i < TYPE_NFIELDS (type); i++)
2139 enum type_code field_type_code;
2140 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2142 /* Is it a floating point type field? */
2143 if (field_type_code == TYPE_CODE_FLT)
2149 /* If bitpos != 0, then we have to care about it. */
2150 if (TYPE_FIELD_BITPOS (type, i) != 0)
2152 /* Bitfields are not addressable. If the field bitsize is
2153 zero, then the field is not packed. Hence it cannot be
2154 a bitfield or any other packed type. */
2155 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2167 /* Write into appropriate registers a function return value of type
2168 TYPE, given in virtual format. */
2171 arm_store_return_value (struct type *type, struct regcache *regs,
2172 const gdb_byte *valbuf)
2174 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2176 char buf[MAX_REGISTER_SIZE];
2178 switch (gdbarch_tdep (current_gdbarch)->fp_model)
2182 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2183 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2186 case ARM_FLOAT_SOFT_FPA:
2187 case ARM_FLOAT_SOFT_VFP:
2188 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2189 if (TYPE_LENGTH (type) > 4)
2190 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2191 valbuf + INT_REGISTER_SIZE);
2196 (__FILE__, __LINE__,
2197 _("arm_store_return_value: Floating point model not supported"));
2201 else if (TYPE_CODE (type) == TYPE_CODE_INT
2202 || TYPE_CODE (type) == TYPE_CODE_CHAR
2203 || TYPE_CODE (type) == TYPE_CODE_BOOL
2204 || TYPE_CODE (type) == TYPE_CODE_PTR
2205 || TYPE_CODE (type) == TYPE_CODE_REF
2206 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2208 if (TYPE_LENGTH (type) <= 4)
2210 /* Values of one word or less are zero/sign-extended and
2212 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2213 LONGEST val = unpack_long (type, valbuf);
2215 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2216 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2220 /* Integral values greater than one word are stored in consecutive
2221 registers starting with r0. This will always be a multiple of
2222 the regiser size. */
2223 int len = TYPE_LENGTH (type);
2224 int regno = ARM_A1_REGNUM;
2228 regcache_cooked_write (regs, regno++, valbuf);
2229 len -= INT_REGISTER_SIZE;
2230 valbuf += INT_REGISTER_SIZE;
2236 /* For a structure or union the behaviour is as if the value had
2237 been stored to word-aligned memory and then loaded into
2238 registers with 32-bit load instruction(s). */
2239 int len = TYPE_LENGTH (type);
2240 int regno = ARM_A1_REGNUM;
2241 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2245 memcpy (tmpbuf, valbuf,
2246 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2247 regcache_cooked_write (regs, regno++, tmpbuf);
2248 len -= INT_REGISTER_SIZE;
2249 valbuf += INT_REGISTER_SIZE;
2255 /* Handle function return values. */
2257 static enum return_value_convention
2258 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2259 struct regcache *regcache, gdb_byte *readbuf,
2260 const gdb_byte *writebuf)
2262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2264 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2265 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2266 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2268 if (tdep->struct_return == pcc_struct_return
2269 || arm_return_in_memory (gdbarch, valtype))
2270 return RETURN_VALUE_STRUCT_CONVENTION;
2274 arm_store_return_value (valtype, regcache, writebuf);
2277 arm_extract_return_value (valtype, regcache, readbuf);
2279 return RETURN_VALUE_REGISTER_CONVENTION;
2284 arm_get_longjmp_target (CORE_ADDR *pc)
2287 char buf[INT_REGISTER_SIZE];
2288 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2290 jb_addr = read_register (ARM_A1_REGNUM);
2292 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2296 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2300 /* Return non-zero if the PC is inside a thumb call thunk. */
2303 arm_in_call_stub (CORE_ADDR pc, char *name)
2305 CORE_ADDR start_addr;
2307 /* Find the starting address of the function containing the PC. If
2308 the caller didn't give us a name, look it up at the same time. */
2309 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2313 return strncmp (name, "_call_via_r", 11) == 0;
2316 /* If PC is in a Thumb call or return stub, return the address of the
2317 target PC, which is in a register. The thunk functions are called
2318 _called_via_xx, where x is the register name. The possible names
2319 are r0-r9, sl, fp, ip, sp, and lr. */
2322 arm_skip_stub (CORE_ADDR pc)
2325 CORE_ADDR start_addr;
2327 /* Find the starting address and name of the function containing the PC. */
2328 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2331 /* Call thunks always start with "_call_via_". */
2332 if (strncmp (name, "_call_via_", 10) == 0)
2334 /* Use the name suffix to determine which register contains the
2336 static char *table[15] =
2337 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2338 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2342 for (regno = 0; regno <= 14; regno++)
2343 if (strcmp (&name[10], table[regno]) == 0)
2344 return read_register (regno);
2347 return 0; /* not a stub */
2351 set_arm_command (char *args, int from_tty)
2353 printf_unfiltered (_("\
2354 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2355 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2359 show_arm_command (char *args, int from_tty)
2361 cmd_show_list (showarmcmdlist, from_tty, "");
2365 arm_update_current_architecture (void)
2367 struct gdbarch_info info;
2369 /* If the current architecture is not ARM, we have nothing to do. */
2370 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2373 /* Update the architecture. */
2374 gdbarch_info_init (&info);
2376 if (!gdbarch_update_p (info))
2377 internal_error (__FILE__, __LINE__, "could not update architecture");
2381 set_fp_model_sfunc (char *args, int from_tty,
2382 struct cmd_list_element *c)
2384 enum arm_float_model fp_model;
2386 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2387 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2389 arm_fp_model = fp_model;
2393 if (fp_model == ARM_FLOAT_LAST)
2394 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2397 arm_update_current_architecture ();
2401 show_fp_model (struct ui_file *file, int from_tty,
2402 struct cmd_list_element *c, const char *value)
2404 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2406 if (arm_fp_model == ARM_FLOAT_AUTO
2407 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2408 fprintf_filtered (file, _("\
2409 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2410 fp_model_strings[tdep->fp_model]);
2412 fprintf_filtered (file, _("\
2413 The current ARM floating point model is \"%s\".\n"),
2414 fp_model_strings[arm_fp_model]);
2418 arm_set_abi (char *args, int from_tty,
2419 struct cmd_list_element *c)
2421 enum arm_abi_kind arm_abi;
2423 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2424 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2426 arm_abi_global = arm_abi;
2430 if (arm_abi == ARM_ABI_LAST)
2431 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2434 arm_update_current_architecture ();
2438 arm_show_abi (struct ui_file *file, int from_tty,
2439 struct cmd_list_element *c, const char *value)
2441 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2443 if (arm_abi_global == ARM_ABI_AUTO
2444 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2445 fprintf_filtered (file, _("\
2446 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2447 arm_abi_strings[tdep->arm_abi]);
2449 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2453 /* If the user changes the register disassembly style used for info
2454 register and other commands, we have to also switch the style used
2455 in opcodes for disassembly output. This function is run in the "set
2456 arm disassembly" command, and does that. */
2459 set_disassembly_style_sfunc (char *args, int from_tty,
2460 struct cmd_list_element *c)
2462 set_disassembly_style ();
2465 /* Return the ARM register name corresponding to register I. */
2467 arm_register_name (int i)
2469 return arm_register_names[i];
2473 set_disassembly_style (void)
2475 const char *setname, *setdesc, *const *regnames;
2478 /* Find the style that the user wants in the opcodes table. */
2480 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2481 while ((disassembly_style != setname)
2482 && (current < num_disassembly_options))
2483 get_arm_regnames (++current, &setname, &setdesc, ®names);
2484 current_option = current;
2486 /* Fill our copy. */
2487 for (j = 0; j < numregs; j++)
2488 arm_register_names[j] = (char *) regnames[j];
2491 if (isupper (*regnames[ARM_PC_REGNUM]))
2493 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2494 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2498 arm_register_names[ARM_FPS_REGNUM] = "fps";
2499 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2502 /* Synchronize the disassembler. */
2503 set_arm_regname_option (current);
2506 /* Test whether the coff symbol specific value corresponds to a Thumb
2510 coff_sym_is_thumb (int val)
2512 return (val == C_THUMBEXT ||
2513 val == C_THUMBSTAT ||
2514 val == C_THUMBEXTFUNC ||
2515 val == C_THUMBSTATFUNC ||
2516 val == C_THUMBLABEL);
2519 /* arm_coff_make_msymbol_special()
2520 arm_elf_make_msymbol_special()
2522 These functions test whether the COFF or ELF symbol corresponds to
2523 an address in thumb code, and set a "special" bit in a minimal
2524 symbol to indicate that it does. */
2527 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2529 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2531 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2533 MSYMBOL_SET_SPECIAL (msym);
2537 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2539 if (coff_sym_is_thumb (val))
2540 MSYMBOL_SET_SPECIAL (msym);
2544 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2546 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2548 /* If necessary, set the T bit. */
2551 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2552 if (arm_pc_is_thumb (pc))
2553 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2555 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2559 static enum gdb_osabi
2560 arm_elf_osabi_sniffer (bfd *abfd)
2562 unsigned int elfosabi;
2563 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2565 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2567 if (elfosabi == ELFOSABI_ARM)
2568 /* GNU tools use this value. Check note sections in this case,
2570 bfd_map_over_sections (abfd,
2571 generic_elf_osabi_sniff_abi_tag_sections,
2574 /* Anything else will be handled by the generic ELF sniffer. */
2579 /* Initialize the current architecture based on INFO. If possible,
2580 re-use an architecture from ARCHES, which is a list of
2581 architectures already created during this debugging session.
2583 Called e.g. at program startup, when reading a core file, and when
2584 reading a binary file. */
2586 static struct gdbarch *
2587 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2589 struct gdbarch_tdep *tdep;
2590 struct gdbarch *gdbarch;
2591 struct gdbarch_list *best_arch;
2592 enum arm_abi_kind arm_abi = arm_abi_global;
2593 enum arm_float_model fp_model = arm_fp_model;
2595 /* If we have an object to base this architecture on, try to determine
2598 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2600 int ei_osabi, e_flags;
2602 switch (bfd_get_flavour (info.abfd))
2604 case bfd_target_aout_flavour:
2605 /* Assume it's an old APCS-style ABI. */
2606 arm_abi = ARM_ABI_APCS;
2609 case bfd_target_coff_flavour:
2610 /* Assume it's an old APCS-style ABI. */
2612 arm_abi = ARM_ABI_APCS;
2615 case bfd_target_elf_flavour:
2616 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2617 e_flags = elf_elfheader (info.abfd)->e_flags;
2619 if (ei_osabi == ELFOSABI_ARM)
2621 /* GNU tools used to use this value, but do not for EABI
2622 objects. There's nowhere to tag an EABI version
2623 anyway, so assume APCS. */
2624 arm_abi = ARM_ABI_APCS;
2626 else if (ei_osabi == ELFOSABI_NONE)
2628 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2632 case EF_ARM_EABI_UNKNOWN:
2633 /* Assume GNU tools. */
2634 arm_abi = ARM_ABI_APCS;
2637 case EF_ARM_EABI_VER4:
2638 case EF_ARM_EABI_VER5:
2639 arm_abi = ARM_ABI_AAPCS;
2640 /* EABI binaries default to VFP float ordering. */
2641 if (fp_model == ARM_FLOAT_AUTO)
2642 fp_model = ARM_FLOAT_SOFT_VFP;
2646 /* Leave it as "auto". */
2647 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2652 if (fp_model == ARM_FLOAT_AUTO)
2654 int e_flags = elf_elfheader (info.abfd)->e_flags;
2656 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2659 /* Leave it as "auto". Strictly speaking this case
2660 means FPA, but almost nobody uses that now, and
2661 many toolchains fail to set the appropriate bits
2662 for the floating-point model they use. */
2664 case EF_ARM_SOFT_FLOAT:
2665 fp_model = ARM_FLOAT_SOFT_FPA;
2667 case EF_ARM_VFP_FLOAT:
2668 fp_model = ARM_FLOAT_VFP;
2670 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2671 fp_model = ARM_FLOAT_SOFT_VFP;
2678 /* Leave it as "auto". */
2683 /* Now that we have inferred any architecture settings that we
2684 can, try to inherit from the last ARM ABI. */
2687 if (arm_abi == ARM_ABI_AUTO)
2688 arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi;
2690 if (fp_model == ARM_FLOAT_AUTO)
2691 fp_model = gdbarch_tdep (arches->gdbarch)->fp_model;
2695 /* There was no prior ARM architecture; fill in default values. */
2697 if (arm_abi == ARM_ABI_AUTO)
2698 arm_abi = ARM_ABI_APCS;
2700 /* We used to default to FPA for generic ARM, but almost nobody
2701 uses that now, and we now provide a way for the user to force
2702 the model. So default to the most useful variant. */
2703 if (fp_model == ARM_FLOAT_AUTO)
2704 fp_model = ARM_FLOAT_SOFT_FPA;
2707 /* If there is already a candidate, use it. */
2708 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2710 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2712 if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2715 if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2718 /* Found a match. */
2722 if (best_arch != NULL)
2723 return best_arch->gdbarch;
2725 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2726 gdbarch = gdbarch_alloc (&info, tdep);
2728 /* Record additional information about the architecture we are defining.
2729 These are gdbarch discriminators, like the OSABI. */
2730 tdep->arm_abi = arm_abi;
2731 tdep->fp_model = fp_model;
2734 switch (info.byte_order)
2736 case BFD_ENDIAN_BIG:
2737 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2738 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2739 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2740 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2744 case BFD_ENDIAN_LITTLE:
2745 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2746 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2747 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2748 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2753 internal_error (__FILE__, __LINE__,
2754 _("arm_gdbarch_init: bad byte order for float format"));
2757 /* On ARM targets char defaults to unsigned. */
2758 set_gdbarch_char_signed (gdbarch, 0);
2760 /* This should be low enough for everything. */
2761 tdep->lowest_pc = 0x20;
2762 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2764 /* The default, for both APCS and AAPCS, is to return small
2765 structures in registers. */
2766 tdep->struct_return = reg_struct_return;
2768 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2769 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2771 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2773 /* Frame handling. */
2774 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2775 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2776 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2778 frame_base_set_default (gdbarch, &arm_normal_base);
2780 /* Address manipulation. */
2781 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2782 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2784 /* Advance PC across function entry code. */
2785 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2787 /* The stack grows downward. */
2788 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2790 /* Breakpoint manipulation. */
2791 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2793 /* Information about registers, etc. */
2794 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2795 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2796 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2797 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2798 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2799 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2800 set_gdbarch_register_type (gdbarch, arm_register_type);
2802 /* Internal <-> external register number maps. */
2803 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2805 /* Integer registers are 4 bytes. */
2806 set_gdbarch_deprecated_register_size (gdbarch, 4);
2807 set_gdbarch_register_name (gdbarch, arm_register_name);
2809 /* Returning results. */
2810 set_gdbarch_return_value (gdbarch, arm_return_value);
2812 /* Single stepping. */
2813 /* XXX For an RDI target we should ask the target if it can single-step. */
2814 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2817 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2819 /* Minsymbol frobbing. */
2820 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2821 set_gdbarch_coff_make_msymbol_special (gdbarch,
2822 arm_coff_make_msymbol_special);
2824 /* Hook in the ABI-specific overrides, if they have been registered. */
2825 gdbarch_init_osabi (info, gdbarch);
2827 /* Add some default predicates. */
2828 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
2829 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2830 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2832 /* Now we have tuned the configuration, set a few final things,
2833 based on what the OS ABI has told us. */
2835 if (tdep->jb_pc >= 0)
2836 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2838 /* Floating point sizes and format. */
2839 switch (info.byte_order)
2841 case BFD_ENDIAN_BIG:
2842 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2843 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2844 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2847 case BFD_ENDIAN_LITTLE:
2848 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2849 if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA)
2851 set_gdbarch_double_format
2852 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2853 set_gdbarch_long_double_format
2854 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2858 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2859 set_gdbarch_long_double_format (gdbarch,
2860 &floatformat_ieee_double_little);
2865 internal_error (__FILE__, __LINE__,
2866 _("arm_gdbarch_init: bad byte order for float format"));
2873 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2875 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2880 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2881 (unsigned long) tdep->lowest_pc);
2884 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2887 _initialize_arm_tdep (void)
2889 struct ui_file *stb;
2891 struct cmd_list_element *new_set, *new_show;
2892 const char *setname;
2893 const char *setdesc;
2894 const char *const *regnames;
2896 static char *helptext;
2897 char regdesc[1024], *rdptr = regdesc;
2898 size_t rest = sizeof (regdesc);
2900 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2902 /* Register an ELF OS ABI sniffer for ARM binaries. */
2903 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2904 bfd_target_elf_flavour,
2905 arm_elf_osabi_sniffer);
2907 /* Get the number of possible sets of register names defined in opcodes. */
2908 num_disassembly_options = get_arm_regname_num_options ();
2910 /* Add root prefix command for all "set arm"/"show arm" commands. */
2911 add_prefix_cmd ("arm", no_class, set_arm_command,
2912 _("Various ARM-specific commands."),
2913 &setarmcmdlist, "set arm ", 0, &setlist);
2915 add_prefix_cmd ("arm", no_class, show_arm_command,
2916 _("Various ARM-specific commands."),
2917 &showarmcmdlist, "show arm ", 0, &showlist);
2919 /* Sync the opcode insn printer with our register viewer. */
2920 parse_arm_disassembler_option ("reg-names-std");
2922 /* Initialize the array that will be passed to
2923 add_setshow_enum_cmd(). */
2924 valid_disassembly_styles
2925 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2926 for (i = 0; i < num_disassembly_options; i++)
2928 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2929 valid_disassembly_styles[i] = setname;
2930 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
2933 /* Copy the default names (if found) and synchronize disassembler. */
2934 if (!strcmp (setname, "std"))
2936 disassembly_style = setname;
2938 for (j = 0; j < numregs; j++)
2939 arm_register_names[j] = (char *) regnames[j];
2940 set_arm_regname_option (i);
2943 /* Mark the end of valid options. */
2944 valid_disassembly_styles[num_disassembly_options] = NULL;
2946 /* Create the help text. */
2947 stb = mem_fileopen ();
2948 fprintf_unfiltered (stb, "%s%s%s",
2949 _("The valid values are:\n"),
2951 _("The default is \"std\"."));
2952 helptext = ui_file_xstrdup (stb, &length);
2953 ui_file_delete (stb);
2955 add_setshow_enum_cmd("disassembler", no_class,
2956 valid_disassembly_styles, &disassembly_style,
2957 _("Set the disassembly style."),
2958 _("Show the disassembly style."),
2960 set_disassembly_style_sfunc,
2961 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
2962 &setarmcmdlist, &showarmcmdlist);
2964 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2965 _("Set usage of ARM 32-bit mode."),
2966 _("Show usage of ARM 32-bit mode."),
2967 _("When off, a 26-bit PC will be used."),
2969 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2970 &setarmcmdlist, &showarmcmdlist);
2972 /* Add a command to allow the user to force the FPU model. */
2973 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2974 _("Set the floating point type."),
2975 _("Show the floating point type."),
2976 _("auto - Determine the FP typefrom the OS-ABI.\n\
2977 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2978 fpa - FPA co-processor (GCC compiled).\n\
2979 softvfp - Software FP with pure-endian doubles.\n\
2980 vfp - VFP co-processor."),
2981 set_fp_model_sfunc, show_fp_model,
2982 &setarmcmdlist, &showarmcmdlist);
2984 /* Add a command to allow the user to force the ABI. */
2985 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
2988 NULL, arm_set_abi, arm_show_abi,
2989 &setarmcmdlist, &showarmcmdlist);
2991 /* Debugging flag. */
2992 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2993 _("Set ARM debugging."),
2994 _("Show ARM debugging."),
2995 _("When on, arm-specific debugging is enabled."),
2997 NULL, /* FIXME: i18n: "ARM debugging is %s. */
2998 &setdebuglist, &showdebuglist);