1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper () */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
33 #include "arch-utils.h"
35 #include "frame-unwind.h"
36 #include "frame-base.h"
37 #include "trad-frame.h"
39 #include "dwarf2-frame.h"
41 #include "prologue-value.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element *setarmcmdlist = NULL;
72 static struct cmd_list_element *showarmcmdlist = NULL;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
88 static const char *current_fp_model = "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
101 static const char *arm_abi_string = "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options;
106 /* The standard register names, and all the valid aliases for them. */
111 } arm_register_aliases[] = {
112 /* Basic register numbers. */
129 /* Synonyms (argument and variable registers). */
142 /* Other platform-specific names for r9. */
150 /* Names used by GCC (not listed in the ARM EABI). */
153 /* A special name from the older ATPCS. */
157 static const char *const arm_register_names[] =
158 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
159 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
160 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
161 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
162 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
163 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
164 "fps", "cpsr" }; /* 24 25 */
166 /* Valid register name styles. */
167 static const char **valid_disassembly_styles;
169 /* Disassembly style to use. Default to "std" register names. */
170 static const char *disassembly_style;
172 /* This is used to keep the bfd arch_info in sync with the disassembly
174 static void set_disassembly_style_sfunc(char *, int,
175 struct cmd_list_element *);
176 static void set_disassembly_style (void);
178 static void convert_from_extended (const struct floatformat *, const void *,
180 static void convert_to_extended (const struct floatformat *, void *,
183 struct arm_prologue_cache
185 /* The stack pointer at the time this frame was created; i.e. the
186 caller's stack pointer when this function was called. It is used
187 to identify this frame. */
190 /* The frame base for this frame is just prev_sp + frame offset -
191 frame size. FRAMESIZE is the size of this stack frame, and
192 FRAMEOFFSET if the initial offset from the stack pointer (this
193 frame's stack pointer, not PREV_SP) to the frame base. */
198 /* The register used to hold the frame pointer for this frame. */
201 /* Saved register offsets. */
202 struct trad_frame_saved_reg *saved_regs;
205 /* Addresses for calling Thumb functions have the bit 0 set.
206 Here are some macros to test, set, or clear bit 0 of addresses. */
207 #define IS_THUMB_ADDR(addr) ((addr) & 1)
208 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
209 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
211 /* Set to true if the 32-bit mode is in use. */
215 /* Determine if the program counter specified in MEMADDR is in a Thumb
219 arm_pc_is_thumb (CORE_ADDR memaddr)
221 struct minimal_symbol *sym;
223 /* If bit 0 of the address is set, assume this is a Thumb address. */
224 if (IS_THUMB_ADDR (memaddr))
227 /* Thumb functions have a "special" bit set in minimal symbols. */
228 sym = lookup_minimal_symbol_by_pc (memaddr);
231 return (MSYMBOL_IS_SPECIAL (sym));
239 /* Remove useless bits from addresses in a running program. */
241 arm_addr_bits_remove (CORE_ADDR val)
244 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
246 return (val & 0x03fffffc);
249 /* When reading symbols, we need to zap the low bit of the address,
250 which may be set to 1 for Thumb functions. */
252 arm_smash_text_address (CORE_ADDR val)
257 /* Analyze a Thumb prologue, looking for a recognizable stack frame
258 and frame pointer. Scan until we encounter a store that could
259 clobber the stack frame unexpectedly, or an unknown instruction. */
262 thumb_analyze_prologue (struct gdbarch *gdbarch,
263 CORE_ADDR start, CORE_ADDR limit,
264 struct arm_prologue_cache *cache)
268 struct pv_area *stack;
269 struct cleanup *back_to;
272 for (i = 0; i < 16; i++)
273 regs[i] = pv_register (i, 0);
274 stack = make_pv_area (ARM_SP_REGNUM);
275 back_to = make_cleanup_free_pv_area (stack);
277 /* The call instruction saved PC in LR, and the current PC is not
278 interesting. Due to this file's conventions, we want the value
279 of LR at this function's entry, not at the call site, so we do
280 not record the save of the PC - when the ARM prologue analyzer
281 has also been converted to the pv mechanism, we could record the
282 save here and remove the hack in prev_register. */
283 regs[ARM_PC_REGNUM] = pv_unknown ();
285 while (start < limit)
289 insn = read_memory_unsigned_integer (start, 2);
291 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
297 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
298 whether to save LR (R14). */
299 mask = (insn & 0xff) | ((insn & 0x100) << 6);
301 /* Calculate offsets of saved R0-R7 and LR. */
302 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
303 if (mask & (1 << regno))
305 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
311 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
313 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
319 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
322 offset = (insn & 0x7f) << 2; /* get scaled offset */
323 if (insn & 0x80) /* Check for SUB. */
324 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
327 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
330 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
331 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
333 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
335 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
336 int src_reg = (insn & 0x78) >> 3;
337 regs[dst_reg] = regs[src_reg];
339 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
341 /* Handle stores to the stack. Normally pushes are used,
342 but with GCC -mtpcs-frame, there may be other stores
343 in the prologue to create the frame. */
344 int regno = (insn >> 8) & 0x7;
347 offset = (insn & 0xff) << 2;
348 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
350 if (pv_area_store_would_trash (stack, addr))
353 pv_area_store (stack, addr, 4, regs[regno]);
357 /* We don't know what this instruction is. We're finished
358 scanning. NOTE: Recognizing more safe-to-ignore
359 instructions here will improve support for optimized
369 do_cleanups (back_to);
373 /* frameoffset is unused for this unwinder. */
374 cache->frameoffset = 0;
376 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
378 /* Frame pointer is fp. Frame size is constant. */
379 cache->framereg = ARM_FP_REGNUM;
380 cache->framesize = -regs[ARM_FP_REGNUM].k;
382 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
384 /* Frame pointer is r7. Frame size is constant. */
385 cache->framereg = THUMB_FP_REGNUM;
386 cache->framesize = -regs[THUMB_FP_REGNUM].k;
388 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
390 /* Try the stack pointer... this is a bit desperate. */
391 cache->framereg = ARM_SP_REGNUM;
392 cache->framesize = -regs[ARM_SP_REGNUM].k;
396 /* We're just out of luck. We don't know where the frame is. */
397 cache->framereg = -1;
398 cache->framesize = 0;
401 for (i = 0; i < 16; i++)
402 if (pv_area_find_reg (stack, gdbarch, i, &offset))
403 cache->saved_regs[i].addr = offset;
405 do_cleanups (back_to);
409 /* Advance the PC across any function entry prologue instructions to
410 reach some "real" code.
412 The APCS (ARM Procedure Call Standard) defines the following
416 [stmfd sp!, {a1,a2,a3,a4}]
417 stmfd sp!, {...,fp,ip,lr,pc}
418 [stfe f7, [sp, #-12]!]
419 [stfe f6, [sp, #-12]!]
420 [stfe f5, [sp, #-12]!]
421 [stfe f4, [sp, #-12]!]
422 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
425 arm_skip_prologue (CORE_ADDR pc)
429 CORE_ADDR func_addr, func_end = 0;
431 struct symtab_and_line sal;
433 /* If we're in a dummy frame, don't even try to skip the prologue. */
434 if (deprecated_pc_in_call_dummy (pc))
437 /* See what the symbol table says. */
439 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
443 /* Found a function. */
444 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
445 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
447 /* Don't use this trick for assembly source files. */
448 sal = find_pc_line (func_addr, 0);
449 if ((sal.line != 0) && (sal.end < func_end))
454 /* Can't find the prologue end in the symbol table, try it the hard way
455 by disassembling the instructions. */
457 /* Like arm_scan_prologue, stop no later than pc + 64. */
458 if (func_end == 0 || func_end > pc + 64)
461 /* Check if this is Thumb code. */
462 if (arm_pc_is_thumb (pc))
463 return thumb_analyze_prologue (current_gdbarch, pc, func_end, NULL);
465 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
467 inst = read_memory_unsigned_integer (skip_pc, 4);
469 /* "mov ip, sp" is no longer a required part of the prologue. */
470 if (inst == 0xe1a0c00d) /* mov ip, sp */
473 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
476 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
479 /* Some prologues begin with "str lr, [sp, #-4]!". */
480 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
483 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
486 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
489 /* Any insns after this point may float into the code, if it makes
490 for better instruction scheduling, so we skip them only if we
491 find them, but still consider the function to be frame-ful. */
493 /* We may have either one sfmfd instruction here, or several stfe
494 insns, depending on the version of floating point code we
496 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
499 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
502 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
505 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
508 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
509 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
510 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
513 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
514 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
515 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
518 /* Un-recognized instruction; stop scanning. */
522 return skip_pc; /* End of prologue */
526 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
527 This function decodes a Thumb function prologue to determine:
528 1) the size of the stack frame
529 2) which registers are saved on it
530 3) the offsets of saved regs
531 4) the offset from the stack pointer to the frame pointer
533 A typical Thumb function prologue would create this stack frame
534 (offsets relative to FP)
535 old SP -> 24 stack parameters
538 R7 -> 0 local variables (16 bytes)
539 SP -> -12 additional stack space (12 bytes)
540 The frame size would thus be 36 bytes, and the frame offset would be
541 12 bytes. The frame register is R7.
543 The comments for thumb_skip_prolog() describe the algorithm we use
544 to detect the end of the prolog. */
548 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
550 CORE_ADDR prologue_start;
551 CORE_ADDR prologue_end;
552 CORE_ADDR current_pc;
553 /* Which register has been copied to register n? */
556 bit 0 - push { rlist }
557 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
558 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
563 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
565 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
567 if (sal.line == 0) /* no line info, use current PC */
568 prologue_end = prev_pc;
569 else if (sal.end < prologue_end) /* next line begins after fn end */
570 prologue_end = sal.end; /* (probably means no prologue) */
573 /* We're in the boondocks: we have no idea where the start of the
577 prologue_end = min (prologue_end, prev_pc);
579 thumb_analyze_prologue (current_gdbarch, prologue_start, prologue_end,
583 /* This function decodes an ARM function prologue to determine:
584 1) the size of the stack frame
585 2) which registers are saved on it
586 3) the offsets of saved regs
587 4) the offset from the stack pointer to the frame pointer
588 This information is stored in the "extra" fields of the frame_info.
590 There are two basic forms for the ARM prologue. The fixed argument
591 function call will look like:
594 stmfd sp!, {fp, ip, lr, pc}
598 Which would create this stack frame (offsets relative to FP):
599 IP -> 4 (caller's stack)
600 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
601 -4 LR (return address in caller)
602 -8 IP (copy of caller's SP)
604 SP -> -28 Local variables
606 The frame size would thus be 32 bytes, and the frame offset would be
607 28 bytes. The stmfd call can also save any of the vN registers it
608 plans to use, which increases the frame size accordingly.
610 Note: The stored PC is 8 off of the STMFD instruction that stored it
611 because the ARM Store instructions always store PC + 8 when you read
614 A variable argument function call will look like:
617 stmfd sp!, {a1, a2, a3, a4}
618 stmfd sp!, {fp, ip, lr, pc}
621 Which would create this stack frame (offsets relative to FP):
622 IP -> 20 (caller's stack)
627 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
628 -4 LR (return address in caller)
629 -8 IP (copy of caller's SP)
631 SP -> -28 Local variables
633 The frame size would thus be 48 bytes, and the frame offset would be
636 There is another potential complication, which is that the optimizer
637 will try to separate the store of fp in the "stmfd" instruction from
638 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
639 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
641 Also, note, the original version of the ARM toolchain claimed that there
644 instruction at the end of the prologue. I have never seen GCC produce
645 this, and the ARM docs don't mention it. We still test for it below in
651 arm_scan_prologue (struct frame_info *next_frame,
652 struct arm_prologue_cache *cache)
654 struct gdbarch *gdbarch = get_frame_arch (next_frame);
655 int regno, sp_offset, fp_offset, ip_offset;
656 CORE_ADDR prologue_start, prologue_end, current_pc;
657 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
659 /* Assume there is no frame until proven otherwise. */
660 cache->framereg = ARM_SP_REGNUM;
661 cache->framesize = 0;
662 cache->frameoffset = 0;
664 /* Check for Thumb prologue. */
665 if (arm_pc_is_thumb (prev_pc))
667 thumb_scan_prologue (prev_pc, cache);
671 /* Find the function prologue. If we can't find the function in
672 the symbol table, peek in the stack frame to find the PC. */
673 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
675 /* One way to find the end of the prologue (which works well
676 for unoptimized code) is to do the following:
678 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
681 prologue_end = prev_pc;
682 else if (sal.end < prologue_end)
683 prologue_end = sal.end;
685 This mechanism is very accurate so long as the optimizer
686 doesn't move any instructions from the function body into the
687 prologue. If this happens, sal.end will be the last
688 instruction in the first hunk of prologue code just before
689 the first instruction that the scheduler has moved from
690 the body to the prologue.
692 In order to make sure that we scan all of the prologue
693 instructions, we use a slightly less accurate mechanism which
694 may scan more than necessary. To help compensate for this
695 lack of accuracy, the prologue scanning loop below contains
696 several clauses which'll cause the loop to terminate early if
697 an implausible prologue instruction is encountered.
703 is a suitable endpoint since it accounts for the largest
704 possible prologue plus up to five instructions inserted by
707 if (prologue_end > prologue_start + 64)
709 prologue_end = prologue_start + 64; /* See above. */
714 /* We have no symbol information. Our only option is to assume this
715 function has a standard stack frame and the normal frame register.
716 Then, we can find the value of our frame pointer on entrance to
717 the callee (or at the present moment if this is the innermost frame).
718 The value stored there should be the address of the stmfd + 8. */
720 LONGEST return_value;
722 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
723 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
727 prologue_start = gdbarch_addr_bits_remove
728 (gdbarch, return_value) - 8;
729 prologue_end = prologue_start + 64; /* See above. */
733 if (prev_pc < prologue_end)
734 prologue_end = prev_pc;
736 /* Now search the prologue looking for instructions that set up the
737 frame pointer, adjust the stack pointer, and save registers.
739 Be careful, however, and if it doesn't look like a prologue,
740 don't try to scan it. If, for instance, a frameless function
741 begins with stmfd sp!, then we will tell ourselves there is
742 a frame, which will confuse stack traceback, as well as "finish"
743 and other operations that rely on a knowledge of the stack
746 In the APCS, the prologue should start with "mov ip, sp" so
747 if we don't see this as the first insn, we will stop.
749 [Note: This doesn't seem to be true any longer, so it's now an
750 optional part of the prologue. - Kevin Buettner, 2001-11-20]
752 [Note further: The "mov ip,sp" only seems to be missing in
753 frameless functions at optimization level "-O2" or above,
754 in which case it is often (but not always) replaced by
755 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
757 sp_offset = fp_offset = ip_offset = 0;
759 for (current_pc = prologue_start;
760 current_pc < prologue_end;
763 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
765 if (insn == 0xe1a0c00d) /* mov ip, sp */
770 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
772 unsigned imm = insn & 0xff; /* immediate value */
773 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
774 imm = (imm >> rot) | (imm << (32 - rot));
778 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
780 unsigned imm = insn & 0xff; /* immediate value */
781 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
782 imm = (imm >> rot) | (imm << (32 - rot));
786 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
789 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
792 else if ((insn & 0xffff0000) == 0xe92d0000)
793 /* stmfd sp!, {..., fp, ip, lr, pc}
795 stmfd sp!, {a1, a2, a3, a4} */
797 int mask = insn & 0xffff;
799 /* Calculate offsets of saved registers. */
800 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
801 if (mask & (1 << regno))
804 cache->saved_regs[regno].addr = sp_offset;
807 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
808 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
809 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
811 /* No need to add this to saved_regs -- it's just an arg reg. */
814 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
815 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
816 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
818 /* No need to add this to saved_regs -- it's just an arg reg. */
821 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
823 unsigned imm = insn & 0xff; /* immediate value */
824 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
825 imm = (imm >> rot) | (imm << (32 - rot));
826 fp_offset = -imm + ip_offset;
827 cache->framereg = ARM_FP_REGNUM;
829 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
831 unsigned imm = insn & 0xff; /* immediate value */
832 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
833 imm = (imm >> rot) | (imm << (32 - rot));
836 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
837 && gdbarch_tdep (gdbarch)->have_fpa_registers)
840 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
841 cache->saved_regs[regno].addr = sp_offset;
843 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
844 && gdbarch_tdep (gdbarch)->have_fpa_registers)
847 unsigned int fp_start_reg, fp_bound_reg;
849 if ((insn & 0x800) == 0x800) /* N0 is set */
851 if ((insn & 0x40000) == 0x40000) /* N1 is set */
858 if ((insn & 0x40000) == 0x40000) /* N1 is set */
864 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
865 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
866 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
869 cache->saved_regs[fp_start_reg++].addr = sp_offset;
872 else if ((insn & 0xf0000000) != 0xe0000000)
873 break; /* Condition not true, exit early */
874 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
875 break; /* Don't scan past a block load */
877 /* The optimizer might shove anything into the prologue,
878 so we just skip what we don't recognize. */
882 /* The frame size is just the negative of the offset (from the
883 original SP) of the last thing thing we pushed on the stack.
884 The frame offset is [new FP] - [new SP]. */
885 cache->framesize = -sp_offset;
886 if (cache->framereg == ARM_FP_REGNUM)
887 cache->frameoffset = fp_offset - sp_offset;
889 cache->frameoffset = 0;
892 static struct arm_prologue_cache *
893 arm_make_prologue_cache (struct frame_info *next_frame)
896 struct arm_prologue_cache *cache;
897 CORE_ADDR unwound_fp;
899 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
900 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
902 arm_scan_prologue (next_frame, cache);
904 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
908 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
910 /* Calculate actual addresses of saved registers using offsets
911 determined by arm_scan_prologue. */
912 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (next_frame)); reg++)
913 if (trad_frame_addr_p (cache->saved_regs, reg))
914 cache->saved_regs[reg].addr += cache->prev_sp;
919 /* Our frame ID for a normal frame is the current function's starting PC
920 and the caller's SP when we were called. */
923 arm_prologue_this_id (struct frame_info *next_frame,
925 struct frame_id *this_id)
927 struct arm_prologue_cache *cache;
931 if (*this_cache == NULL)
932 *this_cache = arm_make_prologue_cache (next_frame);
935 func = frame_func_unwind (next_frame, NORMAL_FRAME);
937 /* This is meant to halt the backtrace at "_start". Make sure we
938 don't halt it at a generic dummy frame. */
939 if (func <= LOWEST_PC)
942 /* If we've hit a wall, stop. */
943 if (cache->prev_sp == 0)
946 id = frame_id_build (cache->prev_sp, func);
951 arm_prologue_prev_register (struct frame_info *next_frame,
955 enum lval_type *lvalp,
960 struct arm_prologue_cache *cache;
962 if (*this_cache == NULL)
963 *this_cache = arm_make_prologue_cache (next_frame);
966 /* If we are asked to unwind the PC, then we need to return the LR
967 instead. The saved value of PC points into this frame's
968 prologue, not the next frame's resume location. */
969 if (prev_regnum == ARM_PC_REGNUM)
970 prev_regnum = ARM_LR_REGNUM;
972 /* SP is generally not saved to the stack, but this frame is
973 identified by NEXT_FRAME's stack pointer at the time of the call.
974 The value was already reconstructed into PREV_SP. */
975 if (prev_regnum == ARM_SP_REGNUM)
979 store_unsigned_integer (valuep, 4, cache->prev_sp);
983 trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum,
984 optimized, lvalp, addrp, realnump, valuep);
987 struct frame_unwind arm_prologue_unwind = {
989 arm_prologue_this_id,
990 arm_prologue_prev_register
993 static const struct frame_unwind *
994 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
996 return &arm_prologue_unwind;
999 static struct arm_prologue_cache *
1000 arm_make_stub_cache (struct frame_info *next_frame)
1003 struct arm_prologue_cache *cache;
1004 CORE_ADDR unwound_fp;
1006 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1007 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1009 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1014 /* Our frame ID for a stub frame is the current SP and LR. */
1017 arm_stub_this_id (struct frame_info *next_frame,
1019 struct frame_id *this_id)
1021 struct arm_prologue_cache *cache;
1023 if (*this_cache == NULL)
1024 *this_cache = arm_make_stub_cache (next_frame);
1025 cache = *this_cache;
1027 *this_id = frame_id_build (cache->prev_sp,
1028 frame_pc_unwind (next_frame));
1031 struct frame_unwind arm_stub_unwind = {
1034 arm_prologue_prev_register
1037 static const struct frame_unwind *
1038 arm_stub_unwind_sniffer (struct frame_info *next_frame)
1040 CORE_ADDR addr_in_block;
1043 addr_in_block = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1044 if (in_plt_section (addr_in_block, NULL)
1045 || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0)
1046 return &arm_stub_unwind;
1052 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1054 struct arm_prologue_cache *cache;
1056 if (*this_cache == NULL)
1057 *this_cache = arm_make_prologue_cache (next_frame);
1058 cache = *this_cache;
1060 return cache->prev_sp + cache->frameoffset - cache->framesize;
1063 struct frame_base arm_normal_base = {
1064 &arm_prologue_unwind,
1065 arm_normal_frame_base,
1066 arm_normal_frame_base,
1067 arm_normal_frame_base
1070 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1071 dummy frame. The frame ID's base needs to match the TOS value
1072 saved by save_dummy_frame_tos() and returned from
1073 arm_push_dummy_call, and the PC needs to match the dummy frame's
1076 static struct frame_id
1077 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1079 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1080 frame_pc_unwind (next_frame));
1083 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1084 be used to construct the previous frame's ID, after looking up the
1085 containing function). */
1088 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1091 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1092 return arm_addr_bits_remove (pc);
1096 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1098 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1101 /* When arguments must be pushed onto the stack, they go on in reverse
1102 order. The code below implements a FILO (stack) to do this. */
1107 struct stack_item *prev;
1111 static struct stack_item *
1112 push_stack_item (struct stack_item *prev, void *contents, int len)
1114 struct stack_item *si;
1115 si = xmalloc (sizeof (struct stack_item));
1116 si->data = xmalloc (len);
1119 memcpy (si->data, contents, len);
1123 static struct stack_item *
1124 pop_stack_item (struct stack_item *si)
1126 struct stack_item *dead = si;
1134 /* Return the alignment (in bytes) of the given type. */
1137 arm_type_align (struct type *t)
1143 t = check_typedef (t);
1144 switch (TYPE_CODE (t))
1147 /* Should never happen. */
1148 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1152 case TYPE_CODE_ENUM:
1156 case TYPE_CODE_RANGE:
1157 case TYPE_CODE_BITSTRING:
1159 case TYPE_CODE_CHAR:
1160 case TYPE_CODE_BOOL:
1161 return TYPE_LENGTH (t);
1163 case TYPE_CODE_ARRAY:
1164 case TYPE_CODE_COMPLEX:
1165 /* TODO: What about vector types? */
1166 return arm_type_align (TYPE_TARGET_TYPE (t));
1168 case TYPE_CODE_STRUCT:
1169 case TYPE_CODE_UNION:
1171 for (n = 0; n < TYPE_NFIELDS (t); n++)
1173 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1181 /* We currently only support passing parameters in integer registers. This
1182 conforms with GCC's default model. Several other variants exist and
1183 we should probably support some of them based on the selected ABI. */
1186 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1187 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1188 struct value **args, CORE_ADDR sp, int struct_return,
1189 CORE_ADDR struct_addr)
1194 struct stack_item *si = NULL;
1196 /* Set the return address. For the ARM, the return breakpoint is
1197 always at BP_ADDR. */
1198 /* XXX Fix for Thumb. */
1199 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1201 /* Walk through the list of args and determine how large a temporary
1202 stack is required. Need to take care here as structs may be
1203 passed on the stack, and we have to to push them. */
1206 argreg = ARM_A1_REGNUM;
1209 /* The struct_return pointer occupies the first parameter
1210 passing register. */
1214 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1215 gdbarch_register_name (gdbarch, argreg),
1216 paddr (struct_addr));
1217 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1221 for (argnum = 0; argnum < nargs; argnum++)
1224 struct type *arg_type;
1225 struct type *target_type;
1226 enum type_code typecode;
1230 arg_type = check_typedef (value_type (args[argnum]));
1231 len = TYPE_LENGTH (arg_type);
1232 target_type = TYPE_TARGET_TYPE (arg_type);
1233 typecode = TYPE_CODE (arg_type);
1234 val = value_contents_writeable (args[argnum]);
1236 align = arm_type_align (arg_type);
1237 /* Round alignment up to a whole number of words. */
1238 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1239 /* Different ABIs have different maximum alignments. */
1240 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1242 /* The APCS ABI only requires word alignment. */
1243 align = INT_REGISTER_SIZE;
1247 /* The AAPCS requires at most doubleword alignment. */
1248 if (align > INT_REGISTER_SIZE * 2)
1249 align = INT_REGISTER_SIZE * 2;
1252 /* Push stack padding for dowubleword alignment. */
1253 if (nstack & (align - 1))
1255 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1256 nstack += INT_REGISTER_SIZE;
1259 /* Doubleword aligned quantities must go in even register pairs. */
1260 if (argreg <= ARM_LAST_ARG_REGNUM
1261 && align > INT_REGISTER_SIZE
1265 /* If the argument is a pointer to a function, and it is a
1266 Thumb function, create a LOCAL copy of the value and set
1267 the THUMB bit in it. */
1268 if (TYPE_CODE_PTR == typecode
1269 && target_type != NULL
1270 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1272 CORE_ADDR regval = extract_unsigned_integer (val, len);
1273 if (arm_pc_is_thumb (regval))
1276 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1280 /* Copy the argument to general registers or the stack in
1281 register-sized pieces. Large arguments are split between
1282 registers and stack. */
1285 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1287 if (argreg <= ARM_LAST_ARG_REGNUM)
1289 /* The argument is being passed in a general purpose
1291 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1292 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1293 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1295 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1297 gdbarch_register_name
1299 phex (regval, INT_REGISTER_SIZE));
1300 regcache_cooked_write_unsigned (regcache, argreg, regval);
1305 /* Push the arguments onto the stack. */
1307 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1309 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1310 nstack += INT_REGISTER_SIZE;
1317 /* If we have an odd number of words to push, then decrement the stack
1318 by one word now, so first stack argument will be dword aligned. */
1325 write_memory (sp, si->data, si->len);
1326 si = pop_stack_item (si);
1329 /* Finally, update teh SP register. */
1330 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1336 /* Always align the frame to an 8-byte boundary. This is required on
1337 some platforms and harmless on the rest. */
1340 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1342 /* Align the stack to eight bytes. */
1343 return sp & ~ (CORE_ADDR) 7;
1347 print_fpu_flags (int flags)
1349 if (flags & (1 << 0))
1350 fputs ("IVO ", stdout);
1351 if (flags & (1 << 1))
1352 fputs ("DVZ ", stdout);
1353 if (flags & (1 << 2))
1354 fputs ("OFL ", stdout);
1355 if (flags & (1 << 3))
1356 fputs ("UFL ", stdout);
1357 if (flags & (1 << 4))
1358 fputs ("INX ", stdout);
1362 /* Print interesting information about the floating point processor
1363 (if present) or emulator. */
1365 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1366 struct frame_info *frame, const char *args)
1368 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1371 type = (status >> 24) & 127;
1372 if (status & (1 << 31))
1373 printf (_("Hardware FPU type %d\n"), type);
1375 printf (_("Software FPU type %d\n"), type);
1376 /* i18n: [floating point unit] mask */
1377 fputs (_("mask: "), stdout);
1378 print_fpu_flags (status >> 16);
1379 /* i18n: [floating point unit] flags */
1380 fputs (_("flags: "), stdout);
1381 print_fpu_flags (status);
1384 /* Return the GDB type object for the "standard" data type of data in
1387 static struct type *
1388 arm_register_type (struct gdbarch *gdbarch, int regnum)
1390 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1391 return builtin_type_arm_ext;
1392 else if (regnum == ARM_SP_REGNUM)
1393 return builtin_type_void_data_ptr;
1394 else if (regnum == ARM_PC_REGNUM)
1395 return builtin_type_void_func_ptr;
1396 else if (regnum >= ARRAY_SIZE (arm_register_names))
1397 /* These registers are only supported on targets which supply
1398 an XML description. */
1399 return builtin_type_int0;
1401 return builtin_type_uint32;
1404 /* Map a DWARF register REGNUM onto the appropriate GDB register
1408 arm_dwarf_reg_to_regnum (int reg)
1410 /* Core integer regs. */
1411 if (reg >= 0 && reg <= 15)
1414 /* Legacy FPA encoding. These were once used in a way which
1415 overlapped with VFP register numbering, so their use is
1416 discouraged, but GDB doesn't support the ARM toolchain
1417 which used them for VFP. */
1418 if (reg >= 16 && reg <= 23)
1419 return ARM_F0_REGNUM + reg - 16;
1421 /* New assignments for the FPA registers. */
1422 if (reg >= 96 && reg <= 103)
1423 return ARM_F0_REGNUM + reg - 96;
1425 /* WMMX register assignments. */
1426 if (reg >= 104 && reg <= 111)
1427 return ARM_WCGR0_REGNUM + reg - 104;
1429 if (reg >= 112 && reg <= 127)
1430 return ARM_WR0_REGNUM + reg - 112;
1432 if (reg >= 192 && reg <= 199)
1433 return ARM_WC0_REGNUM + reg - 192;
1438 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1440 arm_register_sim_regno (int regnum)
1443 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (current_gdbarch));
1445 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1446 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1448 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1449 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1451 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1452 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1454 if (reg < NUM_GREGS)
1455 return SIM_ARM_R0_REGNUM + reg;
1458 if (reg < NUM_FREGS)
1459 return SIM_ARM_FP0_REGNUM + reg;
1462 if (reg < NUM_SREGS)
1463 return SIM_ARM_FPS_REGNUM + reg;
1466 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1469 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1470 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1471 It is thought that this is is the floating-point register format on
1472 little-endian systems. */
1475 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1479 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1480 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1482 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1484 floatformat_from_doublest (fmt, &d, dbl);
1488 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1491 floatformat_to_doublest (fmt, ptr, &d);
1492 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1493 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1495 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1500 condition_true (unsigned long cond, unsigned long status_reg)
1502 if (cond == INST_AL || cond == INST_NV)
1508 return ((status_reg & FLAG_Z) != 0);
1510 return ((status_reg & FLAG_Z) == 0);
1512 return ((status_reg & FLAG_C) != 0);
1514 return ((status_reg & FLAG_C) == 0);
1516 return ((status_reg & FLAG_N) != 0);
1518 return ((status_reg & FLAG_N) == 0);
1520 return ((status_reg & FLAG_V) != 0);
1522 return ((status_reg & FLAG_V) == 0);
1524 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1526 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1528 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1530 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1532 return (((status_reg & FLAG_Z) == 0) &&
1533 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1535 return (((status_reg & FLAG_Z) != 0) ||
1536 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1541 /* Support routines for single stepping. Calculate the next PC value. */
1542 #define submask(x) ((1L << ((x) + 1)) - 1)
1543 #define bit(obj,st) (((obj) >> (st)) & 1)
1544 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1545 #define sbits(obj,st,fn) \
1546 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1547 #define BranchDest(addr,instr) \
1548 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1551 static unsigned long
1552 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1553 unsigned long pc_val, unsigned long status_reg)
1555 unsigned long res, shift;
1556 int rm = bits (inst, 0, 3);
1557 unsigned long shifttype = bits (inst, 5, 6);
1561 int rs = bits (inst, 8, 11);
1562 shift = (rs == 15 ? pc_val + 8
1563 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1566 shift = bits (inst, 7, 11);
1569 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1570 + (bit (inst, 4) ? 12 : 8))
1571 : get_frame_register_unsigned (frame, rm));
1576 res = shift >= 32 ? 0 : res << shift;
1580 res = shift >= 32 ? 0 : res >> shift;
1586 res = ((res & 0x80000000L)
1587 ? ~((~res) >> shift) : res >> shift);
1590 case 3: /* ROR/RRX */
1593 res = (res >> 1) | (carry ? 0x80000000L : 0);
1595 res = (res >> shift) | (res << (32 - shift));
1599 return res & 0xffffffff;
1602 /* Return number of 1-bits in VAL. */
1605 bitcount (unsigned long val)
1608 for (nbits = 0; val != 0; nbits++)
1609 val &= val - 1; /* delete rightmost 1-bit in val */
1614 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1616 struct gdbarch *gdbarch = get_frame_arch (frame);
1617 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1618 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1619 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1620 unsigned long offset;
1622 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1626 /* Fetch the saved PC from the stack. It's stored above
1627 all of the other registers. */
1628 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1629 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1630 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1631 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1633 error (_("Infinite loop detected"));
1635 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1637 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1638 unsigned long cond = bits (inst1, 8, 11);
1639 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1640 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1642 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1644 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1646 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1648 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1649 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1650 nextpc = pc_val + offset;
1651 /* For BLX make sure to clear the low bits. */
1652 if (bits (inst2, 11, 12) == 1)
1653 nextpc = nextpc & 0xfffffffc;
1655 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1657 if (bits (inst1, 3, 6) == 0x0f)
1660 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1662 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1664 error (_("Infinite loop detected"));
1671 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1673 struct gdbarch *gdbarch = get_frame_arch (frame);
1674 unsigned long pc_val;
1675 unsigned long this_instr;
1676 unsigned long status;
1679 if (arm_pc_is_thumb (pc))
1680 return thumb_get_next_pc (frame, pc);
1682 pc_val = (unsigned long) pc;
1683 this_instr = read_memory_unsigned_integer (pc, 4);
1684 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1685 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1687 if (bits (this_instr, 28, 31) == INST_NV)
1688 switch (bits (this_instr, 24, 27))
1693 /* Branch with Link and change to Thumb. */
1694 nextpc = BranchDest (pc, this_instr);
1695 nextpc |= bit (this_instr, 24) << 1;
1697 nextpc = gdbarch_addr_bits_remove (current_gdbarch, nextpc);
1699 error (_("Infinite loop detected"));
1705 /* Coprocessor register transfer. */
1706 if (bits (this_instr, 12, 15) == 15)
1707 error (_("Invalid update to pc in instruction"));
1710 else if (condition_true (bits (this_instr, 28, 31), status))
1712 switch (bits (this_instr, 24, 27))
1715 case 0x1: /* data processing */
1719 unsigned long operand1, operand2, result = 0;
1723 if (bits (this_instr, 12, 15) != 15)
1726 if (bits (this_instr, 22, 25) == 0
1727 && bits (this_instr, 4, 7) == 9) /* multiply */
1728 error (_("Invalid update to pc in instruction"));
1730 /* BX <reg>, BLX <reg> */
1731 if (bits (this_instr, 4, 27) == 0x12fff1
1732 || bits (this_instr, 4, 27) == 0x12fff3)
1734 rn = bits (this_instr, 0, 3);
1735 result = (rn == 15) ? pc_val + 8
1736 : get_frame_register_unsigned (frame, rn);
1737 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1741 error (_("Infinite loop detected"));
1746 /* Multiply into PC */
1747 c = (status & FLAG_C) ? 1 : 0;
1748 rn = bits (this_instr, 16, 19);
1749 operand1 = (rn == 15) ? pc_val + 8
1750 : get_frame_register_unsigned (frame, rn);
1752 if (bit (this_instr, 25))
1754 unsigned long immval = bits (this_instr, 0, 7);
1755 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1756 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1759 else /* operand 2 is a shifted register */
1760 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1762 switch (bits (this_instr, 21, 24))
1765 result = operand1 & operand2;
1769 result = operand1 ^ operand2;
1773 result = operand1 - operand2;
1777 result = operand2 - operand1;
1781 result = operand1 + operand2;
1785 result = operand1 + operand2 + c;
1789 result = operand1 - operand2 + c;
1793 result = operand2 - operand1 + c;
1799 case 0xb: /* tst, teq, cmp, cmn */
1800 result = (unsigned long) nextpc;
1804 result = operand1 | operand2;
1808 /* Always step into a function. */
1813 result = operand1 & ~operand2;
1820 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1824 error (_("Infinite loop detected"));
1829 case 0x5: /* data transfer */
1832 if (bit (this_instr, 20))
1835 if (bits (this_instr, 12, 15) == 15)
1841 if (bit (this_instr, 22))
1842 error (_("Invalid update to pc in instruction"));
1844 /* byte write to PC */
1845 rn = bits (this_instr, 16, 19);
1846 base = (rn == 15) ? pc_val + 8
1847 : get_frame_register_unsigned (frame, rn);
1848 if (bit (this_instr, 24))
1851 int c = (status & FLAG_C) ? 1 : 0;
1852 unsigned long offset =
1853 (bit (this_instr, 25)
1854 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
1855 : bits (this_instr, 0, 11));
1857 if (bit (this_instr, 23))
1862 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1865 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1868 error (_("Infinite loop detected"));
1874 case 0x9: /* block transfer */
1875 if (bit (this_instr, 20))
1878 if (bit (this_instr, 15))
1883 if (bit (this_instr, 23))
1886 unsigned long reglist = bits (this_instr, 0, 14);
1887 offset = bitcount (reglist) * 4;
1888 if (bit (this_instr, 24)) /* pre */
1891 else if (bit (this_instr, 24))
1895 unsigned long rn_val =
1896 get_frame_register_unsigned (frame,
1897 bits (this_instr, 16, 19));
1899 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1903 nextpc = gdbarch_addr_bits_remove
1906 error (_("Infinite loop detected"));
1911 case 0xb: /* branch & link */
1912 case 0xa: /* branch */
1914 nextpc = BranchDest (pc, this_instr);
1916 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1918 error (_("Infinite loop detected"));
1924 case 0xe: /* coproc ops */
1929 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
1937 /* single_step() is called just before we want to resume the inferior,
1938 if we want to single-step it but there is no hardware or kernel
1939 single-step support. We find the target of the coming instruction
1940 and breakpoint it. */
1943 arm_software_single_step (struct frame_info *frame)
1945 /* NOTE: This may insert the wrong breakpoint instruction when
1946 single-stepping over a mode-changing instruction, if the
1947 CPSR heuristics are used. */
1949 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
1950 insert_single_step_breakpoint (next_pc);
1955 #include "bfd-in2.h"
1956 #include "libcoff.h"
1959 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1961 if (arm_pc_is_thumb (memaddr))
1963 static asymbol *asym;
1964 static combined_entry_type ce;
1965 static struct coff_symbol_struct csym;
1966 static struct bfd fake_bfd;
1967 static bfd_target fake_target;
1969 if (csym.native == NULL)
1971 /* Create a fake symbol vector containing a Thumb symbol.
1972 This is solely so that the code in print_insn_little_arm()
1973 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1974 the presence of a Thumb symbol and switch to decoding
1975 Thumb instructions. */
1977 fake_target.flavour = bfd_target_coff_flavour;
1978 fake_bfd.xvec = &fake_target;
1979 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1981 csym.symbol.the_bfd = &fake_bfd;
1982 csym.symbol.name = "fake";
1983 asym = (asymbol *) & csym;
1986 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1987 info->symbols = &asym;
1990 info->symbols = NULL;
1992 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1993 return print_insn_big_arm (memaddr, info);
1995 return print_insn_little_arm (memaddr, info);
1998 /* The following define instruction sequences that will cause ARM
1999 cpu's to take an undefined instruction trap. These are used to
2000 signal a breakpoint to GDB.
2002 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2003 modes. A different instruction is required for each mode. The ARM
2004 cpu's can also be big or little endian. Thus four different
2005 instructions are needed to support all cases.
2007 Note: ARMv4 defines several new instructions that will take the
2008 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2009 not in fact add the new instructions. The new undefined
2010 instructions in ARMv4 are all instructions that had no defined
2011 behaviour in earlier chips. There is no guarantee that they will
2012 raise an exception, but may be treated as NOP's. In practice, it
2013 may only safe to rely on instructions matching:
2015 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2016 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2017 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2019 Even this may only true if the condition predicate is true. The
2020 following use a condition predicate of ALWAYS so it is always TRUE.
2022 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2023 and NetBSD all use a software interrupt rather than an undefined
2024 instruction to force a trap. This can be handled by by the
2025 abi-specific code during establishment of the gdbarch vector. */
2027 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2028 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2029 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2030 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2032 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2033 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2034 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2035 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2037 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2038 the program counter value to determine whether a 16-bit or 32-bit
2039 breakpoint should be used. It returns a pointer to a string of
2040 bytes that encode a breakpoint instruction, stores the length of
2041 the string to *lenptr, and adjusts the program counter (if
2042 necessary) to point to the actual memory location where the
2043 breakpoint should be inserted. */
2045 static const unsigned char *
2046 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2048 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2050 if (arm_pc_is_thumb (*pcptr))
2052 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2053 *lenptr = tdep->thumb_breakpoint_size;
2054 return tdep->thumb_breakpoint;
2058 *lenptr = tdep->arm_breakpoint_size;
2059 return tdep->arm_breakpoint;
2063 /* Extract from an array REGBUF containing the (raw) register state a
2064 function return value of type TYPE, and copy that, in virtual
2065 format, into VALBUF. */
2068 arm_extract_return_value (struct type *type, struct regcache *regs,
2071 if (TYPE_CODE_FLT == TYPE_CODE (type))
2073 switch (gdbarch_tdep (get_regcache_arch (regs))->fp_model)
2077 /* The value is in register F0 in internal format. We need to
2078 extract the raw value and then convert it to the desired
2080 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2082 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2083 convert_from_extended (floatformat_from_type (type), tmpbuf,
2088 case ARM_FLOAT_SOFT_FPA:
2089 case ARM_FLOAT_SOFT_VFP:
2090 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2091 if (TYPE_LENGTH (type) > 4)
2092 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2093 valbuf + INT_REGISTER_SIZE);
2098 (__FILE__, __LINE__,
2099 _("arm_extract_return_value: Floating point model not supported"));
2103 else if (TYPE_CODE (type) == TYPE_CODE_INT
2104 || TYPE_CODE (type) == TYPE_CODE_CHAR
2105 || TYPE_CODE (type) == TYPE_CODE_BOOL
2106 || TYPE_CODE (type) == TYPE_CODE_PTR
2107 || TYPE_CODE (type) == TYPE_CODE_REF
2108 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2110 /* If the the type is a plain integer, then the access is
2111 straight-forward. Otherwise we have to play around a bit more. */
2112 int len = TYPE_LENGTH (type);
2113 int regno = ARM_A1_REGNUM;
2118 /* By using store_unsigned_integer we avoid having to do
2119 anything special for small big-endian values. */
2120 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2121 store_unsigned_integer (valbuf,
2122 (len > INT_REGISTER_SIZE
2123 ? INT_REGISTER_SIZE : len),
2125 len -= INT_REGISTER_SIZE;
2126 valbuf += INT_REGISTER_SIZE;
2131 /* For a structure or union the behaviour is as if the value had
2132 been stored to word-aligned memory and then loaded into
2133 registers with 32-bit load instruction(s). */
2134 int len = TYPE_LENGTH (type);
2135 int regno = ARM_A1_REGNUM;
2136 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2140 regcache_cooked_read (regs, regno++, tmpbuf);
2141 memcpy (valbuf, tmpbuf,
2142 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2143 len -= INT_REGISTER_SIZE;
2144 valbuf += INT_REGISTER_SIZE;
2150 /* Will a function return an aggregate type in memory or in a
2151 register? Return 0 if an aggregate type can be returned in a
2152 register, 1 if it must be returned in memory. */
2155 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2158 enum type_code code;
2160 CHECK_TYPEDEF (type);
2162 /* In the ARM ABI, "integer" like aggregate types are returned in
2163 registers. For an aggregate type to be integer like, its size
2164 must be less than or equal to INT_REGISTER_SIZE and the
2165 offset of each addressable subfield must be zero. Note that bit
2166 fields are not addressable, and all addressable subfields of
2167 unions always start at offset zero.
2169 This function is based on the behaviour of GCC 2.95.1.
2170 See: gcc/arm.c: arm_return_in_memory() for details.
2172 Note: All versions of GCC before GCC 2.95.2 do not set up the
2173 parameters correctly for a function returning the following
2174 structure: struct { float f;}; This should be returned in memory,
2175 not a register. Richard Earnshaw sent me a patch, but I do not
2176 know of any way to detect if a function like the above has been
2177 compiled with the correct calling convention. */
2179 /* All aggregate types that won't fit in a register must be returned
2181 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2186 /* The AAPCS says all aggregates not larger than a word are returned
2188 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2191 /* The only aggregate types that can be returned in a register are
2192 structs and unions. Arrays must be returned in memory. */
2193 code = TYPE_CODE (type);
2194 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2199 /* Assume all other aggregate types can be returned in a register.
2200 Run a check for structures, unions and arrays. */
2203 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2206 /* Need to check if this struct/union is "integer" like. For
2207 this to be true, its size must be less than or equal to
2208 INT_REGISTER_SIZE and the offset of each addressable
2209 subfield must be zero. Note that bit fields are not
2210 addressable, and unions always start at offset zero. If any
2211 of the subfields is a floating point type, the struct/union
2212 cannot be an integer type. */
2214 /* For each field in the object, check:
2215 1) Is it FP? --> yes, nRc = 1;
2216 2) Is it addressable (bitpos != 0) and
2217 not packed (bitsize == 0)?
2221 for (i = 0; i < TYPE_NFIELDS (type); i++)
2223 enum type_code field_type_code;
2224 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2226 /* Is it a floating point type field? */
2227 if (field_type_code == TYPE_CODE_FLT)
2233 /* If bitpos != 0, then we have to care about it. */
2234 if (TYPE_FIELD_BITPOS (type, i) != 0)
2236 /* Bitfields are not addressable. If the field bitsize is
2237 zero, then the field is not packed. Hence it cannot be
2238 a bitfield or any other packed type. */
2239 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2251 /* Write into appropriate registers a function return value of type
2252 TYPE, given in virtual format. */
2255 arm_store_return_value (struct type *type, struct regcache *regs,
2256 const gdb_byte *valbuf)
2258 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2260 char buf[MAX_REGISTER_SIZE];
2262 switch (gdbarch_tdep (get_regcache_arch (regs))->fp_model)
2266 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2267 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2270 case ARM_FLOAT_SOFT_FPA:
2271 case ARM_FLOAT_SOFT_VFP:
2272 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2273 if (TYPE_LENGTH (type) > 4)
2274 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2275 valbuf + INT_REGISTER_SIZE);
2280 (__FILE__, __LINE__,
2281 _("arm_store_return_value: Floating point model not supported"));
2285 else if (TYPE_CODE (type) == TYPE_CODE_INT
2286 || TYPE_CODE (type) == TYPE_CODE_CHAR
2287 || TYPE_CODE (type) == TYPE_CODE_BOOL
2288 || TYPE_CODE (type) == TYPE_CODE_PTR
2289 || TYPE_CODE (type) == TYPE_CODE_REF
2290 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2292 if (TYPE_LENGTH (type) <= 4)
2294 /* Values of one word or less are zero/sign-extended and
2296 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2297 LONGEST val = unpack_long (type, valbuf);
2299 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2300 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2304 /* Integral values greater than one word are stored in consecutive
2305 registers starting with r0. This will always be a multiple of
2306 the regiser size. */
2307 int len = TYPE_LENGTH (type);
2308 int regno = ARM_A1_REGNUM;
2312 regcache_cooked_write (regs, regno++, valbuf);
2313 len -= INT_REGISTER_SIZE;
2314 valbuf += INT_REGISTER_SIZE;
2320 /* For a structure or union the behaviour is as if the value had
2321 been stored to word-aligned memory and then loaded into
2322 registers with 32-bit load instruction(s). */
2323 int len = TYPE_LENGTH (type);
2324 int regno = ARM_A1_REGNUM;
2325 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2329 memcpy (tmpbuf, valbuf,
2330 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2331 regcache_cooked_write (regs, regno++, tmpbuf);
2332 len -= INT_REGISTER_SIZE;
2333 valbuf += INT_REGISTER_SIZE;
2339 /* Handle function return values. */
2341 static enum return_value_convention
2342 arm_return_value (struct gdbarch *gdbarch, struct type *valtype,
2343 struct regcache *regcache, gdb_byte *readbuf,
2344 const gdb_byte *writebuf)
2346 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2348 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2349 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2350 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2352 if (tdep->struct_return == pcc_struct_return
2353 || arm_return_in_memory (gdbarch, valtype))
2354 return RETURN_VALUE_STRUCT_CONVENTION;
2358 arm_store_return_value (valtype, regcache, writebuf);
2361 arm_extract_return_value (valtype, regcache, readbuf);
2363 return RETURN_VALUE_REGISTER_CONVENTION;
2368 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2371 char buf[INT_REGISTER_SIZE];
2372 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2374 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2376 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2380 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2384 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2385 return the target PC. Otherwise return 0. */
2388 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2392 CORE_ADDR start_addr;
2394 /* Find the starting address and name of the function containing the PC. */
2395 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2398 /* If PC is in a Thumb call or return stub, return the address of the
2399 target PC, which is in a register. The thunk functions are called
2400 _call_via_xx, where x is the register name. The possible names
2401 are r0-r9, sl, fp, ip, sp, and lr. */
2402 if (strncmp (name, "_call_via_", 10) == 0)
2404 /* Use the name suffix to determine which register contains the
2406 static char *table[15] =
2407 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2408 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2411 int offset = strlen (name) - 2;
2413 for (regno = 0; regno <= 14; regno++)
2414 if (strcmp (&name[offset], table[regno]) == 0)
2415 return get_frame_register_unsigned (frame, regno);
2418 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2419 non-interworking calls to foo. We could decode the stubs
2420 to find the target but it's easier to use the symbol table. */
2421 namelen = strlen (name);
2422 if (name[0] == '_' && name[1] == '_'
2423 && ((namelen > 2 + strlen ("_from_thumb")
2424 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2425 strlen ("_from_thumb")) == 0)
2426 || (namelen > 2 + strlen ("_from_arm")
2427 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2428 strlen ("_from_arm")) == 0)))
2431 int target_len = namelen - 2;
2432 struct minimal_symbol *minsym;
2433 struct objfile *objfile;
2434 struct obj_section *sec;
2436 if (name[namelen - 1] == 'b')
2437 target_len -= strlen ("_from_thumb");
2439 target_len -= strlen ("_from_arm");
2441 target_name = alloca (target_len + 1);
2442 memcpy (target_name, name + 2, target_len);
2443 target_name[target_len] = '\0';
2445 sec = find_pc_section (pc);
2446 objfile = (sec == NULL) ? NULL : sec->objfile;
2447 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2449 return SYMBOL_VALUE_ADDRESS (minsym);
2454 return 0; /* not a stub */
2458 set_arm_command (char *args, int from_tty)
2460 printf_unfiltered (_("\
2461 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2462 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2466 show_arm_command (char *args, int from_tty)
2468 cmd_show_list (showarmcmdlist, from_tty, "");
2472 arm_update_current_architecture (void)
2474 struct gdbarch_info info;
2476 /* If the current architecture is not ARM, we have nothing to do. */
2477 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2480 /* Update the architecture. */
2481 gdbarch_info_init (&info);
2483 if (!gdbarch_update_p (info))
2484 internal_error (__FILE__, __LINE__, "could not update architecture");
2488 set_fp_model_sfunc (char *args, int from_tty,
2489 struct cmd_list_element *c)
2491 enum arm_float_model fp_model;
2493 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2494 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2496 arm_fp_model = fp_model;
2500 if (fp_model == ARM_FLOAT_LAST)
2501 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2504 arm_update_current_architecture ();
2508 show_fp_model (struct ui_file *file, int from_tty,
2509 struct cmd_list_element *c, const char *value)
2511 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2513 if (arm_fp_model == ARM_FLOAT_AUTO
2514 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2515 fprintf_filtered (file, _("\
2516 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2517 fp_model_strings[tdep->fp_model]);
2519 fprintf_filtered (file, _("\
2520 The current ARM floating point model is \"%s\".\n"),
2521 fp_model_strings[arm_fp_model]);
2525 arm_set_abi (char *args, int from_tty,
2526 struct cmd_list_element *c)
2528 enum arm_abi_kind arm_abi;
2530 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2531 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2533 arm_abi_global = arm_abi;
2537 if (arm_abi == ARM_ABI_LAST)
2538 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2541 arm_update_current_architecture ();
2545 arm_show_abi (struct ui_file *file, int from_tty,
2546 struct cmd_list_element *c, const char *value)
2548 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2550 if (arm_abi_global == ARM_ABI_AUTO
2551 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2552 fprintf_filtered (file, _("\
2553 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2554 arm_abi_strings[tdep->arm_abi]);
2556 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2560 /* If the user changes the register disassembly style used for info
2561 register and other commands, we have to also switch the style used
2562 in opcodes for disassembly output. This function is run in the "set
2563 arm disassembly" command, and does that. */
2566 set_disassembly_style_sfunc (char *args, int from_tty,
2567 struct cmd_list_element *c)
2569 set_disassembly_style ();
2572 /* Return the ARM register name corresponding to register I. */
2574 arm_register_name (int i)
2576 if (i >= ARRAY_SIZE (arm_register_names))
2577 /* These registers are only supported on targets which supply
2578 an XML description. */
2581 return arm_register_names[i];
2585 set_disassembly_style (void)
2589 /* Find the style that the user wants. */
2590 for (current = 0; current < num_disassembly_options; current++)
2591 if (disassembly_style == valid_disassembly_styles[current])
2593 gdb_assert (current < num_disassembly_options);
2595 /* Synchronize the disassembler. */
2596 set_arm_regname_option (current);
2599 /* Test whether the coff symbol specific value corresponds to a Thumb
2603 coff_sym_is_thumb (int val)
2605 return (val == C_THUMBEXT ||
2606 val == C_THUMBSTAT ||
2607 val == C_THUMBEXTFUNC ||
2608 val == C_THUMBSTATFUNC ||
2609 val == C_THUMBLABEL);
2612 /* arm_coff_make_msymbol_special()
2613 arm_elf_make_msymbol_special()
2615 These functions test whether the COFF or ELF symbol corresponds to
2616 an address in thumb code, and set a "special" bit in a minimal
2617 symbol to indicate that it does. */
2620 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2622 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2624 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2626 MSYMBOL_SET_SPECIAL (msym);
2630 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2632 if (coff_sym_is_thumb (val))
2633 MSYMBOL_SET_SPECIAL (msym);
2637 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2639 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2641 /* If necessary, set the T bit. */
2645 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2646 if (arm_pc_is_thumb (pc))
2647 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | 0x20);
2649 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2650 val & ~(ULONGEST) 0x20);
2654 static struct value *
2655 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2657 const int *reg_p = baton;
2658 return value_of_register (*reg_p, frame);
2661 static enum gdb_osabi
2662 arm_elf_osabi_sniffer (bfd *abfd)
2664 unsigned int elfosabi;
2665 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2667 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2669 if (elfosabi == ELFOSABI_ARM)
2670 /* GNU tools use this value. Check note sections in this case,
2672 bfd_map_over_sections (abfd,
2673 generic_elf_osabi_sniff_abi_tag_sections,
2676 /* Anything else will be handled by the generic ELF sniffer. */
2681 /* Initialize the current architecture based on INFO. If possible,
2682 re-use an architecture from ARCHES, which is a list of
2683 architectures already created during this debugging session.
2685 Called e.g. at program startup, when reading a core file, and when
2686 reading a binary file. */
2688 static struct gdbarch *
2689 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2691 struct gdbarch_tdep *tdep;
2692 struct gdbarch *gdbarch;
2693 struct gdbarch_list *best_arch;
2694 enum arm_abi_kind arm_abi = arm_abi_global;
2695 enum arm_float_model fp_model = arm_fp_model;
2696 struct tdesc_arch_data *tdesc_data = NULL;
2698 int have_fpa_registers = 1;
2700 /* Check any target description for validity. */
2701 if (tdesc_has_registers (info.target_desc))
2703 /* For most registers we require GDB's default names; but also allow
2704 the numeric names for sp / lr / pc, as a convenience. */
2705 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2706 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2707 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2709 const struct tdesc_feature *feature;
2712 feature = tdesc_find_feature (info.target_desc,
2713 "org.gnu.gdb.arm.core");
2714 if (feature == NULL)
2717 tdesc_data = tdesc_data_alloc ();
2720 for (i = 0; i < ARM_SP_REGNUM; i++)
2721 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2722 arm_register_names[i]);
2723 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2726 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2729 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2732 valid_p &= tdesc_numbered_register (feature, tdesc_data,
2733 ARM_PS_REGNUM, "cpsr");
2737 tdesc_data_cleanup (tdesc_data);
2741 feature = tdesc_find_feature (info.target_desc,
2742 "org.gnu.gdb.arm.fpa");
2743 if (feature != NULL)
2746 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
2747 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2748 arm_register_names[i]);
2751 tdesc_data_cleanup (tdesc_data);
2756 have_fpa_registers = 0;
2758 feature = tdesc_find_feature (info.target_desc,
2759 "org.gnu.gdb.xscale.iwmmxt");
2760 if (feature != NULL)
2762 static const char *const iwmmxt_names[] = {
2763 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2764 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2765 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2766 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2770 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
2772 &= tdesc_numbered_register (feature, tdesc_data, i,
2773 iwmmxt_names[i - ARM_WR0_REGNUM]);
2775 /* Check for the control registers, but do not fail if they
2777 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
2778 tdesc_numbered_register (feature, tdesc_data, i,
2779 iwmmxt_names[i - ARM_WR0_REGNUM]);
2781 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
2783 &= tdesc_numbered_register (feature, tdesc_data, i,
2784 iwmmxt_names[i - ARM_WR0_REGNUM]);
2788 tdesc_data_cleanup (tdesc_data);
2794 /* If we have an object to base this architecture on, try to determine
2797 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2799 int ei_osabi, e_flags;
2801 switch (bfd_get_flavour (info.abfd))
2803 case bfd_target_aout_flavour:
2804 /* Assume it's an old APCS-style ABI. */
2805 arm_abi = ARM_ABI_APCS;
2808 case bfd_target_coff_flavour:
2809 /* Assume it's an old APCS-style ABI. */
2811 arm_abi = ARM_ABI_APCS;
2814 case bfd_target_elf_flavour:
2815 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2816 e_flags = elf_elfheader (info.abfd)->e_flags;
2818 if (ei_osabi == ELFOSABI_ARM)
2820 /* GNU tools used to use this value, but do not for EABI
2821 objects. There's nowhere to tag an EABI version
2822 anyway, so assume APCS. */
2823 arm_abi = ARM_ABI_APCS;
2825 else if (ei_osabi == ELFOSABI_NONE)
2827 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2831 case EF_ARM_EABI_UNKNOWN:
2832 /* Assume GNU tools. */
2833 arm_abi = ARM_ABI_APCS;
2836 case EF_ARM_EABI_VER4:
2837 case EF_ARM_EABI_VER5:
2838 arm_abi = ARM_ABI_AAPCS;
2839 /* EABI binaries default to VFP float ordering. */
2840 if (fp_model == ARM_FLOAT_AUTO)
2841 fp_model = ARM_FLOAT_SOFT_VFP;
2845 /* Leave it as "auto". */
2846 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2851 if (fp_model == ARM_FLOAT_AUTO)
2853 int e_flags = elf_elfheader (info.abfd)->e_flags;
2855 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2858 /* Leave it as "auto". Strictly speaking this case
2859 means FPA, but almost nobody uses that now, and
2860 many toolchains fail to set the appropriate bits
2861 for the floating-point model they use. */
2863 case EF_ARM_SOFT_FLOAT:
2864 fp_model = ARM_FLOAT_SOFT_FPA;
2866 case EF_ARM_VFP_FLOAT:
2867 fp_model = ARM_FLOAT_VFP;
2869 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2870 fp_model = ARM_FLOAT_SOFT_VFP;
2877 /* Leave it as "auto". */
2882 /* If there is already a candidate, use it. */
2883 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2885 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2887 if (arm_abi != ARM_ABI_AUTO
2888 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2891 if (fp_model != ARM_FLOAT_AUTO
2892 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
2895 /* Found a match. */
2899 if (best_arch != NULL)
2901 if (tdesc_data != NULL)
2902 tdesc_data_cleanup (tdesc_data);
2903 return best_arch->gdbarch;
2906 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
2907 gdbarch = gdbarch_alloc (&info, tdep);
2909 /* Record additional information about the architecture we are defining.
2910 These are gdbarch discriminators, like the OSABI. */
2911 tdep->arm_abi = arm_abi;
2912 tdep->fp_model = fp_model;
2913 tdep->have_fpa_registers = have_fpa_registers;
2916 switch (info.byte_order)
2918 case BFD_ENDIAN_BIG:
2919 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2920 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2921 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2922 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2926 case BFD_ENDIAN_LITTLE:
2927 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2928 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2929 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2930 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2935 internal_error (__FILE__, __LINE__,
2936 _("arm_gdbarch_init: bad byte order for float format"));
2939 /* On ARM targets char defaults to unsigned. */
2940 set_gdbarch_char_signed (gdbarch, 0);
2942 /* This should be low enough for everything. */
2943 tdep->lowest_pc = 0x20;
2944 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2946 /* The default, for both APCS and AAPCS, is to return small
2947 structures in registers. */
2948 tdep->struct_return = reg_struct_return;
2950 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2951 set_gdbarch_frame_align (gdbarch, arm_frame_align);
2953 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2955 /* Frame handling. */
2956 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2957 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2958 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2960 frame_base_set_default (gdbarch, &arm_normal_base);
2962 /* Address manipulation. */
2963 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2964 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2966 /* Advance PC across function entry code. */
2967 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2969 /* Skip trampolines. */
2970 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
2972 /* The stack grows downward. */
2973 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2975 /* Breakpoint manipulation. */
2976 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2978 /* Information about registers, etc. */
2979 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2980 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2981 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2982 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
2983 set_gdbarch_register_type (gdbarch, arm_register_type);
2985 /* This "info float" is FPA-specific. Use the generic version if we
2987 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
2988 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2990 /* Internal <-> external register number maps. */
2991 set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
2992 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
2993 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2995 set_gdbarch_register_name (gdbarch, arm_register_name);
2997 /* Returning results. */
2998 set_gdbarch_return_value (gdbarch, arm_return_value);
3001 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3003 /* Minsymbol frobbing. */
3004 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3005 set_gdbarch_coff_make_msymbol_special (gdbarch,
3006 arm_coff_make_msymbol_special);
3008 /* Virtual tables. */
3009 set_gdbarch_vbit_in_delta (gdbarch, 1);
3011 /* Hook in the ABI-specific overrides, if they have been registered. */
3012 gdbarch_init_osabi (info, gdbarch);
3014 /* Add some default predicates. */
3015 frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer);
3016 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3017 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
3019 /* Now we have tuned the configuration, set a few final things,
3020 based on what the OS ABI has told us. */
3022 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3023 binaries are always marked. */
3024 if (tdep->arm_abi == ARM_ABI_AUTO)
3025 tdep->arm_abi = ARM_ABI_APCS;
3027 /* We used to default to FPA for generic ARM, but almost nobody
3028 uses that now, and we now provide a way for the user to force
3029 the model. So default to the most useful variant. */
3030 if (tdep->fp_model == ARM_FLOAT_AUTO)
3031 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3033 if (tdep->jb_pc >= 0)
3034 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3036 /* Floating point sizes and format. */
3037 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3038 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3040 set_gdbarch_double_format
3041 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3042 set_gdbarch_long_double_format
3043 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3047 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3048 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3052 tdesc_use_registers (gdbarch, tdesc_data);
3054 /* Add standard register aliases. We add aliases even for those
3055 nanes which are used by the current architecture - it's simpler,
3056 and does no harm, since nothing ever lists user registers. */
3057 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3058 user_reg_add (gdbarch, arm_register_aliases[i].name,
3059 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3065 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3067 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3072 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3073 (unsigned long) tdep->lowest_pc);
3076 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3079 _initialize_arm_tdep (void)
3081 struct ui_file *stb;
3083 struct cmd_list_element *new_set, *new_show;
3084 const char *setname;
3085 const char *setdesc;
3086 const char *const *regnames;
3088 static char *helptext;
3089 char regdesc[1024], *rdptr = regdesc;
3090 size_t rest = sizeof (regdesc);
3092 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3094 /* Register an ELF OS ABI sniffer for ARM binaries. */
3095 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3096 bfd_target_elf_flavour,
3097 arm_elf_osabi_sniffer);
3099 /* Get the number of possible sets of register names defined in opcodes. */
3100 num_disassembly_options = get_arm_regname_num_options ();
3102 /* Add root prefix command for all "set arm"/"show arm" commands. */
3103 add_prefix_cmd ("arm", no_class, set_arm_command,
3104 _("Various ARM-specific commands."),
3105 &setarmcmdlist, "set arm ", 0, &setlist);
3107 add_prefix_cmd ("arm", no_class, show_arm_command,
3108 _("Various ARM-specific commands."),
3109 &showarmcmdlist, "show arm ", 0, &showlist);
3111 /* Sync the opcode insn printer with our register viewer. */
3112 parse_arm_disassembler_option ("reg-names-std");
3114 /* Initialize the array that will be passed to
3115 add_setshow_enum_cmd(). */
3116 valid_disassembly_styles
3117 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3118 for (i = 0; i < num_disassembly_options; i++)
3120 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3121 valid_disassembly_styles[i] = setname;
3122 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3125 /* When we find the default names, tell the disassembler to use
3127 if (!strcmp (setname, "std"))
3129 disassembly_style = setname;
3130 set_arm_regname_option (i);
3133 /* Mark the end of valid options. */
3134 valid_disassembly_styles[num_disassembly_options] = NULL;
3136 /* Create the help text. */
3137 stb = mem_fileopen ();
3138 fprintf_unfiltered (stb, "%s%s%s",
3139 _("The valid values are:\n"),
3141 _("The default is \"std\"."));
3142 helptext = ui_file_xstrdup (stb, &length);
3143 ui_file_delete (stb);
3145 add_setshow_enum_cmd("disassembler", no_class,
3146 valid_disassembly_styles, &disassembly_style,
3147 _("Set the disassembly style."),
3148 _("Show the disassembly style."),
3150 set_disassembly_style_sfunc,
3151 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3152 &setarmcmdlist, &showarmcmdlist);
3154 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3155 _("Set usage of ARM 32-bit mode."),
3156 _("Show usage of ARM 32-bit mode."),
3157 _("When off, a 26-bit PC will be used."),
3159 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3160 &setarmcmdlist, &showarmcmdlist);
3162 /* Add a command to allow the user to force the FPU model. */
3163 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3164 _("Set the floating point type."),
3165 _("Show the floating point type."),
3166 _("auto - Determine the FP typefrom the OS-ABI.\n\
3167 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3168 fpa - FPA co-processor (GCC compiled).\n\
3169 softvfp - Software FP with pure-endian doubles.\n\
3170 vfp - VFP co-processor."),
3171 set_fp_model_sfunc, show_fp_model,
3172 &setarmcmdlist, &showarmcmdlist);
3174 /* Add a command to allow the user to force the ABI. */
3175 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3178 NULL, arm_set_abi, arm_show_abi,
3179 &setarmcmdlist, &showarmcmdlist);
3181 /* Debugging flag. */
3182 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3183 _("Set ARM debugging."),
3184 _("Show ARM debugging."),
3185 _("When on, arm-specific debugging is enabled."),
3187 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3188 &setdebuglist, &showdebuglist);