1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
57 /* Macros for setting and testing a bit in a minimal symbol that marks
58 it as Thumb function. The MSB of the minimal symbol's "info" field
59 is used for this purpose.
61 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
62 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64 #define MSYMBOL_SET_SPECIAL(msym) \
65 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71 /* The list of available "set arm ..." and "show arm ..." commands. */
72 static struct cmd_list_element *setarmcmdlist = NULL;
73 static struct cmd_list_element *showarmcmdlist = NULL;
75 /* The type of floating-point to use. Keep this in sync with enum
76 arm_float_model, and the help string in _initialize_arm_tdep. */
77 static const char *fp_model_strings[] =
87 /* A variable that can be configured by the user. */
88 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
89 static const char *current_fp_model = "auto";
91 /* The ABI to use. Keep this in sync with arm_abi_kind. */
92 static const char *arm_abi_strings[] =
100 /* A variable that can be configured by the user. */
101 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
102 static const char *arm_abi_string = "auto";
104 /* Number of different reg name sets (options). */
105 static int num_disassembly_options;
107 /* The standard register names, and all the valid aliases for them. */
112 } arm_register_aliases[] = {
113 /* Basic register numbers. */
130 /* Synonyms (argument and variable registers). */
143 /* Other platform-specific names for r9. */
151 /* Names used by GCC (not listed in the ARM EABI). */
154 /* A special name from the older ATPCS. */
158 static const char *const arm_register_names[] =
159 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
160 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
161 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
162 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
163 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
164 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
165 "fps", "cpsr" }; /* 24 25 */
167 /* Valid register name styles. */
168 static const char **valid_disassembly_styles;
170 /* Disassembly style to use. Default to "std" register names. */
171 static const char *disassembly_style;
173 /* This is used to keep the bfd arch_info in sync with the disassembly
175 static void set_disassembly_style_sfunc(char *, int,
176 struct cmd_list_element *);
177 static void set_disassembly_style (void);
179 static void convert_from_extended (const struct floatformat *, const void *,
181 static void convert_to_extended (const struct floatformat *, void *,
184 struct arm_prologue_cache
186 /* The stack pointer at the time this frame was created; i.e. the
187 caller's stack pointer when this function was called. It is used
188 to identify this frame. */
191 /* The frame base for this frame is just prev_sp - frame size.
192 FRAMESIZE is the distance from the frame pointer to the
193 initial stack pointer. */
197 /* The register used to hold the frame pointer for this frame. */
200 /* Saved register offsets. */
201 struct trad_frame_saved_reg *saved_regs;
204 /* Addresses for calling Thumb functions have the bit 0 set.
205 Here are some macros to test, set, or clear bit 0 of addresses. */
206 #define IS_THUMB_ADDR(addr) ((addr) & 1)
207 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
208 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
210 /* Set to true if the 32-bit mode is in use. */
214 /* Determine if FRAME is executing in Thumb mode. */
217 arm_frame_is_thumb (struct frame_info *frame)
221 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
222 directly (from a signal frame or dummy frame) or by interpreting
223 the saved LR (from a prologue or DWARF frame). So consult it and
224 trust the unwinders. */
225 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
227 return (cpsr & CPSR_T) != 0;
230 /* Determine if the program counter specified in MEMADDR is in a Thumb
231 function. This function should be called for addresses unrelated to
232 any executing frame; otherwise, prefer arm_frame_is_thumb. */
235 arm_pc_is_thumb (CORE_ADDR memaddr)
237 struct minimal_symbol *sym;
239 /* If bit 0 of the address is set, assume this is a Thumb address. */
240 if (IS_THUMB_ADDR (memaddr))
243 /* Thumb functions have a "special" bit set in minimal symbols. */
244 sym = lookup_minimal_symbol_by_pc (memaddr);
247 return (MSYMBOL_IS_SPECIAL (sym));
255 /* Remove useless bits from addresses in a running program. */
257 arm_addr_bits_remove (CORE_ADDR val)
260 return UNMAKE_THUMB_ADDR (val);
262 return (val & 0x03fffffc);
265 /* When reading symbols, we need to zap the low bit of the address,
266 which may be set to 1 for Thumb functions. */
268 arm_smash_text_address (CORE_ADDR val)
273 /* Analyze a Thumb prologue, looking for a recognizable stack frame
274 and frame pointer. Scan until we encounter a store that could
275 clobber the stack frame unexpectedly, or an unknown instruction. */
278 thumb_analyze_prologue (struct gdbarch *gdbarch,
279 CORE_ADDR start, CORE_ADDR limit,
280 struct arm_prologue_cache *cache)
284 struct pv_area *stack;
285 struct cleanup *back_to;
288 for (i = 0; i < 16; i++)
289 regs[i] = pv_register (i, 0);
290 stack = make_pv_area (ARM_SP_REGNUM);
291 back_to = make_cleanup_free_pv_area (stack);
293 while (start < limit)
297 insn = read_memory_unsigned_integer (start, 2);
299 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
304 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
307 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
308 whether to save LR (R14). */
309 mask = (insn & 0xff) | ((insn & 0x100) << 6);
311 /* Calculate offsets of saved R0-R7 and LR. */
312 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
313 if (mask & (1 << regno))
315 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
317 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
320 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
323 offset = (insn & 0x7f) << 2; /* get scaled offset */
324 if (insn & 0x80) /* Check for SUB. */
325 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
328 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
331 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
332 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
334 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
336 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
337 int src_reg = (insn & 0x78) >> 3;
338 regs[dst_reg] = regs[src_reg];
340 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
342 /* Handle stores to the stack. Normally pushes are used,
343 but with GCC -mtpcs-frame, there may be other stores
344 in the prologue to create the frame. */
345 int regno = (insn >> 8) & 0x7;
348 offset = (insn & 0xff) << 2;
349 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
351 if (pv_area_store_would_trash (stack, addr))
354 pv_area_store (stack, addr, 4, regs[regno]);
358 /* We don't know what this instruction is. We're finished
359 scanning. NOTE: Recognizing more safe-to-ignore
360 instructions here will improve support for optimized
370 do_cleanups (back_to);
374 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
376 /* Frame pointer is fp. Frame size is constant. */
377 cache->framereg = ARM_FP_REGNUM;
378 cache->framesize = -regs[ARM_FP_REGNUM].k;
380 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
382 /* Frame pointer is r7. Frame size is constant. */
383 cache->framereg = THUMB_FP_REGNUM;
384 cache->framesize = -regs[THUMB_FP_REGNUM].k;
386 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
388 /* Try the stack pointer... this is a bit desperate. */
389 cache->framereg = ARM_SP_REGNUM;
390 cache->framesize = -regs[ARM_SP_REGNUM].k;
394 /* We're just out of luck. We don't know where the frame is. */
395 cache->framereg = -1;
396 cache->framesize = 0;
399 for (i = 0; i < 16; i++)
400 if (pv_area_find_reg (stack, gdbarch, i, &offset))
401 cache->saved_regs[i].addr = offset;
403 do_cleanups (back_to);
407 /* Advance the PC across any function entry prologue instructions to
408 reach some "real" code.
410 The APCS (ARM Procedure Call Standard) defines the following
414 [stmfd sp!, {a1,a2,a3,a4}]
415 stmfd sp!, {...,fp,ip,lr,pc}
416 [stfe f7, [sp, #-12]!]
417 [stfe f6, [sp, #-12]!]
418 [stfe f5, [sp, #-12]!]
419 [stfe f4, [sp, #-12]!]
420 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
423 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
427 CORE_ADDR func_addr, func_end = 0;
429 struct symtab_and_line sal;
431 /* If we're in a dummy frame, don't even try to skip the prologue. */
432 if (deprecated_pc_in_call_dummy (pc))
435 /* See what the symbol table says. */
437 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
441 /* Found a function. */
442 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
443 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
445 /* Don't use this trick for assembly source files. */
446 sal = find_pc_line (func_addr, 0);
447 if ((sal.line != 0) && (sal.end < func_end))
452 /* Can't find the prologue end in the symbol table, try it the hard way
453 by disassembling the instructions. */
455 /* Like arm_scan_prologue, stop no later than pc + 64. */
456 if (func_end == 0 || func_end > pc + 64)
459 /* Check if this is Thumb code. */
460 if (arm_pc_is_thumb (pc))
461 return thumb_analyze_prologue (gdbarch, pc, func_end, NULL);
463 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
465 inst = read_memory_unsigned_integer (skip_pc, 4);
467 /* "mov ip, sp" is no longer a required part of the prologue. */
468 if (inst == 0xe1a0c00d) /* mov ip, sp */
471 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
474 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
477 /* Some prologues begin with "str lr, [sp, #-4]!". */
478 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
481 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
484 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
487 /* Any insns after this point may float into the code, if it makes
488 for better instruction scheduling, so we skip them only if we
489 find them, but still consider the function to be frame-ful. */
491 /* We may have either one sfmfd instruction here, or several stfe
492 insns, depending on the version of floating point code we
494 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
497 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
500 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
503 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
506 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
507 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
508 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
511 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
512 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
513 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
516 /* Un-recognized instruction; stop scanning. */
520 return skip_pc; /* End of prologue */
524 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
525 This function decodes a Thumb function prologue to determine:
526 1) the size of the stack frame
527 2) which registers are saved on it
528 3) the offsets of saved regs
529 4) the offset from the stack pointer to the frame pointer
531 A typical Thumb function prologue would create this stack frame
532 (offsets relative to FP)
533 old SP -> 24 stack parameters
536 R7 -> 0 local variables (16 bytes)
537 SP -> -12 additional stack space (12 bytes)
538 The frame size would thus be 36 bytes, and the frame offset would be
539 12 bytes. The frame register is R7.
541 The comments for thumb_skip_prolog() describe the algorithm we use
542 to detect the end of the prolog. */
546 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
547 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
549 CORE_ADDR prologue_start;
550 CORE_ADDR prologue_end;
551 CORE_ADDR current_pc;
553 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
556 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
558 if (sal.line == 0) /* no line info, use current PC */
559 prologue_end = prev_pc;
560 else if (sal.end < prologue_end) /* next line begins after fn end */
561 prologue_end = sal.end; /* (probably means no prologue) */
564 /* We're in the boondocks: we have no idea where the start of the
568 prologue_end = min (prologue_end, prev_pc);
570 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
573 /* This function decodes an ARM function prologue to determine:
574 1) the size of the stack frame
575 2) which registers are saved on it
576 3) the offsets of saved regs
577 4) the offset from the stack pointer to the frame pointer
578 This information is stored in the "extra" fields of the frame_info.
580 There are two basic forms for the ARM prologue. The fixed argument
581 function call will look like:
584 stmfd sp!, {fp, ip, lr, pc}
588 Which would create this stack frame (offsets relative to FP):
589 IP -> 4 (caller's stack)
590 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
591 -4 LR (return address in caller)
592 -8 IP (copy of caller's SP)
594 SP -> -28 Local variables
596 The frame size would thus be 32 bytes, and the frame offset would be
597 28 bytes. The stmfd call can also save any of the vN registers it
598 plans to use, which increases the frame size accordingly.
600 Note: The stored PC is 8 off of the STMFD instruction that stored it
601 because the ARM Store instructions always store PC + 8 when you read
604 A variable argument function call will look like:
607 stmfd sp!, {a1, a2, a3, a4}
608 stmfd sp!, {fp, ip, lr, pc}
611 Which would create this stack frame (offsets relative to FP):
612 IP -> 20 (caller's stack)
617 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
618 -4 LR (return address in caller)
619 -8 IP (copy of caller's SP)
621 SP -> -28 Local variables
623 The frame size would thus be 48 bytes, and the frame offset would be
626 There is another potential complication, which is that the optimizer
627 will try to separate the store of fp in the "stmfd" instruction from
628 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
629 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
631 Also, note, the original version of the ARM toolchain claimed that there
634 instruction at the end of the prologue. I have never seen GCC produce
635 this, and the ARM docs don't mention it. We still test for it below in
641 arm_scan_prologue (struct frame_info *this_frame,
642 struct arm_prologue_cache *cache)
644 struct gdbarch *gdbarch = get_frame_arch (this_frame);
646 CORE_ADDR prologue_start, prologue_end, current_pc;
647 CORE_ADDR prev_pc = get_frame_pc (this_frame);
648 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
649 pv_t regs[ARM_FPS_REGNUM];
650 struct pv_area *stack;
651 struct cleanup *back_to;
654 /* Assume there is no frame until proven otherwise. */
655 cache->framereg = ARM_SP_REGNUM;
656 cache->framesize = 0;
658 /* Check for Thumb prologue. */
659 if (arm_frame_is_thumb (this_frame))
661 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
665 /* Find the function prologue. If we can't find the function in
666 the symbol table, peek in the stack frame to find the PC. */
667 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
670 /* One way to find the end of the prologue (which works well
671 for unoptimized code) is to do the following:
673 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
676 prologue_end = prev_pc;
677 else if (sal.end < prologue_end)
678 prologue_end = sal.end;
680 This mechanism is very accurate so long as the optimizer
681 doesn't move any instructions from the function body into the
682 prologue. If this happens, sal.end will be the last
683 instruction in the first hunk of prologue code just before
684 the first instruction that the scheduler has moved from
685 the body to the prologue.
687 In order to make sure that we scan all of the prologue
688 instructions, we use a slightly less accurate mechanism which
689 may scan more than necessary. To help compensate for this
690 lack of accuracy, the prologue scanning loop below contains
691 several clauses which'll cause the loop to terminate early if
692 an implausible prologue instruction is encountered.
698 is a suitable endpoint since it accounts for the largest
699 possible prologue plus up to five instructions inserted by
702 if (prologue_end > prologue_start + 64)
704 prologue_end = prologue_start + 64; /* See above. */
709 /* We have no symbol information. Our only option is to assume this
710 function has a standard stack frame and the normal frame register.
711 Then, we can find the value of our frame pointer on entrance to
712 the callee (or at the present moment if this is the innermost frame).
713 The value stored there should be the address of the stmfd + 8. */
715 LONGEST return_value;
717 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
718 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
722 prologue_start = gdbarch_addr_bits_remove
723 (gdbarch, return_value) - 8;
724 prologue_end = prologue_start + 64; /* See above. */
728 if (prev_pc < prologue_end)
729 prologue_end = prev_pc;
731 /* Now search the prologue looking for instructions that set up the
732 frame pointer, adjust the stack pointer, and save registers.
734 Be careful, however, and if it doesn't look like a prologue,
735 don't try to scan it. If, for instance, a frameless function
736 begins with stmfd sp!, then we will tell ourselves there is
737 a frame, which will confuse stack traceback, as well as "finish"
738 and other operations that rely on a knowledge of the stack
741 In the APCS, the prologue should start with "mov ip, sp" so
742 if we don't see this as the first insn, we will stop.
744 [Note: This doesn't seem to be true any longer, so it's now an
745 optional part of the prologue. - Kevin Buettner, 2001-11-20]
747 [Note further: The "mov ip,sp" only seems to be missing in
748 frameless functions at optimization level "-O2" or above,
749 in which case it is often (but not always) replaced by
750 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
752 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
753 regs[regno] = pv_register (regno, 0);
754 stack = make_pv_area (ARM_SP_REGNUM);
755 back_to = make_cleanup_free_pv_area (stack);
757 for (current_pc = prologue_start;
758 current_pc < prologue_end;
761 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
763 if (insn == 0xe1a0c00d) /* mov ip, sp */
765 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
768 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
770 unsigned imm = insn & 0xff; /* immediate value */
771 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
772 imm = (imm >> rot) | (imm << (32 - rot));
773 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
776 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
778 unsigned imm = insn & 0xff; /* immediate value */
779 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
780 imm = (imm >> rot) | (imm << (32 - rot));
781 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
784 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
786 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
788 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
789 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
792 else if ((insn & 0xffff0000) == 0xe92d0000)
793 /* stmfd sp!, {..., fp, ip, lr, pc}
795 stmfd sp!, {a1, a2, a3, a4} */
797 int mask = insn & 0xffff;
799 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
802 /* Calculate offsets of saved registers. */
803 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
804 if (mask & (1 << regno))
806 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
807 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
810 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
811 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
812 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
814 /* No need to add this to saved_regs -- it's just an arg reg. */
817 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
818 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
819 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
821 /* No need to add this to saved_regs -- it's just an arg reg. */
824 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
826 unsigned imm = insn & 0xff; /* immediate value */
827 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
828 imm = (imm >> rot) | (imm << (32 - rot));
829 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
831 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
833 unsigned imm = insn & 0xff; /* immediate value */
834 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
835 imm = (imm >> rot) | (imm << (32 - rot));
836 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
838 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
839 && gdbarch_tdep (gdbarch)->have_fpa_registers)
841 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
844 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
845 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
846 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
848 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
849 && gdbarch_tdep (gdbarch)->have_fpa_registers)
852 unsigned int fp_start_reg, fp_bound_reg;
854 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
857 if ((insn & 0x800) == 0x800) /* N0 is set */
859 if ((insn & 0x40000) == 0x40000) /* N1 is set */
866 if ((insn & 0x40000) == 0x40000) /* N1 is set */
872 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
873 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
874 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
876 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
877 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
878 regs[fp_start_reg++]);
881 else if ((insn & 0xf0000000) != 0xe0000000)
882 break; /* Condition not true, exit early */
883 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
884 break; /* Don't scan past a block load */
886 /* The optimizer might shove anything into the prologue,
887 so we just skip what we don't recognize. */
891 /* The frame size is just the distance from the frame register
892 to the original stack pointer. */
893 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
895 /* Frame pointer is fp. */
896 cache->framereg = ARM_FP_REGNUM;
897 cache->framesize = -regs[ARM_FP_REGNUM].k;
899 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
901 /* Try the stack pointer... this is a bit desperate. */
902 cache->framereg = ARM_SP_REGNUM;
903 cache->framesize = -regs[ARM_SP_REGNUM].k;
907 /* We're just out of luck. We don't know where the frame is. */
908 cache->framereg = -1;
909 cache->framesize = 0;
912 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
913 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
914 cache->saved_regs[regno].addr = offset;
916 do_cleanups (back_to);
919 static struct arm_prologue_cache *
920 arm_make_prologue_cache (struct frame_info *this_frame)
923 struct arm_prologue_cache *cache;
924 CORE_ADDR unwound_fp;
926 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
927 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
929 arm_scan_prologue (this_frame, cache);
931 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
935 cache->prev_sp = unwound_fp + cache->framesize;
937 /* Calculate actual addresses of saved registers using offsets
938 determined by arm_scan_prologue. */
939 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
940 if (trad_frame_addr_p (cache->saved_regs, reg))
941 cache->saved_regs[reg].addr += cache->prev_sp;
946 /* Our frame ID for a normal frame is the current function's starting PC
947 and the caller's SP when we were called. */
950 arm_prologue_this_id (struct frame_info *this_frame,
952 struct frame_id *this_id)
954 struct arm_prologue_cache *cache;
958 if (*this_cache == NULL)
959 *this_cache = arm_make_prologue_cache (this_frame);
962 func = get_frame_func (this_frame);
964 /* This is meant to halt the backtrace at "_start". Make sure we
965 don't halt it at a generic dummy frame. */
966 if (func <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
969 /* If we've hit a wall, stop. */
970 if (cache->prev_sp == 0)
973 id = frame_id_build (cache->prev_sp, func);
977 static struct value *
978 arm_prologue_prev_register (struct frame_info *this_frame,
982 struct arm_prologue_cache *cache;
984 if (*this_cache == NULL)
985 *this_cache = arm_make_prologue_cache (this_frame);
988 /* If we are asked to unwind the PC, then we need to return the LR
989 instead. The prologue may save PC, but it will point into this
990 frame's prologue, not the next frame's resume location. Also
991 strip the saved T bit. A valid LR may have the low bit set, but
992 a valid PC never does. */
993 if (prev_regnum == ARM_PC_REGNUM)
997 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
998 return frame_unwind_got_constant (this_frame, prev_regnum,
999 arm_addr_bits_remove (lr));
1002 /* SP is generally not saved to the stack, but this frame is
1003 identified by the next frame's stack pointer at the time of the call.
1004 The value was already reconstructed into PREV_SP. */
1005 if (prev_regnum == ARM_SP_REGNUM)
1006 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1008 /* The CPSR may have been changed by the call instruction and by the
1009 called function. The only bit we can reconstruct is the T bit,
1010 by checking the low bit of LR as of the call. This is a reliable
1011 indicator of Thumb-ness except for some ARM v4T pre-interworking
1012 Thumb code, which could get away with a clear low bit as long as
1013 the called function did not use bx. Guess that all other
1014 bits are unchanged; the condition flags are presumably lost,
1015 but the processor status is likely valid. */
1016 if (prev_regnum == ARM_PS_REGNUM)
1020 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1021 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1022 if (IS_THUMB_ADDR (lr))
1026 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1029 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1033 struct frame_unwind arm_prologue_unwind = {
1035 arm_prologue_this_id,
1036 arm_prologue_prev_register,
1038 default_frame_sniffer
1041 static struct arm_prologue_cache *
1042 arm_make_stub_cache (struct frame_info *this_frame)
1045 struct arm_prologue_cache *cache;
1046 CORE_ADDR unwound_fp;
1048 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1049 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1051 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
1056 /* Our frame ID for a stub frame is the current SP and LR. */
1059 arm_stub_this_id (struct frame_info *this_frame,
1061 struct frame_id *this_id)
1063 struct arm_prologue_cache *cache;
1065 if (*this_cache == NULL)
1066 *this_cache = arm_make_stub_cache (this_frame);
1067 cache = *this_cache;
1069 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
1073 arm_stub_unwind_sniffer (const struct frame_unwind *self,
1074 struct frame_info *this_frame,
1075 void **this_prologue_cache)
1077 CORE_ADDR addr_in_block;
1080 addr_in_block = get_frame_address_in_block (this_frame);
1081 if (in_plt_section (addr_in_block, NULL)
1082 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1088 struct frame_unwind arm_stub_unwind = {
1091 arm_prologue_prev_register,
1093 arm_stub_unwind_sniffer
1097 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1099 struct arm_prologue_cache *cache;
1101 if (*this_cache == NULL)
1102 *this_cache = arm_make_prologue_cache (this_frame);
1103 cache = *this_cache;
1105 return cache->prev_sp - cache->framesize;
1108 struct frame_base arm_normal_base = {
1109 &arm_prologue_unwind,
1110 arm_normal_frame_base,
1111 arm_normal_frame_base,
1112 arm_normal_frame_base
1115 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1116 dummy frame. The frame ID's base needs to match the TOS value
1117 saved by save_dummy_frame_tos() and returned from
1118 arm_push_dummy_call, and the PC needs to match the dummy frame's
1121 static struct frame_id
1122 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1124 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1125 get_frame_pc (this_frame));
1128 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1129 be used to construct the previous frame's ID, after looking up the
1130 containing function). */
1133 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1136 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1137 return arm_addr_bits_remove (pc);
1141 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1143 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1146 static struct value *
1147 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1155 /* The PC is normally copied from the return column, which
1156 describes saves of LR. However, that version may have an
1157 extra bit set to indicate Thumb state. The bit is not
1159 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1160 return frame_unwind_got_constant (this_frame, regnum,
1161 arm_addr_bits_remove (lr));
1164 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1167 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1168 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1169 if (IS_THUMB_ADDR (lr))
1173 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1176 internal_error (__FILE__, __LINE__,
1177 _("Unexpected register %d"), regnum);
1182 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1183 struct dwarf2_frame_state_reg *reg,
1184 struct frame_info *this_frame)
1190 reg->how = DWARF2_FRAME_REG_FN;
1191 reg->loc.fn = arm_dwarf2_prev_register;
1194 reg->how = DWARF2_FRAME_REG_CFA;
1199 /* When arguments must be pushed onto the stack, they go on in reverse
1200 order. The code below implements a FILO (stack) to do this. */
1205 struct stack_item *prev;
1209 static struct stack_item *
1210 push_stack_item (struct stack_item *prev, void *contents, int len)
1212 struct stack_item *si;
1213 si = xmalloc (sizeof (struct stack_item));
1214 si->data = xmalloc (len);
1217 memcpy (si->data, contents, len);
1221 static struct stack_item *
1222 pop_stack_item (struct stack_item *si)
1224 struct stack_item *dead = si;
1232 /* Return the alignment (in bytes) of the given type. */
1235 arm_type_align (struct type *t)
1241 t = check_typedef (t);
1242 switch (TYPE_CODE (t))
1245 /* Should never happen. */
1246 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1250 case TYPE_CODE_ENUM:
1254 case TYPE_CODE_RANGE:
1255 case TYPE_CODE_BITSTRING:
1257 case TYPE_CODE_CHAR:
1258 case TYPE_CODE_BOOL:
1259 return TYPE_LENGTH (t);
1261 case TYPE_CODE_ARRAY:
1262 case TYPE_CODE_COMPLEX:
1263 /* TODO: What about vector types? */
1264 return arm_type_align (TYPE_TARGET_TYPE (t));
1266 case TYPE_CODE_STRUCT:
1267 case TYPE_CODE_UNION:
1269 for (n = 0; n < TYPE_NFIELDS (t); n++)
1271 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1279 /* We currently only support passing parameters in integer registers. This
1280 conforms with GCC's default model. Several other variants exist and
1281 we should probably support some of them based on the selected ABI. */
1284 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1285 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1286 struct value **args, CORE_ADDR sp, int struct_return,
1287 CORE_ADDR struct_addr)
1292 struct stack_item *si = NULL;
1294 /* Set the return address. For the ARM, the return breakpoint is
1295 always at BP_ADDR. */
1296 /* XXX Fix for Thumb. */
1297 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1299 /* Walk through the list of args and determine how large a temporary
1300 stack is required. Need to take care here as structs may be
1301 passed on the stack, and we have to to push them. */
1304 argreg = ARM_A1_REGNUM;
1307 /* The struct_return pointer occupies the first parameter
1308 passing register. */
1312 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1313 gdbarch_register_name (gdbarch, argreg),
1314 paddr (struct_addr));
1315 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1319 for (argnum = 0; argnum < nargs; argnum++)
1322 struct type *arg_type;
1323 struct type *target_type;
1324 enum type_code typecode;
1328 arg_type = check_typedef (value_type (args[argnum]));
1329 len = TYPE_LENGTH (arg_type);
1330 target_type = TYPE_TARGET_TYPE (arg_type);
1331 typecode = TYPE_CODE (arg_type);
1332 val = value_contents_writeable (args[argnum]);
1334 align = arm_type_align (arg_type);
1335 /* Round alignment up to a whole number of words. */
1336 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1337 /* Different ABIs have different maximum alignments. */
1338 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1340 /* The APCS ABI only requires word alignment. */
1341 align = INT_REGISTER_SIZE;
1345 /* The AAPCS requires at most doubleword alignment. */
1346 if (align > INT_REGISTER_SIZE * 2)
1347 align = INT_REGISTER_SIZE * 2;
1350 /* Push stack padding for dowubleword alignment. */
1351 if (nstack & (align - 1))
1353 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1354 nstack += INT_REGISTER_SIZE;
1357 /* Doubleword aligned quantities must go in even register pairs. */
1358 if (argreg <= ARM_LAST_ARG_REGNUM
1359 && align > INT_REGISTER_SIZE
1363 /* If the argument is a pointer to a function, and it is a
1364 Thumb function, create a LOCAL copy of the value and set
1365 the THUMB bit in it. */
1366 if (TYPE_CODE_PTR == typecode
1367 && target_type != NULL
1368 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1370 CORE_ADDR regval = extract_unsigned_integer (val, len);
1371 if (arm_pc_is_thumb (regval))
1374 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1378 /* Copy the argument to general registers or the stack in
1379 register-sized pieces. Large arguments are split between
1380 registers and stack. */
1383 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1385 if (argreg <= ARM_LAST_ARG_REGNUM)
1387 /* The argument is being passed in a general purpose
1389 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1390 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1391 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1393 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1395 gdbarch_register_name
1397 phex (regval, INT_REGISTER_SIZE));
1398 regcache_cooked_write_unsigned (regcache, argreg, regval);
1403 /* Push the arguments onto the stack. */
1405 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1407 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1408 nstack += INT_REGISTER_SIZE;
1415 /* If we have an odd number of words to push, then decrement the stack
1416 by one word now, so first stack argument will be dword aligned. */
1423 write_memory (sp, si->data, si->len);
1424 si = pop_stack_item (si);
1427 /* Finally, update teh SP register. */
1428 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1434 /* Always align the frame to an 8-byte boundary. This is required on
1435 some platforms and harmless on the rest. */
1438 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1440 /* Align the stack to eight bytes. */
1441 return sp & ~ (CORE_ADDR) 7;
1445 print_fpu_flags (int flags)
1447 if (flags & (1 << 0))
1448 fputs ("IVO ", stdout);
1449 if (flags & (1 << 1))
1450 fputs ("DVZ ", stdout);
1451 if (flags & (1 << 2))
1452 fputs ("OFL ", stdout);
1453 if (flags & (1 << 3))
1454 fputs ("UFL ", stdout);
1455 if (flags & (1 << 4))
1456 fputs ("INX ", stdout);
1460 /* Print interesting information about the floating point processor
1461 (if present) or emulator. */
1463 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1464 struct frame_info *frame, const char *args)
1466 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1469 type = (status >> 24) & 127;
1470 if (status & (1 << 31))
1471 printf (_("Hardware FPU type %d\n"), type);
1473 printf (_("Software FPU type %d\n"), type);
1474 /* i18n: [floating point unit] mask */
1475 fputs (_("mask: "), stdout);
1476 print_fpu_flags (status >> 16);
1477 /* i18n: [floating point unit] flags */
1478 fputs (_("flags: "), stdout);
1479 print_fpu_flags (status);
1482 /* Return the GDB type object for the "standard" data type of data in
1485 static struct type *
1486 arm_register_type (struct gdbarch *gdbarch, int regnum)
1488 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1489 return builtin_type_arm_ext;
1490 else if (regnum == ARM_SP_REGNUM)
1491 return builtin_type_void_data_ptr;
1492 else if (regnum == ARM_PC_REGNUM)
1493 return builtin_type_void_func_ptr;
1494 else if (regnum >= ARRAY_SIZE (arm_register_names))
1495 /* These registers are only supported on targets which supply
1496 an XML description. */
1497 return builtin_type_int0;
1499 return builtin_type_uint32;
1502 /* Map a DWARF register REGNUM onto the appropriate GDB register
1506 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1508 /* Core integer regs. */
1509 if (reg >= 0 && reg <= 15)
1512 /* Legacy FPA encoding. These were once used in a way which
1513 overlapped with VFP register numbering, so their use is
1514 discouraged, but GDB doesn't support the ARM toolchain
1515 which used them for VFP. */
1516 if (reg >= 16 && reg <= 23)
1517 return ARM_F0_REGNUM + reg - 16;
1519 /* New assignments for the FPA registers. */
1520 if (reg >= 96 && reg <= 103)
1521 return ARM_F0_REGNUM + reg - 96;
1523 /* WMMX register assignments. */
1524 if (reg >= 104 && reg <= 111)
1525 return ARM_WCGR0_REGNUM + reg - 104;
1527 if (reg >= 112 && reg <= 127)
1528 return ARM_WR0_REGNUM + reg - 112;
1530 if (reg >= 192 && reg <= 199)
1531 return ARM_WC0_REGNUM + reg - 192;
1536 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1538 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1541 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
1543 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1544 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1546 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1547 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1549 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1550 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1552 if (reg < NUM_GREGS)
1553 return SIM_ARM_R0_REGNUM + reg;
1556 if (reg < NUM_FREGS)
1557 return SIM_ARM_FP0_REGNUM + reg;
1560 if (reg < NUM_SREGS)
1561 return SIM_ARM_FPS_REGNUM + reg;
1564 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1567 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1568 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1569 It is thought that this is is the floating-point register format on
1570 little-endian systems. */
1573 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1574 void *dbl, int endianess)
1578 if (endianess == BFD_ENDIAN_BIG)
1579 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1581 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1583 floatformat_from_doublest (fmt, &d, dbl);
1587 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1592 floatformat_to_doublest (fmt, ptr, &d);
1593 if (endianess == BFD_ENDIAN_BIG)
1594 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1596 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1601 condition_true (unsigned long cond, unsigned long status_reg)
1603 if (cond == INST_AL || cond == INST_NV)
1609 return ((status_reg & FLAG_Z) != 0);
1611 return ((status_reg & FLAG_Z) == 0);
1613 return ((status_reg & FLAG_C) != 0);
1615 return ((status_reg & FLAG_C) == 0);
1617 return ((status_reg & FLAG_N) != 0);
1619 return ((status_reg & FLAG_N) == 0);
1621 return ((status_reg & FLAG_V) != 0);
1623 return ((status_reg & FLAG_V) == 0);
1625 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1627 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1629 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1631 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1633 return (((status_reg & FLAG_Z) == 0) &&
1634 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1636 return (((status_reg & FLAG_Z) != 0) ||
1637 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1642 /* Support routines for single stepping. Calculate the next PC value. */
1643 #define submask(x) ((1L << ((x) + 1)) - 1)
1644 #define bit(obj,st) (((obj) >> (st)) & 1)
1645 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1646 #define sbits(obj,st,fn) \
1647 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1648 #define BranchDest(addr,instr) \
1649 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1652 static unsigned long
1653 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1654 unsigned long pc_val, unsigned long status_reg)
1656 unsigned long res, shift;
1657 int rm = bits (inst, 0, 3);
1658 unsigned long shifttype = bits (inst, 5, 6);
1662 int rs = bits (inst, 8, 11);
1663 shift = (rs == 15 ? pc_val + 8
1664 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1667 shift = bits (inst, 7, 11);
1670 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1671 + (bit (inst, 4) ? 12 : 8))
1672 : get_frame_register_unsigned (frame, rm));
1677 res = shift >= 32 ? 0 : res << shift;
1681 res = shift >= 32 ? 0 : res >> shift;
1687 res = ((res & 0x80000000L)
1688 ? ~((~res) >> shift) : res >> shift);
1691 case 3: /* ROR/RRX */
1694 res = (res >> 1) | (carry ? 0x80000000L : 0);
1696 res = (res >> shift) | (res << (32 - shift));
1700 return res & 0xffffffff;
1703 /* Return number of 1-bits in VAL. */
1706 bitcount (unsigned long val)
1709 for (nbits = 0; val != 0; nbits++)
1710 val &= val - 1; /* delete rightmost 1-bit in val */
1715 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1717 struct gdbarch *gdbarch = get_frame_arch (frame);
1718 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1719 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1720 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1721 unsigned long offset;
1723 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1727 /* Fetch the saved PC from the stack. It's stored above
1728 all of the other registers. */
1729 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1730 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1731 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1732 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1734 error (_("Infinite loop detected"));
1736 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1738 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1739 unsigned long cond = bits (inst1, 8, 11);
1740 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1741 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1743 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1745 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1747 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1749 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1750 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1751 nextpc = pc_val + offset;
1752 /* For BLX make sure to clear the low bits. */
1753 if (bits (inst2, 11, 12) == 1)
1754 nextpc = nextpc & 0xfffffffc;
1756 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1758 if (bits (inst1, 3, 6) == 0x0f)
1761 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1763 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1765 error (_("Infinite loop detected"));
1772 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1774 struct gdbarch *gdbarch = get_frame_arch (frame);
1775 unsigned long pc_val;
1776 unsigned long this_instr;
1777 unsigned long status;
1780 if (arm_frame_is_thumb (frame))
1781 return thumb_get_next_pc (frame, pc);
1783 pc_val = (unsigned long) pc;
1784 this_instr = read_memory_unsigned_integer (pc, 4);
1785 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1786 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1788 if (bits (this_instr, 28, 31) == INST_NV)
1789 switch (bits (this_instr, 24, 27))
1794 /* Branch with Link and change to Thumb. */
1795 nextpc = BranchDest (pc, this_instr);
1796 nextpc |= bit (this_instr, 24) << 1;
1798 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1800 error (_("Infinite loop detected"));
1806 /* Coprocessor register transfer. */
1807 if (bits (this_instr, 12, 15) == 15)
1808 error (_("Invalid update to pc in instruction"));
1811 else if (condition_true (bits (this_instr, 28, 31), status))
1813 switch (bits (this_instr, 24, 27))
1816 case 0x1: /* data processing */
1820 unsigned long operand1, operand2, result = 0;
1824 if (bits (this_instr, 12, 15) != 15)
1827 if (bits (this_instr, 22, 25) == 0
1828 && bits (this_instr, 4, 7) == 9) /* multiply */
1829 error (_("Invalid update to pc in instruction"));
1831 /* BX <reg>, BLX <reg> */
1832 if (bits (this_instr, 4, 27) == 0x12fff1
1833 || bits (this_instr, 4, 27) == 0x12fff3)
1835 rn = bits (this_instr, 0, 3);
1836 result = (rn == 15) ? pc_val + 8
1837 : get_frame_register_unsigned (frame, rn);
1838 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1842 error (_("Infinite loop detected"));
1847 /* Multiply into PC */
1848 c = (status & FLAG_C) ? 1 : 0;
1849 rn = bits (this_instr, 16, 19);
1850 operand1 = (rn == 15) ? pc_val + 8
1851 : get_frame_register_unsigned (frame, rn);
1853 if (bit (this_instr, 25))
1855 unsigned long immval = bits (this_instr, 0, 7);
1856 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1857 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1860 else /* operand 2 is a shifted register */
1861 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1863 switch (bits (this_instr, 21, 24))
1866 result = operand1 & operand2;
1870 result = operand1 ^ operand2;
1874 result = operand1 - operand2;
1878 result = operand2 - operand1;
1882 result = operand1 + operand2;
1886 result = operand1 + operand2 + c;
1890 result = operand1 - operand2 + c;
1894 result = operand2 - operand1 + c;
1900 case 0xb: /* tst, teq, cmp, cmn */
1901 result = (unsigned long) nextpc;
1905 result = operand1 | operand2;
1909 /* Always step into a function. */
1914 result = operand1 & ~operand2;
1921 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1925 error (_("Infinite loop detected"));
1930 case 0x5: /* data transfer */
1933 if (bit (this_instr, 20))
1936 if (bits (this_instr, 12, 15) == 15)
1942 if (bit (this_instr, 22))
1943 error (_("Invalid update to pc in instruction"));
1945 /* byte write to PC */
1946 rn = bits (this_instr, 16, 19);
1947 base = (rn == 15) ? pc_val + 8
1948 : get_frame_register_unsigned (frame, rn);
1949 if (bit (this_instr, 24))
1952 int c = (status & FLAG_C) ? 1 : 0;
1953 unsigned long offset =
1954 (bit (this_instr, 25)
1955 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
1956 : bits (this_instr, 0, 11));
1958 if (bit (this_instr, 23))
1963 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1966 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1969 error (_("Infinite loop detected"));
1975 case 0x9: /* block transfer */
1976 if (bit (this_instr, 20))
1979 if (bit (this_instr, 15))
1984 if (bit (this_instr, 23))
1987 unsigned long reglist = bits (this_instr, 0, 14);
1988 offset = bitcount (reglist) * 4;
1989 if (bit (this_instr, 24)) /* pre */
1992 else if (bit (this_instr, 24))
1996 unsigned long rn_val =
1997 get_frame_register_unsigned (frame,
1998 bits (this_instr, 16, 19));
2000 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2004 nextpc = gdbarch_addr_bits_remove
2007 error (_("Infinite loop detected"));
2012 case 0xb: /* branch & link */
2013 case 0xa: /* branch */
2015 nextpc = BranchDest (pc, this_instr);
2017 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2019 error (_("Infinite loop detected"));
2025 case 0xe: /* coproc ops */
2030 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
2038 /* single_step() is called just before we want to resume the inferior,
2039 if we want to single-step it but there is no hardware or kernel
2040 single-step support. We find the target of the coming instruction
2041 and breakpoint it. */
2044 arm_software_single_step (struct frame_info *frame)
2046 /* NOTE: This may insert the wrong breakpoint instruction when
2047 single-stepping over a mode-changing instruction, if the
2048 CPSR heuristics are used. */
2050 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
2051 insert_single_step_breakpoint (next_pc);
2056 #include "bfd-in2.h"
2057 #include "libcoff.h"
2060 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2062 if (arm_pc_is_thumb (memaddr))
2064 static asymbol *asym;
2065 static combined_entry_type ce;
2066 static struct coff_symbol_struct csym;
2067 static struct bfd fake_bfd;
2068 static bfd_target fake_target;
2070 if (csym.native == NULL)
2072 /* Create a fake symbol vector containing a Thumb symbol.
2073 This is solely so that the code in print_insn_little_arm()
2074 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2075 the presence of a Thumb symbol and switch to decoding
2076 Thumb instructions. */
2078 fake_target.flavour = bfd_target_coff_flavour;
2079 fake_bfd.xvec = &fake_target;
2080 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2082 csym.symbol.the_bfd = &fake_bfd;
2083 csym.symbol.name = "fake";
2084 asym = (asymbol *) & csym;
2087 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2088 info->symbols = &asym;
2091 info->symbols = NULL;
2093 if (info->endian == BFD_ENDIAN_BIG)
2094 return print_insn_big_arm (memaddr, info);
2096 return print_insn_little_arm (memaddr, info);
2099 /* The following define instruction sequences that will cause ARM
2100 cpu's to take an undefined instruction trap. These are used to
2101 signal a breakpoint to GDB.
2103 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2104 modes. A different instruction is required for each mode. The ARM
2105 cpu's can also be big or little endian. Thus four different
2106 instructions are needed to support all cases.
2108 Note: ARMv4 defines several new instructions that will take the
2109 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2110 not in fact add the new instructions. The new undefined
2111 instructions in ARMv4 are all instructions that had no defined
2112 behaviour in earlier chips. There is no guarantee that they will
2113 raise an exception, but may be treated as NOP's. In practice, it
2114 may only safe to rely on instructions matching:
2116 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2117 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2118 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2120 Even this may only true if the condition predicate is true. The
2121 following use a condition predicate of ALWAYS so it is always TRUE.
2123 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2124 and NetBSD all use a software interrupt rather than an undefined
2125 instruction to force a trap. This can be handled by by the
2126 abi-specific code during establishment of the gdbarch vector. */
2128 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2129 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2130 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2131 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2133 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2134 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2135 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2136 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2138 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2139 the program counter value to determine whether a 16-bit or 32-bit
2140 breakpoint should be used. It returns a pointer to a string of
2141 bytes that encode a breakpoint instruction, stores the length of
2142 the string to *lenptr, and adjusts the program counter (if
2143 necessary) to point to the actual memory location where the
2144 breakpoint should be inserted. */
2146 static const unsigned char *
2147 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
2149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2151 if (arm_pc_is_thumb (*pcptr))
2153 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2154 *lenptr = tdep->thumb_breakpoint_size;
2155 return tdep->thumb_breakpoint;
2159 *lenptr = tdep->arm_breakpoint_size;
2160 return tdep->arm_breakpoint;
2164 /* Extract from an array REGBUF containing the (raw) register state a
2165 function return value of type TYPE, and copy that, in virtual
2166 format, into VALBUF. */
2169 arm_extract_return_value (struct type *type, struct regcache *regs,
2172 struct gdbarch *gdbarch = get_regcache_arch (regs);
2174 if (TYPE_CODE_FLT == TYPE_CODE (type))
2176 switch (gdbarch_tdep (gdbarch)->fp_model)
2180 /* The value is in register F0 in internal format. We need to
2181 extract the raw value and then convert it to the desired
2183 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2185 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2186 convert_from_extended (floatformat_from_type (type), tmpbuf,
2187 valbuf, gdbarch_byte_order (gdbarch));
2191 case ARM_FLOAT_SOFT_FPA:
2192 case ARM_FLOAT_SOFT_VFP:
2193 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2194 if (TYPE_LENGTH (type) > 4)
2195 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2196 valbuf + INT_REGISTER_SIZE);
2201 (__FILE__, __LINE__,
2202 _("arm_extract_return_value: Floating point model not supported"));
2206 else if (TYPE_CODE (type) == TYPE_CODE_INT
2207 || TYPE_CODE (type) == TYPE_CODE_CHAR
2208 || TYPE_CODE (type) == TYPE_CODE_BOOL
2209 || TYPE_CODE (type) == TYPE_CODE_PTR
2210 || TYPE_CODE (type) == TYPE_CODE_REF
2211 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2213 /* If the the type is a plain integer, then the access is
2214 straight-forward. Otherwise we have to play around a bit more. */
2215 int len = TYPE_LENGTH (type);
2216 int regno = ARM_A1_REGNUM;
2221 /* By using store_unsigned_integer we avoid having to do
2222 anything special for small big-endian values. */
2223 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2224 store_unsigned_integer (valbuf,
2225 (len > INT_REGISTER_SIZE
2226 ? INT_REGISTER_SIZE : len),
2228 len -= INT_REGISTER_SIZE;
2229 valbuf += INT_REGISTER_SIZE;
2234 /* For a structure or union the behaviour is as if the value had
2235 been stored to word-aligned memory and then loaded into
2236 registers with 32-bit load instruction(s). */
2237 int len = TYPE_LENGTH (type);
2238 int regno = ARM_A1_REGNUM;
2239 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2243 regcache_cooked_read (regs, regno++, tmpbuf);
2244 memcpy (valbuf, tmpbuf,
2245 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2246 len -= INT_REGISTER_SIZE;
2247 valbuf += INT_REGISTER_SIZE;
2253 /* Will a function return an aggregate type in memory or in a
2254 register? Return 0 if an aggregate type can be returned in a
2255 register, 1 if it must be returned in memory. */
2258 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2261 enum type_code code;
2263 CHECK_TYPEDEF (type);
2265 /* In the ARM ABI, "integer" like aggregate types are returned in
2266 registers. For an aggregate type to be integer like, its size
2267 must be less than or equal to INT_REGISTER_SIZE and the
2268 offset of each addressable subfield must be zero. Note that bit
2269 fields are not addressable, and all addressable subfields of
2270 unions always start at offset zero.
2272 This function is based on the behaviour of GCC 2.95.1.
2273 See: gcc/arm.c: arm_return_in_memory() for details.
2275 Note: All versions of GCC before GCC 2.95.2 do not set up the
2276 parameters correctly for a function returning the following
2277 structure: struct { float f;}; This should be returned in memory,
2278 not a register. Richard Earnshaw sent me a patch, but I do not
2279 know of any way to detect if a function like the above has been
2280 compiled with the correct calling convention. */
2282 /* All aggregate types that won't fit in a register must be returned
2284 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2289 /* The AAPCS says all aggregates not larger than a word are returned
2291 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2294 /* The only aggregate types that can be returned in a register are
2295 structs and unions. Arrays must be returned in memory. */
2296 code = TYPE_CODE (type);
2297 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2302 /* Assume all other aggregate types can be returned in a register.
2303 Run a check for structures, unions and arrays. */
2306 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2309 /* Need to check if this struct/union is "integer" like. For
2310 this to be true, its size must be less than or equal to
2311 INT_REGISTER_SIZE and the offset of each addressable
2312 subfield must be zero. Note that bit fields are not
2313 addressable, and unions always start at offset zero. If any
2314 of the subfields is a floating point type, the struct/union
2315 cannot be an integer type. */
2317 /* For each field in the object, check:
2318 1) Is it FP? --> yes, nRc = 1;
2319 2) Is it addressable (bitpos != 0) and
2320 not packed (bitsize == 0)?
2324 for (i = 0; i < TYPE_NFIELDS (type); i++)
2326 enum type_code field_type_code;
2327 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2329 /* Is it a floating point type field? */
2330 if (field_type_code == TYPE_CODE_FLT)
2336 /* If bitpos != 0, then we have to care about it. */
2337 if (TYPE_FIELD_BITPOS (type, i) != 0)
2339 /* Bitfields are not addressable. If the field bitsize is
2340 zero, then the field is not packed. Hence it cannot be
2341 a bitfield or any other packed type. */
2342 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2354 /* Write into appropriate registers a function return value of type
2355 TYPE, given in virtual format. */
2358 arm_store_return_value (struct type *type, struct regcache *regs,
2359 const gdb_byte *valbuf)
2361 struct gdbarch *gdbarch = get_regcache_arch (regs);
2363 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2365 char buf[MAX_REGISTER_SIZE];
2367 switch (gdbarch_tdep (gdbarch)->fp_model)
2371 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2372 gdbarch_byte_order (gdbarch));
2373 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2376 case ARM_FLOAT_SOFT_FPA:
2377 case ARM_FLOAT_SOFT_VFP:
2378 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2379 if (TYPE_LENGTH (type) > 4)
2380 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2381 valbuf + INT_REGISTER_SIZE);
2386 (__FILE__, __LINE__,
2387 _("arm_store_return_value: Floating point model not supported"));
2391 else if (TYPE_CODE (type) == TYPE_CODE_INT
2392 || TYPE_CODE (type) == TYPE_CODE_CHAR
2393 || TYPE_CODE (type) == TYPE_CODE_BOOL
2394 || TYPE_CODE (type) == TYPE_CODE_PTR
2395 || TYPE_CODE (type) == TYPE_CODE_REF
2396 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2398 if (TYPE_LENGTH (type) <= 4)
2400 /* Values of one word or less are zero/sign-extended and
2402 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2403 LONGEST val = unpack_long (type, valbuf);
2405 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2406 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2410 /* Integral values greater than one word are stored in consecutive
2411 registers starting with r0. This will always be a multiple of
2412 the regiser size. */
2413 int len = TYPE_LENGTH (type);
2414 int regno = ARM_A1_REGNUM;
2418 regcache_cooked_write (regs, regno++, valbuf);
2419 len -= INT_REGISTER_SIZE;
2420 valbuf += INT_REGISTER_SIZE;
2426 /* For a structure or union the behaviour is as if the value had
2427 been stored to word-aligned memory and then loaded into
2428 registers with 32-bit load instruction(s). */
2429 int len = TYPE_LENGTH (type);
2430 int regno = ARM_A1_REGNUM;
2431 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2435 memcpy (tmpbuf, valbuf,
2436 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2437 regcache_cooked_write (regs, regno++, tmpbuf);
2438 len -= INT_REGISTER_SIZE;
2439 valbuf += INT_REGISTER_SIZE;
2445 /* Handle function return values. */
2447 static enum return_value_convention
2448 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2449 struct type *valtype, struct regcache *regcache,
2450 gdb_byte *readbuf, const gdb_byte *writebuf)
2452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2454 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2455 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2456 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2458 if (tdep->struct_return == pcc_struct_return
2459 || arm_return_in_memory (gdbarch, valtype))
2460 return RETURN_VALUE_STRUCT_CONVENTION;
2464 arm_store_return_value (valtype, regcache, writebuf);
2467 arm_extract_return_value (valtype, regcache, readbuf);
2469 return RETURN_VALUE_REGISTER_CONVENTION;
2474 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2477 char buf[INT_REGISTER_SIZE];
2478 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2480 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2482 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2486 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2490 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2491 return the target PC. Otherwise return 0. */
2494 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2498 CORE_ADDR start_addr;
2500 /* Find the starting address and name of the function containing the PC. */
2501 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2504 /* If PC is in a Thumb call or return stub, return the address of the
2505 target PC, which is in a register. The thunk functions are called
2506 _call_via_xx, where x is the register name. The possible names
2507 are r0-r9, sl, fp, ip, sp, and lr. */
2508 if (strncmp (name, "_call_via_", 10) == 0)
2510 /* Use the name suffix to determine which register contains the
2512 static char *table[15] =
2513 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2514 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2517 int offset = strlen (name) - 2;
2519 for (regno = 0; regno <= 14; regno++)
2520 if (strcmp (&name[offset], table[regno]) == 0)
2521 return get_frame_register_unsigned (frame, regno);
2524 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2525 non-interworking calls to foo. We could decode the stubs
2526 to find the target but it's easier to use the symbol table. */
2527 namelen = strlen (name);
2528 if (name[0] == '_' && name[1] == '_'
2529 && ((namelen > 2 + strlen ("_from_thumb")
2530 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2531 strlen ("_from_thumb")) == 0)
2532 || (namelen > 2 + strlen ("_from_arm")
2533 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2534 strlen ("_from_arm")) == 0)))
2537 int target_len = namelen - 2;
2538 struct minimal_symbol *minsym;
2539 struct objfile *objfile;
2540 struct obj_section *sec;
2542 if (name[namelen - 1] == 'b')
2543 target_len -= strlen ("_from_thumb");
2545 target_len -= strlen ("_from_arm");
2547 target_name = alloca (target_len + 1);
2548 memcpy (target_name, name + 2, target_len);
2549 target_name[target_len] = '\0';
2551 sec = find_pc_section (pc);
2552 objfile = (sec == NULL) ? NULL : sec->objfile;
2553 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2555 return SYMBOL_VALUE_ADDRESS (minsym);
2560 return 0; /* not a stub */
2564 set_arm_command (char *args, int from_tty)
2566 printf_unfiltered (_("\
2567 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2568 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2572 show_arm_command (char *args, int from_tty)
2574 cmd_show_list (showarmcmdlist, from_tty, "");
2578 arm_update_current_architecture (void)
2580 struct gdbarch_info info;
2582 /* If the current architecture is not ARM, we have nothing to do. */
2583 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm)
2586 /* Update the architecture. */
2587 gdbarch_info_init (&info);
2589 if (!gdbarch_update_p (info))
2590 internal_error (__FILE__, __LINE__, "could not update architecture");
2594 set_fp_model_sfunc (char *args, int from_tty,
2595 struct cmd_list_element *c)
2597 enum arm_float_model fp_model;
2599 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2600 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2602 arm_fp_model = fp_model;
2606 if (fp_model == ARM_FLOAT_LAST)
2607 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2610 arm_update_current_architecture ();
2614 show_fp_model (struct ui_file *file, int from_tty,
2615 struct cmd_list_element *c, const char *value)
2617 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2619 if (arm_fp_model == ARM_FLOAT_AUTO
2620 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2621 fprintf_filtered (file, _("\
2622 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2623 fp_model_strings[tdep->fp_model]);
2625 fprintf_filtered (file, _("\
2626 The current ARM floating point model is \"%s\".\n"),
2627 fp_model_strings[arm_fp_model]);
2631 arm_set_abi (char *args, int from_tty,
2632 struct cmd_list_element *c)
2634 enum arm_abi_kind arm_abi;
2636 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2637 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2639 arm_abi_global = arm_abi;
2643 if (arm_abi == ARM_ABI_LAST)
2644 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2647 arm_update_current_architecture ();
2651 arm_show_abi (struct ui_file *file, int from_tty,
2652 struct cmd_list_element *c, const char *value)
2654 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2656 if (arm_abi_global == ARM_ABI_AUTO
2657 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2658 fprintf_filtered (file, _("\
2659 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2660 arm_abi_strings[tdep->arm_abi]);
2662 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2666 /* If the user changes the register disassembly style used for info
2667 register and other commands, we have to also switch the style used
2668 in opcodes for disassembly output. This function is run in the "set
2669 arm disassembly" command, and does that. */
2672 set_disassembly_style_sfunc (char *args, int from_tty,
2673 struct cmd_list_element *c)
2675 set_disassembly_style ();
2678 /* Return the ARM register name corresponding to register I. */
2680 arm_register_name (struct gdbarch *gdbarch, int i)
2682 if (i >= ARRAY_SIZE (arm_register_names))
2683 /* These registers are only supported on targets which supply
2684 an XML description. */
2687 return arm_register_names[i];
2691 set_disassembly_style (void)
2695 /* Find the style that the user wants. */
2696 for (current = 0; current < num_disassembly_options; current++)
2697 if (disassembly_style == valid_disassembly_styles[current])
2699 gdb_assert (current < num_disassembly_options);
2701 /* Synchronize the disassembler. */
2702 set_arm_regname_option (current);
2705 /* Test whether the coff symbol specific value corresponds to a Thumb
2709 coff_sym_is_thumb (int val)
2711 return (val == C_THUMBEXT ||
2712 val == C_THUMBSTAT ||
2713 val == C_THUMBEXTFUNC ||
2714 val == C_THUMBSTATFUNC ||
2715 val == C_THUMBLABEL);
2718 /* arm_coff_make_msymbol_special()
2719 arm_elf_make_msymbol_special()
2721 These functions test whether the COFF or ELF symbol corresponds to
2722 an address in thumb code, and set a "special" bit in a minimal
2723 symbol to indicate that it does. */
2726 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2728 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2730 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2732 MSYMBOL_SET_SPECIAL (msym);
2736 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2738 if (coff_sym_is_thumb (val))
2739 MSYMBOL_SET_SPECIAL (msym);
2743 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2745 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2747 /* If necessary, set the T bit. */
2751 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2752 if (arm_pc_is_thumb (pc))
2753 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
2755 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2756 val & ~(ULONGEST) CPSR_T);
2760 static struct value *
2761 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2763 const int *reg_p = baton;
2764 return value_of_register (*reg_p, frame);
2767 static enum gdb_osabi
2768 arm_elf_osabi_sniffer (bfd *abfd)
2770 unsigned int elfosabi;
2771 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2773 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2775 if (elfosabi == ELFOSABI_ARM)
2776 /* GNU tools use this value. Check note sections in this case,
2778 bfd_map_over_sections (abfd,
2779 generic_elf_osabi_sniff_abi_tag_sections,
2782 /* Anything else will be handled by the generic ELF sniffer. */
2787 /* Initialize the current architecture based on INFO. If possible,
2788 re-use an architecture from ARCHES, which is a list of
2789 architectures already created during this debugging session.
2791 Called e.g. at program startup, when reading a core file, and when
2792 reading a binary file. */
2794 static struct gdbarch *
2795 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2797 struct gdbarch_tdep *tdep;
2798 struct gdbarch *gdbarch;
2799 struct gdbarch_list *best_arch;
2800 enum arm_abi_kind arm_abi = arm_abi_global;
2801 enum arm_float_model fp_model = arm_fp_model;
2802 struct tdesc_arch_data *tdesc_data = NULL;
2804 int have_fpa_registers = 1;
2806 /* Check any target description for validity. */
2807 if (tdesc_has_registers (info.target_desc))
2809 /* For most registers we require GDB's default names; but also allow
2810 the numeric names for sp / lr / pc, as a convenience. */
2811 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
2812 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
2813 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
2815 const struct tdesc_feature *feature;
2818 feature = tdesc_find_feature (info.target_desc,
2819 "org.gnu.gdb.arm.core");
2820 if (feature == NULL)
2823 tdesc_data = tdesc_data_alloc ();
2826 for (i = 0; i < ARM_SP_REGNUM; i++)
2827 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2828 arm_register_names[i]);
2829 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2832 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2835 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
2838 valid_p &= tdesc_numbered_register (feature, tdesc_data,
2839 ARM_PS_REGNUM, "cpsr");
2843 tdesc_data_cleanup (tdesc_data);
2847 feature = tdesc_find_feature (info.target_desc,
2848 "org.gnu.gdb.arm.fpa");
2849 if (feature != NULL)
2852 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
2853 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
2854 arm_register_names[i]);
2857 tdesc_data_cleanup (tdesc_data);
2862 have_fpa_registers = 0;
2864 feature = tdesc_find_feature (info.target_desc,
2865 "org.gnu.gdb.xscale.iwmmxt");
2866 if (feature != NULL)
2868 static const char *const iwmmxt_names[] = {
2869 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2870 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2871 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2872 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2876 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
2878 &= tdesc_numbered_register (feature, tdesc_data, i,
2879 iwmmxt_names[i - ARM_WR0_REGNUM]);
2881 /* Check for the control registers, but do not fail if they
2883 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
2884 tdesc_numbered_register (feature, tdesc_data, i,
2885 iwmmxt_names[i - ARM_WR0_REGNUM]);
2887 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
2889 &= tdesc_numbered_register (feature, tdesc_data, i,
2890 iwmmxt_names[i - ARM_WR0_REGNUM]);
2894 tdesc_data_cleanup (tdesc_data);
2900 /* If we have an object to base this architecture on, try to determine
2903 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
2905 int ei_osabi, e_flags;
2907 switch (bfd_get_flavour (info.abfd))
2909 case bfd_target_aout_flavour:
2910 /* Assume it's an old APCS-style ABI. */
2911 arm_abi = ARM_ABI_APCS;
2914 case bfd_target_coff_flavour:
2915 /* Assume it's an old APCS-style ABI. */
2917 arm_abi = ARM_ABI_APCS;
2920 case bfd_target_elf_flavour:
2921 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2922 e_flags = elf_elfheader (info.abfd)->e_flags;
2924 if (ei_osabi == ELFOSABI_ARM)
2926 /* GNU tools used to use this value, but do not for EABI
2927 objects. There's nowhere to tag an EABI version
2928 anyway, so assume APCS. */
2929 arm_abi = ARM_ABI_APCS;
2931 else if (ei_osabi == ELFOSABI_NONE)
2933 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
2937 case EF_ARM_EABI_UNKNOWN:
2938 /* Assume GNU tools. */
2939 arm_abi = ARM_ABI_APCS;
2942 case EF_ARM_EABI_VER4:
2943 case EF_ARM_EABI_VER5:
2944 arm_abi = ARM_ABI_AAPCS;
2945 /* EABI binaries default to VFP float ordering. */
2946 if (fp_model == ARM_FLOAT_AUTO)
2947 fp_model = ARM_FLOAT_SOFT_VFP;
2951 /* Leave it as "auto". */
2952 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
2957 if (fp_model == ARM_FLOAT_AUTO)
2959 int e_flags = elf_elfheader (info.abfd)->e_flags;
2961 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
2964 /* Leave it as "auto". Strictly speaking this case
2965 means FPA, but almost nobody uses that now, and
2966 many toolchains fail to set the appropriate bits
2967 for the floating-point model they use. */
2969 case EF_ARM_SOFT_FLOAT:
2970 fp_model = ARM_FLOAT_SOFT_FPA;
2972 case EF_ARM_VFP_FLOAT:
2973 fp_model = ARM_FLOAT_VFP;
2975 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
2976 fp_model = ARM_FLOAT_SOFT_VFP;
2983 /* Leave it as "auto". */
2988 /* If there is already a candidate, use it. */
2989 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2991 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2993 if (arm_abi != ARM_ABI_AUTO
2994 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
2997 if (fp_model != ARM_FLOAT_AUTO
2998 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
3001 /* Found a match. */
3005 if (best_arch != NULL)
3007 if (tdesc_data != NULL)
3008 tdesc_data_cleanup (tdesc_data);
3009 return best_arch->gdbarch;
3012 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
3013 gdbarch = gdbarch_alloc (&info, tdep);
3015 /* Record additional information about the architecture we are defining.
3016 These are gdbarch discriminators, like the OSABI. */
3017 tdep->arm_abi = arm_abi;
3018 tdep->fp_model = fp_model;
3019 tdep->have_fpa_registers = have_fpa_registers;
3022 switch (info.byte_order)
3024 case BFD_ENDIAN_BIG:
3025 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3026 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3027 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3028 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3032 case BFD_ENDIAN_LITTLE:
3033 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3034 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3035 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3036 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3041 internal_error (__FILE__, __LINE__,
3042 _("arm_gdbarch_init: bad byte order for float format"));
3045 /* On ARM targets char defaults to unsigned. */
3046 set_gdbarch_char_signed (gdbarch, 0);
3048 /* This should be low enough for everything. */
3049 tdep->lowest_pc = 0x20;
3050 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3052 /* The default, for both APCS and AAPCS, is to return small
3053 structures in registers. */
3054 tdep->struct_return = reg_struct_return;
3056 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
3057 set_gdbarch_frame_align (gdbarch, arm_frame_align);
3059 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3061 /* Frame handling. */
3062 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
3063 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3064 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3066 frame_base_set_default (gdbarch, &arm_normal_base);
3068 /* Address manipulation. */
3069 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3070 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3072 /* Advance PC across function entry code. */
3073 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3075 /* Skip trampolines. */
3076 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3078 /* The stack grows downward. */
3079 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3081 /* Breakpoint manipulation. */
3082 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3084 /* Information about registers, etc. */
3085 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3086 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3087 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3088 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3089 set_gdbarch_register_type (gdbarch, arm_register_type);
3091 /* This "info float" is FPA-specific. Use the generic version if we
3093 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3094 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3096 /* Internal <-> external register number maps. */
3097 set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3098 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3099 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3101 set_gdbarch_register_name (gdbarch, arm_register_name);
3103 /* Returning results. */
3104 set_gdbarch_return_value (gdbarch, arm_return_value);
3107 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3109 /* Minsymbol frobbing. */
3110 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3111 set_gdbarch_coff_make_msymbol_special (gdbarch,
3112 arm_coff_make_msymbol_special);
3114 /* Virtual tables. */
3115 set_gdbarch_vbit_in_delta (gdbarch, 1);
3117 /* Hook in the ABI-specific overrides, if they have been registered. */
3118 gdbarch_init_osabi (info, gdbarch);
3120 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3122 /* Add some default predicates. */
3123 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3124 dwarf2_append_unwinders (gdbarch);
3125 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
3127 /* Now we have tuned the configuration, set a few final things,
3128 based on what the OS ABI has told us. */
3130 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3131 binaries are always marked. */
3132 if (tdep->arm_abi == ARM_ABI_AUTO)
3133 tdep->arm_abi = ARM_ABI_APCS;
3135 /* We used to default to FPA for generic ARM, but almost nobody
3136 uses that now, and we now provide a way for the user to force
3137 the model. So default to the most useful variant. */
3138 if (tdep->fp_model == ARM_FLOAT_AUTO)
3139 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3141 if (tdep->jb_pc >= 0)
3142 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3144 /* Floating point sizes and format. */
3145 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3146 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3148 set_gdbarch_double_format
3149 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3150 set_gdbarch_long_double_format
3151 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3155 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3156 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3160 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3162 /* Add standard register aliases. We add aliases even for those
3163 nanes which are used by the current architecture - it's simpler,
3164 and does no harm, since nothing ever lists user registers. */
3165 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3166 user_reg_add (gdbarch, arm_register_aliases[i].name,
3167 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3173 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3175 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3180 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3181 (unsigned long) tdep->lowest_pc);
3184 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3187 _initialize_arm_tdep (void)
3189 struct ui_file *stb;
3191 struct cmd_list_element *new_set, *new_show;
3192 const char *setname;
3193 const char *setdesc;
3194 const char *const *regnames;
3196 static char *helptext;
3197 char regdesc[1024], *rdptr = regdesc;
3198 size_t rest = sizeof (regdesc);
3200 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3202 /* Register an ELF OS ABI sniffer for ARM binaries. */
3203 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3204 bfd_target_elf_flavour,
3205 arm_elf_osabi_sniffer);
3207 /* Get the number of possible sets of register names defined in opcodes. */
3208 num_disassembly_options = get_arm_regname_num_options ();
3210 /* Add root prefix command for all "set arm"/"show arm" commands. */
3211 add_prefix_cmd ("arm", no_class, set_arm_command,
3212 _("Various ARM-specific commands."),
3213 &setarmcmdlist, "set arm ", 0, &setlist);
3215 add_prefix_cmd ("arm", no_class, show_arm_command,
3216 _("Various ARM-specific commands."),
3217 &showarmcmdlist, "show arm ", 0, &showlist);
3219 /* Sync the opcode insn printer with our register viewer. */
3220 parse_arm_disassembler_option ("reg-names-std");
3222 /* Initialize the array that will be passed to
3223 add_setshow_enum_cmd(). */
3224 valid_disassembly_styles
3225 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3226 for (i = 0; i < num_disassembly_options; i++)
3228 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
3229 valid_disassembly_styles[i] = setname;
3230 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3233 /* When we find the default names, tell the disassembler to use
3235 if (!strcmp (setname, "std"))
3237 disassembly_style = setname;
3238 set_arm_regname_option (i);
3241 /* Mark the end of valid options. */
3242 valid_disassembly_styles[num_disassembly_options] = NULL;
3244 /* Create the help text. */
3245 stb = mem_fileopen ();
3246 fprintf_unfiltered (stb, "%s%s%s",
3247 _("The valid values are:\n"),
3249 _("The default is \"std\"."));
3250 helptext = ui_file_xstrdup (stb, &length);
3251 ui_file_delete (stb);
3253 add_setshow_enum_cmd("disassembler", no_class,
3254 valid_disassembly_styles, &disassembly_style,
3255 _("Set the disassembly style."),
3256 _("Show the disassembly style."),
3258 set_disassembly_style_sfunc,
3259 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3260 &setarmcmdlist, &showarmcmdlist);
3262 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3263 _("Set usage of ARM 32-bit mode."),
3264 _("Show usage of ARM 32-bit mode."),
3265 _("When off, a 26-bit PC will be used."),
3267 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3268 &setarmcmdlist, &showarmcmdlist);
3270 /* Add a command to allow the user to force the FPU model. */
3271 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
3272 _("Set the floating point type."),
3273 _("Show the floating point type."),
3274 _("auto - Determine the FP typefrom the OS-ABI.\n\
3275 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3276 fpa - FPA co-processor (GCC compiled).\n\
3277 softvfp - Software FP with pure-endian doubles.\n\
3278 vfp - VFP co-processor."),
3279 set_fp_model_sfunc, show_fp_model,
3280 &setarmcmdlist, &showarmcmdlist);
3282 /* Add a command to allow the user to force the ABI. */
3283 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3286 NULL, arm_set_abi, arm_show_abi,
3287 &setarmcmdlist, &showarmcmdlist);
3289 /* Debugging flag. */
3290 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3291 _("Set ARM debugging."),
3292 _("Show ARM debugging."),
3293 _("When on, arm-specific debugging is enabled."),
3295 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3296 &setdebuglist, &showdebuglist);