1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "gdb_string.h"
28 #include "ia64-tdep.h"
29 #include "linux-nat.h"
32 #include <sys/ptrace.h>
37 #include <sys/syscall.h>
40 #include <asm/ptrace_offsets.h>
41 #include <sys/procfs.h>
43 /* Prototypes for supply_gregset etc. */
46 /* These must match the order of the register names.
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
51 static int u_offsets[] =
53 /* general registers */
54 -1, /* gr0 not available; i.e, it's always zero */
86 /* gr32 through gr127 not directly available via the ptrace interface */
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
221 /* predicate registers - we don't fetch these individually */
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
239 /* virtual frame pointer and virtual return address pointer */
241 /* other registers */
244 PT_CR_IPSR, /* psr */
246 /* kernel registers not visible via ptrace interface (?) */
247 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, -1, -1, -1, -1, -1, -1, -1,
255 -1, /* Not available: FCR, IA32 floating control register */
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, /* Not available: EC, the Epilog Count register */
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
285 either rnat or unat or from memory. */
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
305 ia64_register_addr (int regno)
309 if (regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
310 error (_("Invalid register number %d."), regno);
312 if (u_offsets[regno] == -1)
315 addr = (CORE_ADDR) u_offsets[regno];
321 ia64_cannot_fetch_register (int regno)
324 || regno >= gdbarch_num_regs (current_gdbarch)
325 || u_offsets[regno] == -1;
329 ia64_cannot_store_register (int regno)
331 /* Rationale behind not permitting stores to bspstore...
333 The IA-64 architecture provides bspstore and bsp which refer
334 memory locations in the RSE's backing store. bspstore is the
335 next location which will be written when the RSE needs to write
336 to memory. bsp is the address at which r32 in the current frame
337 would be found if it were written to the backing store.
339 The IA-64 architecture provides read-only access to bsp and
340 read/write access to bspstore (but only when the RSE is in
341 the enforced lazy mode). It should be noted that stores
342 to bspstore also affect the value of bsp. Changing bspstore
343 does not affect the number of dirty entries between bspstore
344 and bsp, so changing bspstore by N words will also cause bsp
345 to be changed by (roughly) N as well. (It could be N-1 or N+1
346 depending upon where the NaT collection bits fall.)
348 OTOH, the Linux kernel provides read/write access to bsp (and
349 currently read/write access to bspstore as well). But it
350 is definitely the case that if you change one, the other
351 will change at the same time. It is more useful to gdb to
352 be able to change bsp. So in order to prevent strange and
353 undesirable things from happening when a dummy stack frame
354 is popped (after calling an inferior function), we allow
355 bspstore to be read, but not written. (Note that popping
356 a (generic) dummy stack frame causes all registers that
357 were previously read from the inferior process to be written
361 || regno >= gdbarch_num_regs (current_gdbarch)
362 || u_offsets[regno] == -1
363 || regno == IA64_BSPSTORE_REGNUM;
367 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
370 const greg_t *regp = (const greg_t *) gregsetp;
372 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
374 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
377 /* FIXME: NAT collection bits are at index 32; gotta deal with these
380 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
382 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
384 regcache_raw_supply (regcache, regi,
385 regp + 34 + (regi - IA64_BR0_REGNUM));
388 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
389 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
390 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
391 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
392 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
393 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
394 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
395 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
396 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
397 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
398 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
399 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
400 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
404 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
407 greg_t *regp = (greg_t *) gregsetp;
409 #define COPY_REG(_idx_,_regi_) \
410 if ((regno == -1) || regno == _regi_) \
411 regcache_raw_collect (regcache, _regi_, regp + _idx_)
413 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
415 COPY_REG (regi - IA64_GR0_REGNUM, regi);
418 /* FIXME: NAT collection bits at index 32? */
420 COPY_REG (33, IA64_PR_REGNUM);
422 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
424 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
427 COPY_REG (42, IA64_IP_REGNUM);
428 COPY_REG (43, IA64_CFM_REGNUM);
429 COPY_REG (44, IA64_PSR_REGNUM);
430 COPY_REG (45, IA64_RSC_REGNUM);
431 COPY_REG (46, IA64_BSP_REGNUM);
432 COPY_REG (47, IA64_BSPSTORE_REGNUM);
433 COPY_REG (48, IA64_RNAT_REGNUM);
434 COPY_REG (49, IA64_CCV_REGNUM);
435 COPY_REG (50, IA64_UNAT_REGNUM);
436 COPY_REG (51, IA64_FPSR_REGNUM);
437 COPY_REG (52, IA64_PFS_REGNUM);
438 COPY_REG (53, IA64_LC_REGNUM);
439 COPY_REG (54, IA64_EC_REGNUM);
442 /* Given a pointer to a floating point register set in /proc format
443 (fpregset_t *), unpack the register contents and supply them as gdb's
444 idea of the current floating point register values. */
447 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
452 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
454 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
455 regcache_raw_supply (regcache, regi, from);
459 /* Given a pointer to a floating point register set in /proc format
460 (fpregset_t *), update the register specified by REGNO from gdb's idea
461 of the current floating point register set. If REGNO is -1, update
465 fill_fpregset (const struct regcache *regcache,
466 fpregset_t *fpregsetp, int regno)
470 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
472 if ((regno == -1) || (regno == regi))
473 regcache_raw_collect (regcache, regi,
474 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
478 #define IA64_PSR_DB (1UL << 24)
479 #define IA64_PSR_DD (1UL << 39)
482 enable_watchpoints_in_psr (struct regcache *regcache)
486 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
487 if (!(psr & IA64_PSR_DB))
489 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
490 watchpoints and breakpoints. */
491 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
496 fetch_debug_register (ptid_t ptid, int idx)
505 val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);
511 store_debug_register (ptid_t ptid, int idx, long val)
519 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
523 fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
526 *dbr_addr = fetch_debug_register (ptid, 2 * idx);
528 *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
532 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
535 store_debug_register (ptid, 2 * idx, *dbr_addr);
537 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
541 is_power_of_2 (int val)
546 for (i = 0; i < 8 * sizeof (val); i++)
550 return onecount <= 1;
554 ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
556 ptid_t ptid = inferior_ptid;
558 long dbr_addr, dbr_mask;
559 int max_watchpoints = 4;
561 if (len <= 0 || !is_power_of_2 (len))
564 for (idx = 0; idx < max_watchpoints; idx++)
566 fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
567 if ((dbr_mask & (0x3UL << 62)) == 0)
569 /* Exit loop if both r and w bits clear */
574 if (idx == max_watchpoints)
577 dbr_addr = (long) addr;
578 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
579 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
583 dbr_mask |= (1L << 62); /* Set w bit */
586 dbr_mask |= (1L << 63); /* Set r bit */
589 dbr_mask |= (3L << 62); /* Set both r and w bits */
595 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
596 enable_watchpoints_in_psr (get_current_regcache ());
602 ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type)
604 ptid_t ptid = inferior_ptid;
606 long dbr_addr, dbr_mask;
607 int max_watchpoints = 4;
609 if (len <= 0 || !is_power_of_2 (len))
612 for (idx = 0; idx < max_watchpoints; idx++)
614 fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
615 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
619 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
627 ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
631 struct siginfo siginfo;
632 ptid_t ptid = inferior_ptid;
633 struct regcache *regcache = get_current_regcache ();
640 ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
642 if (errno != 0 || siginfo.si_signo != SIGTRAP ||
643 (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
646 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
647 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
648 for the next instruction */
649 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
651 *addr_p = (CORE_ADDR)siginfo.si_addr;
656 ia64_linux_stopped_by_watchpoint (void)
659 return ia64_linux_stopped_data_address (¤t_target, &addr);
663 ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
669 /* Fetch register REGNUM from the inferior. */
672 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
676 PTRACE_TYPE_RET *buf;
679 if (ia64_cannot_fetch_register (regnum))
681 regcache_raw_supply (regcache, regnum, NULL);
685 /* Cater for systems like GNU/Linux, that implement threads as
686 separate processes. */
687 pid = ptid_get_lwp (inferior_ptid);
689 pid = ptid_get_pid (inferior_ptid);
691 /* This isn't really an address, but ptrace thinks of it as one. */
692 addr = ia64_register_addr (regnum);
693 size = register_size (current_gdbarch, regnum);
695 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
698 /* Read the register contents from the inferior a chunk at a time. */
699 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
702 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
704 error (_("Couldn't read register %s (#%d): %s."),
705 gdbarch_register_name (current_gdbarch, regnum),
706 regnum, safe_strerror (errno));
708 addr += sizeof (PTRACE_TYPE_RET);
710 regcache_raw_supply (regcache, regnum, buf);
713 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
714 for all registers. */
717 ia64_linux_fetch_registers (struct regcache *regcache, int regnum)
720 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++)
721 ia64_linux_fetch_register (regcache, regnum);
723 ia64_linux_fetch_register (regcache, regnum);
726 /* Store register REGNUM into the inferior. */
729 ia64_linux_store_register (const struct regcache *regcache, int regnum)
733 PTRACE_TYPE_RET *buf;
736 if (ia64_cannot_store_register (regnum))
739 /* Cater for systems like GNU/Linux, that implement threads as
740 separate processes. */
741 pid = ptid_get_lwp (inferior_ptid);
743 pid = ptid_get_pid (inferior_ptid);
745 /* This isn't really an address, but ptrace thinks of it as one. */
746 addr = ia64_register_addr (regnum);
747 size = register_size (current_gdbarch, regnum);
749 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
752 /* Write the register contents into the inferior a chunk at a time. */
753 regcache_raw_collect (regcache, regnum, buf);
754 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
757 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
759 error (_("Couldn't write register %s (#%d): %s."),
760 gdbarch_register_name (current_gdbarch, regnum),
761 regnum, safe_strerror (errno));
763 addr += sizeof (PTRACE_TYPE_RET);
767 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
768 this for all registers. */
771 ia64_linux_store_registers (struct regcache *regcache, int regnum)
774 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++)
775 ia64_linux_store_register (regcache, regnum);
777 ia64_linux_store_register (regcache, regnum);
781 static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
782 const char *, gdb_byte *, const gdb_byte *,
786 ia64_linux_xfer_partial (struct target_ops *ops,
787 enum target_object object,
789 gdb_byte *readbuf, const gdb_byte *writebuf,
790 ULONGEST offset, LONGEST len)
792 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
793 return syscall (__NR_getunwind, readbuf, len);
795 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
799 void _initialize_ia64_linux_nat (void);
802 _initialize_ia64_linux_nat (void)
804 struct target_ops *t = linux_target ();
806 /* Fill in the generic GNU/Linux methods. */
809 /* Override the default fetch/store register routines. */
810 t->to_fetch_registers = ia64_linux_fetch_registers;
811 t->to_store_registers = ia64_linux_store_registers;
813 /* Override the default to_xfer_partial. */
814 super_xfer_partial = t->to_xfer_partial;
815 t->to_xfer_partial = ia64_linux_xfer_partial;
817 /* Override watchpoint routines. */
819 /* The IA-64 architecture can step over a watch point (without triggering
820 it again) if the "dd" (data debug fault disable) bit in the processor
823 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
824 code there has determined that a hardware watchpoint has indeed
825 been hit. The CPU will then be able to execute one instruction
826 without triggering a watchpoint. */
828 t->to_have_steppable_watchpoint = 1;
829 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
830 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
831 t->to_stopped_data_address = ia64_linux_stopped_data_address;
832 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
833 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
835 /* Register the target. */
836 linux_nat_add_target (t);