1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
61 static const struct objfile_data *mips_pdr_data;
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE = 4,
74 MIPS_FPU_DOUBLE_REGSIZE = 8
78 static const char *mips_abi_string;
80 static const char *mips_abi_strings[] = {
91 /* Various MIPS ISA options (related to stack analysis) can be
92 overridden dynamically. Establish an enum/array for managing
95 static const char size_auto[] = "auto";
96 static const char size_32[] = "32";
97 static const char size_64[] = "64";
99 static const char *size_enums[] = {
106 /* Some MIPS boards don't support floating point while others only
107 support single-precision floating-point operations. */
111 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
112 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
113 MIPS_FPU_NONE /* No floating point. */
116 #ifndef MIPS_DEFAULT_FPU_TYPE
117 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
119 static int mips_fpu_type_auto = 1;
120 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
122 static int mips_debug = 0;
124 /* Properties (for struct target_desc) describing the g/G packet
126 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
127 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi;
137 enum mips_abi found_abi;
138 enum mips_fpu_type mips_fpu_type;
139 int mips_last_arg_regnum;
140 int mips_last_fp_arg_regnum;
141 int default_mask_address_p;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum *regnum;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names;
152 /* The size of register data available from the target, if known.
153 This doesn't quite obsolete the manual
154 mips64_transfers_32bit_regs_p, since that is documented to force
155 left alignment even for big endian (very strange). */
156 int register_size_valid_p;
161 n32n64_floatformat_always_valid (const struct floatformat *fmt,
167 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
168 They are implemented as a pair of 64bit doubles where the high
169 part holds the result of the operation rounded to double, and
170 the low double holds the difference between the exact result and
171 the rounded result. So "high" + "low" contains the result with
172 added precision. Unfortunately, the floatformat structure used
173 by GDB is not powerful enough to describe this format. As a temporary
174 measure, we define a 128bit floatformat that only uses the high part.
175 We lose a bit of precision but that's probably the best we can do
176 for now with the current infrastructure. */
178 static const struct floatformat floatformat_n32n64_long_double_big =
180 floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52,
181 floatformat_intbit_no,
182 "floatformat_n32n64_long_double_big",
183 n32n64_floatformat_always_valid
186 static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] =
188 &floatformat_n32n64_long_double_big,
189 &floatformat_n32n64_long_double_big
192 const struct mips_regnum *
193 mips_regnum (struct gdbarch *gdbarch)
195 return gdbarch_tdep (gdbarch)->regnum;
199 mips_fpa0_regnum (struct gdbarch *gdbarch)
201 return mips_regnum (gdbarch)->fp0 + 12;
204 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
205 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
207 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
209 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
211 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
213 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
214 functions to test, set, or clear bit 0 of addresses. */
217 is_mips16_addr (CORE_ADDR addr)
223 unmake_mips16_addr (CORE_ADDR addr)
225 return ((addr) & ~(CORE_ADDR) 1);
228 /* Return the contents of register REGNUM as a signed integer. */
231 read_signed_register (int regnum)
234 regcache_cooked_read_signed (current_regcache, regnum, &val);
239 read_signed_register_pid (int regnum, ptid_t ptid)
244 if (ptid_equal (ptid, inferior_ptid))
245 return read_signed_register (regnum);
247 save_ptid = inferior_ptid;
249 inferior_ptid = ptid;
251 retval = read_signed_register (regnum);
253 inferior_ptid = save_ptid;
258 /* Return the MIPS ABI associated with GDBARCH. */
260 mips_abi (struct gdbarch *gdbarch)
262 return gdbarch_tdep (gdbarch)->mips_abi;
266 mips_isa_regsize (struct gdbarch *gdbarch)
268 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270 /* If we know how big the registers are, use that size. */
271 if (tdep->register_size_valid_p)
272 return tdep->register_size;
274 /* Fall back to the previous behavior. */
275 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
276 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
279 /* Return the currently configured (or set) saved register size. */
281 static const char *mips_abi_regsize_string = size_auto;
284 mips_abi_regsize (struct gdbarch *gdbarch)
286 if (mips_abi_regsize_string == size_auto)
287 switch (mips_abi (gdbarch))
289 case MIPS_ABI_EABI32:
295 case MIPS_ABI_EABI64:
297 case MIPS_ABI_UNKNOWN:
300 internal_error (__FILE__, __LINE__, _("bad switch"));
302 else if (mips_abi_regsize_string == size_64)
304 else /* if (mips_abi_regsize_string == size_32) */
308 /* Functions for setting and testing a bit in a minimal symbol that
309 marks it as 16-bit function. The MSB of the minimal symbol's
310 "info" field is used for this purpose.
312 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
313 i.e. refers to a 16-bit function, and sets a "special" bit in a
314 minimal symbol to mark it as a 16-bit function
316 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
319 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
321 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
323 MSYMBOL_INFO (msym) = (char *)
324 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
325 SYMBOL_VALUE_ADDRESS (msym) |= 1;
330 msymbol_is_special (struct minimal_symbol *msym)
332 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
335 /* XFER a value from the big/little/left end of the register.
336 Depending on the size of the value it might occupy the entire
337 register or just part of it. Make an allowance for this, aligning
338 things accordingly. */
341 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
342 enum bfd_endian endian, gdb_byte *in,
343 const gdb_byte *out, int buf_offset)
346 gdb_assert (reg_num >= NUM_REGS);
347 /* Need to transfer the left or right part of the register, based on
348 the targets byte order. */
352 reg_offset = register_size (current_gdbarch, reg_num) - length;
354 case BFD_ENDIAN_LITTLE:
357 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
361 internal_error (__FILE__, __LINE__, _("bad switch"));
364 fprintf_unfiltered (gdb_stderr,
365 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
366 reg_num, reg_offset, buf_offset, length);
367 if (mips_debug && out != NULL)
370 fprintf_unfiltered (gdb_stdlog, "out ");
371 for (i = 0; i < length; i++)
372 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
375 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
378 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
380 if (mips_debug && in != NULL)
383 fprintf_unfiltered (gdb_stdlog, "in ");
384 for (i = 0; i < length; i++)
385 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
388 fprintf_unfiltered (gdb_stdlog, "\n");
391 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
392 compatiblity mode. A return value of 1 means that we have
393 physical 64-bit registers, but should treat them as 32-bit registers. */
396 mips2_fp_compat (void)
398 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
400 if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
405 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
406 in all the places we deal with FP registers. PR gdb/413. */
407 /* Otherwise check the FR bit in the status register - it controls
408 the FP compatiblity mode. If it is clear we are in compatibility
410 if ((read_register (MIPS_PS_REGNUM) & ST0_FR) == 0)
417 /* The amount of space reserved on the stack for registers. This is
418 different to MIPS_ABI_REGSIZE as it determines the alignment of
419 data allocated after the registers have run out. */
421 static const char *mips_stack_argsize_string = size_auto;
424 mips_stack_argsize (struct gdbarch *gdbarch)
426 if (mips_stack_argsize_string == size_auto)
427 return mips_abi_regsize (gdbarch);
428 else if (mips_stack_argsize_string == size_64)
430 else /* if (mips_stack_argsize_string == size_32) */
434 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
436 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
438 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
440 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
442 static struct type *mips_float_register_type (void);
443 static struct type *mips_double_register_type (void);
445 /* The list of available "set mips " and "show mips " commands */
447 static struct cmd_list_element *setmipscmdlist = NULL;
448 static struct cmd_list_element *showmipscmdlist = NULL;
450 /* Integer registers 0 thru 31 are handled explicitly by
451 mips_register_name(). Processor specific registers 32 and above
452 are listed in the following tables. */
455 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
459 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
460 "sr", "lo", "hi", "bad", "cause", "pc",
461 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
462 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
463 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
464 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
465 "fsr", "fir", "" /*"fp" */ , "",
466 "", "", "", "", "", "", "", "",
467 "", "", "", "", "", "", "", "",
470 /* Names of IDT R3041 registers. */
472 static const char *mips_r3041_reg_names[] = {
473 "sr", "lo", "hi", "bad", "cause", "pc",
474 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
475 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
476 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
477 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
478 "fsr", "fir", "", /*"fp" */ "",
479 "", "", "bus", "ccfg", "", "", "", "",
480 "", "", "port", "cmp", "", "", "epc", "prid",
483 /* Names of tx39 registers. */
485 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
486 "sr", "lo", "hi", "bad", "cause", "pc",
487 "", "", "", "", "", "", "", "",
488 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
490 "", "", "", "", "", "", "", "",
492 "", "", "", "", "", "", "", "",
493 "", "", "config", "cache", "debug", "depc", "epc", ""
496 /* Names of IRIX registers. */
497 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
498 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
502 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
506 /* Return the name of the register corresponding to REGNO. */
508 mips_register_name (int regno)
510 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
511 /* GPR names for all ABIs other than n32/n64. */
512 static char *mips_gpr_names[] = {
513 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
514 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
515 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
516 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
519 /* GPR names for n32 and n64 ABIs. */
520 static char *mips_n32_n64_gpr_names[] = {
521 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
522 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
523 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
524 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
527 enum mips_abi abi = mips_abi (current_gdbarch);
529 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
530 don't make the raw register names visible. */
531 int rawnum = regno % NUM_REGS;
532 if (regno < NUM_REGS)
535 /* The MIPS integer registers are always mapped from 0 to 31. The
536 names of the registers (which reflects the conventions regarding
537 register use) vary depending on the ABI. */
538 if (0 <= rawnum && rawnum < 32)
540 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
541 return mips_n32_n64_gpr_names[rawnum];
543 return mips_gpr_names[rawnum];
545 else if (32 <= rawnum && rawnum < NUM_REGS)
547 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
548 return tdep->mips_processor_reg_names[rawnum - 32];
551 internal_error (__FILE__, __LINE__,
552 _("mips_register_name: bad register number %d"), rawnum);
555 /* Return the groups that a MIPS register can be categorised into. */
558 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
559 struct reggroup *reggroup)
564 int rawnum = regnum % NUM_REGS;
565 int pseudo = regnum / NUM_REGS;
566 if (reggroup == all_reggroup)
568 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
569 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
570 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
571 (gdbarch), as not all architectures are multi-arch. */
572 raw_p = rawnum < NUM_REGS;
573 if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
575 if (reggroup == float_reggroup)
576 return float_p && pseudo;
577 if (reggroup == vector_reggroup)
578 return vector_p && pseudo;
579 if (reggroup == general_reggroup)
580 return (!vector_p && !float_p) && pseudo;
581 /* Save the pseudo registers. Need to make certain that any code
582 extracting register values from a saved register cache also uses
584 if (reggroup == save_reggroup)
585 return raw_p && pseudo;
586 /* Restore the same pseudo register. */
587 if (reggroup == restore_reggroup)
588 return raw_p && pseudo;
592 /* Map the symbol table registers which live in the range [1 *
593 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
594 registers. Take care of alignment and size problems. */
597 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
598 int cookednum, gdb_byte *buf)
600 int rawnum = cookednum % NUM_REGS;
601 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
602 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
603 regcache_raw_read (regcache, rawnum, buf);
604 else if (register_size (gdbarch, rawnum) >
605 register_size (gdbarch, cookednum))
607 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
608 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
609 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
611 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
614 internal_error (__FILE__, __LINE__, _("bad register size"));
618 mips_pseudo_register_write (struct gdbarch *gdbarch,
619 struct regcache *regcache, int cookednum,
622 int rawnum = cookednum % NUM_REGS;
623 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
624 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
625 regcache_raw_write (regcache, rawnum, buf);
626 else if (register_size (gdbarch, rawnum) >
627 register_size (gdbarch, cookednum))
629 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
630 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
631 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
633 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
636 internal_error (__FILE__, __LINE__, _("bad register size"));
639 /* Table to translate MIPS16 register field to actual register number. */
640 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
642 /* Heuristic_proc_start may hunt through the text section for a long
643 time across a 2400 baud serial line. Allows the user to limit this
646 static unsigned int heuristic_fence_post = 0;
648 /* Number of bytes of storage in the actual machine representation for
649 register N. NOTE: This defines the pseudo register type so need to
650 rebuild the architecture vector. */
652 static int mips64_transfers_32bit_regs_p = 0;
655 set_mips64_transfers_32bit_regs (char *args, int from_tty,
656 struct cmd_list_element *c)
658 struct gdbarch_info info;
659 gdbarch_info_init (&info);
660 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
661 instead of relying on globals. Doing that would let generic code
662 handle the search for this specific architecture. */
663 if (!gdbarch_update_p (info))
665 mips64_transfers_32bit_regs_p = 0;
666 error (_("32-bit compatibility mode not supported"));
670 /* Convert to/from a register and the corresponding memory value. */
673 mips_convert_register_p (int regnum, struct type *type)
675 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
676 && register_size (current_gdbarch, regnum) == 4
677 && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
678 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
679 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
683 mips_register_to_value (struct frame_info *frame, int regnum,
684 struct type *type, gdb_byte *to)
686 get_frame_register (frame, regnum + 0, to + 4);
687 get_frame_register (frame, regnum + 1, to + 0);
691 mips_value_to_register (struct frame_info *frame, int regnum,
692 struct type *type, const gdb_byte *from)
694 put_frame_register (frame, regnum + 0, from + 4);
695 put_frame_register (frame, regnum + 1, from + 0);
698 /* Return the GDB type object for the "standard" data type of data in
702 mips_register_type (struct gdbarch *gdbarch, int regnum)
704 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
705 if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
706 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32)
708 /* The floating-point registers raw, or cooked, always match
709 mips_isa_regsize(), and also map 1:1, byte for byte. */
710 if (mips_isa_regsize (gdbarch) == 4)
711 return builtin_type_ieee_single;
713 return builtin_type_ieee_double;
715 else if (regnum < NUM_REGS)
717 /* The raw or ISA registers. These are all sized according to
719 if (mips_isa_regsize (gdbarch) == 4)
720 return builtin_type_int32;
722 return builtin_type_int64;
726 /* The cooked or ABI registers. These are sized according to
727 the ABI (with a few complications). */
728 if (regnum >= (NUM_REGS
729 + mips_regnum (current_gdbarch)->fp_control_status)
730 && regnum <= NUM_REGS + MIPS_LAST_EMBED_REGNUM)
731 /* The pseudo/cooked view of the embedded registers is always
732 32-bit. The raw view is handled below. */
733 return builtin_type_int32;
734 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
735 /* The target, while possibly using a 64-bit register buffer,
736 is only transfering 32-bits of each integer register.
737 Reflect this in the cooked/pseudo (ABI) register value. */
738 return builtin_type_int32;
739 else if (mips_abi_regsize (gdbarch) == 4)
740 /* The ABI is restricted to 32-bit registers (the ISA could be
742 return builtin_type_int32;
745 return builtin_type_int64;
749 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
754 return read_signed_register (MIPS_SP_REGNUM);
757 /* Should the upper word of 64-bit addresses be zeroed? */
758 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
761 mips_mask_address_p (struct gdbarch_tdep *tdep)
763 switch (mask_address_var)
765 case AUTO_BOOLEAN_TRUE:
767 case AUTO_BOOLEAN_FALSE:
770 case AUTO_BOOLEAN_AUTO:
771 return tdep->default_mask_address_p;
773 internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch"));
779 show_mask_address (struct ui_file *file, int from_tty,
780 struct cmd_list_element *c, const char *value)
782 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
784 deprecated_show_value_hack (file, from_tty, c, value);
785 switch (mask_address_var)
787 case AUTO_BOOLEAN_TRUE:
788 printf_filtered ("The 32 bit mips address mask is enabled\n");
790 case AUTO_BOOLEAN_FALSE:
791 printf_filtered ("The 32 bit mips address mask is disabled\n");
793 case AUTO_BOOLEAN_AUTO:
795 ("The 32 bit address mask is set automatically. Currently %s\n",
796 mips_mask_address_p (tdep) ? "enabled" : "disabled");
799 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
804 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
807 mips_pc_is_mips16 (CORE_ADDR memaddr)
809 struct minimal_symbol *sym;
811 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
812 if (is_mips16_addr (memaddr))
815 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
816 the high bit of the info field. Use this to decide if the function is
817 MIPS16 or normal MIPS. */
818 sym = lookup_minimal_symbol_by_pc (memaddr);
820 return msymbol_is_special (sym);
825 /* MIPS believes that the PC has a sign extended value. Perhaps the
826 all registers should be sign extended for simplicity? */
829 mips_read_pc (ptid_t ptid)
831 return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
835 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
837 return frame_unwind_register_signed (next_frame,
838 NUM_REGS + mips_regnum (gdbarch)->pc);
841 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
842 dummy frame. The frame ID's base needs to match the TOS value
843 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
846 static struct frame_id
847 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
849 return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM),
850 frame_pc_unwind (next_frame));
854 mips_write_pc (CORE_ADDR pc, ptid_t ptid)
856 write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
859 /* Fetch and return instruction from the specified location. If the PC
860 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
863 mips_fetch_instruction (CORE_ADDR addr)
865 gdb_byte buf[MIPS_INSN32_SIZE];
869 if (mips_pc_is_mips16 (addr))
871 instlen = MIPS_INSN16_SIZE;
872 addr = unmake_mips16_addr (addr);
875 instlen = MIPS_INSN32_SIZE;
876 status = read_memory_nobpt (addr, buf, instlen);
878 memory_error (status, addr);
879 return extract_unsigned_integer (buf, instlen);
882 /* These the fields of 32 bit mips instructions */
883 #define mips32_op(x) (x >> 26)
884 #define itype_op(x) (x >> 26)
885 #define itype_rs(x) ((x >> 21) & 0x1f)
886 #define itype_rt(x) ((x >> 16) & 0x1f)
887 #define itype_immediate(x) (x & 0xffff)
889 #define jtype_op(x) (x >> 26)
890 #define jtype_target(x) (x & 0x03ffffff)
892 #define rtype_op(x) (x >> 26)
893 #define rtype_rs(x) ((x >> 21) & 0x1f)
894 #define rtype_rt(x) ((x >> 16) & 0x1f)
895 #define rtype_rd(x) ((x >> 11) & 0x1f)
896 #define rtype_shamt(x) ((x >> 6) & 0x1f)
897 #define rtype_funct(x) (x & 0x3f)
900 mips32_relative_offset (ULONGEST inst)
902 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2;
905 /* Determine where to set a single step breakpoint while considering
906 branch prediction. */
908 mips32_next_pc (CORE_ADDR pc)
912 inst = mips_fetch_instruction (pc);
913 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
915 if (itype_op (inst) >> 2 == 5)
916 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
918 op = (itype_op (inst) & 0x03);
933 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
934 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
936 int tf = itype_rt (inst) & 0x01;
937 int cnum = itype_rt (inst) >> 2;
939 read_signed_register (mips_regnum (current_gdbarch)->
941 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
943 if (((cond >> cnum) & 0x01) == tf)
944 pc += mips32_relative_offset (inst) + 4;
949 pc += 4; /* Not a branch, next instruction is easy */
952 { /* This gets way messy */
954 /* Further subdivide into SPECIAL, REGIMM and other */
955 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
957 case 0: /* SPECIAL */
958 op = rtype_funct (inst);
963 /* Set PC to that address */
964 pc = read_signed_register (rtype_rs (inst));
970 break; /* end SPECIAL */
973 op = itype_rt (inst); /* branch condition */
978 case 16: /* BLTZAL */
979 case 18: /* BLTZALL */
981 if (read_signed_register (itype_rs (inst)) < 0)
982 pc += mips32_relative_offset (inst) + 4;
984 pc += 8; /* after the delay slot */
988 case 17: /* BGEZAL */
989 case 19: /* BGEZALL */
990 if (read_signed_register (itype_rs (inst)) >= 0)
991 pc += mips32_relative_offset (inst) + 4;
993 pc += 8; /* after the delay slot */
995 /* All of the other instructions in the REGIMM category */
1000 break; /* end REGIMM */
1005 reg = jtype_target (inst) << 2;
1006 /* Upper four bits get never changed... */
1007 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
1010 /* FIXME case JALX : */
1013 reg = jtype_target (inst) << 2;
1014 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */
1015 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1017 break; /* The new PC will be alternate mode */
1018 case 4: /* BEQ, BEQL */
1020 if (read_signed_register (itype_rs (inst)) ==
1021 read_signed_register (itype_rt (inst)))
1022 pc += mips32_relative_offset (inst) + 4;
1026 case 5: /* BNE, BNEL */
1028 if (read_signed_register (itype_rs (inst)) !=
1029 read_signed_register (itype_rt (inst)))
1030 pc += mips32_relative_offset (inst) + 4;
1034 case 6: /* BLEZ, BLEZL */
1035 if (read_signed_register (itype_rs (inst)) <= 0)
1036 pc += mips32_relative_offset (inst) + 4;
1042 greater_branch: /* BGTZ, BGTZL */
1043 if (read_signed_register (itype_rs (inst)) > 0)
1044 pc += mips32_relative_offset (inst) + 4;
1051 } /* mips32_next_pc */
1053 /* Decoding the next place to set a breakpoint is irregular for the
1054 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1055 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1056 We dont want to set a single step instruction on the extend instruction
1060 /* Lots of mips16 instruction formats */
1061 /* Predicting jumps requires itype,ritype,i8type
1062 and their extensions extItype,extritype,extI8type
1064 enum mips16_inst_fmts
1066 itype, /* 0 immediate 5,10 */
1067 ritype, /* 1 5,3,8 */
1068 rrtype, /* 2 5,3,3,5 */
1069 rritype, /* 3 5,3,3,5 */
1070 rrrtype, /* 4 5,3,3,3,2 */
1071 rriatype, /* 5 5,3,3,1,4 */
1072 shifttype, /* 6 5,3,3,3,2 */
1073 i8type, /* 7 5,3,8 */
1074 i8movtype, /* 8 5,3,3,5 */
1075 i8mov32rtype, /* 9 5,3,5,3 */
1076 i64type, /* 10 5,3,8 */
1077 ri64type, /* 11 5,3,3,5 */
1078 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1079 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1080 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1081 extRRItype, /* 15 5,5,5,5,3,3,5 */
1082 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1083 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1084 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1085 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1086 extRi64type, /* 20 5,6,5,5,3,3,5 */
1087 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1089 /* I am heaping all the fields of the formats into one structure and
1090 then, only the fields which are involved in instruction extension */
1094 unsigned int regx; /* Function in i8 type */
1099 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1100 for the bits which make up the immediatate extension. */
1103 extended_offset (unsigned int extension)
1106 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1108 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1110 value |= extension & 0x01f; /* extract 4:0 */
1114 /* Only call this function if you know that this is an extendable
1115 instruction, It wont malfunction, but why make excess remote memory references?
1116 If the immediate operands get sign extended or somthing, do it after
1117 the extension is performed.
1119 /* FIXME: Every one of these cases needs to worry about sign extension
1120 when the offset is to be used in relative addressing */
1124 fetch_mips_16 (CORE_ADDR pc)
1127 pc &= 0xfffffffe; /* clear the low order bit */
1128 target_read_memory (pc, buf, 2);
1129 return extract_unsigned_integer (buf, 2);
1133 unpack_mips16 (CORE_ADDR pc,
1134 unsigned int extension,
1136 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1141 switch (insn_format)
1148 value = extended_offset (extension);
1149 value = value << 11; /* rom for the original value */
1150 value |= inst & 0x7ff; /* eleven bits from instruction */
1154 value = inst & 0x7ff;
1155 /* FIXME : Consider sign extension */
1164 { /* A register identifier and an offset */
1165 /* Most of the fields are the same as I type but the
1166 immediate value is of a different length */
1170 value = extended_offset (extension);
1171 value = value << 8; /* from the original instruction */
1172 value |= inst & 0xff; /* eleven bits from instruction */
1173 regx = (extension >> 8) & 0x07; /* or i8 funct */
1174 if (value & 0x4000) /* test the sign bit , bit 26 */
1176 value &= ~0x3fff; /* remove the sign bit */
1182 value = inst & 0xff; /* 8 bits */
1183 regx = (inst >> 8) & 0x07; /* or i8 funct */
1184 /* FIXME: Do sign extension , this format needs it */
1185 if (value & 0x80) /* THIS CONFUSES ME */
1187 value &= 0xef; /* remove the sign bit */
1197 unsigned long value;
1198 unsigned int nexthalf;
1199 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1200 value = value << 16;
1201 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1209 internal_error (__FILE__, __LINE__, _("bad switch"));
1211 upk->offset = offset;
1218 add_offset_16 (CORE_ADDR pc, int offset)
1220 return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
1224 extended_mips16_next_pc (CORE_ADDR pc,
1225 unsigned int extension, unsigned int insn)
1227 int op = (insn >> 11);
1230 case 2: /* Branch */
1233 struct upk_mips16 upk;
1234 unpack_mips16 (pc, extension, insn, itype, &upk);
1235 offset = upk.offset;
1241 pc += (offset << 1) + 2;
1244 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1246 struct upk_mips16 upk;
1247 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1248 pc = add_offset_16 (pc, upk.offset);
1249 if ((insn >> 10) & 0x01) /* Exchange mode */
1250 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1257 struct upk_mips16 upk;
1259 unpack_mips16 (pc, extension, insn, ritype, &upk);
1260 reg = read_signed_register (upk.regx);
1262 pc += (upk.offset << 1) + 2;
1269 struct upk_mips16 upk;
1271 unpack_mips16 (pc, extension, insn, ritype, &upk);
1272 reg = read_signed_register (upk.regx);
1274 pc += (upk.offset << 1) + 2;
1279 case 12: /* I8 Formats btez btnez */
1281 struct upk_mips16 upk;
1283 unpack_mips16 (pc, extension, insn, i8type, &upk);
1284 /* upk.regx contains the opcode */
1285 reg = read_signed_register (24); /* Test register is 24 */
1286 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1287 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1288 /* pc = add_offset_16(pc,upk.offset) ; */
1289 pc += (upk.offset << 1) + 2;
1294 case 29: /* RR Formats JR, JALR, JALR-RA */
1296 struct upk_mips16 upk;
1297 /* upk.fmt = rrtype; */
1302 upk.regx = (insn >> 8) & 0x07;
1303 upk.regy = (insn >> 5) & 0x07;
1311 break; /* Function return instruction */
1317 break; /* BOGUS Guess */
1319 pc = read_signed_register (reg);
1326 /* This is an instruction extension. Fetch the real instruction
1327 (which follows the extension) and decode things based on
1331 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1344 mips16_next_pc (CORE_ADDR pc)
1346 unsigned int insn = fetch_mips_16 (pc);
1347 return extended_mips16_next_pc (pc, 0, insn);
1350 /* The mips_next_pc function supports single_step when the remote
1351 target monitor or stub is not developed enough to do a single_step.
1352 It works by decoding the current instruction and predicting where a
1353 branch will go. This isnt hard because all the data is available.
1354 The MIPS32 and MIPS16 variants are quite different */
1356 mips_next_pc (CORE_ADDR pc)
1359 return mips16_next_pc (pc);
1361 return mips32_next_pc (pc);
1364 struct mips_frame_cache
1367 struct trad_frame_saved_reg *saved_regs;
1370 /* Set a register's saved stack address in temp_saved_regs. If an
1371 address has already been set for this register, do nothing; this
1372 way we will only recognize the first save of a given register in a
1375 For simplicity, save the address in both [0 .. NUM_REGS) and
1376 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1377 is used as it is only second range (the ABI instead of ISA
1378 registers) that comes into play when finding saved registers in a
1382 set_reg_offset (struct mips_frame_cache *this_cache, int regnum,
1385 if (this_cache != NULL
1386 && this_cache->saved_regs[regnum].addr == -1)
1388 this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset;
1389 this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset;
1394 /* Fetch the immediate value from a MIPS16 instruction.
1395 If the previous instruction was an EXTEND, use it to extend
1396 the upper bits of the immediate value. This is a helper function
1397 for mips16_scan_prologue. */
1400 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1401 unsigned short inst, /* current instruction */
1402 int nbits, /* number of bits in imm field */
1403 int scale, /* scale factor to be applied to imm */
1404 int is_signed) /* is the imm field signed? */
1408 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1410 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1411 if (offset & 0x8000) /* check for negative extend */
1412 offset = 0 - (0x10000 - (offset & 0xffff));
1413 return offset | (inst & 0x1f);
1417 int max_imm = 1 << nbits;
1418 int mask = max_imm - 1;
1419 int sign_bit = max_imm >> 1;
1421 offset = inst & mask;
1422 if (is_signed && (offset & sign_bit))
1423 offset = 0 - (max_imm - offset);
1424 return offset * scale;
1429 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1430 the associated FRAME_CACHE if not null.
1431 Return the address of the first instruction past the prologue. */
1434 mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1435 struct frame_info *next_frame,
1436 struct mips_frame_cache *this_cache)
1439 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1441 long frame_offset = 0; /* Size of stack frame. */
1442 long frame_adjust = 0; /* Offset of FP from SP. */
1443 int frame_reg = MIPS_SP_REGNUM;
1444 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1445 unsigned inst = 0; /* current instruction */
1446 unsigned entry_inst = 0; /* the entry instruction */
1449 int extend_bytes = 0;
1450 int prev_extend_bytes;
1451 CORE_ADDR end_prologue_addr = 0;
1453 /* Can be called when there's no process, and hence when there's no
1455 if (next_frame != NULL)
1456 sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM);
1460 if (limit_pc > start_pc + 200)
1461 limit_pc = start_pc + 200;
1463 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE)
1465 /* Save the previous instruction. If it's an EXTEND, we'll extract
1466 the immediate offset extension from it in mips16_get_imm. */
1469 /* Fetch and decode the instruction. */
1470 inst = (unsigned short) mips_fetch_instruction (cur_pc);
1472 /* Normally we ignore extend instructions. However, if it is
1473 not followed by a valid prologue instruction, then this
1474 instruction is not part of the prologue either. We must
1475 remember in this case to adjust the end_prologue_addr back
1477 if ((inst & 0xf800) == 0xf000) /* extend */
1479 extend_bytes = MIPS_INSN16_SIZE;
1483 prev_extend_bytes = extend_bytes;
1486 if ((inst & 0xff00) == 0x6300 /* addiu sp */
1487 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1489 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
1490 if (offset < 0) /* negative stack adjustment? */
1491 frame_offset -= offset;
1493 /* Exit loop if a positive stack adjustment is found, which
1494 usually means that the stack cleanup code in the function
1495 epilogue is reached. */
1498 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1500 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1501 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
1502 set_reg_offset (this_cache, reg, sp + offset);
1504 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1506 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1507 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1508 set_reg_offset (this_cache, reg, sp + offset);
1510 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1512 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1513 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1515 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1517 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
1518 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1520 else if (inst == 0x673d) /* move $s1, $sp */
1525 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1527 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1528 frame_addr = sp + offset;
1530 frame_adjust = offset;
1532 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1534 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1535 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1536 set_reg_offset (this_cache, reg, frame_addr + offset);
1538 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1540 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1541 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
1542 set_reg_offset (this_cache, reg, frame_addr + offset);
1544 else if ((inst & 0xf81f) == 0xe809
1545 && (inst & 0x700) != 0x700) /* entry */
1546 entry_inst = inst; /* save for later processing */
1547 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
1548 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */
1549 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1551 /* This instruction is part of the prologue, but we don't
1552 need to do anything special to handle it. */
1556 /* This instruction is not an instruction typically found
1557 in a prologue, so we must have reached the end of the
1559 if (end_prologue_addr == 0)
1560 end_prologue_addr = cur_pc - prev_extend_bytes;
1564 /* The entry instruction is typically the first instruction in a function,
1565 and it stores registers at offsets relative to the value of the old SP
1566 (before the prologue). But the value of the sp parameter to this
1567 function is the new SP (after the prologue has been executed). So we
1568 can't calculate those offsets until we've seen the entire prologue,
1569 and can calculate what the old SP must have been. */
1570 if (entry_inst != 0)
1572 int areg_count = (entry_inst >> 8) & 7;
1573 int sreg_count = (entry_inst >> 6) & 3;
1575 /* The entry instruction always subtracts 32 from the SP. */
1578 /* Now we can calculate what the SP must have been at the
1579 start of the function prologue. */
1582 /* Check if a0-a3 were saved in the caller's argument save area. */
1583 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1585 set_reg_offset (this_cache, reg, sp + offset);
1586 offset += mips_abi_regsize (current_gdbarch);
1589 /* Check if the ra register was pushed on the stack. */
1591 if (entry_inst & 0x20)
1593 set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset);
1594 offset -= mips_abi_regsize (current_gdbarch);
1597 /* Check if the s0 and s1 registers were pushed on the stack. */
1598 for (reg = 16; reg < sreg_count + 16; reg++)
1600 set_reg_offset (this_cache, reg, sp + offset);
1601 offset -= mips_abi_regsize (current_gdbarch);
1605 if (this_cache != NULL)
1608 (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
1609 + frame_offset - frame_adjust);
1610 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1611 be able to get rid of the assignment below, evetually. But it's
1612 still needed for now. */
1613 this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1614 = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM];
1617 /* If we didn't reach the end of the prologue when scanning the function
1618 instructions, then set end_prologue_addr to the address of the
1619 instruction immediately after the last one we scanned. */
1620 if (end_prologue_addr == 0)
1621 end_prologue_addr = cur_pc;
1623 return end_prologue_addr;
1626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1627 Procedures that use the 32-bit instruction set are handled by the
1628 mips_insn32 unwinder. */
1630 static struct mips_frame_cache *
1631 mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache)
1633 struct mips_frame_cache *cache;
1635 if ((*this_cache) != NULL)
1636 return (*this_cache);
1637 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1638 (*this_cache) = cache;
1639 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1641 /* Analyze the function prologue. */
1643 const CORE_ADDR pc =
1644 frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1645 CORE_ADDR start_addr;
1647 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1648 if (start_addr == 0)
1649 start_addr = heuristic_proc_start (pc);
1650 /* We can't analyze the prologue if we couldn't find the begining
1652 if (start_addr == 0)
1655 mips16_scan_prologue (start_addr, pc, next_frame, *this_cache);
1658 /* SP_REGNUM, contains the value and not the address. */
1659 trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
1661 return (*this_cache);
1665 mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache,
1666 struct frame_id *this_id)
1668 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1670 (*this_id) = frame_id_build (info->base,
1671 frame_func_unwind (next_frame, NORMAL_FRAME));
1675 mips_insn16_frame_prev_register (struct frame_info *next_frame,
1677 int regnum, int *optimizedp,
1678 enum lval_type *lvalp, CORE_ADDR *addrp,
1679 int *realnump, gdb_byte *valuep)
1681 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1683 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
1684 optimizedp, lvalp, addrp, realnump, valuep);
1687 static const struct frame_unwind mips_insn16_frame_unwind =
1690 mips_insn16_frame_this_id,
1691 mips_insn16_frame_prev_register
1694 static const struct frame_unwind *
1695 mips_insn16_frame_sniffer (struct frame_info *next_frame)
1697 CORE_ADDR pc = frame_pc_unwind (next_frame);
1698 if (mips_pc_is_mips16 (pc))
1699 return &mips_insn16_frame_unwind;
1704 mips_insn16_frame_base_address (struct frame_info *next_frame,
1707 struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame,
1712 static const struct frame_base mips_insn16_frame_base =
1714 &mips_insn16_frame_unwind,
1715 mips_insn16_frame_base_address,
1716 mips_insn16_frame_base_address,
1717 mips_insn16_frame_base_address
1720 static const struct frame_base *
1721 mips_insn16_frame_base_sniffer (struct frame_info *next_frame)
1723 if (mips_insn16_frame_sniffer (next_frame) != NULL)
1724 return &mips_insn16_frame_base;
1729 /* Mark all the registers as unset in the saved_regs array
1730 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1733 reset_saved_regs (struct mips_frame_cache *this_cache)
1735 if (this_cache == NULL || this_cache->saved_regs == NULL)
1739 const int num_regs = NUM_REGS;
1742 for (i = 0; i < num_regs; i++)
1744 this_cache->saved_regs[i].addr = -1;
1749 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1750 the associated FRAME_CACHE if not null.
1751 Return the address of the first instruction past the prologue. */
1754 mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1755 struct frame_info *next_frame,
1756 struct mips_frame_cache *this_cache)
1759 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
1762 int frame_reg = MIPS_SP_REGNUM;
1764 CORE_ADDR end_prologue_addr = 0;
1765 int seen_sp_adjust = 0;
1766 int load_immediate_bytes = 0;
1768 /* Can be called when there's no process, and hence when there's no
1770 if (next_frame != NULL)
1771 sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM);
1775 if (limit_pc > start_pc + 200)
1776 limit_pc = start_pc + 200;
1781 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE)
1783 unsigned long inst, high_word, low_word;
1786 /* Fetch the instruction. */
1787 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1789 /* Save some code by pre-extracting some useful fields. */
1790 high_word = (inst >> 16) & 0xffff;
1791 low_word = inst & 0xffff;
1792 reg = high_word & 0x1f;
1794 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
1795 || high_word == 0x23bd /* addi $sp,$sp,-i */
1796 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1798 if (low_word & 0x8000) /* negative stack adjustment? */
1799 frame_offset += 0x10000 - low_word;
1801 /* Exit loop if a positive stack adjustment is found, which
1802 usually means that the stack cleanup code in the function
1803 epilogue is reached. */
1807 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1809 set_reg_offset (this_cache, reg, sp + low_word);
1811 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1813 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1814 set_reg_offset (this_cache, reg, sp + low_word);
1816 else if (high_word == 0x27be) /* addiu $30,$sp,size */
1818 /* Old gcc frame, r30 is virtual frame pointer. */
1819 if ((long) low_word != frame_offset)
1820 frame_addr = sp + low_word;
1821 else if (frame_reg == MIPS_SP_REGNUM)
1823 unsigned alloca_adjust;
1826 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
1827 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
1828 if (alloca_adjust > 0)
1830 /* FP > SP + frame_size. This may be because of
1831 an alloca or somethings similar. Fix sp to
1832 "pre-alloca" value, and try again. */
1833 sp += alloca_adjust;
1834 /* Need to reset the status of all registers. Otherwise,
1835 we will hit a guard that prevents the new address
1836 for each register to be recomputed during the second
1838 reset_saved_regs (this_cache);
1843 /* move $30,$sp. With different versions of gas this will be either
1844 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1845 Accept any one of these. */
1846 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1848 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1849 if (frame_reg == MIPS_SP_REGNUM)
1851 unsigned alloca_adjust;
1854 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
1855 alloca_adjust = (unsigned) (frame_addr - sp);
1856 if (alloca_adjust > 0)
1858 /* FP > SP + frame_size. This may be because of
1859 an alloca or somethings similar. Fix sp to
1860 "pre-alloca" value, and try again. */
1862 /* Need to reset the status of all registers. Otherwise,
1863 we will hit a guard that prevents the new address
1864 for each register to be recomputed during the second
1866 reset_saved_regs (this_cache);
1871 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1873 set_reg_offset (this_cache, reg, frame_addr + low_word);
1875 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1876 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1877 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1878 || high_word == 0x3c1c /* lui $gp,n */
1879 || high_word == 0x279c /* addiu $gp,$gp,n */
1880 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
1881 || inst == 0x033ce021 /* addu $gp,$t9,$gp */
1884 /* These instructions are part of the prologue, but we don't
1885 need to do anything special to handle them. */
1887 /* The instructions below load $at or $t0 with an immediate
1888 value in preparation for a stack adjustment via
1889 subu $sp,$sp,[$at,$t0]. These instructions could also
1890 initialize a local variable, so we accept them only before
1891 a stack adjustment instruction was seen. */
1892 else if (!seen_sp_adjust
1893 && (high_word == 0x3c01 /* lui $at,n */
1894 || high_word == 0x3c08 /* lui $t0,n */
1895 || high_word == 0x3421 /* ori $at,$at,n */
1896 || high_word == 0x3508 /* ori $t0,$t0,n */
1897 || high_word == 0x3401 /* ori $at,$zero,n */
1898 || high_word == 0x3408 /* ori $t0,$zero,n */
1901 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
1905 /* This instruction is not an instruction typically found
1906 in a prologue, so we must have reached the end of the
1908 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
1909 loop now? Why would we need to continue scanning the function
1911 if (end_prologue_addr == 0)
1912 end_prologue_addr = cur_pc;
1916 if (this_cache != NULL)
1919 (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg)
1921 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
1922 this assignment below, eventually. But it's still needed
1924 this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1925 = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM];
1928 /* If we didn't reach the end of the prologue when scanning the function
1929 instructions, then set end_prologue_addr to the address of the
1930 instruction immediately after the last one we scanned. */
1931 /* brobecker/2004-10-10: I don't think this would ever happen, but
1932 we may as well be careful and do our best if we have a null
1933 end_prologue_addr. */
1934 if (end_prologue_addr == 0)
1935 end_prologue_addr = cur_pc;
1937 /* In a frameless function, we might have incorrectly
1938 skipped some load immediate instructions. Undo the skipping
1939 if the load immediate was not followed by a stack adjustment. */
1940 if (load_immediate_bytes && !seen_sp_adjust)
1941 end_prologue_addr -= load_immediate_bytes;
1943 return end_prologue_addr;
1946 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1947 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1948 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1951 static struct mips_frame_cache *
1952 mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache)
1954 struct mips_frame_cache *cache;
1956 if ((*this_cache) != NULL)
1957 return (*this_cache);
1959 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1960 (*this_cache) = cache;
1961 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1963 /* Analyze the function prologue. */
1965 const CORE_ADDR pc =
1966 frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1967 CORE_ADDR start_addr;
1969 find_pc_partial_function (pc, NULL, &start_addr, NULL);
1970 if (start_addr == 0)
1971 start_addr = heuristic_proc_start (pc);
1972 /* We can't analyze the prologue if we couldn't find the begining
1974 if (start_addr == 0)
1977 mips32_scan_prologue (start_addr, pc, next_frame, *this_cache);
1980 /* SP_REGNUM, contains the value and not the address. */
1981 trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
1983 return (*this_cache);
1987 mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache,
1988 struct frame_id *this_id)
1990 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
1992 (*this_id) = frame_id_build (info->base,
1993 frame_func_unwind (next_frame, NORMAL_FRAME));
1997 mips_insn32_frame_prev_register (struct frame_info *next_frame,
1999 int regnum, int *optimizedp,
2000 enum lval_type *lvalp, CORE_ADDR *addrp,
2001 int *realnump, gdb_byte *valuep)
2003 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2005 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
2006 optimizedp, lvalp, addrp, realnump, valuep);
2009 static const struct frame_unwind mips_insn32_frame_unwind =
2012 mips_insn32_frame_this_id,
2013 mips_insn32_frame_prev_register
2016 static const struct frame_unwind *
2017 mips_insn32_frame_sniffer (struct frame_info *next_frame)
2019 CORE_ADDR pc = frame_pc_unwind (next_frame);
2020 if (! mips_pc_is_mips16 (pc))
2021 return &mips_insn32_frame_unwind;
2026 mips_insn32_frame_base_address (struct frame_info *next_frame,
2029 struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame,
2034 static const struct frame_base mips_insn32_frame_base =
2036 &mips_insn32_frame_unwind,
2037 mips_insn32_frame_base_address,
2038 mips_insn32_frame_base_address,
2039 mips_insn32_frame_base_address
2042 static const struct frame_base *
2043 mips_insn32_frame_base_sniffer (struct frame_info *next_frame)
2045 if (mips_insn32_frame_sniffer (next_frame) != NULL)
2046 return &mips_insn32_frame_base;
2051 static struct trad_frame_cache *
2052 mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache)
2055 CORE_ADDR start_addr;
2056 CORE_ADDR stack_addr;
2057 struct trad_frame_cache *this_trad_cache;
2059 if ((*this_cache) != NULL)
2060 return (*this_cache);
2061 this_trad_cache = trad_frame_cache_zalloc (next_frame);
2062 (*this_cache) = this_trad_cache;
2064 /* The return address is in the link register. */
2065 trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM);
2067 /* Frame ID, since it's a frameless / stackless function, no stack
2068 space is allocated and SP on entry is the current SP. */
2069 pc = frame_pc_unwind (next_frame);
2070 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2071 stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM);
2072 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr));
2074 /* Assume that the frame's base is the same as the
2076 trad_frame_set_this_base (this_trad_cache, stack_addr);
2078 return this_trad_cache;
2082 mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache,
2083 struct frame_id *this_id)
2085 struct trad_frame_cache *this_trad_cache
2086 = mips_stub_frame_cache (next_frame, this_cache);
2087 trad_frame_get_id (this_trad_cache, this_id);
2091 mips_stub_frame_prev_register (struct frame_info *next_frame,
2093 int regnum, int *optimizedp,
2094 enum lval_type *lvalp, CORE_ADDR *addrp,
2095 int *realnump, gdb_byte *valuep)
2097 struct trad_frame_cache *this_trad_cache
2098 = mips_stub_frame_cache (next_frame, this_cache);
2099 trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp,
2100 lvalp, addrp, realnump, valuep);
2103 static const struct frame_unwind mips_stub_frame_unwind =
2106 mips_stub_frame_this_id,
2107 mips_stub_frame_prev_register
2110 static const struct frame_unwind *
2111 mips_stub_frame_sniffer (struct frame_info *next_frame)
2113 struct obj_section *s;
2114 CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
2116 if (in_plt_section (pc, NULL))
2117 return &mips_stub_frame_unwind;
2119 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2120 s = find_pc_section (pc);
2123 && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section),
2124 ".MIPS.stubs") == 0)
2125 return &mips_stub_frame_unwind;
2131 mips_stub_frame_base_address (struct frame_info *next_frame,
2134 struct trad_frame_cache *this_trad_cache
2135 = mips_stub_frame_cache (next_frame, this_cache);
2136 return trad_frame_get_this_base (this_trad_cache);
2139 static const struct frame_base mips_stub_frame_base =
2141 &mips_stub_frame_unwind,
2142 mips_stub_frame_base_address,
2143 mips_stub_frame_base_address,
2144 mips_stub_frame_base_address
2147 static const struct frame_base *
2148 mips_stub_frame_base_sniffer (struct frame_info *next_frame)
2150 if (mips_stub_frame_sniffer (next_frame) != NULL)
2151 return &mips_stub_frame_base;
2157 read_next_frame_reg (struct frame_info *fi, int regno)
2159 /* Always a pseudo. */
2160 gdb_assert (regno >= NUM_REGS);
2164 regcache_cooked_read_signed (current_regcache, regno, &val);
2168 return frame_unwind_register_signed (fi, regno);
2172 /* mips_addr_bits_remove - remove useless address bits */
2175 mips_addr_bits_remove (CORE_ADDR addr)
2177 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2178 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
2179 /* This hack is a work-around for existing boards using PMON, the
2180 simulator, and any other 64-bit targets that doesn't have true
2181 64-bit addressing. On these targets, the upper 32 bits of
2182 addresses are ignored by the hardware. Thus, the PC or SP are
2183 likely to have been sign extended to all 1s by instruction
2184 sequences that load 32-bit addresses. For example, a typical
2185 piece of code that loads an address is this:
2187 lui $r2, <upper 16 bits>
2188 ori $r2, <lower 16 bits>
2190 But the lui sign-extends the value such that the upper 32 bits
2191 may be all 1s. The workaround is simply to mask off these
2192 bits. In the future, gcc may be changed to support true 64-bit
2193 addressing, and this masking will have to be disabled. */
2194 return addr &= 0xffffffffUL;
2199 /* mips_software_single_step() is called just before we want to resume
2200 the inferior, if we want to single-step it but there is no hardware
2201 or kernel single-step support (MIPS on GNU/Linux for example). We find
2202 the target of the coming instruction and breakpoint it. */
2205 mips_software_single_step (struct regcache *regcache)
2207 CORE_ADDR pc, next_pc;
2209 pc = read_register (mips_regnum (current_gdbarch)->pc);
2210 next_pc = mips_next_pc (pc);
2212 insert_single_step_breakpoint (next_pc);
2216 /* Test whether the PC points to the return instruction at the
2217 end of a function. */
2220 mips_about_to_return (CORE_ADDR pc)
2222 if (mips_pc_is_mips16 (pc))
2223 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2224 generates a "jr $ra"; other times it generates code to load
2225 the return address from the stack to an accessible register (such
2226 as $a3), then a "jr" using that register. This second case
2227 is almost impossible to distinguish from an indirect jump
2228 used for switch statements, so we don't even try. */
2229 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
2231 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
2235 /* This fencepost looks highly suspicious to me. Removing it also
2236 seems suspicious as it could affect remote debugging across serial
2240 heuristic_proc_start (CORE_ADDR pc)
2247 pc = ADDR_BITS_REMOVE (pc);
2249 fence = start_pc - heuristic_fence_post;
2253 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
2254 fence = VM_MIN_ADDRESS;
2256 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE;
2258 /* search back for previous return */
2259 for (start_pc -= instlen;; start_pc -= instlen)
2260 if (start_pc < fence)
2262 /* It's not clear to me why we reach this point when
2263 stop_soon, but with this test, at least we
2264 don't print out warnings for every child forked (eg, on
2265 decstation). 22apr93 rich@cygnus.com. */
2266 if (stop_soon == NO_STOP_QUIETLY)
2268 static int blurb_printed = 0;
2270 warning (_("GDB can't find the start of the function at 0x%s."),
2275 /* This actually happens frequently in embedded
2276 development, when you first connect to a board
2277 and your stack pointer and pc are nowhere in
2278 particular. This message needs to give people
2279 in that situation enough information to
2280 determine that it's no big deal. */
2281 printf_filtered ("\n\
2282 GDB is unable to find the start of the function at 0x%s\n\
2283 and thus can't determine the size of that function's stack frame.\n\
2284 This means that GDB may be unable to access that stack frame, or\n\
2285 the frames below it.\n\
2286 This problem is most likely caused by an invalid program counter or\n\
2288 However, if you think GDB should simply search farther back\n\
2289 from 0x%s for code which looks like the beginning of a\n\
2290 function, you can increase the range of the search using the `set\n\
2291 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
2298 else if (mips_pc_is_mips16 (start_pc))
2300 unsigned short inst;
2302 /* On MIPS16, any one of the following is likely to be the
2303 start of a function:
2307 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2308 inst = mips_fetch_instruction (start_pc);
2309 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2310 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
2311 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
2312 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
2314 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
2315 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2320 else if (mips_about_to_return (start_pc))
2322 /* Skip return and its delay slot. */
2323 start_pc += 2 * MIPS_INSN32_SIZE;
2330 struct mips_objfile_private
2336 /* According to the current ABI, should the type be passed in a
2337 floating-point register (assuming that there is space)? When there
2338 is no FPU, FP are not even considered as possible candidates for
2339 FP registers and, consequently this returns false - forces FP
2340 arguments into integer registers. */
2343 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2345 return ((typecode == TYPE_CODE_FLT
2347 && (typecode == TYPE_CODE_STRUCT
2348 || typecode == TYPE_CODE_UNION)
2349 && TYPE_NFIELDS (arg_type) == 1
2350 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
2352 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2355 /* On o32, argument passing in GPRs depends on the alignment of the type being
2356 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2359 mips_type_needs_double_align (struct type *type)
2361 enum type_code typecode = TYPE_CODE (type);
2363 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2365 else if (typecode == TYPE_CODE_STRUCT)
2367 if (TYPE_NFIELDS (type) < 1)
2369 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2371 else if (typecode == TYPE_CODE_UNION)
2375 n = TYPE_NFIELDS (type);
2376 for (i = 0; i < n; i++)
2377 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2384 /* Adjust the address downward (direction of stack growth) so that it
2385 is correctly aligned for a new stack frame. */
2387 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2389 return align_down (addr, 16);
2393 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2394 struct regcache *regcache, CORE_ADDR bp_addr,
2395 int nargs, struct value **args, CORE_ADDR sp,
2396 int struct_return, CORE_ADDR struct_addr)
2402 int stack_offset = 0;
2403 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2404 CORE_ADDR func_addr = find_function_addr (function, NULL);
2406 /* For shared libraries, "t9" needs to point at the function
2408 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2410 /* Set the return address register to point to the entry point of
2411 the program, where a breakpoint lies in wait. */
2412 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2414 /* First ensure that the stack and structure return address (if any)
2415 are properly aligned. The stack has to be at least 64-bit
2416 aligned even on 32-bit machines, because doubles must be 64-bit
2417 aligned. For n32 and n64, stack frames need to be 128-bit
2418 aligned, so we round to this widest known alignment. */
2420 sp = align_down (sp, 16);
2421 struct_addr = align_down (struct_addr, 16);
2423 /* Now make space on the stack for the args. We allocate more
2424 than necessary for EABI, because the first few arguments are
2425 passed in registers, but that's OK. */
2426 for (argnum = 0; argnum < nargs; argnum++)
2427 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
2428 mips_stack_argsize (gdbarch));
2429 sp -= align_up (len, 16);
2432 fprintf_unfiltered (gdb_stdlog,
2433 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2434 paddr_nz (sp), (long) align_up (len, 16));
2436 /* Initialize the integer and float register pointers. */
2437 argreg = MIPS_A0_REGNUM;
2438 float_argreg = mips_fpa0_regnum (current_gdbarch);
2440 /* The struct_return pointer occupies the first parameter-passing reg. */
2444 fprintf_unfiltered (gdb_stdlog,
2445 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2446 argreg, paddr_nz (struct_addr));
2447 write_register (argreg++, struct_addr);
2450 /* Now load as many as possible of the first arguments into
2451 registers, and push the rest onto the stack. Loop thru args
2452 from first to last. */
2453 for (argnum = 0; argnum < nargs; argnum++)
2455 const gdb_byte *val;
2456 gdb_byte valbuf[MAX_REGISTER_SIZE];
2457 struct value *arg = args[argnum];
2458 struct type *arg_type = check_typedef (value_type (arg));
2459 int len = TYPE_LENGTH (arg_type);
2460 enum type_code typecode = TYPE_CODE (arg_type);
2463 fprintf_unfiltered (gdb_stdlog,
2464 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2465 argnum + 1, len, (int) typecode);
2467 /* The EABI passes structures that do not fit in a register by
2469 if (len > mips_abi_regsize (gdbarch)
2470 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2472 store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch),
2473 VALUE_ADDRESS (arg));
2474 typecode = TYPE_CODE_PTR;
2475 len = mips_abi_regsize (gdbarch);
2478 fprintf_unfiltered (gdb_stdlog, " push");
2481 val = value_contents (arg);
2483 /* 32-bit ABIs always start floating point arguments in an
2484 even-numbered floating point register. Round the FP register
2485 up before the check to see if there are any FP registers
2486 left. Non MIPS_EABI targets also pass the FP in the integer
2487 registers so also round up normal registers. */
2488 if (mips_abi_regsize (gdbarch) < 8
2489 && fp_register_arg_p (typecode, arg_type))
2491 if ((float_argreg & 1))
2495 /* Floating point arguments passed in registers have to be
2496 treated specially. On 32-bit architectures, doubles
2497 are passed in register pairs; the even register gets
2498 the low word, and the odd register gets the high word.
2499 On non-EABI processors, the first two floating point arguments are
2500 also copied to general registers, because MIPS16 functions
2501 don't use float registers for arguments. This duplication of
2502 arguments in general registers can't hurt non-MIPS16 functions
2503 because those registers are normally skipped. */
2504 /* MIPS_EABI squeezes a struct that contains a single floating
2505 point value into an FP register instead of pushing it onto the
2507 if (fp_register_arg_p (typecode, arg_type)
2508 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2510 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
2512 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2513 unsigned long regval;
2515 /* Write the low word of the double to the even register(s). */
2516 regval = extract_unsigned_integer (val + low_offset, 4);
2518 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2519 float_argreg, phex (regval, 4));
2520 write_register (float_argreg++, regval);
2522 /* Write the high word of the double to the odd register(s). */
2523 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2525 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2526 float_argreg, phex (regval, 4));
2527 write_register (float_argreg++, regval);
2531 /* This is a floating point value that fits entirely
2532 in a single register. */
2533 /* On 32 bit ABI's the float_argreg is further adjusted
2534 above to ensure that it is even register aligned. */
2535 LONGEST regval = extract_unsigned_integer (val, len);
2537 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2538 float_argreg, phex (regval, len));
2539 write_register (float_argreg++, regval);
2544 /* Copy the argument to general registers or the stack in
2545 register-sized pieces. Large arguments are split between
2546 registers and stack. */
2547 /* Note: structs whose size is not a multiple of
2548 mips_abi_regsize() are treated specially: Irix cc passes
2549 them in registers where gcc sometimes puts them on the
2550 stack. For maximum compatibility, we will put them in
2552 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
2553 && (len % mips_abi_regsize (gdbarch) != 0));
2555 /* Note: Floating-point values that didn't fit into an FP
2556 register are only written to memory. */
2559 /* Remember if the argument was written to the stack. */
2560 int stack_used_p = 0;
2561 int partial_len = (len < mips_abi_regsize (gdbarch)
2562 ? len : mips_abi_regsize (gdbarch));
2565 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2568 /* Write this portion of the argument to the stack. */
2569 if (argreg > MIPS_LAST_ARG_REGNUM
2571 || fp_register_arg_p (typecode, arg_type))
2573 /* Should shorter than int integer values be
2574 promoted to int before being stored? */
2575 int longword_offset = 0;
2578 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2580 if (mips_stack_argsize (gdbarch) == 8
2581 && (typecode == TYPE_CODE_INT
2582 || typecode == TYPE_CODE_PTR
2583 || typecode == TYPE_CODE_FLT) && len <= 4)
2584 longword_offset = mips_stack_argsize (gdbarch) - len;
2585 else if ((typecode == TYPE_CODE_STRUCT
2586 || typecode == TYPE_CODE_UNION)
2587 && (TYPE_LENGTH (arg_type)
2588 < mips_stack_argsize (gdbarch)))
2589 longword_offset = mips_stack_argsize (gdbarch) - len;
2594 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2595 paddr_nz (stack_offset));
2596 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2597 paddr_nz (longword_offset));
2600 addr = sp + stack_offset + longword_offset;
2605 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2607 for (i = 0; i < partial_len; i++)
2609 fprintf_unfiltered (gdb_stdlog, "%02x",
2613 write_memory (addr, val, partial_len);
2616 /* Note!!! This is NOT an else clause. Odd sized
2617 structs may go thru BOTH paths. Floating point
2618 arguments will not. */
2619 /* Write this portion of the argument to a general
2620 purpose register. */
2621 if (argreg <= MIPS_LAST_ARG_REGNUM
2622 && !fp_register_arg_p (typecode, arg_type))
2625 extract_unsigned_integer (val, partial_len);
2628 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2631 mips_abi_regsize (gdbarch)));
2632 write_register (argreg, regval);
2639 /* Compute the the offset into the stack at which we
2640 will copy the next parameter.
2642 In the new EABI (and the NABI32), the stack_offset
2643 only needs to be adjusted when it has been used. */
2646 stack_offset += align_up (partial_len,
2647 mips_stack_argsize (gdbarch));
2651 fprintf_unfiltered (gdb_stdlog, "\n");
2654 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2656 /* Return adjusted stack pointer. */
2660 /* Determine the return value convention being used. */
2662 static enum return_value_convention
2663 mips_eabi_return_value (struct gdbarch *gdbarch,
2664 struct type *type, struct regcache *regcache,
2665 gdb_byte *readbuf, const gdb_byte *writebuf)
2667 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2668 return RETURN_VALUE_STRUCT_CONVENTION;
2670 memset (readbuf, 0, TYPE_LENGTH (type));
2671 return RETURN_VALUE_REGISTER_CONVENTION;
2675 /* N32/N64 ABI stuff. */
2678 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2679 struct regcache *regcache, CORE_ADDR bp_addr,
2680 int nargs, struct value **args, CORE_ADDR sp,
2681 int struct_return, CORE_ADDR struct_addr)
2687 int stack_offset = 0;
2688 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2689 CORE_ADDR func_addr = find_function_addr (function, NULL);
2691 /* For shared libraries, "t9" needs to point at the function
2693 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
2695 /* Set the return address register to point to the entry point of
2696 the program, where a breakpoint lies in wait. */
2697 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
2699 /* First ensure that the stack and structure return address (if any)
2700 are properly aligned. The stack has to be at least 64-bit
2701 aligned even on 32-bit machines, because doubles must be 64-bit
2702 aligned. For n32 and n64, stack frames need to be 128-bit
2703 aligned, so we round to this widest known alignment. */
2705 sp = align_down (sp, 16);
2706 struct_addr = align_down (struct_addr, 16);
2708 /* Now make space on the stack for the args. */
2709 for (argnum = 0; argnum < nargs; argnum++)
2710 len += align_up (TYPE_LENGTH (value_type (args[argnum])),
2711 mips_stack_argsize (gdbarch));
2712 sp -= align_up (len, 16);
2715 fprintf_unfiltered (gdb_stdlog,
2716 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2717 paddr_nz (sp), (long) align_up (len, 16));
2719 /* Initialize the integer and float register pointers. */
2720 argreg = MIPS_A0_REGNUM;
2721 float_argreg = mips_fpa0_regnum (current_gdbarch);
2723 /* The struct_return pointer occupies the first parameter-passing reg. */
2727 fprintf_unfiltered (gdb_stdlog,
2728 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2729 argreg, paddr_nz (struct_addr));
2730 write_register (argreg++, struct_addr);
2733 /* Now load as many as possible of the first arguments into
2734 registers, and push the rest onto the stack. Loop thru args
2735 from first to last. */
2736 for (argnum = 0; argnum < nargs; argnum++)
2738 const gdb_byte *val;
2739 struct value *arg = args[argnum];
2740 struct type *arg_type = check_typedef (value_type (arg));
2741 int len = TYPE_LENGTH (arg_type);
2742 enum type_code typecode = TYPE_CODE (arg_type);
2745 fprintf_unfiltered (gdb_stdlog,
2746 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2747 argnum + 1, len, (int) typecode);
2749 val = value_contents (arg);
2751 if (fp_register_arg_p (typecode, arg_type)
2752 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2754 /* This is a floating point value that fits entirely
2755 in a single register. */
2756 /* On 32 bit ABI's the float_argreg is further adjusted
2757 above to ensure that it is even register aligned. */
2758 LONGEST regval = extract_unsigned_integer (val, len);
2760 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2761 float_argreg, phex (regval, len));
2762 write_register (float_argreg++, regval);
2765 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
2766 argreg, phex (regval, len));
2767 write_register (argreg, regval);
2772 /* Copy the argument to general registers or the stack in
2773 register-sized pieces. Large arguments are split between
2774 registers and stack. */
2775 /* Note: structs whose size is not a multiple of
2776 mips_abi_regsize() are treated specially: Irix cc passes
2777 them in registers where gcc sometimes puts them on the
2778 stack. For maximum compatibility, we will put them in
2780 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
2781 && (len % mips_abi_regsize (gdbarch) != 0));
2782 /* Note: Floating-point values that didn't fit into an FP
2783 register are only written to memory. */
2786 /* Remember if the argument was written to the stack. */
2787 int stack_used_p = 0;
2788 int partial_len = (len < mips_abi_regsize (gdbarch)
2789 ? len : mips_abi_regsize (gdbarch));
2792 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2795 /* Write this portion of the argument to the stack. */
2796 if (argreg > MIPS_LAST_ARG_REGNUM
2798 || fp_register_arg_p (typecode, arg_type))
2800 /* Should shorter than int integer values be
2801 promoted to int before being stored? */
2802 int longword_offset = 0;
2805 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2807 if (mips_stack_argsize (gdbarch) == 8
2808 && (typecode == TYPE_CODE_INT
2809 || typecode == TYPE_CODE_PTR
2810 || typecode == TYPE_CODE_FLT) && len <= 4)
2811 longword_offset = mips_stack_argsize (gdbarch) - len;
2816 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2817 paddr_nz (stack_offset));
2818 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2819 paddr_nz (longword_offset));
2822 addr = sp + stack_offset + longword_offset;
2827 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2829 for (i = 0; i < partial_len; i++)
2831 fprintf_unfiltered (gdb_stdlog, "%02x",
2835 write_memory (addr, val, partial_len);
2838 /* Note!!! This is NOT an else clause. Odd sized
2839 structs may go thru BOTH paths. Floating point
2840 arguments will not. */
2841 /* Write this portion of the argument to a general
2842 purpose register. */
2843 if (argreg <= MIPS_LAST_ARG_REGNUM
2844 && !fp_register_arg_p (typecode, arg_type))
2847 extract_unsigned_integer (val, partial_len);
2849 /* A non-floating-point argument being passed in a
2850 general register. If a struct or union, and if
2851 the remaining length is smaller than the register
2852 size, we have to adjust the register value on
2855 It does not seem to be necessary to do the
2856 same for integral types.
2858 cagney/2001-07-23: gdb/179: Also, GCC, when
2859 outputting LE O32 with sizeof (struct) <
2860 mips_abi_regsize(), generates a left shift
2861 as part of storing the argument in a register
2862 (the left shift isn't generated when
2863 sizeof (struct) >= mips_abi_regsize()). Since
2864 it is quite possible that this is GCC
2865 contradicting the LE/O32 ABI, GDB has not been
2866 adjusted to accommodate this. Either someone
2867 needs to demonstrate that the LE/O32 ABI
2868 specifies such a left shift OR this new ABI gets
2869 identified as such and GDB gets tweaked
2872 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2873 && partial_len < mips_abi_regsize (gdbarch)
2874 && (typecode == TYPE_CODE_STRUCT
2875 || typecode == TYPE_CODE_UNION))
2876 regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
2880 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2883 mips_abi_regsize (gdbarch)));
2884 write_register (argreg, regval);
2891 /* Compute the the offset into the stack at which we
2892 will copy the next parameter.
2894 In N32 (N64?), the stack_offset only needs to be
2895 adjusted when it has been used. */
2898 stack_offset += align_up (partial_len,
2899 mips_stack_argsize (gdbarch));
2903 fprintf_unfiltered (gdb_stdlog, "\n");
2906 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
2908 /* Return adjusted stack pointer. */
2912 static enum return_value_convention
2913 mips_n32n64_return_value (struct gdbarch *gdbarch,
2914 struct type *type, struct regcache *regcache,
2915 gdb_byte *readbuf, const gdb_byte *writebuf)
2917 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2918 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2919 || TYPE_CODE (type) == TYPE_CODE_UNION
2920 || TYPE_CODE (type) == TYPE_CODE_ARRAY
2921 || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
2922 return RETURN_VALUE_STRUCT_CONVENTION;
2923 else if (TYPE_CODE (type) == TYPE_CODE_FLT
2924 && TYPE_LENGTH (type) == 16
2925 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2927 /* A 128-bit floating-point value fills both $f0 and $f2. The
2928 two registers are used in the same as memory order, so the
2929 eight bytes with the lower memory address are in $f0. */
2931 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
2932 mips_xfer_register (regcache,
2933 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
2934 8, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
2935 mips_xfer_register (regcache,
2936 NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 2,
2937 8, TARGET_BYTE_ORDER, readbuf ? readbuf + 8 : readbuf,
2938 writebuf ? writebuf + 8 : writebuf, 0);
2939 return RETURN_VALUE_REGISTER_CONVENTION;
2941 else if (TYPE_CODE (type) == TYPE_CODE_FLT
2942 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2944 /* A floating-point value belongs in the least significant part
2947 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
2948 mips_xfer_register (regcache,
2949 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
2951 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
2952 return RETURN_VALUE_REGISTER_CONVENTION;
2954 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2955 && TYPE_NFIELDS (type) <= 2
2956 && TYPE_NFIELDS (type) >= 1
2957 && ((TYPE_NFIELDS (type) == 1
2958 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
2960 || (TYPE_NFIELDS (type) == 2
2961 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
2963 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
2965 && tdep->mips_fpu_type != MIPS_FPU_NONE)
2967 /* A struct that contains one or two floats. Each value is part
2968 in the least significant part of their floating point
2972 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
2973 field < TYPE_NFIELDS (type); field++, regnum += 2)
2975 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
2978 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
2980 mips_xfer_register (regcache, NUM_REGS + regnum,
2981 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
2982 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
2984 return RETURN_VALUE_REGISTER_CONVENTION;
2986 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2987 || TYPE_CODE (type) == TYPE_CODE_UNION)
2989 /* A structure or union. Extract the left justified value,
2990 regardless of the byte order. I.e. DO NOT USE
2994 for (offset = 0, regnum = MIPS_V0_REGNUM;
2995 offset < TYPE_LENGTH (type);
2996 offset += register_size (current_gdbarch, regnum), regnum++)
2998 int xfer = register_size (current_gdbarch, regnum);
2999 if (offset + xfer > TYPE_LENGTH (type))
3000 xfer = TYPE_LENGTH (type) - offset;
3002 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3003 offset, xfer, regnum);
3004 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3005 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3007 return RETURN_VALUE_REGISTER_CONVENTION;
3011 /* A scalar extract each part but least-significant-byte
3015 for (offset = 0, regnum = MIPS_V0_REGNUM;
3016 offset < TYPE_LENGTH (type);
3017 offset += register_size (current_gdbarch, regnum), regnum++)
3019 int xfer = register_size (current_gdbarch, regnum);
3020 if (offset + xfer > TYPE_LENGTH (type))
3021 xfer = TYPE_LENGTH (type) - offset;
3023 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3024 offset, xfer, regnum);
3025 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3026 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3028 return RETURN_VALUE_REGISTER_CONVENTION;
3032 /* O32 ABI stuff. */
3035 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3036 struct regcache *regcache, CORE_ADDR bp_addr,
3037 int nargs, struct value **args, CORE_ADDR sp,
3038 int struct_return, CORE_ADDR struct_addr)
3044 int stack_offset = 0;
3045 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3046 CORE_ADDR func_addr = find_function_addr (function, NULL);
3048 /* For shared libraries, "t9" needs to point at the function
3050 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3052 /* Set the return address register to point to the entry point of
3053 the program, where a breakpoint lies in wait. */
3054 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3056 /* First ensure that the stack and structure return address (if any)
3057 are properly aligned. The stack has to be at least 64-bit
3058 aligned even on 32-bit machines, because doubles must be 64-bit
3059 aligned. For n32 and n64, stack frames need to be 128-bit
3060 aligned, so we round to this widest known alignment. */
3062 sp = align_down (sp, 16);
3063 struct_addr = align_down (struct_addr, 16);
3065 /* Now make space on the stack for the args. */
3066 for (argnum = 0; argnum < nargs; argnum++)
3068 struct type *arg_type = check_typedef (value_type (args[argnum]));
3069 int arglen = TYPE_LENGTH (arg_type);
3071 /* Align to double-word if necessary. */
3072 if (mips_type_needs_double_align (arg_type))
3073 len = align_up (len, mips_stack_argsize (gdbarch) * 2);
3074 /* Allocate space on the stack. */
3075 len += align_up (arglen, mips_stack_argsize (gdbarch));
3077 sp -= align_up (len, 16);
3080 fprintf_unfiltered (gdb_stdlog,
3081 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3082 paddr_nz (sp), (long) align_up (len, 16));
3084 /* Initialize the integer and float register pointers. */
3085 argreg = MIPS_A0_REGNUM;
3086 float_argreg = mips_fpa0_regnum (current_gdbarch);
3088 /* The struct_return pointer occupies the first parameter-passing reg. */
3092 fprintf_unfiltered (gdb_stdlog,
3093 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3094 argreg, paddr_nz (struct_addr));
3095 write_register (argreg++, struct_addr);
3096 stack_offset += mips_stack_argsize (gdbarch);
3099 /* Now load as many as possible of the first arguments into
3100 registers, and push the rest onto the stack. Loop thru args
3101 from first to last. */
3102 for (argnum = 0; argnum < nargs; argnum++)
3104 const gdb_byte *val;
3105 struct value *arg = args[argnum];
3106 struct type *arg_type = check_typedef (value_type (arg));
3107 int len = TYPE_LENGTH (arg_type);
3108 enum type_code typecode = TYPE_CODE (arg_type);
3111 fprintf_unfiltered (gdb_stdlog,
3112 "mips_o32_push_dummy_call: %d len=%d type=%d",
3113 argnum + 1, len, (int) typecode);
3115 val = value_contents (arg);
3117 /* 32-bit ABIs always start floating point arguments in an
3118 even-numbered floating point register. Round the FP register
3119 up before the check to see if there are any FP registers
3120 left. O32/O64 targets also pass the FP in the integer
3121 registers so also round up normal registers. */
3122 if (fp_register_arg_p (typecode, arg_type))
3124 if ((float_argreg & 1))
3128 /* Floating point arguments passed in registers have to be
3129 treated specially. On 32-bit architectures, doubles
3130 are passed in register pairs; the even register gets
3131 the low word, and the odd register gets the high word.
3132 On O32/O64, the first two floating point arguments are
3133 also copied to general registers, because MIPS16 functions
3134 don't use float registers for arguments. This duplication of
3135 arguments in general registers can't hurt non-MIPS16 functions
3136 because those registers are normally skipped. */
3138 if (fp_register_arg_p (typecode, arg_type)
3139 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3141 if (register_size (gdbarch, float_argreg) < 8 && len == 8)
3143 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3144 unsigned long regval;
3146 /* Write the low word of the double to the even register(s). */
3147 regval = extract_unsigned_integer (val + low_offset, 4);
3149 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3150 float_argreg, phex (regval, 4));
3151 write_register (float_argreg++, regval);
3153 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3154 argreg, phex (regval, 4));
3155 write_register (argreg++, regval);
3157 /* Write the high word of the double to the odd register(s). */
3158 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3160 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3161 float_argreg, phex (regval, 4));
3162 write_register (float_argreg++, regval);
3165 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3166 argreg, phex (regval, 4));
3167 write_register (argreg++, regval);
3171 /* This is a floating point value that fits entirely
3172 in a single register. */
3173 /* On 32 bit ABI's the float_argreg is further adjusted
3174 above to ensure that it is even register aligned. */
3175 LONGEST regval = extract_unsigned_integer (val, len);
3177 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3178 float_argreg, phex (regval, len));
3179 write_register (float_argreg++, regval);
3180 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3181 registers for each argument. The below is (my
3182 guess) to ensure that the corresponding integer
3183 register has reserved the same space. */
3185 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3186 argreg, phex (regval, len));
3187 write_register (argreg, regval);
3190 /* Reserve space for the FP register. */
3191 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
3195 /* Copy the argument to general registers or the stack in
3196 register-sized pieces. Large arguments are split between
3197 registers and stack. */
3198 /* Note: structs whose size is not a multiple of
3199 mips_abi_regsize() are treated specially: Irix cc passes
3200 them in registers where gcc sometimes puts them on the
3201 stack. For maximum compatibility, we will put them in
3203 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3204 && (len % mips_abi_regsize (gdbarch) != 0));
3205 /* Structures should be aligned to eight bytes (even arg registers)
3206 on MIPS_ABI_O32, if their first member has double precision. */
3207 if (mips_type_needs_double_align (arg_type))
3212 stack_offset += mips_abi_regsize (gdbarch);
3217 /* Remember if the argument was written to the stack. */
3218 int stack_used_p = 0;
3219 int partial_len = (len < mips_abi_regsize (gdbarch)
3220 ? len : mips_abi_regsize (gdbarch));
3223 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3226 /* Write this portion of the argument to the stack. */
3227 if (argreg > MIPS_LAST_ARG_REGNUM
3228 || odd_sized_struct)
3230 /* Should shorter than int integer values be
3231 promoted to int before being stored? */
3232 int longword_offset = 0;
3235 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3237 if (mips_stack_argsize (gdbarch) == 8
3238 && (typecode == TYPE_CODE_INT
3239 || typecode == TYPE_CODE_PTR
3240 || typecode == TYPE_CODE_FLT) && len <= 4)
3241 longword_offset = mips_stack_argsize (gdbarch) - len;
3246 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3247 paddr_nz (stack_offset));
3248 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3249 paddr_nz (longword_offset));
3252 addr = sp + stack_offset + longword_offset;
3257 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3259 for (i = 0; i < partial_len; i++)
3261 fprintf_unfiltered (gdb_stdlog, "%02x",
3265 write_memory (addr, val, partial_len);
3268 /* Note!!! This is NOT an else clause. Odd sized
3269 structs may go thru BOTH paths. */
3270 /* Write this portion of the argument to a general
3271 purpose register. */
3272 if (argreg <= MIPS_LAST_ARG_REGNUM)
3274 LONGEST regval = extract_signed_integer (val, partial_len);
3275 /* Value may need to be sign extended, because
3276 mips_isa_regsize() != mips_abi_regsize(). */
3278 /* A non-floating-point argument being passed in a
3279 general register. If a struct or union, and if
3280 the remaining length is smaller than the register
3281 size, we have to adjust the register value on
3284 It does not seem to be necessary to do the
3285 same for integral types.
3287 Also don't do this adjustment on O64 binaries.
3289 cagney/2001-07-23: gdb/179: Also, GCC, when
3290 outputting LE O32 with sizeof (struct) <
3291 mips_abi_regsize(), generates a left shift
3292 as part of storing the argument in a register
3293 (the left shift isn't generated when
3294 sizeof (struct) >= mips_abi_regsize()). Since
3295 it is quite possible that this is GCC
3296 contradicting the LE/O32 ABI, GDB has not been
3297 adjusted to accommodate this. Either someone
3298 needs to demonstrate that the LE/O32 ABI
3299 specifies such a left shift OR this new ABI gets
3300 identified as such and GDB gets tweaked
3303 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3304 && partial_len < mips_abi_regsize (gdbarch)
3305 && (typecode == TYPE_CODE_STRUCT
3306 || typecode == TYPE_CODE_UNION))
3307 regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
3311 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3314 mips_abi_regsize (gdbarch)));
3315 write_register (argreg, regval);
3318 /* Prevent subsequent floating point arguments from
3319 being passed in floating point registers. */
3320 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3326 /* Compute the the offset into the stack at which we
3327 will copy the next parameter.
3329 In older ABIs, the caller reserved space for
3330 registers that contained arguments. This was loosely
3331 refered to as their "home". Consequently, space is
3332 always allocated. */
3334 stack_offset += align_up (partial_len,
3335 mips_stack_argsize (gdbarch));
3339 fprintf_unfiltered (gdb_stdlog, "\n");
3342 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3344 /* Return adjusted stack pointer. */
3348 static enum return_value_convention
3349 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3350 struct regcache *regcache,
3351 gdb_byte *readbuf, const gdb_byte *writebuf)
3353 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3355 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3356 || TYPE_CODE (type) == TYPE_CODE_UNION
3357 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3358 return RETURN_VALUE_STRUCT_CONVENTION;
3359 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3360 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3362 /* A single-precision floating-point value. It fits in the
3363 least significant part of FP0. */
3365 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3366 mips_xfer_register (regcache,
3367 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3369 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3370 return RETURN_VALUE_REGISTER_CONVENTION;
3372 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3373 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3375 /* A double-precision floating-point value. The most
3376 significant part goes in FP1, and the least significant in
3379 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3380 switch (TARGET_BYTE_ORDER)
3382 case BFD_ENDIAN_LITTLE:
3383 mips_xfer_register (regcache,
3384 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3385 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3386 mips_xfer_register (regcache,
3387 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3388 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3390 case BFD_ENDIAN_BIG:
3391 mips_xfer_register (regcache,
3392 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3393 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3394 mips_xfer_register (regcache,
3395 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3396 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3399 internal_error (__FILE__, __LINE__, _("bad switch"));
3401 return RETURN_VALUE_REGISTER_CONVENTION;
3404 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3405 && TYPE_NFIELDS (type) <= 2
3406 && TYPE_NFIELDS (type) >= 1
3407 && ((TYPE_NFIELDS (type) == 1
3408 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3410 || (TYPE_NFIELDS (type) == 2
3411 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3413 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3415 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3417 /* A struct that contains one or two floats. Each value is part
3418 in the least significant part of their floating point
3420 gdb_byte reg[MAX_REGISTER_SIZE];
3423 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3424 field < TYPE_NFIELDS (type); field++, regnum += 2)
3426 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3429 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3431 mips_xfer_register (regcache, NUM_REGS + regnum,
3432 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3433 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3435 return RETURN_VALUE_REGISTER_CONVENTION;
3439 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3440 || TYPE_CODE (type) == TYPE_CODE_UNION)
3442 /* A structure or union. Extract the left justified value,
3443 regardless of the byte order. I.e. DO NOT USE
3447 for (offset = 0, regnum = MIPS_V0_REGNUM;
3448 offset < TYPE_LENGTH (type);
3449 offset += register_size (current_gdbarch, regnum), regnum++)
3451 int xfer = register_size (current_gdbarch, regnum);
3452 if (offset + xfer > TYPE_LENGTH (type))
3453 xfer = TYPE_LENGTH (type) - offset;
3455 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3456 offset, xfer, regnum);
3457 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3458 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3460 return RETURN_VALUE_REGISTER_CONVENTION;
3465 /* A scalar extract each part but least-significant-byte
3466 justified. o32 thinks registers are 4 byte, regardless of
3467 the ISA. mips_stack_argsize controls this. */
3470 for (offset = 0, regnum = MIPS_V0_REGNUM;
3471 offset < TYPE_LENGTH (type);
3472 offset += mips_stack_argsize (gdbarch), regnum++)
3474 int xfer = mips_stack_argsize (gdbarch);
3475 if (offset + xfer > TYPE_LENGTH (type))
3476 xfer = TYPE_LENGTH (type) - offset;
3478 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3479 offset, xfer, regnum);
3480 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3481 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3483 return RETURN_VALUE_REGISTER_CONVENTION;
3487 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3491 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3492 struct regcache *regcache, CORE_ADDR bp_addr,
3494 struct value **args, CORE_ADDR sp,
3495 int struct_return, CORE_ADDR struct_addr)
3501 int stack_offset = 0;
3502 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3503 CORE_ADDR func_addr = find_function_addr (function, NULL);
3505 /* For shared libraries, "t9" needs to point at the function
3507 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr);
3509 /* Set the return address register to point to the entry point of
3510 the program, where a breakpoint lies in wait. */
3511 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr);
3513 /* First ensure that the stack and structure return address (if any)
3514 are properly aligned. The stack has to be at least 64-bit
3515 aligned even on 32-bit machines, because doubles must be 64-bit
3516 aligned. For n32 and n64, stack frames need to be 128-bit
3517 aligned, so we round to this widest known alignment. */
3519 sp = align_down (sp, 16);
3520 struct_addr = align_down (struct_addr, 16);
3522 /* Now make space on the stack for the args. */
3523 for (argnum = 0; argnum < nargs; argnum++)
3525 struct type *arg_type = check_typedef (value_type (args[argnum]));
3526 int arglen = TYPE_LENGTH (arg_type);
3528 /* Allocate space on the stack. */
3529 len += align_up (arglen, mips_stack_argsize (gdbarch));
3531 sp -= align_up (len, 16);
3534 fprintf_unfiltered (gdb_stdlog,
3535 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3536 paddr_nz (sp), (long) align_up (len, 16));
3538 /* Initialize the integer and float register pointers. */
3539 argreg = MIPS_A0_REGNUM;
3540 float_argreg = mips_fpa0_regnum (current_gdbarch);
3542 /* The struct_return pointer occupies the first parameter-passing reg. */
3546 fprintf_unfiltered (gdb_stdlog,
3547 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3548 argreg, paddr_nz (struct_addr));
3549 write_register (argreg++, struct_addr);
3550 stack_offset += mips_stack_argsize (gdbarch);
3553 /* Now load as many as possible of the first arguments into
3554 registers, and push the rest onto the stack. Loop thru args
3555 from first to last. */
3556 for (argnum = 0; argnum < nargs; argnum++)
3558 const gdb_byte *val;
3559 struct value *arg = args[argnum];
3560 struct type *arg_type = check_typedef (value_type (arg));
3561 int len = TYPE_LENGTH (arg_type);
3562 enum type_code typecode = TYPE_CODE (arg_type);
3565 fprintf_unfiltered (gdb_stdlog,
3566 "mips_o64_push_dummy_call: %d len=%d type=%d",
3567 argnum + 1, len, (int) typecode);
3569 val = value_contents (arg);
3571 /* Floating point arguments passed in registers have to be
3572 treated specially. On 32-bit architectures, doubles
3573 are passed in register pairs; the even register gets
3574 the low word, and the odd register gets the high word.
3575 On O32/O64, the first two floating point arguments are
3576 also copied to general registers, because MIPS16 functions
3577 don't use float registers for arguments. This duplication of
3578 arguments in general registers can't hurt non-MIPS16 functions
3579 because those registers are normally skipped. */
3581 if (fp_register_arg_p (typecode, arg_type)
3582 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3584 LONGEST regval = extract_unsigned_integer (val, len);
3586 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3587 float_argreg, phex (regval, len));
3588 write_register (float_argreg++, regval);
3590 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3591 argreg, phex (regval, len));
3592 write_register (argreg, regval);
3594 /* Reserve space for the FP register. */
3595 stack_offset += align_up (len, mips_stack_argsize (gdbarch));
3599 /* Copy the argument to general registers or the stack in
3600 register-sized pieces. Large arguments are split between
3601 registers and stack. */
3602 /* Note: structs whose size is not a multiple of
3603 mips_abi_regsize() are treated specially: Irix cc passes
3604 them in registers where gcc sometimes puts them on the
3605 stack. For maximum compatibility, we will put them in
3607 int odd_sized_struct = ((len > mips_abi_regsize (gdbarch))
3608 && (len % mips_abi_regsize (gdbarch) != 0));
3611 /* Remember if the argument was written to the stack. */
3612 int stack_used_p = 0;
3613 int partial_len = (len < mips_abi_regsize (gdbarch)
3614 ? len : mips_abi_regsize (gdbarch));
3617 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3620 /* Write this portion of the argument to the stack. */
3621 if (argreg > MIPS_LAST_ARG_REGNUM
3622 || odd_sized_struct)
3624 /* Should shorter than int integer values be
3625 promoted to int before being stored? */
3626 int longword_offset = 0;
3629 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3631 if (mips_stack_argsize (gdbarch) == 8
3632 && (typecode == TYPE_CODE_INT
3633 || typecode == TYPE_CODE_PTR
3634 || typecode == TYPE_CODE_FLT) && len <= 4)
3635 longword_offset = mips_stack_argsize (gdbarch) - len;
3640 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3641 paddr_nz (stack_offset));
3642 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3643 paddr_nz (longword_offset));
3646 addr = sp + stack_offset + longword_offset;
3651 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3653 for (i = 0; i < partial_len; i++)
3655 fprintf_unfiltered (gdb_stdlog, "%02x",
3659 write_memory (addr, val, partial_len);
3662 /* Note!!! This is NOT an else clause. Odd sized
3663 structs may go thru BOTH paths. */
3664 /* Write this portion of the argument to a general
3665 purpose register. */
3666 if (argreg <= MIPS_LAST_ARG_REGNUM)
3668 LONGEST regval = extract_signed_integer (val, partial_len);
3669 /* Value may need to be sign extended, because
3670 mips_isa_regsize() != mips_abi_regsize(). */
3672 /* A non-floating-point argument being passed in a
3673 general register. If a struct or union, and if
3674 the remaining length is smaller than the register
3675 size, we have to adjust the register value on
3678 It does not seem to be necessary to do the
3679 same for integral types. */
3681 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3682 && partial_len < mips_abi_regsize (gdbarch)
3683 && (typecode == TYPE_CODE_STRUCT
3684 || typecode == TYPE_CODE_UNION))
3685 regval <<= ((mips_abi_regsize (gdbarch) - partial_len)
3689 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3692 mips_abi_regsize (gdbarch)));
3693 write_register (argreg, regval);
3696 /* Prevent subsequent floating point arguments from
3697 being passed in floating point registers. */
3698 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3704 /* Compute the the offset into the stack at which we
3705 will copy the next parameter.
3707 In older ABIs, the caller reserved space for
3708 registers that contained arguments. This was loosely
3709 refered to as their "home". Consequently, space is
3710 always allocated. */
3712 stack_offset += align_up (partial_len,
3713 mips_stack_argsize (gdbarch));
3717 fprintf_unfiltered (gdb_stdlog, "\n");
3720 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
3722 /* Return adjusted stack pointer. */
3726 static enum return_value_convention
3727 mips_o64_return_value (struct gdbarch *gdbarch,
3728 struct type *type, struct regcache *regcache,
3729 gdb_byte *readbuf, const gdb_byte *writebuf)
3731 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3733 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3734 || TYPE_CODE (type) == TYPE_CODE_UNION
3735 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3736 return RETURN_VALUE_STRUCT_CONVENTION;
3737 else if (fp_register_arg_p (TYPE_CODE (type), type))
3739 /* A floating-point value. It fits in the least significant
3742 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3743 mips_xfer_register (regcache,
3744 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3746 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3747 return RETURN_VALUE_REGISTER_CONVENTION;
3751 /* A scalar extract each part but least-significant-byte
3755 for (offset = 0, regnum = MIPS_V0_REGNUM;
3756 offset < TYPE_LENGTH (type);
3757 offset += mips_stack_argsize (gdbarch), regnum++)
3759 int xfer = mips_stack_argsize (gdbarch);
3760 if (offset + xfer > TYPE_LENGTH (type))
3761 xfer = TYPE_LENGTH (type) - offset;
3763 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3764 offset, xfer, regnum);
3765 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3766 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3768 return RETURN_VALUE_REGISTER_CONVENTION;
3772 /* Floating point register management.
3774 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3775 64bit operations, these early MIPS cpus treat fp register pairs
3776 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3777 registers and offer a compatibility mode that emulates the MIPS2 fp
3778 model. When operating in MIPS2 fp compat mode, later cpu's split
3779 double precision floats into two 32-bit chunks and store them in
3780 consecutive fp regs. To display 64-bit floats stored in this
3781 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3782 Throw in user-configurable endianness and you have a real mess.
3784 The way this works is:
3785 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3786 double-precision value will be split across two logical registers.
3787 The lower-numbered logical register will hold the low-order bits,
3788 regardless of the processor's endianness.
3789 - If we are on a 64-bit processor, and we are looking for a
3790 single-precision value, it will be in the low ordered bits
3791 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3792 save slot in memory.
3793 - If we are in 64-bit mode, everything is straightforward.
3795 Note that this code only deals with "live" registers at the top of the
3796 stack. We will attempt to deal with saved registers later, when
3797 the raw/cooked register interface is in place. (We need a general
3798 interface that can deal with dynamic saved register sizes -- fp
3799 regs could be 32 bits wide in one frame and 64 on the frame above
3802 static struct type *
3803 mips_float_register_type (void)
3805 return builtin_type_ieee_single;
3808 static struct type *
3809 mips_double_register_type (void)
3811 return builtin_type_ieee_double;
3814 /* Copy a 32-bit single-precision value from the current frame
3815 into rare_buffer. */
3818 mips_read_fp_register_single (struct frame_info *frame, int regno,
3819 gdb_byte *rare_buffer)
3821 int raw_size = register_size (current_gdbarch, regno);
3822 gdb_byte *raw_buffer = alloca (raw_size);
3824 if (!frame_register_read (frame, regno, raw_buffer))
3825 error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno));
3828 /* We have a 64-bit value for this register. Find the low-order
3832 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3837 memcpy (rare_buffer, raw_buffer + offset, 4);
3841 memcpy (rare_buffer, raw_buffer, 4);
3845 /* Copy a 64-bit double-precision value from the current frame into
3846 rare_buffer. This may include getting half of it from the next
3850 mips_read_fp_register_double (struct frame_info *frame, int regno,
3851 gdb_byte *rare_buffer)
3853 int raw_size = register_size (current_gdbarch, regno);
3855 if (raw_size == 8 && !mips2_fp_compat ())
3857 /* We have a 64-bit value for this register, and we should use
3859 if (!frame_register_read (frame, regno, rare_buffer))
3860 error (_("can't read register %d (%s)"), regno, REGISTER_NAME (regno));
3864 if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
3865 internal_error (__FILE__, __LINE__,
3866 _("mips_read_fp_register_double: bad access to "
3867 "odd-numbered FP register"));
3869 /* mips_read_fp_register_single will find the correct 32 bits from
3871 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3873 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
3874 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
3878 mips_read_fp_register_single (frame, regno, rare_buffer);
3879 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
3885 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
3887 { /* do values for FP (float) regs */
3888 gdb_byte *raw_buffer;
3889 double doub, flt1; /* doubles extracted from raw hex data */
3892 raw_buffer = alloca (2 * register_size (current_gdbarch,
3893 mips_regnum (current_gdbarch)->fp0));
3895 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
3896 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
3899 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
3901 /* 4-byte registers: Print hex and floating. Also print even
3902 numbered registers as doubles. */
3903 mips_read_fp_register_single (frame, regnum, raw_buffer);
3904 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3906 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
3909 fprintf_filtered (file, " flt: ");
3911 fprintf_filtered (file, " <invalid float> ");
3913 fprintf_filtered (file, "%-17.9g", flt1);
3915 if (regnum % 2 == 0)
3917 mips_read_fp_register_double (frame, regnum, raw_buffer);
3918 doub = unpack_double (mips_double_register_type (), raw_buffer,
3921 fprintf_filtered (file, " dbl: ");
3923 fprintf_filtered (file, "<invalid double>");
3925 fprintf_filtered (file, "%-24.17g", doub);
3930 /* Eight byte registers: print each one as hex, float and double. */
3931 mips_read_fp_register_single (frame, regnum, raw_buffer);
3932 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
3934 mips_read_fp_register_double (frame, regnum, raw_buffer);
3935 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
3938 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
3941 fprintf_filtered (file, " flt: ");
3943 fprintf_filtered (file, "<invalid float>");
3945 fprintf_filtered (file, "%-17.9g", flt1);
3947 fprintf_filtered (file, " dbl: ");
3949 fprintf_filtered (file, "<invalid double>");
3951 fprintf_filtered (file, "%-24.17g", doub);
3956 mips_print_register (struct ui_file *file, struct frame_info *frame,
3957 int regnum, int all)
3959 struct gdbarch *gdbarch = get_frame_arch (frame);
3960 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
3963 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
3965 mips_print_fp_register (file, frame, regnum);
3969 /* Get the data in raw format. */
3970 if (!frame_register_read (frame, regnum, raw_buffer))
3972 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
3976 fputs_filtered (REGISTER_NAME (regnum), file);
3978 /* The problem with printing numeric register names (r26, etc.) is that
3979 the user can't use them on input. Probably the best solution is to
3980 fix it so that either the numeric or the funky (a2, etc.) names
3981 are accepted on input. */
3982 if (regnum < MIPS_NUMREGS)
3983 fprintf_filtered (file, "(r%d): ", regnum);
3985 fprintf_filtered (file, ": ");
3987 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3989 register_size (current_gdbarch,
3990 regnum) - register_size (current_gdbarch, regnum);
3994 print_scalar_formatted (raw_buffer + offset,
3995 register_type (gdbarch, regnum), 'x', 0,
3999 /* Replacement for generic do_registers_info.
4000 Print regs in pretty columns. */
4003 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4006 fprintf_filtered (file, " ");
4007 mips_print_fp_register (file, frame, regnum);
4008 fprintf_filtered (file, "\n");
4013 /* Print a row's worth of GP (int) registers, with name labels above */
4016 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4019 struct gdbarch *gdbarch = get_frame_arch (frame);
4020 /* do values for GP (int) regs */
4021 gdb_byte raw_buffer[MAX_REGISTER_SIZE];
4022 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4026 /* For GP registers, we print a separate row of names above the vals */
4027 for (col = 0, regnum = start_regnum;
4028 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4030 if (*REGISTER_NAME (regnum) == '\0')
4031 continue; /* unused register */
4032 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4034 break; /* end the row: reached FP register */
4036 fprintf_filtered (file, " ");
4037 fprintf_filtered (file,
4038 mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4039 REGISTER_NAME (regnum));
4046 /* print the R0 to R31 names */
4047 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4048 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4050 fprintf_filtered (file, "\n ");
4052 /* now print the values in hex, 4 or 8 to the row */
4053 for (col = 0, regnum = start_regnum;
4054 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4056 if (*REGISTER_NAME (regnum) == '\0')
4057 continue; /* unused register */
4058 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4060 break; /* end row: reached FP register */
4061 /* OK: get the data in raw format. */
4062 if (!frame_register_read (frame, regnum, raw_buffer))
4063 error (_("can't read register %d (%s)"), regnum, REGISTER_NAME (regnum));
4064 /* pad small registers */
4066 byte < (mips_abi_regsize (current_gdbarch)
4067 - register_size (current_gdbarch, regnum)); byte++)
4068 printf_filtered (" ");
4069 /* Now print the register value in hex, endian order. */
4070 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4072 register_size (current_gdbarch,
4073 regnum) - register_size (current_gdbarch, regnum);
4074 byte < register_size (current_gdbarch, regnum); byte++)
4075 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4077 for (byte = register_size (current_gdbarch, regnum) - 1;
4079 fprintf_filtered (file, "%02x", raw_buffer[byte]);
4080 fprintf_filtered (file, " ");
4083 if (col > 0) /* ie. if we actually printed anything... */
4084 fprintf_filtered (file, "\n");
4089 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4092 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4093 struct frame_info *frame, int regnum, int all)
4095 if (regnum != -1) /* do one specified register */
4097 gdb_assert (regnum >= NUM_REGS);
4098 if (*(REGISTER_NAME (regnum)) == '\0')
4099 error (_("Not a valid register for the current processor type"));
4101 mips_print_register (file, frame, regnum, 0);
4102 fprintf_filtered (file, "\n");
4105 /* do all (or most) registers */
4108 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4110 if (TYPE_CODE (register_type (gdbarch, regnum)) ==
4113 if (all) /* true for "INFO ALL-REGISTERS" command */
4114 regnum = print_fp_register_row (file, frame, regnum);
4116 regnum += MIPS_NUMREGS; /* skip floating point regs */
4119 regnum = print_gp_register_row (file, frame, regnum);
4124 /* Is this a branch with a delay slot? */
4127 is_delayed (unsigned long insn)
4130 for (i = 0; i < NUMOPCODES; ++i)
4131 if (mips_opcodes[i].pinfo != INSN_MACRO
4132 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4134 return (i < NUMOPCODES
4135 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4136 | INSN_COND_BRANCH_DELAY
4137 | INSN_COND_BRANCH_LIKELY)));
4141 mips_single_step_through_delay (struct gdbarch *gdbarch,
4142 struct frame_info *frame)
4144 CORE_ADDR pc = get_frame_pc (frame);
4145 gdb_byte buf[MIPS_INSN32_SIZE];
4147 /* There is no branch delay slot on MIPS16. */
4148 if (mips_pc_is_mips16 (pc))
4151 if (!breakpoint_here_p (pc + 4))
4154 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf))
4155 /* If error reading memory, guess that it is not a delayed
4158 return is_delayed (extract_unsigned_integer (buf, sizeof buf));
4161 /* To skip prologues, I use this predicate. Returns either PC itself
4162 if the code at PC does not look like a function prologue; otherwise
4163 returns an address that (if we're lucky) follows the prologue. If
4164 LENIENT, then we must skip everything which is involved in setting
4165 up the frame (it's OK to skip more, just so long as we don't skip
4166 anything which might clobber the registers which are being saved.
4167 We must skip more in the case where part of the prologue is in the
4168 delay slot of a non-prologue instruction). */
4171 mips_skip_prologue (CORE_ADDR pc)
4174 CORE_ADDR func_addr;
4176 /* See if we can determine the end of the prologue via the symbol table.
4177 If so, then return either PC, or the PC after the prologue, whichever
4179 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
4181 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
4182 if (post_prologue_pc != 0)
4183 return max (pc, post_prologue_pc);
4186 /* Can't determine prologue from the symbol table, need to examine
4189 /* Find an upper limit on the function prologue using the debug
4190 information. If the debug information could not be used to provide
4191 that bound, then use an arbitrary large number as the upper bound. */
4192 limit_pc = skip_prologue_using_sal (pc);
4194 limit_pc = pc + 100; /* Magic. */
4196 if (mips_pc_is_mips16 (pc))
4197 return mips16_scan_prologue (pc, limit_pc, NULL, NULL);
4199 return mips32_scan_prologue (pc, limit_pc, NULL, NULL);
4202 /* Root of all "set mips "/"show mips " commands. This will eventually be
4203 used for all MIPS-specific commands. */
4206 show_mips_command (char *args, int from_tty)
4208 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4212 set_mips_command (char *args, int from_tty)
4215 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4216 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4219 /* Commands to show/set the MIPS FPU type. */
4222 show_mipsfpu_command (char *args, int from_tty)
4225 switch (MIPS_FPU_TYPE)
4227 case MIPS_FPU_SINGLE:
4228 fpu = "single-precision";
4230 case MIPS_FPU_DOUBLE:
4231 fpu = "double-precision";
4234 fpu = "absent (none)";
4237 internal_error (__FILE__, __LINE__, _("bad switch"));
4239 if (mips_fpu_type_auto)
4241 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4245 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4250 set_mipsfpu_command (char *args, int from_tty)
4253 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4254 show_mipsfpu_command (args, from_tty);
4258 set_mipsfpu_single_command (char *args, int from_tty)
4260 struct gdbarch_info info;
4261 gdbarch_info_init (&info);
4262 mips_fpu_type = MIPS_FPU_SINGLE;
4263 mips_fpu_type_auto = 0;
4264 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4265 instead of relying on globals. Doing that would let generic code
4266 handle the search for this specific architecture. */
4267 if (!gdbarch_update_p (info))
4268 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4272 set_mipsfpu_double_command (char *args, int from_tty)
4274 struct gdbarch_info info;
4275 gdbarch_info_init (&info);
4276 mips_fpu_type = MIPS_FPU_DOUBLE;
4277 mips_fpu_type_auto = 0;
4278 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4279 instead of relying on globals. Doing that would let generic code
4280 handle the search for this specific architecture. */
4281 if (!gdbarch_update_p (info))
4282 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4286 set_mipsfpu_none_command (char *args, int from_tty)
4288 struct gdbarch_info info;
4289 gdbarch_info_init (&info);
4290 mips_fpu_type = MIPS_FPU_NONE;
4291 mips_fpu_type_auto = 0;
4292 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4293 instead of relying on globals. Doing that would let generic code
4294 handle the search for this specific architecture. */
4295 if (!gdbarch_update_p (info))
4296 internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
4300 set_mipsfpu_auto_command (char *args, int from_tty)
4302 mips_fpu_type_auto = 1;
4305 /* Attempt to identify the particular processor model by reading the
4306 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4307 the relevant processor still exists (it dates back to '94) and
4308 secondly this is not the way to do this. The processor type should
4309 be set by forcing an architecture change. */
4312 deprecated_mips_set_processor_regs_hack (void)
4314 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4317 prid = read_register (MIPS_PRID_REGNUM);
4319 if ((prid & ~0xf) == 0x700)
4320 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4323 /* Just like reinit_frame_cache, but with the right arguments to be
4324 callable as an sfunc. */
4327 reinit_frame_cache_sfunc (char *args, int from_tty,
4328 struct cmd_list_element *c)
4330 reinit_frame_cache ();
4334 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4336 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4338 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4339 disassembler needs to be able to locally determine the ISA, and
4340 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4342 if (mips_pc_is_mips16 (memaddr))
4343 info->mach = bfd_mach_mips16;
4345 /* Round down the instruction address to the appropriate boundary. */
4346 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4348 /* Set the disassembler options. */
4349 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4351 /* Set up the disassembler info, so that we get the right
4352 register names from libopcodes. */
4353 if (tdep->mips_abi == MIPS_ABI_N32)
4354 info->disassembler_options = "gpr-names=n32";
4356 info->disassembler_options = "gpr-names=64";
4357 info->flavour = bfd_target_elf_flavour;
4360 /* This string is not recognized explicitly by the disassembler,
4361 but it tells the disassembler to not try to guess the ABI from
4362 the bfd elf headers, such that, if the user overrides the ABI
4363 of a program linked as NewABI, the disassembly will follow the
4364 register naming conventions specified by the user. */
4365 info->disassembler_options = "gpr-names=32";
4367 /* Call the appropriate disassembler based on the target endian-ness. */
4368 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4369 return print_insn_big_mips (memaddr, info);
4371 return print_insn_little_mips (memaddr, info);
4374 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4375 counter value to determine whether a 16- or 32-bit breakpoint should be
4376 used. It returns a pointer to a string of bytes that encode a breakpoint
4377 instruction, stores the length of the string to *lenptr, and adjusts pc
4378 (if necessary) to point to the actual memory location where the
4379 breakpoint should be inserted. */
4381 static const gdb_byte *
4382 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
4384 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4386 if (mips_pc_is_mips16 (*pcptr))
4388 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 };
4389 *pcptr = unmake_mips16_addr (*pcptr);
4390 *lenptr = sizeof (mips16_big_breakpoint);
4391 return mips16_big_breakpoint;
4395 /* The IDT board uses an unusual breakpoint value, and
4396 sometimes gets confused when it sees the usual MIPS
4397 breakpoint instruction. */
4398 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd };
4399 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
4400 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
4402 *lenptr = sizeof (big_breakpoint);
4404 if (strcmp (target_shortname, "mips") == 0)
4405 return idt_big_breakpoint;
4406 else if (strcmp (target_shortname, "ddb") == 0
4407 || strcmp (target_shortname, "pmon") == 0
4408 || strcmp (target_shortname, "lsi") == 0)
4409 return pmon_big_breakpoint;
4411 return big_breakpoint;
4416 if (mips_pc_is_mips16 (*pcptr))
4418 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 };
4419 *pcptr = unmake_mips16_addr (*pcptr);
4420 *lenptr = sizeof (mips16_little_breakpoint);
4421 return mips16_little_breakpoint;
4425 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 };
4426 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
4427 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
4429 *lenptr = sizeof (little_breakpoint);
4431 if (strcmp (target_shortname, "mips") == 0)
4432 return idt_little_breakpoint;
4433 else if (strcmp (target_shortname, "ddb") == 0
4434 || strcmp (target_shortname, "pmon") == 0
4435 || strcmp (target_shortname, "lsi") == 0)
4436 return pmon_little_breakpoint;
4438 return little_breakpoint;
4443 /* If PC is in a mips16 call or return stub, return the address of the target
4444 PC, which is either the callee or the caller. There are several
4445 cases which must be handled:
4447 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4448 target PC is in $31 ($ra).
4449 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4450 and the target PC is in $2.
4451 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4452 before the jal instruction, this is effectively a call stub
4453 and the the target PC is in $2. Otherwise this is effectively
4454 a return stub and the target PC is in $18.
4456 See the source code for the stubs in gcc/config/mips/mips16.S for
4460 mips_skip_trampoline_code (CORE_ADDR pc)
4463 CORE_ADDR start_addr;
4465 /* Find the starting address and name of the function containing the PC. */
4466 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
4469 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4470 target PC is in $31 ($ra). */
4471 if (strcmp (name, "__mips16_ret_sf") == 0
4472 || strcmp (name, "__mips16_ret_df") == 0)
4473 return read_signed_register (MIPS_RA_REGNUM);
4475 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
4477 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4478 and the target PC is in $2. */
4479 if (name[19] >= '0' && name[19] <= '9')
4480 return read_signed_register (2);
4482 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4483 before the jal instruction, this is effectively a call stub
4484 and the the target PC is in $2. Otherwise this is effectively
4485 a return stub and the target PC is in $18. */
4486 else if (name[19] == 's' || name[19] == 'd')
4488 if (pc == start_addr)
4490 /* Check if the target of the stub is a compiler-generated
4491 stub. Such a stub for a function bar might have a name
4492 like __fn_stub_bar, and might look like this:
4497 la $1,bar (becomes a lui/addiu pair)
4499 So scan down to the lui/addi and extract the target
4500 address from those two instructions. */
4502 CORE_ADDR target_pc = read_signed_register (2);
4506 /* See if the name of the target function is __fn_stub_*. */
4507 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
4510 if (strncmp (name, "__fn_stub_", 10) != 0
4511 && strcmp (name, "etext") != 0
4512 && strcmp (name, "_etext") != 0)
4515 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4516 The limit on the search is arbitrarily set to 20
4517 instructions. FIXME. */
4518 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE)
4520 inst = mips_fetch_instruction (target_pc);
4521 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
4522 pc = (inst << 16) & 0xffff0000; /* high word */
4523 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
4524 return pc | (inst & 0xffff); /* low word */
4527 /* Couldn't find the lui/addui pair, so return stub address. */
4531 /* This is the 'return' part of a call stub. The return
4532 address is in $r18. */
4533 return read_signed_register (18);
4536 return 0; /* not a stub */
4539 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4540 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4543 mips_stab_reg_to_regnum (int num)
4546 if (num >= 0 && num < 32)
4548 else if (num >= 38 && num < 70)
4549 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
4551 regnum = mips_regnum (current_gdbarch)->hi;
4553 regnum = mips_regnum (current_gdbarch)->lo;
4555 /* This will hopefully (eventually) provoke a warning. Should
4556 we be calling complaint() here? */
4557 return NUM_REGS + NUM_PSEUDO_REGS;
4558 return NUM_REGS + regnum;
4562 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4563 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
4566 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
4569 if (num >= 0 && num < 32)
4571 else if (num >= 32 && num < 64)
4572 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
4574 regnum = mips_regnum (current_gdbarch)->hi;
4576 regnum = mips_regnum (current_gdbarch)->lo;
4578 /* This will hopefully (eventually) provoke a warning. Should we
4579 be calling complaint() here? */
4580 return NUM_REGS + NUM_PSEUDO_REGS;
4581 return NUM_REGS + regnum;
4585 mips_register_sim_regno (int regnum)
4587 /* Only makes sense to supply raw registers. */
4588 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
4589 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4590 decide if it is valid. Should instead define a standard sim/gdb
4591 register numbering scheme. */
4592 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
4593 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
4596 return LEGACY_SIM_REGNO_IGNORE;
4600 /* Convert an integer into an address. Extracting the value signed
4601 guarantees a correctly sign extended address. */
4604 mips_integer_to_address (struct gdbarch *gdbarch,
4605 struct type *type, const gdb_byte *buf)
4607 return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type));
4611 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
4613 enum mips_abi *abip = (enum mips_abi *) obj;
4614 const char *name = bfd_get_section_name (abfd, sect);
4616 if (*abip != MIPS_ABI_UNKNOWN)
4619 if (strncmp (name, ".mdebug.", 8) != 0)
4622 if (strcmp (name, ".mdebug.abi32") == 0)
4623 *abip = MIPS_ABI_O32;
4624 else if (strcmp (name, ".mdebug.abiN32") == 0)
4625 *abip = MIPS_ABI_N32;
4626 else if (strcmp (name, ".mdebug.abi64") == 0)
4627 *abip = MIPS_ABI_N64;
4628 else if (strcmp (name, ".mdebug.abiO64") == 0)
4629 *abip = MIPS_ABI_O64;
4630 else if (strcmp (name, ".mdebug.eabi32") == 0)
4631 *abip = MIPS_ABI_EABI32;
4632 else if (strcmp (name, ".mdebug.eabi64") == 0)
4633 *abip = MIPS_ABI_EABI64;
4635 warning (_("unsupported ABI %s."), name + 8);
4639 mips_find_long_section (bfd *abfd, asection *sect, void *obj)
4641 int *lbp = (int *) obj;
4642 const char *name = bfd_get_section_name (abfd, sect);
4644 if (strncmp (name, ".gcc_compiled_long32", 20) == 0)
4646 else if (strncmp (name, ".gcc_compiled_long64", 20) == 0)
4648 else if (strncmp (name, ".gcc_compiled_long", 18) == 0)
4649 warning (_("unrecognized .gcc_compiled_longXX"));
4652 static enum mips_abi
4653 global_mips_abi (void)
4657 for (i = 0; mips_abi_strings[i] != NULL; i++)
4658 if (mips_abi_strings[i] == mips_abi_string)
4659 return (enum mips_abi) i;
4661 internal_error (__FILE__, __LINE__, _("unknown ABI string"));
4665 mips_register_g_packet_guesses (struct gdbarch *gdbarch)
4667 static struct target_desc *tdesc_gp32, *tdesc_gp64;
4669 if (tdesc_gp32 == NULL)
4671 /* Create feature sets with the appropriate properties. The values
4672 are not important. */
4674 tdesc_gp32 = allocate_target_description ();
4675 set_tdesc_property (tdesc_gp32, PROPERTY_GP32, "");
4677 tdesc_gp64 = allocate_target_description ();
4678 set_tdesc_property (tdesc_gp64, PROPERTY_GP64, "");
4681 /* If the size matches the set of 32-bit or 64-bit integer registers,
4682 assume that's what we've got. */
4683 register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32);
4684 register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64);
4686 /* If the size matches the full set of registers GDB traditionally
4687 knows about, including floating point, for either 32-bit or
4688 64-bit, assume that's what we've got. */
4689 register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32);
4690 register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64);
4692 /* Otherwise we don't have a useful guess. */
4695 static struct gdbarch *
4696 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4698 struct gdbarch *gdbarch;
4699 struct gdbarch_tdep *tdep;
4701 enum mips_abi mips_abi, found_abi, wanted_abi;
4703 enum mips_fpu_type fpu_type;
4705 /* First of all, extract the elf_flags, if available. */
4706 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
4707 elf_flags = elf_elfheader (info.abfd)->e_flags;
4708 else if (arches != NULL)
4709 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
4713 fprintf_unfiltered (gdb_stdlog,
4714 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
4716 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4717 switch ((elf_flags & EF_MIPS_ABI))
4719 case E_MIPS_ABI_O32:
4720 found_abi = MIPS_ABI_O32;
4722 case E_MIPS_ABI_O64:
4723 found_abi = MIPS_ABI_O64;
4725 case E_MIPS_ABI_EABI32:
4726 found_abi = MIPS_ABI_EABI32;
4728 case E_MIPS_ABI_EABI64:
4729 found_abi = MIPS_ABI_EABI64;
4732 if ((elf_flags & EF_MIPS_ABI2))
4733 found_abi = MIPS_ABI_N32;
4735 found_abi = MIPS_ABI_UNKNOWN;
4739 /* GCC creates a pseudo-section whose name describes the ABI. */
4740 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
4741 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
4743 /* If we have no useful BFD information, use the ABI from the last
4744 MIPS architecture (if there is one). */
4745 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
4746 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
4748 /* Try the architecture for any hint of the correct ABI. */
4749 if (found_abi == MIPS_ABI_UNKNOWN
4750 && info.bfd_arch_info != NULL
4751 && info.bfd_arch_info->arch == bfd_arch_mips)
4753 switch (info.bfd_arch_info->mach)
4755 case bfd_mach_mips3900:
4756 found_abi = MIPS_ABI_EABI32;
4758 case bfd_mach_mips4100:
4759 case bfd_mach_mips5000:
4760 found_abi = MIPS_ABI_EABI64;
4762 case bfd_mach_mips8000:
4763 case bfd_mach_mips10000:
4764 /* On Irix, ELF64 executables use the N64 ABI. The
4765 pseudo-sections which describe the ABI aren't present
4766 on IRIX. (Even for executables created by gcc.) */
4767 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4768 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4769 found_abi = MIPS_ABI_N64;
4771 found_abi = MIPS_ABI_N32;
4776 /* Default 64-bit objects to N64 instead of O32. */
4777 if (found_abi == MIPS_ABI_UNKNOWN
4778 && info.abfd != NULL
4779 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
4780 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
4781 found_abi = MIPS_ABI_N64;
4784 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
4787 /* What has the user specified from the command line? */
4788 wanted_abi = global_mips_abi ();
4790 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
4793 /* Now that we have found what the ABI for this binary would be,
4794 check whether the user is overriding it. */
4795 if (wanted_abi != MIPS_ABI_UNKNOWN)
4796 mips_abi = wanted_abi;
4797 else if (found_abi != MIPS_ABI_UNKNOWN)
4798 mips_abi = found_abi;
4800 mips_abi = MIPS_ABI_O32;
4802 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
4805 /* Also used when doing an architecture lookup. */
4807 fprintf_unfiltered (gdb_stdlog,
4808 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
4809 mips64_transfers_32bit_regs_p);
4811 /* Determine the MIPS FPU type. */
4812 if (!mips_fpu_type_auto)
4813 fpu_type = mips_fpu_type;
4814 else if (info.bfd_arch_info != NULL
4815 && info.bfd_arch_info->arch == bfd_arch_mips)
4816 switch (info.bfd_arch_info->mach)
4818 case bfd_mach_mips3900:
4819 case bfd_mach_mips4100:
4820 case bfd_mach_mips4111:
4821 case bfd_mach_mips4120:
4822 fpu_type = MIPS_FPU_NONE;
4824 case bfd_mach_mips4650:
4825 fpu_type = MIPS_FPU_SINGLE;
4828 fpu_type = MIPS_FPU_DOUBLE;
4831 else if (arches != NULL)
4832 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
4834 fpu_type = MIPS_FPU_DOUBLE;
4836 fprintf_unfiltered (gdb_stdlog,
4837 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
4839 /* Check for blatant incompatibilities. */
4841 /* If we have only 32-bit registers, then we can't debug a 64-bit
4843 if (info.target_desc
4844 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
4845 && mips_abi != MIPS_ABI_EABI32
4846 && mips_abi != MIPS_ABI_O32)
4849 /* try to find a pre-existing architecture */
4850 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4852 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4854 /* MIPS needs to be pedantic about which ABI the object is
4856 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
4858 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
4860 /* Need to be pedantic about which register virtual size is
4862 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
4863 != mips64_transfers_32bit_regs_p)
4865 /* Be pedantic about which FPU is selected. */
4866 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
4868 return arches->gdbarch;
4871 /* Need a new architecture. Fill in a target specific vector. */
4872 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4873 gdbarch = gdbarch_alloc (&info, tdep);
4874 tdep->elf_flags = elf_flags;
4875 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
4876 tdep->found_abi = found_abi;
4877 tdep->mips_abi = mips_abi;
4878 tdep->mips_fpu_type = fpu_type;
4879 tdep->register_size_valid_p = 0;
4880 tdep->register_size = 0;
4882 if (info.target_desc)
4884 /* Some useful properties can be inferred from the target. */
4885 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL)
4887 tdep->register_size_valid_p = 1;
4888 tdep->register_size = 4;
4890 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL)
4892 tdep->register_size_valid_p = 1;
4893 tdep->register_size = 8;
4897 /* Initially set everything according to the default ABI/ISA. */
4898 set_gdbarch_short_bit (gdbarch, 16);
4899 set_gdbarch_int_bit (gdbarch, 32);
4900 set_gdbarch_float_bit (gdbarch, 32);
4901 set_gdbarch_double_bit (gdbarch, 64);
4902 set_gdbarch_long_double_bit (gdbarch, 64);
4903 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
4904 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
4905 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
4907 set_gdbarch_elf_make_msymbol_special (gdbarch,
4908 mips_elf_make_msymbol_special);
4910 /* Fill in the OS dependant register numbers and names. */
4912 const char **reg_names;
4913 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
4914 struct mips_regnum);
4915 if (info.osabi == GDB_OSABI_IRIX)
4920 regnum->badvaddr = 66;
4923 regnum->fp_control_status = 69;
4924 regnum->fp_implementation_revision = 70;
4926 reg_names = mips_irix_reg_names;
4930 regnum->lo = MIPS_EMBED_LO_REGNUM;
4931 regnum->hi = MIPS_EMBED_HI_REGNUM;
4932 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
4933 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
4934 regnum->pc = MIPS_EMBED_PC_REGNUM;
4935 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
4936 regnum->fp_control_status = 70;
4937 regnum->fp_implementation_revision = 71;
4939 if (info.bfd_arch_info != NULL
4940 && info.bfd_arch_info->mach == bfd_mach_mips3900)
4941 reg_names = mips_tx39_reg_names;
4943 reg_names = mips_generic_reg_names;
4945 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
4946 replaced by read_pc? */
4947 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs);
4948 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs);
4949 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
4950 set_gdbarch_num_regs (gdbarch, num_regs);
4951 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
4952 set_gdbarch_register_name (gdbarch, mips_register_name);
4953 tdep->mips_processor_reg_names = reg_names;
4954 tdep->regnum = regnum;
4960 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
4961 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
4962 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
4963 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
4964 tdep->default_mask_address_p = 0;
4965 set_gdbarch_long_bit (gdbarch, 32);
4966 set_gdbarch_ptr_bit (gdbarch, 32);
4967 set_gdbarch_long_long_bit (gdbarch, 64);
4970 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
4971 set_gdbarch_return_value (gdbarch, mips_o64_return_value);
4972 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1;
4973 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
4974 tdep->default_mask_address_p = 0;
4975 set_gdbarch_long_bit (gdbarch, 32);
4976 set_gdbarch_ptr_bit (gdbarch, 32);
4977 set_gdbarch_long_long_bit (gdbarch, 64);
4979 case MIPS_ABI_EABI32:
4980 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
4981 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
4982 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4983 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4984 tdep->default_mask_address_p = 0;
4985 set_gdbarch_long_bit (gdbarch, 32);
4986 set_gdbarch_ptr_bit (gdbarch, 32);
4987 set_gdbarch_long_long_bit (gdbarch, 64);
4989 case MIPS_ABI_EABI64:
4990 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
4991 set_gdbarch_return_value (gdbarch, mips_eabi_return_value);
4992 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
4993 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
4994 tdep->default_mask_address_p = 0;
4995 set_gdbarch_long_bit (gdbarch, 64);
4996 set_gdbarch_ptr_bit (gdbarch, 64);
4997 set_gdbarch_long_long_bit (gdbarch, 64);
5000 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5001 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5002 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5003 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5004 tdep->default_mask_address_p = 0;
5005 set_gdbarch_long_bit (gdbarch, 32);
5006 set_gdbarch_ptr_bit (gdbarch, 32);
5007 set_gdbarch_long_long_bit (gdbarch, 64);
5008 set_gdbarch_long_double_bit (gdbarch, 128);
5009 set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
5012 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5013 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5014 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1;
5015 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5016 tdep->default_mask_address_p = 0;
5017 set_gdbarch_long_bit (gdbarch, 64);
5018 set_gdbarch_ptr_bit (gdbarch, 64);
5019 set_gdbarch_long_long_bit (gdbarch, 64);
5020 set_gdbarch_long_double_bit (gdbarch, 128);
5021 set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long);
5024 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5027 /* GCC creates a pseudo-section whose name specifies the size of
5028 longs, since -mlong32 or -mlong64 may be used independent of
5029 other options. How those options affect pointer sizes is ABI and
5030 architecture dependent, so use them to override the default sizes
5031 set by the ABI. This table shows the relationship between ABI,
5032 -mlongXX, and size of pointers:
5034 ABI -mlongXX ptr bits
5035 --- -------- --------
5049 Note that for o32 and eabi32, pointers are always 32 bits
5050 regardless of any -mlongXX option. For all others, pointers and
5051 longs are the same, as set by -mlongXX or set by defaults.
5054 if (info.abfd != NULL)
5058 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit);
5061 set_gdbarch_long_bit (gdbarch, long_bit);
5065 case MIPS_ABI_EABI32:
5070 case MIPS_ABI_EABI64:
5071 set_gdbarch_ptr_bit (gdbarch, long_bit);
5074 internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
5079 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5080 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5083 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5084 flag in object files because to do so would make it impossible to
5085 link with libraries compiled without "-gp32". This is
5086 unnecessarily restrictive.
5088 We could solve this problem by adding "-gp32" multilibs to gcc,
5089 but to set this flag before gcc is built with such multilibs will
5090 break too many systems.''
5092 But even more unhelpfully, the default linker output target for
5093 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5094 for 64-bit programs - you need to change the ABI to change this,
5095 and not all gcc targets support that currently. Therefore using
5096 this flag to detect 32-bit mode would do the wrong thing given
5097 the current gcc - it would make GDB treat these 64-bit programs
5098 as 32-bit programs by default. */
5100 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5101 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5102 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5104 /* Add/remove bits from an address. The MIPS needs be careful to
5105 ensure that all 32 bit addresses are sign extended to 64 bits. */
5106 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5108 /* Unwind the frame. */
5109 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5110 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5112 /* Map debug register numbers onto internal register numbers. */
5113 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5114 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5115 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5116 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5117 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5118 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5119 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5120 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5122 /* MIPS version of CALL_DUMMY */
5124 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5125 replaced by a command, and all targets will default to on stack
5126 (regardless of the stack's execute status). */
5127 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5128 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5130 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5131 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5132 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5134 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5135 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5137 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5139 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5140 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5141 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5143 set_gdbarch_register_type (gdbarch, mips_register_type);
5145 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5147 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5149 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5150 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5151 need to all be folded into the target vector. Since they are
5152 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5153 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5155 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5157 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code);
5159 set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay);
5161 /* Virtual tables. */
5162 set_gdbarch_vbit_in_delta (gdbarch, 1);
5164 mips_register_g_packet_guesses (gdbarch);
5166 /* Hook in OS ABI-specific overrides, if they have been registered. */
5167 gdbarch_init_osabi (info, gdbarch);
5169 /* Unwind the frame. */
5170 frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer);
5171 frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer);
5172 frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer);
5173 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
5174 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer);
5175 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
5181 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5183 struct gdbarch_info info;
5185 /* Force the architecture to update, and (if it's a MIPS architecture)
5186 mips_gdbarch_init will take care of the rest. */
5187 gdbarch_info_init (&info);
5188 gdbarch_update_p (info);
5191 /* Print out which MIPS ABI is in use. */
5194 show_mips_abi (struct ui_file *file,
5196 struct cmd_list_element *ignored_cmd,
5197 const char *ignored_value)
5199 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5202 "The MIPS ABI is unknown because the current architecture "
5206 enum mips_abi global_abi = global_mips_abi ();
5207 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5208 const char *actual_abi_str = mips_abi_strings[actual_abi];
5210 if (global_abi == MIPS_ABI_UNKNOWN)
5213 "The MIPS ABI is set automatically (currently \"%s\").\n",
5215 else if (global_abi == actual_abi)
5218 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5222 /* Probably shouldn't happen... */
5225 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5226 actual_abi_str, mips_abi_strings[global_abi]);
5232 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5234 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5238 int ef_mips_32bitmode;
5239 /* Determine the ISA. */
5240 switch (tdep->elf_flags & EF_MIPS_ARCH)
5258 /* Determine the size of a pointer. */
5259 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5260 fprintf_unfiltered (file,
5261 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5263 fprintf_unfiltered (file,
5264 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5266 fprintf_unfiltered (file,
5267 "mips_dump_tdep: ef_mips_arch = %d\n",
5269 fprintf_unfiltered (file,
5270 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5271 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5272 fprintf_unfiltered (file,
5273 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5274 mips_mask_address_p (tdep),
5275 tdep->default_mask_address_p);
5277 fprintf_unfiltered (file,
5278 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5279 MIPS_DEFAULT_FPU_TYPE,
5280 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5281 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5282 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5284 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5285 fprintf_unfiltered (file,
5286 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5288 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5289 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5290 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5292 fprintf_unfiltered (file,
5293 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5294 mips_stack_argsize (current_gdbarch));
5297 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
5300 _initialize_mips_tdep (void)
5302 static struct cmd_list_element *mipsfpulist = NULL;
5303 struct cmd_list_element *c;
5305 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
5306 if (MIPS_ABI_LAST + 1
5307 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
5308 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
5310 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
5312 mips_pdr_data = register_objfile_data ();
5314 /* Add root prefix command for all "set mips"/"show mips" commands */
5315 add_prefix_cmd ("mips", no_class, set_mips_command,
5316 _("Various MIPS specific commands."),
5317 &setmipscmdlist, "set mips ", 0, &setlist);
5319 add_prefix_cmd ("mips", no_class, show_mips_command,
5320 _("Various MIPS specific commands."),
5321 &showmipscmdlist, "show mips ", 0, &showlist);
5323 /* Allow the user to override the saved register size. */
5324 add_setshow_enum_cmd ("saved-gpreg-size", class_obscure,
5325 size_enums, &mips_abi_regsize_string, _("\
5326 Set size of general purpose registers saved on the stack."), _("\
5327 Show size of general purpose registers saved on the stack."), _("\
5328 This option can be set to one of:\n\
5329 32 - Force GDB to treat saved GP registers as 32-bit\n\
5330 64 - Force GDB to treat saved GP registers as 64-bit\n\
5331 auto - Allow GDB to use the target's default setting or autodetect the\n\
5332 saved GP register size from information contained in the\n\
5333 executable (default)."),
5335 NULL, /* FIXME: i18n: Size of general purpose registers saved on the stack is %s. */
5336 &setmipscmdlist, &showmipscmdlist);
5338 /* Allow the user to override the argument stack size. */
5339 add_setshow_enum_cmd ("stack-arg-size", class_obscure,
5340 size_enums, &mips_stack_argsize_string, _("\
5341 Set the amount of stack space reserved for each argument."), _("\
5342 Show the amount of stack space reserved for each argument."), _("\
5343 This option can be set to one of:\n\
5344 32 - Force GDB to allocate 32-bit chunks per argument\n\
5345 64 - Force GDB to allocate 64-bit chunks per argument\n\
5346 auto - Allow GDB to determine the correct setting from the current\n\
5347 target and executable (default)"),
5349 NULL, /* FIXME: i18n: The amount of stack space reserved for each argument is %s. */
5350 &setmipscmdlist, &showmipscmdlist);
5352 /* Allow the user to override the ABI. */
5353 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
5354 &mips_abi_string, _("\
5355 Set the MIPS ABI used by this program."), _("\
5356 Show the MIPS ABI used by this program."), _("\
5357 This option can be set to one of:\n\
5358 auto - the default ABI associated with the current binary\n\
5367 &setmipscmdlist, &showmipscmdlist);
5369 /* Let the user turn off floating point and set the fence post for
5370 heuristic_proc_start. */
5372 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
5373 _("Set use of MIPS floating-point coprocessor."),
5374 &mipsfpulist, "set mipsfpu ", 0, &setlist);
5375 add_cmd ("single", class_support, set_mipsfpu_single_command,
5376 _("Select single-precision MIPS floating-point coprocessor."),
5378 add_cmd ("double", class_support, set_mipsfpu_double_command,
5379 _("Select double-precision MIPS floating-point coprocessor."),
5381 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
5382 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
5383 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
5384 add_cmd ("none", class_support, set_mipsfpu_none_command,
5385 _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
5386 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
5387 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
5388 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
5389 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
5390 _("Select MIPS floating-point coprocessor automatically."),
5392 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
5393 _("Show current use of MIPS floating-point coprocessor target."),
5396 /* We really would like to have both "0" and "unlimited" work, but
5397 command.c doesn't deal with that. So make it a var_zinteger
5398 because the user can always use "999999" or some such for unlimited. */
5399 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support,
5400 &heuristic_fence_post, _("\
5401 Set the distance searched for the start of a function."), _("\
5402 Show the distance searched for the start of a function."), _("\
5403 If you are debugging a stripped executable, GDB needs to search through the\n\
5404 program for the start of a function. This command sets the distance of the\n\
5405 search. The only need to set it is when debugging a stripped executable."),
5406 reinit_frame_cache_sfunc,
5407 NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5408 &setlist, &showlist);
5410 /* Allow the user to control whether the upper bits of 64-bit
5411 addresses should be zeroed. */
5412 add_setshow_auto_boolean_cmd ("mask-address", no_class,
5413 &mask_address_var, _("\
5414 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5415 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5416 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5417 allow GDB to determine the correct value."),
5418 NULL, show_mask_address,
5419 &setmipscmdlist, &showmipscmdlist);
5421 /* Allow the user to control the size of 32 bit registers within the
5422 raw remote packet. */
5423 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
5424 &mips64_transfers_32bit_regs_p, _("\
5425 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5427 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5429 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5430 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5431 64 bits for others. Use \"off\" to disable compatibility mode"),
5432 set_mips64_transfers_32bit_regs,
5433 NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5434 &setlist, &showlist);
5436 /* Debug this files internals. */
5437 add_setshow_zinteger_cmd ("mips", class_maintenance,
5439 Set mips debugging."), _("\
5440 Show mips debugging."), _("\
5441 When non-zero, mips specific debugging is enabled."),
5443 NULL, /* FIXME: i18n: Mips debugging is currently %s. */
5444 &setdebuglist, &showdebuglist);