1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
40 #include "arch-utils.h"
43 #include "mips-tdep.h"
45 #include "reggroups.h"
46 #include "opcode/mips.h"
50 #include "sim-regno.h"
53 static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
54 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
56 /* A useful bit in the CP0 status register (PS_REGNUM). */
57 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
58 #define ST0_FR (1 << 26)
60 /* The sizes of floating point registers. */
64 MIPS_FPU_SINGLE_REGSIZE = 4,
65 MIPS_FPU_DOUBLE_REGSIZE = 8
69 static const char *mips_abi_string;
71 static const char *mips_abi_strings[] = {
82 struct frame_extra_info
84 mips_extra_func_info_t proc_desc;
88 /* Various MIPS ISA options (related to stack analysis) can be
89 overridden dynamically. Establish an enum/array for managing
92 static const char size_auto[] = "auto";
93 static const char size_32[] = "32";
94 static const char size_64[] = "64";
96 static const char *size_enums[] = {
103 /* Some MIPS boards don't support floating point while others only
104 support single-precision floating-point operations. See also
105 FP_REGISTER_DOUBLE. */
109 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
110 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
111 MIPS_FPU_NONE /* No floating point. */
114 #ifndef MIPS_DEFAULT_FPU_TYPE
115 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
117 static int mips_fpu_type_auto = 1;
118 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
120 static int mips_debug = 0;
122 /* MIPS specific per-architecture information */
125 /* from the elf header */
129 enum mips_abi mips_abi;
130 enum mips_abi found_abi;
131 enum mips_fpu_type mips_fpu_type;
132 int mips_last_arg_regnum;
133 int mips_last_fp_arg_regnum;
134 int mips_default_saved_regsize;
135 int mips_fp_register_double;
136 int mips_default_stack_argsize;
137 int default_mask_address_p;
138 /* Is the target using 64-bit raw integer registers but only
139 storing a left-aligned 32-bit value in each? */
140 int mips64_transfers_32bit_regs_p;
143 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
144 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
146 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
148 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
150 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
152 /* Return the currently configured (or set) saved register size. */
154 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
156 static const char *mips_saved_regsize_string = size_auto;
158 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
160 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
161 functions to test, set, or clear bit 0 of addresses. */
164 is_mips16_addr (CORE_ADDR addr)
170 make_mips16_addr (CORE_ADDR addr)
176 unmake_mips16_addr (CORE_ADDR addr)
178 return ((addr) & ~1);
181 /* Return the contents of register REGNUM as a signed integer. */
184 read_signed_register (int regnum)
186 void *buf = alloca (register_size (current_gdbarch, regnum));
187 deprecated_read_register_gen (regnum, buf);
188 return (extract_signed_integer (buf, register_size (current_gdbarch, regnum)));
192 read_signed_register_pid (int regnum, ptid_t ptid)
197 if (ptid_equal (ptid, inferior_ptid))
198 return read_signed_register (regnum);
200 save_ptid = inferior_ptid;
202 inferior_ptid = ptid;
204 retval = read_signed_register (regnum);
206 inferior_ptid = save_ptid;
211 /* Return the MIPS ABI associated with GDBARCH. */
213 mips_abi (struct gdbarch *gdbarch)
215 return gdbarch_tdep (gdbarch)->mips_abi;
219 mips_regsize (struct gdbarch *gdbarch)
221 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
222 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
226 mips_saved_regsize (void)
228 if (mips_saved_regsize_string == size_auto)
229 return MIPS_DEFAULT_SAVED_REGSIZE;
230 else if (mips_saved_regsize_string == size_64)
232 else /* if (mips_saved_regsize_string == size_32) */
236 /* Functions for setting and testing a bit in a minimal symbol that
237 marks it as 16-bit function. The MSB of the minimal symbol's
238 "info" field is used for this purpose.
240 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
241 i.e. refers to a 16-bit function, and sets a "special" bit in a
242 minimal symbol to mark it as a 16-bit function
244 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
247 mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
249 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
251 MSYMBOL_INFO (msym) = (char *)
252 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
253 SYMBOL_VALUE_ADDRESS (msym) |= 1;
258 msymbol_is_special (struct minimal_symbol *msym)
260 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
263 /* XFER a value from the big/little/left end of the register.
264 Depending on the size of the value it might occupy the entire
265 register or just part of it. Make an allowance for this, aligning
266 things accordingly. */
269 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
270 enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
273 bfd_byte reg[MAX_REGISTER_SIZE];
275 gdb_assert (reg_num >= NUM_REGS);
276 /* Need to transfer the left or right part of the register, based on
277 the targets byte order. */
281 reg_offset = register_size (current_gdbarch, reg_num) - length;
283 case BFD_ENDIAN_LITTLE:
286 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
290 internal_error (__FILE__, __LINE__, "bad switch");
293 fprintf_unfiltered (gdb_stderr,
294 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
295 reg_num, reg_offset, buf_offset, length);
296 if (mips_debug && out != NULL)
299 fprintf_unfiltered (gdb_stdlog, "out ");
300 for (i = 0; i < length; i++)
301 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
304 regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
306 regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
307 if (mips_debug && in != NULL)
310 fprintf_unfiltered (gdb_stdlog, "in ");
311 for (i = 0; i < length; i++)
312 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
315 fprintf_unfiltered (gdb_stdlog, "\n");
318 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
319 compatiblity mode. A return value of 1 means that we have
320 physical 64-bit registers, but should treat them as 32-bit registers. */
323 mips2_fp_compat (void)
325 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
327 if (register_size (current_gdbarch, FP0_REGNUM) == 4)
331 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
332 in all the places we deal with FP registers. PR gdb/413. */
333 /* Otherwise check the FR bit in the status register - it controls
334 the FP compatiblity mode. If it is clear we are in compatibility
336 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
343 /* Indicate that the ABI makes use of double-precision registers
344 provided by the FPU (rather than combining pairs of registers to
345 form double-precision values). See also MIPS_FPU_TYPE. */
346 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
348 /* The amount of space reserved on the stack for registers. This is
349 different to MIPS_SAVED_REGSIZE as it determines the alignment of
350 data allocated after the registers have run out. */
352 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
354 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
356 static const char *mips_stack_argsize_string = size_auto;
359 mips_stack_argsize (void)
361 if (mips_stack_argsize_string == size_auto)
362 return MIPS_DEFAULT_STACK_ARGSIZE;
363 else if (mips_stack_argsize_string == size_64)
365 else /* if (mips_stack_argsize_string == size_32) */
369 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
371 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
373 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
374 struct frame_info *, int);
376 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
378 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
380 static int mips_set_processor_type (char *);
382 static void mips_show_processor_type_command (char *, int);
384 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
386 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
387 struct frame_info *next_frame,
390 static CORE_ADDR after_prologue (CORE_ADDR pc,
391 mips_extra_func_info_t proc_desc);
393 static struct type *mips_float_register_type (void);
394 static struct type *mips_double_register_type (void);
396 /* This value is the model of MIPS in use. It is derived from the value
397 of the PrID register. */
399 char *mips_processor_type;
401 char *tmp_mips_processor_type;
403 /* The list of available "set mips " and "show mips " commands */
405 static struct cmd_list_element *setmipscmdlist = NULL;
406 static struct cmd_list_element *showmipscmdlist = NULL;
408 /* A set of original names, to be used when restoring back to generic
409 registers from a specific set. */
410 static char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
412 /* Integer registers 0 thru 31 are handled explicitly by
413 mips_register_name(). Processor specific registers 32 and above
414 are listed in the sets of register names assigned to
415 mips_processor_reg_names. */
416 static char **mips_processor_reg_names = mips_generic_reg_names;
418 /* Return the name of the register corresponding to REGNO. */
420 mips_register_name (int regno)
422 /* GPR names for all ABIs other than n32/n64. */
423 static char *mips_gpr_names[] = {
424 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
425 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
426 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
427 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
430 /* GPR names for n32 and n64 ABIs. */
431 static char *mips_n32_n64_gpr_names[] = {
432 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
433 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
434 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
435 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
438 enum mips_abi abi = mips_abi (current_gdbarch);
440 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
441 don't make the raw register names visible. */
442 int rawnum = regno % NUM_REGS;
443 if (regno < NUM_REGS)
446 /* The MIPS integer registers are always mapped from 0 to 31. The
447 names of the registers (which reflects the conventions regarding
448 register use) vary depending on the ABI. */
449 if (0 <= rawnum && rawnum < 32)
451 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
452 return mips_n32_n64_gpr_names[rawnum];
454 return mips_gpr_names[rawnum];
456 else if (32 <= rawnum && rawnum < NUM_REGS)
457 return mips_processor_reg_names[rawnum - 32];
459 internal_error (__FILE__, __LINE__,
460 "mips_register_name: bad register number %d", rawnum);
464 /* Names of IDT R3041 registers. */
466 char *mips_r3041_reg_names[] = {
467 "sr", "lo", "hi", "bad", "cause","pc",
468 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
469 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
470 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
471 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
472 "fsr", "fir", "",/*"fp"*/ "",
473 "", "", "bus", "ccfg", "", "", "", "",
474 "", "", "port", "cmp", "", "", "epc", "prid",
477 /* Names of IDT R3051 registers. */
479 char *mips_r3051_reg_names[] = {
480 "sr", "lo", "hi", "bad", "cause","pc",
481 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
482 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
483 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
484 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
485 "fsr", "fir", ""/*"fp"*/, "",
486 "inx", "rand", "elo", "", "ctxt", "", "", "",
487 "", "", "ehi", "", "", "", "epc", "prid",
490 /* Names of IDT R3081 registers. */
492 char *mips_r3081_reg_names[] = {
493 "sr", "lo", "hi", "bad", "cause","pc",
494 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
495 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
496 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
497 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
498 "fsr", "fir", ""/*"fp"*/, "",
499 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
500 "", "", "ehi", "", "", "", "epc", "prid",
503 /* Names of LSI 33k registers. */
505 char *mips_lsi33k_reg_names[] = {
506 "epc", "hi", "lo", "sr", "cause","badvaddr",
507 "dcic", "bpc", "bda", "", "", "", "", "",
508 "", "", "", "", "", "", "", "",
509 "", "", "", "", "", "", "", "",
510 "", "", "", "", "", "", "", "",
512 "", "", "", "", "", "", "", "",
513 "", "", "", "", "", "", "", "",
519 } mips_processor_type_table[] = {
520 { "generic", mips_generic_reg_names },
521 { "r3041", mips_r3041_reg_names },
522 { "r3051", mips_r3051_reg_names },
523 { "r3071", mips_r3081_reg_names },
524 { "r3081", mips_r3081_reg_names },
525 { "lsi33k", mips_lsi33k_reg_names },
530 /* Return the groups that a MIPS register can be categorised into. */
533 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
534 struct reggroup *reggroup)
539 int rawnum = regnum % NUM_REGS;
540 int pseudo = regnum / NUM_REGS;
541 if (reggroup == all_reggroup)
543 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
544 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
545 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
546 (gdbarch), as not all architectures are multi-arch. */
547 raw_p = rawnum < NUM_REGS;
548 if (REGISTER_NAME (regnum) == NULL
549 || REGISTER_NAME (regnum)[0] == '\0')
551 if (reggroup == float_reggroup)
552 return float_p && pseudo;
553 if (reggroup == vector_reggroup)
554 return vector_p && pseudo;
555 if (reggroup == general_reggroup)
556 return (!vector_p && !float_p) && pseudo;
557 /* Save the pseudo registers. Need to make certain that any code
558 extracting register values from a saved register cache also uses
560 if (reggroup == save_reggroup)
561 return raw_p && pseudo;
562 /* Restore the same pseudo register. */
563 if (reggroup == restore_reggroup)
564 return raw_p && pseudo;
568 /* Map the symbol table registers which live in the range [1 *
569 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
573 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
574 int cookednum, void *buf)
576 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
577 return regcache_raw_read (regcache, cookednum % NUM_REGS, buf);
581 mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
582 int cookednum, const void *buf)
584 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
585 return regcache_raw_write (regcache, cookednum % NUM_REGS, buf);
588 /* Table to translate MIPS16 register field to actual register number. */
589 static int mips16_to_32_reg[8] =
590 {16, 17, 2, 3, 4, 5, 6, 7};
592 /* Heuristic_proc_start may hunt through the text section for a long
593 time across a 2400 baud serial line. Allows the user to limit this
596 static unsigned int heuristic_fence_post = 0;
598 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
599 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
600 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
601 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
602 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
603 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
604 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
605 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
606 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
607 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
608 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
609 this will corrupt pdr.iline. Fortunately we don't use it. */
610 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
611 #define _PROC_MAGIC_ 0x0F0F0F0F
612 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
613 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
615 struct linked_proc_info
617 struct mips_extra_func_info info;
618 struct linked_proc_info *next;
620 *linked_proc_desc_table = NULL;
622 /* Number of bytes of storage in the actual machine representation for
623 register N. NOTE: This defines the pseudo register type so need to
624 rebuild the architecture vector. */
626 static int mips64_transfers_32bit_regs_p = 0;
629 set_mips64_transfers_32bit_regs (char *args, int from_tty,
630 struct cmd_list_element *c)
632 struct gdbarch_info info;
633 gdbarch_info_init (&info);
634 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
635 instead of relying on globals. Doing that would let generic code
636 handle the search for this specific architecture. */
637 if (!gdbarch_update_p (info))
639 mips64_transfers_32bit_regs_p = 0;
640 error ("32-bit compatibility mode not supported");
644 /* Convert between RAW and VIRTUAL registers. The RAW register size
645 defines the remote-gdb packet. */
648 mips_register_convertible (int reg_nr)
650 if (gdbarch_tdep (current_gdbarch)->mips64_transfers_32bit_regs_p)
653 return (register_size (current_gdbarch, reg_nr) > register_size (current_gdbarch, reg_nr));
657 mips_register_convert_to_virtual (int n, struct type *virtual_type,
658 char *raw_buf, char *virt_buf)
660 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
662 raw_buf + (register_size (current_gdbarch, n) - TYPE_LENGTH (virtual_type)),
663 TYPE_LENGTH (virtual_type));
667 TYPE_LENGTH (virtual_type));
671 mips_register_convert_to_raw (struct type *virtual_type, int n,
672 const char *virt_buf, char *raw_buf)
674 memset (raw_buf, 0, register_size (current_gdbarch, n));
675 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
676 memcpy (raw_buf + (register_size (current_gdbarch, n) - TYPE_LENGTH (virtual_type)),
678 TYPE_LENGTH (virtual_type));
682 TYPE_LENGTH (virtual_type));
686 mips_convert_register_p (int regnum, struct type *type)
688 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
689 && register_size (current_gdbarch, regnum) == 4
690 && (regnum) >= FP0_REGNUM && (regnum) < FP0_REGNUM + 32
691 && TYPE_CODE(type) == TYPE_CODE_FLT
692 && TYPE_LENGTH(type) == 8);
696 mips_register_to_value (struct frame_info *frame, int regnum,
697 struct type *type, void *to)
699 get_frame_register (frame, regnum + 0, (char *) to + 4);
700 get_frame_register (frame, regnum + 1, (char *) to + 0);
704 mips_value_to_register (struct frame_info *frame, int regnum,
705 struct type *type, const void *from)
707 put_frame_register (frame, regnum + 0, (const char *) from + 4);
708 put_frame_register (frame, regnum + 1, (const char *) from + 0);
711 /* Return the GDB type object for the "standard" data type of data in
715 mips_register_type (struct gdbarch *gdbarch, int regnum)
717 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
718 if ((regnum % NUM_REGS) >= FP0_REGNUM
719 && (regnum % NUM_REGS) < FP0_REGNUM + 32)
721 /* The floating-point registers raw, or cooked, always match
722 mips_regsize(), and also map 1:1, byte for byte. */
723 switch (gdbarch_byte_order (gdbarch))
726 if (mips_regsize (gdbarch) == 4)
727 return builtin_type_ieee_single_big;
729 return builtin_type_ieee_double_big;
730 case BFD_ENDIAN_LITTLE:
731 if (mips_regsize (gdbarch) == 4)
732 return builtin_type_ieee_single_little;
734 return builtin_type_ieee_double_little;
735 case BFD_ENDIAN_UNKNOWN:
737 internal_error (__FILE__, __LINE__, "bad switch");
740 else if (regnum >= (NUM_REGS + FCRCS_REGNUM)
741 && regnum <= NUM_REGS + LAST_EMBED_REGNUM)
742 /* The pseudo/cooked view of the embedded registers is always
743 32-bit. The raw view is handled below. */
744 return builtin_type_int32;
745 else if (regnum >= NUM_REGS && mips_regsize (gdbarch)
746 && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
747 /* The target, while using a 64-bit register buffer, is only
748 transfering 32-bits of each integer register. Reflect this in
749 the cooked/pseudo register value. */
750 return builtin_type_int32;
751 else if (mips_regsize (gdbarch) == 8)
753 return builtin_type_int64;
756 return builtin_type_int32;
759 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
764 return read_signed_register (SP_REGNUM);
767 /* Should the upper word of 64-bit addresses be zeroed? */
768 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
771 mips_mask_address_p (void)
773 switch (mask_address_var)
775 case AUTO_BOOLEAN_TRUE:
777 case AUTO_BOOLEAN_FALSE:
780 case AUTO_BOOLEAN_AUTO:
781 return MIPS_DEFAULT_MASK_ADDRESS_P;
783 internal_error (__FILE__, __LINE__,
784 "mips_mask_address_p: bad switch");
790 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
792 switch (mask_address_var)
794 case AUTO_BOOLEAN_TRUE:
795 printf_filtered ("The 32 bit mips address mask is enabled\n");
797 case AUTO_BOOLEAN_FALSE:
798 printf_filtered ("The 32 bit mips address mask is disabled\n");
800 case AUTO_BOOLEAN_AUTO:
801 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
802 mips_mask_address_p () ? "enabled" : "disabled");
805 internal_error (__FILE__, __LINE__,
806 "show_mask_address: bad switch");
811 /* Should call_function allocate stack space for a struct return? */
814 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
816 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
820 mips_n32n64_use_struct_convention (int gcc_p, struct type *type)
822 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
825 /* Should call_function pass struct by reference?
826 For each architecture, structs are passed either by
827 value or by reference, depending on their size. */
830 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
832 enum type_code typecode = TYPE_CODE (check_typedef (type));
833 int len = TYPE_LENGTH (check_typedef (type));
835 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
836 return (len > MIPS_SAVED_REGSIZE);
842 mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type)
844 return 0; /* Assumption: N32/N64 never passes struct by ref. */
848 mips_o32_reg_struct_has_addr (int gcc_p, struct type *type)
850 return 0; /* Assumption: O32/O64 never passes struct by ref. */
853 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
856 pc_is_mips16 (bfd_vma memaddr)
858 struct minimal_symbol *sym;
860 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
861 if (is_mips16_addr (memaddr))
864 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
865 the high bit of the info field. Use this to decide if the function is
866 MIPS16 or normal MIPS. */
867 sym = lookup_minimal_symbol_by_pc (memaddr);
869 return msymbol_is_special (sym);
874 /* MIPS believes that the PC has a sign extended value. Perhaphs the
875 all registers should be sign extended for simplicity? */
878 mips_read_pc (ptid_t ptid)
880 return read_signed_register_pid (PC_REGNUM, ptid);
883 /* This returns the PC of the first inst after the prologue. If we can't
884 find the prologue, then return 0. */
887 after_prologue (CORE_ADDR pc,
888 mips_extra_func_info_t proc_desc)
890 struct symtab_and_line sal;
891 CORE_ADDR func_addr, func_end;
893 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
894 to read the stack pointer from the current machine state, because
895 the current machine state has nothing to do with the information
896 we need from the proc_desc; and the process may or may not exist
899 proc_desc = find_proc_desc (pc, NULL, 0);
903 /* If function is frameless, then we need to do it the hard way. I
904 strongly suspect that frameless always means prologueless... */
905 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
906 && PROC_FRAME_OFFSET (proc_desc) == 0)
910 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
911 return 0; /* Unknown */
913 sal = find_pc_line (func_addr, 0);
915 if (sal.end < func_end)
918 /* The line after the prologue is after the end of the function. In this
919 case, tell the caller to find the prologue the hard way. */
924 /* Decode a MIPS32 instruction that saves a register in the stack, and
925 set the appropriate bit in the general register mask or float register mask
926 to indicate which register is saved. This is a helper function
927 for mips_find_saved_regs. */
930 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
931 unsigned long *float_mask)
935 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
936 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
937 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
939 /* It might be possible to use the instruction to
940 find the offset, rather than the code below which
941 is based on things being in a certain order in the
942 frame, but figuring out what the instruction's offset
943 is relative to might be a little tricky. */
944 reg = (inst & 0x001f0000) >> 16;
945 *gen_mask |= (1 << reg);
947 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
948 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
949 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
952 reg = ((inst & 0x001f0000) >> 16);
953 *float_mask |= (1 << reg);
957 /* Decode a MIPS16 instruction that saves a register in the stack, and
958 set the appropriate bit in the general register or float register mask
959 to indicate which register is saved. This is a helper function
960 for mips_find_saved_regs. */
963 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
965 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
967 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
968 *gen_mask |= (1 << reg);
970 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
972 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
973 *gen_mask |= (1 << reg);
975 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
976 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
977 *gen_mask |= (1 << RA_REGNUM);
981 /* Fetch and return instruction from the specified location. If the PC
982 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
985 mips_fetch_instruction (CORE_ADDR addr)
987 char buf[MIPS_INSTLEN];
991 if (pc_is_mips16 (addr))
993 instlen = MIPS16_INSTLEN;
994 addr = unmake_mips16_addr (addr);
997 instlen = MIPS_INSTLEN;
998 status = read_memory_nobpt (addr, buf, instlen);
1000 memory_error (status, addr);
1001 return extract_unsigned_integer (buf, instlen);
1005 /* These the fields of 32 bit mips instructions */
1006 #define mips32_op(x) (x >> 26)
1007 #define itype_op(x) (x >> 26)
1008 #define itype_rs(x) ((x >> 21) & 0x1f)
1009 #define itype_rt(x) ((x >> 16) & 0x1f)
1010 #define itype_immediate(x) (x & 0xffff)
1012 #define jtype_op(x) (x >> 26)
1013 #define jtype_target(x) (x & 0x03ffffff)
1015 #define rtype_op(x) (x >> 26)
1016 #define rtype_rs(x) ((x >> 21) & 0x1f)
1017 #define rtype_rt(x) ((x >> 16) & 0x1f)
1018 #define rtype_rd(x) ((x >> 11) & 0x1f)
1019 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1020 #define rtype_funct(x) (x & 0x3f)
1023 mips32_relative_offset (unsigned long inst)
1026 x = itype_immediate (inst);
1027 if (x & 0x8000) /* sign bit set */
1029 x |= 0xffff0000; /* sign extension */
1035 /* Determine whate to set a single step breakpoint while considering
1036 branch prediction */
1038 mips32_next_pc (CORE_ADDR pc)
1042 inst = mips_fetch_instruction (pc);
1043 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1045 if (itype_op (inst) >> 2 == 5)
1046 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1048 op = (itype_op (inst) & 0x03);
1058 goto greater_branch;
1063 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1064 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1066 int tf = itype_rt (inst) & 0x01;
1067 int cnum = itype_rt (inst) >> 2;
1068 int fcrcs = read_signed_register (FCRCS_REGNUM);
1069 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1071 if (((cond >> cnum) & 0x01) == tf)
1072 pc += mips32_relative_offset (inst) + 4;
1077 pc += 4; /* Not a branch, next instruction is easy */
1080 { /* This gets way messy */
1082 /* Further subdivide into SPECIAL, REGIMM and other */
1083 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1085 case 0: /* SPECIAL */
1086 op = rtype_funct (inst);
1091 /* Set PC to that address */
1092 pc = read_signed_register (rtype_rs (inst));
1098 break; /* end SPECIAL */
1099 case 1: /* REGIMM */
1101 op = itype_rt (inst); /* branch condition */
1106 case 16: /* BLTZAL */
1107 case 18: /* BLTZALL */
1109 if (read_signed_register (itype_rs (inst)) < 0)
1110 pc += mips32_relative_offset (inst) + 4;
1112 pc += 8; /* after the delay slot */
1116 case 17: /* BGEZAL */
1117 case 19: /* BGEZALL */
1118 greater_equal_branch:
1119 if (read_signed_register (itype_rs (inst)) >= 0)
1120 pc += mips32_relative_offset (inst) + 4;
1122 pc += 8; /* after the delay slot */
1124 /* All of the other instructions in the REGIMM category */
1129 break; /* end REGIMM */
1134 reg = jtype_target (inst) << 2;
1135 /* Upper four bits get never changed... */
1136 pc = reg + ((pc + 4) & 0xf0000000);
1139 /* FIXME case JALX : */
1142 reg = jtype_target (inst) << 2;
1143 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1144 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1146 break; /* The new PC will be alternate mode */
1147 case 4: /* BEQ, BEQL */
1149 if (read_signed_register (itype_rs (inst)) ==
1150 read_signed_register (itype_rt (inst)))
1151 pc += mips32_relative_offset (inst) + 4;
1155 case 5: /* BNE, BNEL */
1157 if (read_signed_register (itype_rs (inst)) !=
1158 read_signed_register (itype_rt (inst)))
1159 pc += mips32_relative_offset (inst) + 4;
1163 case 6: /* BLEZ, BLEZL */
1165 if (read_signed_register (itype_rs (inst) <= 0))
1166 pc += mips32_relative_offset (inst) + 4;
1172 greater_branch: /* BGTZ, BGTZL */
1173 if (read_signed_register (itype_rs (inst) > 0))
1174 pc += mips32_relative_offset (inst) + 4;
1181 } /* mips32_next_pc */
1183 /* Decoding the next place to set a breakpoint is irregular for the
1184 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1185 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1186 We dont want to set a single step instruction on the extend instruction
1190 /* Lots of mips16 instruction formats */
1191 /* Predicting jumps requires itype,ritype,i8type
1192 and their extensions extItype,extritype,extI8type
1194 enum mips16_inst_fmts
1196 itype, /* 0 immediate 5,10 */
1197 ritype, /* 1 5,3,8 */
1198 rrtype, /* 2 5,3,3,5 */
1199 rritype, /* 3 5,3,3,5 */
1200 rrrtype, /* 4 5,3,3,3,2 */
1201 rriatype, /* 5 5,3,3,1,4 */
1202 shifttype, /* 6 5,3,3,3,2 */
1203 i8type, /* 7 5,3,8 */
1204 i8movtype, /* 8 5,3,3,5 */
1205 i8mov32rtype, /* 9 5,3,5,3 */
1206 i64type, /* 10 5,3,8 */
1207 ri64type, /* 11 5,3,3,5 */
1208 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1209 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1210 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1211 extRRItype, /* 15 5,5,5,5,3,3,5 */
1212 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1213 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1214 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1215 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1216 extRi64type, /* 20 5,6,5,5,3,3,5 */
1217 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1219 /* I am heaping all the fields of the formats into one structure and
1220 then, only the fields which are involved in instruction extension */
1224 unsigned int regx; /* Function in i8 type */
1229 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1230 for the bits which make up the immediatate extension. */
1233 extended_offset (unsigned int extension)
1236 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1238 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1240 value |= extension & 0x01f; /* extract 4:0 */
1244 /* Only call this function if you know that this is an extendable
1245 instruction, It wont malfunction, but why make excess remote memory references?
1246 If the immediate operands get sign extended or somthing, do it after
1247 the extension is performed.
1249 /* FIXME: Every one of these cases needs to worry about sign extension
1250 when the offset is to be used in relative addressing */
1254 fetch_mips_16 (CORE_ADDR pc)
1257 pc &= 0xfffffffe; /* clear the low order bit */
1258 target_read_memory (pc, buf, 2);
1259 return extract_unsigned_integer (buf, 2);
1263 unpack_mips16 (CORE_ADDR pc,
1264 unsigned int extension,
1266 enum mips16_inst_fmts insn_format,
1267 struct upk_mips16 *upk)
1272 switch (insn_format)
1279 value = extended_offset (extension);
1280 value = value << 11; /* rom for the original value */
1281 value |= inst & 0x7ff; /* eleven bits from instruction */
1285 value = inst & 0x7ff;
1286 /* FIXME : Consider sign extension */
1295 { /* A register identifier and an offset */
1296 /* Most of the fields are the same as I type but the
1297 immediate value is of a different length */
1301 value = extended_offset (extension);
1302 value = value << 8; /* from the original instruction */
1303 value |= inst & 0xff; /* eleven bits from instruction */
1304 regx = (extension >> 8) & 0x07; /* or i8 funct */
1305 if (value & 0x4000) /* test the sign bit , bit 26 */
1307 value &= ~0x3fff; /* remove the sign bit */
1313 value = inst & 0xff; /* 8 bits */
1314 regx = (inst >> 8) & 0x07; /* or i8 funct */
1315 /* FIXME: Do sign extension , this format needs it */
1316 if (value & 0x80) /* THIS CONFUSES ME */
1318 value &= 0xef; /* remove the sign bit */
1328 unsigned long value;
1329 unsigned int nexthalf;
1330 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1331 value = value << 16;
1332 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1340 internal_error (__FILE__, __LINE__,
1343 upk->offset = offset;
1350 add_offset_16 (CORE_ADDR pc, int offset)
1352 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1356 extended_mips16_next_pc (CORE_ADDR pc,
1357 unsigned int extension,
1360 int op = (insn >> 11);
1363 case 2: /* Branch */
1366 struct upk_mips16 upk;
1367 unpack_mips16 (pc, extension, insn, itype, &upk);
1368 offset = upk.offset;
1374 pc += (offset << 1) + 2;
1377 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1379 struct upk_mips16 upk;
1380 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1381 pc = add_offset_16 (pc, upk.offset);
1382 if ((insn >> 10) & 0x01) /* Exchange mode */
1383 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1390 struct upk_mips16 upk;
1392 unpack_mips16 (pc, extension, insn, ritype, &upk);
1393 reg = read_signed_register (upk.regx);
1395 pc += (upk.offset << 1) + 2;
1402 struct upk_mips16 upk;
1404 unpack_mips16 (pc, extension, insn, ritype, &upk);
1405 reg = read_signed_register (upk.regx);
1407 pc += (upk.offset << 1) + 2;
1412 case 12: /* I8 Formats btez btnez */
1414 struct upk_mips16 upk;
1416 unpack_mips16 (pc, extension, insn, i8type, &upk);
1417 /* upk.regx contains the opcode */
1418 reg = read_signed_register (24); /* Test register is 24 */
1419 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1420 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1421 /* pc = add_offset_16(pc,upk.offset) ; */
1422 pc += (upk.offset << 1) + 2;
1427 case 29: /* RR Formats JR, JALR, JALR-RA */
1429 struct upk_mips16 upk;
1430 /* upk.fmt = rrtype; */
1435 upk.regx = (insn >> 8) & 0x07;
1436 upk.regy = (insn >> 5) & 0x07;
1444 break; /* Function return instruction */
1450 break; /* BOGUS Guess */
1452 pc = read_signed_register (reg);
1459 /* This is an instruction extension. Fetch the real instruction
1460 (which follows the extension) and decode things based on
1464 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1477 mips16_next_pc (CORE_ADDR pc)
1479 unsigned int insn = fetch_mips_16 (pc);
1480 return extended_mips16_next_pc (pc, 0, insn);
1483 /* The mips_next_pc function supports single_step when the remote
1484 target monitor or stub is not developed enough to do a single_step.
1485 It works by decoding the current instruction and predicting where a
1486 branch will go. This isnt hard because all the data is available.
1487 The MIPS32 and MIPS16 variants are quite different */
1489 mips_next_pc (CORE_ADDR pc)
1492 return mips16_next_pc (pc);
1494 return mips32_next_pc (pc);
1497 /* Set up the 'saved_regs' array. This is a data structure containing
1498 the addresses on the stack where each register has been saved, for
1499 each stack frame. Registers that have not been saved will have
1500 zero here. The stack pointer register is special: rather than the
1501 address where the stack register has been saved,
1502 saved_regs[SP_REGNUM] will have the actual value of the previous
1503 frame's stack register. */
1506 mips_find_saved_regs (struct frame_info *fci)
1509 /* r0 bit means kernel trap */
1511 /* What registers have been saved? Bitmasks. */
1512 unsigned long gen_mask, float_mask;
1513 mips_extra_func_info_t proc_desc;
1515 CORE_ADDR *saved_regs;
1517 if (deprecated_get_frame_saved_regs (fci) != NULL)
1519 saved_regs = frame_saved_regs_zalloc (fci);
1521 /* If it is the frame for sigtramp, the saved registers are located
1522 in a sigcontext structure somewhere on the stack. If the stack
1523 layout for sigtramp changes we might have to change these
1524 constants and the companion fixup_sigtramp in mdebugread.c */
1525 #ifndef SIGFRAME_BASE
1526 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1527 above the sigtramp frame. */
1528 #define SIGFRAME_BASE mips_regsize (current_gdbarch)
1529 /* FIXME! Are these correct?? */
1530 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * mips_regsize (current_gdbarch))
1531 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * mips_regsize (current_gdbarch))
1532 #define SIGFRAME_FPREGSAVE_OFF \
1533 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * mips_regsize (current_gdbarch) + 3 * mips_regsize (current_gdbarch))
1535 #ifndef SIGFRAME_REG_SIZE
1536 /* FIXME! Is this correct?? */
1537 #define SIGFRAME_REG_SIZE mips_regsize (current_gdbarch)
1539 if ((get_frame_type (fci) == SIGTRAMP_FRAME))
1541 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1543 CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF
1544 + ireg * SIGFRAME_REG_SIZE);
1545 set_reg_offset (saved_regs, ireg, reg_position);
1547 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1549 CORE_ADDR reg_position = (get_frame_base (fci)
1550 + SIGFRAME_FPREGSAVE_OFF
1551 + ireg * SIGFRAME_REG_SIZE);
1552 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
1555 set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF);
1556 /* SP_REGNUM, contains the value and not the address. */
1557 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
1561 proc_desc = get_frame_extra_info (fci)->proc_desc;
1562 if (proc_desc == NULL)
1563 /* I'm not sure how/whether this can happen. Normally when we
1564 can't find a proc_desc, we "synthesize" one using
1565 heuristic_proc_desc and set the saved_regs right away. */
1568 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1569 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1570 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1572 if (/* In any frame other than the innermost or a frame interrupted
1573 by a signal, we assume that all registers have been saved.
1574 This assumes that all register saves in a function happen
1575 before the first function call. */
1576 (get_next_frame (fci) == NULL
1577 || (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME))
1579 /* In a dummy frame we know exactly where things are saved. */
1580 && !PROC_DESC_IS_DUMMY (proc_desc)
1582 /* Don't bother unless we are inside a function prologue.
1583 Outside the prologue, we know where everything is. */
1585 && in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc))
1587 /* Not sure exactly what kernel_trap means, but if it means the
1588 kernel saves the registers without a prologue doing it, we
1589 better not examine the prologue to see whether registers
1590 have been saved yet. */
1593 /* We need to figure out whether the registers that the
1594 proc_desc claims are saved have been saved yet. */
1598 /* Bitmasks; set if we have found a save for the register. */
1599 unsigned long gen_save_found = 0;
1600 unsigned long float_save_found = 0;
1603 /* If the address is odd, assume this is MIPS16 code. */
1604 addr = PROC_LOW_ADDR (proc_desc);
1605 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1607 /* Scan through this function's instructions preceding the
1608 current PC, and look for those that save registers. */
1609 while (addr < get_frame_pc (fci))
1611 inst = mips_fetch_instruction (addr);
1612 if (pc_is_mips16 (addr))
1613 mips16_decode_reg_save (inst, &gen_save_found);
1615 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1618 gen_mask = gen_save_found;
1619 float_mask = float_save_found;
1622 /* Fill in the offsets for the registers which gen_mask says were
1625 CORE_ADDR reg_position = (get_frame_base (fci)
1626 + PROC_REG_OFFSET (proc_desc));
1627 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1628 if (gen_mask & 0x80000000)
1630 set_reg_offset (saved_regs, ireg, reg_position);
1631 reg_position -= MIPS_SAVED_REGSIZE;
1635 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1636 order of that normally used by gcc. Therefore, we have to fetch
1637 the first instruction of the function, and if it's an entry
1638 instruction that saves $s0 or $s1, correct their saved addresses. */
1639 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1641 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1642 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1646 int sreg_count = (inst >> 6) & 3;
1648 /* Check if the ra register was pushed on the stack. */
1649 CORE_ADDR reg_position = (get_frame_base (fci)
1650 + PROC_REG_OFFSET (proc_desc));
1652 reg_position -= MIPS_SAVED_REGSIZE;
1654 /* Check if the s0 and s1 registers were pushed on the
1656 for (reg = 16; reg < sreg_count + 16; reg++)
1658 set_reg_offset (saved_regs, reg, reg_position);
1659 reg_position -= MIPS_SAVED_REGSIZE;
1664 /* Fill in the offsets for the registers which float_mask says were
1667 CORE_ADDR reg_position = (get_frame_base (fci)
1668 + PROC_FREG_OFFSET (proc_desc));
1670 /* Fill in the offsets for the float registers which float_mask
1672 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1673 if (float_mask & 0x80000000)
1675 if (MIPS_SAVED_REGSIZE == 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1677 /* On a big endian 32 bit ABI, floating point registers
1678 are paired to form doubles such that the most
1679 significant part is in $f[N+1] and the least
1680 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1681 registers are also spilled as a pair and stored as a
1684 When little-endian the least significant part is
1685 stored first leading to the memory order $f[N] and
1688 Unfortunately, when big-endian the most significant
1689 part of the double is stored first, and the least
1690 significant is stored second. This leads to the
1691 registers being ordered in memory as firt $f[N+1] and
1694 For the big-endian case make certain that the
1695 addresses point at the correct (swapped) locations
1696 $f[N] and $f[N+1] pair (keep in mind that
1697 reg_position is decremented each time through the
1700 set_reg_offset (saved_regs, FP0_REGNUM + ireg,
1701 reg_position - MIPS_SAVED_REGSIZE);
1703 set_reg_offset (saved_regs, FP0_REGNUM + ireg,
1704 reg_position + MIPS_SAVED_REGSIZE);
1707 set_reg_offset (saved_regs, FP0_REGNUM + ireg, reg_position);
1708 reg_position -= MIPS_SAVED_REGSIZE;
1711 set_reg_offset (saved_regs, PC_REGNUM, saved_regs[RA_REGNUM]);
1714 /* SP_REGNUM, contains the value and not the address. */
1715 set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
1719 read_next_frame_reg (struct frame_info *fi, int regno)
1721 /* Always a pseudo. */
1722 gdb_assert (regno >= NUM_REGS);
1726 regcache_cooked_read_signed (current_regcache, regno, &val);
1729 else if ((regno % NUM_REGS) == SP_REGNUM)
1730 /* The SP_REGNUM is special, its value is stored in saved_regs.
1731 In fact, it is so special that it can even only be fetched
1732 using a raw register number! Once this code as been converted
1733 to frame-unwind the problem goes away. */
1734 return frame_unwind_register_signed (fi, regno % NUM_REGS);
1736 return frame_unwind_register_signed (fi, regno);
1740 /* mips_addr_bits_remove - remove useless address bits */
1743 mips_addr_bits_remove (CORE_ADDR addr)
1745 if (mips_mask_address_p ()
1746 && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
1747 /* This hack is a work-around for existing boards using PMON, the
1748 simulator, and any other 64-bit targets that doesn't have true
1749 64-bit addressing. On these targets, the upper 32 bits of
1750 addresses are ignored by the hardware. Thus, the PC or SP are
1751 likely to have been sign extended to all 1s by instruction
1752 sequences that load 32-bit addresses. For example, a typical
1753 piece of code that loads an address is this:
1755 lui $r2, <upper 16 bits>
1756 ori $r2, <lower 16 bits>
1758 But the lui sign-extends the value such that the upper 32 bits
1759 may be all 1s. The workaround is simply to mask off these
1760 bits. In the future, gcc may be changed to support true 64-bit
1761 addressing, and this masking will have to be disabled. */
1762 return addr &= 0xffffffffUL;
1767 /* mips_software_single_step() is called just before we want to resume
1768 the inferior, if we want to single-step it but there is no hardware
1769 or kernel single-step support (MIPS on GNU/Linux for example). We find
1770 the target of the coming instruction and breakpoint it.
1772 single_step is also called just after the inferior stops. If we had
1773 set up a simulated single-step, we undo our damage. */
1776 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1778 static CORE_ADDR next_pc;
1779 typedef char binsn_quantum[BREAKPOINT_MAX];
1780 static binsn_quantum break_mem;
1783 if (insert_breakpoints_p)
1785 pc = read_register (PC_REGNUM);
1786 next_pc = mips_next_pc (pc);
1788 target_insert_breakpoint (next_pc, break_mem);
1791 target_remove_breakpoint (next_pc, break_mem);
1795 mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
1800 ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
1801 : get_next_frame (prev)
1802 ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
1804 tmp = SKIP_TRAMPOLINE_CODE (pc);
1805 return tmp ? tmp : pc;
1810 mips_frame_saved_pc (struct frame_info *frame)
1814 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
1817 /* Always unwind the cooked PC register value. */
1818 frame_unwind_signed_register (frame, NUM_REGS + PC_REGNUM, &tmp);
1823 mips_extra_func_info_t proc_desc
1824 = get_frame_extra_info (frame)->proc_desc;
1825 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
1826 saved_pc = read_memory_integer (get_frame_base (frame) - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
1829 /* We have to get the saved pc from the sigcontext if it is
1830 a signal handler frame. */
1831 int pcreg = (get_frame_type (frame) == SIGTRAMP_FRAME ? PC_REGNUM
1832 : proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
1833 saved_pc = read_next_frame_reg (frame, NUM_REGS + pcreg);
1836 return ADDR_BITS_REMOVE (saved_pc);
1839 static struct mips_extra_func_info temp_proc_desc;
1841 /* This hack will go away once the get_prev_frame() code has been
1842 modified to set the frame's type first. That is BEFORE init extra
1843 frame info et.al. is called. This is because it will become
1844 possible to skip the init extra info call for sigtramp and dummy
1846 static CORE_ADDR *temp_saved_regs;
1848 /* Set a register's saved stack address in temp_saved_regs. If an
1849 address has already been set for this register, do nothing; this
1850 way we will only recognize the first save of a given register in a
1853 For simplicity, save the address in both [0 .. NUM_REGS) and
1854 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1855 is used as it is only second range (the ABI instead of ISA
1856 registers) that comes into play when finding saved registers in a
1860 set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
1862 if (saved_regs[regno] == 0)
1864 saved_regs[regno + 0 * NUM_REGS] = offset;
1865 saved_regs[regno + 1 * NUM_REGS] = offset;
1870 /* Test whether the PC points to the return instruction at the
1871 end of a function. */
1874 mips_about_to_return (CORE_ADDR pc)
1876 if (pc_is_mips16 (pc))
1877 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1878 generates a "jr $ra"; other times it generates code to load
1879 the return address from the stack to an accessible register (such
1880 as $a3), then a "jr" using that register. This second case
1881 is almost impossible to distinguish from an indirect jump
1882 used for switch statements, so we don't even try. */
1883 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1885 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1889 /* This fencepost looks highly suspicious to me. Removing it also
1890 seems suspicious as it could affect remote debugging across serial
1894 heuristic_proc_start (CORE_ADDR pc)
1901 pc = ADDR_BITS_REMOVE (pc);
1903 fence = start_pc - heuristic_fence_post;
1907 if (heuristic_fence_post == UINT_MAX
1908 || fence < VM_MIN_ADDRESS)
1909 fence = VM_MIN_ADDRESS;
1911 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1913 /* search back for previous return */
1914 for (start_pc -= instlen;; start_pc -= instlen)
1915 if (start_pc < fence)
1917 /* It's not clear to me why we reach this point when
1918 stop_soon, but with this test, at least we
1919 don't print out warnings for every child forked (eg, on
1920 decstation). 22apr93 rich@cygnus.com. */
1921 if (stop_soon == NO_STOP_QUIETLY)
1923 static int blurb_printed = 0;
1925 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1930 /* This actually happens frequently in embedded
1931 development, when you first connect to a board
1932 and your stack pointer and pc are nowhere in
1933 particular. This message needs to give people
1934 in that situation enough information to
1935 determine that it's no big deal. */
1936 printf_filtered ("\n\
1937 GDB is unable to find the start of the function at 0x%s\n\
1938 and thus can't determine the size of that function's stack frame.\n\
1939 This means that GDB may be unable to access that stack frame, or\n\
1940 the frames below it.\n\
1941 This problem is most likely caused by an invalid program counter or\n\
1943 However, if you think GDB should simply search farther back\n\
1944 from 0x%s for code which looks like the beginning of a\n\
1945 function, you can increase the range of the search using the `set\n\
1946 heuristic-fence-post' command.\n",
1947 paddr_nz (pc), paddr_nz (pc));
1954 else if (pc_is_mips16 (start_pc))
1956 unsigned short inst;
1958 /* On MIPS16, any one of the following is likely to be the
1959 start of a function:
1963 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1964 inst = mips_fetch_instruction (start_pc);
1965 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1966 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1967 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1968 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1970 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1971 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1976 else if (mips_about_to_return (start_pc))
1978 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1985 /* Fetch the immediate value from a MIPS16 instruction.
1986 If the previous instruction was an EXTEND, use it to extend
1987 the upper bits of the immediate value. This is a helper function
1988 for mips16_heuristic_proc_desc. */
1991 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1992 unsigned short inst, /* current instruction */
1993 int nbits, /* number of bits in imm field */
1994 int scale, /* scale factor to be applied to imm */
1995 int is_signed) /* is the imm field signed? */
1999 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2001 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
2002 if (offset & 0x8000) /* check for negative extend */
2003 offset = 0 - (0x10000 - (offset & 0xffff));
2004 return offset | (inst & 0x1f);
2008 int max_imm = 1 << nbits;
2009 int mask = max_imm - 1;
2010 int sign_bit = max_imm >> 1;
2012 offset = inst & mask;
2013 if (is_signed && (offset & sign_bit))
2014 offset = 0 - (max_imm - offset);
2015 return offset * scale;
2020 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2021 stream from start_pc to limit_pc. */
2024 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2025 struct frame_info *next_frame, CORE_ADDR sp)
2028 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
2029 unsigned short prev_inst = 0; /* saved copy of previous instruction */
2030 unsigned inst = 0; /* current instruction */
2031 unsigned entry_inst = 0; /* the entry instruction */
2034 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
2035 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2037 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
2039 /* Save the previous instruction. If it's an EXTEND, we'll extract
2040 the immediate offset extension from it in mips16_get_imm. */
2043 /* Fetch and decode the instruction. */
2044 inst = (unsigned short) mips_fetch_instruction (cur_pc);
2045 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2046 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2048 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2049 if (offset < 0) /* negative stack adjustment? */
2050 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
2052 /* Exit loop if a positive stack adjustment is found, which
2053 usually means that the stack cleanup code in the function
2054 epilogue is reached. */
2057 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2059 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2060 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
2061 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2062 set_reg_offset (temp_saved_regs, reg, sp + offset);
2064 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2066 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2067 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2068 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2069 set_reg_offset (temp_saved_regs, reg, sp + offset);
2071 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2073 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2074 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2075 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2077 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2079 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2080 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2081 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2083 else if (inst == 0x673d) /* move $s1, $sp */
2086 PROC_FRAME_REG (&temp_proc_desc) = 17;
2088 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2090 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2091 frame_addr = sp + offset;
2092 PROC_FRAME_REG (&temp_proc_desc) = 17;
2093 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2095 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2097 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2098 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2099 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2100 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2102 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2104 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2105 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2106 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2107 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2109 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2110 entry_inst = inst; /* save for later processing */
2111 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2112 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
2115 /* The entry instruction is typically the first instruction in a function,
2116 and it stores registers at offsets relative to the value of the old SP
2117 (before the prologue). But the value of the sp parameter to this
2118 function is the new SP (after the prologue has been executed). So we
2119 can't calculate those offsets until we've seen the entire prologue,
2120 and can calculate what the old SP must have been. */
2121 if (entry_inst != 0)
2123 int areg_count = (entry_inst >> 8) & 7;
2124 int sreg_count = (entry_inst >> 6) & 3;
2126 /* The entry instruction always subtracts 32 from the SP. */
2127 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2129 /* Now we can calculate what the SP must have been at the
2130 start of the function prologue. */
2131 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2133 /* Check if a0-a3 were saved in the caller's argument save area. */
2134 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2136 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2137 set_reg_offset (temp_saved_regs, reg, sp + offset);
2138 offset += MIPS_SAVED_REGSIZE;
2141 /* Check if the ra register was pushed on the stack. */
2143 if (entry_inst & 0x20)
2145 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2146 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2147 offset -= MIPS_SAVED_REGSIZE;
2150 /* Check if the s0 and s1 registers were pushed on the stack. */
2151 for (reg = 16; reg < sreg_count + 16; reg++)
2153 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2154 set_reg_offset (temp_saved_regs, reg, sp + offset);
2155 offset -= MIPS_SAVED_REGSIZE;
2161 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2162 struct frame_info *next_frame, CORE_ADDR sp)
2165 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2167 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2168 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2169 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2170 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2171 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2173 unsigned long inst, high_word, low_word;
2176 /* Fetch the instruction. */
2177 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2179 /* Save some code by pre-extracting some useful fields. */
2180 high_word = (inst >> 16) & 0xffff;
2181 low_word = inst & 0xffff;
2182 reg = high_word & 0x1f;
2184 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2185 || high_word == 0x23bd /* addi $sp,$sp,-i */
2186 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2188 if (low_word & 0x8000) /* negative stack adjustment? */
2189 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2191 /* Exit loop if a positive stack adjustment is found, which
2192 usually means that the stack cleanup code in the function
2193 epilogue is reached. */
2196 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2198 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2199 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2201 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2203 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2204 but the register size used is only 32 bits. Make the address
2205 for the saved register point to the lower 32 bits. */
2206 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2207 set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch));
2209 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2211 /* Old gcc frame, r30 is virtual frame pointer. */
2212 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2213 frame_addr = sp + low_word;
2214 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2216 unsigned alloca_adjust;
2217 PROC_FRAME_REG (&temp_proc_desc) = 30;
2218 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2219 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2220 if (alloca_adjust > 0)
2222 /* FP > SP + frame_size. This may be because
2223 * of an alloca or somethings similar.
2224 * Fix sp to "pre-alloca" value, and try again.
2226 sp += alloca_adjust;
2231 /* move $30,$sp. With different versions of gas this will be either
2232 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2233 Accept any one of these. */
2234 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2236 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2237 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2239 unsigned alloca_adjust;
2240 PROC_FRAME_REG (&temp_proc_desc) = 30;
2241 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2242 alloca_adjust = (unsigned) (frame_addr - sp);
2243 if (alloca_adjust > 0)
2245 /* FP > SP + frame_size. This may be because
2246 * of an alloca or somethings similar.
2247 * Fix sp to "pre-alloca" value, and try again.
2249 sp += alloca_adjust;
2254 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2256 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2257 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
2262 static mips_extra_func_info_t
2263 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2264 struct frame_info *next_frame, int cur_frame)
2269 sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM);
2275 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2276 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2277 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2278 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2279 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2280 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2282 if (start_pc + 200 < limit_pc)
2283 limit_pc = start_pc + 200;
2284 if (pc_is_mips16 (start_pc))
2285 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2287 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2288 return &temp_proc_desc;
2291 struct mips_objfile_private
2297 /* Global used to communicate between non_heuristic_proc_desc and
2298 compare_pdr_entries within qsort (). */
2299 static bfd *the_bfd;
2302 compare_pdr_entries (const void *a, const void *b)
2304 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2305 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2309 else if (lhs == rhs)
2315 static mips_extra_func_info_t
2316 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2318 CORE_ADDR startaddr;
2319 mips_extra_func_info_t proc_desc;
2320 struct block *b = block_for_pc (pc);
2322 struct obj_section *sec;
2323 struct mips_objfile_private *priv;
2325 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
2328 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2330 *addrptr = startaddr;
2334 sec = find_pc_section (pc);
2337 priv = (struct mips_objfile_private *) sec->objfile->obj_private;
2339 /* Search the ".pdr" section generated by GAS. This includes most of
2340 the information normally found in ECOFF PDRs. */
2342 the_bfd = sec->objfile->obfd;
2344 && (the_bfd->format == bfd_object
2345 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2346 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2348 /* Right now GAS only outputs the address as a four-byte sequence.
2349 This means that we should not bother with this method on 64-bit
2350 targets (until that is fixed). */
2352 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2353 sizeof (struct mips_objfile_private));
2355 sec->objfile->obj_private = priv;
2357 else if (priv == NULL)
2361 priv = obstack_alloc (& sec->objfile->psymbol_obstack,
2362 sizeof (struct mips_objfile_private));
2364 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2367 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2368 priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
2370 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2371 priv->contents, 0, priv->size);
2373 /* In general, the .pdr section is sorted. However, in the
2374 presence of multiple code sections (and other corner cases)
2375 it can become unsorted. Sort it so that we can use a faster
2377 qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
2382 sec->objfile->obj_private = priv;
2386 if (priv->size != 0)
2392 high = priv->size / 32;
2398 mid = (low + high) / 2;
2400 ptr = priv->contents + mid * 32;
2401 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2402 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2403 SECT_OFF_TEXT (sec->objfile));
2404 if (pdr_pc == startaddr)
2406 if (pdr_pc > startaddr)
2411 while (low != high);
2415 struct symbol *sym = find_pc_function (pc);
2417 /* Fill in what we need of the proc_desc. */
2418 proc_desc = (mips_extra_func_info_t)
2419 obstack_alloc (&sec->objfile->psymbol_obstack,
2420 sizeof (struct mips_extra_func_info));
2421 PROC_LOW_ADDR (proc_desc) = startaddr;
2423 /* Only used for dummy frames. */
2424 PROC_HIGH_ADDR (proc_desc) = 0;
2426 PROC_FRAME_OFFSET (proc_desc)
2427 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2428 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2430 PROC_FRAME_ADJUST (proc_desc) = 0;
2431 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2433 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2435 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2437 PROC_FREG_OFFSET (proc_desc)
2438 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2439 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2441 proc_desc->pdr.isym = (long) sym;
2451 if (startaddr > BLOCK_START (b))
2453 /* This is the "pathological" case referred to in a comment in
2454 print_frame_info. It might be better to move this check into
2459 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
2461 /* If we never found a PDR for this function in symbol reading, then
2462 examine prologues to find the information. */
2465 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2466 if (PROC_FRAME_REG (proc_desc) == -1)
2476 static mips_extra_func_info_t
2477 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2479 mips_extra_func_info_t proc_desc;
2480 CORE_ADDR startaddr = 0;
2482 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2486 /* IF this is the topmost frame AND
2487 * (this proc does not have debugging information OR
2488 * the PC is in the procedure prologue)
2489 * THEN create a "heuristic" proc_desc (by analyzing
2490 * the actual code) to replace the "official" proc_desc.
2492 if (next_frame == NULL)
2494 struct symtab_and_line val;
2495 struct symbol *proc_symbol =
2496 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2500 val = find_pc_line (BLOCK_START
2501 (SYMBOL_BLOCK_VALUE (proc_symbol)),
2503 val.pc = val.end ? val.end : pc;
2505 if (!proc_symbol || pc < val.pc)
2507 mips_extra_func_info_t found_heuristic =
2508 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2509 pc, next_frame, cur_frame);
2510 if (found_heuristic)
2511 proc_desc = found_heuristic;
2517 /* Is linked_proc_desc_table really necessary? It only seems to be used
2518 by procedure call dummys. However, the procedures being called ought
2519 to have their own proc_descs, and even if they don't,
2520 heuristic_proc_desc knows how to create them! */
2522 struct linked_proc_info *link;
2524 for (link = linked_proc_desc_table; link; link = link->next)
2525 if (PROC_LOW_ADDR (&link->info) <= pc
2526 && PROC_HIGH_ADDR (&link->info) > pc)
2530 startaddr = heuristic_proc_start (pc);
2533 heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2539 get_frame_pointer (struct frame_info *frame,
2540 mips_extra_func_info_t proc_desc)
2542 return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
2543 + PROC_FRAME_OFFSET (proc_desc)
2544 - PROC_FRAME_ADJUST (proc_desc));
2547 static mips_extra_func_info_t cached_proc_desc;
2550 mips_frame_chain (struct frame_info *frame)
2552 mips_extra_func_info_t proc_desc;
2554 CORE_ADDR saved_pc = DEPRECATED_FRAME_SAVED_PC (frame);
2556 if (saved_pc == 0 || deprecated_inside_entry_file (saved_pc))
2559 /* Check if the PC is inside a call stub. If it is, fetch the
2560 PC of the caller of that stub. */
2561 if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0)
2564 if (DEPRECATED_PC_IN_CALL_DUMMY (saved_pc, 0, 0))
2566 /* A dummy frame, uses SP not FP. Get the old SP value. If all
2567 is well, frame->frame the bottom of the current frame will
2568 contain that value. */
2569 return get_frame_base (frame);
2572 /* Look up the procedure descriptor for this PC. */
2573 proc_desc = find_proc_desc (saved_pc, frame, 1);
2577 cached_proc_desc = proc_desc;
2579 /* If no frame pointer and frame size is zero, we must be at end
2580 of stack (or otherwise hosed). If we don't check frame size,
2581 we loop forever if we see a zero size frame. */
2582 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
2583 && PROC_FRAME_OFFSET (proc_desc) == 0
2584 /* The previous frame from a sigtramp frame might be frameless
2585 and have frame size zero. */
2586 && !(get_frame_type (frame) == SIGTRAMP_FRAME)
2587 /* For a generic dummy frame, let get_frame_pointer() unwind a
2588 register value saved as part of the dummy frame call. */
2589 && !(DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0)))
2592 return get_frame_pointer (frame, proc_desc);
2596 mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
2599 mips_extra_func_info_t proc_desc;
2601 if (get_frame_type (fci) == DUMMY_FRAME)
2604 /* Use proc_desc calculated in frame_chain. When there is no
2605 next frame, i.e, get_next_frame (fci) == NULL, we call
2606 find_proc_desc () to calculate it, passing an explicit
2607 NULL as the frame parameter. */
2609 get_next_frame (fci)
2611 : find_proc_desc (get_frame_pc (fci),
2612 NULL /* i.e, get_next_frame (fci) */,
2615 frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info));
2617 deprecated_set_frame_saved_regs_hack (fci, NULL);
2618 get_frame_extra_info (fci)->proc_desc =
2619 proc_desc == &temp_proc_desc ? 0 : proc_desc;
2622 /* Fixup frame-pointer - only needed for top frame */
2623 /* This may not be quite right, if proc has a real frame register.
2624 Get the value of the frame relative sp, procedure might have been
2625 interrupted by a signal at it's very start. */
2626 if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc)
2627 && !PROC_DESC_IS_DUMMY (proc_desc))
2628 deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM));
2629 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0))
2630 /* Do not ``fix'' fci->frame. It will have the value of the
2631 generic dummy frame's top-of-stack (since the draft
2632 fci->frame is obtained by returning the unwound stack
2633 pointer) and that is what we want. That way the fci->frame
2634 value will match the top-of-stack value that was saved as
2635 part of the dummy frames data. */
2638 deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc));
2640 if (proc_desc == &temp_proc_desc)
2644 /* Do not set the saved registers for a sigtramp frame,
2645 mips_find_saved_registers will do that for us. We can't
2646 use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
2648 /* FIXME: cagney/2002-11-18: This problem will go away once
2649 frame.c:get_prev_frame() is modified to set the frame's
2650 type before calling functions like this. */
2651 find_pc_partial_function (get_frame_pc (fci), &name,
2652 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
2653 if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name))
2655 frame_saved_regs_zalloc (fci);
2656 /* Set value of previous frame's stack pointer.
2657 Remember that saved_regs[SP_REGNUM] is special in
2658 that it contains the value of the stack pointer
2659 register. The other saved_regs values are addresses
2660 (in the inferior) at which a given register's value
2662 set_reg_offset (temp_saved_regs, SP_REGNUM,
2663 get_frame_base (fci));
2664 set_reg_offset (temp_saved_regs, PC_REGNUM,
2665 temp_saved_regs[RA_REGNUM]);
2666 memcpy (deprecated_get_frame_saved_regs (fci), temp_saved_regs,
2667 SIZEOF_FRAME_SAVED_REGS);
2671 /* hack: if argument regs are saved, guess these contain args */
2672 /* assume we can't tell how many args for now */
2673 get_frame_extra_info (fci)->num_args = -1;
2674 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
2676 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
2678 get_frame_extra_info (fci)->num_args = regnum - A0_REGNUM + 1;
2685 /* MIPS stack frames are almost impenetrable. When execution stops,
2686 we basically have to look at symbol information for the function
2687 that we stopped in, which tells us *which* register (if any) is
2688 the base of the frame pointer, and what offset from that register
2689 the frame itself is at.
2691 This presents a problem when trying to examine a stack in memory
2692 (that isn't executing at the moment), using the "frame" command. We
2693 don't have a PC, nor do we have any registers except SP.
2695 This routine takes two arguments, SP and PC, and tries to make the
2696 cached frames look as if these two arguments defined a frame on the
2697 cache. This allows the rest of info frame to extract the important
2698 arguments without difficulty. */
2701 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2704 error ("MIPS frame specifications require two arguments: sp and pc");
2706 return create_new_frame (argv[0], argv[1]);
2709 /* According to the current ABI, should the type be passed in a
2710 floating-point register (assuming that there is space)? When there
2711 is no FPU, FP are not even considered as possibile candidates for
2712 FP registers and, consequently this returns false - forces FP
2713 arguments into integer registers. */
2716 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2718 return ((typecode == TYPE_CODE_FLT
2720 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2721 && TYPE_NFIELDS (arg_type) == 1
2722 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2723 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2726 /* On o32, argument passing in GPRs depends on the alignment of the type being
2727 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2730 mips_type_needs_double_align (struct type *type)
2732 enum type_code typecode = TYPE_CODE (type);
2734 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2736 else if (typecode == TYPE_CODE_STRUCT)
2738 if (TYPE_NFIELDS (type) < 1)
2740 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2742 else if (typecode == TYPE_CODE_UNION)
2746 n = TYPE_NFIELDS (type);
2747 for (i = 0; i < n; i++)
2748 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2755 /* Adjust the address downward (direction of stack growth) so that it
2756 is correctly aligned for a new stack frame. */
2758 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2760 return align_down (addr, 16);
2764 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2765 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2766 struct value **args, CORE_ADDR sp, int struct_return,
2767 CORE_ADDR struct_addr)
2773 int stack_offset = 0;
2775 /* For shared libraries, "t9" needs to point at the function
2777 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2779 /* Set the return address register to point to the entry point of
2780 the program, where a breakpoint lies in wait. */
2781 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2783 /* First ensure that the stack and structure return address (if any)
2784 are properly aligned. The stack has to be at least 64-bit
2785 aligned even on 32-bit machines, because doubles must be 64-bit
2786 aligned. For n32 and n64, stack frames need to be 128-bit
2787 aligned, so we round to this widest known alignment. */
2789 sp = align_down (sp, 16);
2790 struct_addr = align_down (struct_addr, 16);
2792 /* Now make space on the stack for the args. We allocate more
2793 than necessary for EABI, because the first few arguments are
2794 passed in registers, but that's OK. */
2795 for (argnum = 0; argnum < nargs; argnum++)
2796 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2797 MIPS_STACK_ARGSIZE);
2798 sp -= align_up (len, 16);
2801 fprintf_unfiltered (gdb_stdlog,
2802 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2803 paddr_nz (sp), (long) align_up (len, 16));
2805 /* Initialize the integer and float register pointers. */
2807 float_argreg = FPA0_REGNUM;
2809 /* The struct_return pointer occupies the first parameter-passing reg. */
2813 fprintf_unfiltered (gdb_stdlog,
2814 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2815 argreg, paddr_nz (struct_addr));
2816 write_register (argreg++, struct_addr);
2819 /* Now load as many as possible of the first arguments into
2820 registers, and push the rest onto the stack. Loop thru args
2821 from first to last. */
2822 for (argnum = 0; argnum < nargs; argnum++)
2825 char valbuf[MAX_REGISTER_SIZE];
2826 struct value *arg = args[argnum];
2827 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2828 int len = TYPE_LENGTH (arg_type);
2829 enum type_code typecode = TYPE_CODE (arg_type);
2832 fprintf_unfiltered (gdb_stdlog,
2833 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2834 argnum + 1, len, (int) typecode);
2836 /* The EABI passes structures that do not fit in a register by
2838 if (len > MIPS_SAVED_REGSIZE
2839 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2841 store_unsigned_integer (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
2842 typecode = TYPE_CODE_PTR;
2843 len = MIPS_SAVED_REGSIZE;
2846 fprintf_unfiltered (gdb_stdlog, " push");
2849 val = (char *) VALUE_CONTENTS (arg);
2851 /* 32-bit ABIs always start floating point arguments in an
2852 even-numbered floating point register. Round the FP register
2853 up before the check to see if there are any FP registers
2854 left. Non MIPS_EABI targets also pass the FP in the integer
2855 registers so also round up normal registers. */
2856 if (!FP_REGISTER_DOUBLE
2857 && fp_register_arg_p (typecode, arg_type))
2859 if ((float_argreg & 1))
2863 /* Floating point arguments passed in registers have to be
2864 treated specially. On 32-bit architectures, doubles
2865 are passed in register pairs; the even register gets
2866 the low word, and the odd register gets the high word.
2867 On non-EABI processors, the first two floating point arguments are
2868 also copied to general registers, because MIPS16 functions
2869 don't use float registers for arguments. This duplication of
2870 arguments in general registers can't hurt non-MIPS16 functions
2871 because those registers are normally skipped. */
2872 /* MIPS_EABI squeezes a struct that contains a single floating
2873 point value into an FP register instead of pushing it onto the
2875 if (fp_register_arg_p (typecode, arg_type)
2876 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2878 if (!FP_REGISTER_DOUBLE && len == 8)
2880 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2881 unsigned long regval;
2883 /* Write the low word of the double to the even register(s). */
2884 regval = extract_unsigned_integer (val + low_offset, 4);
2886 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2887 float_argreg, phex (regval, 4));
2888 write_register (float_argreg++, regval);
2890 /* Write the high word of the double to the odd register(s). */
2891 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2893 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2894 float_argreg, phex (regval, 4));
2895 write_register (float_argreg++, regval);
2899 /* This is a floating point value that fits entirely
2900 in a single register. */
2901 /* On 32 bit ABI's the float_argreg is further adjusted
2902 above to ensure that it is even register aligned. */
2903 LONGEST regval = extract_unsigned_integer (val, len);
2905 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2906 float_argreg, phex (regval, len));
2907 write_register (float_argreg++, regval);
2912 /* Copy the argument to general registers or the stack in
2913 register-sized pieces. Large arguments are split between
2914 registers and stack. */
2915 /* Note: structs whose size is not a multiple of
2916 mips_regsize() are treated specially: Irix cc passes them
2917 in registers where gcc sometimes puts them on the stack.
2918 For maximum compatibility, we will put them in both
2920 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
2921 (len % MIPS_SAVED_REGSIZE != 0));
2923 /* Note: Floating-point values that didn't fit into an FP
2924 register are only written to memory. */
2927 /* Remember if the argument was written to the stack. */
2928 int stack_used_p = 0;
2930 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
2933 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2936 /* Write this portion of the argument to the stack. */
2937 if (argreg > MIPS_LAST_ARG_REGNUM
2939 || fp_register_arg_p (typecode, arg_type))
2941 /* Should shorter than int integer values be
2942 promoted to int before being stored? */
2943 int longword_offset = 0;
2946 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2948 if (MIPS_STACK_ARGSIZE == 8 &&
2949 (typecode == TYPE_CODE_INT ||
2950 typecode == TYPE_CODE_PTR ||
2951 typecode == TYPE_CODE_FLT) && len <= 4)
2952 longword_offset = MIPS_STACK_ARGSIZE - len;
2953 else if ((typecode == TYPE_CODE_STRUCT ||
2954 typecode == TYPE_CODE_UNION) &&
2955 TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE)
2956 longword_offset = MIPS_STACK_ARGSIZE - len;
2961 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2962 paddr_nz (stack_offset));
2963 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2964 paddr_nz (longword_offset));
2967 addr = sp + stack_offset + longword_offset;
2972 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2974 for (i = 0; i < partial_len; i++)
2976 fprintf_unfiltered (gdb_stdlog, "%02x",
2980 write_memory (addr, val, partial_len);
2983 /* Note!!! This is NOT an else clause. Odd sized
2984 structs may go thru BOTH paths. Floating point
2985 arguments will not. */
2986 /* Write this portion of the argument to a general
2987 purpose register. */
2988 if (argreg <= MIPS_LAST_ARG_REGNUM
2989 && !fp_register_arg_p (typecode, arg_type))
2991 LONGEST regval = extract_unsigned_integer (val, partial_len);
2994 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2996 phex (regval, MIPS_SAVED_REGSIZE));
2997 write_register (argreg, regval);
3004 /* Compute the the offset into the stack at which we
3005 will copy the next parameter.
3007 In the new EABI (and the NABI32), the stack_offset
3008 only needs to be adjusted when it has been used. */
3011 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
3015 fprintf_unfiltered (gdb_stdlog, "\n");
3018 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3020 /* Return adjusted stack pointer. */
3024 /* N32/N64 version of push_dummy_call. */
3027 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3028 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3029 struct value **args, CORE_ADDR sp, int struct_return,
3030 CORE_ADDR struct_addr)
3036 int stack_offset = 0;
3038 /* For shared libraries, "t9" needs to point at the function
3040 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3042 /* Set the return address register to point to the entry point of
3043 the program, where a breakpoint lies in wait. */
3044 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3046 /* First ensure that the stack and structure return address (if any)
3047 are properly aligned. The stack has to be at least 64-bit
3048 aligned even on 32-bit machines, because doubles must be 64-bit
3049 aligned. For n32 and n64, stack frames need to be 128-bit
3050 aligned, so we round to this widest known alignment. */
3052 sp = align_down (sp, 16);
3053 struct_addr = align_down (struct_addr, 16);
3055 /* Now make space on the stack for the args. */
3056 for (argnum = 0; argnum < nargs; argnum++)
3057 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3058 MIPS_STACK_ARGSIZE);
3059 sp -= align_up (len, 16);
3062 fprintf_unfiltered (gdb_stdlog,
3063 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3064 paddr_nz (sp), (long) align_up (len, 16));
3066 /* Initialize the integer and float register pointers. */
3068 float_argreg = FPA0_REGNUM;
3070 /* The struct_return pointer occupies the first parameter-passing reg. */
3074 fprintf_unfiltered (gdb_stdlog,
3075 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3076 argreg, paddr_nz (struct_addr));
3077 write_register (argreg++, struct_addr);
3080 /* Now load as many as possible of the first arguments into
3081 registers, and push the rest onto the stack. Loop thru args
3082 from first to last. */
3083 for (argnum = 0; argnum < nargs; argnum++)
3086 char valbuf[MAX_REGISTER_SIZE];
3087 struct value *arg = args[argnum];
3088 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3089 int len = TYPE_LENGTH (arg_type);
3090 enum type_code typecode = TYPE_CODE (arg_type);
3093 fprintf_unfiltered (gdb_stdlog,
3094 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3095 argnum + 1, len, (int) typecode);
3097 val = (char *) VALUE_CONTENTS (arg);
3099 if (fp_register_arg_p (typecode, arg_type)
3100 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3102 /* This is a floating point value that fits entirely
3103 in a single register. */
3104 /* On 32 bit ABI's the float_argreg is further adjusted
3105 above to ensure that it is even register aligned. */
3106 LONGEST regval = extract_unsigned_integer (val, len);
3108 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3109 float_argreg, phex (regval, len));
3110 write_register (float_argreg++, regval);
3113 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3114 argreg, phex (regval, len));
3115 write_register (argreg, regval);
3120 /* Copy the argument to general registers or the stack in
3121 register-sized pieces. Large arguments are split between
3122 registers and stack. */
3123 /* Note: structs whose size is not a multiple of
3124 mips_regsize() are treated specially: Irix cc passes them
3125 in registers where gcc sometimes puts them on the stack.
3126 For maximum compatibility, we will put them in both
3128 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3129 (len % MIPS_SAVED_REGSIZE != 0));
3130 /* Note: Floating-point values that didn't fit into an FP
3131 register are only written to memory. */
3134 /* Rememer if the argument was written to the stack. */
3135 int stack_used_p = 0;
3136 int partial_len = len < MIPS_SAVED_REGSIZE ?
3137 len : MIPS_SAVED_REGSIZE;
3140 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3143 /* Write this portion of the argument to the stack. */
3144 if (argreg > MIPS_LAST_ARG_REGNUM
3146 || fp_register_arg_p (typecode, arg_type))
3148 /* Should shorter than int integer values be
3149 promoted to int before being stored? */
3150 int longword_offset = 0;
3153 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3155 if (MIPS_STACK_ARGSIZE == 8 &&
3156 (typecode == TYPE_CODE_INT ||
3157 typecode == TYPE_CODE_PTR ||
3158 typecode == TYPE_CODE_FLT) && len <= 4)
3159 longword_offset = MIPS_STACK_ARGSIZE - len;
3164 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3165 paddr_nz (stack_offset));
3166 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3167 paddr_nz (longword_offset));
3170 addr = sp + stack_offset + longword_offset;
3175 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3177 for (i = 0; i < partial_len; i++)
3179 fprintf_unfiltered (gdb_stdlog, "%02x",
3183 write_memory (addr, val, partial_len);
3186 /* Note!!! This is NOT an else clause. Odd sized
3187 structs may go thru BOTH paths. Floating point
3188 arguments will not. */
3189 /* Write this portion of the argument to a general
3190 purpose register. */
3191 if (argreg <= MIPS_LAST_ARG_REGNUM
3192 && !fp_register_arg_p (typecode, arg_type))
3194 LONGEST regval = extract_unsigned_integer (val, partial_len);
3196 /* A non-floating-point argument being passed in a
3197 general register. If a struct or union, and if
3198 the remaining length is smaller than the register
3199 size, we have to adjust the register value on
3202 It does not seem to be necessary to do the
3203 same for integral types.
3205 cagney/2001-07-23: gdb/179: Also, GCC, when
3206 outputting LE O32 with sizeof (struct) <
3207 MIPS_SAVED_REGSIZE, generates a left shift as
3208 part of storing the argument in a register a
3209 register (the left shift isn't generated when
3210 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3211 is quite possible that this is GCC contradicting
3212 the LE/O32 ABI, GDB has not been adjusted to
3213 accommodate this. Either someone needs to
3214 demonstrate that the LE/O32 ABI specifies such a
3215 left shift OR this new ABI gets identified as
3216 such and GDB gets tweaked accordingly. */
3218 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3219 && partial_len < MIPS_SAVED_REGSIZE
3220 && (typecode == TYPE_CODE_STRUCT ||
3221 typecode == TYPE_CODE_UNION))
3222 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3226 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3228 phex (regval, MIPS_SAVED_REGSIZE));
3229 write_register (argreg, regval);
3236 /* Compute the the offset into the stack at which we
3237 will copy the next parameter.
3239 In N32 (N64?), the stack_offset only needs to be
3240 adjusted when it has been used. */
3243 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
3247 fprintf_unfiltered (gdb_stdlog, "\n");
3250 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3252 /* Return adjusted stack pointer. */
3256 /* O32 version of push_dummy_call. */
3259 mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3260 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3261 struct value **args, CORE_ADDR sp, int struct_return,
3262 CORE_ADDR struct_addr)
3268 int stack_offset = 0;
3270 /* For shared libraries, "t9" needs to point at the function
3272 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3274 /* Set the return address register to point to the entry point of
3275 the program, where a breakpoint lies in wait. */
3276 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3278 /* First ensure that the stack and structure return address (if any)
3279 are properly aligned. The stack has to be at least 64-bit
3280 aligned even on 32-bit machines, because doubles must be 64-bit
3281 aligned. For n32 and n64, stack frames need to be 128-bit
3282 aligned, so we round to this widest known alignment. */
3284 sp = align_down (sp, 16);
3285 struct_addr = align_down (struct_addr, 16);
3287 /* Now make space on the stack for the args. */
3288 for (argnum = 0; argnum < nargs; argnum++)
3289 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3290 MIPS_STACK_ARGSIZE);
3291 sp -= align_up (len, 16);
3294 fprintf_unfiltered (gdb_stdlog,
3295 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3296 paddr_nz (sp), (long) align_up (len, 16));
3298 /* Initialize the integer and float register pointers. */
3300 float_argreg = FPA0_REGNUM;
3302 /* The struct_return pointer occupies the first parameter-passing reg. */
3306 fprintf_unfiltered (gdb_stdlog,
3307 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3308 argreg, paddr_nz (struct_addr));
3309 write_register (argreg++, struct_addr);
3310 stack_offset += MIPS_STACK_ARGSIZE;
3313 /* Now load as many as possible of the first arguments into
3314 registers, and push the rest onto the stack. Loop thru args
3315 from first to last. */
3316 for (argnum = 0; argnum < nargs; argnum++)
3319 char valbuf[MAX_REGISTER_SIZE];
3320 struct value *arg = args[argnum];
3321 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3322 int len = TYPE_LENGTH (arg_type);
3323 enum type_code typecode = TYPE_CODE (arg_type);
3326 fprintf_unfiltered (gdb_stdlog,
3327 "mips_o32_push_dummy_call: %d len=%d type=%d",
3328 argnum + 1, len, (int) typecode);
3330 val = (char *) VALUE_CONTENTS (arg);
3332 /* 32-bit ABIs always start floating point arguments in an
3333 even-numbered floating point register. Round the FP register
3334 up before the check to see if there are any FP registers
3335 left. O32/O64 targets also pass the FP in the integer
3336 registers so also round up normal registers. */
3337 if (!FP_REGISTER_DOUBLE
3338 && fp_register_arg_p (typecode, arg_type))
3340 if ((float_argreg & 1))
3344 /* Floating point arguments passed in registers have to be
3345 treated specially. On 32-bit architectures, doubles
3346 are passed in register pairs; the even register gets
3347 the low word, and the odd register gets the high word.
3348 On O32/O64, the first two floating point arguments are
3349 also copied to general registers, because MIPS16 functions
3350 don't use float registers for arguments. This duplication of
3351 arguments in general registers can't hurt non-MIPS16 functions
3352 because those registers are normally skipped. */
3354 if (fp_register_arg_p (typecode, arg_type)
3355 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3357 if (!FP_REGISTER_DOUBLE && len == 8)
3359 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3360 unsigned long regval;
3362 /* Write the low word of the double to the even register(s). */
3363 regval = extract_unsigned_integer (val + low_offset, 4);
3365 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3366 float_argreg, phex (regval, 4));
3367 write_register (float_argreg++, regval);
3369 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3370 argreg, phex (regval, 4));
3371 write_register (argreg++, regval);
3373 /* Write the high word of the double to the odd register(s). */
3374 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3376 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3377 float_argreg, phex (regval, 4));
3378 write_register (float_argreg++, regval);
3381 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3382 argreg, phex (regval, 4));
3383 write_register (argreg++, regval);
3387 /* This is a floating point value that fits entirely
3388 in a single register. */
3389 /* On 32 bit ABI's the float_argreg is further adjusted
3390 above to ensure that it is even register aligned. */
3391 LONGEST regval = extract_unsigned_integer (val, len);
3393 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3394 float_argreg, phex (regval, len));
3395 write_register (float_argreg++, regval);
3396 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3397 registers for each argument. The below is (my
3398 guess) to ensure that the corresponding integer
3399 register has reserved the same space. */
3401 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3402 argreg, phex (regval, len));
3403 write_register (argreg, regval);
3404 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3406 /* Reserve space for the FP register. */
3407 stack_offset += align_up (len, MIPS_STACK_ARGSIZE);
3411 /* Copy the argument to general registers or the stack in
3412 register-sized pieces. Large arguments are split between
3413 registers and stack. */
3414 /* Note: structs whose size is not a multiple of
3415 mips_regsize() are treated specially: Irix cc passes them
3416 in registers where gcc sometimes puts them on the stack.
3417 For maximum compatibility, we will put them in both
3419 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3420 (len % MIPS_SAVED_REGSIZE != 0));
3421 /* Structures should be aligned to eight bytes (even arg registers)
3422 on MIPS_ABI_O32, if their first member has double precision. */
3423 if (MIPS_SAVED_REGSIZE < 8
3424 && mips_type_needs_double_align (arg_type))
3429 /* Note: Floating-point values that didn't fit into an FP
3430 register are only written to memory. */
3433 /* Remember if the argument was written to the stack. */
3434 int stack_used_p = 0;
3436 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3439 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3442 /* Write this portion of the argument to the stack. */
3443 if (argreg > MIPS_LAST_ARG_REGNUM
3445 || fp_register_arg_p (typecode, arg_type))
3447 /* Should shorter than int integer values be
3448 promoted to int before being stored? */
3449 int longword_offset = 0;
3452 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3454 if (MIPS_STACK_ARGSIZE == 8 &&
3455 (typecode == TYPE_CODE_INT ||
3456 typecode == TYPE_CODE_PTR ||
3457 typecode == TYPE_CODE_FLT) && len <= 4)
3458 longword_offset = MIPS_STACK_ARGSIZE - len;
3463 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3464 paddr_nz (stack_offset));
3465 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3466 paddr_nz (longword_offset));
3469 addr = sp + stack_offset + longword_offset;
3474 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3476 for (i = 0; i < partial_len; i++)
3478 fprintf_unfiltered (gdb_stdlog, "%02x",
3482 write_memory (addr, val, partial_len);
3485 /* Note!!! This is NOT an else clause. Odd sized
3486 structs may go thru BOTH paths. Floating point
3487 arguments will not. */
3488 /* Write this portion of the argument to a general
3489 purpose register. */
3490 if (argreg <= MIPS_LAST_ARG_REGNUM
3491 && !fp_register_arg_p (typecode, arg_type))
3493 LONGEST regval = extract_signed_integer (val, partial_len);
3494 /* Value may need to be sign extended, because
3495 mips_regsize() != MIPS_SAVED_REGSIZE. */
3497 /* A non-floating-point argument being passed in a
3498 general register. If a struct or union, and if
3499 the remaining length is smaller than the register
3500 size, we have to adjust the register value on
3503 It does not seem to be necessary to do the
3504 same for integral types.
3506 Also don't do this adjustment on O64 binaries.
3508 cagney/2001-07-23: gdb/179: Also, GCC, when
3509 outputting LE O32 with sizeof (struct) <
3510 MIPS_SAVED_REGSIZE, generates a left shift as
3511 part of storing the argument in a register a
3512 register (the left shift isn't generated when
3513 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3514 is quite possible that this is GCC contradicting
3515 the LE/O32 ABI, GDB has not been adjusted to
3516 accommodate this. Either someone needs to
3517 demonstrate that the LE/O32 ABI specifies such a
3518 left shift OR this new ABI gets identified as
3519 such and GDB gets tweaked accordingly. */
3521 if (MIPS_SAVED_REGSIZE < 8
3522 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3523 && partial_len < MIPS_SAVED_REGSIZE
3524 && (typecode == TYPE_CODE_STRUCT ||
3525 typecode == TYPE_CODE_UNION))
3526 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3530 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3532 phex (regval, MIPS_SAVED_REGSIZE));
3533 write_register (argreg, regval);
3536 /* Prevent subsequent floating point arguments from
3537 being passed in floating point registers. */
3538 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3544 /* Compute the the offset into the stack at which we
3545 will copy the next parameter.
3547 In older ABIs, the caller reserved space for
3548 registers that contained arguments. This was loosely
3549 refered to as their "home". Consequently, space is
3550 always allocated. */
3552 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
3556 fprintf_unfiltered (gdb_stdlog, "\n");
3559 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3561 /* Return adjusted stack pointer. */
3565 /* O64 version of push_dummy_call. */
3568 mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3569 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
3570 struct value **args, CORE_ADDR sp, int struct_return,
3571 CORE_ADDR struct_addr)
3577 int stack_offset = 0;
3579 /* For shared libraries, "t9" needs to point at the function
3581 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3583 /* Set the return address register to point to the entry point of
3584 the program, where a breakpoint lies in wait. */
3585 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3587 /* First ensure that the stack and structure return address (if any)
3588 are properly aligned. The stack has to be at least 64-bit
3589 aligned even on 32-bit machines, because doubles must be 64-bit
3590 aligned. For n32 and n64, stack frames need to be 128-bit
3591 aligned, so we round to this widest known alignment. */
3593 sp = align_down (sp, 16);
3594 struct_addr = align_down (struct_addr, 16);
3596 /* Now make space on the stack for the args. */
3597 for (argnum = 0; argnum < nargs; argnum++)
3598 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3599 MIPS_STACK_ARGSIZE);
3600 sp -= align_up (len, 16);
3603 fprintf_unfiltered (gdb_stdlog,
3604 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3605 paddr_nz (sp), (long) align_up (len, 16));
3607 /* Initialize the integer and float register pointers. */
3609 float_argreg = FPA0_REGNUM;
3611 /* The struct_return pointer occupies the first parameter-passing reg. */
3615 fprintf_unfiltered (gdb_stdlog,
3616 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3617 argreg, paddr_nz (struct_addr));
3618 write_register (argreg++, struct_addr);
3619 stack_offset += MIPS_STACK_ARGSIZE;
3622 /* Now load as many as possible of the first arguments into
3623 registers, and push the rest onto the stack. Loop thru args
3624 from first to last. */
3625 for (argnum = 0; argnum < nargs; argnum++)
3628 char valbuf[MAX_REGISTER_SIZE];
3629 struct value *arg = args[argnum];
3630 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3631 int len = TYPE_LENGTH (arg_type);
3632 enum type_code typecode = TYPE_CODE (arg_type);
3635 fprintf_unfiltered (gdb_stdlog,
3636 "mips_o64_push_dummy_call: %d len=%d type=%d",
3637 argnum + 1, len, (int) typecode);
3639 val = (char *) VALUE_CONTENTS (arg);
3641 /* 32-bit ABIs always start floating point arguments in an
3642 even-numbered floating point register. Round the FP register
3643 up before the check to see if there are any FP registers
3644 left. O32/O64 targets also pass the FP in the integer
3645 registers so also round up normal registers. */
3646 if (!FP_REGISTER_DOUBLE
3647 && fp_register_arg_p (typecode, arg_type))
3649 if ((float_argreg & 1))
3653 /* Floating point arguments passed in registers have to be
3654 treated specially. On 32-bit architectures, doubles
3655 are passed in register pairs; the even register gets
3656 the low word, and the odd register gets the high word.
3657 On O32/O64, the first two floating point arguments are
3658 also copied to general registers, because MIPS16 functions
3659 don't use float registers for arguments. This duplication of
3660 arguments in general registers can't hurt non-MIPS16 functions
3661 because those registers are normally skipped. */
3663 if (fp_register_arg_p (typecode, arg_type)
3664 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3666 if (!FP_REGISTER_DOUBLE && len == 8)
3668 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3669 unsigned long regval;
3671 /* Write the low word of the double to the even register(s). */
3672 regval = extract_unsigned_integer (val + low_offset, 4);
3674 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3675 float_argreg, phex (regval, 4));
3676 write_register (float_argreg++, regval);
3678 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3679 argreg, phex (regval, 4));
3680 write_register (argreg++, regval);
3682 /* Write the high word of the double to the odd register(s). */
3683 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3685 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3686 float_argreg, phex (regval, 4));
3687 write_register (float_argreg++, regval);
3690 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3691 argreg, phex (regval, 4));
3692 write_register (argreg++, regval);
3696 /* This is a floating point value that fits entirely
3697 in a single register. */
3698 /* On 32 bit ABI's the float_argreg is further adjusted
3699 above to ensure that it is even register aligned. */
3700 LONGEST regval = extract_unsigned_integer (val, len);
3702 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3703 float_argreg, phex (regval, len));
3704 write_register (float_argreg++, regval);
3705 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3706 registers for each argument. The below is (my
3707 guess) to ensure that the corresponding integer
3708 register has reserved the same space. */
3710 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3711 argreg, phex (regval, len));
3712 write_register (argreg, regval);
3713 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3715 /* Reserve space for the FP register. */
3716 stack_offset += align_up (len, MIPS_STACK_ARGSIZE);
3720 /* Copy the argument to general registers or the stack in
3721 register-sized pieces. Large arguments are split between
3722 registers and stack. */
3723 /* Note: structs whose size is not a multiple of
3724 mips_regsize() are treated specially: Irix cc passes them
3725 in registers where gcc sometimes puts them on the stack.
3726 For maximum compatibility, we will put them in both
3728 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
3729 (len % MIPS_SAVED_REGSIZE != 0));
3730 /* Structures should be aligned to eight bytes (even arg registers)
3731 on MIPS_ABI_O32, if their first member has double precision. */
3732 if (MIPS_SAVED_REGSIZE < 8
3733 && mips_type_needs_double_align (arg_type))
3738 /* Note: Floating-point values that didn't fit into an FP
3739 register are only written to memory. */
3742 /* Remember if the argument was written to the stack. */
3743 int stack_used_p = 0;
3745 len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
3748 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3751 /* Write this portion of the argument to the stack. */
3752 if (argreg > MIPS_LAST_ARG_REGNUM
3754 || fp_register_arg_p (typecode, arg_type))
3756 /* Should shorter than int integer values be
3757 promoted to int before being stored? */
3758 int longword_offset = 0;
3761 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3763 if (MIPS_STACK_ARGSIZE == 8 &&
3764 (typecode == TYPE_CODE_INT ||
3765 typecode == TYPE_CODE_PTR ||
3766 typecode == TYPE_CODE_FLT) && len <= 4)
3767 longword_offset = MIPS_STACK_ARGSIZE - len;
3772 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3773 paddr_nz (stack_offset));
3774 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3775 paddr_nz (longword_offset));
3778 addr = sp + stack_offset + longword_offset;
3783 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3785 for (i = 0; i < partial_len; i++)
3787 fprintf_unfiltered (gdb_stdlog, "%02x",
3791 write_memory (addr, val, partial_len);
3794 /* Note!!! This is NOT an else clause. Odd sized
3795 structs may go thru BOTH paths. Floating point
3796 arguments will not. */
3797 /* Write this portion of the argument to a general
3798 purpose register. */
3799 if (argreg <= MIPS_LAST_ARG_REGNUM
3800 && !fp_register_arg_p (typecode, arg_type))
3802 LONGEST regval = extract_signed_integer (val, partial_len);
3803 /* Value may need to be sign extended, because
3804 mips_regsize() != MIPS_SAVED_REGSIZE. */
3806 /* A non-floating-point argument being passed in a
3807 general register. If a struct or union, and if
3808 the remaining length is smaller than the register
3809 size, we have to adjust the register value on
3812 It does not seem to be necessary to do the
3813 same for integral types.
3815 Also don't do this adjustment on O64 binaries.
3817 cagney/2001-07-23: gdb/179: Also, GCC, when
3818 outputting LE O32 with sizeof (struct) <
3819 MIPS_SAVED_REGSIZE, generates a left shift as
3820 part of storing the argument in a register a
3821 register (the left shift isn't generated when
3822 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3823 is quite possible that this is GCC contradicting
3824 the LE/O32 ABI, GDB has not been adjusted to
3825 accommodate this. Either someone needs to
3826 demonstrate that the LE/O32 ABI specifies such a
3827 left shift OR this new ABI gets identified as
3828 such and GDB gets tweaked accordingly. */
3830 if (MIPS_SAVED_REGSIZE < 8
3831 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3832 && partial_len < MIPS_SAVED_REGSIZE
3833 && (typecode == TYPE_CODE_STRUCT ||
3834 typecode == TYPE_CODE_UNION))
3835 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
3839 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3841 phex (regval, MIPS_SAVED_REGSIZE));
3842 write_register (argreg, regval);
3845 /* Prevent subsequent floating point arguments from
3846 being passed in floating point registers. */
3847 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3853 /* Compute the the offset into the stack at which we
3854 will copy the next parameter.
3856 In older ABIs, the caller reserved space for
3857 registers that contained arguments. This was loosely
3858 refered to as their "home". Consequently, space is
3859 always allocated. */
3861 stack_offset += align_up (partial_len, MIPS_STACK_ARGSIZE);
3865 fprintf_unfiltered (gdb_stdlog, "\n");
3868 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3870 /* Return adjusted stack pointer. */
3875 mips_pop_frame (void)
3878 struct frame_info *frame = get_current_frame ();
3879 CORE_ADDR new_sp = get_frame_base (frame);
3880 mips_extra_func_info_t proc_desc;
3882 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
3884 generic_pop_dummy_frame ();
3885 flush_cached_frames ();
3889 proc_desc = get_frame_extra_info (frame)->proc_desc;
3890 write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
3891 mips_find_saved_regs (frame);
3892 for (regnum = 0; regnum < NUM_REGS; regnum++)
3893 if (regnum != SP_REGNUM && regnum != PC_REGNUM
3894 && deprecated_get_frame_saved_regs (frame)[regnum])
3896 /* Floating point registers must not be sign extended,
3897 in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */
3899 if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32)
3900 write_register (regnum,
3901 read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum],
3902 MIPS_SAVED_REGSIZE));
3904 write_register (regnum,
3905 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
3906 MIPS_SAVED_REGSIZE));
3909 write_register (SP_REGNUM, new_sp);
3910 flush_cached_frames ();
3912 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
3914 struct linked_proc_info *pi_ptr, *prev_ptr;
3916 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
3918 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
3920 if (&pi_ptr->info == proc_desc)
3925 error ("Can't locate dummy extra frame info\n");
3927 if (prev_ptr != NULL)
3928 prev_ptr->next = pi_ptr->next;
3930 linked_proc_desc_table = pi_ptr->next;
3934 write_register (HI_REGNUM,
3935 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
3936 MIPS_SAVED_REGSIZE));
3937 write_register (LO_REGNUM,
3938 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
3939 MIPS_SAVED_REGSIZE));
3940 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
3941 write_register (FCRCS_REGNUM,
3942 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
3943 MIPS_SAVED_REGSIZE));
3947 /* Floating point register management.
3949 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3950 64bit operations, these early MIPS cpus treat fp register pairs
3951 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3952 registers and offer a compatibility mode that emulates the MIPS2 fp
3953 model. When operating in MIPS2 fp compat mode, later cpu's split
3954 double precision floats into two 32-bit chunks and store them in
3955 consecutive fp regs. To display 64-bit floats stored in this
3956 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3957 Throw in user-configurable endianness and you have a real mess.
3959 The way this works is:
3960 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3961 double-precision value will be split across two logical registers.
3962 The lower-numbered logical register will hold the low-order bits,
3963 regardless of the processor's endianness.
3964 - If we are on a 64-bit processor, and we are looking for a
3965 single-precision value, it will be in the low ordered bits
3966 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3967 save slot in memory.
3968 - If we are in 64-bit mode, everything is straightforward.
3970 Note that this code only deals with "live" registers at the top of the
3971 stack. We will attempt to deal with saved registers later, when
3972 the raw/cooked register interface is in place. (We need a general
3973 interface that can deal with dynamic saved register sizes -- fp
3974 regs could be 32 bits wide in one frame and 64 on the frame above
3977 static struct type *
3978 mips_float_register_type (void)
3980 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3981 return builtin_type_ieee_single_big;
3983 return builtin_type_ieee_single_little;
3986 static struct type *
3987 mips_double_register_type (void)
3989 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3990 return builtin_type_ieee_double_big;
3992 return builtin_type_ieee_double_little;
3995 /* Copy a 32-bit single-precision value from the current frame
3996 into rare_buffer. */
3999 mips_read_fp_register_single (struct frame_info *frame, int regno,
4002 int raw_size = register_size (current_gdbarch, regno);
4003 char *raw_buffer = alloca (raw_size);
4005 if (!frame_register_read (frame, regno, raw_buffer))
4006 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4009 /* We have a 64-bit value for this register. Find the low-order
4013 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4018 memcpy (rare_buffer, raw_buffer + offset, 4);
4022 memcpy (rare_buffer, raw_buffer, 4);
4026 /* Copy a 64-bit double-precision value from the current frame into
4027 rare_buffer. This may include getting half of it from the next
4031 mips_read_fp_register_double (struct frame_info *frame, int regno,
4034 int raw_size = register_size (current_gdbarch, regno);
4036 if (raw_size == 8 && !mips2_fp_compat ())
4038 /* We have a 64-bit value for this register, and we should use
4040 if (!frame_register_read (frame, regno, rare_buffer))
4041 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4045 if ((regno - FP0_REGNUM) & 1)
4046 internal_error (__FILE__, __LINE__,
4047 "mips_read_fp_register_double: bad access to "
4048 "odd-numbered FP register");
4050 /* mips_read_fp_register_single will find the correct 32 bits from
4052 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4054 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4055 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4059 mips_read_fp_register_single (frame, regno, rare_buffer);
4060 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4066 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4068 { /* do values for FP (float) regs */
4070 double doub, flt1, flt2; /* doubles extracted from raw hex data */
4071 int inv1, inv2, namelen;
4073 raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, FP0_REGNUM));
4075 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4076 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4079 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
4081 /* 4-byte registers: Print hex and floating. Also print even
4082 numbered registers as doubles. */
4083 mips_read_fp_register_single (frame, regnum, raw_buffer);
4084 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4086 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file);
4088 fprintf_filtered (file, " flt: ");
4090 fprintf_filtered (file, " <invalid float> ");
4092 fprintf_filtered (file, "%-17.9g", flt1);
4094 if (regnum % 2 == 0)
4096 mips_read_fp_register_double (frame, regnum, raw_buffer);
4097 doub = unpack_double (mips_double_register_type (), raw_buffer,
4100 fprintf_filtered (file, " dbl: ");
4102 fprintf_filtered (file, "<invalid double>");
4104 fprintf_filtered (file, "%-24.17g", doub);
4109 /* Eight byte registers: print each one as hex, float and double. */
4110 mips_read_fp_register_single (frame, regnum, raw_buffer);
4111 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4113 mips_read_fp_register_double (frame, regnum, raw_buffer);
4114 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4117 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file);
4119 fprintf_filtered (file, " flt: ");
4121 fprintf_filtered (file, "<invalid float>");
4123 fprintf_filtered (file, "%-17.9g", flt1);
4125 fprintf_filtered (file, " dbl: ");
4127 fprintf_filtered (file, "<invalid double>");
4129 fprintf_filtered (file, "%-24.17g", doub);
4134 mips_print_register (struct ui_file *file, struct frame_info *frame,
4135 int regnum, int all)
4137 struct gdbarch *gdbarch = get_frame_arch (frame);
4138 char raw_buffer[MAX_REGISTER_SIZE];
4141 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4143 mips_print_fp_register (file, frame, regnum);
4147 /* Get the data in raw format. */
4148 if (!frame_register_read (frame, regnum, raw_buffer))
4150 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4154 fputs_filtered (REGISTER_NAME (regnum), file);
4156 /* The problem with printing numeric register names (r26, etc.) is that
4157 the user can't use them on input. Probably the best solution is to
4158 fix it so that either the numeric or the funky (a2, etc.) names
4159 are accepted on input. */
4160 if (regnum < MIPS_NUMREGS)
4161 fprintf_filtered (file, "(r%d): ", regnum);
4163 fprintf_filtered (file, ": ");
4165 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4166 offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum);
4170 print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum),
4174 /* Replacement for generic do_registers_info.
4175 Print regs in pretty columns. */
4178 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4181 fprintf_filtered (file, " ");
4182 mips_print_fp_register (file, frame, regnum);
4183 fprintf_filtered (file, "\n");
4188 /* Print a row's worth of GP (int) registers, with name labels above */
4191 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4194 struct gdbarch *gdbarch = get_frame_arch (frame);
4195 /* do values for GP (int) regs */
4196 char raw_buffer[MAX_REGISTER_SIZE];
4197 int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4201 /* For GP registers, we print a separate row of names above the vals */
4202 fprintf_filtered (file, " ");
4203 for (col = 0, regnum = start_regnum;
4204 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
4207 if (*REGISTER_NAME (regnum) == '\0')
4208 continue; /* unused register */
4209 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4210 break; /* end the row: reached FP register */
4211 fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4212 REGISTER_NAME (regnum));
4215 /* print the R0 to R31 names */
4216 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4217 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4219 fprintf_filtered (file, "\n ");
4221 /* now print the values in hex, 4 or 8 to the row */
4222 for (col = 0, regnum = start_regnum;
4223 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
4226 if (*REGISTER_NAME (regnum) == '\0')
4227 continue; /* unused register */
4228 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4229 break; /* end row: reached FP register */
4230 /* OK: get the data in raw format. */
4231 if (!frame_register_read (frame, regnum, raw_buffer))
4232 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4233 /* pad small registers */
4235 byte < (mips_regsize (current_gdbarch)
4236 - register_size (current_gdbarch, regnum));
4238 printf_filtered (" ");
4239 /* Now print the register value in hex, endian order. */
4240 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4241 for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum);
4242 byte < register_size (current_gdbarch, regnum);
4244 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4246 for (byte = register_size (current_gdbarch, regnum) - 1;
4249 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4250 fprintf_filtered (file, " ");
4253 if (col > 0) /* ie. if we actually printed anything... */
4254 fprintf_filtered (file, "\n");
4259 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4262 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4263 struct frame_info *frame, int regnum, int all)
4265 if (regnum != -1) /* do one specified register */
4267 gdb_assert (regnum >= NUM_REGS);
4268 if (*(REGISTER_NAME (regnum)) == '\0')
4269 error ("Not a valid register for the current processor type");
4271 mips_print_register (file, frame, regnum, 0);
4272 fprintf_filtered (file, "\n");
4275 /* do all (or most) registers */
4278 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4280 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4282 if (all) /* true for "INFO ALL-REGISTERS" command */
4283 regnum = print_fp_register_row (file, frame, regnum);
4285 regnum += MIPS_NUMREGS; /* skip floating point regs */
4288 regnum = print_gp_register_row (file, frame, regnum);
4293 /* Is this a branch with a delay slot? */
4295 static int is_delayed (unsigned long);
4298 is_delayed (unsigned long insn)
4301 for (i = 0; i < NUMOPCODES; ++i)
4302 if (mips_opcodes[i].pinfo != INSN_MACRO
4303 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4305 return (i < NUMOPCODES
4306 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4307 | INSN_COND_BRANCH_DELAY
4308 | INSN_COND_BRANCH_LIKELY)));
4312 mips_step_skips_delay (CORE_ADDR pc)
4314 char buf[MIPS_INSTLEN];
4316 /* There is no branch delay slot on MIPS16. */
4317 if (pc_is_mips16 (pc))
4320 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4321 /* If error reading memory, guess that it is not a delayed branch. */
4323 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
4327 /* Skip the PC past function prologue instructions (32-bit version).
4328 This is a helper function for mips_skip_prologue. */
4331 mips32_skip_prologue (CORE_ADDR pc)
4335 int seen_sp_adjust = 0;
4336 int load_immediate_bytes = 0;
4338 /* Skip the typical prologue instructions. These are the stack adjustment
4339 instruction and the instructions that save registers on the stack
4340 or in the gcc frame. */
4341 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
4343 unsigned long high_word;
4345 inst = mips_fetch_instruction (pc);
4346 high_word = (inst >> 16) & 0xffff;
4348 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4349 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4351 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4352 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4354 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4355 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4356 && (inst & 0x001F0000)) /* reg != $zero */
4359 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4361 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4363 continue; /* reg != $zero */
4365 /* move $s8,$sp. With different versions of gas this will be either
4366 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4367 Accept any one of these. */
4368 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4371 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4373 else if (high_word == 0x3c1c) /* lui $gp,n */
4375 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4377 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4378 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4380 /* The following instructions load $at or $t0 with an immediate
4381 value in preparation for a stack adjustment via
4382 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4383 a local variable, so we accept them only before a stack adjustment
4384 instruction was seen. */
4385 else if (!seen_sp_adjust)
4387 if (high_word == 0x3c01 || /* lui $at,n */
4388 high_word == 0x3c08) /* lui $t0,n */
4390 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4393 else if (high_word == 0x3421 || /* ori $at,$at,n */
4394 high_word == 0x3508 || /* ori $t0,$t0,n */
4395 high_word == 0x3401 || /* ori $at,$zero,n */
4396 high_word == 0x3408) /* ori $t0,$zero,n */
4398 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4408 /* In a frameless function, we might have incorrectly
4409 skipped some load immediate instructions. Undo the skipping
4410 if the load immediate was not followed by a stack adjustment. */
4411 if (load_immediate_bytes && !seen_sp_adjust)
4412 pc -= load_immediate_bytes;
4416 /* Skip the PC past function prologue instructions (16-bit version).
4417 This is a helper function for mips_skip_prologue. */
4420 mips16_skip_prologue (CORE_ADDR pc)
4423 int extend_bytes = 0;
4424 int prev_extend_bytes;
4426 /* Table of instructions likely to be found in a function prologue. */
4429 unsigned short inst;
4430 unsigned short mask;
4437 , /* addiu $sp,offset */
4441 , /* daddiu $sp,offset */
4445 , /* sw reg,n($sp) */
4449 , /* sd reg,n($sp) */
4453 , /* sw $ra,n($sp) */
4457 , /* sd $ra,n($sp) */
4465 , /* sw $a0-$a3,n($s1) */
4469 , /* move reg,$a0-$a3 */
4473 , /* entry pseudo-op */
4477 , /* addiu $s1,$sp,n */
4480 } /* end of table marker */
4483 /* Skip the typical prologue instructions. These are the stack adjustment
4484 instruction and the instructions that save registers on the stack
4485 or in the gcc frame. */
4486 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
4488 unsigned short inst;
4491 inst = mips_fetch_instruction (pc);
4493 /* Normally we ignore an extend instruction. However, if it is
4494 not followed by a valid prologue instruction, we must adjust
4495 the pc back over the extend so that it won't be considered
4496 part of the prologue. */
4497 if ((inst & 0xf800) == 0xf000) /* extend */
4499 extend_bytes = MIPS16_INSTLEN;
4502 prev_extend_bytes = extend_bytes;
4505 /* Check for other valid prologue instructions besides extend. */
4506 for (i = 0; table[i].mask != 0; i++)
4507 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4509 if (table[i].mask != 0) /* it was in table? */
4510 continue; /* ignore it */
4514 /* Return the current pc, adjusted backwards by 2 if
4515 the previous instruction was an extend. */
4516 return pc - prev_extend_bytes;
4522 /* To skip prologues, I use this predicate. Returns either PC itself
4523 if the code at PC does not look like a function prologue; otherwise
4524 returns an address that (if we're lucky) follows the prologue. If
4525 LENIENT, then we must skip everything which is involved in setting
4526 up the frame (it's OK to skip more, just so long as we don't skip
4527 anything which might clobber the registers which are being saved.
4528 We must skip more in the case where part of the prologue is in the
4529 delay slot of a non-prologue instruction). */
4532 mips_skip_prologue (CORE_ADDR pc)
4534 /* See if we can determine the end of the prologue via the symbol table.
4535 If so, then return either PC, or the PC after the prologue, whichever
4538 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4540 if (post_prologue_pc != 0)
4541 return max (pc, post_prologue_pc);
4543 /* Can't determine prologue from the symbol table, need to examine
4546 if (pc_is_mips16 (pc))
4547 return mips16_skip_prologue (pc);
4549 return mips32_skip_prologue (pc);
4552 /* Determine how a return value is stored within the MIPS register
4553 file, given the return type `valtype'. */
4555 struct return_value_word
4564 return_value_location (struct type *valtype,
4565 struct return_value_word *hi,
4566 struct return_value_word *lo)
4568 int len = TYPE_LENGTH (valtype);
4570 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
4571 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
4572 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
4574 if (!FP_REGISTER_DOUBLE && len == 8)
4576 /* We need to break a 64bit float in two 32 bit halves and
4577 spread them across a floating-point register pair. */
4578 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
4579 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
4580 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4581 && register_size (current_gdbarch, FP0_REGNUM) == 8)
4583 hi->reg_offset = lo->reg_offset;
4584 lo->reg = FP0_REGNUM + 0;
4585 hi->reg = FP0_REGNUM + 1;
4591 /* The floating point value fits in a single floating-point
4593 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4594 && register_size (current_gdbarch, FP0_REGNUM) == 8
4597 lo->reg = FP0_REGNUM;
4608 /* Locate a result possibly spread across two registers. */
4610 lo->reg = regnum + 0;
4611 hi->reg = regnum + 1;
4612 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4613 && len < MIPS_SAVED_REGSIZE)
4615 /* "un-left-justify" the value in the low register */
4616 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
4621 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4622 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
4623 && len < MIPS_SAVED_REGSIZE * 2
4624 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
4625 TYPE_CODE (valtype) == TYPE_CODE_UNION))
4627 /* "un-left-justify" the value spread across two registers. */
4628 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
4629 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
4631 hi->len = len - lo->len;
4635 /* Only perform a partial copy of the second register. */
4638 if (len > MIPS_SAVED_REGSIZE)
4640 lo->len = MIPS_SAVED_REGSIZE;
4641 hi->len = len - MIPS_SAVED_REGSIZE;
4649 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4650 && register_size (current_gdbarch, regnum) == 8
4651 && MIPS_SAVED_REGSIZE == 4)
4653 /* Account for the fact that only the least-signficant part
4654 of the register is being used */
4655 lo->reg_offset += 4;
4656 hi->reg_offset += 4;
4659 hi->buf_offset = lo->len;
4663 /* Given a return value in `regbuf' with a type `valtype', extract and
4664 copy its value into `valbuf'. */
4667 mips_eabi_extract_return_value (struct type *valtype,
4671 struct return_value_word lo;
4672 struct return_value_word hi;
4673 return_value_location (valtype, &hi, &lo);
4675 memcpy (valbuf + lo.buf_offset,
4676 regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset,
4680 memcpy (valbuf + hi.buf_offset,
4681 regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset,
4686 mips_o64_extract_return_value (struct type *valtype,
4690 struct return_value_word lo;
4691 struct return_value_word hi;
4692 return_value_location (valtype, &hi, &lo);
4694 memcpy (valbuf + lo.buf_offset,
4695 regbuf + DEPRECATED_REGISTER_BYTE (lo.reg) + lo.reg_offset,
4699 memcpy (valbuf + hi.buf_offset,
4700 regbuf + DEPRECATED_REGISTER_BYTE (hi.reg) + hi.reg_offset,
4704 /* Given a return value in `valbuf' with a type `valtype', write it's
4705 value into the appropriate register. */
4708 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
4710 char raw_buffer[MAX_REGISTER_SIZE];
4711 struct return_value_word lo;
4712 struct return_value_word hi;
4713 return_value_location (valtype, &hi, &lo);
4715 memset (raw_buffer, 0, sizeof (raw_buffer));
4716 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4717 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
4718 register_size (current_gdbarch, lo.reg));
4722 memset (raw_buffer, 0, sizeof (raw_buffer));
4723 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4724 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
4725 register_size (current_gdbarch, hi.reg));
4730 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4732 char raw_buffer[MAX_REGISTER_SIZE];
4733 struct return_value_word lo;
4734 struct return_value_word hi;
4735 return_value_location (valtype, &hi, &lo);
4737 memset (raw_buffer, 0, sizeof (raw_buffer));
4738 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4739 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
4740 register_size (current_gdbarch, lo.reg));
4744 memset (raw_buffer, 0, sizeof (raw_buffer));
4745 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4746 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
4747 register_size (current_gdbarch, hi.reg));
4751 /* O32 ABI stuff. */
4754 mips_o32_xfer_return_value (struct type *type,
4755 struct regcache *regcache,
4756 bfd_byte *in, const bfd_byte *out)
4758 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4759 if (TYPE_CODE (type) == TYPE_CODE_FLT
4760 && TYPE_LENGTH (type) == 4
4761 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4763 /* A single-precision floating-point value. It fits in the
4764 least significant part of FP0. */
4766 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4767 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type),
4768 TARGET_BYTE_ORDER, in, out, 0);
4770 else if (TYPE_CODE (type) == TYPE_CODE_FLT
4771 && TYPE_LENGTH (type) == 8
4772 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4774 /* A double-precision floating-point value. The most
4775 significant part goes in FP1, and the least significant in
4778 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
4779 switch (TARGET_BYTE_ORDER)
4781 case BFD_ENDIAN_LITTLE:
4782 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4,
4783 TARGET_BYTE_ORDER, in, out, 0);
4784 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4,
4785 TARGET_BYTE_ORDER, in, out, 4);
4787 case BFD_ENDIAN_BIG:
4788 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 1, 4,
4789 TARGET_BYTE_ORDER, in, out, 0);
4790 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM + 0, 4,
4791 TARGET_BYTE_ORDER, in, out, 4);
4794 internal_error (__FILE__, __LINE__, "bad switch");
4798 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4799 && TYPE_NFIELDS (type) <= 2
4800 && TYPE_NFIELDS (type) >= 1
4801 && ((TYPE_NFIELDS (type) == 1
4802 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4804 || (TYPE_NFIELDS (type) == 2
4805 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4807 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4809 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4811 /* A struct that contains one or two floats. Each value is part
4812 in the least significant part of their floating point
4814 bfd_byte reg[MAX_REGISTER_SIZE];
4817 for (field = 0, regnum = FP0_REGNUM;
4818 field < TYPE_NFIELDS (type);
4819 field++, regnum += 2)
4821 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4824 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4825 mips_xfer_register (regcache, NUM_REGS + regnum,
4826 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4827 TARGET_BYTE_ORDER, in, out, offset);
4832 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4833 || TYPE_CODE (type) == TYPE_CODE_UNION)
4835 /* A structure or union. Extract the left justified value,
4836 regardless of the byte order. I.e. DO NOT USE
4840 for (offset = 0, regnum = V0_REGNUM;
4841 offset < TYPE_LENGTH (type);
4842 offset += register_size (current_gdbarch, regnum), regnum++)
4844 int xfer = register_size (current_gdbarch, regnum);
4845 if (offset + xfer > TYPE_LENGTH (type))
4846 xfer = TYPE_LENGTH (type) - offset;
4848 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4849 offset, xfer, regnum);
4850 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4851 BFD_ENDIAN_UNKNOWN, in, out, offset);
4857 /* A scalar extract each part but least-significant-byte
4858 justified. o32 thinks registers are 4 byte, regardless of
4859 the ISA. mips_stack_argsize controls this. */
4862 for (offset = 0, regnum = V0_REGNUM;
4863 offset < TYPE_LENGTH (type);
4864 offset += mips_stack_argsize (), regnum++)
4866 int xfer = mips_stack_argsize ();
4868 if (offset + xfer > TYPE_LENGTH (type))
4869 xfer = TYPE_LENGTH (type) - offset;
4871 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4872 offset, xfer, regnum);
4873 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4874 TARGET_BYTE_ORDER, in, out, offset);
4880 mips_o32_extract_return_value (struct type *type,
4881 struct regcache *regcache,
4884 mips_o32_xfer_return_value (type, regcache, valbuf, NULL);
4888 mips_o32_store_return_value (struct type *type, char *valbuf)
4890 mips_o32_xfer_return_value (type, current_regcache, NULL, valbuf);
4893 /* N32/N44 ABI stuff. */
4896 mips_n32n64_xfer_return_value (struct type *type,
4897 struct regcache *regcache,
4898 bfd_byte *in, const bfd_byte *out)
4900 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4901 if (TYPE_CODE (type) == TYPE_CODE_FLT
4902 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4904 /* A floating-point value belongs in the least significant part
4907 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
4908 mips_xfer_register (regcache, NUM_REGS + FP0_REGNUM, TYPE_LENGTH (type),
4909 TARGET_BYTE_ORDER, in, out, 0);
4911 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4912 && TYPE_NFIELDS (type) <= 2
4913 && TYPE_NFIELDS (type) >= 1
4914 && ((TYPE_NFIELDS (type) == 1
4915 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4917 || (TYPE_NFIELDS (type) == 2
4918 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
4920 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
4922 && tdep->mips_fpu_type != MIPS_FPU_NONE)
4924 /* A struct that contains one or two floats. Each value is part
4925 in the least significant part of their floating point
4927 bfd_byte reg[MAX_REGISTER_SIZE];
4930 for (field = 0, regnum = FP0_REGNUM;
4931 field < TYPE_NFIELDS (type);
4932 field++, regnum += 2)
4934 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
4937 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
4938 mips_xfer_register (regcache, NUM_REGS + regnum,
4939 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
4940 TARGET_BYTE_ORDER, in, out, offset);
4943 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
4944 || TYPE_CODE (type) == TYPE_CODE_UNION)
4946 /* A structure or union. Extract the left justified value,
4947 regardless of the byte order. I.e. DO NOT USE
4951 for (offset = 0, regnum = V0_REGNUM;
4952 offset < TYPE_LENGTH (type);
4953 offset += register_size (current_gdbarch, regnum), regnum++)
4955 int xfer = register_size (current_gdbarch, regnum);
4956 if (offset + xfer > TYPE_LENGTH (type))
4957 xfer = TYPE_LENGTH (type) - offset;
4959 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
4960 offset, xfer, regnum);
4961 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4962 BFD_ENDIAN_UNKNOWN, in, out, offset);
4967 /* A scalar extract each part but least-significant-byte
4971 for (offset = 0, regnum = V0_REGNUM;
4972 offset < TYPE_LENGTH (type);
4973 offset += register_size (current_gdbarch, regnum), regnum++)
4975 int xfer = register_size (current_gdbarch, regnum);
4977 if (offset + xfer > TYPE_LENGTH (type))
4978 xfer = TYPE_LENGTH (type) - offset;
4980 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
4981 offset, xfer, regnum);
4982 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
4983 TARGET_BYTE_ORDER, in, out, offset);
4989 mips_n32n64_extract_return_value (struct type *type,
4990 struct regcache *regcache,
4993 mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL);
4997 mips_n32n64_store_return_value (struct type *type, char *valbuf)
4999 mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf);
5003 mips_extract_struct_value_address (struct regcache *regcache)
5005 /* FIXME: This will only work at random. The caller passes the
5006 struct_return address in V0, but it is not preserved. It may
5007 still be there, or this may be a random value. */
5010 regcache_cooked_read_signed (regcache, V0_REGNUM, &val);
5014 /* Exported procedure: Is PC in the signal trampoline code */
5017 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
5019 if (sigtramp_address == 0)
5021 return (pc >= sigtramp_address && pc < sigtramp_end);
5024 /* Root of all "set mips "/"show mips " commands. This will eventually be
5025 used for all MIPS-specific commands. */
5028 show_mips_command (char *args, int from_tty)
5030 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
5034 set_mips_command (char *args, int from_tty)
5036 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
5037 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
5040 /* Commands to show/set the MIPS FPU type. */
5043 show_mipsfpu_command (char *args, int from_tty)
5046 switch (MIPS_FPU_TYPE)
5048 case MIPS_FPU_SINGLE:
5049 fpu = "single-precision";
5051 case MIPS_FPU_DOUBLE:
5052 fpu = "double-precision";
5055 fpu = "absent (none)";
5058 internal_error (__FILE__, __LINE__, "bad switch");
5060 if (mips_fpu_type_auto)
5061 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5064 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
5070 set_mipsfpu_command (char *args, int from_tty)
5072 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5073 show_mipsfpu_command (args, from_tty);
5077 set_mipsfpu_single_command (char *args, int from_tty)
5079 mips_fpu_type = MIPS_FPU_SINGLE;
5080 mips_fpu_type_auto = 0;
5081 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE;
5085 set_mipsfpu_double_command (char *args, int from_tty)
5087 mips_fpu_type = MIPS_FPU_DOUBLE;
5088 mips_fpu_type_auto = 0;
5089 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE;
5093 set_mipsfpu_none_command (char *args, int from_tty)
5095 mips_fpu_type = MIPS_FPU_NONE;
5096 mips_fpu_type_auto = 0;
5097 gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE;
5101 set_mipsfpu_auto_command (char *args, int from_tty)
5103 mips_fpu_type_auto = 1;
5106 /* Command to set the processor type. */
5109 mips_set_processor_type_command (char *args, int from_tty)
5113 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
5115 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
5116 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5117 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
5119 /* Restore the value. */
5120 tmp_mips_processor_type = xstrdup (mips_processor_type);
5125 if (!mips_set_processor_type (tmp_mips_processor_type))
5127 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
5128 /* Restore its value. */
5129 tmp_mips_processor_type = xstrdup (mips_processor_type);
5134 mips_show_processor_type_command (char *args, int from_tty)
5138 /* Modify the actual processor type. */
5141 mips_set_processor_type (char *str)
5148 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
5150 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
5152 mips_processor_type = str;
5153 mips_processor_reg_names = mips_processor_type_table[i].regnames;
5155 /* FIXME tweak fpu flag too */
5162 /* Attempt to identify the particular processor model by reading the
5166 mips_read_processor_type (void)
5170 prid = read_register (PRID_REGNUM);
5172 if ((prid & ~0xf) == 0x700)
5173 return savestring ("r3041", strlen ("r3041"));
5178 /* Just like reinit_frame_cache, but with the right arguments to be
5179 callable as an sfunc. */
5182 reinit_frame_cache_sfunc (char *args, int from_tty,
5183 struct cmd_list_element *c)
5185 reinit_frame_cache ();
5189 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
5191 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5192 mips_extra_func_info_t proc_desc;
5194 /* Search for the function containing this address. Set the low bit
5195 of the address when searching, in case we were given an even address
5196 that is the start of a 16-bit function. If we didn't do this,
5197 the search would fail because the symbol table says the function
5198 starts at an odd address, i.e. 1 byte past the given address. */
5199 memaddr = ADDR_BITS_REMOVE (memaddr);
5200 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
5202 /* Make an attempt to determine if this is a 16-bit function. If
5203 the procedure descriptor exists and the address therein is odd,
5204 it's definitely a 16-bit function. Otherwise, we have to just
5205 guess that if the address passed in is odd, it's 16-bits. */
5206 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5207 disassembler needs to be able to locally determine the ISA, and
5208 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5212 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
5213 info->mach = bfd_mach_mips16;
5217 if (pc_is_mips16 (memaddr))
5218 info->mach = bfd_mach_mips16;
5221 /* Round down the instruction address to the appropriate boundary. */
5222 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
5224 /* Set the disassembler options. */
5225 if (tdep->mips_abi == MIPS_ABI_N32
5226 || tdep->mips_abi == MIPS_ABI_N64)
5228 /* Set up the disassembler info, so that we get the right
5229 register names from libopcodes. */
5230 if (tdep->mips_abi == MIPS_ABI_N32)
5231 info->disassembler_options = "gpr-names=n32";
5233 info->disassembler_options = "gpr-names=64";
5234 info->flavour = bfd_target_elf_flavour;
5237 /* This string is not recognized explicitly by the disassembler,
5238 but it tells the disassembler to not try to guess the ABI from
5239 the bfd elf headers, such that, if the user overrides the ABI
5240 of a program linked as NewABI, the disassembly will follow the
5241 register naming conventions specified by the user. */
5242 info->disassembler_options = "gpr-names=32";
5244 /* Call the appropriate disassembler based on the target endian-ness. */
5245 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5246 return print_insn_big_mips (memaddr, info);
5248 return print_insn_little_mips (memaddr, info);
5251 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5252 counter value to determine whether a 16- or 32-bit breakpoint should be
5253 used. It returns a pointer to a string of bytes that encode a breakpoint
5254 instruction, stores the length of the string to *lenptr, and adjusts pc
5255 (if necessary) to point to the actual memory location where the
5256 breakpoint should be inserted. */
5258 static const unsigned char *
5259 mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
5261 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5263 if (pc_is_mips16 (*pcptr))
5265 static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5};
5266 *pcptr = unmake_mips16_addr (*pcptr);
5267 *lenptr = sizeof (mips16_big_breakpoint);
5268 return mips16_big_breakpoint;
5272 /* The IDT board uses an unusual breakpoint value, and
5273 sometimes gets confused when it sees the usual MIPS
5274 breakpoint instruction. */
5275 static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd};
5276 static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd};
5277 static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd};
5279 *lenptr = sizeof (big_breakpoint);
5281 if (strcmp (target_shortname, "mips") == 0)
5282 return idt_big_breakpoint;
5283 else if (strcmp (target_shortname, "ddb") == 0
5284 || strcmp (target_shortname, "pmon") == 0
5285 || strcmp (target_shortname, "lsi") == 0)
5286 return pmon_big_breakpoint;
5288 return big_breakpoint;
5293 if (pc_is_mips16 (*pcptr))
5295 static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8};
5296 *pcptr = unmake_mips16_addr (*pcptr);
5297 *lenptr = sizeof (mips16_little_breakpoint);
5298 return mips16_little_breakpoint;
5302 static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0};
5303 static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0};
5304 static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0};
5306 *lenptr = sizeof (little_breakpoint);
5308 if (strcmp (target_shortname, "mips") == 0)
5309 return idt_little_breakpoint;
5310 else if (strcmp (target_shortname, "ddb") == 0
5311 || strcmp (target_shortname, "pmon") == 0
5312 || strcmp (target_shortname, "lsi") == 0)
5313 return pmon_little_breakpoint;
5315 return little_breakpoint;
5320 /* If PC is in a mips16 call or return stub, return the address of the target
5321 PC, which is either the callee or the caller. There are several
5322 cases which must be handled:
5324 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5325 target PC is in $31 ($ra).
5326 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5327 and the target PC is in $2.
5328 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5329 before the jal instruction, this is effectively a call stub
5330 and the the target PC is in $2. Otherwise this is effectively
5331 a return stub and the target PC is in $18.
5333 See the source code for the stubs in gcc/config/mips/mips16.S for
5336 This function implements the SKIP_TRAMPOLINE_CODE macro.
5340 mips_skip_stub (CORE_ADDR pc)
5343 CORE_ADDR start_addr;
5345 /* Find the starting address and name of the function containing the PC. */
5346 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5349 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5350 target PC is in $31 ($ra). */
5351 if (strcmp (name, "__mips16_ret_sf") == 0
5352 || strcmp (name, "__mips16_ret_df") == 0)
5353 return read_signed_register (RA_REGNUM);
5355 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5357 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5358 and the target PC is in $2. */
5359 if (name[19] >= '0' && name[19] <= '9')
5360 return read_signed_register (2);
5362 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5363 before the jal instruction, this is effectively a call stub
5364 and the the target PC is in $2. Otherwise this is effectively
5365 a return stub and the target PC is in $18. */
5366 else if (name[19] == 's' || name[19] == 'd')
5368 if (pc == start_addr)
5370 /* Check if the target of the stub is a compiler-generated
5371 stub. Such a stub for a function bar might have a name
5372 like __fn_stub_bar, and might look like this:
5377 la $1,bar (becomes a lui/addiu pair)
5379 So scan down to the lui/addi and extract the target
5380 address from those two instructions. */
5382 CORE_ADDR target_pc = read_signed_register (2);
5386 /* See if the name of the target function is __fn_stub_*. */
5387 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
5389 if (strncmp (name, "__fn_stub_", 10) != 0
5390 && strcmp (name, "etext") != 0
5391 && strcmp (name, "_etext") != 0)
5394 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5395 The limit on the search is arbitrarily set to 20
5396 instructions. FIXME. */
5397 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5399 inst = mips_fetch_instruction (target_pc);
5400 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5401 pc = (inst << 16) & 0xffff0000; /* high word */
5402 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5403 return pc | (inst & 0xffff); /* low word */
5406 /* Couldn't find the lui/addui pair, so return stub address. */
5410 /* This is the 'return' part of a call stub. The return
5411 address is in $r18. */
5412 return read_signed_register (18);
5415 return 0; /* not a stub */
5419 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5420 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5423 mips_in_call_stub (CORE_ADDR pc, char *name)
5425 CORE_ADDR start_addr;
5427 /* Find the starting address of the function containing the PC. If the
5428 caller didn't give us a name, look it up at the same time. */
5429 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
5432 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5434 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5435 if (name[19] >= '0' && name[19] <= '9')
5437 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5438 before the jal instruction, this is effectively a call stub. */
5439 else if (name[19] == 's' || name[19] == 'd')
5440 return pc == start_addr;
5443 return 0; /* not a stub */
5447 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5448 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5451 mips_in_return_stub (CORE_ADDR pc, char *name)
5453 CORE_ADDR start_addr;
5455 /* Find the starting address of the function containing the PC. */
5456 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5459 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5460 if (strcmp (name, "__mips16_ret_sf") == 0
5461 || strcmp (name, "__mips16_ret_df") == 0)
5464 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5465 i.e. after the jal instruction, this is effectively a return stub. */
5466 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5467 && (name[19] == 's' || name[19] == 'd')
5468 && pc != start_addr)
5471 return 0; /* not a stub */
5475 /* Return non-zero if the PC is in a library helper function that should
5476 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5479 mips_ignore_helper (CORE_ADDR pc)
5483 /* Find the starting address and name of the function containing the PC. */
5484 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5487 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5488 that we want to ignore. */
5489 return (strcmp (name, "__mips16_ret_sf") == 0
5490 || strcmp (name, "__mips16_ret_df") == 0);
5494 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5495 the register stored on the stack (32) is different to its real raw
5496 size (64). The below ensures that registers are fetched from the
5497 stack using their ABI size and then stored into the RAW_BUFFER
5498 using their raw size.
5500 The alternative to adding this function would be to add an ABI
5501 macro - REGISTER_STACK_SIZE(). */
5504 mips_get_saved_register (char *raw_buffer,
5507 struct frame_info *frame,
5509 enum lval_type *lvalp)
5512 enum lval_type lvalx;
5516 /* Always a pseudo. */
5517 gdb_assert (regnum >= NUM_REGS);
5519 /* Make certain that all needed parameters are present. */
5524 if (optimizedp == NULL)
5525 optimizedp = &optimizedx;
5527 if ((regnum % NUM_REGS) == SP_REGNUM)
5528 /* The SP_REGNUM is special, its value is stored in saved_regs.
5529 In fact, it is so special that it can even only be fetched
5530 using a raw register number! Once this code as been converted
5531 to frame-unwind the problem goes away. */
5532 frame_register_unwind (deprecated_get_next_frame_hack (frame),
5533 regnum % NUM_REGS, optimizedp, lvalp, addrp,
5534 &realnumx, raw_buffer);
5536 /* Get it from the next frame. */
5537 frame_register_unwind (deprecated_get_next_frame_hack (frame),
5538 regnum, optimizedp, lvalp, addrp,
5539 &realnumx, raw_buffer);
5542 /* Immediately after a function call, return the saved pc.
5543 Can't always go through the frames for this because on some machines
5544 the new frame is not set up until the new function executes
5545 some instructions. */
5548 mips_saved_pc_after_call (struct frame_info *frame)
5550 return read_signed_register (RA_REGNUM);
5554 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5555 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5558 mips_stab_reg_to_regnum (int num)
5561 if (num >= 0 && num < 32)
5563 else if (num >= 38 && num < 70)
5564 regnum = num + FP0_REGNUM - 38;
5570 /* This will hopefully (eventually) provoke a warning. Should
5571 we be calling complaint() here? */
5572 return NUM_REGS + NUM_PSEUDO_REGS;
5573 return NUM_REGS + regnum;
5577 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5578 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5581 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
5584 if (num >= 0 && num < 32)
5586 else if (num >= 32 && num < 64)
5587 regnum = num + FP0_REGNUM - 32;
5593 /* This will hopefully (eventually) provoke a warning. Should we
5594 be calling complaint() here? */
5595 return NUM_REGS + NUM_PSEUDO_REGS;
5596 return NUM_REGS + regnum;
5600 mips_register_sim_regno (int regnum)
5602 /* Only makes sense to supply raw registers. */
5603 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
5604 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5605 decide if it is valid. Should instead define a standard sim/gdb
5606 register numbering scheme. */
5607 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
5608 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
5611 return LEGACY_SIM_REGNO_IGNORE;
5615 /* Convert an integer into an address. By first converting the value
5616 into a pointer and then extracting it signed, the address is
5617 guarenteed to be correctly sign extended. */
5620 mips_integer_to_address (struct type *type, void *buf)
5622 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5623 LONGEST val = unpack_long (type, buf);
5624 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5625 return extract_signed_integer (tmp,
5626 TYPE_LENGTH (builtin_type_void_data_ptr));
5630 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5632 enum mips_abi *abip = (enum mips_abi *) obj;
5633 const char *name = bfd_get_section_name (abfd, sect);
5635 if (*abip != MIPS_ABI_UNKNOWN)
5638 if (strncmp (name, ".mdebug.", 8) != 0)
5641 if (strcmp (name, ".mdebug.abi32") == 0)
5642 *abip = MIPS_ABI_O32;
5643 else if (strcmp (name, ".mdebug.abiN32") == 0)
5644 *abip = MIPS_ABI_N32;
5645 else if (strcmp (name, ".mdebug.abi64") == 0)
5646 *abip = MIPS_ABI_N64;
5647 else if (strcmp (name, ".mdebug.abiO64") == 0)
5648 *abip = MIPS_ABI_O64;
5649 else if (strcmp (name, ".mdebug.eabi32") == 0)
5650 *abip = MIPS_ABI_EABI32;
5651 else if (strcmp (name, ".mdebug.eabi64") == 0)
5652 *abip = MIPS_ABI_EABI64;
5654 warning ("unsupported ABI %s.", name + 8);
5657 static enum mips_abi
5658 global_mips_abi (void)
5662 for (i = 0; mips_abi_strings[i] != NULL; i++)
5663 if (mips_abi_strings[i] == mips_abi_string)
5664 return (enum mips_abi) i;
5666 internal_error (__FILE__, __LINE__,
5667 "unknown ABI string");
5670 static struct gdbarch *
5671 mips_gdbarch_init (struct gdbarch_info info,
5672 struct gdbarch_list *arches)
5674 struct gdbarch *gdbarch;
5675 struct gdbarch_tdep *tdep;
5677 enum mips_abi mips_abi, found_abi, wanted_abi;
5684 /* First of all, extract the elf_flags, if available. */
5685 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5686 elf_flags = elf_elfheader (info.abfd)->e_flags;
5689 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5690 switch ((elf_flags & EF_MIPS_ABI))
5692 case E_MIPS_ABI_O32:
5693 mips_abi = MIPS_ABI_O32;
5695 case E_MIPS_ABI_O64:
5696 mips_abi = MIPS_ABI_O64;
5698 case E_MIPS_ABI_EABI32:
5699 mips_abi = MIPS_ABI_EABI32;
5701 case E_MIPS_ABI_EABI64:
5702 mips_abi = MIPS_ABI_EABI64;
5705 if ((elf_flags & EF_MIPS_ABI2))
5706 mips_abi = MIPS_ABI_N32;
5708 mips_abi = MIPS_ABI_UNKNOWN;
5712 /* GCC creates a pseudo-section whose name describes the ABI. */
5713 if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5714 bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi);
5716 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5717 Use the ABI from the last architecture if there is one. */
5718 if (info.abfd == NULL && arches != NULL)
5719 mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5721 /* Try the architecture for any hint of the correct ABI. */
5722 if (mips_abi == MIPS_ABI_UNKNOWN
5723 && info.bfd_arch_info != NULL
5724 && info.bfd_arch_info->arch == bfd_arch_mips)
5726 switch (info.bfd_arch_info->mach)
5728 case bfd_mach_mips3900:
5729 mips_abi = MIPS_ABI_EABI32;
5731 case bfd_mach_mips4100:
5732 case bfd_mach_mips5000:
5733 mips_abi = MIPS_ABI_EABI64;
5735 case bfd_mach_mips8000:
5736 case bfd_mach_mips10000:
5737 /* On Irix, ELF64 executables use the N64 ABI. The
5738 pseudo-sections which describe the ABI aren't present
5739 on IRIX. (Even for executables created by gcc.) */
5740 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5741 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5742 mips_abi = MIPS_ABI_N64;
5744 mips_abi = MIPS_ABI_N32;
5749 if (mips_abi == MIPS_ABI_UNKNOWN)
5750 mips_abi = MIPS_ABI_O32;
5752 /* Now that we have found what the ABI for this binary would be,
5753 check whether the user is overriding it. */
5754 found_abi = mips_abi;
5755 wanted_abi = global_mips_abi ();
5756 if (wanted_abi != MIPS_ABI_UNKNOWN)
5757 mips_abi = wanted_abi;
5761 fprintf_unfiltered (gdb_stdlog,
5762 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5764 fprintf_unfiltered (gdb_stdlog,
5765 "mips_gdbarch_init: mips_abi = %d\n",
5767 fprintf_unfiltered (gdb_stdlog,
5768 "mips_gdbarch_init: found_mips_abi = %d\n",
5772 /* try to find a pre-existing architecture */
5773 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5775 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5777 /* MIPS needs to be pedantic about which ABI the object is
5779 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5781 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5783 /* Need to be pedantic about which register virtual size is
5785 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5786 != mips64_transfers_32bit_regs_p)
5788 return arches->gdbarch;
5791 /* Need a new architecture. Fill in a target specific vector. */
5792 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5793 gdbarch = gdbarch_alloc (&info, tdep);
5794 tdep->elf_flags = elf_flags;
5795 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5797 /* Initially set everything according to the default ABI/ISA. */
5798 set_gdbarch_short_bit (gdbarch, 16);
5799 set_gdbarch_int_bit (gdbarch, 32);
5800 set_gdbarch_float_bit (gdbarch, 32);
5801 set_gdbarch_double_bit (gdbarch, 64);
5802 set_gdbarch_long_double_bit (gdbarch, 64);
5803 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5804 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5805 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5806 tdep->found_abi = found_abi;
5807 tdep->mips_abi = mips_abi;
5809 set_gdbarch_elf_make_msymbol_special (gdbarch,
5810 mips_elf_make_msymbol_special);
5813 if (info.osabi == GDB_OSABI_IRIX)
5817 set_gdbarch_num_regs (gdbarch, num_regs);
5818 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5823 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5824 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value);
5825 set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value);
5826 tdep->mips_default_saved_regsize = 4;
5827 tdep->mips_default_stack_argsize = 4;
5828 tdep->mips_fp_register_double = 0;
5829 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5830 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5831 tdep->default_mask_address_p = 0;
5832 set_gdbarch_long_bit (gdbarch, 32);
5833 set_gdbarch_ptr_bit (gdbarch, 32);
5834 set_gdbarch_long_long_bit (gdbarch, 64);
5835 set_gdbarch_deprecated_reg_struct_has_addr
5836 (gdbarch, mips_o32_reg_struct_has_addr);
5837 set_gdbarch_use_struct_convention (gdbarch,
5838 always_use_struct_convention);
5841 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5842 set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value);
5843 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
5844 tdep->mips_default_saved_regsize = 8;
5845 tdep->mips_default_stack_argsize = 8;
5846 tdep->mips_fp_register_double = 1;
5847 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5848 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 4 - 1;
5849 tdep->default_mask_address_p = 0;
5850 set_gdbarch_long_bit (gdbarch, 32);
5851 set_gdbarch_ptr_bit (gdbarch, 32);
5852 set_gdbarch_long_long_bit (gdbarch, 64);
5853 set_gdbarch_deprecated_reg_struct_has_addr
5854 (gdbarch, mips_o32_reg_struct_has_addr);
5855 set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
5857 case MIPS_ABI_EABI32:
5858 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5859 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5860 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5861 tdep->mips_default_saved_regsize = 4;
5862 tdep->mips_default_stack_argsize = 4;
5863 tdep->mips_fp_register_double = 0;
5864 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5865 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5866 tdep->default_mask_address_p = 0;
5867 set_gdbarch_long_bit (gdbarch, 32);
5868 set_gdbarch_ptr_bit (gdbarch, 32);
5869 set_gdbarch_long_long_bit (gdbarch, 64);
5870 set_gdbarch_deprecated_reg_struct_has_addr
5871 (gdbarch, mips_eabi_reg_struct_has_addr);
5872 set_gdbarch_use_struct_convention (gdbarch,
5873 mips_eabi_use_struct_convention);
5875 case MIPS_ABI_EABI64:
5876 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5877 set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
5878 set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
5879 tdep->mips_default_saved_regsize = 8;
5880 tdep->mips_default_stack_argsize = 8;
5881 tdep->mips_fp_register_double = 1;
5882 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5883 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5884 tdep->default_mask_address_p = 0;
5885 set_gdbarch_long_bit (gdbarch, 64);
5886 set_gdbarch_ptr_bit (gdbarch, 64);
5887 set_gdbarch_long_long_bit (gdbarch, 64);
5888 set_gdbarch_deprecated_reg_struct_has_addr
5889 (gdbarch, mips_eabi_reg_struct_has_addr);
5890 set_gdbarch_use_struct_convention (gdbarch,
5891 mips_eabi_use_struct_convention);
5894 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5895 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5896 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5897 tdep->mips_default_saved_regsize = 8;
5898 tdep->mips_default_stack_argsize = 8;
5899 tdep->mips_fp_register_double = 1;
5900 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5901 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5902 tdep->default_mask_address_p = 0;
5903 set_gdbarch_long_bit (gdbarch, 32);
5904 set_gdbarch_ptr_bit (gdbarch, 32);
5905 set_gdbarch_long_long_bit (gdbarch, 64);
5906 set_gdbarch_use_struct_convention (gdbarch,
5907 mips_n32n64_use_struct_convention);
5908 set_gdbarch_deprecated_reg_struct_has_addr
5909 (gdbarch, mips_n32n64_reg_struct_has_addr);
5912 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5913 set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value);
5914 set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value);
5915 tdep->mips_default_saved_regsize = 8;
5916 tdep->mips_default_stack_argsize = 8;
5917 tdep->mips_fp_register_double = 1;
5918 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5919 tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1;
5920 tdep->default_mask_address_p = 0;
5921 set_gdbarch_long_bit (gdbarch, 64);
5922 set_gdbarch_ptr_bit (gdbarch, 64);
5923 set_gdbarch_long_long_bit (gdbarch, 64);
5924 set_gdbarch_use_struct_convention (gdbarch,
5925 mips_n32n64_use_struct_convention);
5926 set_gdbarch_deprecated_reg_struct_has_addr
5927 (gdbarch, mips_n32n64_reg_struct_has_addr);
5930 internal_error (__FILE__, __LINE__,
5931 "unknown ABI in switch");
5934 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5935 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5938 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5939 flag in object files because to do so would make it impossible to
5940 link with libraries compiled without "-gp32". This is
5941 unnecessarily restrictive.
5943 We could solve this problem by adding "-gp32" multilibs to gcc,
5944 but to set this flag before gcc is built with such multilibs will
5945 break too many systems.''
5947 But even more unhelpfully, the default linker output target for
5948 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5949 for 64-bit programs - you need to change the ABI to change this,
5950 and not all gcc targets support that currently. Therefore using
5951 this flag to detect 32-bit mode would do the wrong thing given
5952 the current gcc - it would make GDB treat these 64-bit programs
5953 as 32-bit programs by default. */
5955 /* enable/disable the MIPS FPU */
5956 if (!mips_fpu_type_auto)
5957 tdep->mips_fpu_type = mips_fpu_type;
5958 else if (info.bfd_arch_info != NULL
5959 && info.bfd_arch_info->arch == bfd_arch_mips)
5960 switch (info.bfd_arch_info->mach)
5962 case bfd_mach_mips3900:
5963 case bfd_mach_mips4100:
5964 case bfd_mach_mips4111:
5965 tdep->mips_fpu_type = MIPS_FPU_NONE;
5967 case bfd_mach_mips4650:
5968 tdep->mips_fpu_type = MIPS_FPU_SINGLE;
5971 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5975 tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
5977 /* MIPS version of register names. NOTE: At present the MIPS
5978 register name management is part way between the old -
5979 #undef/#define MIPS_REGISTER_NAMES and the new REGISTER_NAME(nr).
5980 Further work on it is required. */
5981 set_gdbarch_register_name (gdbarch, mips_register_name);
5982 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5983 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
5984 set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
5985 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5987 /* Add/remove bits from an address. The MIPS needs be careful to
5988 ensure that all 32 bit addresses are sign extended to 64 bits. */
5989 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5991 /* There's a mess in stack frame creation. See comments in
5992 blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
5993 set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
5995 /* Map debug register numbers onto internal register numbers. */
5996 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5997 set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5998 set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5999 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
6000 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
6002 /* Initialize a frame */
6003 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs);
6004 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
6006 /* MIPS version of CALL_DUMMY */
6008 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6009 replaced by a command, and all targets will default to on stack
6010 (regardless of the stack's execute status). */
6011 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
6012 set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame);
6013 set_gdbarch_frame_align (gdbarch, mips_frame_align);
6014 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
6015 set_gdbarch_deprecated_register_convertible (gdbarch, mips_register_convertible);
6016 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual);
6017 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, mips_register_convert_to_raw);
6019 set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain);
6020 set_gdbarch_frameless_function_invocation (gdbarch,
6021 generic_frameless_function_invocation_not);
6022 set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc);
6023 set_gdbarch_frame_args_skip (gdbarch, 0);
6025 set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register);
6027 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6028 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
6029 set_gdbarch_decr_pc_after_break (gdbarch, 0);
6031 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
6032 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
6034 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
6035 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
6036 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
6038 set_gdbarch_function_start_offset (gdbarch, 0);
6040 set_gdbarch_register_type (gdbarch, mips_register_type);
6042 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
6043 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
6045 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
6047 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6048 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6049 need to all be folded into the target vector. Since they are
6050 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6051 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6053 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6055 /* Hook in OS ABI-specific overrides, if they have been registered. */
6056 gdbarch_init_osabi (info, gdbarch);
6058 set_gdbarch_extract_struct_value_address (gdbarch,
6059 mips_extract_struct_value_address);
6061 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
6063 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
6064 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
6070 mips_abi_update (char *ignore_args, int from_tty,
6071 struct cmd_list_element *c)
6073 struct gdbarch_info info;
6075 /* Force the architecture to update, and (if it's a MIPS architecture)
6076 mips_gdbarch_init will take care of the rest. */
6077 gdbarch_info_init (&info);
6078 gdbarch_update_p (info);
6081 /* Print out which MIPS ABI is in use. */
6084 show_mips_abi (char *ignore_args, int from_tty)
6086 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
6088 "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6091 enum mips_abi global_abi = global_mips_abi ();
6092 enum mips_abi actual_abi = mips_abi (current_gdbarch);
6093 const char *actual_abi_str = mips_abi_strings[actual_abi];
6095 if (global_abi == MIPS_ABI_UNKNOWN)
6096 printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
6098 else if (global_abi == actual_abi)
6100 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6104 /* Probably shouldn't happen... */
6106 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6108 mips_abi_strings[global_abi]);
6114 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
6116 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
6120 int ef_mips_32bitmode;
6121 /* determine the ISA */
6122 switch (tdep->elf_flags & EF_MIPS_ARCH)
6140 /* determine the size of a pointer */
6141 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
6142 fprintf_unfiltered (file,
6143 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6145 fprintf_unfiltered (file,
6146 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6148 fprintf_unfiltered (file,
6149 "mips_dump_tdep: ef_mips_arch = %d\n",
6151 fprintf_unfiltered (file,
6152 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6154 mips_abi_strings[tdep->mips_abi]);
6155 fprintf_unfiltered (file,
6156 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6157 mips_mask_address_p (),
6158 tdep->default_mask_address_p);
6160 fprintf_unfiltered (file,
6161 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6162 FP_REGISTER_DOUBLE);
6163 fprintf_unfiltered (file,
6164 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6165 MIPS_DEFAULT_FPU_TYPE,
6166 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
6167 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6168 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6170 fprintf_unfiltered (file,
6171 "mips_dump_tdep: MIPS_EABI = %d\n",
6173 fprintf_unfiltered (file,
6174 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
6175 MIPS_LAST_FP_ARG_REGNUM,
6176 MIPS_LAST_FP_ARG_REGNUM - FPA0_REGNUM + 1);
6177 fprintf_unfiltered (file,
6178 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6180 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
6181 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
6182 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
6184 fprintf_unfiltered (file,
6185 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
6186 MIPS_DEFAULT_SAVED_REGSIZE);
6187 fprintf_unfiltered (file,
6188 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
6189 FP_REGISTER_DOUBLE);
6190 fprintf_unfiltered (file,
6191 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
6192 MIPS_DEFAULT_STACK_ARGSIZE);
6193 fprintf_unfiltered (file,
6194 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
6195 MIPS_STACK_ARGSIZE);
6196 fprintf_unfiltered (file,
6197 "mips_dump_tdep: A0_REGNUM = %d\n",
6199 fprintf_unfiltered (file,
6200 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6201 XSTRING (ADDR_BITS_REMOVE(ADDR)));
6202 fprintf_unfiltered (file,
6203 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6204 XSTRING (ATTACH_DETACH));
6205 fprintf_unfiltered (file,
6206 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
6208 fprintf_unfiltered (file,
6209 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
6211 fprintf_unfiltered (file,
6212 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6213 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
6214 fprintf_unfiltered (file,
6215 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6216 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
6217 fprintf_unfiltered (file,
6218 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
6220 fprintf_unfiltered (file,
6221 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
6223 fprintf_unfiltered (file,
6224 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6225 FIRST_EMBED_REGNUM);
6226 fprintf_unfiltered (file,
6227 "mips_dump_tdep: FPA0_REGNUM = %d\n",
6229 fprintf_unfiltered (file,
6230 "mips_dump_tdep: HI_REGNUM = %d\n",
6232 fprintf_unfiltered (file,
6233 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6234 XSTRING (IGNORE_HELPER_CALL (PC)));
6235 fprintf_unfiltered (file,
6236 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6237 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
6238 fprintf_unfiltered (file,
6239 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6240 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
6241 fprintf_unfiltered (file,
6242 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6244 fprintf_unfiltered (file,
6245 "mips_dump_tdep: LO_REGNUM = %d\n",
6247 #ifdef MACHINE_CPROC_FP_OFFSET
6248 fprintf_unfiltered (file,
6249 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6250 MACHINE_CPROC_FP_OFFSET);
6252 #ifdef MACHINE_CPROC_PC_OFFSET
6253 fprintf_unfiltered (file,
6254 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6255 MACHINE_CPROC_PC_OFFSET);
6257 #ifdef MACHINE_CPROC_SP_OFFSET
6258 fprintf_unfiltered (file,
6259 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6260 MACHINE_CPROC_SP_OFFSET);
6262 fprintf_unfiltered (file,
6263 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6265 fprintf_unfiltered (file,
6266 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6267 fprintf_unfiltered (file,
6268 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6269 fprintf_unfiltered (file,
6270 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6272 fprintf_unfiltered (file,
6273 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6274 MIPS_LAST_ARG_REGNUM,
6275 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
6276 fprintf_unfiltered (file,
6277 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6279 fprintf_unfiltered (file,
6280 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6281 fprintf_unfiltered (file,
6282 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6283 MIPS_SAVED_REGSIZE);
6284 fprintf_unfiltered (file,
6285 "mips_dump_tdep: PRID_REGNUM = %d\n",
6287 fprintf_unfiltered (file,
6288 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6289 fprintf_unfiltered (file,
6290 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6291 fprintf_unfiltered (file,
6292 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6293 fprintf_unfiltered (file,
6294 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6295 fprintf_unfiltered (file,
6296 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6297 fprintf_unfiltered (file,
6298 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6299 fprintf_unfiltered (file,
6300 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6301 fprintf_unfiltered (file,
6302 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6303 fprintf_unfiltered (file,
6304 "mips_dump_tdep: PROC_PC_REG = function?\n");
6305 fprintf_unfiltered (file,
6306 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6307 fprintf_unfiltered (file,
6308 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6309 fprintf_unfiltered (file,
6310 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6311 fprintf_unfiltered (file,
6312 "mips_dump_tdep: PS_REGNUM = %d\n",
6314 fprintf_unfiltered (file,
6315 "mips_dump_tdep: RA_REGNUM = %d\n",
6318 fprintf_unfiltered (file,
6319 "mips_dump_tdep: SAVED_BYTES = %d\n",
6323 fprintf_unfiltered (file,
6324 "mips_dump_tdep: SAVED_FP = %d\n",
6328 fprintf_unfiltered (file,
6329 "mips_dump_tdep: SAVED_PC = %d\n",
6332 fprintf_unfiltered (file,
6333 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6334 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6335 fprintf_unfiltered (file,
6336 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6337 fprintf_unfiltered (file,
6338 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6340 fprintf_unfiltered (file,
6341 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6342 SIGFRAME_FPREGSAVE_OFF);
6343 fprintf_unfiltered (file,
6344 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6346 fprintf_unfiltered (file,
6347 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6348 SIGFRAME_REGSAVE_OFF);
6349 fprintf_unfiltered (file,
6350 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6352 fprintf_unfiltered (file,
6353 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6354 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6355 fprintf_unfiltered (file,
6356 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6357 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6358 fprintf_unfiltered (file,
6359 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6360 SOFTWARE_SINGLE_STEP_P ());
6361 fprintf_unfiltered (file,
6362 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6363 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6364 #ifdef STACK_END_ADDR
6365 fprintf_unfiltered (file,
6366 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6369 fprintf_unfiltered (file,
6370 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6371 XSTRING (STEP_SKIPS_DELAY (PC)));
6372 fprintf_unfiltered (file,
6373 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6374 STEP_SKIPS_DELAY_P);
6375 fprintf_unfiltered (file,
6376 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6377 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6378 fprintf_unfiltered (file,
6379 "mips_dump_tdep: T9_REGNUM = %d\n",
6381 fprintf_unfiltered (file,
6382 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6383 fprintf_unfiltered (file,
6384 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6385 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
6386 fprintf_unfiltered (file,
6387 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6388 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6390 fprintf_unfiltered (file,
6391 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6392 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6395 fprintf_unfiltered (file,
6396 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6399 #ifdef TRACE_FLAVOR_SIZE
6400 fprintf_unfiltered (file,
6401 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6405 fprintf_unfiltered (file,
6406 "mips_dump_tdep: TRACE_SET # %s\n",
6407 XSTRING (TRACE_SET (X,STATE)));
6409 #ifdef UNUSED_REGNUM
6410 fprintf_unfiltered (file,
6411 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6414 fprintf_unfiltered (file,
6415 "mips_dump_tdep: V0_REGNUM = %d\n",
6417 fprintf_unfiltered (file,
6418 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6419 (long) VM_MIN_ADDRESS);
6420 fprintf_unfiltered (file,
6421 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6423 fprintf_unfiltered (file,
6424 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6428 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6431 _initialize_mips_tdep (void)
6433 static struct cmd_list_element *mipsfpulist = NULL;
6434 struct cmd_list_element *c;
6436 mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
6437 if (MIPS_ABI_LAST + 1
6438 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6439 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6441 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6443 /* Add root prefix command for all "set mips"/"show mips" commands */
6444 add_prefix_cmd ("mips", no_class, set_mips_command,
6445 "Various MIPS specific commands.",
6446 &setmipscmdlist, "set mips ", 0, &setlist);
6448 add_prefix_cmd ("mips", no_class, show_mips_command,
6449 "Various MIPS specific commands.",
6450 &showmipscmdlist, "show mips ", 0, &showlist);
6452 /* Allow the user to override the saved register size. */
6453 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6456 &mips_saved_regsize_string, "\
6457 Set size of general purpose registers saved on the stack.\n\
6458 This option can be set to one of:\n\
6459 32 - Force GDB to treat saved GP registers as 32-bit\n\
6460 64 - Force GDB to treat saved GP registers as 64-bit\n\
6461 auto - Allow GDB to use the target's default setting or autodetect the\n\
6462 saved GP register size from information contained in the executable.\n\
6467 /* Allow the user to override the argument stack size. */
6468 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6471 &mips_stack_argsize_string, "\
6472 Set the amount of stack space reserved for each argument.\n\
6473 This option can be set to one of:\n\
6474 32 - Force GDB to allocate 32-bit chunks per argument\n\
6475 64 - Force GDB to allocate 64-bit chunks per argument\n\
6476 auto - Allow GDB to determine the correct setting from the current\n\
6477 target and executable (default)",
6481 /* Allow the user to override the ABI. */
6482 c = add_set_enum_cmd
6483 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6484 "Set the ABI used by this program.\n"
6485 "This option can be set to one of:\n"
6486 " auto - the default ABI associated with the current binary\n"
6494 set_cmd_sfunc (c, mips_abi_update);
6495 add_cmd ("abi", class_obscure, show_mips_abi,
6496 "Show ABI in use by MIPS target", &showmipscmdlist);
6498 /* Let the user turn off floating point and set the fence post for
6499 heuristic_proc_start. */
6501 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6502 "Set use of MIPS floating-point coprocessor.",
6503 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6504 add_cmd ("single", class_support, set_mipsfpu_single_command,
6505 "Select single-precision MIPS floating-point coprocessor.",
6507 add_cmd ("double", class_support, set_mipsfpu_double_command,
6508 "Select double-precision MIPS floating-point coprocessor.",
6510 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6511 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6512 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6513 add_cmd ("none", class_support, set_mipsfpu_none_command,
6514 "Select no MIPS floating-point coprocessor.",
6516 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6517 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6518 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6519 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6520 "Select MIPS floating-point coprocessor automatically.",
6522 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6523 "Show current use of MIPS floating-point coprocessor target.",
6526 /* We really would like to have both "0" and "unlimited" work, but
6527 command.c doesn't deal with that. So make it a var_zinteger
6528 because the user can always use "999999" or some such for unlimited. */
6529 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6530 (char *) &heuristic_fence_post,
6532 Set the distance searched for the start of a function.\n\
6533 If you are debugging a stripped executable, GDB needs to search through the\n\
6534 program for the start of a function. This command sets the distance of the\n\
6535 search. The only need to set it is when debugging a stripped executable.",
6537 /* We need to throw away the frame cache when we set this, since it
6538 might change our ability to get backtraces. */
6539 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6540 add_show_from_set (c, &showlist);
6542 /* Allow the user to control whether the upper bits of 64-bit
6543 addresses should be zeroed. */
6544 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6545 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6546 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6547 allow GDB to determine the correct value.\n", "\
6548 Show zeroing of upper 32 bits of 64-bit addresses.",
6549 NULL, show_mask_address,
6550 &setmipscmdlist, &showmipscmdlist);
6552 /* Allow the user to control the size of 32 bit registers within the
6553 raw remote packet. */
6554 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6555 var_boolean, &mips64_transfers_32bit_regs_p, "\
6556 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6557 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6558 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6559 64 bits for others. Use \"off\" to disable compatibility mode", "\
6560 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6561 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6562 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6563 64 bits for others. Use \"off\" to disable compatibility mode",
6564 set_mips64_transfers_32bit_regs, NULL,
6565 &setlist, &showlist);
6567 /* Debug this files internals. */
6568 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6569 &mips_debug, "Set mips debugging.\n\
6570 When non-zero, mips specific debugging is enabled.", &setdebuglist),