1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "reggroups.h"
64 /* If the kernel has to deliver a signal, it pushes a sigcontext
65 structure on the stack and then calls the signal handler, passing
66 the address of the sigcontext in an argument register. Usually
67 the signal handler doesn't save this register, so we have to
68 access the sigcontext structure via an offset from the signal handler
70 The following constants were determined by experimentation on AIX 3.2. */
71 #define SIG_FRAME_PC_OFFSET 96
72 #define SIG_FRAME_LR_OFFSET 108
73 #define SIG_FRAME_FP_OFFSET 284
75 /* To be used by skip_prologue. */
77 struct rs6000_framedata
79 int offset; /* total size of frame --- the distance
80 by which we decrement sp to allocate
82 int saved_gpr; /* smallest # of saved gpr */
83 int saved_fpr; /* smallest # of saved fpr */
84 int saved_vr; /* smallest # of saved vr */
85 int saved_ev; /* smallest # of saved ev */
86 int alloca_reg; /* alloca register number (frame ptr) */
87 char frameless; /* true if frameless functions. */
88 char nosavedpc; /* true if pc not saved. */
89 int gpr_offset; /* offset of saved gprs from prev sp */
90 int fpr_offset; /* offset of saved fprs from prev sp */
91 int vr_offset; /* offset of saved vrs from prev sp */
92 int ev_offset; /* offset of saved evs from prev sp */
93 int lr_offset; /* offset of saved lr */
94 int cr_offset; /* offset of saved cr */
95 int vrsave_offset; /* offset of saved vrsave register */
98 /* Description of a single register. */
102 char *name; /* name of register */
103 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
104 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
105 unsigned char fpr; /* whether register is floating-point */
106 unsigned char pseudo; /* whether register is pseudo */
107 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
108 This is an ISA SPR number, not a GDB
112 /* Breakpoint shadows for the single step instructions will be kept here. */
114 static struct sstep_breaks
116 /* Address, or 0 if this is not in use. */
118 /* Shadow contents. */
123 /* Hook for determining the TOC address when calling functions in the
124 inferior under AIX. The initialization code in rs6000-nat.c sets
125 this hook to point to find_toc_address. */
127 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
129 /* Hook to set the current architecture when starting a child process.
130 rs6000-nat.c sets this. */
132 void (*rs6000_set_host_arch_hook) (int) = NULL;
134 /* Static function prototypes */
136 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
138 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
139 struct rs6000_framedata *);
141 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
143 altivec_register_p (int regno)
145 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
146 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
149 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
153 /* Return true if REGNO is an SPE register, false otherwise. */
155 spe_register_p (int regno)
157 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
159 /* Is it a reference to EV0 -- EV31, and do we have those? */
160 if (tdep->ppc_ev0_regnum >= 0
161 && tdep->ppc_ev31_regnum >= 0
162 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
165 /* Is it a reference to one of the raw upper GPR halves? */
166 if (tdep->ppc_ev0_upper_regnum >= 0
167 && tdep->ppc_ev0_upper_regnum <= regno
168 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
171 /* Is it a reference to the 64-bit accumulator, and do we have that? */
172 if (tdep->ppc_acc_regnum >= 0
173 && tdep->ppc_acc_regnum == regno)
176 /* Is it a reference to the SPE floating-point status and control register,
177 and do we have that? */
178 if (tdep->ppc_spefscr_regnum >= 0
179 && tdep->ppc_spefscr_regnum == regno)
186 /* Return non-zero if the architecture described by GDBARCH has
187 floating-point registers (f0 --- f31 and fpscr). */
189 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 return (tdep->ppc_fp0_regnum >= 0
194 && tdep->ppc_fpscr_regnum >= 0);
198 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
201 This is a helper function for init_sim_regno_table, constructing
202 the table mapping GDB register numbers to sim register numbers; we
203 initialize every element in that table to -1 before we start
206 set_sim_regno (int *table, int gdb_regno, int sim_regno)
208 /* Make sure we don't try to assign any given GDB register a sim
209 register number more than once. */
210 gdb_assert (table[gdb_regno] == -1);
211 table[gdb_regno] = sim_regno;
215 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
216 numbers to simulator register numbers, based on the values placed
217 in the ARCH->tdep->ppc_foo_regnum members. */
219 init_sim_regno_table (struct gdbarch *arch)
221 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
222 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
223 const struct reg *regs = tdep->regs;
224 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
227 /* Presume that all registers not explicitly mentioned below are
228 unavailable from the sim. */
229 for (i = 0; i < total_regs; i++)
232 /* General-purpose registers. */
233 for (i = 0; i < ppc_num_gprs; i++)
234 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
236 /* Floating-point registers. */
237 if (tdep->ppc_fp0_regnum >= 0)
238 for (i = 0; i < ppc_num_fprs; i++)
239 set_sim_regno (sim_regno,
240 tdep->ppc_fp0_regnum + i,
241 sim_ppc_f0_regnum + i);
242 if (tdep->ppc_fpscr_regnum >= 0)
243 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
245 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
246 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
247 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
249 /* Segment registers. */
250 if (tdep->ppc_sr0_regnum >= 0)
251 for (i = 0; i < ppc_num_srs; i++)
252 set_sim_regno (sim_regno,
253 tdep->ppc_sr0_regnum + i,
254 sim_ppc_sr0_regnum + i);
256 /* Altivec registers. */
257 if (tdep->ppc_vr0_regnum >= 0)
259 for (i = 0; i < ppc_num_vrs; i++)
260 set_sim_regno (sim_regno,
261 tdep->ppc_vr0_regnum + i,
262 sim_ppc_vr0_regnum + i);
264 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
265 we can treat this more like the other cases. */
266 set_sim_regno (sim_regno,
267 tdep->ppc_vr0_regnum + ppc_num_vrs,
268 sim_ppc_vscr_regnum);
270 /* vsave is a special-purpose register, so the code below handles it. */
272 /* SPE APU (E500) registers. */
273 if (tdep->ppc_ev0_regnum >= 0)
274 for (i = 0; i < ppc_num_gprs; i++)
275 set_sim_regno (sim_regno,
276 tdep->ppc_ev0_regnum + i,
277 sim_ppc_ev0_regnum + i);
278 if (tdep->ppc_ev0_upper_regnum >= 0)
279 for (i = 0; i < ppc_num_gprs; i++)
280 set_sim_regno (sim_regno,
281 tdep->ppc_ev0_upper_regnum + i,
282 sim_ppc_rh0_regnum + i);
283 if (tdep->ppc_acc_regnum >= 0)
284 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
285 /* spefscr is a special-purpose register, so the code below handles it. */
287 /* Now handle all special-purpose registers. Verify that they
288 haven't mistakenly been assigned numbers by any of the above
290 for (i = 0; i < total_regs; i++)
291 if (regs[i].spr_num >= 0)
292 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
294 /* Drop the initialized array into place. */
295 tdep->sim_regno = sim_regno;
299 /* Given a GDB register number REG, return the corresponding SIM
302 rs6000_register_sim_regno (int reg)
304 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
307 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
308 sim_regno = tdep->sim_regno[reg];
313 return LEGACY_SIM_REGNO_IGNORE;
318 /* Register set support functions. */
321 ppc_supply_reg (struct regcache *regcache, int regnum,
322 const gdb_byte *regs, size_t offset)
324 if (regnum != -1 && offset != -1)
325 regcache_raw_supply (regcache, regnum, regs + offset);
329 ppc_collect_reg (const struct regcache *regcache, int regnum,
330 gdb_byte *regs, size_t offset)
332 if (regnum != -1 && offset != -1)
333 regcache_raw_collect (regcache, regnum, regs + offset);
336 /* Supply register REGNUM in the general-purpose register set REGSET
337 from the buffer specified by GREGS and LEN to register cache
338 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
341 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
342 int regnum, const void *gregs, size_t len)
344 struct gdbarch *gdbarch = get_regcache_arch (regcache);
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 const struct ppc_reg_offsets *offsets = regset->descr;
350 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
351 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
354 if (regnum == -1 || regnum == i)
355 ppc_supply_reg (regcache, i, gregs, offset);
358 if (regnum == -1 || regnum == PC_REGNUM)
359 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
360 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
361 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
362 gregs, offsets->ps_offset);
363 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
364 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
365 gregs, offsets->cr_offset);
366 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
367 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
368 gregs, offsets->lr_offset);
369 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
370 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
371 gregs, offsets->ctr_offset);
372 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
373 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
374 gregs, offsets->cr_offset);
375 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
376 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
379 /* Supply register REGNUM in the floating-point register set REGSET
380 from the buffer specified by FPREGS and LEN to register cache
381 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
384 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
385 int regnum, const void *fpregs, size_t len)
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
389 const struct ppc_reg_offsets *offsets = regset->descr;
393 gdb_assert (ppc_floating_point_unit_p (gdbarch));
395 offset = offsets->f0_offset;
396 for (i = tdep->ppc_fp0_regnum;
397 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
400 if (regnum == -1 || regnum == i)
401 ppc_supply_reg (regcache, i, fpregs, offset);
404 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
405 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
406 fpregs, offsets->fpscr_offset);
409 /* Collect register REGNUM in the general-purpose register set
410 REGSET. from register cache REGCACHE into the buffer specified by
411 GREGS and LEN. If REGNUM is -1, do this for all registers in
415 ppc_collect_gregset (const struct regset *regset,
416 const struct regcache *regcache,
417 int regnum, void *gregs, size_t len)
419 struct gdbarch *gdbarch = get_regcache_arch (regcache);
420 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
421 const struct ppc_reg_offsets *offsets = regset->descr;
425 offset = offsets->r0_offset;
426 for (i = tdep->ppc_gp0_regnum;
427 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
430 if (regnum == -1 || regnum == i)
431 ppc_collect_reg (regcache, i, gregs, offset);
434 if (regnum == -1 || regnum == PC_REGNUM)
435 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
436 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
437 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
438 gregs, offsets->ps_offset);
439 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
440 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
441 gregs, offsets->cr_offset);
442 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
443 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
444 gregs, offsets->lr_offset);
445 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
446 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
447 gregs, offsets->ctr_offset);
448 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
449 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
450 gregs, offsets->xer_offset);
451 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
452 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
453 gregs, offsets->mq_offset);
456 /* Collect register REGNUM in the floating-point register set
457 REGSET. from register cache REGCACHE into the buffer specified by
458 FPREGS and LEN. If REGNUM is -1, do this for all registers in
462 ppc_collect_fpregset (const struct regset *regset,
463 const struct regcache *regcache,
464 int regnum, void *fpregs, size_t len)
466 struct gdbarch *gdbarch = get_regcache_arch (regcache);
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 const struct ppc_reg_offsets *offsets = regset->descr;
472 gdb_assert (ppc_floating_point_unit_p (gdbarch));
474 offset = offsets->f0_offset;
475 for (i = tdep->ppc_fp0_regnum;
476 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
479 if (regnum == -1 || regnum == i)
480 ppc_collect_reg (regcache, i, fpregs, offset);
483 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
484 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
485 fpregs, offsets->fpscr_offset);
489 /* Read a LEN-byte address from debugged memory address MEMADDR. */
492 read_memory_addr (CORE_ADDR memaddr, int len)
494 return read_memory_unsigned_integer (memaddr, len);
498 rs6000_skip_prologue (CORE_ADDR pc)
500 struct rs6000_framedata frame;
501 pc = skip_prologue (pc, 0, &frame);
506 /* Fill in fi->saved_regs */
508 struct frame_extra_info
510 /* Functions calling alloca() change the value of the stack
511 pointer. We need to use initial stack pointer (which is saved in
512 r31 by gcc) in such cases. If a compiler emits traceback table,
513 then we should use the alloca register specified in traceback
515 CORE_ADDR initial_sp; /* initial stack pointer. */
518 /* Get the ith function argument for the current function. */
520 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
523 return get_frame_register_unsigned (frame, 3 + argi);
526 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
529 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
536 absolute = (int) ((instr >> 1) & 1);
541 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
545 dest = pc + immediate;
549 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
553 dest = pc + immediate;
557 ext_op = (instr >> 1) & 0x3ff;
559 if (ext_op == 16) /* br conditional register */
561 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
563 /* If we are about to return from a signal handler, dest is
564 something like 0x3c90. The current frame is a signal handler
565 caller frame, upon completion of the sigreturn system call
566 execution will return to the saved PC in the frame. */
567 if (dest < TEXT_SEGMENT_BASE)
569 struct frame_info *fi;
571 fi = get_current_frame ();
573 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
574 gdbarch_tdep (current_gdbarch)->wordsize);
578 else if (ext_op == 528) /* br cond to count reg */
580 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
582 /* If we are about to execute a system call, dest is something
583 like 0x22fc or 0x3b00. Upon completion the system call
584 will return to the address in the link register. */
585 if (dest < TEXT_SEGMENT_BASE)
586 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
595 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
599 /* Sequence of bytes for breakpoint instruction. */
601 const static unsigned char *
602 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
604 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
605 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
607 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
608 return big_breakpoint;
610 return little_breakpoint;
614 /* AIX does not support PT_STEP. Simulate it. */
617 rs6000_software_single_step (enum target_signal signal,
618 int insert_breakpoints_p)
622 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
628 if (insert_breakpoints_p)
633 insn = read_memory_integer (loc, 4);
635 breaks[0] = loc + breakp_sz;
637 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
639 /* Don't put two breakpoints on the same address. */
640 if (breaks[1] == breaks[0])
643 stepBreaks[1].address = 0;
645 for (ii = 0; ii < 2; ++ii)
648 /* ignore invalid breakpoint. */
649 if (breaks[ii] == -1)
651 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
652 stepBreaks[ii].address = breaks[ii];
659 /* remove step breakpoints. */
660 for (ii = 0; ii < 2; ++ii)
661 if (stepBreaks[ii].address != 0)
662 target_remove_breakpoint (stepBreaks[ii].address,
663 stepBreaks[ii].data);
665 errno = 0; /* FIXME, don't ignore errors! */
666 /* What errors? {read,write}_memory call error(). */
670 /* return pc value after skipping a function prologue and also return
671 information about a function frame.
673 in struct rs6000_framedata fdata:
674 - frameless is TRUE, if function does not have a frame.
675 - nosavedpc is TRUE, if function does not save %pc value in its frame.
676 - offset is the initial size of this stack frame --- the amount by
677 which we decrement the sp to allocate the frame.
678 - saved_gpr is the number of the first saved gpr.
679 - saved_fpr is the number of the first saved fpr.
680 - saved_vr is the number of the first saved vr.
681 - saved_ev is the number of the first saved ev.
682 - alloca_reg is the number of the register used for alloca() handling.
684 - gpr_offset is the offset of the first saved gpr from the previous frame.
685 - fpr_offset is the offset of the first saved fpr from the previous frame.
686 - vr_offset is the offset of the first saved vr from the previous frame.
687 - ev_offset is the offset of the first saved ev from the previous frame.
688 - lr_offset is the offset of the saved lr
689 - cr_offset is the offset of the saved cr
690 - vrsave_offset is the offset of the saved vrsave register
693 #define SIGNED_SHORT(x) \
694 ((sizeof (short) == 2) \
695 ? ((int)(short)(x)) \
696 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
698 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
700 /* Limit the number of skipped non-prologue instructions, as the examining
701 of the prologue is expensive. */
702 static int max_skip_non_prologue_insns = 10;
704 /* Given PC representing the starting address of a function, and
705 LIM_PC which is the (sloppy) limit to which to scan when looking
706 for a prologue, attempt to further refine this limit by using
707 the line data in the symbol table. If successful, a better guess
708 on where the prologue ends is returned, otherwise the previous
709 value of lim_pc is returned. */
711 /* FIXME: cagney/2004-02-14: This function and logic have largely been
712 superseded by skip_prologue_using_sal. */
715 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
717 struct symtab_and_line prologue_sal;
719 prologue_sal = find_pc_line (pc, 0);
720 if (prologue_sal.line != 0)
723 CORE_ADDR addr = prologue_sal.end;
725 /* Handle the case in which compiler's optimizer/scheduler
726 has moved instructions into the prologue. We scan ahead
727 in the function looking for address ranges whose corresponding
728 line number is less than or equal to the first one that we
729 found for the function. (It can be less than when the
730 scheduler puts a body instruction before the first prologue
732 for (i = 2 * max_skip_non_prologue_insns;
733 i > 0 && (lim_pc == 0 || addr < lim_pc);
736 struct symtab_and_line sal;
738 sal = find_pc_line (addr, 0);
741 if (sal.line <= prologue_sal.line
742 && sal.symtab == prologue_sal.symtab)
749 if (lim_pc == 0 || prologue_sal.end < lim_pc)
750 lim_pc = prologue_sal.end;
755 /* Return nonzero if the given instruction OP can be part of the prologue
756 of a function and saves a parameter on the stack. FRAMEP should be
757 set if one of the previous instructions in the function has set the
761 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
763 /* Move parameters from argument registers to temporary register. */
764 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
766 /* Rx must be scratch register r0. */
767 const int rx_regno = (op >> 16) & 31;
768 /* Ry: Only r3 - r10 are used for parameter passing. */
769 const int ry_regno = GET_SRC_REG (op);
771 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
773 *r0_contains_arg = 1;
780 /* Save a General Purpose Register on stack. */
782 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
783 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
785 /* Rx: Only r3 - r10 are used for parameter passing. */
786 const int rx_regno = GET_SRC_REG (op);
788 return (rx_regno >= 3 && rx_regno <= 10);
791 /* Save a General Purpose Register on stack via the Frame Pointer. */
794 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
795 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
796 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
798 /* Rx: Usually, only r3 - r10 are used for parameter passing.
799 However, the compiler sometimes uses r0 to hold an argument. */
800 const int rx_regno = GET_SRC_REG (op);
802 return ((rx_regno >= 3 && rx_regno <= 10)
803 || (rx_regno == 0 && *r0_contains_arg));
806 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
808 /* Only f2 - f8 are used for parameter passing. */
809 const int src_regno = GET_SRC_REG (op);
811 return (src_regno >= 2 && src_regno <= 8);
814 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
816 /* Only f2 - f8 are used for parameter passing. */
817 const int src_regno = GET_SRC_REG (op);
819 return (src_regno >= 2 && src_regno <= 8);
822 /* Not an insn that saves a parameter on stack. */
827 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
829 CORE_ADDR orig_pc = pc;
830 CORE_ADDR last_prologue_pc = pc;
831 CORE_ADDR li_found_pc = 0;
835 long vr_saved_offset = 0;
844 int minimal_toc_loaded = 0;
845 int prev_insn_was_prologue_insn = 1;
846 int num_skip_non_prologue_insns = 0;
847 int r0_contains_arg = 0;
848 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
849 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
851 /* Attempt to find the end of the prologue when no limit is specified.
852 Note that refine_prologue_limit() has been written so that it may
853 be used to "refine" the limits of non-zero PC values too, but this
854 is only safe if we 1) trust the line information provided by the
855 compiler and 2) iterate enough to actually find the end of the
858 It may become a good idea at some point (for both performance and
859 accuracy) to unconditionally call refine_prologue_limit(). But,
860 until we can make a clear determination that this is beneficial,
861 we'll play it safe and only use it to obtain a limit when none
862 has been specified. */
864 lim_pc = refine_prologue_limit (pc, lim_pc);
866 memset (fdata, 0, sizeof (struct rs6000_framedata));
867 fdata->saved_gpr = -1;
868 fdata->saved_fpr = -1;
869 fdata->saved_vr = -1;
870 fdata->saved_ev = -1;
871 fdata->alloca_reg = -1;
872 fdata->frameless = 1;
873 fdata->nosavedpc = 1;
877 /* Sometimes it isn't clear if an instruction is a prologue
878 instruction or not. When we encounter one of these ambiguous
879 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
880 Otherwise, we'll assume that it really is a prologue instruction. */
881 if (prev_insn_was_prologue_insn)
882 last_prologue_pc = pc;
884 /* Stop scanning if we've hit the limit. */
885 if (lim_pc != 0 && pc >= lim_pc)
888 prev_insn_was_prologue_insn = 1;
890 /* Fetch the instruction and convert it to an integer. */
891 if (target_read_memory (pc, buf, 4))
893 op = extract_signed_integer (buf, 4);
895 if ((op & 0xfc1fffff) == 0x7c0802a6)
897 /* Since shared library / PIC code, which needs to get its
898 address at runtime, can appear to save more than one link
912 remember just the first one, but skip over additional
915 lr_reg = (op & 0x03e00000);
920 else if ((op & 0xfc1fffff) == 0x7c000026)
922 cr_reg = (op & 0x03e00000);
928 else if ((op & 0xfc1f0000) == 0xd8010000)
929 { /* stfd Rx,NUM(r1) */
930 reg = GET_SRC_REG (op);
931 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
933 fdata->saved_fpr = reg;
934 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
939 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
940 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
941 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
942 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
945 reg = GET_SRC_REG (op);
946 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
948 fdata->saved_gpr = reg;
949 if ((op & 0xfc1f0003) == 0xf8010000)
951 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
956 else if ((op & 0xffff0000) == 0x60000000)
959 /* Allow nops in the prologue, but do not consider them to
960 be part of the prologue unless followed by other prologue
962 prev_insn_was_prologue_insn = 0;
966 else if ((op & 0xffff0000) == 0x3c000000)
967 { /* addis 0,0,NUM, used
969 fdata->offset = (op & 0x0000ffff) << 16;
970 fdata->frameless = 0;
975 else if ((op & 0xffff0000) == 0x60000000)
976 { /* ori 0,0,NUM, 2nd ha
977 lf of >= 32k frames */
978 fdata->offset |= (op & 0x0000ffff);
979 fdata->frameless = 0;
984 else if (lr_reg >= 0 &&
985 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
986 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
987 /* stw Rx, NUM(r1) */
988 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
989 /* stwu Rx, NUM(r1) */
990 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
991 { /* where Rx == lr */
992 fdata->lr_offset = offset;
993 fdata->nosavedpc = 0;
994 /* Invalidate lr_reg, but don't set it to -1.
995 That would mean that it had never been set. */
997 if ((op & 0xfc000003) == 0xf8000000 || /* std */
998 (op & 0xfc000000) == 0x90000000) /* stw */
1000 /* Does not update r1, so add displacement to lr_offset. */
1001 fdata->lr_offset += SIGNED_SHORT (op);
1006 else if (cr_reg >= 0 &&
1007 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1008 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1009 /* stw Rx, NUM(r1) */
1010 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1011 /* stwu Rx, NUM(r1) */
1012 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1013 { /* where Rx == cr */
1014 fdata->cr_offset = offset;
1015 /* Invalidate cr_reg, but don't set it to -1.
1016 That would mean that it had never been set. */
1018 if ((op & 0xfc000003) == 0xf8000000 ||
1019 (op & 0xfc000000) == 0x90000000)
1021 /* Does not update r1, so add displacement to cr_offset. */
1022 fdata->cr_offset += SIGNED_SHORT (op);
1027 else if (op == 0x48000005)
1033 else if (op == 0x48000004)
1038 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1039 in V.4 -mminimal-toc */
1040 (op & 0xffff0000) == 0x3bde0000)
1041 { /* addi 30,30,foo@l */
1045 else if ((op & 0xfc000001) == 0x48000001)
1049 fdata->frameless = 0;
1050 /* Don't skip over the subroutine call if it is not within
1051 the first three instructions of the prologue and either
1052 we have no line table information or the line info tells
1053 us that the subroutine call is not part of the line
1054 associated with the prologue. */
1055 if ((pc - orig_pc) > 8)
1057 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1058 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1060 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1064 op = read_memory_integer (pc + 4, 4);
1066 /* At this point, make sure this is not a trampoline
1067 function (a function that simply calls another functions,
1068 and nothing else). If the next is not a nop, this branch
1069 was part of the function prologue. */
1071 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1072 break; /* don't skip over
1077 /* update stack pointer */
1078 else if ((op & 0xfc1f0000) == 0x94010000)
1079 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1080 fdata->frameless = 0;
1081 fdata->offset = SIGNED_SHORT (op);
1082 offset = fdata->offset;
1085 else if ((op & 0xfc1f016a) == 0x7c01016e)
1086 { /* stwux rX,r1,rY */
1087 /* no way to figure out what r1 is going to be */
1088 fdata->frameless = 0;
1089 offset = fdata->offset;
1092 else if ((op & 0xfc1f0003) == 0xf8010001)
1093 { /* stdu rX,NUM(r1) */
1094 fdata->frameless = 0;
1095 fdata->offset = SIGNED_SHORT (op & ~3UL);
1096 offset = fdata->offset;
1099 else if ((op & 0xfc1f016a) == 0x7c01016a)
1100 { /* stdux rX,r1,rY */
1101 /* no way to figure out what r1 is going to be */
1102 fdata->frameless = 0;
1103 offset = fdata->offset;
1106 /* Load up minimal toc pointer */
1107 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1108 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1109 && !minimal_toc_loaded)
1111 minimal_toc_loaded = 1;
1114 /* move parameters from argument registers to local variable
1117 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1118 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1119 (((op >> 21) & 31) <= 10) &&
1120 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1124 /* store parameters in stack */
1126 /* Move parameters from argument registers to temporary register. */
1127 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1131 /* Set up frame pointer */
1133 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1134 || op == 0x7c3f0b78)
1136 fdata->frameless = 0;
1138 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1141 /* Another way to set up the frame pointer. */
1143 else if ((op & 0xfc1fffff) == 0x38010000)
1144 { /* addi rX, r1, 0x0 */
1145 fdata->frameless = 0;
1147 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1148 + ((op & ~0x38010000) >> 21));
1151 /* AltiVec related instructions. */
1152 /* Store the vrsave register (spr 256) in another register for
1153 later manipulation, or load a register into the vrsave
1154 register. 2 instructions are used: mfvrsave and
1155 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1156 and mtspr SPR256, Rn. */
1157 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1158 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1159 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1161 vrsave_reg = GET_SRC_REG (op);
1164 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1168 /* Store the register where vrsave was saved to onto the stack:
1169 rS is the register where vrsave was stored in a previous
1171 /* 100100 sssss 00001 dddddddd dddddddd */
1172 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1174 if (vrsave_reg == GET_SRC_REG (op))
1176 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1181 /* Compute the new value of vrsave, by modifying the register
1182 where vrsave was saved to. */
1183 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1184 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1188 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1189 in a pair of insns to save the vector registers on the
1191 /* 001110 00000 00000 iiii iiii iiii iiii */
1192 /* 001110 01110 00000 iiii iiii iiii iiii */
1193 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1194 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1196 if ((op & 0xffff0000) == 0x38000000)
1197 r0_contains_arg = 0;
1199 vr_saved_offset = SIGNED_SHORT (op);
1201 /* This insn by itself is not part of the prologue, unless
1202 if part of the pair of insns mentioned above. So do not
1203 record this insn as part of the prologue yet. */
1204 prev_insn_was_prologue_insn = 0;
1206 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1207 /* 011111 sssss 11111 00000 00111001110 */
1208 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1210 if (pc == (li_found_pc + 4))
1212 vr_reg = GET_SRC_REG (op);
1213 /* If this is the first vector reg to be saved, or if
1214 it has a lower number than others previously seen,
1215 reupdate the frame info. */
1216 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1218 fdata->saved_vr = vr_reg;
1219 fdata->vr_offset = vr_saved_offset + offset;
1221 vr_saved_offset = -1;
1226 /* End AltiVec related instructions. */
1228 /* Start BookE related instructions. */
1229 /* Store gen register S at (r31+uimm).
1230 Any register less than r13 is volatile, so we don't care. */
1231 /* 000100 sssss 11111 iiiii 01100100001 */
1232 else if (arch_info->mach == bfd_mach_ppc_e500
1233 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1235 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1238 ev_reg = GET_SRC_REG (op);
1239 imm = (op >> 11) & 0x1f;
1240 ev_offset = imm * 8;
1241 /* If this is the first vector reg to be saved, or if
1242 it has a lower number than others previously seen,
1243 reupdate the frame info. */
1244 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1246 fdata->saved_ev = ev_reg;
1247 fdata->ev_offset = ev_offset + offset;
1252 /* Store gen register rS at (r1+rB). */
1253 /* 000100 sssss 00001 bbbbb 01100100000 */
1254 else if (arch_info->mach == bfd_mach_ppc_e500
1255 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1257 if (pc == (li_found_pc + 4))
1259 ev_reg = GET_SRC_REG (op);
1260 /* If this is the first vector reg to be saved, or if
1261 it has a lower number than others previously seen,
1262 reupdate the frame info. */
1263 /* We know the contents of rB from the previous instruction. */
1264 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1266 fdata->saved_ev = ev_reg;
1267 fdata->ev_offset = vr_saved_offset + offset;
1269 vr_saved_offset = -1;
1275 /* Store gen register r31 at (rA+uimm). */
1276 /* 000100 11111 aaaaa iiiii 01100100001 */
1277 else if (arch_info->mach == bfd_mach_ppc_e500
1278 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1280 /* Wwe know that the source register is 31 already, but
1281 it can't hurt to compute it. */
1282 ev_reg = GET_SRC_REG (op);
1283 ev_offset = ((op >> 11) & 0x1f) * 8;
1284 /* If this is the first vector reg to be saved, or if
1285 it has a lower number than others previously seen,
1286 reupdate the frame info. */
1287 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1289 fdata->saved_ev = ev_reg;
1290 fdata->ev_offset = ev_offset + offset;
1295 /* Store gen register S at (r31+r0).
1296 Store param on stack when offset from SP bigger than 4 bytes. */
1297 /* 000100 sssss 11111 00000 01100100000 */
1298 else if (arch_info->mach == bfd_mach_ppc_e500
1299 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1301 if (pc == (li_found_pc + 4))
1303 if ((op & 0x03e00000) >= 0x01a00000)
1305 ev_reg = GET_SRC_REG (op);
1306 /* If this is the first vector reg to be saved, or if
1307 it has a lower number than others previously seen,
1308 reupdate the frame info. */
1309 /* We know the contents of r0 from the previous
1311 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1313 fdata->saved_ev = ev_reg;
1314 fdata->ev_offset = vr_saved_offset + offset;
1318 vr_saved_offset = -1;
1323 /* End BookE related instructions. */
1327 /* Not a recognized prologue instruction.
1328 Handle optimizer code motions into the prologue by continuing
1329 the search if we have no valid frame yet or if the return
1330 address is not yet saved in the frame. */
1331 if (fdata->frameless == 0
1332 && (lr_reg == -1 || fdata->nosavedpc == 0))
1335 if (op == 0x4e800020 /* blr */
1336 || op == 0x4e800420) /* bctr */
1337 /* Do not scan past epilogue in frameless functions or
1340 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1341 /* Never skip branches. */
1344 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1345 /* Do not scan too many insns, scanning insns is expensive with
1349 /* Continue scanning. */
1350 prev_insn_was_prologue_insn = 0;
1356 /* I have problems with skipping over __main() that I need to address
1357 * sometime. Previously, I used to use misc_function_vector which
1358 * didn't work as well as I wanted to be. -MGO */
1360 /* If the first thing after skipping a prolog is a branch to a function,
1361 this might be a call to an initializer in main(), introduced by gcc2.
1362 We'd like to skip over it as well. Fortunately, xlc does some extra
1363 work before calling a function right after a prologue, thus we can
1364 single out such gcc2 behaviour. */
1367 if ((op & 0xfc000001) == 0x48000001)
1368 { /* bl foo, an initializer function? */
1369 op = read_memory_integer (pc + 4, 4);
1371 if (op == 0x4def7b82)
1372 { /* cror 0xf, 0xf, 0xf (nop) */
1374 /* Check and see if we are in main. If so, skip over this
1375 initializer function as well. */
1377 tmp = find_pc_misc_function (pc);
1379 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1385 fdata->offset = -fdata->offset;
1386 return last_prologue_pc;
1390 /*************************************************************************
1391 Support for creating pushing a dummy frame into the stack, and popping
1393 *************************************************************************/
1396 /* All the ABI's require 16 byte alignment. */
1398 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1400 return (addr & -16);
1403 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1404 the first eight words of the argument list (that might be less than
1405 eight parameters if some parameters occupy more than one word) are
1406 passed in r3..r10 registers. float and double parameters are
1407 passed in fpr's, in addition to that. Rest of the parameters if any
1408 are passed in user stack. There might be cases in which half of the
1409 parameter is copied into registers, the other half is pushed into
1412 Stack must be aligned on 64-bit boundaries when synthesizing
1415 If the function is returning a structure, then the return address is passed
1416 in r3, then the first 7 words of the parameters can be passed in registers,
1417 starting from r4. */
1420 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1421 struct regcache *regcache, CORE_ADDR bp_addr,
1422 int nargs, struct value **args, CORE_ADDR sp,
1423 int struct_return, CORE_ADDR struct_addr)
1425 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1428 int argno; /* current argument number */
1429 int argbytes; /* current argument byte */
1430 gdb_byte tmp_buffer[50];
1431 int f_argno = 0; /* current floating point argno */
1432 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1433 CORE_ADDR func_addr = find_function_addr (function, NULL);
1435 struct value *arg = 0;
1440 /* The calling convention this function implements assumes the
1441 processor has floating-point registers. We shouldn't be using it
1442 on PPC variants that lack them. */
1443 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1445 /* The first eight words of ther arguments are passed in registers.
1446 Copy them appropriately. */
1449 /* If the function is returning a `struct', then the first word
1450 (which will be passed in r3) is used for struct return address.
1451 In that case we should advance one word and start from r4
1452 register to copy parameters. */
1455 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1461 effectively indirect call... gcc does...
1463 return_val example( float, int);
1466 float in fp0, int in r3
1467 offset of stack on overflow 8/16
1468 for varargs, must go by type.
1470 float in r3&r4, int in r5
1471 offset of stack on overflow different
1473 return in r3 or f0. If no float, must study how gcc emulates floats;
1474 pay attention to arg promotion.
1475 User may have to cast\args to handle promotion correctly
1476 since gdb won't know if prototype supplied or not.
1479 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1481 int reg_size = register_size (current_gdbarch, ii + 3);
1484 type = check_typedef (value_type (arg));
1485 len = TYPE_LENGTH (type);
1487 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1490 /* Floating point arguments are passed in fpr's, as well as gpr's.
1491 There are 13 fpr's reserved for passing parameters. At this point
1492 there is no way we would run out of them. */
1494 gdb_assert (len <= 8);
1496 regcache_cooked_write (regcache,
1497 tdep->ppc_fp0_regnum + 1 + f_argno,
1498 value_contents (arg));
1505 /* Argument takes more than one register. */
1506 while (argbytes < len)
1508 gdb_byte word[MAX_REGISTER_SIZE];
1509 memset (word, 0, reg_size);
1511 ((char *) value_contents (arg)) + argbytes,
1512 (len - argbytes) > reg_size
1513 ? reg_size : len - argbytes);
1514 regcache_cooked_write (regcache,
1515 tdep->ppc_gp0_regnum + 3 + ii,
1517 ++ii, argbytes += reg_size;
1520 goto ran_out_of_registers_for_arguments;
1527 /* Argument can fit in one register. No problem. */
1528 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1529 gdb_byte word[MAX_REGISTER_SIZE];
1531 memset (word, 0, reg_size);
1532 memcpy (word, value_contents (arg), len);
1533 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1538 ran_out_of_registers_for_arguments:
1540 saved_sp = read_sp ();
1542 /* Location for 8 parameters are always reserved. */
1545 /* Another six words for back chain, TOC register, link register, etc. */
1548 /* Stack pointer must be quadword aligned. */
1551 /* If there are more arguments, allocate space for them in
1552 the stack, then push them starting from the ninth one. */
1554 if ((argno < nargs) || argbytes)
1560 space += ((len - argbytes + 3) & -4);
1566 for (; jj < nargs; ++jj)
1568 struct value *val = args[jj];
1569 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1572 /* Add location required for the rest of the parameters. */
1573 space = (space + 15) & -16;
1576 /* This is another instance we need to be concerned about
1577 securing our stack space. If we write anything underneath %sp
1578 (r1), we might conflict with the kernel who thinks he is free
1579 to use this area. So, update %sp first before doing anything
1582 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1584 /* If the last argument copied into the registers didn't fit there
1585 completely, push the rest of it into stack. */
1589 write_memory (sp + 24 + (ii * 4),
1590 value_contents (arg) + argbytes,
1593 ii += ((len - argbytes + 3) & -4) / 4;
1596 /* Push the rest of the arguments into stack. */
1597 for (; argno < nargs; ++argno)
1601 type = check_typedef (value_type (arg));
1602 len = TYPE_LENGTH (type);
1605 /* Float types should be passed in fpr's, as well as in the
1607 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1610 gdb_assert (len <= 8);
1612 regcache_cooked_write (regcache,
1613 tdep->ppc_fp0_regnum + 1 + f_argno,
1614 value_contents (arg));
1618 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1619 ii += ((len + 3) & -4) / 4;
1623 /* Set the stack pointer. According to the ABI, the SP is meant to
1624 be set _before_ the corresponding stack space is used. On AIX,
1625 this even applies when the target has been completely stopped!
1626 Not doing this can lead to conflicts with the kernel which thinks
1627 that it still has control over this not-yet-allocated stack
1629 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1631 /* Set back chain properly. */
1632 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1633 write_memory (sp, tmp_buffer, wordsize);
1635 /* Point the inferior function call's return address at the dummy's
1637 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1639 /* Set the TOC register, get the value from the objfile reader
1640 which, in turn, gets it from the VMAP table. */
1641 if (rs6000_find_toc_address_hook != NULL)
1643 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1644 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1647 target_store_registers (-1);
1651 /* PowerOpen always puts structures in memory. Vectors, which were
1652 added later, do get returned in a register though. */
1655 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1657 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1658 && TYPE_VECTOR (value_type))
1664 rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf,
1668 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1670 /* The calling convention this function implements assumes the
1671 processor has floating-point registers. We shouldn't be using it
1672 on PPC variants that lack them. */
1673 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1675 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1678 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1679 We need to truncate the return value into float size (4 byte) if
1682 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1683 (tdep->ppc_fp0_regnum + 1)],
1684 builtin_type_double,
1688 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1689 && TYPE_LENGTH (valtype) == 16
1690 && TYPE_VECTOR (valtype))
1692 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1693 TYPE_LENGTH (valtype));
1697 /* return value is copied starting from r3. */
1698 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1699 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
1700 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
1703 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1704 TYPE_LENGTH (valtype));
1708 /* Return whether handle_inferior_event() should proceed through code
1709 starting at PC in function NAME when stepping.
1711 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1712 handle memory references that are too distant to fit in instructions
1713 generated by the compiler. For example, if 'foo' in the following
1718 is greater than 32767, the linker might replace the lwz with a branch to
1719 somewhere in @FIX1 that does the load in 2 instructions and then branches
1720 back to where execution should continue.
1722 GDB should silently step over @FIX code, just like AIX dbx does.
1723 Unfortunately, the linker uses the "b" instruction for the
1724 branches, meaning that the link register doesn't get set.
1725 Therefore, GDB's usual step_over_function () mechanism won't work.
1727 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1728 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1732 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1734 return name && !strncmp (name, "@FIX", 4);
1737 /* Skip code that the user doesn't want to see when stepping:
1739 1. Indirect function calls use a piece of trampoline code to do context
1740 switching, i.e. to set the new TOC table. Skip such code if we are on
1741 its first instruction (as when we have single-stepped to here).
1743 2. Skip shared library trampoline code (which is different from
1744 indirect function call trampolines).
1746 3. Skip bigtoc fixup code.
1748 Result is desired PC to step until, or NULL if we are not in
1749 code that should be skipped. */
1752 rs6000_skip_trampoline_code (CORE_ADDR pc)
1754 unsigned int ii, op;
1756 CORE_ADDR solib_target_pc;
1757 struct minimal_symbol *msymbol;
1759 static unsigned trampoline_code[] =
1761 0x800b0000, /* l r0,0x0(r11) */
1762 0x90410014, /* st r2,0x14(r1) */
1763 0x7c0903a6, /* mtctr r0 */
1764 0x804b0004, /* l r2,0x4(r11) */
1765 0x816b0008, /* l r11,0x8(r11) */
1766 0x4e800420, /* bctr */
1767 0x4e800020, /* br */
1771 /* Check for bigtoc fixup code. */
1772 msymbol = lookup_minimal_symbol_by_pc (pc);
1774 && rs6000_in_solib_return_trampoline (pc,
1775 DEPRECATED_SYMBOL_NAME (msymbol)))
1777 /* Double-check that the third instruction from PC is relative "b". */
1778 op = read_memory_integer (pc + 8, 4);
1779 if ((op & 0xfc000003) == 0x48000000)
1781 /* Extract bits 6-29 as a signed 24-bit relative word address and
1782 add it to the containing PC. */
1783 rel = ((int)(op << 6) >> 6);
1784 return pc + 8 + rel;
1788 /* If pc is in a shared library trampoline, return its target. */
1789 solib_target_pc = find_solib_trampoline_target (pc);
1790 if (solib_target_pc)
1791 return solib_target_pc;
1793 for (ii = 0; trampoline_code[ii]; ++ii)
1795 op = read_memory_integer (pc + (ii * 4), 4);
1796 if (op != trampoline_code[ii])
1799 ii = read_register (11); /* r11 holds destination addr */
1800 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1804 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1805 isn't available with that word size, return 0. */
1808 regsize (const struct reg *reg, int wordsize)
1810 return wordsize == 8 ? reg->sz64 : reg->sz32;
1813 /* Return the name of register number N, or null if no such register exists
1814 in the current architecture. */
1817 rs6000_register_name (int n)
1819 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1820 const struct reg *reg = tdep->regs + n;
1822 if (!regsize (reg, tdep->wordsize))
1827 /* Return the GDB type object for the "standard" data type
1828 of data in register N. */
1830 static struct type *
1831 rs6000_register_type (struct gdbarch *gdbarch, int n)
1833 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1834 const struct reg *reg = tdep->regs + n;
1837 return builtin_type_double;
1840 int size = regsize (reg, tdep->wordsize);
1844 return builtin_type_int0;
1846 return builtin_type_uint32;
1848 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1849 return builtin_type_vec64;
1851 return builtin_type_uint64;
1854 return builtin_type_vec128;
1857 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
1863 /* Is REGNUM a member of REGGROUP? */
1865 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1866 struct reggroup *group)
1868 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1873 if (REGISTER_NAME (regnum) == NULL
1874 || *REGISTER_NAME (regnum) == '\0')
1876 if (group == all_reggroup)
1879 float_p = (regnum == tdep->ppc_fpscr_regnum
1880 || (regnum >= tdep->ppc_fp0_regnum
1881 && regnum < tdep->ppc_fp0_regnum + 32));
1882 if (group == float_reggroup)
1885 vector_p = ((tdep->ppc_vr0_regnum >= 0
1886 && regnum >= tdep->ppc_vr0_regnum
1887 && regnum < tdep->ppc_vr0_regnum + 32)
1888 || (tdep->ppc_ev0_regnum >= 0
1889 && regnum >= tdep->ppc_ev0_regnum
1890 && regnum < tdep->ppc_ev0_regnum + 32)
1891 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
1892 || regnum == tdep->ppc_vrsave_regnum
1893 || regnum == tdep->ppc_acc_regnum
1894 || regnum == tdep->ppc_spefscr_regnum);
1895 if (group == vector_reggroup)
1898 /* Note that PS aka MSR isn't included - it's a system register (and
1899 besides, due to GCC's CFI foobar you do not want to restore
1901 general_p = ((regnum >= tdep->ppc_gp0_regnum
1902 && regnum < tdep->ppc_gp0_regnum + 32)
1903 || regnum == tdep->ppc_toc_regnum
1904 || regnum == tdep->ppc_cr_regnum
1905 || regnum == tdep->ppc_lr_regnum
1906 || regnum == tdep->ppc_ctr_regnum
1907 || regnum == tdep->ppc_xer_regnum
1908 || regnum == PC_REGNUM);
1909 if (group == general_reggroup)
1912 if (group == save_reggroup || group == restore_reggroup)
1913 return general_p || vector_p || float_p;
1918 /* The register format for RS/6000 floating point registers is always
1919 double, we need a conversion if the memory format is float. */
1922 rs6000_convert_register_p (int regnum, struct type *type)
1924 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1927 && TYPE_CODE (type) == TYPE_CODE_FLT
1928 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
1932 rs6000_register_to_value (struct frame_info *frame,
1937 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1938 gdb_byte from[MAX_REGISTER_SIZE];
1940 gdb_assert (reg->fpr);
1941 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1943 get_frame_register (frame, regnum, from);
1944 convert_typed_floating (from, builtin_type_double, to, type);
1948 rs6000_value_to_register (struct frame_info *frame,
1951 const gdb_byte *from)
1953 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1954 gdb_byte to[MAX_REGISTER_SIZE];
1956 gdb_assert (reg->fpr);
1957 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1959 convert_typed_floating (from, type, to, builtin_type_double);
1960 put_frame_register (frame, regnum, to);
1963 /* Move SPE vector register values between a 64-bit buffer and the two
1964 32-bit raw register halves in a regcache. This function handles
1965 both splitting a 64-bit value into two 32-bit halves, and joining
1966 two halves into a whole 64-bit value, depending on the function
1967 passed as the MOVE argument.
1969 EV_REG must be the number of an SPE evN vector register --- a
1970 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
1973 Call MOVE once for each 32-bit half of that register, passing
1974 REGCACHE, the number of the raw register corresponding to that
1975 half, and the address of the appropriate half of BUFFER.
1977 For example, passing 'regcache_raw_read' as the MOVE function will
1978 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
1979 'regcache_raw_supply' will supply the contents of BUFFER to the
1980 appropriate pair of raw registers in REGCACHE.
1982 You may need to cast away some 'const' qualifiers when passing
1983 MOVE, since this function can't tell at compile-time which of
1984 REGCACHE or BUFFER is acting as the source of the data. If C had
1985 co-variant type qualifiers, ... */
1987 e500_move_ev_register (void (*move) (struct regcache *regcache,
1988 int regnum, gdb_byte *buf),
1989 struct regcache *regcache, int ev_reg,
1992 struct gdbarch *arch = get_regcache_arch (regcache);
1993 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1995 gdb_byte *byte_buffer = buffer;
1997 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
1998 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2000 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2002 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2004 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2005 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2009 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2010 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2015 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2016 int reg_nr, gdb_byte *buffer)
2018 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2019 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2021 gdb_assert (regcache_arch == gdbarch);
2023 if (tdep->ppc_ev0_regnum <= reg_nr
2024 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2025 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2027 internal_error (__FILE__, __LINE__,
2028 _("e500_pseudo_register_read: "
2029 "called on unexpected register '%s' (%d)"),
2030 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2034 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2035 int reg_nr, const gdb_byte *buffer)
2037 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2038 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2040 gdb_assert (regcache_arch == gdbarch);
2042 if (tdep->ppc_ev0_regnum <= reg_nr
2043 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2044 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2046 regcache, reg_nr, (gdb_byte *) buffer);
2048 internal_error (__FILE__, __LINE__,
2049 _("e500_pseudo_register_read: "
2050 "called on unexpected register '%s' (%d)"),
2051 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2054 /* The E500 needs a custom reggroup function: it has anonymous raw
2055 registers, and default_register_reggroup_p assumes that anonymous
2056 registers are not members of any reggroup. */
2058 e500_register_reggroup_p (struct gdbarch *gdbarch,
2060 struct reggroup *group)
2062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2064 /* The save and restore register groups need to include the
2065 upper-half registers, even though they're anonymous. */
2066 if ((group == save_reggroup
2067 || group == restore_reggroup)
2068 && (tdep->ppc_ev0_upper_regnum <= regnum
2069 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2072 /* In all other regards, the default reggroup definition is fine. */
2073 return default_register_reggroup_p (gdbarch, regnum, group);
2076 /* Convert a DBX STABS register number to a GDB register number. */
2078 rs6000_stab_reg_to_regnum (int num)
2080 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2082 if (0 <= num && num <= 31)
2083 return tdep->ppc_gp0_regnum + num;
2084 else if (32 <= num && num <= 63)
2085 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2086 specifies registers the architecture doesn't have? Our
2087 callers don't check the value we return. */
2088 return tdep->ppc_fp0_regnum + (num - 32);
2089 else if (77 <= num && num <= 108)
2090 return tdep->ppc_vr0_regnum + (num - 77);
2091 else if (1200 <= num && num < 1200 + 32)
2092 return tdep->ppc_ev0_regnum + (num - 1200);
2097 return tdep->ppc_mq_regnum;
2099 return tdep->ppc_lr_regnum;
2101 return tdep->ppc_ctr_regnum;
2103 return tdep->ppc_xer_regnum;
2105 return tdep->ppc_vrsave_regnum;
2107 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2109 return tdep->ppc_acc_regnum;
2111 return tdep->ppc_spefscr_regnum;
2118 /* Convert a Dwarf 2 register number to a GDB register number. */
2120 rs6000_dwarf2_reg_to_regnum (int num)
2122 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2124 if (0 <= num && num <= 31)
2125 return tdep->ppc_gp0_regnum + num;
2126 else if (32 <= num && num <= 63)
2127 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2128 specifies registers the architecture doesn't have? Our
2129 callers don't check the value we return. */
2130 return tdep->ppc_fp0_regnum + (num - 32);
2131 else if (1124 <= num && num < 1124 + 32)
2132 return tdep->ppc_vr0_regnum + (num - 1124);
2133 else if (1200 <= num && num < 1200 + 32)
2134 return tdep->ppc_ev0_regnum + (num - 1200);
2139 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2141 return tdep->ppc_acc_regnum;
2143 return tdep->ppc_mq_regnum;
2145 return tdep->ppc_xer_regnum;
2147 return tdep->ppc_lr_regnum;
2149 return tdep->ppc_ctr_regnum;
2151 return tdep->ppc_vrsave_regnum;
2153 return tdep->ppc_spefscr_regnum;
2161 rs6000_store_return_value (struct type *type,
2162 struct regcache *regcache,
2163 const gdb_byte *valbuf)
2165 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2169 /* The calling convention this function implements assumes the
2170 processor has floating-point registers. We shouldn't be using it
2171 on PPC variants that lack them. */
2172 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2174 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2175 /* Floating point values are returned starting from FPR1 and up.
2176 Say a double_double_double type could be returned in
2177 FPR1/FPR2/FPR3 triple. */
2178 regnum = tdep->ppc_fp0_regnum + 1;
2179 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2181 if (TYPE_LENGTH (type) == 16
2182 && TYPE_VECTOR (type))
2183 regnum = tdep->ppc_vr0_regnum + 2;
2185 internal_error (__FILE__, __LINE__,
2186 _("rs6000_store_return_value: "
2187 "unexpected array return type"));
2190 /* Everything else is returned in GPR3 and up. */
2191 regnum = tdep->ppc_gp0_regnum + 3;
2194 size_t bytes_written = 0;
2196 while (bytes_written < TYPE_LENGTH (type))
2198 /* How much of this value can we write to this register? */
2199 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
2200 register_size (gdbarch, regnum));
2201 regcache_cooked_write_part (regcache, regnum,
2203 valbuf + bytes_written);
2205 bytes_written += bytes_to_write;
2211 /* Extract from an array REGBUF containing the (raw) register state
2212 the address in which a function should return its structure value,
2213 as a CORE_ADDR (or an expression that can be used as one). */
2216 rs6000_extract_struct_value_address (struct regcache *regcache)
2218 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2219 function call GDB knows the address of the struct return value
2220 and hence, should not need to call this function. Unfortunately,
2221 the current call_function_by_hand() code only saves the most
2222 recent struct address leading to occasional calls. The code
2223 should instead maintain a stack of such addresses (in the dummy
2225 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2226 really got no idea where the return value is being stored. While
2227 r3, on function entry, contained the address it will have since
2228 been reused (scratch) and hence wouldn't be valid */
2232 /* Hook called when a new child process is started. */
2235 rs6000_create_inferior (int pid)
2237 if (rs6000_set_host_arch_hook)
2238 rs6000_set_host_arch_hook (pid);
2241 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2243 Usually a function pointer's representation is simply the address
2244 of the function. On the RS/6000 however, a function pointer is
2245 represented by a pointer to an OPD entry. This OPD entry contains
2246 three words, the first word is the address of the function, the
2247 second word is the TOC pointer (r2), and the third word is the
2248 static chain value. Throughout GDB it is currently assumed that a
2249 function pointer contains the address of the function, which is not
2250 easy to fix. In addition, the conversion of a function address to
2251 a function pointer would require allocation of an OPD entry in the
2252 inferior's memory space, with all its drawbacks. To be able to
2253 call C++ virtual methods in the inferior (which are called via
2254 function pointers), find_function_addr uses this function to get the
2255 function address from a function pointer. */
2257 /* Return real function address if ADDR (a function pointer) is in the data
2258 space and is therefore a special function pointer. */
2261 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2263 struct target_ops *targ)
2265 struct obj_section *s;
2267 s = find_pc_section (addr);
2268 if (s && s->the_bfd_section->flags & SEC_CODE)
2271 /* ADDR is in the data space, so it's a special function pointer. */
2272 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
2276 /* Handling the various POWER/PowerPC variants. */
2279 /* The arrays here called registers_MUMBLE hold information about available
2282 For each family of PPC variants, I've tried to isolate out the
2283 common registers and put them up front, so that as long as you get
2284 the general family right, GDB will correctly identify the registers
2285 common to that family. The common register sets are:
2287 For the 60x family: hid0 hid1 iabr dabr pir
2289 For the 505 and 860 family: eie eid nri
2291 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2292 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2295 Most of these register groups aren't anything formal. I arrived at
2296 them by looking at the registers that occurred in more than one
2299 Note: kevinb/2002-04-30: Support for the fpscr register was added
2300 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2301 for Power. For PowerPC, slot 70 was unused and was already in the
2302 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2303 slot 70 was being used for "mq", so the next available slot (71)
2304 was chosen. It would have been nice to be able to make the
2305 register numbers the same across processor cores, but this wasn't
2306 possible without either 1) renumbering some registers for some
2307 processors or 2) assigning fpscr to a really high slot that's
2308 larger than any current register number. Doing (1) is bad because
2309 existing stubs would break. Doing (2) is undesirable because it
2310 would introduce a really large gap between fpscr and the rest of
2311 the registers for most processors. */
2313 /* Convenience macros for populating register arrays. */
2315 /* Within another macro, convert S to a string. */
2319 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2320 and 64 bits on 64-bit systems. */
2321 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2323 /* Return a struct reg defining register NAME that's 32 bits on all
2325 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2327 /* Return a struct reg defining register NAME that's 64 bits on all
2329 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2331 /* Return a struct reg defining register NAME that's 128 bits on all
2333 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2335 /* Return a struct reg defining floating-point register NAME. */
2336 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2338 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2339 long on all systems. */
2340 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2342 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2343 systems and that doesn't exist on 64-bit systems. */
2344 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2346 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2347 systems and that doesn't exist on 32-bit systems. */
2348 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2350 /* Return a struct reg placeholder for a register that doesn't exist. */
2351 #define R0 { 0, 0, 0, 0, 0, -1 }
2353 /* Return a struct reg defining an anonymous raw register that's 32
2354 bits on all systems. */
2355 #define A4 { 0, 4, 4, 0, 0, -1 }
2357 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2358 32-bit systems and 64 bits on 64-bit systems. */
2359 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2361 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2363 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2365 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2366 all systems, and whose SPR number is NUMBER. */
2367 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2369 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2370 64-bit systems and that doesn't exist on 32-bit systems. */
2371 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2373 /* UISA registers common across all architectures, including POWER. */
2375 #define COMMON_UISA_REGS \
2376 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2377 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2378 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2379 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2380 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2381 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2382 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2383 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2384 /* 64 */ R(pc), R(ps)
2386 /* UISA-level SPRs for PowerPC. */
2387 #define PPC_UISA_SPRS \
2388 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2390 /* UISA-level SPRs for PowerPC without floating point support. */
2391 #define PPC_UISA_NOFP_SPRS \
2392 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2394 /* Segment registers, for PowerPC. */
2395 #define PPC_SEGMENT_REGS \
2396 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2397 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2398 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2399 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2401 /* OEA SPRs for PowerPC. */
2402 #define PPC_OEA_SPRS \
2404 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2405 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2406 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2407 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2408 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2409 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2410 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2411 /* 116 */ S4(dec), S(dabr), S4(ear)
2413 /* AltiVec registers. */
2414 #define PPC_ALTIVEC_REGS \
2415 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2416 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2417 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2418 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2419 /*151*/R4(vscr), R4(vrsave)
2422 /* On machines supporting the SPE APU, the general-purpose registers
2423 are 64 bits long. There are SIMD vector instructions to treat them
2424 as pairs of floats, but the rest of the instruction set treats them
2425 as 32-bit registers, and only operates on their lower halves.
2427 In the GDB regcache, we treat their high and low halves as separate
2428 registers. The low halves we present as the general-purpose
2429 registers, and then we have pseudo-registers that stitch together
2430 the upper and lower halves and present them as pseudo-registers. */
2432 /* SPE GPR lower halves --- raw registers. */
2433 #define PPC_SPE_GP_REGS \
2434 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2435 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2436 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2437 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2439 /* SPE GPR upper halves --- anonymous raw registers. */
2440 #define PPC_SPE_UPPER_GP_REGS \
2441 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2442 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2443 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2444 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2446 /* SPE GPR vector registers --- pseudo registers based on underlying
2447 gprs and the anonymous upper half raw registers. */
2448 #define PPC_EV_PSEUDO_REGS \
2449 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2450 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2451 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2452 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2454 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2455 user-level SPR's. */
2456 static const struct reg registers_power[] =
2459 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2463 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2464 view of the PowerPC. */
2465 static const struct reg registers_powerpc[] =
2474 Some notes about the "tcr" special-purpose register:
2475 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2476 403's programmable interval timer, fixed interval timer, and
2478 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2479 watchdog timer, and nothing else.
2481 Some of the fields are similar between the two, but they're not
2482 compatible with each other. Since the two variants have different
2483 registers, with different numbers, but the same name, we can't
2484 splice the register name to get the SPR number. */
2485 static const struct reg registers_403[] =
2491 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2492 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2493 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2494 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2495 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2496 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2499 /* IBM PowerPC 403GC.
2500 See the comments about 'tcr' for the 403, above. */
2501 static const struct reg registers_403GC[] =
2507 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2508 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2509 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2510 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2511 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2512 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2513 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2514 /* 147 */ S(tbhu), S(tblu)
2517 /* Motorola PowerPC 505. */
2518 static const struct reg registers_505[] =
2524 /* 119 */ S(eie), S(eid), S(nri)
2527 /* Motorola PowerPC 860 or 850. */
2528 static const struct reg registers_860[] =
2534 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2535 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2536 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2537 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2538 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2539 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2540 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2541 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2542 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2543 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2544 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2545 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2548 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2549 for reading and writing RTCU and RTCL. However, how one reads and writes a
2550 register is the stub's problem. */
2551 static const struct reg registers_601[] =
2557 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2558 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2561 /* Motorola PowerPC 602.
2562 See the notes under the 403 about 'tcr'. */
2563 static const struct reg registers_602[] =
2569 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2570 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2571 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2574 /* Motorola/IBM PowerPC 603 or 603e. */
2575 static const struct reg registers_603[] =
2581 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2582 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2583 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2586 /* Motorola PowerPC 604 or 604e. */
2587 static const struct reg registers_604[] =
2593 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2594 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2595 /* 127 */ S(sia), S(sda)
2598 /* Motorola/IBM PowerPC 750 or 740. */
2599 static const struct reg registers_750[] =
2605 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2606 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2607 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2608 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2609 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2610 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2614 /* Motorola PowerPC 7400. */
2615 static const struct reg registers_7400[] =
2617 /* gpr0-gpr31, fpr0-fpr31 */
2619 /* cr, lr, ctr, xer, fpscr */
2624 /* vr0-vr31, vrsave, vscr */
2626 /* FIXME? Add more registers? */
2629 /* Motorola e500. */
2630 static const struct reg registers_e500[] =
2632 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2633 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2634 /* 64 .. 65 */ R(pc), R(ps),
2635 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2636 /* 71 .. 72 */ R8(acc), S4(spefscr),
2637 /* NOTE: Add new registers here the end of the raw register
2638 list and just before the first pseudo register. */
2639 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2642 /* Information about a particular processor variant. */
2646 /* Name of this variant. */
2649 /* English description of the variant. */
2652 /* bfd_arch_info.arch corresponding to variant. */
2653 enum bfd_architecture arch;
2655 /* bfd_arch_info.mach corresponding to variant. */
2658 /* Number of real registers. */
2661 /* Number of pseudo registers. */
2664 /* Number of total registers (the sum of nregs and npregs). */
2667 /* Table of register names; registers[R] is the name of the register
2669 const struct reg *regs;
2672 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2675 num_registers (const struct reg *reg_list, int num_tot_regs)
2680 for (i = 0; i < num_tot_regs; i++)
2681 if (!reg_list[i].pseudo)
2688 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2693 for (i = 0; i < num_tot_regs; i++)
2694 if (reg_list[i].pseudo)
2700 /* Information in this table comes from the following web sites:
2701 IBM: http://www.chips.ibm.com:80/products/embedded/
2702 Motorola: http://www.mot.com/SPS/PowerPC/
2704 I'm sure I've got some of the variant descriptions not quite right.
2705 Please report any inaccuracies you find to GDB's maintainer.
2707 If you add entries to this table, please be sure to allow the new
2708 value as an argument to the --with-cpu flag, in configure.in. */
2710 static struct variant variants[] =
2713 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2714 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2716 {"power", "POWER user-level", bfd_arch_rs6000,
2717 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2719 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2720 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2722 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2723 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2725 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2726 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2728 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2729 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2731 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2732 604, -1, -1, tot_num_registers (registers_604),
2734 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2735 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2737 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2738 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2740 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2741 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2743 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2744 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2746 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2747 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2749 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2750 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2754 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2755 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2757 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2758 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2760 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2761 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2763 {"a35", "PowerPC A35", bfd_arch_powerpc,
2764 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2766 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2767 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2769 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2770 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2773 /* FIXME: I haven't checked the register sets of the following. */
2774 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2775 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2777 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2778 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2780 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2781 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2784 {0, 0, 0, 0, 0, 0, 0, 0}
2787 /* Initialize the number of registers and pseudo registers in each variant. */
2790 init_variants (void)
2794 for (v = variants; v->name; v++)
2797 v->nregs = num_registers (v->regs, v->num_tot_regs);
2798 if (v->npregs == -1)
2799 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2803 /* Return the variant corresponding to architecture ARCH and machine number
2804 MACH. If no such variant exists, return null. */
2806 static const struct variant *
2807 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2809 const struct variant *v;
2811 for (v = variants; v->name; v++)
2812 if (arch == v->arch && mach == v->mach)
2819 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2821 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2822 return print_insn_big_powerpc (memaddr, info);
2824 return print_insn_little_powerpc (memaddr, info);
2828 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2830 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2833 static struct frame_id
2834 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2836 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2838 frame_pc_unwind (next_frame));
2841 struct rs6000_frame_cache
2844 CORE_ADDR initial_sp;
2845 struct trad_frame_saved_reg *saved_regs;
2848 static struct rs6000_frame_cache *
2849 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2851 struct rs6000_frame_cache *cache;
2852 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2853 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2854 struct rs6000_framedata fdata;
2855 int wordsize = tdep->wordsize;
2858 if ((*this_cache) != NULL)
2859 return (*this_cache);
2860 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2861 (*this_cache) = cache;
2862 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2864 func = frame_func_unwind (next_frame);
2865 pc = frame_pc_unwind (next_frame);
2866 skip_prologue (func, pc, &fdata);
2868 /* Figure out the parent's stack pointer. */
2870 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2871 address of the current frame. Things might be easier if the
2872 ->frame pointed to the outer-most address of the frame. In
2873 the mean time, the address of the prev frame is used as the
2874 base address of this frame. */
2875 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2877 /* If the function appears to be frameless, check a couple of likely
2878 indicators that we have simply failed to find the frame setup.
2879 Two common cases of this are missing symbols (i.e.
2880 frame_func_unwind returns the wrong address or 0), and assembly
2881 stubs which have a fast exit path but set up a frame on the slow
2884 If the LR appears to return to this function, then presume that
2885 we have an ABI compliant frame that we failed to find. */
2886 if (fdata.frameless && fdata.lr_offset == 0)
2891 saved_lr = frame_unwind_register_unsigned (next_frame,
2892 tdep->ppc_lr_regnum);
2893 if (func == 0 && saved_lr == pc)
2897 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
2898 if (func == saved_func)
2904 fdata.frameless = 0;
2905 fdata.lr_offset = wordsize;
2909 if (!fdata.frameless)
2910 /* Frameless really means stackless. */
2911 cache->base = read_memory_addr (cache->base, wordsize);
2913 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2915 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2916 All fpr's from saved_fpr to fp31 are saved. */
2918 if (fdata.saved_fpr >= 0)
2921 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2923 /* If skip_prologue says floating-point registers were saved,
2924 but the current architecture has no floating-point registers,
2925 then that's strange. But we have no indices to even record
2926 the addresses under, so we just ignore it. */
2927 if (ppc_floating_point_unit_p (gdbarch))
2928 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2930 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2935 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2936 All gpr's from saved_gpr to gpr31 are saved. */
2938 if (fdata.saved_gpr >= 0)
2941 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2942 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2944 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2945 gpr_addr += wordsize;
2949 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2950 All vr's from saved_vr to vr31 are saved. */
2951 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2953 if (fdata.saved_vr >= 0)
2956 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2957 for (i = fdata.saved_vr; i < 32; i++)
2959 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2960 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2965 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2966 All vr's from saved_ev to ev31 are saved. ????? */
2967 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2969 if (fdata.saved_ev >= 0)
2972 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2973 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2975 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2976 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2977 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2982 /* If != 0, fdata.cr_offset is the offset from the frame that
2984 if (fdata.cr_offset != 0)
2985 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2987 /* If != 0, fdata.lr_offset is the offset from the frame that
2989 if (fdata.lr_offset != 0)
2990 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2991 /* The PC is found in the link register. */
2992 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2994 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2995 holds the VRSAVE. */
2996 if (fdata.vrsave_offset != 0)
2997 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2999 if (fdata.alloca_reg < 0)
3000 /* If no alloca register used, then fi->frame is the value of the
3001 %sp for this frame, and it is good enough. */
3002 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3004 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3011 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3012 struct frame_id *this_id)
3014 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3016 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
3020 rs6000_frame_prev_register (struct frame_info *next_frame,
3022 int regnum, int *optimizedp,
3023 enum lval_type *lvalp, CORE_ADDR *addrp,
3024 int *realnump, gdb_byte *valuep)
3026 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3028 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3029 optimizedp, lvalp, addrp, realnump, valuep);
3032 static const struct frame_unwind rs6000_frame_unwind =
3035 rs6000_frame_this_id,
3036 rs6000_frame_prev_register
3039 static const struct frame_unwind *
3040 rs6000_frame_sniffer (struct frame_info *next_frame)
3042 return &rs6000_frame_unwind;
3048 rs6000_frame_base_address (struct frame_info *next_frame,
3051 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3053 return info->initial_sp;
3056 static const struct frame_base rs6000_frame_base = {
3057 &rs6000_frame_unwind,
3058 rs6000_frame_base_address,
3059 rs6000_frame_base_address,
3060 rs6000_frame_base_address
3063 static const struct frame_base *
3064 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3066 return &rs6000_frame_base;
3069 /* Initialize the current architecture based on INFO. If possible, re-use an
3070 architecture from ARCHES, which is a list of architectures already created
3071 during this debugging session.
3073 Called e.g. at program startup, when reading a core file, and when reading
3076 static struct gdbarch *
3077 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3079 struct gdbarch *gdbarch;
3080 struct gdbarch_tdep *tdep;
3081 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3083 const struct variant *v;
3084 enum bfd_architecture arch;
3090 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3091 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3093 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3094 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3096 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3098 /* Check word size. If INFO is from a binary file, infer it from
3099 that, else choose a likely default. */
3100 if (from_xcoff_exec)
3102 if (bfd_xcoff_is_xcoff64 (info.abfd))
3107 else if (from_elf_exec)
3109 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3116 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3117 wordsize = info.bfd_arch_info->bits_per_word /
3118 info.bfd_arch_info->bits_per_byte;
3123 /* Find a candidate among extant architectures. */
3124 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3126 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3128 /* Word size in the various PowerPC bfd_arch_info structs isn't
3129 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3130 separate word size check. */
3131 tdep = gdbarch_tdep (arches->gdbarch);
3132 if (tdep && tdep->wordsize == wordsize)
3133 return arches->gdbarch;
3136 /* None found, create a new architecture from INFO, whose bfd_arch_info
3137 validity depends on the source:
3138 - executable useless
3139 - rs6000_host_arch() good
3141 - "set arch" trust blindly
3142 - GDB startup useless but harmless */
3144 if (!from_xcoff_exec)
3146 arch = info.bfd_arch_info->arch;
3147 mach = info.bfd_arch_info->mach;
3151 arch = bfd_arch_powerpc;
3152 bfd_default_set_arch_mach (&abfd, arch, 0);
3153 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3154 mach = info.bfd_arch_info->mach;
3156 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3157 tdep->wordsize = wordsize;
3159 /* For e500 executables, the apuinfo section is of help here. Such
3160 section contains the identifier and revision number of each
3161 Application-specific Processing Unit that is present on the
3162 chip. The content of the section is determined by the assembler
3163 which looks at each instruction and determines which unit (and
3164 which version of it) can execute it. In our case we just look for
3165 the existance of the section. */
3169 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3172 arch = info.bfd_arch_info->arch;
3173 mach = bfd_mach_ppc_e500;
3174 bfd_default_set_arch_mach (&abfd, arch, mach);
3175 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3179 gdbarch = gdbarch_alloc (&info, tdep);
3181 /* Initialize the number of real and pseudo registers in each variant. */
3184 /* Choose variant. */
3185 v = find_variant_by_arch (arch, mach);
3189 tdep->regs = v->regs;
3191 tdep->ppc_gp0_regnum = 0;
3192 tdep->ppc_toc_regnum = 2;
3193 tdep->ppc_ps_regnum = 65;
3194 tdep->ppc_cr_regnum = 66;
3195 tdep->ppc_lr_regnum = 67;
3196 tdep->ppc_ctr_regnum = 68;
3197 tdep->ppc_xer_regnum = 69;
3198 if (v->mach == bfd_mach_ppc_601)
3199 tdep->ppc_mq_regnum = 124;
3200 else if (arch == bfd_arch_rs6000)
3201 tdep->ppc_mq_regnum = 70;
3203 tdep->ppc_mq_regnum = -1;
3204 tdep->ppc_fp0_regnum = 32;
3205 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3206 tdep->ppc_sr0_regnum = 71;
3207 tdep->ppc_vr0_regnum = -1;
3208 tdep->ppc_vrsave_regnum = -1;
3209 tdep->ppc_ev0_upper_regnum = -1;
3210 tdep->ppc_ev0_regnum = -1;
3211 tdep->ppc_ev31_regnum = -1;
3212 tdep->ppc_acc_regnum = -1;
3213 tdep->ppc_spefscr_regnum = -1;
3215 set_gdbarch_pc_regnum (gdbarch, 64);
3216 set_gdbarch_sp_regnum (gdbarch, 1);
3217 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3218 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3219 if (sysv_abi && wordsize == 8)
3220 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3221 else if (sysv_abi && wordsize == 4)
3222 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3225 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
3226 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
3229 /* Set lr_frame_offset. */
3231 tdep->lr_frame_offset = 16;
3233 tdep->lr_frame_offset = 4;
3235 tdep->lr_frame_offset = 8;
3237 if (v->arch == bfd_arch_rs6000)
3238 tdep->ppc_sr0_regnum = -1;
3239 else if (v->arch == bfd_arch_powerpc)
3243 tdep->ppc_sr0_regnum = -1;
3244 tdep->ppc_vr0_regnum = 71;
3245 tdep->ppc_vrsave_regnum = 104;
3247 case bfd_mach_ppc_7400:
3248 tdep->ppc_vr0_regnum = 119;
3249 tdep->ppc_vrsave_regnum = 152;
3251 case bfd_mach_ppc_e500:
3252 tdep->ppc_toc_regnum = -1;
3253 tdep->ppc_ev0_upper_regnum = 32;
3254 tdep->ppc_ev0_regnum = 73;
3255 tdep->ppc_ev31_regnum = 104;
3256 tdep->ppc_acc_regnum = 71;
3257 tdep->ppc_spefscr_regnum = 72;
3258 tdep->ppc_fp0_regnum = -1;
3259 tdep->ppc_fpscr_regnum = -1;
3260 tdep->ppc_sr0_regnum = -1;
3261 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3262 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3263 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3266 case bfd_mach_ppc64:
3267 case bfd_mach_ppc_620:
3268 case bfd_mach_ppc_630:
3269 case bfd_mach_ppc_a35:
3270 case bfd_mach_ppc_rs64ii:
3271 case bfd_mach_ppc_rs64iii:
3272 /* These processor's register sets don't have segment registers. */
3273 tdep->ppc_sr0_regnum = -1;
3277 internal_error (__FILE__, __LINE__,
3278 _("rs6000_gdbarch_init: "
3279 "received unexpected BFD 'arch' value"));
3281 /* Sanity check on registers. */
3282 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3284 /* Select instruction printer. */
3285 if (arch == bfd_arch_rs6000)
3286 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3288 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3290 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3292 set_gdbarch_num_regs (gdbarch, v->nregs);
3293 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3294 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3295 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3296 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3298 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3299 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3300 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3301 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3302 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3303 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3304 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3306 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3308 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3309 set_gdbarch_char_signed (gdbarch, 0);
3311 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3312 if (sysv_abi && wordsize == 8)
3314 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3315 else if (!sysv_abi && wordsize == 4)
3316 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3317 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3318 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3320 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3322 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3323 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3324 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3326 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3327 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3328 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3329 is correct for the SysV ABI when the wordsize is 8, but I'm also
3330 fairly certain that ppc_sysv_abi_push_arguments() will give even
3331 worse results since it only works for 32-bit code. So, for the moment,
3332 we're better off calling rs6000_push_arguments() since it works for
3333 64-bit code. At some point in the future, this matter needs to be
3335 if (sysv_abi && wordsize == 4)
3336 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3337 else if (sysv_abi && wordsize == 8)
3338 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3340 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3342 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
3344 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3345 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3346 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3348 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3349 for the descriptor and ".FN" for the entry-point -- a user
3350 specifying "break FN" will unexpectedly end up with a breakpoint
3351 on the descriptor and not the function. This architecture method
3352 transforms any breakpoints on descriptors into breakpoints on the
3353 corresponding entry point. */
3354 if (sysv_abi && wordsize == 8)
3355 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3357 /* Not sure on this. FIXMEmgo */
3358 set_gdbarch_frame_args_skip (gdbarch, 8);
3361 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
3365 /* Handle RS/6000 function pointers (which are really function
3367 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3368 rs6000_convert_from_func_ptr_addr);
3371 /* Helpers for function argument information. */
3372 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3374 /* Hook in ABI-specific overrides, if they have been registered. */
3375 gdbarch_init_osabi (info, gdbarch);
3379 case GDB_OSABI_LINUX:
3380 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3381 have altivec registers. If not, ptrace will fail the first time it's
3382 called to access one and will not be called again. This wart will
3383 be removed when Daniel Jacobowitz's proposal for autodetecting target
3384 registers is implemented. */
3385 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3387 tdep->ppc_vr0_regnum = 71;
3388 tdep->ppc_vrsave_regnum = 104;
3391 case GDB_OSABI_NETBSD_AOUT:
3392 case GDB_OSABI_NETBSD_ELF:
3393 case GDB_OSABI_UNKNOWN:
3394 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3395 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3396 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3397 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3400 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3402 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3403 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3404 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3405 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3408 if (from_xcoff_exec)
3410 /* NOTE: jimix/2003-06-09: This test should really check for
3411 GDB_OSABI_AIX when that is defined and becomes
3412 available. (Actually, once things are properly split apart,
3413 the test goes away.) */
3414 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3415 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3418 init_sim_regno_table (gdbarch);
3424 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3426 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3431 /* FIXME: Dump gdbarch_tdep. */
3434 /* Initialization code. */
3436 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3439 _initialize_rs6000_tdep (void)
3441 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3442 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);