1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-505.c"
70 #include "features/rs6000/powerpc-601.c"
71 #include "features/rs6000/powerpc-602.c"
72 #include "features/rs6000/powerpc-603.c"
73 #include "features/rs6000/powerpc-604.c"
74 #include "features/rs6000/powerpc-64.c"
75 #include "features/rs6000/powerpc-altivec64.c"
76 #include "features/rs6000/powerpc-vsx64.c"
77 #include "features/rs6000/powerpc-7400.c"
78 #include "features/rs6000/powerpc-750.c"
79 #include "features/rs6000/powerpc-860.c"
80 #include "features/rs6000/powerpc-e500.c"
81 #include "features/rs6000/rs6000.c"
83 /* Determine if regnum is an SPE pseudo-register. */
84 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88 /* Determine if regnum is a decimal float pseudo-register. */
89 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93 /* Determine if regnum is a POWER7 VSX register. */
94 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98 /* Determine if regnum is a POWER7 Extended FP register. */
99 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
103 /* The list of available "set powerpc ..." and "show powerpc ..."
105 static struct cmd_list_element *setpowerpccmdlist = NULL;
106 static struct cmd_list_element *showpowerpccmdlist = NULL;
108 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111 static const char *powerpc_vector_strings[] =
120 /* A variable that can be configured by the user. */
121 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122 static const char *powerpc_vector_abi_string = "auto";
124 /* To be used by skip_prologue. */
126 struct rs6000_framedata
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
131 int saved_gpr; /* smallest # of saved gpr */
132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
133 int saved_fpr; /* smallest # of saved fpr */
134 int saved_vr; /* smallest # of saved vr */
135 int saved_ev; /* smallest # of saved ev */
136 int alloca_reg; /* alloca register number (frame ptr) */
137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
139 char used_bl; /* true if link register clobbered */
140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
142 int vr_offset; /* offset of saved vrs from prev sp */
143 int ev_offset; /* offset of saved evs from prev sp */
144 int lr_offset; /* offset of saved lr */
145 int lr_register; /* register of saved lr, if trustworthy */
146 int cr_offset; /* offset of saved cr */
147 int vrsave_offset; /* offset of saved vrsave register */
151 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153 vsx_register_p (struct gdbarch *gdbarch, int regno)
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
163 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165 altivec_register_p (struct gdbarch *gdbarch, int regno)
167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
175 /* Return true if REGNO is an SPE register, false otherwise. */
177 spe_register_p (struct gdbarch *gdbarch, int regno)
179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
182 if (IS_SPE_PSEUDOREG (tdep, regno))
185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
206 /* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
209 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
217 /* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
220 ppc_vsx_support_p (struct gdbarch *gdbarch)
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 return tdep->ppc_vsr0_regnum >= 0;
227 /* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230 ppc_altivec_support_p (struct gdbarch *gdbarch)
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
238 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
246 set_sim_regno (int *table, int gdb_regno, int sim_regno)
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
255 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
259 init_sim_regno_table (struct gdbarch *arch)
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
262 int total_regs = gdbarch_num_regs (arch);
263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292 /* Segment registers. */
293 for (i = 0; i < ppc_num_srs; i++)
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
316 /* vsave is a special-purpose register, so the code below handles it. */
318 /* SPE APU (E500) registers. */
319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
332 for (i = 0; i < sim_ppc_num_sprs; i++)
334 const char *spr_name = sim_spr_register_name (i);
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
350 /* Given a GDB register number REG, return the corresponding SIM
353 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
358 if (tdep->sim_regno == NULL)
359 init_sim_regno_table (gdbarch);
362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
364 sim_regno = tdep->sim_regno[reg];
369 return LEGACY_SIM_REGNO_IGNORE;
374 /* Register set support functions. */
376 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
380 ppc_supply_reg (struct regcache *regcache, int regnum,
381 const gdb_byte *regs, size_t offset, int regsize)
383 if (regnum != -1 && offset != -1)
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
393 regcache_raw_supply (regcache, regnum, regs + offset);
397 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
401 ppc_collect_reg (const struct regcache *regcache, int regnum,
402 gdb_byte *regs, size_t offset, int regsize)
404 if (regnum != -1 && offset != -1)
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
422 regcache_raw_collect (regcache, regnum, regs + offset);
427 ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
465 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
480 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
497 /* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
502 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
514 int gpr_size = offsets->gpr_size;
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
542 /* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
547 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
555 if (!ppc_floating_point_unit_p (gdbarch))
558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
579 /* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
584 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
590 if (!ppc_vsx_support_p (gdbarch))
593 tdep = gdbarch_tdep (gdbarch);
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
610 /* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
615 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
623 if (!ppc_altivec_support_p (gdbarch))
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 ppc_supply_reg (regcache, regnum,
654 /* Collect register REGNUM in the general-purpose register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 GREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
673 int gpr_size = offsets->gpr_size;
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
701 /* Collect register REGNUM in the floating-point register set
702 REGSET from register cache REGCACHE into the buffer specified by
703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
707 ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
716 if (!ppc_floating_point_unit_p (gdbarch))
719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
740 /* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
746 ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
753 if (!ppc_vsx_support_p (gdbarch))
756 tdep = gdbarch_tdep (gdbarch);
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
774 /* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
780 ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
789 if (!ppc_altivec_support_p (gdbarch))
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 ppc_collect_reg (regcache, regnum,
822 insn_changes_sp_or_jumps (unsigned long insn)
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
829 /* Changes the stack pointer. */
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
842 /* Transfers control. */
848 if (opcode == 19 && subcode == 16)
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
856 /* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
874 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
877 bfd_byte insn_buf[PPC_INSN_SIZE];
878 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
880 struct frame_info *curfrm;
882 /* Find the search limits based on function boundaries and hard limit. */
884 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
887 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
888 if (epilogue_start < func_start) epilogue_start = func_start;
890 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
891 if (epilogue_end > func_end) epilogue_end = func_end;
893 curfrm = get_current_frame ();
895 /* Scan forward until next 'blr'. */
897 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
899 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
901 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
902 if (insn == 0x4e800020)
904 /* Assume a bctr is a tail call unless it points strictly within
906 if (insn == 0x4e800420)
908 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
909 tdep->ppc_ctr_regnum);
910 if (ctr > func_start && ctr < func_end)
915 if (insn_changes_sp_or_jumps (insn))
919 /* Scan backward until adjustment to stack pointer (R1). */
921 for (scan_pc = pc - PPC_INSN_SIZE;
922 scan_pc >= epilogue_start;
923 scan_pc -= PPC_INSN_SIZE)
925 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
927 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
928 if (insn_changes_sp_or_jumps (insn))
935 /* Get the ith function argument for the current function. */
937 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
940 return get_frame_register_unsigned (frame, 3 + argi);
943 /* Sequence of bytes for breakpoint instruction. */
945 const static unsigned char *
946 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
949 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
950 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
952 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
953 return big_breakpoint;
955 return little_breakpoint;
958 /* Instruction masks for displaced stepping. */
959 #define BRANCH_MASK 0xfc000000
960 #define BP_MASK 0xFC0007FE
961 #define B_INSN 0x48000000
962 #define BC_INSN 0x40000000
963 #define BXL_INSN 0x4c000000
964 #define BP_INSN 0x7C000008
966 /* Fix up the state of registers and memory after having single-stepped
967 a displaced instruction. */
969 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
970 struct displaced_step_closure *closure,
971 CORE_ADDR from, CORE_ADDR to,
972 struct regcache *regs)
974 /* Since we use simple_displaced_step_copy_insn, our closure is a
975 copy of the instruction. */
976 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
979 /* Offset for non PC-relative instructions. */
980 LONGEST offset = PPC_INSN_SIZE;
982 opcode = insn & BRANCH_MASK;
985 fprintf_unfiltered (gdb_stdlog,
986 "displaced: (ppc) fixup (0x%s, 0x%s)\n",
987 paddr_nz (from), paddr_nz (to));
990 /* Handle PC-relative branch instructions. */
991 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
995 /* Read the current PC value after the instruction has been executed
996 in a displaced location. Calculate the offset to be applied to the
997 original PC value before the displaced stepping. */
998 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1000 offset = current_pc - to;
1002 if (opcode != BXL_INSN)
1004 /* Check for AA bit indicating whether this is an absolute
1005 addressing or PC-relative (1: absolute, 0: relative). */
1008 /* PC-relative addressing is being used in the branch. */
1009 if (debug_displaced)
1012 "displaced: (ppc) branch instruction: 0x%s\n"
1013 "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n",
1014 paddr_nz (insn), paddr_nz (current_pc),
1015 paddr_nz (from + offset));
1017 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1023 /* If we're here, it means we have a branch to LR or CTR. If the
1024 branch was taken, the offset is probably greater than 4 (the next
1025 instruction), so it's safe to assume that an offset of 4 means we
1026 did not take the branch. */
1027 if (offset == PPC_INSN_SIZE)
1028 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1029 from + PPC_INSN_SIZE);
1032 /* Check for LK bit indicating whether we should set the link
1033 register to point to the next instruction
1034 (1: Set, 0: Don't set). */
1037 /* Link register needs to be set to the next instruction's PC. */
1038 regcache_cooked_write_unsigned (regs,
1039 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1040 from + PPC_INSN_SIZE);
1041 if (debug_displaced)
1042 fprintf_unfiltered (gdb_stdlog,
1043 "displaced: (ppc) adjusted LR to 0x%s\n",
1044 paddr_nz (from + PPC_INSN_SIZE));
1048 /* Check for breakpoints in the inferior. If we've found one, place the PC
1049 right at the breakpoint instruction. */
1050 else if ((insn & BP_MASK) == BP_INSN)
1051 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1053 /* Handle any other instructions that do not fit in the categories above. */
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1058 /* Instruction masks used during single-stepping of atomic sequences. */
1059 #define LWARX_MASK 0xfc0007fe
1060 #define LWARX_INSTRUCTION 0x7c000028
1061 #define LDARX_INSTRUCTION 0x7c0000A8
1062 #define STWCX_MASK 0xfc0007ff
1063 #define STWCX_INSTRUCTION 0x7c00012d
1064 #define STDCX_INSTRUCTION 0x7c0001ad
1066 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1067 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1068 is found, attempt to step through it. A breakpoint is placed at the end of
1072 ppc_deal_with_atomic_sequence (struct frame_info *frame)
1074 CORE_ADDR pc = get_frame_pc (frame);
1075 CORE_ADDR breaks[2] = {-1, -1};
1077 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1078 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1081 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1082 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1083 int opcode; /* Branch instruction's OPcode. */
1084 int bc_insn_count = 0; /* Conditional branch instruction count. */
1086 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1087 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1088 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1091 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1093 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1095 loc += PPC_INSN_SIZE;
1096 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1098 /* Assume that there is at most one conditional branch in the atomic
1099 sequence. If a conditional branch is found, put a breakpoint in
1100 its destination address. */
1101 if ((insn & BRANCH_MASK) == BC_INSN)
1103 int immediate = ((insn & ~3) << 16) >> 16;
1104 int absolute = ((insn >> 1) & 1);
1106 if (bc_insn_count >= 1)
1107 return 0; /* More than one conditional branch found, fallback
1108 to the standard single-step code. */
1111 breaks[1] = immediate;
1113 breaks[1] = pc + immediate;
1119 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1120 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1124 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1125 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1126 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1130 loc += PPC_INSN_SIZE;
1131 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1133 /* Insert a breakpoint right after the end of the atomic sequence. */
1136 /* Check for duplicated breakpoints. Check also for a breakpoint
1137 placed (branch instruction's destination) at the stwcx/stdcx
1138 instruction, this resets the reservation and take us back to the
1139 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1140 if (last_breakpoint && ((breaks[1] == breaks[0])
1141 || (breaks[1] == closing_insn)))
1142 last_breakpoint = 0;
1144 /* Effectively inserts the breakpoints. */
1145 for (index = 0; index <= last_breakpoint; index++)
1146 insert_single_step_breakpoint (breaks[index]);
1152 #define SIGNED_SHORT(x) \
1153 ((sizeof (short) == 2) \
1154 ? ((int)(short)(x)) \
1155 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1157 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1159 /* Limit the number of skipped non-prologue instructions, as the examining
1160 of the prologue is expensive. */
1161 static int max_skip_non_prologue_insns = 10;
1163 /* Return nonzero if the given instruction OP can be part of the prologue
1164 of a function and saves a parameter on the stack. FRAMEP should be
1165 set if one of the previous instructions in the function has set the
1169 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1171 /* Move parameters from argument registers to temporary register. */
1172 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1174 /* Rx must be scratch register r0. */
1175 const int rx_regno = (op >> 16) & 31;
1176 /* Ry: Only r3 - r10 are used for parameter passing. */
1177 const int ry_regno = GET_SRC_REG (op);
1179 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1181 *r0_contains_arg = 1;
1188 /* Save a General Purpose Register on stack. */
1190 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1191 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1193 /* Rx: Only r3 - r10 are used for parameter passing. */
1194 const int rx_regno = GET_SRC_REG (op);
1196 return (rx_regno >= 3 && rx_regno <= 10);
1199 /* Save a General Purpose Register on stack via the Frame Pointer. */
1202 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1203 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1204 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1206 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1207 However, the compiler sometimes uses r0 to hold an argument. */
1208 const int rx_regno = GET_SRC_REG (op);
1210 return ((rx_regno >= 3 && rx_regno <= 10)
1211 || (rx_regno == 0 && *r0_contains_arg));
1214 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1216 /* Only f2 - f8 are used for parameter passing. */
1217 const int src_regno = GET_SRC_REG (op);
1219 return (src_regno >= 2 && src_regno <= 8);
1222 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1224 /* Only f2 - f8 are used for parameter passing. */
1225 const int src_regno = GET_SRC_REG (op);
1227 return (src_regno >= 2 && src_regno <= 8);
1230 /* Not an insn that saves a parameter on stack. */
1234 /* Assuming that INSN is a "bl" instruction located at PC, return
1235 nonzero if the destination of the branch is a "blrl" instruction.
1237 This sequence is sometimes found in certain function prologues.
1238 It allows the function to load the LR register with a value that
1239 they can use to access PIC data using PC-relative offsets. */
1242 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1249 absolute = (int) ((insn >> 1) & 1);
1250 immediate = ((insn & ~3) << 6) >> 6;
1254 dest = pc + immediate;
1256 dest_insn = read_memory_integer (dest, 4);
1257 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1263 /* Masks for decoding a branch-and-link (bl) instruction.
1265 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1266 The former is anded with the opcode in question; if the result of
1267 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1268 question is a ``bl'' instruction.
1270 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1271 the branch displacement. */
1273 #define BL_MASK 0xfc000001
1274 #define BL_INSTRUCTION 0x48000001
1275 #define BL_DISPLACEMENT_MASK 0x03fffffc
1277 static unsigned long
1278 rs6000_fetch_instruction (const CORE_ADDR pc)
1283 /* Fetch the instruction and convert it to an integer. */
1284 if (target_read_memory (pc, buf, 4))
1286 op = extract_unsigned_integer (buf, 4);
1291 /* GCC generates several well-known sequences of instructions at the begining
1292 of each function prologue when compiling with -fstack-check. If one of
1293 such sequences starts at START_PC, then return the address of the
1294 instruction immediately past this sequence. Otherwise, return START_PC. */
1297 rs6000_skip_stack_check (const CORE_ADDR start_pc)
1299 CORE_ADDR pc = start_pc;
1300 unsigned long op = rs6000_fetch_instruction (pc);
1302 /* First possible sequence: A small number of probes.
1303 stw 0, -<some immediate>(1)
1304 [repeat this instruction any (small) number of times]
1307 if ((op & 0xffff0000) == 0x90010000)
1309 while ((op & 0xffff0000) == 0x90010000)
1312 op = rs6000_fetch_instruction (pc);
1317 /* Second sequence: A probing loop.
1318 addi 12,1,-<some immediate>
1319 lis 0,-<some immediate>
1320 [possibly ori 0,0,<some immediate>]
1324 addi 12,12,-<some immediate>
1327 [possibly one last probe: stw 0,<some immediate>(12)]
1332 /* addi 12,1,-<some immediate> */
1333 if ((op & 0xffff0000) != 0x39810000)
1336 /* lis 0,-<some immediate> */
1338 op = rs6000_fetch_instruction (pc);
1339 if ((op & 0xffff0000) != 0x3c000000)
1343 op = rs6000_fetch_instruction (pc);
1344 /* [possibly ori 0,0,<some immediate>] */
1345 if ((op & 0xffff0000) == 0x60000000)
1348 op = rs6000_fetch_instruction (pc);
1351 if (op != 0x7c0c0214)
1356 op = rs6000_fetch_instruction (pc);
1357 if (op != 0x7c0c0000)
1362 op = rs6000_fetch_instruction (pc);
1363 if ((op & 0xff9f0001) != 0x41820000)
1366 /* addi 12,12,-<some immediate> */
1368 op = rs6000_fetch_instruction (pc);
1369 if ((op & 0xffff0000) != 0x398c0000)
1374 op = rs6000_fetch_instruction (pc);
1375 if (op != 0x900c0000)
1380 op = rs6000_fetch_instruction (pc);
1381 if ((op & 0xfc000001) != 0x48000000)
1384 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1386 op = rs6000_fetch_instruction (pc);
1387 if ((op & 0xffff0000) == 0x900c0000)
1390 op = rs6000_fetch_instruction (pc);
1393 /* We found a valid stack-check sequence, return the new PC. */
1397 /* Third sequence: No probe; instead, a comparizon between the stack size
1398 limit (saved in a run-time global variable) and the current stack
1401 addi 0,1,-<some immediate>
1402 lis 12,__gnat_stack_limit@ha
1403 lwz 12,__gnat_stack_limit@l(12)
1406 or, with a small variant in the case of a bigger stack frame:
1407 addis 0,1,<some immediate>
1408 addic 0,0,-<some immediate>
1409 lis 12,__gnat_stack_limit@ha
1410 lwz 12,__gnat_stack_limit@l(12)
1415 /* addi 0,1,-<some immediate> */
1416 if ((op & 0xffff0000) != 0x38010000)
1418 /* small stack frame variant not recognized; try the
1419 big stack frame variant: */
1421 /* addis 0,1,<some immediate> */
1422 if ((op & 0xffff0000) != 0x3c010000)
1425 /* addic 0,0,-<some immediate> */
1427 op = rs6000_fetch_instruction (pc);
1428 if ((op & 0xffff0000) != 0x30000000)
1432 /* lis 12,<some immediate> */
1434 op = rs6000_fetch_instruction (pc);
1435 if ((op & 0xffff0000) != 0x3d800000)
1438 /* lwz 12,<some immediate>(12) */
1440 op = rs6000_fetch_instruction (pc);
1441 if ((op & 0xffff0000) != 0x818c0000)
1446 op = rs6000_fetch_instruction (pc);
1447 if ((op & 0xfffffffe) != 0x7c406008)
1450 /* We found a valid stack-check sequence, return the new PC. */
1454 /* No stack check code in our prologue, return the start_pc. */
1458 /* return pc value after skipping a function prologue and also return
1459 information about a function frame.
1461 in struct rs6000_framedata fdata:
1462 - frameless is TRUE, if function does not have a frame.
1463 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1464 - offset is the initial size of this stack frame --- the amount by
1465 which we decrement the sp to allocate the frame.
1466 - saved_gpr is the number of the first saved gpr.
1467 - saved_fpr is the number of the first saved fpr.
1468 - saved_vr is the number of the first saved vr.
1469 - saved_ev is the number of the first saved ev.
1470 - alloca_reg is the number of the register used for alloca() handling.
1472 - gpr_offset is the offset of the first saved gpr from the previous frame.
1473 - fpr_offset is the offset of the first saved fpr from the previous frame.
1474 - vr_offset is the offset of the first saved vr from the previous frame.
1475 - ev_offset is the offset of the first saved ev from the previous frame.
1476 - lr_offset is the offset of the saved lr
1477 - cr_offset is the offset of the saved cr
1478 - vrsave_offset is the offset of the saved vrsave register
1482 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1483 struct rs6000_framedata *fdata)
1485 CORE_ADDR orig_pc = pc;
1486 CORE_ADDR last_prologue_pc = pc;
1487 CORE_ADDR li_found_pc = 0;
1491 long vr_saved_offset = 0;
1497 int vrsave_reg = -1;
1500 int minimal_toc_loaded = 0;
1501 int prev_insn_was_prologue_insn = 1;
1502 int num_skip_non_prologue_insns = 0;
1503 int r0_contains_arg = 0;
1504 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1505 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1507 memset (fdata, 0, sizeof (struct rs6000_framedata));
1508 fdata->saved_gpr = -1;
1509 fdata->saved_fpr = -1;
1510 fdata->saved_vr = -1;
1511 fdata->saved_ev = -1;
1512 fdata->alloca_reg = -1;
1513 fdata->frameless = 1;
1514 fdata->nosavedpc = 1;
1515 fdata->lr_register = -1;
1517 pc = rs6000_skip_stack_check (pc);
1523 /* Sometimes it isn't clear if an instruction is a prologue
1524 instruction or not. When we encounter one of these ambiguous
1525 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1526 Otherwise, we'll assume that it really is a prologue instruction. */
1527 if (prev_insn_was_prologue_insn)
1528 last_prologue_pc = pc;
1530 /* Stop scanning if we've hit the limit. */
1534 prev_insn_was_prologue_insn = 1;
1536 /* Fetch the instruction and convert it to an integer. */
1537 if (target_read_memory (pc, buf, 4))
1539 op = extract_unsigned_integer (buf, 4);
1541 if ((op & 0xfc1fffff) == 0x7c0802a6)
1543 /* Since shared library / PIC code, which needs to get its
1544 address at runtime, can appear to save more than one link
1558 remember just the first one, but skip over additional
1561 lr_reg = (op & 0x03e00000) >> 21;
1563 r0_contains_arg = 0;
1566 else if ((op & 0xfc1fffff) == 0x7c000026)
1568 cr_reg = (op & 0x03e00000);
1570 r0_contains_arg = 0;
1574 else if ((op & 0xfc1f0000) == 0xd8010000)
1575 { /* stfd Rx,NUM(r1) */
1576 reg = GET_SRC_REG (op);
1577 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1579 fdata->saved_fpr = reg;
1580 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1585 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1586 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1587 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1588 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1591 reg = GET_SRC_REG (op);
1592 if ((op & 0xfc1f0000) == 0xbc010000)
1593 fdata->gpr_mask |= ~((1U << reg) - 1);
1595 fdata->gpr_mask |= 1U << reg;
1596 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1598 fdata->saved_gpr = reg;
1599 if ((op & 0xfc1f0003) == 0xf8010000)
1601 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1606 else if ((op & 0xffff0000) == 0x60000000)
1609 /* Allow nops in the prologue, but do not consider them to
1610 be part of the prologue unless followed by other prologue
1612 prev_insn_was_prologue_insn = 0;
1616 else if ((op & 0xffff0000) == 0x3c000000)
1617 { /* addis 0,0,NUM, used
1618 for >= 32k frames */
1619 fdata->offset = (op & 0x0000ffff) << 16;
1620 fdata->frameless = 0;
1621 r0_contains_arg = 0;
1625 else if ((op & 0xffff0000) == 0x60000000)
1626 { /* ori 0,0,NUM, 2nd ha
1627 lf of >= 32k frames */
1628 fdata->offset |= (op & 0x0000ffff);
1629 fdata->frameless = 0;
1630 r0_contains_arg = 0;
1634 else if (lr_reg >= 0 &&
1635 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1636 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1637 /* stw Rx, NUM(r1) */
1638 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1639 /* stwu Rx, NUM(r1) */
1640 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1641 { /* where Rx == lr */
1642 fdata->lr_offset = offset;
1643 fdata->nosavedpc = 0;
1644 /* Invalidate lr_reg, but don't set it to -1.
1645 That would mean that it had never been set. */
1647 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1648 (op & 0xfc000000) == 0x90000000) /* stw */
1650 /* Does not update r1, so add displacement to lr_offset. */
1651 fdata->lr_offset += SIGNED_SHORT (op);
1656 else if (cr_reg >= 0 &&
1657 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1658 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1659 /* stw Rx, NUM(r1) */
1660 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1661 /* stwu Rx, NUM(r1) */
1662 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1663 { /* where Rx == cr */
1664 fdata->cr_offset = offset;
1665 /* Invalidate cr_reg, but don't set it to -1.
1666 That would mean that it had never been set. */
1668 if ((op & 0xfc000003) == 0xf8000000 ||
1669 (op & 0xfc000000) == 0x90000000)
1671 /* Does not update r1, so add displacement to cr_offset. */
1672 fdata->cr_offset += SIGNED_SHORT (op);
1677 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1679 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1680 prediction bits. If the LR has already been saved, we can
1684 else if (op == 0x48000005)
1691 else if (op == 0x48000004)
1696 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1697 in V.4 -mminimal-toc */
1698 (op & 0xffff0000) == 0x3bde0000)
1699 { /* addi 30,30,foo@l */
1703 else if ((op & 0xfc000001) == 0x48000001)
1707 fdata->frameless = 0;
1709 /* If the return address has already been saved, we can skip
1710 calls to blrl (for PIC). */
1711 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1717 /* Don't skip over the subroutine call if it is not within
1718 the first three instructions of the prologue and either
1719 we have no line table information or the line info tells
1720 us that the subroutine call is not part of the line
1721 associated with the prologue. */
1722 if ((pc - orig_pc) > 8)
1724 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1725 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1727 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1731 op = read_memory_integer (pc + 4, 4);
1733 /* At this point, make sure this is not a trampoline
1734 function (a function that simply calls another functions,
1735 and nothing else). If the next is not a nop, this branch
1736 was part of the function prologue. */
1738 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1739 break; /* don't skip over
1745 /* update stack pointer */
1746 else if ((op & 0xfc1f0000) == 0x94010000)
1747 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1748 fdata->frameless = 0;
1749 fdata->offset = SIGNED_SHORT (op);
1750 offset = fdata->offset;
1753 else if ((op & 0xfc1f016a) == 0x7c01016e)
1754 { /* stwux rX,r1,rY */
1755 /* no way to figure out what r1 is going to be */
1756 fdata->frameless = 0;
1757 offset = fdata->offset;
1760 else if ((op & 0xfc1f0003) == 0xf8010001)
1761 { /* stdu rX,NUM(r1) */
1762 fdata->frameless = 0;
1763 fdata->offset = SIGNED_SHORT (op & ~3UL);
1764 offset = fdata->offset;
1767 else if ((op & 0xfc1f016a) == 0x7c01016a)
1768 { /* stdux rX,r1,rY */
1769 /* no way to figure out what r1 is going to be */
1770 fdata->frameless = 0;
1771 offset = fdata->offset;
1774 else if ((op & 0xffff0000) == 0x38210000)
1775 { /* addi r1,r1,SIMM */
1776 fdata->frameless = 0;
1777 fdata->offset += SIGNED_SHORT (op);
1778 offset = fdata->offset;
1781 /* Load up minimal toc pointer. Do not treat an epilogue restore
1782 of r31 as a minimal TOC load. */
1783 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1784 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1786 && !minimal_toc_loaded)
1788 minimal_toc_loaded = 1;
1791 /* move parameters from argument registers to local variable
1794 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1795 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1796 (((op >> 21) & 31) <= 10) &&
1797 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1801 /* store parameters in stack */
1803 /* Move parameters from argument registers to temporary register. */
1804 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1808 /* Set up frame pointer */
1810 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1811 || op == 0x7c3f0b78)
1813 fdata->frameless = 0;
1815 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1818 /* Another way to set up the frame pointer. */
1820 else if ((op & 0xfc1fffff) == 0x38010000)
1821 { /* addi rX, r1, 0x0 */
1822 fdata->frameless = 0;
1824 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1825 + ((op & ~0x38010000) >> 21));
1828 /* AltiVec related instructions. */
1829 /* Store the vrsave register (spr 256) in another register for
1830 later manipulation, or load a register into the vrsave
1831 register. 2 instructions are used: mfvrsave and
1832 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1833 and mtspr SPR256, Rn. */
1834 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1835 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1836 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1838 vrsave_reg = GET_SRC_REG (op);
1841 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1845 /* Store the register where vrsave was saved to onto the stack:
1846 rS is the register where vrsave was stored in a previous
1848 /* 100100 sssss 00001 dddddddd dddddddd */
1849 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1851 if (vrsave_reg == GET_SRC_REG (op))
1853 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1858 /* Compute the new value of vrsave, by modifying the register
1859 where vrsave was saved to. */
1860 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1861 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1865 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1866 in a pair of insns to save the vector registers on the
1868 /* 001110 00000 00000 iiii iiii iiii iiii */
1869 /* 001110 01110 00000 iiii iiii iiii iiii */
1870 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1871 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1873 if ((op & 0xffff0000) == 0x38000000)
1874 r0_contains_arg = 0;
1876 vr_saved_offset = SIGNED_SHORT (op);
1878 /* This insn by itself is not part of the prologue, unless
1879 if part of the pair of insns mentioned above. So do not
1880 record this insn as part of the prologue yet. */
1881 prev_insn_was_prologue_insn = 0;
1883 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1884 /* 011111 sssss 11111 00000 00111001110 */
1885 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1887 if (pc == (li_found_pc + 4))
1889 vr_reg = GET_SRC_REG (op);
1890 /* If this is the first vector reg to be saved, or if
1891 it has a lower number than others previously seen,
1892 reupdate the frame info. */
1893 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1895 fdata->saved_vr = vr_reg;
1896 fdata->vr_offset = vr_saved_offset + offset;
1898 vr_saved_offset = -1;
1903 /* End AltiVec related instructions. */
1905 /* Start BookE related instructions. */
1906 /* Store gen register S at (r31+uimm).
1907 Any register less than r13 is volatile, so we don't care. */
1908 /* 000100 sssss 11111 iiiii 01100100001 */
1909 else if (arch_info->mach == bfd_mach_ppc_e500
1910 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1912 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1915 ev_reg = GET_SRC_REG (op);
1916 imm = (op >> 11) & 0x1f;
1917 ev_offset = imm * 8;
1918 /* If this is the first vector reg to be saved, or if
1919 it has a lower number than others previously seen,
1920 reupdate the frame info. */
1921 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1923 fdata->saved_ev = ev_reg;
1924 fdata->ev_offset = ev_offset + offset;
1929 /* Store gen register rS at (r1+rB). */
1930 /* 000100 sssss 00001 bbbbb 01100100000 */
1931 else if (arch_info->mach == bfd_mach_ppc_e500
1932 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1934 if (pc == (li_found_pc + 4))
1936 ev_reg = GET_SRC_REG (op);
1937 /* If this is the first vector reg to be saved, or if
1938 it has a lower number than others previously seen,
1939 reupdate the frame info. */
1940 /* We know the contents of rB from the previous instruction. */
1941 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1943 fdata->saved_ev = ev_reg;
1944 fdata->ev_offset = vr_saved_offset + offset;
1946 vr_saved_offset = -1;
1952 /* Store gen register r31 at (rA+uimm). */
1953 /* 000100 11111 aaaaa iiiii 01100100001 */
1954 else if (arch_info->mach == bfd_mach_ppc_e500
1955 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1957 /* Wwe know that the source register is 31 already, but
1958 it can't hurt to compute it. */
1959 ev_reg = GET_SRC_REG (op);
1960 ev_offset = ((op >> 11) & 0x1f) * 8;
1961 /* If this is the first vector reg to be saved, or if
1962 it has a lower number than others previously seen,
1963 reupdate the frame info. */
1964 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1966 fdata->saved_ev = ev_reg;
1967 fdata->ev_offset = ev_offset + offset;
1972 /* Store gen register S at (r31+r0).
1973 Store param on stack when offset from SP bigger than 4 bytes. */
1974 /* 000100 sssss 11111 00000 01100100000 */
1975 else if (arch_info->mach == bfd_mach_ppc_e500
1976 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1978 if (pc == (li_found_pc + 4))
1980 if ((op & 0x03e00000) >= 0x01a00000)
1982 ev_reg = GET_SRC_REG (op);
1983 /* If this is the first vector reg to be saved, or if
1984 it has a lower number than others previously seen,
1985 reupdate the frame info. */
1986 /* We know the contents of r0 from the previous
1988 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1990 fdata->saved_ev = ev_reg;
1991 fdata->ev_offset = vr_saved_offset + offset;
1995 vr_saved_offset = -1;
2000 /* End BookE related instructions. */
2004 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2006 /* Not a recognized prologue instruction.
2007 Handle optimizer code motions into the prologue by continuing
2008 the search if we have no valid frame yet or if the return
2009 address is not yet saved in the frame. Also skip instructions
2010 if some of the GPRs expected to be saved are not yet saved. */
2011 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2012 && (fdata->gpr_mask & all_mask) == all_mask)
2015 if (op == 0x4e800020 /* blr */
2016 || op == 0x4e800420) /* bctr */
2017 /* Do not scan past epilogue in frameless functions or
2020 if ((op & 0xf4000000) == 0x40000000) /* bxx */
2021 /* Never skip branches. */
2024 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2025 /* Do not scan too many insns, scanning insns is expensive with
2029 /* Continue scanning. */
2030 prev_insn_was_prologue_insn = 0;
2036 /* I have problems with skipping over __main() that I need to address
2037 * sometime. Previously, I used to use misc_function_vector which
2038 * didn't work as well as I wanted to be. -MGO */
2040 /* If the first thing after skipping a prolog is a branch to a function,
2041 this might be a call to an initializer in main(), introduced by gcc2.
2042 We'd like to skip over it as well. Fortunately, xlc does some extra
2043 work before calling a function right after a prologue, thus we can
2044 single out such gcc2 behaviour. */
2047 if ((op & 0xfc000001) == 0x48000001)
2048 { /* bl foo, an initializer function? */
2049 op = read_memory_integer (pc + 4, 4);
2051 if (op == 0x4def7b82)
2052 { /* cror 0xf, 0xf, 0xf (nop) */
2054 /* Check and see if we are in main. If so, skip over this
2055 initializer function as well. */
2057 tmp = find_pc_misc_function (pc);
2059 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2065 if (pc == lim_pc && lr_reg >= 0)
2066 fdata->lr_register = lr_reg;
2068 fdata->offset = -fdata->offset;
2069 return last_prologue_pc;
2073 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2075 struct rs6000_framedata frame;
2076 CORE_ADDR limit_pc, func_addr;
2078 /* See if we can determine the end of the prologue via the symbol table.
2079 If so, then return either PC, or the PC after the prologue, whichever
2081 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
2083 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
2084 if (post_prologue_pc != 0)
2085 return max (pc, post_prologue_pc);
2088 /* Can't determine prologue from the symbol table, need to examine
2091 /* Find an upper limit on the function prologue using the debug
2092 information. If the debug information could not be used to provide
2093 that bound, then use an arbitrary large number as the upper bound. */
2094 limit_pc = skip_prologue_using_sal (pc);
2096 limit_pc = pc + 100; /* Magic. */
2098 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2102 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2103 in the prologue of main().
2105 The function below examines the code pointed at by PC and checks to
2106 see if it corresponds to a call to __eabi. If so, it returns the
2107 address of the instruction following that call. Otherwise, it simply
2111 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2116 if (target_read_memory (pc, buf, 4))
2118 op = extract_unsigned_integer (buf, 4);
2120 if ((op & BL_MASK) == BL_INSTRUCTION)
2122 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2123 CORE_ADDR call_dest = pc + 4 + displ;
2124 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2126 /* We check for ___eabi (three leading underscores) in addition
2127 to __eabi in case the GCC option "-fleading-underscore" was
2128 used to compile the program. */
2130 && SYMBOL_LINKAGE_NAME (s) != NULL
2131 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2132 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2138 /* All the ABI's require 16 byte alignment. */
2140 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2142 return (addr & -16);
2145 /* Return whether handle_inferior_event() should proceed through code
2146 starting at PC in function NAME when stepping.
2148 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2149 handle memory references that are too distant to fit in instructions
2150 generated by the compiler. For example, if 'foo' in the following
2155 is greater than 32767, the linker might replace the lwz with a branch to
2156 somewhere in @FIX1 that does the load in 2 instructions and then branches
2157 back to where execution should continue.
2159 GDB should silently step over @FIX code, just like AIX dbx does.
2160 Unfortunately, the linker uses the "b" instruction for the
2161 branches, meaning that the link register doesn't get set.
2162 Therefore, GDB's usual step_over_function () mechanism won't work.
2164 Instead, use the gdbarch_skip_trampoline_code and
2165 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2169 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2171 return name && !strncmp (name, "@FIX", 4);
2174 /* Skip code that the user doesn't want to see when stepping:
2176 1. Indirect function calls use a piece of trampoline code to do context
2177 switching, i.e. to set the new TOC table. Skip such code if we are on
2178 its first instruction (as when we have single-stepped to here).
2180 2. Skip shared library trampoline code (which is different from
2181 indirect function call trampolines).
2183 3. Skip bigtoc fixup code.
2185 Result is desired PC to step until, or NULL if we are not in
2186 code that should be skipped. */
2189 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2191 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2192 unsigned int ii, op;
2194 CORE_ADDR solib_target_pc;
2195 struct minimal_symbol *msymbol;
2197 static unsigned trampoline_code[] =
2199 0x800b0000, /* l r0,0x0(r11) */
2200 0x90410014, /* st r2,0x14(r1) */
2201 0x7c0903a6, /* mtctr r0 */
2202 0x804b0004, /* l r2,0x4(r11) */
2203 0x816b0008, /* l r11,0x8(r11) */
2204 0x4e800420, /* bctr */
2205 0x4e800020, /* br */
2209 /* Check for bigtoc fixup code. */
2210 msymbol = lookup_minimal_symbol_by_pc (pc);
2212 && rs6000_in_solib_return_trampoline (pc, SYMBOL_LINKAGE_NAME (msymbol)))
2214 /* Double-check that the third instruction from PC is relative "b". */
2215 op = read_memory_integer (pc + 8, 4);
2216 if ((op & 0xfc000003) == 0x48000000)
2218 /* Extract bits 6-29 as a signed 24-bit relative word address and
2219 add it to the containing PC. */
2220 rel = ((int)(op << 6) >> 6);
2221 return pc + 8 + rel;
2225 /* If pc is in a shared library trampoline, return its target. */
2226 solib_target_pc = find_solib_trampoline_target (frame, pc);
2227 if (solib_target_pc)
2228 return solib_target_pc;
2230 for (ii = 0; trampoline_code[ii]; ++ii)
2232 op = read_memory_integer (pc + (ii * 4), 4);
2233 if (op != trampoline_code[ii])
2236 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
2237 pc = read_memory_unsigned_integer (ii, tdep->wordsize); /* (r11) value */
2241 /* ISA-specific vector types. */
2243 static struct type *
2244 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2246 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2248 if (!tdep->ppc_builtin_type_vec64)
2250 /* The type we're building is this: */
2252 union __gdb_builtin_type_vec64
2256 int32_t v2_int32[2];
2257 int16_t v4_int16[4];
2264 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2265 append_composite_type_field (t, "uint64", builtin_type_int64);
2266 append_composite_type_field (t, "v2_float",
2267 init_vector_type (builtin_type_float, 2));
2268 append_composite_type_field (t, "v2_int32",
2269 init_vector_type (builtin_type_int32, 2));
2270 append_composite_type_field (t, "v4_int16",
2271 init_vector_type (builtin_type_int16, 4));
2272 append_composite_type_field (t, "v8_int8",
2273 init_vector_type (builtin_type_int8, 8));
2275 TYPE_VECTOR (t) = 1;
2276 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2277 tdep->ppc_builtin_type_vec64 = t;
2280 return tdep->ppc_builtin_type_vec64;
2283 /* Vector 128 type. */
2285 static struct type *
2286 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2288 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2290 if (!tdep->ppc_builtin_type_vec128)
2292 /* The type we're building is this
2294 type = union __ppc_builtin_type_vec128 {
2297 int32_t v4_int32[4];
2298 int16_t v8_int16[8];
2299 int8_t v16_int8[16];
2305 t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2306 append_composite_type_field (t, "uint128", builtin_type_uint128);
2307 append_composite_type_field (t, "v4_float",
2308 init_vector_type (builtin_type (gdbarch)->builtin_float, 4));
2309 append_composite_type_field (t, "v4_int32",
2310 init_vector_type (builtin_type_int32, 4));
2311 append_composite_type_field (t, "v8_int16",
2312 init_vector_type (builtin_type_int16, 8));
2313 append_composite_type_field (t, "v16_int8",
2314 init_vector_type (builtin_type_int8, 16));
2316 TYPE_VECTOR (t) = 1;
2317 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2318 tdep->ppc_builtin_type_vec128 = t;
2321 return tdep->ppc_builtin_type_vec128;
2324 /* Return the name of register number REGNO, or the empty string if it
2325 is an anonymous register. */
2328 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2332 /* The upper half "registers" have names in the XML description,
2333 but we present only the low GPRs and the full 64-bit registers
2335 if (tdep->ppc_ev0_upper_regnum >= 0
2336 && tdep->ppc_ev0_upper_regnum <= regno
2337 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2340 /* Hide the upper halves of the vs0~vs31 registers. */
2341 if (tdep->ppc_vsr0_regnum >= 0
2342 && tdep->ppc_vsr0_upper_regnum <= regno
2343 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2346 /* Check if the SPE pseudo registers are available. */
2347 if (IS_SPE_PSEUDOREG (tdep, regno))
2349 static const char *const spe_regnames[] = {
2350 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2351 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2352 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2353 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2355 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2358 /* Check if the decimal128 pseudo-registers are available. */
2359 if (IS_DFP_PSEUDOREG (tdep, regno))
2361 static const char *const dfp128_regnames[] = {
2362 "dl0", "dl1", "dl2", "dl3",
2363 "dl4", "dl5", "dl6", "dl7",
2364 "dl8", "dl9", "dl10", "dl11",
2365 "dl12", "dl13", "dl14", "dl15"
2367 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2370 /* Check if this is a VSX pseudo-register. */
2371 if (IS_VSX_PSEUDOREG (tdep, regno))
2373 static const char *const vsx_regnames[] = {
2374 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2375 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2376 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2377 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2378 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2379 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2380 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2381 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2382 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2384 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2387 /* Check if the this is a Extended FP pseudo-register. */
2388 if (IS_EFP_PSEUDOREG (tdep, regno))
2390 static const char *const efpr_regnames[] = {
2391 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2392 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2393 "f46", "f47", "f48", "f49", "f50", "f51",
2394 "f52", "f53", "f54", "f55", "f56", "f57",
2395 "f58", "f59", "f60", "f61", "f62", "f63"
2397 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2400 return tdesc_register_name (gdbarch, regno);
2403 /* Return the GDB type object for the "standard" data type of data in
2406 static struct type *
2407 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2411 /* These are the only pseudo-registers we support. */
2412 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2413 || IS_DFP_PSEUDOREG (tdep, regnum)
2414 || IS_VSX_PSEUDOREG (tdep, regnum)
2415 || IS_EFP_PSEUDOREG (tdep, regnum));
2417 /* These are the e500 pseudo-registers. */
2418 if (IS_SPE_PSEUDOREG (tdep, regnum))
2419 return rs6000_builtin_type_vec64 (gdbarch);
2420 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2421 /* PPC decimal128 pseudo-registers. */
2422 return builtin_type (gdbarch)->builtin_declong;
2423 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2424 /* POWER7 VSX pseudo-registers. */
2425 return rs6000_builtin_type_vec128 (gdbarch);
2427 /* POWER7 Extended FP pseudo-registers. */
2428 return builtin_type (gdbarch)->builtin_double;
2431 /* Is REGNUM a member of REGGROUP? */
2433 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2434 struct reggroup *group)
2436 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2438 /* These are the only pseudo-registers we support. */
2439 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2440 || IS_DFP_PSEUDOREG (tdep, regnum)
2441 || IS_VSX_PSEUDOREG (tdep, regnum)
2442 || IS_EFP_PSEUDOREG (tdep, regnum));
2444 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2445 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2446 return group == all_reggroup || group == vector_reggroup;
2448 /* PPC decimal128 or Extended FP pseudo-registers. */
2449 return group == all_reggroup || group == float_reggroup;
2452 /* The register format for RS/6000 floating point registers is always
2453 double, we need a conversion if the memory format is float. */
2456 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2461 return (tdep->ppc_fp0_regnum >= 0
2462 && regnum >= tdep->ppc_fp0_regnum
2463 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2464 && TYPE_CODE (type) == TYPE_CODE_FLT
2465 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2469 rs6000_register_to_value (struct frame_info *frame,
2474 gdb_byte from[MAX_REGISTER_SIZE];
2476 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2478 get_frame_register (frame, regnum, from);
2479 convert_typed_floating (from, builtin_type_double, to, type);
2483 rs6000_value_to_register (struct frame_info *frame,
2486 const gdb_byte *from)
2488 gdb_byte to[MAX_REGISTER_SIZE];
2490 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2492 convert_typed_floating (from, type, to, builtin_type_double);
2493 put_frame_register (frame, regnum, to);
2496 /* Move SPE vector register values between a 64-bit buffer and the two
2497 32-bit raw register halves in a regcache. This function handles
2498 both splitting a 64-bit value into two 32-bit halves, and joining
2499 two halves into a whole 64-bit value, depending on the function
2500 passed as the MOVE argument.
2502 EV_REG must be the number of an SPE evN vector register --- a
2503 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2506 Call MOVE once for each 32-bit half of that register, passing
2507 REGCACHE, the number of the raw register corresponding to that
2508 half, and the address of the appropriate half of BUFFER.
2510 For example, passing 'regcache_raw_read' as the MOVE function will
2511 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2512 'regcache_raw_supply' will supply the contents of BUFFER to the
2513 appropriate pair of raw registers in REGCACHE.
2515 You may need to cast away some 'const' qualifiers when passing
2516 MOVE, since this function can't tell at compile-time which of
2517 REGCACHE or BUFFER is acting as the source of the data. If C had
2518 co-variant type qualifiers, ... */
2520 e500_move_ev_register (void (*move) (struct regcache *regcache,
2521 int regnum, gdb_byte *buf),
2522 struct regcache *regcache, int ev_reg,
2525 struct gdbarch *arch = get_regcache_arch (regcache);
2526 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2528 gdb_byte *byte_buffer = buffer;
2530 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2532 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2534 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2536 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2537 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2541 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2542 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2547 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2548 int reg_nr, gdb_byte *buffer)
2550 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2554 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2555 int reg_nr, const gdb_byte *buffer)
2557 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2559 regcache, reg_nr, (gdb_byte *) buffer);
2562 /* Read method for DFP pseudo-registers. */
2564 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2565 int reg_nr, gdb_byte *buffer)
2567 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2568 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2570 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2572 /* Read two FP registers to form a whole dl register. */
2573 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2574 2 * reg_index, buffer);
2575 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2576 2 * reg_index + 1, buffer + 8);
2580 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2581 2 * reg_index + 1, buffer + 8);
2582 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2583 2 * reg_index, buffer);
2587 /* Write method for DFP pseudo-registers. */
2589 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2590 int reg_nr, const gdb_byte *buffer)
2592 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2593 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2595 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2597 /* Write each half of the dl register into a separate
2599 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2600 2 * reg_index, buffer);
2601 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2602 2 * reg_index + 1, buffer + 8);
2606 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2607 2 * reg_index + 1, buffer + 8);
2608 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2609 2 * reg_index, buffer);
2613 /* Read method for POWER7 VSX pseudo-registers. */
2615 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2616 int reg_nr, gdb_byte *buffer)
2618 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2619 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2621 /* Read the portion that overlaps the VMX registers. */
2623 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2624 reg_index - 32, buffer);
2626 /* Read the portion that overlaps the FPR registers. */
2627 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2629 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2631 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2632 reg_index, buffer + 8);
2636 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2637 reg_index, buffer + 8);
2638 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2643 /* Write method for POWER7 VSX pseudo-registers. */
2645 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2646 int reg_nr, const gdb_byte *buffer)
2648 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2649 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2651 /* Write the portion that overlaps the VMX registers. */
2653 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2654 reg_index - 32, buffer);
2656 /* Write the portion that overlaps the FPR registers. */
2657 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2659 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2661 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2662 reg_index, buffer + 8);
2666 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2667 reg_index, buffer + 8);
2668 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2673 /* Read method for POWER7 Extended FP pseudo-registers. */
2675 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2676 int reg_nr, gdb_byte *buffer)
2678 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2679 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2681 /* Read the portion that overlaps the VMX registers. */
2682 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2686 /* Write method for POWER7 Extended FP pseudo-registers. */
2688 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2689 int reg_nr, const gdb_byte *buffer)
2691 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2692 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2694 /* Write the portion that overlaps the VMX registers. */
2695 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2700 rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2701 int reg_nr, gdb_byte *buffer)
2703 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2704 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2706 gdb_assert (regcache_arch == gdbarch);
2708 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2709 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2710 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2711 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2712 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2713 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2714 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2715 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2717 internal_error (__FILE__, __LINE__,
2718 _("rs6000_pseudo_register_read: "
2719 "called on unexpected register '%s' (%d)"),
2720 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2724 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2725 struct regcache *regcache,
2726 int reg_nr, const gdb_byte *buffer)
2728 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2729 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2731 gdb_assert (regcache_arch == gdbarch);
2733 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2734 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2735 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2736 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2737 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2738 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2739 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2740 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2742 internal_error (__FILE__, __LINE__,
2743 _("rs6000_pseudo_register_write: "
2744 "called on unexpected register '%s' (%d)"),
2745 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2748 /* Convert a DBX STABS register number to a GDB register number. */
2750 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2752 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2754 if (0 <= num && num <= 31)
2755 return tdep->ppc_gp0_regnum + num;
2756 else if (32 <= num && num <= 63)
2757 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2758 specifies registers the architecture doesn't have? Our
2759 callers don't check the value we return. */
2760 return tdep->ppc_fp0_regnum + (num - 32);
2761 else if (77 <= num && num <= 108)
2762 return tdep->ppc_vr0_regnum + (num - 77);
2763 else if (1200 <= num && num < 1200 + 32)
2764 return tdep->ppc_ev0_regnum + (num - 1200);
2769 return tdep->ppc_mq_regnum;
2771 return tdep->ppc_lr_regnum;
2773 return tdep->ppc_ctr_regnum;
2775 return tdep->ppc_xer_regnum;
2777 return tdep->ppc_vrsave_regnum;
2779 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2781 return tdep->ppc_acc_regnum;
2783 return tdep->ppc_spefscr_regnum;
2790 /* Convert a Dwarf 2 register number to a GDB register number. */
2792 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2796 if (0 <= num && num <= 31)
2797 return tdep->ppc_gp0_regnum + num;
2798 else if (32 <= num && num <= 63)
2799 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2800 specifies registers the architecture doesn't have? Our
2801 callers don't check the value we return. */
2802 return tdep->ppc_fp0_regnum + (num - 32);
2803 else if (1124 <= num && num < 1124 + 32)
2804 return tdep->ppc_vr0_regnum + (num - 1124);
2805 else if (1200 <= num && num < 1200 + 32)
2806 return tdep->ppc_ev0_regnum + (num - 1200);
2811 return tdep->ppc_cr_regnum;
2813 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2815 return tdep->ppc_acc_regnum;
2817 return tdep->ppc_mq_regnum;
2819 return tdep->ppc_xer_regnum;
2821 return tdep->ppc_lr_regnum;
2823 return tdep->ppc_ctr_regnum;
2825 return tdep->ppc_vrsave_regnum;
2827 return tdep->ppc_spefscr_regnum;
2833 /* Translate a .eh_frame register to DWARF register, or adjust a
2834 .debug_frame register. */
2837 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2839 /* GCC releases before 3.4 use GCC internal register numbering in
2840 .debug_frame (and .debug_info, et cetera). The numbering is
2841 different from the standard SysV numbering for everything except
2842 for GPRs and FPRs. We can not detect this problem in most cases
2843 - to get accurate debug info for variables living in lr, ctr, v0,
2844 et cetera, use a newer version of GCC. But we must detect
2845 one important case - lr is in column 65 in .debug_frame output,
2848 GCC 3.4, and the "hammer" branch, have a related problem. They
2849 record lr register saves in .debug_frame as 108, but still record
2850 the return column as 65. We fix that up too.
2852 We can do this because 65 is assigned to fpsr, and GCC never
2853 generates debug info referring to it. To add support for
2854 handwritten debug info that restores fpsr, we would need to add a
2855 producer version check to this. */
2864 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2865 internal register numbering; translate that to the standard DWARF2
2866 register numbering. */
2867 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2869 else if (68 <= num && num <= 75) /* cr0-cr8 */
2870 return num - 68 + 86;
2871 else if (77 <= num && num <= 108) /* vr0-vr31 */
2872 return num - 77 + 1124;
2884 case 109: /* vrsave */
2886 case 110: /* vscr */
2888 case 111: /* spe_acc */
2890 case 112: /* spefscr */
2898 /* Handling the various POWER/PowerPC variants. */
2900 /* Information about a particular processor variant. */
2904 /* Name of this variant. */
2907 /* English description of the variant. */
2910 /* bfd_arch_info.arch corresponding to variant. */
2911 enum bfd_architecture arch;
2913 /* bfd_arch_info.mach corresponding to variant. */
2916 /* Target description for this variant. */
2917 struct target_desc **tdesc;
2920 static struct variant variants[] =
2922 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2923 bfd_mach_ppc, &tdesc_powerpc_altivec32},
2924 {"power", "POWER user-level", bfd_arch_rs6000,
2925 bfd_mach_rs6k, &tdesc_rs6000},
2926 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2927 bfd_mach_ppc_403, &tdesc_powerpc_403},
2928 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2929 bfd_mach_ppc_601, &tdesc_powerpc_601},
2930 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2931 bfd_mach_ppc_602, &tdesc_powerpc_602},
2932 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2933 bfd_mach_ppc_603, &tdesc_powerpc_603},
2934 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2935 604, &tdesc_powerpc_604},
2936 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2937 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
2938 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2939 bfd_mach_ppc_505, &tdesc_powerpc_505},
2940 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2941 bfd_mach_ppc_860, &tdesc_powerpc_860},
2942 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2943 bfd_mach_ppc_750, &tdesc_powerpc_750},
2944 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2945 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
2946 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2947 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
2950 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2951 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
2952 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2953 bfd_mach_ppc_620, &tdesc_powerpc_64},
2954 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2955 bfd_mach_ppc_630, &tdesc_powerpc_64},
2956 {"a35", "PowerPC A35", bfd_arch_powerpc,
2957 bfd_mach_ppc_a35, &tdesc_powerpc_64},
2958 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2959 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
2960 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2961 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
2963 /* FIXME: I haven't checked the register sets of the following. */
2964 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2965 bfd_mach_rs6k_rs1, &tdesc_rs6000},
2966 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2967 bfd_mach_rs6k_rsc, &tdesc_rs6000},
2968 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2969 bfd_mach_rs6k_rs2, &tdesc_rs6000},
2974 /* Return the variant corresponding to architecture ARCH and machine number
2975 MACH. If no such variant exists, return null. */
2977 static const struct variant *
2978 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2980 const struct variant *v;
2982 for (v = variants; v->name; v++)
2983 if (arch == v->arch && mach == v->mach)
2990 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2992 if (!info->disassembler_options)
2993 info->disassembler_options = "any";
2995 if (info->endian == BFD_ENDIAN_BIG)
2996 return print_insn_big_powerpc (memaddr, info);
2998 return print_insn_little_powerpc (memaddr, info);
3002 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3004 return frame_unwind_register_unsigned (next_frame,
3005 gdbarch_pc_regnum (gdbarch));
3008 static struct frame_id
3009 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3011 return frame_id_build (get_frame_register_unsigned
3012 (this_frame, gdbarch_sp_regnum (gdbarch)),
3013 get_frame_pc (this_frame));
3016 struct rs6000_frame_cache
3019 CORE_ADDR initial_sp;
3020 struct trad_frame_saved_reg *saved_regs;
3023 static struct rs6000_frame_cache *
3024 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3026 struct rs6000_frame_cache *cache;
3027 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3028 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3029 struct rs6000_framedata fdata;
3030 int wordsize = tdep->wordsize;
3033 if ((*this_cache) != NULL)
3034 return (*this_cache);
3035 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3036 (*this_cache) = cache;
3037 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3039 func = get_frame_func (this_frame);
3040 pc = get_frame_pc (this_frame);
3041 skip_prologue (gdbarch, func, pc, &fdata);
3043 /* Figure out the parent's stack pointer. */
3045 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3046 address of the current frame. Things might be easier if the
3047 ->frame pointed to the outer-most address of the frame. In
3048 the mean time, the address of the prev frame is used as the
3049 base address of this frame. */
3050 cache->base = get_frame_register_unsigned
3051 (this_frame, gdbarch_sp_regnum (gdbarch));
3053 /* If the function appears to be frameless, check a couple of likely
3054 indicators that we have simply failed to find the frame setup.
3055 Two common cases of this are missing symbols (i.e.
3056 get_frame_func returns the wrong address or 0), and assembly
3057 stubs which have a fast exit path but set up a frame on the slow
3060 If the LR appears to return to this function, then presume that
3061 we have an ABI compliant frame that we failed to find. */
3062 if (fdata.frameless && fdata.lr_offset == 0)
3067 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3068 if (func == 0 && saved_lr == pc)
3072 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3073 if (func == saved_func)
3079 fdata.frameless = 0;
3080 fdata.lr_offset = tdep->lr_frame_offset;
3084 if (!fdata.frameless)
3085 /* Frameless really means stackless. */
3086 cache->base = read_memory_unsigned_integer (cache->base, wordsize);
3088 trad_frame_set_value (cache->saved_regs,
3089 gdbarch_sp_regnum (gdbarch), cache->base);
3091 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3092 All fpr's from saved_fpr to fp31 are saved. */
3094 if (fdata.saved_fpr >= 0)
3097 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3099 /* If skip_prologue says floating-point registers were saved,
3100 but the current architecture has no floating-point registers,
3101 then that's strange. But we have no indices to even record
3102 the addresses under, so we just ignore it. */
3103 if (ppc_floating_point_unit_p (gdbarch))
3104 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3106 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3111 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3112 All gpr's from saved_gpr to gpr31 are saved (except during the
3115 if (fdata.saved_gpr >= 0)
3118 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3119 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3121 if (fdata.gpr_mask & (1U << i))
3122 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3123 gpr_addr += wordsize;
3127 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3128 All vr's from saved_vr to vr31 are saved. */
3129 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3131 if (fdata.saved_vr >= 0)
3134 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3135 for (i = fdata.saved_vr; i < 32; i++)
3137 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3138 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3143 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3144 All vr's from saved_ev to ev31 are saved. ????? */
3145 if (tdep->ppc_ev0_regnum != -1)
3147 if (fdata.saved_ev >= 0)
3150 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3151 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3153 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3154 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3155 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3160 /* If != 0, fdata.cr_offset is the offset from the frame that
3162 if (fdata.cr_offset != 0)
3163 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3165 /* If != 0, fdata.lr_offset is the offset from the frame that
3167 if (fdata.lr_offset != 0)
3168 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3169 else if (fdata.lr_register != -1)
3170 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3171 /* The PC is found in the link register. */
3172 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3173 cache->saved_regs[tdep->ppc_lr_regnum];
3175 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3176 holds the VRSAVE. */
3177 if (fdata.vrsave_offset != 0)
3178 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3180 if (fdata.alloca_reg < 0)
3181 /* If no alloca register used, then fi->frame is the value of the
3182 %sp for this frame, and it is good enough. */
3184 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3187 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3193 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3194 struct frame_id *this_id)
3196 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3198 /* This marks the outermost frame. */
3199 if (info->base == 0)
3202 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3205 static struct value *
3206 rs6000_frame_prev_register (struct frame_info *this_frame,
3207 void **this_cache, int regnum)
3209 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3211 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3214 static const struct frame_unwind rs6000_frame_unwind =
3217 rs6000_frame_this_id,
3218 rs6000_frame_prev_register,
3220 default_frame_sniffer
3225 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3227 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3229 return info->initial_sp;
3232 static const struct frame_base rs6000_frame_base = {
3233 &rs6000_frame_unwind,
3234 rs6000_frame_base_address,
3235 rs6000_frame_base_address,
3236 rs6000_frame_base_address
3239 static const struct frame_base *
3240 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3242 return &rs6000_frame_base;
3245 /* DWARF-2 frame support. Used to handle the detection of
3246 clobbered registers during function calls. */
3249 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3250 struct dwarf2_frame_state_reg *reg,
3251 struct frame_info *this_frame)
3253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3255 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3256 non-volatile registers. We will use the same code for both. */
3258 /* Call-saved GP registers. */
3259 if ((regnum >= tdep->ppc_gp0_regnum + 14
3260 && regnum <= tdep->ppc_gp0_regnum + 31)
3261 || (regnum == tdep->ppc_gp0_regnum + 1))
3262 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3264 /* Call-clobbered GP registers. */
3265 if ((regnum >= tdep->ppc_gp0_regnum + 3
3266 && regnum <= tdep->ppc_gp0_regnum + 12)
3267 || (regnum == tdep->ppc_gp0_regnum))
3268 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3270 /* Deal with FP registers, if supported. */
3271 if (tdep->ppc_fp0_regnum >= 0)
3273 /* Call-saved FP registers. */
3274 if ((regnum >= tdep->ppc_fp0_regnum + 14
3275 && regnum <= tdep->ppc_fp0_regnum + 31))
3276 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3278 /* Call-clobbered FP registers. */
3279 if ((regnum >= tdep->ppc_fp0_regnum
3280 && regnum <= tdep->ppc_fp0_regnum + 13))
3281 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3284 /* Deal with ALTIVEC registers, if supported. */
3285 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3287 /* Call-saved Altivec registers. */
3288 if ((regnum >= tdep->ppc_vr0_regnum + 20
3289 && regnum <= tdep->ppc_vr0_regnum + 31)
3290 || regnum == tdep->ppc_vrsave_regnum)
3291 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3293 /* Call-clobbered Altivec registers. */
3294 if ((regnum >= tdep->ppc_vr0_regnum
3295 && regnum <= tdep->ppc_vr0_regnum + 19))
3296 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3299 /* Handle PC register and Stack Pointer correctly. */
3300 if (regnum == gdbarch_pc_regnum (gdbarch))
3301 reg->how = DWARF2_FRAME_REG_RA;
3302 else if (regnum == gdbarch_sp_regnum (gdbarch))
3303 reg->how = DWARF2_FRAME_REG_CFA;
3307 /* Initialize the current architecture based on INFO. If possible, re-use an
3308 architecture from ARCHES, which is a list of architectures already created
3309 during this debugging session.
3311 Called e.g. at program startup, when reading a core file, and when reading
3314 static struct gdbarch *
3315 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3317 struct gdbarch *gdbarch;
3318 struct gdbarch_tdep *tdep;
3319 int wordsize, from_xcoff_exec, from_elf_exec;
3320 enum bfd_architecture arch;
3324 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3326 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3327 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3329 int tdesc_wordsize = -1;
3330 const struct target_desc *tdesc = info.target_desc;
3331 struct tdesc_arch_data *tdesc_data = NULL;
3332 int num_pseudoregs = 0;
3335 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3336 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3338 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3339 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3341 /* Check word size. If INFO is from a binary file, infer it from
3342 that, else choose a likely default. */
3343 if (from_xcoff_exec)
3345 if (bfd_xcoff_is_xcoff64 (info.abfd))
3350 else if (from_elf_exec)
3352 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3357 else if (tdesc_has_registers (tdesc))
3361 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3362 wordsize = info.bfd_arch_info->bits_per_word /
3363 info.bfd_arch_info->bits_per_byte;
3368 /* Get the architecture and machine from the BFD. */
3369 arch = info.bfd_arch_info->arch;
3370 mach = info.bfd_arch_info->mach;
3372 /* For e500 executables, the apuinfo section is of help here. Such
3373 section contains the identifier and revision number of each
3374 Application-specific Processing Unit that is present on the
3375 chip. The content of the section is determined by the assembler
3376 which looks at each instruction and determines which unit (and
3377 which version of it) can execute it. In our case we just look for
3378 the existance of the section. */
3382 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3385 arch = info.bfd_arch_info->arch;
3386 mach = bfd_mach_ppc_e500;
3387 bfd_default_set_arch_mach (&abfd, arch, mach);
3388 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3392 /* Find a default target description which describes our register
3393 layout, if we do not already have one. */
3394 if (! tdesc_has_registers (tdesc))
3396 const struct variant *v;
3398 /* Choose variant. */
3399 v = find_variant_by_arch (arch, mach);
3406 gdb_assert (tdesc_has_registers (tdesc));
3408 /* Check any target description for validity. */
3409 if (tdesc_has_registers (tdesc))
3411 static const char *const gprs[] = {
3412 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3413 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3414 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3415 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3417 static const char *const segment_regs[] = {
3418 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3419 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3421 const struct tdesc_feature *feature;
3423 static const char *const msr_names[] = { "msr", "ps" };
3424 static const char *const cr_names[] = { "cr", "cnd" };
3425 static const char *const ctr_names[] = { "ctr", "cnt" };
3427 feature = tdesc_find_feature (tdesc,
3428 "org.gnu.gdb.power.core");
3429 if (feature == NULL)
3432 tdesc_data = tdesc_data_alloc ();
3435 for (i = 0; i < ppc_num_gprs; i++)
3436 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3437 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3439 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3441 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3444 /* Allow alternate names for these registers, to accomodate GDB's
3446 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3447 PPC_MSR_REGNUM, msr_names);
3448 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3449 PPC_CR_REGNUM, cr_names);
3450 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3451 PPC_CTR_REGNUM, ctr_names);
3455 tdesc_data_cleanup (tdesc_data);
3459 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3462 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3464 wordsize = tdesc_wordsize;
3466 feature = tdesc_find_feature (tdesc,
3467 "org.gnu.gdb.power.fpu");
3468 if (feature != NULL)
3470 static const char *const fprs[] = {
3471 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3472 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3473 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3474 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3477 for (i = 0; i < ppc_num_fprs; i++)
3478 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3479 PPC_F0_REGNUM + i, fprs[i]);
3480 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3481 PPC_FPSCR_REGNUM, "fpscr");
3485 tdesc_data_cleanup (tdesc_data);
3493 /* The DFP pseudo-registers will be available when there are floating
3495 have_dfp = have_fpu;
3497 feature = tdesc_find_feature (tdesc,
3498 "org.gnu.gdb.power.altivec");
3499 if (feature != NULL)
3501 static const char *const vector_regs[] = {
3502 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3503 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3504 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3505 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3509 for (i = 0; i < ppc_num_gprs; i++)
3510 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3513 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3514 PPC_VSCR_REGNUM, "vscr");
3515 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3516 PPC_VRSAVE_REGNUM, "vrsave");
3518 if (have_spe || !valid_p)
3520 tdesc_data_cleanup (tdesc_data);
3528 /* Check for POWER7 VSX registers support. */
3529 feature = tdesc_find_feature (tdesc,
3530 "org.gnu.gdb.power.vsx");
3532 if (feature != NULL)
3534 static const char *const vsx_regs[] = {
3535 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3536 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3537 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3538 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3539 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3545 for (i = 0; i < ppc_num_vshrs; i++)
3546 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3547 PPC_VSR0_UPPER_REGNUM + i,
3551 tdesc_data_cleanup (tdesc_data);
3560 /* On machines supporting the SPE APU, the general-purpose registers
3561 are 64 bits long. There are SIMD vector instructions to treat them
3562 as pairs of floats, but the rest of the instruction set treats them
3563 as 32-bit registers, and only operates on their lower halves.
3565 In the GDB regcache, we treat their high and low halves as separate
3566 registers. The low halves we present as the general-purpose
3567 registers, and then we have pseudo-registers that stitch together
3568 the upper and lower halves and present them as pseudo-registers.
3570 Thus, the target description is expected to supply the upper
3571 halves separately. */
3573 feature = tdesc_find_feature (tdesc,
3574 "org.gnu.gdb.power.spe");
3575 if (feature != NULL)
3577 static const char *const upper_spe[] = {
3578 "ev0h", "ev1h", "ev2h", "ev3h",
3579 "ev4h", "ev5h", "ev6h", "ev7h",
3580 "ev8h", "ev9h", "ev10h", "ev11h",
3581 "ev12h", "ev13h", "ev14h", "ev15h",
3582 "ev16h", "ev17h", "ev18h", "ev19h",
3583 "ev20h", "ev21h", "ev22h", "ev23h",
3584 "ev24h", "ev25h", "ev26h", "ev27h",
3585 "ev28h", "ev29h", "ev30h", "ev31h"
3589 for (i = 0; i < ppc_num_gprs; i++)
3590 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3591 PPC_SPE_UPPER_GP0_REGNUM + i,
3593 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3594 PPC_SPE_ACC_REGNUM, "acc");
3595 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3596 PPC_SPE_FSCR_REGNUM, "spefscr");
3598 if (have_mq || have_fpu || !valid_p)
3600 tdesc_data_cleanup (tdesc_data);
3609 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3610 complain for a 32-bit binary on a 64-bit target; we do not yet
3611 support that. For instance, the 32-bit ABI routines expect
3614 As long as there isn't an explicit target description, we'll
3615 choose one based on the BFD architecture and get a word size
3616 matching the binary (probably powerpc:common or
3617 powerpc:common64). So there is only trouble if a 64-bit target
3618 supplies a 64-bit description while debugging a 32-bit
3620 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3622 tdesc_data_cleanup (tdesc_data);
3627 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3629 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3630 Tag_GNU_Power_ABI_FP))
3633 soft_float_flag = AUTO_BOOLEAN_FALSE;
3636 soft_float_flag = AUTO_BOOLEAN_TRUE;
3643 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3645 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3646 Tag_GNU_Power_ABI_Vector))
3649 vector_abi = POWERPC_VEC_GENERIC;
3652 vector_abi = POWERPC_VEC_ALTIVEC;
3655 vector_abi = POWERPC_VEC_SPE;
3663 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3665 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3668 soft_float = !have_fpu;
3670 /* If we have a hard float binary or setting but no floating point
3671 registers, downgrade to soft float anyway. We're still somewhat
3672 useful in this scenario. */
3673 if (!soft_float && !have_fpu)
3676 /* Similarly for vector registers. */
3677 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3678 vector_abi = POWERPC_VEC_GENERIC;
3680 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3681 vector_abi = POWERPC_VEC_GENERIC;
3683 if (vector_abi == POWERPC_VEC_AUTO)
3686 vector_abi = POWERPC_VEC_ALTIVEC;
3688 vector_abi = POWERPC_VEC_SPE;
3690 vector_abi = POWERPC_VEC_GENERIC;
3693 /* Do not limit the vector ABI based on available hardware, since we
3694 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3696 /* Find a candidate among extant architectures. */
3697 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3699 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3701 /* Word size in the various PowerPC bfd_arch_info structs isn't
3702 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3703 separate word size check. */
3704 tdep = gdbarch_tdep (arches->gdbarch);
3705 if (tdep && tdep->soft_float != soft_float)
3707 if (tdep && tdep->vector_abi != vector_abi)
3709 if (tdep && tdep->wordsize == wordsize)
3711 if (tdesc_data != NULL)
3712 tdesc_data_cleanup (tdesc_data);
3713 return arches->gdbarch;
3717 /* None found, create a new architecture from INFO, whose bfd_arch_info
3718 validity depends on the source:
3719 - executable useless
3720 - rs6000_host_arch() good
3722 - "set arch" trust blindly
3723 - GDB startup useless but harmless */
3725 tdep = XCALLOC (1, struct gdbarch_tdep);
3726 tdep->wordsize = wordsize;
3727 tdep->soft_float = soft_float;
3728 tdep->vector_abi = vector_abi;
3730 gdbarch = gdbarch_alloc (&info, tdep);
3732 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3733 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3734 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3735 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3736 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3737 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3738 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3739 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3741 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3742 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3743 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
3744 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3745 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3746 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3747 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3748 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3750 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3751 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3752 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3753 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3754 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3756 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3757 GDB traditionally called it "ps", though, so let GDB add an
3759 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3762 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3764 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3766 /* Set lr_frame_offset. */
3768 tdep->lr_frame_offset = 16;
3770 tdep->lr_frame_offset = 4;
3772 if (have_spe || have_dfp || have_vsx)
3774 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3775 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
3778 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3780 /* Select instruction printer. */
3781 if (arch == bfd_arch_rs6000)
3782 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3784 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3786 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
3789 num_pseudoregs += 32;
3791 num_pseudoregs += 16;
3793 /* Include both VSX and Extended FP registers. */
3794 num_pseudoregs += 96;
3796 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
3798 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3799 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3800 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3801 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3802 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3803 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3804 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3805 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3806 set_gdbarch_char_signed (gdbarch, 0);
3808 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3811 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3813 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3814 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3815 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3817 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3818 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3821 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3822 else if (wordsize == 8)
3823 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3825 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3826 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3827 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
3829 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3830 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3832 /* The value of symbols of type N_SO and N_FUN maybe null when
3834 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3836 /* Handles single stepping of atomic sequences. */
3837 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
3839 /* Not sure on this. FIXMEmgo */
3840 set_gdbarch_frame_args_skip (gdbarch, 8);
3842 /* Helpers for function argument information. */
3843 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3846 set_gdbarch_in_solib_return_trampoline
3847 (gdbarch, rs6000_in_solib_return_trampoline);
3848 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3850 /* Hook in the DWARF CFI frame unwinder. */
3851 dwarf2_append_unwinders (gdbarch);
3852 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3854 /* Frame handling. */
3855 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3857 /* Setup displaced stepping. */
3858 set_gdbarch_displaced_step_copy_insn (gdbarch,
3859 simple_displaced_step_copy_insn);
3860 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3861 set_gdbarch_displaced_step_free_closure (gdbarch,
3862 simple_displaced_step_free_closure);
3863 set_gdbarch_displaced_step_location (gdbarch,
3864 displaced_step_at_entry_point);
3866 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3868 /* Hook in ABI-specific overrides, if they have been registered. */
3869 info.target_desc = tdesc;
3870 info.tdep_info = (void *) tdesc_data;
3871 gdbarch_init_osabi (info, gdbarch);
3875 case GDB_OSABI_LINUX:
3876 case GDB_OSABI_NETBSD_AOUT:
3877 case GDB_OSABI_NETBSD_ELF:
3878 case GDB_OSABI_UNKNOWN:
3879 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3880 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3881 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
3882 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3885 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3887 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3888 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3889 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
3890 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3893 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3894 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3895 rs6000_pseudo_register_reggroup_p);
3896 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3898 /* Override the normal target description method to make the SPE upper
3899 halves anonymous. */
3900 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3902 /* Choose register numbers for all supported pseudo-registers. */
3903 tdep->ppc_ev0_regnum = -1;
3904 tdep->ppc_dl0_regnum = -1;
3905 tdep->ppc_vsr0_regnum = -1;
3906 tdep->ppc_efpr0_regnum = -1;
3908 cur_reg = gdbarch_num_regs (gdbarch);
3912 tdep->ppc_ev0_regnum = cur_reg;
3917 tdep->ppc_dl0_regnum = cur_reg;
3922 tdep->ppc_vsr0_regnum = cur_reg;
3924 tdep->ppc_efpr0_regnum = cur_reg;
3928 gdb_assert (gdbarch_num_regs (gdbarch)
3929 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
3935 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3937 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3942 /* FIXME: Dump gdbarch_tdep. */
3945 /* PowerPC-specific commands. */
3948 set_powerpc_command (char *args, int from_tty)
3950 printf_unfiltered (_("\
3951 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3952 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3956 show_powerpc_command (char *args, int from_tty)
3958 cmd_show_list (showpowerpccmdlist, from_tty, "");
3962 powerpc_set_soft_float (char *args, int from_tty,
3963 struct cmd_list_element *c)
3965 struct gdbarch_info info;
3967 /* Update the architecture. */
3968 gdbarch_info_init (&info);
3969 if (!gdbarch_update_p (info))
3970 internal_error (__FILE__, __LINE__, "could not update architecture");
3974 powerpc_set_vector_abi (char *args, int from_tty,
3975 struct cmd_list_element *c)
3977 struct gdbarch_info info;
3978 enum powerpc_vector_abi vector_abi;
3980 for (vector_abi = POWERPC_VEC_AUTO;
3981 vector_abi != POWERPC_VEC_LAST;
3983 if (strcmp (powerpc_vector_abi_string,
3984 powerpc_vector_strings[vector_abi]) == 0)
3986 powerpc_vector_abi_global = vector_abi;
3990 if (vector_abi == POWERPC_VEC_LAST)
3991 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
3992 powerpc_vector_abi_string);
3994 /* Update the architecture. */
3995 gdbarch_info_init (&info);
3996 if (!gdbarch_update_p (info))
3997 internal_error (__FILE__, __LINE__, "could not update architecture");
4000 /* Initialization code. */
4002 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
4005 _initialize_rs6000_tdep (void)
4007 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4008 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
4010 /* Initialize the standard target descriptions. */
4011 initialize_tdesc_powerpc_32 ();
4012 initialize_tdesc_powerpc_altivec32 ();
4013 initialize_tdesc_powerpc_vsx32 ();
4014 initialize_tdesc_powerpc_403 ();
4015 initialize_tdesc_powerpc_403gc ();
4016 initialize_tdesc_powerpc_505 ();
4017 initialize_tdesc_powerpc_601 ();
4018 initialize_tdesc_powerpc_602 ();
4019 initialize_tdesc_powerpc_603 ();
4020 initialize_tdesc_powerpc_604 ();
4021 initialize_tdesc_powerpc_64 ();
4022 initialize_tdesc_powerpc_altivec64 ();
4023 initialize_tdesc_powerpc_vsx64 ();
4024 initialize_tdesc_powerpc_7400 ();
4025 initialize_tdesc_powerpc_750 ();
4026 initialize_tdesc_powerpc_860 ();
4027 initialize_tdesc_powerpc_e500 ();
4028 initialize_tdesc_rs6000 ();
4030 /* Add root prefix command for all "set powerpc"/"show powerpc"
4032 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4033 _("Various PowerPC-specific commands."),
4034 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4036 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4037 _("Various PowerPC-specific commands."),
4038 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4040 /* Add a command to allow the user to force the ABI. */
4041 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4042 &powerpc_soft_float_global,
4043 _("Set whether to use a soft-float ABI."),
4044 _("Show whether to use a soft-float ABI."),
4046 powerpc_set_soft_float, NULL,
4047 &setpowerpccmdlist, &showpowerpccmdlist);
4049 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4050 &powerpc_vector_abi_string,
4051 _("Set the vector ABI."),
4052 _("Show the vector ABI."),
4053 NULL, powerpc_set_vector_abi, NULL,
4054 &setpowerpccmdlist, &showpowerpccmdlist);