1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
43 #include "dwarf2-frame.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
56 #include "gdb_assert.h"
59 #include "trad-frame.h"
60 #include "frame-unwind.h"
61 #include "frame-base.h"
63 #include "rs6000-tdep.h"
65 /* If the kernel has to deliver a signal, it pushes a sigcontext
66 structure on the stack and then calls the signal handler, passing
67 the address of the sigcontext in an argument register. Usually
68 the signal handler doesn't save this register, so we have to
69 access the sigcontext structure via an offset from the signal handler
71 The following constants were determined by experimentation on AIX 3.2. */
72 #define SIG_FRAME_PC_OFFSET 96
73 #define SIG_FRAME_LR_OFFSET 108
74 #define SIG_FRAME_FP_OFFSET 284
76 /* To be used by skip_prologue. */
78 struct rs6000_framedata
80 int offset; /* total size of frame --- the distance
81 by which we decrement sp to allocate
83 int saved_gpr; /* smallest # of saved gpr */
84 int saved_fpr; /* smallest # of saved fpr */
85 int saved_vr; /* smallest # of saved vr */
86 int saved_ev; /* smallest # of saved ev */
87 int alloca_reg; /* alloca register number (frame ptr) */
88 char frameless; /* true if frameless functions. */
89 char nosavedpc; /* true if pc not saved. */
90 int gpr_offset; /* offset of saved gprs from prev sp */
91 int fpr_offset; /* offset of saved fprs from prev sp */
92 int vr_offset; /* offset of saved vrs from prev sp */
93 int ev_offset; /* offset of saved evs from prev sp */
94 int lr_offset; /* offset of saved lr */
95 int cr_offset; /* offset of saved cr */
96 int vrsave_offset; /* offset of saved vrsave register */
99 /* Description of a single register. */
103 char *name; /* name of register */
104 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
105 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
106 unsigned char fpr; /* whether register is floating-point */
107 unsigned char pseudo; /* whether register is pseudo */
108 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
109 This is an ISA SPR number, not a GDB
113 /* Hook for determining the TOC address when calling functions in the
114 inferior under AIX. The initialization code in rs6000-nat.c sets
115 this hook to point to find_toc_address. */
117 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
119 /* Static function prototypes */
121 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
123 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
124 struct rs6000_framedata *);
126 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
128 altivec_register_p (int regno)
130 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
131 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
134 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
138 /* Return true if REGNO is an SPE register, false otherwise. */
140 spe_register_p (int regno)
142 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
144 /* Is it a reference to EV0 -- EV31, and do we have those? */
145 if (tdep->ppc_ev0_regnum >= 0
146 && tdep->ppc_ev31_regnum >= 0
147 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
150 /* Is it a reference to one of the raw upper GPR halves? */
151 if (tdep->ppc_ev0_upper_regnum >= 0
152 && tdep->ppc_ev0_upper_regnum <= regno
153 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
156 /* Is it a reference to the 64-bit accumulator, and do we have that? */
157 if (tdep->ppc_acc_regnum >= 0
158 && tdep->ppc_acc_regnum == regno)
161 /* Is it a reference to the SPE floating-point status and control register,
162 and do we have that? */
163 if (tdep->ppc_spefscr_regnum >= 0
164 && tdep->ppc_spefscr_regnum == regno)
171 /* Return non-zero if the architecture described by GDBARCH has
172 floating-point registers (f0 --- f31 and fpscr). */
174 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
178 return (tdep->ppc_fp0_regnum >= 0
179 && tdep->ppc_fpscr_regnum >= 0);
183 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
186 This is a helper function for init_sim_regno_table, constructing
187 the table mapping GDB register numbers to sim register numbers; we
188 initialize every element in that table to -1 before we start
191 set_sim_regno (int *table, int gdb_regno, int sim_regno)
193 /* Make sure we don't try to assign any given GDB register a sim
194 register number more than once. */
195 gdb_assert (table[gdb_regno] == -1);
196 table[gdb_regno] = sim_regno;
200 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
201 numbers to simulator register numbers, based on the values placed
202 in the ARCH->tdep->ppc_foo_regnum members. */
204 init_sim_regno_table (struct gdbarch *arch)
206 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
207 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
208 const struct reg *regs = tdep->regs;
209 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
212 /* Presume that all registers not explicitly mentioned below are
213 unavailable from the sim. */
214 for (i = 0; i < total_regs; i++)
217 /* General-purpose registers. */
218 for (i = 0; i < ppc_num_gprs; i++)
219 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
221 /* Floating-point registers. */
222 if (tdep->ppc_fp0_regnum >= 0)
223 for (i = 0; i < ppc_num_fprs; i++)
224 set_sim_regno (sim_regno,
225 tdep->ppc_fp0_regnum + i,
226 sim_ppc_f0_regnum + i);
227 if (tdep->ppc_fpscr_regnum >= 0)
228 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
230 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
231 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
232 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
234 /* Segment registers. */
235 if (tdep->ppc_sr0_regnum >= 0)
236 for (i = 0; i < ppc_num_srs; i++)
237 set_sim_regno (sim_regno,
238 tdep->ppc_sr0_regnum + i,
239 sim_ppc_sr0_regnum + i);
241 /* Altivec registers. */
242 if (tdep->ppc_vr0_regnum >= 0)
244 for (i = 0; i < ppc_num_vrs; i++)
245 set_sim_regno (sim_regno,
246 tdep->ppc_vr0_regnum + i,
247 sim_ppc_vr0_regnum + i);
249 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
250 we can treat this more like the other cases. */
251 set_sim_regno (sim_regno,
252 tdep->ppc_vr0_regnum + ppc_num_vrs,
253 sim_ppc_vscr_regnum);
255 /* vsave is a special-purpose register, so the code below handles it. */
257 /* SPE APU (E500) registers. */
258 if (tdep->ppc_ev0_regnum >= 0)
259 for (i = 0; i < ppc_num_gprs; i++)
260 set_sim_regno (sim_regno,
261 tdep->ppc_ev0_regnum + i,
262 sim_ppc_ev0_regnum + i);
263 if (tdep->ppc_ev0_upper_regnum >= 0)
264 for (i = 0; i < ppc_num_gprs; i++)
265 set_sim_regno (sim_regno,
266 tdep->ppc_ev0_upper_regnum + i,
267 sim_ppc_rh0_regnum + i);
268 if (tdep->ppc_acc_regnum >= 0)
269 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
270 /* spefscr is a special-purpose register, so the code below handles it. */
272 /* Now handle all special-purpose registers. Verify that they
273 haven't mistakenly been assigned numbers by any of the above
275 for (i = 0; i < total_regs; i++)
276 if (regs[i].spr_num >= 0)
277 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
279 /* Drop the initialized array into place. */
280 tdep->sim_regno = sim_regno;
284 /* Given a GDB register number REG, return the corresponding SIM
287 rs6000_register_sim_regno (int reg)
289 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
292 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
293 sim_regno = tdep->sim_regno[reg];
298 return LEGACY_SIM_REGNO_IGNORE;
303 /* Register set support functions. */
306 ppc_supply_reg (struct regcache *regcache, int regnum,
307 const gdb_byte *regs, size_t offset)
309 if (regnum != -1 && offset != -1)
310 regcache_raw_supply (regcache, regnum, regs + offset);
314 ppc_collect_reg (const struct regcache *regcache, int regnum,
315 gdb_byte *regs, size_t offset)
317 if (regnum != -1 && offset != -1)
318 regcache_raw_collect (regcache, regnum, regs + offset);
321 /* Supply register REGNUM in the general-purpose register set REGSET
322 from the buffer specified by GREGS and LEN to register cache
323 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
326 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
327 int regnum, const void *gregs, size_t len)
329 struct gdbarch *gdbarch = get_regcache_arch (regcache);
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
331 const struct ppc_reg_offsets *offsets = regset->descr;
335 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
336 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
339 if (regnum == -1 || regnum == i)
340 ppc_supply_reg (regcache, i, gregs, offset);
343 if (regnum == -1 || regnum == PC_REGNUM)
344 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
345 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
346 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
347 gregs, offsets->ps_offset);
348 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
349 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
350 gregs, offsets->cr_offset);
351 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
352 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
353 gregs, offsets->lr_offset);
354 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
355 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
356 gregs, offsets->ctr_offset);
357 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
358 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
359 gregs, offsets->cr_offset);
360 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
361 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
364 /* Supply register REGNUM in the floating-point register set REGSET
365 from the buffer specified by FPREGS and LEN to register cache
366 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
369 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
370 int regnum, const void *fpregs, size_t len)
372 struct gdbarch *gdbarch = get_regcache_arch (regcache);
373 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
374 const struct ppc_reg_offsets *offsets = regset->descr;
378 gdb_assert (ppc_floating_point_unit_p (gdbarch));
380 offset = offsets->f0_offset;
381 for (i = tdep->ppc_fp0_regnum;
382 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
385 if (regnum == -1 || regnum == i)
386 ppc_supply_reg (regcache, i, fpregs, offset);
389 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
390 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
391 fpregs, offsets->fpscr_offset);
394 /* Collect register REGNUM in the general-purpose register set
395 REGSET. from register cache REGCACHE into the buffer specified by
396 GREGS and LEN. If REGNUM is -1, do this for all registers in
400 ppc_collect_gregset (const struct regset *regset,
401 const struct regcache *regcache,
402 int regnum, void *gregs, size_t len)
404 struct gdbarch *gdbarch = get_regcache_arch (regcache);
405 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
406 const struct ppc_reg_offsets *offsets = regset->descr;
410 offset = offsets->r0_offset;
411 for (i = tdep->ppc_gp0_regnum;
412 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
415 if (regnum == -1 || regnum == i)
416 ppc_collect_reg (regcache, i, gregs, offset);
419 if (regnum == -1 || regnum == PC_REGNUM)
420 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
421 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
422 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
423 gregs, offsets->ps_offset);
424 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
425 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
426 gregs, offsets->cr_offset);
427 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
428 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
429 gregs, offsets->lr_offset);
430 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
431 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
432 gregs, offsets->ctr_offset);
433 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
434 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
435 gregs, offsets->xer_offset);
436 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
437 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
438 gregs, offsets->mq_offset);
441 /* Collect register REGNUM in the floating-point register set
442 REGSET. from register cache REGCACHE into the buffer specified by
443 FPREGS and LEN. If REGNUM is -1, do this for all registers in
447 ppc_collect_fpregset (const struct regset *regset,
448 const struct regcache *regcache,
449 int regnum, void *fpregs, size_t len)
451 struct gdbarch *gdbarch = get_regcache_arch (regcache);
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 const struct ppc_reg_offsets *offsets = regset->descr;
457 gdb_assert (ppc_floating_point_unit_p (gdbarch));
459 offset = offsets->f0_offset;
460 for (i = tdep->ppc_fp0_regnum;
461 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
464 if (regnum == -1 || regnum == i)
465 ppc_collect_reg (regcache, i, fpregs, offset);
468 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
469 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
470 fpregs, offsets->fpscr_offset);
474 /* Read a LEN-byte address from debugged memory address MEMADDR. */
477 read_memory_addr (CORE_ADDR memaddr, int len)
479 return read_memory_unsigned_integer (memaddr, len);
483 rs6000_skip_prologue (CORE_ADDR pc)
485 struct rs6000_framedata frame;
486 CORE_ADDR limit_pc, func_addr;
488 /* See if we can determine the end of the prologue via the symbol table.
489 If so, then return either PC, or the PC after the prologue, whichever
491 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
493 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
494 if (post_prologue_pc != 0)
495 return max (pc, post_prologue_pc);
498 /* Can't determine prologue from the symbol table, need to examine
501 /* Find an upper limit on the function prologue using the debug
502 information. If the debug information could not be used to provide
503 that bound, then use an arbitrary large number as the upper bound. */
504 limit_pc = skip_prologue_using_sal (pc);
506 limit_pc = pc + 100; /* Magic. */
508 pc = skip_prologue (pc, limit_pc, &frame);
513 insn_changes_sp_or_jumps (unsigned long insn)
515 int opcode = (insn >> 26) & 0x03f;
516 int sd = (insn >> 21) & 0x01f;
517 int a = (insn >> 16) & 0x01f;
518 int subcode = (insn >> 1) & 0x3ff;
520 /* Changes the stack pointer. */
522 /* NOTE: There are many ways to change the value of a given register.
523 The ways below are those used when the register is R1, the SP,
524 in a funtion's epilogue. */
526 if (opcode == 31 && subcode == 444 && a == 1)
527 return 1; /* mr R1,Rn */
528 if (opcode == 14 && sd == 1)
529 return 1; /* addi R1,Rn,simm */
530 if (opcode == 58 && sd == 1)
531 return 1; /* ld R1,ds(Rn) */
533 /* Transfers control. */
539 if (opcode == 19 && subcode == 16)
541 if (opcode == 19 && subcode == 528)
542 return 1; /* bcctr */
547 /* Return true if we are in the function's epilogue, i.e. after the
548 instruction that destroyed the function's stack frame.
550 1) scan forward from the point of execution:
551 a) If you find an instruction that modifies the stack pointer
552 or transfers control (except a return), execution is not in
554 b) Stop scanning if you find a return instruction or reach the
555 end of the function or reach the hard limit for the size of
557 2) scan backward from the point of execution:
558 a) If you find an instruction that modifies the stack pointer,
559 execution *is* in an epilogue, return.
560 b) Stop scanning if you reach an instruction that transfers
561 control or the beginning of the function or reach the hard
562 limit for the size of an epilogue. */
565 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
567 bfd_byte insn_buf[PPC_INSN_SIZE];
568 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
570 struct frame_info *curfrm;
572 /* Find the search limits based on function boundaries and hard limit. */
574 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
577 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
578 if (epilogue_start < func_start) epilogue_start = func_start;
580 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
581 if (epilogue_end > func_end) epilogue_end = func_end;
583 curfrm = get_current_frame ();
585 /* Scan forward until next 'blr'. */
587 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
589 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
591 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
592 if (insn == 0x4e800020)
594 if (insn_changes_sp_or_jumps (insn))
598 /* Scan backward until adjustment to stack pointer (R1). */
600 for (scan_pc = pc - PPC_INSN_SIZE;
601 scan_pc >= epilogue_start;
602 scan_pc -= PPC_INSN_SIZE)
604 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
606 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
607 if (insn_changes_sp_or_jumps (insn))
615 /* Fill in fi->saved_regs */
617 struct frame_extra_info
619 /* Functions calling alloca() change the value of the stack
620 pointer. We need to use initial stack pointer (which is saved in
621 r31 by gcc) in such cases. If a compiler emits traceback table,
622 then we should use the alloca register specified in traceback
624 CORE_ADDR initial_sp; /* initial stack pointer. */
627 /* Get the ith function argument for the current function. */
629 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
632 return get_frame_register_unsigned (frame, 3 + argi);
635 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
638 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
645 absolute = (int) ((instr >> 1) & 1);
650 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
654 dest = pc + immediate;
658 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
662 dest = pc + immediate;
666 ext_op = (instr >> 1) & 0x3ff;
668 if (ext_op == 16) /* br conditional register */
670 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
672 /* If we are about to return from a signal handler, dest is
673 something like 0x3c90. The current frame is a signal handler
674 caller frame, upon completion of the sigreturn system call
675 execution will return to the saved PC in the frame. */
676 if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base)
678 struct frame_info *fi;
680 fi = get_current_frame ();
682 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
683 gdbarch_tdep (current_gdbarch)->wordsize);
687 else if (ext_op == 528) /* br cond to count reg */
689 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
691 /* If we are about to execute a system call, dest is something
692 like 0x22fc or 0x3b00. Upon completion the system call
693 will return to the address in the link register. */
694 if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base)
695 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
704 return (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) ? safety : dest;
708 /* Sequence of bytes for breakpoint instruction. */
710 const static unsigned char *
711 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
713 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
714 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
716 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
717 return big_breakpoint;
719 return little_breakpoint;
723 /* AIX does not support PT_STEP. Simulate it. */
726 rs6000_software_single_step (enum target_signal signal,
727 int insert_breakpoints_p)
731 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
737 if (insert_breakpoints_p)
741 insn = read_memory_integer (loc, 4);
743 breaks[0] = loc + breakp_sz;
745 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
747 /* Don't put two breakpoints on the same address. */
748 if (breaks[1] == breaks[0])
751 for (ii = 0; ii < 2; ++ii)
753 /* ignore invalid breakpoint. */
754 if (breaks[ii] == -1)
756 insert_single_step_breakpoint (breaks[ii]);
760 remove_single_step_breakpoints ();
762 errno = 0; /* FIXME, don't ignore errors! */
763 /* What errors? {read,write}_memory call error(). */
768 /* return pc value after skipping a function prologue and also return
769 information about a function frame.
771 in struct rs6000_framedata fdata:
772 - frameless is TRUE, if function does not have a frame.
773 - nosavedpc is TRUE, if function does not save %pc value in its frame.
774 - offset is the initial size of this stack frame --- the amount by
775 which we decrement the sp to allocate the frame.
776 - saved_gpr is the number of the first saved gpr.
777 - saved_fpr is the number of the first saved fpr.
778 - saved_vr is the number of the first saved vr.
779 - saved_ev is the number of the first saved ev.
780 - alloca_reg is the number of the register used for alloca() handling.
782 - gpr_offset is the offset of the first saved gpr from the previous frame.
783 - fpr_offset is the offset of the first saved fpr from the previous frame.
784 - vr_offset is the offset of the first saved vr from the previous frame.
785 - ev_offset is the offset of the first saved ev from the previous frame.
786 - lr_offset is the offset of the saved lr
787 - cr_offset is the offset of the saved cr
788 - vrsave_offset is the offset of the saved vrsave register
791 #define SIGNED_SHORT(x) \
792 ((sizeof (short) == 2) \
793 ? ((int)(short)(x)) \
794 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
796 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
798 /* Limit the number of skipped non-prologue instructions, as the examining
799 of the prologue is expensive. */
800 static int max_skip_non_prologue_insns = 10;
802 /* Return nonzero if the given instruction OP can be part of the prologue
803 of a function and saves a parameter on the stack. FRAMEP should be
804 set if one of the previous instructions in the function has set the
808 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
810 /* Move parameters from argument registers to temporary register. */
811 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
813 /* Rx must be scratch register r0. */
814 const int rx_regno = (op >> 16) & 31;
815 /* Ry: Only r3 - r10 are used for parameter passing. */
816 const int ry_regno = GET_SRC_REG (op);
818 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
820 *r0_contains_arg = 1;
827 /* Save a General Purpose Register on stack. */
829 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
830 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
832 /* Rx: Only r3 - r10 are used for parameter passing. */
833 const int rx_regno = GET_SRC_REG (op);
835 return (rx_regno >= 3 && rx_regno <= 10);
838 /* Save a General Purpose Register on stack via the Frame Pointer. */
841 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
842 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
843 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
845 /* Rx: Usually, only r3 - r10 are used for parameter passing.
846 However, the compiler sometimes uses r0 to hold an argument. */
847 const int rx_regno = GET_SRC_REG (op);
849 return ((rx_regno >= 3 && rx_regno <= 10)
850 || (rx_regno == 0 && *r0_contains_arg));
853 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
855 /* Only f2 - f8 are used for parameter passing. */
856 const int src_regno = GET_SRC_REG (op);
858 return (src_regno >= 2 && src_regno <= 8);
861 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
863 /* Only f2 - f8 are used for parameter passing. */
864 const int src_regno = GET_SRC_REG (op);
866 return (src_regno >= 2 && src_regno <= 8);
869 /* Not an insn that saves a parameter on stack. */
873 /* Assuming that INSN is a "bl" instruction located at PC, return
874 nonzero if the destination of the branch is a "blrl" instruction.
876 This sequence is sometimes found in certain function prologues.
877 It allows the function to load the LR register with a value that
878 they can use to access PIC data using PC-relative offsets. */
881 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
883 const int opcode = 18;
884 const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1);
888 return 0; /* Should never happen, but just return zero to be safe. */
890 dest_insn = read_memory_integer (dest, 4);
891 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
898 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
900 CORE_ADDR orig_pc = pc;
901 CORE_ADDR last_prologue_pc = pc;
902 CORE_ADDR li_found_pc = 0;
906 long vr_saved_offset = 0;
915 int minimal_toc_loaded = 0;
916 int prev_insn_was_prologue_insn = 1;
917 int num_skip_non_prologue_insns = 0;
918 int r0_contains_arg = 0;
919 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
920 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
922 memset (fdata, 0, sizeof (struct rs6000_framedata));
923 fdata->saved_gpr = -1;
924 fdata->saved_fpr = -1;
925 fdata->saved_vr = -1;
926 fdata->saved_ev = -1;
927 fdata->alloca_reg = -1;
928 fdata->frameless = 1;
929 fdata->nosavedpc = 1;
933 /* Sometimes it isn't clear if an instruction is a prologue
934 instruction or not. When we encounter one of these ambiguous
935 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
936 Otherwise, we'll assume that it really is a prologue instruction. */
937 if (prev_insn_was_prologue_insn)
938 last_prologue_pc = pc;
940 /* Stop scanning if we've hit the limit. */
944 prev_insn_was_prologue_insn = 1;
946 /* Fetch the instruction and convert it to an integer. */
947 if (target_read_memory (pc, buf, 4))
949 op = extract_unsigned_integer (buf, 4);
951 if ((op & 0xfc1fffff) == 0x7c0802a6)
953 /* Since shared library / PIC code, which needs to get its
954 address at runtime, can appear to save more than one link
968 remember just the first one, but skip over additional
971 lr_reg = (op & 0x03e00000);
976 else if ((op & 0xfc1fffff) == 0x7c000026)
978 cr_reg = (op & 0x03e00000);
984 else if ((op & 0xfc1f0000) == 0xd8010000)
985 { /* stfd Rx,NUM(r1) */
986 reg = GET_SRC_REG (op);
987 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
989 fdata->saved_fpr = reg;
990 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
995 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
996 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
997 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
998 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1001 reg = GET_SRC_REG (op);
1002 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1004 fdata->saved_gpr = reg;
1005 if ((op & 0xfc1f0003) == 0xf8010000)
1007 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1012 else if ((op & 0xffff0000) == 0x60000000)
1015 /* Allow nops in the prologue, but do not consider them to
1016 be part of the prologue unless followed by other prologue
1018 prev_insn_was_prologue_insn = 0;
1022 else if ((op & 0xffff0000) == 0x3c000000)
1023 { /* addis 0,0,NUM, used
1024 for >= 32k frames */
1025 fdata->offset = (op & 0x0000ffff) << 16;
1026 fdata->frameless = 0;
1027 r0_contains_arg = 0;
1031 else if ((op & 0xffff0000) == 0x60000000)
1032 { /* ori 0,0,NUM, 2nd ha
1033 lf of >= 32k frames */
1034 fdata->offset |= (op & 0x0000ffff);
1035 fdata->frameless = 0;
1036 r0_contains_arg = 0;
1040 else if (lr_reg >= 0 &&
1041 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1042 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1043 /* stw Rx, NUM(r1) */
1044 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1045 /* stwu Rx, NUM(r1) */
1046 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1047 { /* where Rx == lr */
1048 fdata->lr_offset = offset;
1049 fdata->nosavedpc = 0;
1050 /* Invalidate lr_reg, but don't set it to -1.
1051 That would mean that it had never been set. */
1053 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1054 (op & 0xfc000000) == 0x90000000) /* stw */
1056 /* Does not update r1, so add displacement to lr_offset. */
1057 fdata->lr_offset += SIGNED_SHORT (op);
1062 else if (cr_reg >= 0 &&
1063 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1064 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1065 /* stw Rx, NUM(r1) */
1066 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1067 /* stwu Rx, NUM(r1) */
1068 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1069 { /* where Rx == cr */
1070 fdata->cr_offset = offset;
1071 /* Invalidate cr_reg, but don't set it to -1.
1072 That would mean that it had never been set. */
1074 if ((op & 0xfc000003) == 0xf8000000 ||
1075 (op & 0xfc000000) == 0x90000000)
1077 /* Does not update r1, so add displacement to cr_offset. */
1078 fdata->cr_offset += SIGNED_SHORT (op);
1083 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1085 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1086 prediction bits. If the LR has already been saved, we can
1090 else if (op == 0x48000005)
1096 else if (op == 0x48000004)
1101 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1102 in V.4 -mminimal-toc */
1103 (op & 0xffff0000) == 0x3bde0000)
1104 { /* addi 30,30,foo@l */
1108 else if ((op & 0xfc000001) == 0x48000001)
1112 fdata->frameless = 0;
1114 /* If the return address has already been saved, we can skip
1115 calls to blrl (for PIC). */
1116 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1119 /* Don't skip over the subroutine call if it is not within
1120 the first three instructions of the prologue and either
1121 we have no line table information or the line info tells
1122 us that the subroutine call is not part of the line
1123 associated with the prologue. */
1124 if ((pc - orig_pc) > 8)
1126 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1127 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1129 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1133 op = read_memory_integer (pc + 4, 4);
1135 /* At this point, make sure this is not a trampoline
1136 function (a function that simply calls another functions,
1137 and nothing else). If the next is not a nop, this branch
1138 was part of the function prologue. */
1140 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1141 break; /* don't skip over
1146 /* update stack pointer */
1147 else if ((op & 0xfc1f0000) == 0x94010000)
1148 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1149 fdata->frameless = 0;
1150 fdata->offset = SIGNED_SHORT (op);
1151 offset = fdata->offset;
1154 else if ((op & 0xfc1f016a) == 0x7c01016e)
1155 { /* stwux rX,r1,rY */
1156 /* no way to figure out what r1 is going to be */
1157 fdata->frameless = 0;
1158 offset = fdata->offset;
1161 else if ((op & 0xfc1f0003) == 0xf8010001)
1162 { /* stdu rX,NUM(r1) */
1163 fdata->frameless = 0;
1164 fdata->offset = SIGNED_SHORT (op & ~3UL);
1165 offset = fdata->offset;
1168 else if ((op & 0xfc1f016a) == 0x7c01016a)
1169 { /* stdux rX,r1,rY */
1170 /* no way to figure out what r1 is going to be */
1171 fdata->frameless = 0;
1172 offset = fdata->offset;
1175 else if ((op & 0xffff0000) == 0x38210000)
1176 { /* addi r1,r1,SIMM */
1177 fdata->frameless = 0;
1178 fdata->offset += SIGNED_SHORT (op);
1179 offset = fdata->offset;
1182 /* Load up minimal toc pointer. Do not treat an epilogue restore
1183 of r31 as a minimal TOC load. */
1184 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1185 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1187 && !minimal_toc_loaded)
1189 minimal_toc_loaded = 1;
1192 /* move parameters from argument registers to local variable
1195 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1196 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1197 (((op >> 21) & 31) <= 10) &&
1198 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1202 /* store parameters in stack */
1204 /* Move parameters from argument registers to temporary register. */
1205 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1209 /* Set up frame pointer */
1211 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1212 || op == 0x7c3f0b78)
1214 fdata->frameless = 0;
1216 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1219 /* Another way to set up the frame pointer. */
1221 else if ((op & 0xfc1fffff) == 0x38010000)
1222 { /* addi rX, r1, 0x0 */
1223 fdata->frameless = 0;
1225 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1226 + ((op & ~0x38010000) >> 21));
1229 /* AltiVec related instructions. */
1230 /* Store the vrsave register (spr 256) in another register for
1231 later manipulation, or load a register into the vrsave
1232 register. 2 instructions are used: mfvrsave and
1233 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1234 and mtspr SPR256, Rn. */
1235 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1236 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1237 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1239 vrsave_reg = GET_SRC_REG (op);
1242 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1246 /* Store the register where vrsave was saved to onto the stack:
1247 rS is the register where vrsave was stored in a previous
1249 /* 100100 sssss 00001 dddddddd dddddddd */
1250 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1252 if (vrsave_reg == GET_SRC_REG (op))
1254 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1259 /* Compute the new value of vrsave, by modifying the register
1260 where vrsave was saved to. */
1261 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1262 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1266 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1267 in a pair of insns to save the vector registers on the
1269 /* 001110 00000 00000 iiii iiii iiii iiii */
1270 /* 001110 01110 00000 iiii iiii iiii iiii */
1271 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1272 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1274 if ((op & 0xffff0000) == 0x38000000)
1275 r0_contains_arg = 0;
1277 vr_saved_offset = SIGNED_SHORT (op);
1279 /* This insn by itself is not part of the prologue, unless
1280 if part of the pair of insns mentioned above. So do not
1281 record this insn as part of the prologue yet. */
1282 prev_insn_was_prologue_insn = 0;
1284 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1285 /* 011111 sssss 11111 00000 00111001110 */
1286 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1288 if (pc == (li_found_pc + 4))
1290 vr_reg = GET_SRC_REG (op);
1291 /* If this is the first vector reg to be saved, or if
1292 it has a lower number than others previously seen,
1293 reupdate the frame info. */
1294 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1296 fdata->saved_vr = vr_reg;
1297 fdata->vr_offset = vr_saved_offset + offset;
1299 vr_saved_offset = -1;
1304 /* End AltiVec related instructions. */
1306 /* Start BookE related instructions. */
1307 /* Store gen register S at (r31+uimm).
1308 Any register less than r13 is volatile, so we don't care. */
1309 /* 000100 sssss 11111 iiiii 01100100001 */
1310 else if (arch_info->mach == bfd_mach_ppc_e500
1311 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1313 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1316 ev_reg = GET_SRC_REG (op);
1317 imm = (op >> 11) & 0x1f;
1318 ev_offset = imm * 8;
1319 /* If this is the first vector reg to be saved, or if
1320 it has a lower number than others previously seen,
1321 reupdate the frame info. */
1322 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1324 fdata->saved_ev = ev_reg;
1325 fdata->ev_offset = ev_offset + offset;
1330 /* Store gen register rS at (r1+rB). */
1331 /* 000100 sssss 00001 bbbbb 01100100000 */
1332 else if (arch_info->mach == bfd_mach_ppc_e500
1333 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1335 if (pc == (li_found_pc + 4))
1337 ev_reg = GET_SRC_REG (op);
1338 /* If this is the first vector reg to be saved, or if
1339 it has a lower number than others previously seen,
1340 reupdate the frame info. */
1341 /* We know the contents of rB from the previous instruction. */
1342 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1344 fdata->saved_ev = ev_reg;
1345 fdata->ev_offset = vr_saved_offset + offset;
1347 vr_saved_offset = -1;
1353 /* Store gen register r31 at (rA+uimm). */
1354 /* 000100 11111 aaaaa iiiii 01100100001 */
1355 else if (arch_info->mach == bfd_mach_ppc_e500
1356 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1358 /* Wwe know that the source register is 31 already, but
1359 it can't hurt to compute it. */
1360 ev_reg = GET_SRC_REG (op);
1361 ev_offset = ((op >> 11) & 0x1f) * 8;
1362 /* If this is the first vector reg to be saved, or if
1363 it has a lower number than others previously seen,
1364 reupdate the frame info. */
1365 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1367 fdata->saved_ev = ev_reg;
1368 fdata->ev_offset = ev_offset + offset;
1373 /* Store gen register S at (r31+r0).
1374 Store param on stack when offset from SP bigger than 4 bytes. */
1375 /* 000100 sssss 11111 00000 01100100000 */
1376 else if (arch_info->mach == bfd_mach_ppc_e500
1377 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1379 if (pc == (li_found_pc + 4))
1381 if ((op & 0x03e00000) >= 0x01a00000)
1383 ev_reg = GET_SRC_REG (op);
1384 /* If this is the first vector reg to be saved, or if
1385 it has a lower number than others previously seen,
1386 reupdate the frame info. */
1387 /* We know the contents of r0 from the previous
1389 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1391 fdata->saved_ev = ev_reg;
1392 fdata->ev_offset = vr_saved_offset + offset;
1396 vr_saved_offset = -1;
1401 /* End BookE related instructions. */
1405 /* Not a recognized prologue instruction.
1406 Handle optimizer code motions into the prologue by continuing
1407 the search if we have no valid frame yet or if the return
1408 address is not yet saved in the frame. */
1409 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1412 if (op == 0x4e800020 /* blr */
1413 || op == 0x4e800420) /* bctr */
1414 /* Do not scan past epilogue in frameless functions or
1417 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1418 /* Never skip branches. */
1421 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1422 /* Do not scan too many insns, scanning insns is expensive with
1426 /* Continue scanning. */
1427 prev_insn_was_prologue_insn = 0;
1433 /* I have problems with skipping over __main() that I need to address
1434 * sometime. Previously, I used to use misc_function_vector which
1435 * didn't work as well as I wanted to be. -MGO */
1437 /* If the first thing after skipping a prolog is a branch to a function,
1438 this might be a call to an initializer in main(), introduced by gcc2.
1439 We'd like to skip over it as well. Fortunately, xlc does some extra
1440 work before calling a function right after a prologue, thus we can
1441 single out such gcc2 behaviour. */
1444 if ((op & 0xfc000001) == 0x48000001)
1445 { /* bl foo, an initializer function? */
1446 op = read_memory_integer (pc + 4, 4);
1448 if (op == 0x4def7b82)
1449 { /* cror 0xf, 0xf, 0xf (nop) */
1451 /* Check and see if we are in main. If so, skip over this
1452 initializer function as well. */
1454 tmp = find_pc_misc_function (pc);
1456 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1462 fdata->offset = -fdata->offset;
1463 return last_prologue_pc;
1467 /*************************************************************************
1468 Support for creating pushing a dummy frame into the stack, and popping
1470 *************************************************************************/
1473 /* All the ABI's require 16 byte alignment. */
1475 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1477 return (addr & -16);
1480 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1481 the first eight words of the argument list (that might be less than
1482 eight parameters if some parameters occupy more than one word) are
1483 passed in r3..r10 registers. float and double parameters are
1484 passed in fpr's, in addition to that. Rest of the parameters if any
1485 are passed in user stack. There might be cases in which half of the
1486 parameter is copied into registers, the other half is pushed into
1489 Stack must be aligned on 64-bit boundaries when synthesizing
1492 If the function is returning a structure, then the return address is passed
1493 in r3, then the first 7 words of the parameters can be passed in registers,
1494 starting from r4. */
1497 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1498 struct regcache *regcache, CORE_ADDR bp_addr,
1499 int nargs, struct value **args, CORE_ADDR sp,
1500 int struct_return, CORE_ADDR struct_addr)
1502 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1505 int argno; /* current argument number */
1506 int argbytes; /* current argument byte */
1507 gdb_byte tmp_buffer[50];
1508 int f_argno = 0; /* current floating point argno */
1509 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1510 CORE_ADDR func_addr = find_function_addr (function, NULL);
1512 struct value *arg = 0;
1517 /* The calling convention this function implements assumes the
1518 processor has floating-point registers. We shouldn't be using it
1519 on PPC variants that lack them. */
1520 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1522 /* The first eight words of ther arguments are passed in registers.
1523 Copy them appropriately. */
1526 /* If the function is returning a `struct', then the first word
1527 (which will be passed in r3) is used for struct return address.
1528 In that case we should advance one word and start from r4
1529 register to copy parameters. */
1532 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1538 effectively indirect call... gcc does...
1540 return_val example( float, int);
1543 float in fp0, int in r3
1544 offset of stack on overflow 8/16
1545 for varargs, must go by type.
1547 float in r3&r4, int in r5
1548 offset of stack on overflow different
1550 return in r3 or f0. If no float, must study how gcc emulates floats;
1551 pay attention to arg promotion.
1552 User may have to cast\args to handle promotion correctly
1553 since gdb won't know if prototype supplied or not.
1556 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1558 int reg_size = register_size (current_gdbarch, ii + 3);
1561 type = check_typedef (value_type (arg));
1562 len = TYPE_LENGTH (type);
1564 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1567 /* Floating point arguments are passed in fpr's, as well as gpr's.
1568 There are 13 fpr's reserved for passing parameters. At this point
1569 there is no way we would run out of them. */
1571 gdb_assert (len <= 8);
1573 regcache_cooked_write (regcache,
1574 tdep->ppc_fp0_regnum + 1 + f_argno,
1575 value_contents (arg));
1582 /* Argument takes more than one register. */
1583 while (argbytes < len)
1585 gdb_byte word[MAX_REGISTER_SIZE];
1586 memset (word, 0, reg_size);
1588 ((char *) value_contents (arg)) + argbytes,
1589 (len - argbytes) > reg_size
1590 ? reg_size : len - argbytes);
1591 regcache_cooked_write (regcache,
1592 tdep->ppc_gp0_regnum + 3 + ii,
1594 ++ii, argbytes += reg_size;
1597 goto ran_out_of_registers_for_arguments;
1604 /* Argument can fit in one register. No problem. */
1605 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1606 gdb_byte word[MAX_REGISTER_SIZE];
1608 memset (word, 0, reg_size);
1609 memcpy (word, value_contents (arg), len);
1610 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1615 ran_out_of_registers_for_arguments:
1617 saved_sp = read_sp ();
1619 /* Location for 8 parameters are always reserved. */
1622 /* Another six words for back chain, TOC register, link register, etc. */
1625 /* Stack pointer must be quadword aligned. */
1628 /* If there are more arguments, allocate space for them in
1629 the stack, then push them starting from the ninth one. */
1631 if ((argno < nargs) || argbytes)
1637 space += ((len - argbytes + 3) & -4);
1643 for (; jj < nargs; ++jj)
1645 struct value *val = args[jj];
1646 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1649 /* Add location required for the rest of the parameters. */
1650 space = (space + 15) & -16;
1653 /* This is another instance we need to be concerned about
1654 securing our stack space. If we write anything underneath %sp
1655 (r1), we might conflict with the kernel who thinks he is free
1656 to use this area. So, update %sp first before doing anything
1659 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1661 /* If the last argument copied into the registers didn't fit there
1662 completely, push the rest of it into stack. */
1666 write_memory (sp + 24 + (ii * 4),
1667 value_contents (arg) + argbytes,
1670 ii += ((len - argbytes + 3) & -4) / 4;
1673 /* Push the rest of the arguments into stack. */
1674 for (; argno < nargs; ++argno)
1678 type = check_typedef (value_type (arg));
1679 len = TYPE_LENGTH (type);
1682 /* Float types should be passed in fpr's, as well as in the
1684 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1687 gdb_assert (len <= 8);
1689 regcache_cooked_write (regcache,
1690 tdep->ppc_fp0_regnum + 1 + f_argno,
1691 value_contents (arg));
1695 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1696 ii += ((len + 3) & -4) / 4;
1700 /* Set the stack pointer. According to the ABI, the SP is meant to
1701 be set _before_ the corresponding stack space is used. On AIX,
1702 this even applies when the target has been completely stopped!
1703 Not doing this can lead to conflicts with the kernel which thinks
1704 that it still has control over this not-yet-allocated stack
1706 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1708 /* Set back chain properly. */
1709 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1710 write_memory (sp, tmp_buffer, wordsize);
1712 /* Point the inferior function call's return address at the dummy's
1714 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1716 /* Set the TOC register, get the value from the objfile reader
1717 which, in turn, gets it from the VMAP table. */
1718 if (rs6000_find_toc_address_hook != NULL)
1720 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1721 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1724 target_store_registers (-1);
1728 static enum return_value_convention
1729 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
1730 struct regcache *regcache, gdb_byte *readbuf,
1731 const gdb_byte *writebuf)
1733 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1736 /* The calling convention this function implements assumes the
1737 processor has floating-point registers. We shouldn't be using it
1738 on PowerPC variants that lack them. */
1739 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1741 /* AltiVec extension: Functions that declare a vector data type as a
1742 return value place that return value in VR2. */
1743 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
1744 && TYPE_LENGTH (valtype) == 16)
1747 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
1749 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
1751 return RETURN_VALUE_REGISTER_CONVENTION;
1754 /* If the called subprogram returns an aggregate, there exists an
1755 implicit first argument, whose value is the address of a caller-
1756 allocated buffer into which the callee is assumed to store its
1757 return value. All explicit parameters are appropriately
1759 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1760 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1761 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1762 return RETURN_VALUE_STRUCT_CONVENTION;
1764 /* Scalar floating-point values are returned in FPR1 for float or
1765 double, and in FPR1:FPR2 for quadword precision. Fortran
1766 complex*8 and complex*16 are returned in FPR1:FPR2, and
1767 complex*32 is returned in FPR1:FPR4. */
1768 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1769 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
1771 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
1774 /* FIXME: kettenis/2007-01-01: Add support for quadword
1775 precision and complex. */
1779 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
1780 convert_typed_floating (regval, regtype, readbuf, valtype);
1784 convert_typed_floating (writebuf, valtype, regval, regtype);
1785 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
1788 return RETURN_VALUE_REGISTER_CONVENTION;
1791 /* Values of the types int, long, short, pointer, and char (length
1792 is less than or equal to four bytes), as well as bit values of
1793 lengths less than or equal to 32 bits, must be returned right
1794 justified in GPR3 with signed values sign extended and unsigned
1795 values zero extended, as necessary. */
1796 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
1802 /* For reading we don't have to worry about sign extension. */
1803 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1805 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
1809 /* For writing, use unpack_long since that should handle any
1810 required sign extension. */
1811 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1812 unpack_long (valtype, writebuf));
1815 return RETURN_VALUE_REGISTER_CONVENTION;
1818 /* Eight-byte non-floating-point scalar values must be returned in
1821 if (TYPE_LENGTH (valtype) == 8)
1823 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
1824 gdb_assert (tdep->wordsize == 4);
1830 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
1831 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
1833 memcpy (readbuf, regval, 8);
1837 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
1838 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
1842 return RETURN_VALUE_REGISTER_CONVENTION;
1845 return RETURN_VALUE_STRUCT_CONVENTION;
1848 /* Return whether handle_inferior_event() should proceed through code
1849 starting at PC in function NAME when stepping.
1851 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1852 handle memory references that are too distant to fit in instructions
1853 generated by the compiler. For example, if 'foo' in the following
1858 is greater than 32767, the linker might replace the lwz with a branch to
1859 somewhere in @FIX1 that does the load in 2 instructions and then branches
1860 back to where execution should continue.
1862 GDB should silently step over @FIX code, just like AIX dbx does.
1863 Unfortunately, the linker uses the "b" instruction for the
1864 branches, meaning that the link register doesn't get set.
1865 Therefore, GDB's usual step_over_function () mechanism won't work.
1867 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1868 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1872 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1874 return name && !strncmp (name, "@FIX", 4);
1877 /* Skip code that the user doesn't want to see when stepping:
1879 1. Indirect function calls use a piece of trampoline code to do context
1880 switching, i.e. to set the new TOC table. Skip such code if we are on
1881 its first instruction (as when we have single-stepped to here).
1883 2. Skip shared library trampoline code (which is different from
1884 indirect function call trampolines).
1886 3. Skip bigtoc fixup code.
1888 Result is desired PC to step until, or NULL if we are not in
1889 code that should be skipped. */
1892 rs6000_skip_trampoline_code (CORE_ADDR pc)
1894 unsigned int ii, op;
1896 CORE_ADDR solib_target_pc;
1897 struct minimal_symbol *msymbol;
1899 static unsigned trampoline_code[] =
1901 0x800b0000, /* l r0,0x0(r11) */
1902 0x90410014, /* st r2,0x14(r1) */
1903 0x7c0903a6, /* mtctr r0 */
1904 0x804b0004, /* l r2,0x4(r11) */
1905 0x816b0008, /* l r11,0x8(r11) */
1906 0x4e800420, /* bctr */
1907 0x4e800020, /* br */
1911 /* Check for bigtoc fixup code. */
1912 msymbol = lookup_minimal_symbol_by_pc (pc);
1914 && rs6000_in_solib_return_trampoline (pc,
1915 DEPRECATED_SYMBOL_NAME (msymbol)))
1917 /* Double-check that the third instruction from PC is relative "b". */
1918 op = read_memory_integer (pc + 8, 4);
1919 if ((op & 0xfc000003) == 0x48000000)
1921 /* Extract bits 6-29 as a signed 24-bit relative word address and
1922 add it to the containing PC. */
1923 rel = ((int)(op << 6) >> 6);
1924 return pc + 8 + rel;
1928 /* If pc is in a shared library trampoline, return its target. */
1929 solib_target_pc = find_solib_trampoline_target (pc);
1930 if (solib_target_pc)
1931 return solib_target_pc;
1933 for (ii = 0; trampoline_code[ii]; ++ii)
1935 op = read_memory_integer (pc + (ii * 4), 4);
1936 if (op != trampoline_code[ii])
1939 ii = read_register (11); /* r11 holds destination addr */
1940 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1944 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1945 isn't available with that word size, return 0. */
1948 regsize (const struct reg *reg, int wordsize)
1950 return wordsize == 8 ? reg->sz64 : reg->sz32;
1953 /* Return the name of register number N, or null if no such register exists
1954 in the current architecture. */
1957 rs6000_register_name (int n)
1959 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1960 const struct reg *reg = tdep->regs + n;
1962 if (!regsize (reg, tdep->wordsize))
1967 /* Return the GDB type object for the "standard" data type
1968 of data in register N. */
1970 static struct type *
1971 rs6000_register_type (struct gdbarch *gdbarch, int n)
1973 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1974 const struct reg *reg = tdep->regs + n;
1977 return builtin_type_double;
1980 int size = regsize (reg, tdep->wordsize);
1984 return builtin_type_int0;
1986 return builtin_type_uint32;
1988 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1989 return builtin_type_vec64;
1991 return builtin_type_uint64;
1994 return builtin_type_vec128;
1997 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
2003 /* Is REGNUM a member of REGGROUP? */
2005 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2006 struct reggroup *group)
2008 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2013 if (REGISTER_NAME (regnum) == NULL
2014 || *REGISTER_NAME (regnum) == '\0')
2016 if (group == all_reggroup)
2019 float_p = (regnum == tdep->ppc_fpscr_regnum
2020 || (regnum >= tdep->ppc_fp0_regnum
2021 && regnum < tdep->ppc_fp0_regnum + 32));
2022 if (group == float_reggroup)
2025 vector_p = ((tdep->ppc_vr0_regnum >= 0
2026 && regnum >= tdep->ppc_vr0_regnum
2027 && regnum < tdep->ppc_vr0_regnum + 32)
2028 || (tdep->ppc_ev0_regnum >= 0
2029 && regnum >= tdep->ppc_ev0_regnum
2030 && regnum < tdep->ppc_ev0_regnum + 32)
2031 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
2032 || regnum == tdep->ppc_vrsave_regnum
2033 || regnum == tdep->ppc_acc_regnum
2034 || regnum == tdep->ppc_spefscr_regnum);
2035 if (group == vector_reggroup)
2038 /* Note that PS aka MSR isn't included - it's a system register (and
2039 besides, due to GCC's CFI foobar you do not want to restore
2041 general_p = ((regnum >= tdep->ppc_gp0_regnum
2042 && regnum < tdep->ppc_gp0_regnum + 32)
2043 || regnum == tdep->ppc_toc_regnum
2044 || regnum == tdep->ppc_cr_regnum
2045 || regnum == tdep->ppc_lr_regnum
2046 || regnum == tdep->ppc_ctr_regnum
2047 || regnum == tdep->ppc_xer_regnum
2048 || regnum == PC_REGNUM);
2049 if (group == general_reggroup)
2052 if (group == save_reggroup || group == restore_reggroup)
2053 return general_p || vector_p || float_p;
2058 /* The register format for RS/6000 floating point registers is always
2059 double, we need a conversion if the memory format is float. */
2062 rs6000_convert_register_p (int regnum, struct type *type)
2064 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2067 && TYPE_CODE (type) == TYPE_CODE_FLT
2068 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2072 rs6000_register_to_value (struct frame_info *frame,
2077 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2078 gdb_byte from[MAX_REGISTER_SIZE];
2080 gdb_assert (reg->fpr);
2081 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2083 get_frame_register (frame, regnum, from);
2084 convert_typed_floating (from, builtin_type_double, to, type);
2088 rs6000_value_to_register (struct frame_info *frame,
2091 const gdb_byte *from)
2093 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2094 gdb_byte to[MAX_REGISTER_SIZE];
2096 gdb_assert (reg->fpr);
2097 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2099 convert_typed_floating (from, type, to, builtin_type_double);
2100 put_frame_register (frame, regnum, to);
2103 /* Move SPE vector register values between a 64-bit buffer and the two
2104 32-bit raw register halves in a regcache. This function handles
2105 both splitting a 64-bit value into two 32-bit halves, and joining
2106 two halves into a whole 64-bit value, depending on the function
2107 passed as the MOVE argument.
2109 EV_REG must be the number of an SPE evN vector register --- a
2110 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2113 Call MOVE once for each 32-bit half of that register, passing
2114 REGCACHE, the number of the raw register corresponding to that
2115 half, and the address of the appropriate half of BUFFER.
2117 For example, passing 'regcache_raw_read' as the MOVE function will
2118 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2119 'regcache_raw_supply' will supply the contents of BUFFER to the
2120 appropriate pair of raw registers in REGCACHE.
2122 You may need to cast away some 'const' qualifiers when passing
2123 MOVE, since this function can't tell at compile-time which of
2124 REGCACHE or BUFFER is acting as the source of the data. If C had
2125 co-variant type qualifiers, ... */
2127 e500_move_ev_register (void (*move) (struct regcache *regcache,
2128 int regnum, gdb_byte *buf),
2129 struct regcache *regcache, int ev_reg,
2132 struct gdbarch *arch = get_regcache_arch (regcache);
2133 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2135 gdb_byte *byte_buffer = buffer;
2137 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2138 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2140 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2142 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2144 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2145 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2149 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2150 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2155 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2156 int reg_nr, gdb_byte *buffer)
2158 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2159 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2161 gdb_assert (regcache_arch == gdbarch);
2163 if (tdep->ppc_ev0_regnum <= reg_nr
2164 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2165 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2167 internal_error (__FILE__, __LINE__,
2168 _("e500_pseudo_register_read: "
2169 "called on unexpected register '%s' (%d)"),
2170 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2174 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2175 int reg_nr, const gdb_byte *buffer)
2177 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2178 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2180 gdb_assert (regcache_arch == gdbarch);
2182 if (tdep->ppc_ev0_regnum <= reg_nr
2183 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2184 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2186 regcache, reg_nr, (gdb_byte *) buffer);
2188 internal_error (__FILE__, __LINE__,
2189 _("e500_pseudo_register_read: "
2190 "called on unexpected register '%s' (%d)"),
2191 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2194 /* The E500 needs a custom reggroup function: it has anonymous raw
2195 registers, and default_register_reggroup_p assumes that anonymous
2196 registers are not members of any reggroup. */
2198 e500_register_reggroup_p (struct gdbarch *gdbarch,
2200 struct reggroup *group)
2202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2204 /* The save and restore register groups need to include the
2205 upper-half registers, even though they're anonymous. */
2206 if ((group == save_reggroup
2207 || group == restore_reggroup)
2208 && (tdep->ppc_ev0_upper_regnum <= regnum
2209 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2212 /* In all other regards, the default reggroup definition is fine. */
2213 return default_register_reggroup_p (gdbarch, regnum, group);
2216 /* Convert a DBX STABS register number to a GDB register number. */
2218 rs6000_stab_reg_to_regnum (int num)
2220 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2222 if (0 <= num && num <= 31)
2223 return tdep->ppc_gp0_regnum + num;
2224 else if (32 <= num && num <= 63)
2225 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2226 specifies registers the architecture doesn't have? Our
2227 callers don't check the value we return. */
2228 return tdep->ppc_fp0_regnum + (num - 32);
2229 else if (77 <= num && num <= 108)
2230 return tdep->ppc_vr0_regnum + (num - 77);
2231 else if (1200 <= num && num < 1200 + 32)
2232 return tdep->ppc_ev0_regnum + (num - 1200);
2237 return tdep->ppc_mq_regnum;
2239 return tdep->ppc_lr_regnum;
2241 return tdep->ppc_ctr_regnum;
2243 return tdep->ppc_xer_regnum;
2245 return tdep->ppc_vrsave_regnum;
2247 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2249 return tdep->ppc_acc_regnum;
2251 return tdep->ppc_spefscr_regnum;
2258 /* Convert a Dwarf 2 register number to a GDB register number. */
2260 rs6000_dwarf2_reg_to_regnum (int num)
2262 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2264 if (0 <= num && num <= 31)
2265 return tdep->ppc_gp0_regnum + num;
2266 else if (32 <= num && num <= 63)
2267 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2268 specifies registers the architecture doesn't have? Our
2269 callers don't check the value we return. */
2270 return tdep->ppc_fp0_regnum + (num - 32);
2271 else if (1124 <= num && num < 1124 + 32)
2272 return tdep->ppc_vr0_regnum + (num - 1124);
2273 else if (1200 <= num && num < 1200 + 32)
2274 return tdep->ppc_ev0_regnum + (num - 1200);
2279 return tdep->ppc_cr_regnum;
2281 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2283 return tdep->ppc_acc_regnum;
2285 return tdep->ppc_mq_regnum;
2287 return tdep->ppc_xer_regnum;
2289 return tdep->ppc_lr_regnum;
2291 return tdep->ppc_ctr_regnum;
2293 return tdep->ppc_vrsave_regnum;
2295 return tdep->ppc_spefscr_regnum;
2301 /* Translate a .eh_frame register to DWARF register, or adjust a
2302 .debug_frame register. */
2305 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2307 /* GCC releases before 3.4 use GCC internal register numbering in
2308 .debug_frame (and .debug_info, et cetera). The numbering is
2309 different from the standard SysV numbering for everything except
2310 for GPRs and FPRs. We can not detect this problem in most cases
2311 - to get accurate debug info for variables living in lr, ctr, v0,
2312 et cetera, use a newer version of GCC. But we must detect
2313 one important case - lr is in column 65 in .debug_frame output,
2316 GCC 3.4, and the "hammer" branch, have a related problem. They
2317 record lr register saves in .debug_frame as 108, but still record
2318 the return column as 65. We fix that up too.
2320 We can do this because 65 is assigned to fpsr, and GCC never
2321 generates debug info referring to it. To add support for
2322 handwritten debug info that restores fpsr, we would need to add a
2323 producer version check to this. */
2332 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2333 internal register numbering; translate that to the standard DWARF2
2334 register numbering. */
2335 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2337 else if (68 <= num && num <= 75) /* cr0-cr8 */
2338 return num - 68 + 86;
2339 else if (77 <= num && num <= 108) /* vr0-vr31 */
2340 return num - 77 + 1124;
2352 case 109: /* vrsave */
2354 case 110: /* vscr */
2356 case 111: /* spe_acc */
2358 case 112: /* spefscr */
2365 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2367 Usually a function pointer's representation is simply the address
2368 of the function. On the RS/6000 however, a function pointer is
2369 represented by a pointer to an OPD entry. This OPD entry contains
2370 three words, the first word is the address of the function, the
2371 second word is the TOC pointer (r2), and the third word is the
2372 static chain value. Throughout GDB it is currently assumed that a
2373 function pointer contains the address of the function, which is not
2374 easy to fix. In addition, the conversion of a function address to
2375 a function pointer would require allocation of an OPD entry in the
2376 inferior's memory space, with all its drawbacks. To be able to
2377 call C++ virtual methods in the inferior (which are called via
2378 function pointers), find_function_addr uses this function to get the
2379 function address from a function pointer. */
2381 /* Return real function address if ADDR (a function pointer) is in the data
2382 space and is therefore a special function pointer. */
2385 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2387 struct target_ops *targ)
2389 struct obj_section *s;
2391 s = find_pc_section (addr);
2392 if (s && s->the_bfd_section->flags & SEC_CODE)
2395 /* ADDR is in the data space, so it's a special function pointer. */
2396 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2400 /* Handling the various POWER/PowerPC variants. */
2403 /* The arrays here called registers_MUMBLE hold information about available
2406 For each family of PPC variants, I've tried to isolate out the
2407 common registers and put them up front, so that as long as you get
2408 the general family right, GDB will correctly identify the registers
2409 common to that family. The common register sets are:
2411 For the 60x family: hid0 hid1 iabr dabr pir
2413 For the 505 and 860 family: eie eid nri
2415 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2416 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2419 Most of these register groups aren't anything formal. I arrived at
2420 them by looking at the registers that occurred in more than one
2423 Note: kevinb/2002-04-30: Support for the fpscr register was added
2424 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2425 for Power. For PowerPC, slot 70 was unused and was already in the
2426 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2427 slot 70 was being used for "mq", so the next available slot (71)
2428 was chosen. It would have been nice to be able to make the
2429 register numbers the same across processor cores, but this wasn't
2430 possible without either 1) renumbering some registers for some
2431 processors or 2) assigning fpscr to a really high slot that's
2432 larger than any current register number. Doing (1) is bad because
2433 existing stubs would break. Doing (2) is undesirable because it
2434 would introduce a really large gap between fpscr and the rest of
2435 the registers for most processors. */
2437 /* Convenience macros for populating register arrays. */
2439 /* Within another macro, convert S to a string. */
2443 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2444 and 64 bits on 64-bit systems. */
2445 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2447 /* Return a struct reg defining register NAME that's 32 bits on all
2449 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2451 /* Return a struct reg defining register NAME that's 64 bits on all
2453 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2455 /* Return a struct reg defining register NAME that's 128 bits on all
2457 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2459 /* Return a struct reg defining floating-point register NAME. */
2460 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2462 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2463 long on all systems. */
2464 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2466 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2467 systems and that doesn't exist on 64-bit systems. */
2468 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2470 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2471 systems and that doesn't exist on 32-bit systems. */
2472 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2474 /* Return a struct reg placeholder for a register that doesn't exist. */
2475 #define R0 { 0, 0, 0, 0, 0, -1 }
2477 /* Return a struct reg defining an anonymous raw register that's 32
2478 bits on all systems. */
2479 #define A4 { 0, 4, 4, 0, 0, -1 }
2481 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2482 32-bit systems and 64 bits on 64-bit systems. */
2483 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2485 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2487 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2489 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2490 all systems, and whose SPR number is NUMBER. */
2491 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2493 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2494 64-bit systems and that doesn't exist on 32-bit systems. */
2495 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2497 /* UISA registers common across all architectures, including POWER. */
2499 #define COMMON_UISA_REGS \
2500 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2501 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2502 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2503 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2504 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2505 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2506 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2507 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2508 /* 64 */ R(pc), R(ps)
2510 /* UISA-level SPRs for PowerPC. */
2511 #define PPC_UISA_SPRS \
2512 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2514 /* UISA-level SPRs for PowerPC without floating point support. */
2515 #define PPC_UISA_NOFP_SPRS \
2516 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2518 /* Segment registers, for PowerPC. */
2519 #define PPC_SEGMENT_REGS \
2520 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2521 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2522 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2523 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2525 /* OEA SPRs for PowerPC. */
2526 #define PPC_OEA_SPRS \
2528 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2529 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2530 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2531 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2532 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2533 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2534 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2535 /* 116 */ S4(dec), S(dabr), S4(ear)
2537 /* AltiVec registers. */
2538 #define PPC_ALTIVEC_REGS \
2539 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2540 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2541 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2542 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2543 /*151*/R4(vscr), R4(vrsave)
2546 /* On machines supporting the SPE APU, the general-purpose registers
2547 are 64 bits long. There are SIMD vector instructions to treat them
2548 as pairs of floats, but the rest of the instruction set treats them
2549 as 32-bit registers, and only operates on their lower halves.
2551 In the GDB regcache, we treat their high and low halves as separate
2552 registers. The low halves we present as the general-purpose
2553 registers, and then we have pseudo-registers that stitch together
2554 the upper and lower halves and present them as pseudo-registers. */
2556 /* SPE GPR lower halves --- raw registers. */
2557 #define PPC_SPE_GP_REGS \
2558 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2559 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2560 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2561 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2563 /* SPE GPR upper halves --- anonymous raw registers. */
2564 #define PPC_SPE_UPPER_GP_REGS \
2565 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2566 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2567 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2568 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2570 /* SPE GPR vector registers --- pseudo registers based on underlying
2571 gprs and the anonymous upper half raw registers. */
2572 #define PPC_EV_PSEUDO_REGS \
2573 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2574 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2575 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2576 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2578 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2579 user-level SPR's. */
2580 static const struct reg registers_power[] =
2583 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2587 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2588 view of the PowerPC. */
2589 static const struct reg registers_powerpc[] =
2598 Some notes about the "tcr" special-purpose register:
2599 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2600 403's programmable interval timer, fixed interval timer, and
2602 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2603 watchdog timer, and nothing else.
2605 Some of the fields are similar between the two, but they're not
2606 compatible with each other. Since the two variants have different
2607 registers, with different numbers, but the same name, we can't
2608 splice the register name to get the SPR number. */
2609 static const struct reg registers_403[] =
2615 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2616 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2617 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2618 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2619 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2620 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2623 /* IBM PowerPC 403GC.
2624 See the comments about 'tcr' for the 403, above. */
2625 static const struct reg registers_403GC[] =
2631 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2632 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2633 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2634 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2635 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2636 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2637 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2638 /* 147 */ S(tbhu), S(tblu)
2641 /* Motorola PowerPC 505. */
2642 static const struct reg registers_505[] =
2648 /* 119 */ S(eie), S(eid), S(nri)
2651 /* Motorola PowerPC 860 or 850. */
2652 static const struct reg registers_860[] =
2658 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2659 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2660 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2661 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2662 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2663 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2664 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2665 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2666 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2667 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2668 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2669 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2672 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2673 for reading and writing RTCU and RTCL. However, how one reads and writes a
2674 register is the stub's problem. */
2675 static const struct reg registers_601[] =
2681 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2682 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2685 /* Motorola PowerPC 602.
2686 See the notes under the 403 about 'tcr'. */
2687 static const struct reg registers_602[] =
2693 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2694 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2695 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2698 /* Motorola/IBM PowerPC 603 or 603e. */
2699 static const struct reg registers_603[] =
2705 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2706 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2707 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2710 /* Motorola PowerPC 604 or 604e. */
2711 static const struct reg registers_604[] =
2717 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2718 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2719 /* 127 */ S(sia), S(sda)
2722 /* Motorola/IBM PowerPC 750 or 740. */
2723 static const struct reg registers_750[] =
2729 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2730 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2731 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2732 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2733 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2734 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2738 /* Motorola PowerPC 7400. */
2739 static const struct reg registers_7400[] =
2741 /* gpr0-gpr31, fpr0-fpr31 */
2743 /* cr, lr, ctr, xer, fpscr */
2748 /* vr0-vr31, vrsave, vscr */
2750 /* FIXME? Add more registers? */
2753 /* Motorola e500. */
2754 static const struct reg registers_e500[] =
2756 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2757 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2758 /* 64 .. 65 */ R(pc), R(ps),
2759 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2760 /* 71 .. 72 */ R8(acc), S4(spefscr),
2761 /* NOTE: Add new registers here the end of the raw register
2762 list and just before the first pseudo register. */
2763 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2766 /* Information about a particular processor variant. */
2770 /* Name of this variant. */
2773 /* English description of the variant. */
2776 /* bfd_arch_info.arch corresponding to variant. */
2777 enum bfd_architecture arch;
2779 /* bfd_arch_info.mach corresponding to variant. */
2782 /* Number of real registers. */
2785 /* Number of pseudo registers. */
2788 /* Number of total registers (the sum of nregs and npregs). */
2791 /* Table of register names; registers[R] is the name of the register
2793 const struct reg *regs;
2796 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2799 num_registers (const struct reg *reg_list, int num_tot_regs)
2804 for (i = 0; i < num_tot_regs; i++)
2805 if (!reg_list[i].pseudo)
2812 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2817 for (i = 0; i < num_tot_regs; i++)
2818 if (reg_list[i].pseudo)
2824 /* Information in this table comes from the following web sites:
2825 IBM: http://www.chips.ibm.com:80/products/embedded/
2826 Motorola: http://www.mot.com/SPS/PowerPC/
2828 I'm sure I've got some of the variant descriptions not quite right.
2829 Please report any inaccuracies you find to GDB's maintainer.
2831 If you add entries to this table, please be sure to allow the new
2832 value as an argument to the --with-cpu flag, in configure.in. */
2834 static struct variant variants[] =
2837 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2838 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2840 {"power", "POWER user-level", bfd_arch_rs6000,
2841 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2843 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2844 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2846 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2847 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2849 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2850 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2852 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2853 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2855 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2856 604, -1, -1, tot_num_registers (registers_604),
2858 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2859 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2861 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2862 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2864 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2865 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2867 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2868 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2870 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2871 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2873 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2874 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2878 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2879 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2881 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2882 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2884 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2885 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2887 {"a35", "PowerPC A35", bfd_arch_powerpc,
2888 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2890 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2891 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2893 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2894 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2897 /* FIXME: I haven't checked the register sets of the following. */
2898 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2899 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2901 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2902 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2904 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2905 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2908 {0, 0, 0, 0, 0, 0, 0, 0}
2911 /* Initialize the number of registers and pseudo registers in each variant. */
2914 init_variants (void)
2918 for (v = variants; v->name; v++)
2921 v->nregs = num_registers (v->regs, v->num_tot_regs);
2922 if (v->npregs == -1)
2923 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2927 /* Return the variant corresponding to architecture ARCH and machine number
2928 MACH. If no such variant exists, return null. */
2930 static const struct variant *
2931 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2933 const struct variant *v;
2935 for (v = variants; v->name; v++)
2936 if (arch == v->arch && mach == v->mach)
2943 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2945 if (!info->disassembler_options)
2946 info->disassembler_options = "any";
2948 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2949 return print_insn_big_powerpc (memaddr, info);
2951 return print_insn_little_powerpc (memaddr, info);
2955 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2957 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2960 static struct frame_id
2961 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2963 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2965 frame_pc_unwind (next_frame));
2968 struct rs6000_frame_cache
2971 CORE_ADDR initial_sp;
2972 struct trad_frame_saved_reg *saved_regs;
2975 static struct rs6000_frame_cache *
2976 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2978 struct rs6000_frame_cache *cache;
2979 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2980 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2981 struct rs6000_framedata fdata;
2982 int wordsize = tdep->wordsize;
2985 if ((*this_cache) != NULL)
2986 return (*this_cache);
2987 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2988 (*this_cache) = cache;
2989 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2991 func = frame_func_unwind (next_frame, NORMAL_FRAME);
2992 pc = frame_pc_unwind (next_frame);
2993 skip_prologue (func, pc, &fdata);
2995 /* Figure out the parent's stack pointer. */
2997 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2998 address of the current frame. Things might be easier if the
2999 ->frame pointed to the outer-most address of the frame. In
3000 the mean time, the address of the prev frame is used as the
3001 base address of this frame. */
3002 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3004 /* If the function appears to be frameless, check a couple of likely
3005 indicators that we have simply failed to find the frame setup.
3006 Two common cases of this are missing symbols (i.e.
3007 frame_func_unwind returns the wrong address or 0), and assembly
3008 stubs which have a fast exit path but set up a frame on the slow
3011 If the LR appears to return to this function, then presume that
3012 we have an ABI compliant frame that we failed to find. */
3013 if (fdata.frameless && fdata.lr_offset == 0)
3018 saved_lr = frame_unwind_register_unsigned (next_frame,
3019 tdep->ppc_lr_regnum);
3020 if (func == 0 && saved_lr == pc)
3024 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3025 if (func == saved_func)
3031 fdata.frameless = 0;
3032 fdata.lr_offset = tdep->lr_frame_offset;
3036 if (!fdata.frameless)
3037 /* Frameless really means stackless. */
3038 cache->base = read_memory_addr (cache->base, wordsize);
3040 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
3042 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3043 All fpr's from saved_fpr to fp31 are saved. */
3045 if (fdata.saved_fpr >= 0)
3048 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3050 /* If skip_prologue says floating-point registers were saved,
3051 but the current architecture has no floating-point registers,
3052 then that's strange. But we have no indices to even record
3053 the addresses under, so we just ignore it. */
3054 if (ppc_floating_point_unit_p (gdbarch))
3055 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3057 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3062 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3063 All gpr's from saved_gpr to gpr31 are saved. */
3065 if (fdata.saved_gpr >= 0)
3068 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3069 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3071 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3072 gpr_addr += wordsize;
3076 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3077 All vr's from saved_vr to vr31 are saved. */
3078 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3080 if (fdata.saved_vr >= 0)
3083 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3084 for (i = fdata.saved_vr; i < 32; i++)
3086 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3087 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3092 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3093 All vr's from saved_ev to ev31 are saved. ????? */
3094 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3096 if (fdata.saved_ev >= 0)
3099 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3100 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3102 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3103 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3104 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3109 /* If != 0, fdata.cr_offset is the offset from the frame that
3111 if (fdata.cr_offset != 0)
3112 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3114 /* If != 0, fdata.lr_offset is the offset from the frame that
3116 if (fdata.lr_offset != 0)
3117 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3118 /* The PC is found in the link register. */
3119 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
3121 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3122 holds the VRSAVE. */
3123 if (fdata.vrsave_offset != 0)
3124 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3126 if (fdata.alloca_reg < 0)
3127 /* If no alloca register used, then fi->frame is the value of the
3128 %sp for this frame, and it is good enough. */
3129 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3131 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3138 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3139 struct frame_id *this_id)
3141 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3143 (*this_id) = frame_id_build (info->base,
3144 frame_func_unwind (next_frame, NORMAL_FRAME));
3148 rs6000_frame_prev_register (struct frame_info *next_frame,
3150 int regnum, int *optimizedp,
3151 enum lval_type *lvalp, CORE_ADDR *addrp,
3152 int *realnump, gdb_byte *valuep)
3154 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3156 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3157 optimizedp, lvalp, addrp, realnump, valuep);
3160 static const struct frame_unwind rs6000_frame_unwind =
3163 rs6000_frame_this_id,
3164 rs6000_frame_prev_register
3167 static const struct frame_unwind *
3168 rs6000_frame_sniffer (struct frame_info *next_frame)
3170 return &rs6000_frame_unwind;
3176 rs6000_frame_base_address (struct frame_info *next_frame,
3179 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3181 return info->initial_sp;
3184 static const struct frame_base rs6000_frame_base = {
3185 &rs6000_frame_unwind,
3186 rs6000_frame_base_address,
3187 rs6000_frame_base_address,
3188 rs6000_frame_base_address
3191 static const struct frame_base *
3192 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3194 return &rs6000_frame_base;
3197 /* Initialize the current architecture based on INFO. If possible, re-use an
3198 architecture from ARCHES, which is a list of architectures already created
3199 during this debugging session.
3201 Called e.g. at program startup, when reading a core file, and when reading
3204 static struct gdbarch *
3205 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3207 struct gdbarch *gdbarch;
3208 struct gdbarch_tdep *tdep;
3209 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3211 const struct variant *v;
3212 enum bfd_architecture arch;
3218 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3219 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3221 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3222 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3224 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3226 /* Check word size. If INFO is from a binary file, infer it from
3227 that, else choose a likely default. */
3228 if (from_xcoff_exec)
3230 if (bfd_xcoff_is_xcoff64 (info.abfd))
3235 else if (from_elf_exec)
3237 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3244 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3245 wordsize = info.bfd_arch_info->bits_per_word /
3246 info.bfd_arch_info->bits_per_byte;
3251 /* Find a candidate among extant architectures. */
3252 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3254 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3256 /* Word size in the various PowerPC bfd_arch_info structs isn't
3257 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3258 separate word size check. */
3259 tdep = gdbarch_tdep (arches->gdbarch);
3260 if (tdep && tdep->wordsize == wordsize)
3261 return arches->gdbarch;
3264 /* None found, create a new architecture from INFO, whose bfd_arch_info
3265 validity depends on the source:
3266 - executable useless
3267 - rs6000_host_arch() good
3269 - "set arch" trust blindly
3270 - GDB startup useless but harmless */
3272 if (!from_xcoff_exec)
3274 arch = info.bfd_arch_info->arch;
3275 mach = info.bfd_arch_info->mach;
3279 arch = bfd_arch_powerpc;
3280 bfd_default_set_arch_mach (&abfd, arch, 0);
3281 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3282 mach = info.bfd_arch_info->mach;
3284 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3285 tdep->wordsize = wordsize;
3287 /* For e500 executables, the apuinfo section is of help here. Such
3288 section contains the identifier and revision number of each
3289 Application-specific Processing Unit that is present on the
3290 chip. The content of the section is determined by the assembler
3291 which looks at each instruction and determines which unit (and
3292 which version of it) can execute it. In our case we just look for
3293 the existance of the section. */
3297 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3300 arch = info.bfd_arch_info->arch;
3301 mach = bfd_mach_ppc_e500;
3302 bfd_default_set_arch_mach (&abfd, arch, mach);
3303 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3307 gdbarch = gdbarch_alloc (&info, tdep);
3309 /* Initialize the number of real and pseudo registers in each variant. */
3312 /* Choose variant. */
3313 v = find_variant_by_arch (arch, mach);
3317 tdep->regs = v->regs;
3319 tdep->ppc_gp0_regnum = 0;
3320 tdep->ppc_toc_regnum = 2;
3321 tdep->ppc_ps_regnum = 65;
3322 tdep->ppc_cr_regnum = 66;
3323 tdep->ppc_lr_regnum = 67;
3324 tdep->ppc_ctr_regnum = 68;
3325 tdep->ppc_xer_regnum = 69;
3326 if (v->mach == bfd_mach_ppc_601)
3327 tdep->ppc_mq_regnum = 124;
3328 else if (arch == bfd_arch_rs6000)
3329 tdep->ppc_mq_regnum = 70;
3331 tdep->ppc_mq_regnum = -1;
3332 tdep->ppc_fp0_regnum = 32;
3333 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3334 tdep->ppc_sr0_regnum = 71;
3335 tdep->ppc_vr0_regnum = -1;
3336 tdep->ppc_vrsave_regnum = -1;
3337 tdep->ppc_ev0_upper_regnum = -1;
3338 tdep->ppc_ev0_regnum = -1;
3339 tdep->ppc_ev31_regnum = -1;
3340 tdep->ppc_acc_regnum = -1;
3341 tdep->ppc_spefscr_regnum = -1;
3343 set_gdbarch_pc_regnum (gdbarch, 64);
3344 set_gdbarch_sp_regnum (gdbarch, 1);
3345 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3346 set_gdbarch_fp0_regnum (gdbarch, 32);
3347 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3348 if (sysv_abi && wordsize == 8)
3349 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3350 else if (sysv_abi && wordsize == 4)
3351 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3353 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3355 /* Set lr_frame_offset. */
3357 tdep->lr_frame_offset = 16;
3359 tdep->lr_frame_offset = 4;
3361 tdep->lr_frame_offset = 8;
3363 if (v->arch == bfd_arch_rs6000)
3364 tdep->ppc_sr0_regnum = -1;
3365 else if (v->arch == bfd_arch_powerpc)
3369 tdep->ppc_sr0_regnum = -1;
3370 tdep->ppc_vr0_regnum = 71;
3371 tdep->ppc_vrsave_regnum = 104;
3373 case bfd_mach_ppc_7400:
3374 tdep->ppc_vr0_regnum = 119;
3375 tdep->ppc_vrsave_regnum = 152;
3377 case bfd_mach_ppc_e500:
3378 tdep->ppc_toc_regnum = -1;
3379 tdep->ppc_ev0_upper_regnum = 32;
3380 tdep->ppc_ev0_regnum = 73;
3381 tdep->ppc_ev31_regnum = 104;
3382 tdep->ppc_acc_regnum = 71;
3383 tdep->ppc_spefscr_regnum = 72;
3384 tdep->ppc_fp0_regnum = -1;
3385 tdep->ppc_fpscr_regnum = -1;
3386 tdep->ppc_sr0_regnum = -1;
3387 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3388 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3389 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3392 case bfd_mach_ppc64:
3393 case bfd_mach_ppc_620:
3394 case bfd_mach_ppc_630:
3395 case bfd_mach_ppc_a35:
3396 case bfd_mach_ppc_rs64ii:
3397 case bfd_mach_ppc_rs64iii:
3398 /* These processor's register sets don't have segment registers. */
3399 tdep->ppc_sr0_regnum = -1;
3403 internal_error (__FILE__, __LINE__,
3404 _("rs6000_gdbarch_init: "
3405 "received unexpected BFD 'arch' value"));
3407 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3409 /* Sanity check on registers. */
3410 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3412 /* Select instruction printer. */
3413 if (arch == bfd_arch_rs6000)
3414 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3416 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3418 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3420 set_gdbarch_num_regs (gdbarch, v->nregs);
3421 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3422 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3423 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3424 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3426 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3427 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3428 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3429 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3430 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3431 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3432 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3434 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3436 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3437 set_gdbarch_char_signed (gdbarch, 0);
3439 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3440 if (sysv_abi && wordsize == 8)
3442 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3443 else if (!sysv_abi && wordsize == 4)
3444 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3445 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3446 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3448 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3450 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3451 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3452 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3454 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3455 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3457 if (sysv_abi && wordsize == 4)
3458 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3459 else if (sysv_abi && wordsize == 8)
3460 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3462 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3464 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3465 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3467 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3468 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3470 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3471 for the descriptor and ".FN" for the entry-point -- a user
3472 specifying "break FN" will unexpectedly end up with a breakpoint
3473 on the descriptor and not the function. This architecture method
3474 transforms any breakpoints on descriptors into breakpoints on the
3475 corresponding entry point. */
3476 if (sysv_abi && wordsize == 8)
3477 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3479 /* Not sure on this. FIXMEmgo */
3480 set_gdbarch_frame_args_skip (gdbarch, 8);
3484 /* Handle RS/6000 function pointers (which are really function
3486 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3487 rs6000_convert_from_func_ptr_addr);
3490 /* Helpers for function argument information. */
3491 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3494 set_gdbarch_in_solib_return_trampoline
3495 (gdbarch, rs6000_in_solib_return_trampoline);
3496 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3498 /* Hook in the DWARF CFI frame unwinder. */
3499 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3500 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3502 /* Hook in ABI-specific overrides, if they have been registered. */
3503 gdbarch_init_osabi (info, gdbarch);
3507 case GDB_OSABI_LINUX:
3508 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3509 have altivec registers. If not, ptrace will fail the first time it's
3510 called to access one and will not be called again. This wart will
3511 be removed when Daniel Jacobowitz's proposal for autodetecting target
3512 registers is implemented. */
3513 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3515 tdep->ppc_vr0_regnum = 71;
3516 tdep->ppc_vrsave_regnum = 104;
3519 case GDB_OSABI_NETBSD_AOUT:
3520 case GDB_OSABI_NETBSD_ELF:
3521 case GDB_OSABI_UNKNOWN:
3522 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3523 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3524 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3525 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3528 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3530 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3531 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3532 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3533 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3536 init_sim_regno_table (gdbarch);
3542 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3544 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3549 /* FIXME: Dump gdbarch_tdep. */
3552 /* Initialization code. */
3554 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3557 _initialize_rs6000_tdep (void)
3559 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3560 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);