1 ------------------------------------------------------------------------------
2 -- Copyright (C) 2011, Kenichi Kurimoto
4 -- This program is free software; you can redistribute it and/or modify
5 -- it under the terms of the GNU General Public License as published by
6 -- the Free Software Foundation; either version 2 of the License, or
7 -- (at your option) any later version.
9 -- This program is distributed in the hope that it will be useful,
10 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- GNU General Public License for more details.
14 -- You should have received a copy of the GNU General Public License
15 -- along with this program; if not, write to the Free Software
16 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -----------------------------------------------------------------------------
20 -- Author: Kenichi Kurimoto
21 -- Description: AMBA slave interface and huffman decoder for jpeg decode
22 ------------------------------------------------------------------------------
25 use ieee.std_logic_1164.all;
26 use ieee.numeric_std.all;
31 use grlib.devices.all;
34 use techmap.gencomp.all;
41 memtech : integer := DEFMEMTECH;
42 shindex : integer := 0;
44 hmask : integer := 16#fff#;
46 pindex : integer := 0;
48 pmask : integer := 16#fff#;
49 mhindex : integer := 0;
50 chprot : integer := 3);
54 ahbsi : in ahb_slv_in_type;
55 ahbso : out ahb_slv_out_type;
56 apbi : in apb_slv_in_type;
57 apbo : out apb_slv_out_type;
58 kready : in std_logic;
59 kstrobe : out std_logic;
60 kdata : out std_logic_vector(11 downto 0);
61 kaddress : out std_logic_vector(5 downto 0);
62 jpg_setting : out jpg_set_type;
63 error : in std_logic_vector(2 downto 0);
64 startgen : out std_logic;
65 kstrobeq : out std_logic;
66 kdataq : out std_logic_vector(7 downto 0);
67 kaddq : out std_logic_vector(7 downto 0);
68 krddataq : in std_logic_vector(7 downto 0);
73 architecture rtl of huff is
75 constant shconfig : ahb_config_type := (
76 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
77 4 => ahb_membar(haddr, '0', '0', hmask),
80 constant pconfig : apb_config_type := (
81 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
82 1 => apb_iobar(paddr, pmask));
84 constant fdepth : integer := 512;
86 constant const_4b4 : std_logic_vector(3 downto 0) := "0100";
87 constant const_4b5 : std_logic_vector(3 downto 0) := "0101";
88 constant const_4b6 : std_logic_vector(3 downto 0) := "0110";
89 constant const_6b8 : std_logic_vector(5 downto 0) := "001000";
90 constant const_u6b24 : UNSIGNED(5 downto 0) := "011000";
92 function sign_ex(data, bitnum : std_logic_vector) return std_logic_vector is
93 variable outb : std_logic_vector(11 downto 0);
94 variable minusjudge : std_logic;
95 variable tmp : integer;
98 if(bitnum = "0001")then
100 outb := "111111111111";
102 outb := "000000000001";
104 elsif(bitnum = "0010")then
105 if(data(1) = '0')then
106 tmp := to_integer(signed('1' & data(1 downto 0))) + 1;
107 outb := std_logic_vector(to_signed(tmp, 12));
109 tmp := to_integer(signed('0' & data(1 downto 0)));
110 outb := std_logic_vector(to_signed(tmp, 12));
112 elsif(bitnum = "0011")then
113 if(data(2) = '0')then
114 tmp := to_integer(signed('1' & data(2 downto 0))) + 1;
115 outb := std_logic_vector(to_signed(tmp, 12));
117 tmp := to_integer(signed('0' & data(2 downto 0)));
118 outb := std_logic_vector(to_signed(tmp, 12));
120 elsif(bitnum = "0100")then
121 if(data(3) = '0')then
122 tmp := to_integer(signed('1' & data(3 downto 0))) + 1;
123 outb := std_logic_vector(to_signed(tmp, 12));
125 tmp := to_integer(signed('0' & data(3 downto 0)));
126 outb := std_logic_vector(to_signed(tmp, 12));
128 elsif(bitnum = "0101")then
129 if(data(4) = '0')then
130 tmp := to_integer(signed('1' & data(4 downto 0))) + 1;
131 outb := std_logic_vector(to_signed(tmp, 12));
133 tmp := to_integer(signed('0' & data(4 downto 0)));
134 outb := std_logic_vector(to_signed(tmp, 12));
136 elsif(bitnum = "0110")then
137 if(data(5) = '0')then
138 tmp := to_integer(signed('1' & data(5 downto 0))) + 1;
139 outb := std_logic_vector(to_signed(tmp, 12));
141 tmp := to_integer(signed('0' & data(5 downto 0)));
142 outb := std_logic_vector(to_signed(tmp, 12));
144 elsif(bitnum = "0111")then
145 if(data(6) = '0')then
146 tmp := to_integer(signed('1' & data(6 downto 0))) + 1;
147 outb := std_logic_vector(to_signed(tmp, 12));
149 tmp := to_integer(signed('0' & data(6 downto 0)));
150 outb := std_logic_vector(to_signed(tmp, 12));
152 elsif(bitnum = "1000")then
153 if(data(7) = '0')then
154 tmp := to_integer(signed('1' & data(7 downto 0))) + 1;
155 outb := std_logic_vector(to_signed(tmp, 12));
157 tmp := to_integer(signed('0' & data(7 downto 0)));
158 outb := std_logic_vector(to_signed(tmp, 12));
160 elsif(bitnum = "1001")then
161 if(data(8) = '0')then
162 tmp := to_integer(signed('1' & data(8 downto 0))) + 1;
163 outb := std_logic_vector(to_signed(tmp, 12));
165 tmp := to_integer(signed('0' & data(8 downto 0)));
166 outb := std_logic_vector(to_signed(tmp, 12));
168 elsif(bitnum = "1010")then
169 if(data(9) = '0')then
170 tmp := to_integer(signed('1' & data(9 downto 0))) + 1;
171 outb := std_logic_vector(to_signed(tmp, 12));
173 tmp := to_integer(signed('0' & data(9 downto 0)));
174 outb := std_logic_vector(to_signed(tmp, 12));
176 elsif(bitnum = "1011")then
177 if(data(10) = '0')then
178 tmp := to_integer(signed('1' & data(10 downto 0))) + 1;
179 outb := std_logic_vector(to_signed(tmp, 12));
181 tmp := to_integer(signed('0' & data(10 downto 0)));
182 outb := std_logic_vector(to_signed(tmp, 12));
184 -- elsif(bitnum = "1100")then
185 -- if(data(11) = '0)then
186 -- tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
187 -- outb := std_logic_vector(to_signed(tmp, 12));
189 -- tmp := to_integer(signed('0' & data(11 downto 0)));
190 -- outb := std_logic_vector(to_signed(tmp, 12));
192 -- elsif(bitnum ="0000")then
193 -- outb := (others => '0');
195 -- report "sign extention over flow" severity note;
196 outb := (others => '0');
202 type fstate_type is (memwait, bytefetch, ffmemwait, ffcheck, markermode);
203 type dstate_type is (symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby);
205 type ahbs_reg is record
210 getcache : std_logic;
211 rdacache : std_logic;
212 rddcache : std_logic;
215 getoffset : std_logic;
216 rdoffset : std_logic;
219 hreadyff : std_logic;
221 haddkeep : std_logic_vector(15 downto 0);
224 type apbs_reg is record
226 xmcumax : std_logic_vector(5 downto 0);
227 ymcumax : std_logic_vector(4 downto 0);
228 incaddy : std_logic_vector(15 downto 0);
229 incaddmcux : std_logic_vector(15 downto 0);
230 incaddmcuy : std_logic_vector(10 downto 0);
231 fbstartadd : std_logic_vector(31 downto 0);
232 through_bit : std_logic;
233 hardonly : std_logic;
236 type control_reg is record
237 fetch_state : fstate_type;
238 dec_state : dstate_type;
241 fifo_rp : std_logic_vector(8 downto 0);
242 fifo_wp : std_logic_vector(8 downto 0);
243 counter : std_logic_vector(1 downto 0);
244 fetch_reg : std_logic_vector(31 downto 0);
245 marker_reg : std_logic_vector(7 downto 0);
246 valuebit : std_logic_vector(5 downto 0);
247 byteselect : std_logic_vector(1 downto 0);
248 reqbit_keep : std_logic_vector(3 downto 0);
249 runlength_keep : std_logic_vector(3 downto 0);
250 valbit_keep : std_logic_vector(3 downto 0);
252 serial_counter : std_logic_vector(4 downto 0);
253 idcounter : std_logic_vector(3 downto 0);
254 memaddcnt : std_logic_vector(5 downto 0);
255 lastdc0 : std_logic_vector(11 downto 0);
256 lastdc1 : std_logic_vector(11 downto 0);
257 lastdc2 : std_logic_vector(11 downto 0);
258 byte3keep : std_logic_vector(23 downto 0);
260 capture : std_logic_vector(1 downto 0);
261 skipcnt : std_logic_vector(15 downto 0);
264 signal r, rin : control_reg;
265 signal read_en_fifo, write_en_fifo : std_logic;
266 signal read_pointer_fifo : std_logic_vector(8 downto 0);
267 signal write_pointer_fifo : std_logic_vector(8 downto 0);
268 signal data_out_fifo : std_logic_vector(31 downto 0);
269 signal data_in_fifo : std_logic_vector(31 downto 0);
271 signal dccacheadd : std_logic_vector(9 downto 0);
272 signal dccachedin : std_logic_vector(7 downto 0);
273 signal dccachedout : std_logic_vector(7 downto 0);
274 signal dccacheen,dccachewr : std_logic;
275 signal accacheadd : std_logic_vector(9 downto 0);
276 signal accachedin : std_logic_vector(11 downto 0);
277 signal accachedout : std_logic_vector(11 downto 0);
278 signal accacheen,accachewr : std_logic;
279 signal sermaxadd : std_logic_vector(6 downto 0);
280 signal sermaxdin : std_logic_vector(16 downto 0);
281 signal sermaxdout : std_logic_vector(16 downto 0);
282 signal sermaxen,sermaxwr : std_logic;
283 signal seroffadd : std_logic_vector(6 downto 0);
284 signal seroffdin : std_logic_vector(16 downto 0);
285 signal seroffdout : std_logic_vector(16 downto 0);
286 signal seroffen,seroffwr : std_logic;
287 signal servaladd : std_logic_vector(9 downto 0);
288 signal servaldin : std_logic_vector(7 downto 0);
289 signal servaldout : std_logic_vector(7 downto 0);
290 signal servalen,servalwr : std_logic;
292 signal debug_shiftnum : std_logic_vector(4 downto 0);
293 signal debug_sign_exin : std_logic_vector(10 downto 0);
294 signal debug_serialin : std_logic_vector(16 downto 0);
295 signal debug_vcache_symbit : std_logic_vector(4 downto 0);
296 signal debug_vcache_runlength : std_logic_vector(3 downto 0);
297 signal debug_vcache_valbit : std_logic_vector(3 downto 0);
298 signal debug_va : std_logic;
299 signal debug_fifoready : std_logic;
302 ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
303 port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
304 clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
305 huffdccache : syncram generic map(tech => memtech, abits => 10, dbits => 8)
306 port map( clk, dccacheadd, dccachedin, dccachedout, dccacheen, dccachewr);
307 huffaccache : syncram generic map(tech => memtech, abits => 10, dbits => 12)
308 port map( clk, accacheadd, accachedin, accachedout, accacheen, accachewr);
309 serialmax : syncram generic map(tech => memtech, abits => 7, dbits => 17)
310 port map( clk, sermaxadd, sermaxdin, sermaxdout, sermaxen, sermaxwr);
311 serialoffset : syncram generic map(tech => memtech, abits => 7, dbits => 17)
312 port map( clk, seroffadd, seroffdin, seroffdout, seroffen, seroffwr);
313 serialval : syncram generic map(tech => memtech, abits => 10, dbits => 8)
314 port map( clk, servaladd, servaldin, servaldout, servalen, servalwr);
317 comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedout, sermaxdout, seroffdout, servaldout, kready, error, krddataq)
318 variable v : control_reg;
319 variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
320 variable vsready : std_logic;
321 variable write_point : integer;
322 variable read_point : integer;
323 variable num_ele : integer;
324 variable apbwrite : std_logic;
325 variable vprdata : std_logic_vector(31 downto 0);
326 variable vhrdata : std_logic_vector(31 downto 0);
327 variable vwriting :std_logic;
328 variable vreading : std_logic;
329 variable vdccacheadd : std_logic_vector(9 downto 0);
330 variable vdccachewr : std_logic;
331 variable vaccacheadd : std_logic_vector(9 downto 0);
332 variable vaccachewr : std_logic;
333 variable vsermaxadd : std_logic_vector(6 downto 0);
334 variable vsermaxwr : std_logic;
335 variable vseroffadd : std_logic_vector(6 downto 0);
336 variable vseroffwr : std_logic;
337 variable vservaladd : std_logic_vector(9 downto 0);
338 variable vservalwr : std_logic;
340 variable vbytedata : std_logic_vector(7 downto 0);
341 variable vinsertdata : std_logic_vector(7 downto 0);
342 variable vbyte0, vbyte1, vbyte2, vbyte3 : std_logic_vector(7 downto 0);
343 variable vfetching : std_logic;
345 variable vcache_symbit : std_logic_vector(4 downto 0);
346 variable vcache_runlength : std_logic_vector(3 downto 0);
347 variable vcache_valbit : std_logic_vector(3 downto 0);
349 variable vint_plusv : integer;
350 variable vint_minusv : integer;
352 variable vserial_symbit : std_logic_vector(4 downto 0);
353 variable vserial_runlength : std_logic_vector(3 downto 0);
354 variable vserial_valbit : std_logic_vector(3 downto 0);
355 variable vserial_tmpin : std_logic_vector(16 downto 0);
356 variable vserial_mask : std_logic_vector(16 downto 0);
357 variable vserial_judge : std_logic;
358 variable vserial_tmpadd : std_logic_vector(16 downto 0);
360 variable vintshift : integer;
361 variable vshiftnum : std_logic_vector(4 downto 0);
362 variable vint_valuebit : integer;
363 variable vint_valbkp : integer;
364 variable vint_sercnt : integer;
365 variable vshiftout : std_logic_vector(15 downto 0);
366 variable vtmpshiftout : std_logic_vector(31 downto 0);
367 variable va : std_logic;
368 variable vid : std_logic;
369 variable vcompid : std_logic_vector(1 downto 0);
370 variable vkstrobe : std_logic;
371 variable vkdata : std_logic_vector(11 downto 0);
372 variable vint_csymbit : integer;
373 variable vint_reqbitkp : integer;
374 variable vint_cvalbit : integer;
375 variable vint_sersym : integer;
376 variable vint_serval : integer;
378 variable vkaddq : std_logic_vector(7 downto 0);
379 variable vkrdq : std_logic;
380 variable vgetbyte : std_logic;
381 variable vstartgen : std_logic;
385 virq := (others => '0');
386 vdccachewr := '0'; vdccacheadd := (others => '0');
387 vaccachewr := '0'; vaccacheadd := (others => '0');
388 vsermaxwr := '0'; vsermaxadd := (others => '0');
389 vseroffwr := '0'; vseroffadd := (others => '0');
390 vservalwr := '0'; vservaladd := (others => '0');
391 vkaddq := (others => '0'); vkrdq := '0';
392 vserial_judge := '0';
393 vkstrobe := '0'; vstartgen := '0';
396 apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
397 vprdata := (others => '0');
398 case apbi.paddr(5 downto 2) is
400 if apbwrite = '1' then
401 v.preg.fbstartadd := apbi.pwdata(31 downto 0);
403 vprdata := r.preg.fbstartadd(31 downto 0);
405 if apbwrite = '1' then
406 v.preg.sampf := apbi.pwdata(22);
407 v.preg.ymcumax := apbi.pwdata(21 downto 17);
408 v.preg.xmcumax := apbi.pwdata(16 downto 11);
409 v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
411 vprdata := "000000000" & r.preg.sampf & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
413 if apbwrite = '1' then
414 v.preg.incaddy := apbi.pwdata(31 downto 16);
415 v.preg.incaddmcux := apbi.pwdata(15 downto 0);
417 vprdata := r.preg.incaddy & r.preg.incaddmcux;
419 if apbwrite = '1' then
420 if apbi.pwdata(31) = '1' then
423 v.preg.through_bit := apbi.pwdata(15);
424 v.preg.hardonly := apbi.pwdata(14);
425 v.marker_reg := apbi.pwdata(23 downto 16);
427 vprdata := "00000000" & r.marker_reg & r.preg.through_bit & r.preg.hardonly &"00000000000000" ;
431 if(r.hreg.getcache = '1' or r.hreg.hreadyff = '0')then
432 if (r.hreg.haddkeep(15) = '1') then
434 vdccacheadd := r.hreg.haddkeep(11 downto 2);
437 vaccacheadd := r.hreg.haddkeep(11 downto 2);
440 vdccacheadd := ahbsi.haddr(11 downto 2);
441 vaccacheadd := ahbsi.haddr(11 downto 2);
443 if(r.hreg.getq = '1' or r.hreg.hreadyff = '0')then
444 vkaddq := r.hreg.haddkeep(9 downto 2);
446 vkaddq := ahbsi.haddr(9 downto 2);
449 if(r.hreg.getmax = '1' or r.hreg.hreadyff = '0')then
451 vsermaxadd := r.hreg.haddkeep(8 downto 2);
453 vsermaxadd := ahbsi.haddr(8 downto 2);
455 if(r.hreg.getoffset = '1' or r.hreg.hreadyff = '0')then
457 vseroffadd := r.hreg.haddkeep(8 downto 2);
459 vseroffadd := ahbsi.haddr(8 downto 2);
461 if(r.hreg.getval = '1' or r.hreg.hreadyff = '0')then
463 vservaladd := r.hreg.haddkeep(11 downto 2);
465 vservaladd := ahbsi.haddr(11 downto 2);
468 if(ahbsi.hready = '1' ) then
469 v.hreg.getscan := '0';
470 v.hreg.rdscan := '0';
473 v.hreg.getcache := '0';
474 v.hreg.rdacache := '0';
475 v.hreg.rddcache := '0';
476 v.hreg.getmax := '0';
478 v.hreg.getoffset := '0';
479 v.hreg.rdoffset := '0';
480 v.hreg.getval := '0';
483 v.hreg.hselff := ahbsi.hsel(shindex) and ahbsi.htrans(1);
484 vwriting := ahbsi.hwrite and v.hreg.hselff;
485 vreading := (not ahbsi.hwrite) and v.hreg.hselff;
486 if(ahbsi.haddr(19 downto 8) = "000000000000")then
487 if(vwriting = '1')then
488 v.hreg.getscan := '1';
489 elsif(vreading = '1')then
490 v.hreg.rdscan := '1';
493 if(ahbsi.haddr(15 downto 12) = "1100" )then
494 if(vwriting = '1')then
496 elsif(vreading = '1')then
500 if(ahbsi.haddr(15 downto 12) = "0100" or ahbsi.haddr(15 downto 12) = "0101")then
501 if(vwriting = '1')then
502 v.hreg.getcache := '1';
503 elsif(vreading = '1')then
504 v.hreg.rdacache := '1';
507 if(ahbsi.haddr(15 downto 12) = "1000" or ahbsi.haddr(15 downto 12) = "1001")then
508 if(vwriting = '1')then
509 v.hreg.getcache := '1';
510 elsif(vreading = '1')then
511 v.hreg.rddcache := '1';
514 if(ahbsi.haddr(15 downto 10) = "000001")then
515 if(vwriting = '1')then
516 v.hreg.getmax := '1';
517 elsif(vreading = '1')then
521 if(ahbsi.haddr(15 downto 10) = "000010")then
522 if(vwriting = '1')then
523 v.hreg.getoffset := '1';
524 elsif(vreading = '1')then
525 v.hreg.rdoffset := '1';
528 if(ahbsi.haddr(15 downto 13) = "001")then
529 if(vwriting = '1')then
530 v.hreg.getval := '1';
531 elsif(vreading = '1')then
535 v.hreg.haddkeep := ahbsi.haddr(15 downto 0);
538 if( v.hreg.getscan = '1' or v.hreg.getq = '1' or v.hreg.getcache = '1'
539 or v.hreg.getmax = '1' or v.hreg.getoffset = '1' or v.hreg.getval = '1')then
540 v.hreg.hreadyff := not(v.hreg.hselff and not ahbsi.hwrite);
541 v.hreg.getscan := v.hreg.getscan and v.hreg.hreadyff;
542 v.hreg.getq := v.hreg.getq and v.hreg.hreadyff;
543 v.hreg.getcache := v.hreg.getcache and v.hreg.hreadyff;
544 v.hreg.getmax := v.hreg.getmax and v.hreg.hreadyff;
545 v.hreg.getoffset := v.hreg.getoffset and v.hreg.hreadyff;
546 v.hreg.getval := v.hreg.getval and v.hreg.hreadyff;
549 -- FIFO # of element calculation
550 write_point := to_integer(unsigned(r.fifo_wp));
551 read_point := to_integer(unsigned(r.fifo_rp));
552 if (write_point >= read_point) then
553 num_ele := write_point - read_point;
555 num_ele := fdepth - read_point + write_point;
557 if num_ele > fdepth/2 then
562 debug_fifoready <= vsready;
564 vhrdata := vsready & "0000000000000000000000000000000";
565 if(r.hreg.rdscan = '1')then
566 vhrdata := data_out_fifo;
567 elsif(r.hreg.rdq ='1')then
568 vhrdata := "000000000000000000000000" &krddataq;
569 elsif(r.hreg.rdacache = '1')then
570 vhrdata := "00000000000000000000" & accachedout;
571 elsif(r.hreg.rddcache = '1')then
572 vhrdata := "000000000000000000000000" & dccachedout;
573 elsif(r.hreg.rdmax = '1')then
574 vhrdata := "000000000000000" & sermaxdout;
575 elsif(r.hreg.rdoffset = '1')then
576 vhrdata := "000000000000000" & seroffdout;
577 elsif(r.hreg.rdval = '1')then
578 vhrdata := "000000000000000000000000" & servaldout;
582 if r.hreg.getscan = '1' then
583 write_point := write_point + 1;
584 if write_point = fdepth then
588 v.fifo_wp := std_logic_vector(to_unsigned(write_point,9));
591 if((r.fetch_state = bytefetch and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)
592 or (r.fetch_state = ffcheck and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)) then
593 read_point := read_point + 1;
594 if read_point = fdepth then
597 v.byte3keep(23 downto 0) := data_out_fifo(23 downto 0);
599 v.fifo_rp := std_logic_vector(to_unsigned(read_point,9));
601 -- byte select from FIFO output
602 if(r.byteselect = "00") then
603 vbytedata := data_out_fifo(31 downto 24);
604 elsif(r.byteselect = "01") then
605 vbytedata := r.byte3keep(23 downto 16);
606 elsif(r.byteselect = "10") then
607 vbytedata := r.byte3keep(15 downto 8);
609 vbytedata := r.byte3keep(7 downto 0);
613 if((r.fetch_state = bytefetch and unsigned(r.valuebit) <= const_u6b24 )
614 or (r.fetch_state = ffcheck and unsigned(r.valuebit) <= const_u6b24))then
615 v.byteselect := v.byteselect + 1;
620 if(r.fetch_state = ffcheck) then
621 vinsertdata := "11111111";
623 vinsertdata := vbytedata;
626 -- byte fetching to 32bit fetch_register
627 if( (r.fetch_state = bytefetch and vbytedata /= "11111111" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0' )
628 or (r.fetch_state = ffcheck and vbytedata = "00000000" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0')) then
634 if(vfetching = '1') then
635 vbyte0 := vinsertdata;
636 vbyte1 := r.fetch_reg(7 downto 0);
637 vbyte2 := r.fetch_reg(15 downto 8);
638 vbyte3 := r.fetch_reg(23 downto 16);
640 vbyte0 := r.fetch_reg(7 downto 0);
641 vbyte1 := r.fetch_reg(15 downto 8);
642 vbyte2 := r.fetch_reg(23 downto 16);
643 vbyte3 := r.fetch_reg(31 downto 24);
645 v.fetch_reg := vbyte3 & vbyte2 & vbyte1 & vbyte0;
648 if(r.fetch_state = ffcheck and vbytedata /= "00000000" and r.preg.through_bit = '0') then
649 v.marker_reg := vbytedata;
651 if(r.marker_reg /= "00000000")then
655 -- Through bit & skip counter calculation
656 -- This part is for "motion"-JPEG".
657 -- It's not beautiful implementation, but.....
658 if(r.fetch_state = ffcheck and r.preg.through_bit = '1' and vbytedata = "11011010")then
662 if(r.capture = "10")then
663 v.skipcnt(15 downto 8) := vbytedata;
665 if(r.capture = "01")then
666 v.skipcnt(7 downto 0) := vbytedata;
668 if(r.cntdown = '1' and vgetbyte = '1')then
669 if(r.capture = "10")then
672 if(r.capture = "01")then
675 if(r.capture = "00")then
676 v.skipcnt := r.skipcnt - 1;
678 if(r.skipcnt = "0000000000000011")then
679 v.preg.through_bit := '0';
681 v.skipcnt := (others => '0');
685 -- State machine transition (fetch part)
686 case r.fetch_state is
688 if (num_ele /= 0 and unsigned(r.valuebit) <= const_u6b24) then
689 v.fetch_state := bytefetch;
692 if(r.byteselect = "11" and unsigned(r.valuebit) <= const_u6b24 and num_ele = 0 and vbytedata /= "11111111") then
693 v.fetch_state := memwait;
694 elsif( vbytedata = "11111111" and r.byteselect = "11" and num_ele = 0 and unsigned(r.valuebit) <= const_u6b24) then
695 v.fetch_state := ffmemwait;
696 elsif( vbytedata = "11111111" and unsigned(r.valuebit) <= const_u6b24 and (r.byteselect /= "11" or (r.byteselect = "11" and num_ele /= 0))) then
697 v.fetch_state := ffcheck;
700 if(num_ele /= 0) then
701 v.fetch_state := ffcheck;
704 if( (vbytedata = "00000000" and unsigned(r.valuebit) <=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0))
705 or (r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0) )) then
706 v.fetch_state := bytefetch;
707 elsif( (vbytedata = "00000000" and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect = "11" and num_ele = 0))
708 or( r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and r.byteselect = "11" and num_ele = 0 )) then
709 v.fetch_state := memwait;
710 elsif ( vbytedata /= "00000000") then
711 v.fetch_state := markermode;
714 if(r.marker_reg = "00000000" and (r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))) then
715 v.fetch_state := bytefetch;
716 elsif(r.marker_reg = "00000000" and (r.byteselect = "11" and num_ele =0)) then
717 v.fetch_state := memwait;
719 if(r.preg.hardonly = '1' and r.marker_reg = x"D9")then
720 if(r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))then
721 v.marker_reg := "00000000";
722 v.preg.through_bit := '1';
723 elsif(r.byteselect = "11" and num_ele =0)then
724 v.marker_reg := "00000000";
725 v.preg.through_bit := '1';
731 -- cache, serial mem output
732 if(r.dcac = '1') then
733 vcache_symbit := "0" & dccachedout(7 downto 4);
734 vcache_valbit := dccachedout(3 downto 0);
735 vcache_runlength := "0000";
737 vcache_symbit := "0" & accachedout(11 downto 8);
738 vcache_runlength := accachedout(7 downto 4);
739 vcache_valbit := accachedout(3 downto 0);
741 vserial_symbit := r.serial_counter - "00010";
742 vserial_runlength := servaldout(7 downto 4);
743 vserial_valbit := servaldout(3 downto 0);
745 -- valuebit calculation
746 if(vfetching = '1') then
751 if(r.dec_state = symcheck) then
752 if(unsigned(r.reqbit_keep) >= unsigned(vcache_symbit) )then
753 vint_minusv := to_integer(unsigned(vcache_symbit));
757 elsif(r.dec_state = serialfinish) then
758 vint_minusv := to_integer(unsigned(vserial_symbit));
759 elsif(r.dec_state = valout) then
760 vint_minusv := to_integer(unsigned(r.valbit_keep));
765 v.valuebit := std_logic_vector(to_unsigned((to_integer(unsigned(r.valuebit)) + vint_plusv - vint_minusv), 6));
767 -- Padding bit for Markers
768 if(r.fetch_state = markermode or r.preg.through_bit = '1') then
769 if((r.valuebit = "000001" and r.fetch_reg(0) = '1')
770 or (r.valuebit = "000010" and r.fetch_reg(1 downto 0) = "11")
771 or (r.valuebit = "000011" and r.fetch_reg(2 downto 0) = "111")
772 or (r.valuebit = "000100" and r.fetch_reg(3 downto 0) = "1111")
773 or (r.valuebit = "000101" and r.fetch_reg(4 downto 0) = "11111")
774 or (r.valuebit = "000110" and r.fetch_reg(5 downto 0) = "111111")
775 or (r.valuebit = "000111" and r.fetch_reg(6 downto 0) = "1111111")) then
776 v.valuebit := "000000";
779 if(r.dec_state = symreq)then
780 if(r.valuebit >= const_6b8)then
781 v.reqbit_keep := "1000";
783 v.reqbit_keep := r.valuebit(3 downto 0);
787 -- runlength_keep valbit_keep register calculation
788 if(r.dec_state = serialfinish)then
789 v.runlength_keep := vserial_runlength;
790 v.valbit_keep := vserial_valbit;
791 elsif(r.dec_state = symcheck)then
792 v.runlength_keep := vcache_runlength;
793 v.valbit_keep := vcache_valbit;
796 -- shiftnum calculation
797 vint_valuebit := to_integer(unsigned(r.valuebit));
798 vint_valbkp := to_integer(unsigned(r.valbit_keep));
799 vint_sercnt := to_integer(unsigned(r.serial_counter));
802 if(r.dec_state = symreq)then
803 if(vint_valuebit >= 8)then
804 vintshift := vint_valuebit - 8;
808 elsif(r.dec_state = valout)then
809 vintshift := vint_valuebit - vint_valbkp;
810 elsif(r.dec_state = serialcheck)then
811 vintshift := 1 + vint_valuebit - vint_sercnt;
812 elsif(r.dec_state = serialwait)then
813 vintshift := 1 + vint_valuebit - vint_sercnt;
815 vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
817 -- shifter instantiation
818 debug_shiftnum <= vshiftnum;
819 vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
820 vshiftout := vtmpshiftout(15 downto 0);
822 -- write memory address generation
823 if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
829 debug_vcache_symbit <= vcache_symbit;
830 debug_vcache_runlength <= vcache_runlength;
831 debug_vcache_valbit <= vcache_valbit;
833 -- if((va = '1' or r.dec_state = serialfinish) and r.memaddcnt = "111111")then
835 v.memaddcnt := "000000";
836 elsif((va = '1' and vcache_runlength = "0000" and vcache_valbit = "0000")
837 or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
838 v.memaddcnt := "111111";
840 v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
841 elsif(r.dec_state = serialfinish)then
842 v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
845 -- id, dcac calculation
846 if(r.dec_state = valout and r.memaddcnt = "000000")then
848 elsif(r.dec_state = valout and r.memaddcnt = "111111") then
852 if(r.dec_state = valout and r.memaddcnt = "111111") then
853 v.idcounter := r.idcounter + '1';
854 if(r.preg.sampf = '0')then
855 if(v.idcounter = "0110")then
856 v.idcounter := "0000";
859 if(v.idcounter = "1000")then
860 v.idcounter := "0000";
864 if(r.preg.sampf = '0')then
865 if(r.idcounter < const_4b4 )then
868 elsif(r.idcounter < const_4b5)then
876 if(r.idcounter < const_4b4)then
879 elsif(r.idcounter < const_4b6)then
889 if(r.dec_state = symreq)then
891 if(vint_valuebit >7)then
892 vdccacheadd := vid & '0' & vshiftout(7 downto 0);
893 elsif(vint_valuebit = 7)then
894 vdccacheadd := vid & "10" & vshiftout(6 downto 0);
895 elsif(vint_valuebit = 6)then
896 vdccacheadd := vid & "110" & vshiftout(5 downto 0);
897 elsif(vint_valuebit = 5)then
898 vdccacheadd := vid & "1110" & vshiftout(4 downto 0);
899 elsif(vint_valuebit = 4)then
900 vdccacheadd := vid & "11110" & vshiftout(3 downto 0);
901 elsif(vint_valuebit = 3)then
902 vdccacheadd := vid & "111110" & vshiftout(2 downto 0);
903 elsif(vint_valuebit = 2)then
904 vdccacheadd := vid & "1111110" & vshiftout(1 downto 0);
905 elsif(vint_valuebit = 1)then
906 vdccacheadd := vid & "11111110" & vshiftout(0);
910 if(vint_valuebit >7)then
911 vaccacheadd := vid & '0' & vshiftout(7 downto 0);
912 elsif(vint_valuebit = 7)then
913 vaccacheadd := vid & "10" & vshiftout(6 downto 0);
914 elsif(vint_valuebit = 6)then
915 vaccacheadd := vid & "110" & vshiftout(5 downto 0);
916 elsif(vint_valuebit = 5)then
917 vaccacheadd := vid & "1110" & vshiftout(4 downto 0);
918 elsif(vint_valuebit = 4)then
919 vaccacheadd := vid & "11110" & vshiftout(3 downto 0);
920 elsif(vint_valuebit = 3)then
921 vaccacheadd := vid & "111110" & vshiftout(2 downto 0);
922 elsif(vint_valuebit = 2)then
923 vaccacheadd := vid & "1111110" & vshiftout(1 downto 0);
924 elsif(vint_valuebit = 1)then
925 vaccacheadd := vid & "11111110" & vshiftout(0);
932 vserial_mask := "00000000000000000";
933 if(r.serial_counter = "01001")then
934 vserial_mask := "00000000011111111";
935 elsif(r.serial_counter = "01010")then
936 vserial_mask := "00000000111111111";
937 elsif(r.serial_counter = "01011")then
938 vserial_mask := "00000001111111111";
939 elsif(r.serial_counter = "01100")then
940 vserial_mask := "00000011111111111";
941 elsif(r.serial_counter = "01101")then
942 vserial_mask := "00000111111111111";
943 elsif(r.serial_counter = "01110")then
944 vserial_mask := "00001111111111111";
945 elsif(r.serial_counter = "01111")then
946 vserial_mask := "00011111111111111";
947 elsif(r.serial_counter = "10000")then
948 vserial_mask := "00111111111111111";
949 elsif(r.serial_counter = "10001")then
950 vserial_mask := "01111111111111111";
952 vserial_tmpin := ('0' & vshiftout) and vserial_mask;
953 debug_serialin <= vserial_tmpin;
954 if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
955 vsermaxadd := r.dcac & vid & r.serial_counter;
958 if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
959 vseroffadd := r.dcac & vid & r.serial_counter;
962 if(signed(vserial_tmpin) <= to_01(signed(sermaxdout)))then
963 vserial_judge := '1';
965 vserial_tmpadd := std_logic_vector(signed(vserial_tmpin) + signed(seroffdout));
966 if(r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
967 vservaladd := r.dcac & vid & vserial_tmpadd(7 downto 0);
969 if(r.dec_state = serialwait or r.dec_state = serialcheck or r.dec_state = serialfinish)then
973 if(r.dec_state = symreq)then
974 v.serial_counter := "01001";
975 elsif((r.dec_state = symcheck and vint_valuebit > 8)
976 or (r.dec_state = serialcheck and to_integer(unsigned(r.serial_counter))<= vint_valuebit)
977 or (r.dec_state = serialwait and to_integer(unsigned(r.serial_counter))<= vint_valuebit ))
978 or (r.dec_state = serialcheck and vserial_judge = '1')then
979 v.serial_counter := r.serial_counter + 1;
982 -- Sign extention & zigzag memory access
983 debug_sign_exin <= vshiftout(10 downto 0);
984 vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
985 if(r.dec_state = valout and r.dcac = '1')then
986 if(vcompid = "00")then
987 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc0));
989 elsif(vcompid = "01")then
990 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc1));
993 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc2));
997 if(r.dec_state = valout)then
1003 if(vstartgen = '1' or r.marker_reg = x"D9")then
1004 v.lastdc0 := (others => '0');
1005 v.lastdc1 := (others => '0');
1006 v.lastdc2 := (others => '0');
1009 -- Decord part state-machine
1010 -- state = symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby
1011 vint_csymbit := 0; vint_reqbitkp := 0; vint_cvalbit := 0;
1012 vint_sersym := 0; vint_serval := 0;
1014 if notx(vcache_symbit) then
1015 vint_csymbit := to_integer(unsigned(vcache_symbit));
1017 if notx(r.reqbit_keep) then
1018 vint_reqbitkp := to_integer(unsigned(r.reqbit_keep));
1020 if notx(vcache_valbit) then
1021 vint_cvalbit := to_integer(unsigned(vcache_valbit));
1023 if notx(vserial_symbit) then
1024 vint_sersym := to_integer(unsigned(vserial_symbit));
1026 if notx(vserial_valbit) then
1027 vint_serval := to_integer(unsigned(vserial_valbit));
1032 if(kready = '1' and r.valuebit /= "000000")then
1033 v.dec_state := symreq;
1036 if(r.valuebit = "000000")then
1037 v.dec_state := symreq;
1039 v.dec_state := symcheck;
1042 if(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit <= vint_valuebit )then
1043 v.dec_state := valout;
1044 elsif(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit > vint_valuebit )then
1045 v.dec_state := symokvalng;
1046 elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit >= 9)then
1047 v.dec_state := serialcheck;
1048 elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit < 9)then
1049 v.dec_state := serialwait;
1050 elsif(vint_reqbitkp < 8 and (vint_csymbit = 0 or vint_csymbit > vint_reqbitkp))then
1051 v.dec_state := symng;
1054 if(vint_reqbitkp = vint_valuebit)then
1055 v.dec_state := symng;
1057 v.dec_state := symreq;
1060 if(r.memaddcnt = "111111")then
1061 v.dec_state := standby;
1063 v.dec_state := symreq;
1066 if(vint_valbkp <= vint_valuebit)then
1067 v.dec_state := valout;
1069 v.dec_state := symokvalng;
1072 if(vint_sercnt > vint_valuebit) then
1073 v.dec_state := serialwait;
1075 v.dec_state := serialcheck;
1078 if(vserial_judge = '1')then
1079 v.dec_state := serialfinish;
1080 elsif(vint_sercnt > vint_valuebit)then
1081 v.dec_state := serialwait;
1083 v.dec_state := serialcheck;
1085 when serialfinish =>
1086 if(vint_valuebit < vint_sersym + vint_serval)then
1087 v.dec_state := symokvalng;
1089 v.dec_state := valout;
1096 v.hreg.getscan := '0';
1097 v.hreg.rdscan := '0';
1100 v.hreg.getcache := '0';
1101 v.hreg.rdacache := '0';
1102 v.hreg.rddcache := '0';
1103 v.hreg.haddkeep := (others => '0');
1104 v.hreg.getmax := '0';
1105 v.hreg.rdmax := '0';
1106 v.hreg.getoffset := '0';
1107 v.hreg.rdoffset := '0';
1108 v.hreg.getval := '0';
1109 v.hreg.rdval := '0';
1110 v.preg.sampf := '0';
1111 v.preg.xmcumax := (others => '0');
1112 v.preg.ymcumax := (others => '0');
1113 v.preg.incaddy := (others => '0');
1114 v.preg.incaddmcux := (others => '0');
1115 v.preg.incaddmcuy := (others => '0');
1116 v.preg.fbstartadd := (others => '0');
1117 v.preg.through_bit := '0';
1118 v.fetch_state := memwait;
1119 v.dec_state := standby;
1120 v.fifo_rp := (others => '0');
1121 v.fifo_wp := (others => '0');
1122 v.counter := (others => '0');
1123 v.fetch_reg := (others => '0');
1124 v.marker_reg := (others => '0');
1125 v.valuebit := (others => '0');
1126 v.byteselect := (others => '0');
1127 v.reqbit_keep := (others => '0');
1128 v.runlength_keep := (others => '0');
1129 v.valbit_keep := (others => '0');
1131 v.serial_counter := (others => '0');
1132 v.idcounter := (others => '0');
1133 v.memaddcnt := (others => '0');
1134 v.lastdc0 := (others => '0');
1135 v.lastdc1 := (others => '0');
1136 v.lastdc2 := (others => '0');
1137 v.byte3keep := (others => '0');
1140 v.skipcnt := (others => '0');
1145 write_en_fifo <= r.hreg.getscan;
1146 write_pointer_fifo <= r.fifo_wp;
1147 data_in_fifo <= ahbsi.hwdata;
1148 read_en_fifo <= '1';
1149 read_pointer_fifo <= r.fifo_rp;
1151 dccachedin <= ahbsi.hwdata(7 downto 0);
1152 dccacheadd <= vdccacheadd;
1154 dccachewr <= vdccachewr;
1155 accachedin <= ahbsi.hwdata(11 downto 0);
1156 accacheadd <= vaccacheadd;
1158 accachewr <= vaccachewr;
1159 sermaxdin <= ahbsi.hwdata(16 downto 0);
1160 sermaxadd <= vsermaxadd;
1162 sermaxwr <= vsermaxwr;
1163 seroffdin <= ahbsi.hwdata(16 downto 0);
1164 seroffadd <= vseroffadd;
1166 seroffwr <= vseroffwr;
1167 seroffdin <= ahbsi.hwdata(16 downto 0);
1168 servaladd <= vservaladd;
1170 servalwr <= vservalwr;
1171 servaldin <= ahbsi.hwdata(7 downto 0);
1173 jpg_setting.xmcumax <= r.preg.xmcumax;
1174 jpg_setting.ymcumax <= r.preg.ymcumax;
1175 jpg_setting.incaddy <= r.preg.incaddy;
1176 jpg_setting.incaddmcux <= r.preg.incaddmcux;
1177 jpg_setting.incaddmcuy <= r.preg.incaddmcuy;
1178 jpg_setting.fbstartadd <= r.preg.fbstartadd;
1179 startgen <= vstartgen;
1180 jpg_setting.samp_fact <= r.preg.sampf;
1182 kstrobeq <= r.hreg.getq;
1183 kdataq <= ahbsi.hwdata(7 downto 0);
1185 apbo.prdata <= vprdata;
1187 ahbso.hrdata <= vhrdata;
1190 kstrobe <= vkstrobe;
1191 kaddress <= r.memaddcnt;
1196 apbo.pirq <= (others => '0');
1197 apbo.pindex <= pindex;
1198 apbo.pconfig <= pconfig;
1199 ahbso.hconfig <= shconfig;
1200 ahbso.hresp <= "00";
1201 ahbso.hsplit <= (others => '0');
1202 ahbso.hcache <= '0';
1203 ahbso.hready <= '1';
1204 ahbso.hindex <= shindex;
1209 if rising_edge(clk) then