hal/HalDMOutSrc8192C_CE.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 //============================================================
  21 // Description:
  22 //
  23 // This file is for 92CE/92CU dynamic mechanism only
  24 //
  25 //
  26 //============================================================
  27
  28 //============================================================
  29 // include files
  30 //============================================================
  31
  32 #include "odm_precomp.h"
  33
  34 #define         DPK_DELTA_MAPPING_NUM   13
  35 #define         index_mapping_HP_NUM    15
  36 //091212 chiyokolin
  37 static  void
  38 odm_TXPowerTrackingCallback_ThermalMeter_92C(
  39             IN PADAPTER Adapter)
  40 {
  41         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
  42         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
  43         u8                      ThermalValue = 0, delta, delta_LCK, delta_IQK, delta_HP, TimeOut = 100;
  44         int                     ele_A, ele_D, TempCCk, X, value32;
  45         int                     Y, ele_C;
  46         s8                      OFDM_index[2], CCK_index = 0, OFDM_index_old[2], CCK_index_old = 0;
  47         int                     i = 0;
  48         bool            is2T = IS_92C_SERIAL(pHalData->VersionID);
  49
  50 #if MP_DRIVER == 1
  51         PMPT_CONTEXT    pMptCtx = &(Adapter->mppriv.MptCtx);
  52         u8                      *TxPwrLevel = pMptCtx->TxPwrLevel;
  53 #endif
  54         u8                      OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
  55         u8                      ThermalValue_HP_count = 0;
  56         u32                     ThermalValue_HP = 0;
  57         s32                     index_mapping_HP[index_mapping_HP_NUM] = {
  58                                         0,      1,      3,      4,      6,
  59                                         7,      9,      10,     12,     13,
  60                                         15,     16,     18,     19,     21
  61                                         };
  62         s8                      index_HP;
  63
  64         pdmpriv->TXPowerTrackingCallbackCnt++;  //cosa add for debug
  65         pdmpriv->bTXPowerTrackingInit = true;
  66
  67         if (pHalData->CurrentChannel == 14 && !pdmpriv->bCCKinCH14)
  68                 pdmpriv->bCCKinCH14 = true;
  69         else if (pHalData->CurrentChannel != 14 && pdmpriv->bCCKinCH14)
  70                 pdmpriv->bCCKinCH14 = false;
  71
  72         ThermalValue = (u8)PHY_QueryRFReg(Adapter, RF_PATH_A, RF_T_METER, 0x1f);        // 0x24: RF Reg[4:0]
  73
  74         rtl8192c_PHY_APCalibrate(Adapter, (ThermalValue - pHalData->EEPROMThermalMeter));
  75
  76         if (is2T)
  77                 rf = 2;
  78         else
  79                 rf = 1;
  80
  81         if (ThermalValue) {
  82                 {
  83                         //Query OFDM path A default setting
  84                         ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D;
  85                         for (i=0; i<OFDM_TABLE_SIZE_92C; i++)   //find the index
  86                         {
  87                                 if (ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
  88                                 {
  89                                         OFDM_index_old[0] = (u8)i;
  90                                         break;
  91                                 }
  92                         }
  93
  94                         //Query OFDM path B default setting
  95                         if (is2T)
  96                         {
  97                                 ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D;
  98                                 for (i=0; i<OFDM_TABLE_SIZE_92C; i++)   //find the index
  99                                 {
 100                                         if (ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
 101                                         {
 102                                                 OFDM_index_old[1] = (u8)i;
 103                                                 //DBG_8192C("Initial pathB ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n",rOFDM0_XBTxIQImbalance, ele_D, OFDM_index_old[1]);
 104                                                 break;
 105                                         }
 106                                 }
 107                         }
 108
 109                         //Query CCK default setting From 0xa24
 110                         TempCCk = PHY_QueryBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord)&bMaskCCK;
 111                         for (i=0 ; i<CCK_TABLE_SIZE ; i++)
 112                         {
 113                                 if (pdmpriv->bCCKinCH14)
 114                                 {
 115                                         if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==true)
 116                                         {
 117                                                 CCK_index_old =(u8)i;
 118                                                 //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14);
 119                                                 break;
 120                                         }
 121                                 }
 122                                 else
 123                                 {
 124                                         if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==true)
 125                                         {
 126                                                 CCK_index_old =(u8)i;
 127                                                 //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14);
 128                                                 break;
 129                                         }
 130                                 }
 131                         }
 132
 133                         if (!pdmpriv->ThermalValue)
 134                         {
 135                                 pdmpriv->ThermalValue = pHalData->EEPROMThermalMeter;
 136                                 pdmpriv->ThermalValue_LCK = ThermalValue;
 137                                 pdmpriv->ThermalValue_IQK = ThermalValue;
 138                                 pdmpriv->ThermalValue_DPK = pHalData->EEPROMThermalMeter;
 139
 140                                 for (i = 0; i < rf; i++)
 141                                         pdmpriv->OFDM_index_HP[i] = pdmpriv->OFDM_index[i] = OFDM_index_old[i];
 142                                 pdmpriv->CCK_index_HP = pdmpriv->CCK_index = CCK_index_old;
 143                         }
 144
 145                         if (pHalData->BoardType == BOARD_USB_High_PA)
 146                         {
 147                                 pdmpriv->ThermalValue_HP[pdmpriv->ThermalValue_HP_index] = ThermalValue;
 148                                 pdmpriv->ThermalValue_HP_index++;
 149                                 if (pdmpriv->ThermalValue_HP_index == HP_THERMAL_NUM)
 150                                         pdmpriv->ThermalValue_HP_index = 0;
 151
 152                                 for (i = 0; i < HP_THERMAL_NUM; i++)
 153                                 {
 154                                         if (pdmpriv->ThermalValue_HP[i])
 155                                         {
 156                                                 ThermalValue_HP += pdmpriv->ThermalValue_HP[i];
 157                                                 ThermalValue_HP_count++;
 158                                         }
 159                                 }
 160
 161                                 if (ThermalValue_HP_count)
 162                                         ThermalValue = (u8)(ThermalValue_HP / ThermalValue_HP_count);
 163                         }
 164                 }
 165
 166                 delta = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
 167                 if (pHalData->BoardType == BOARD_USB_High_PA) {
 168                         if (pdmpriv->bDoneTxpower)
 169                                 delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
 170                         else
 171                                 delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
 172                 } else {
 173                         delta_HP = 0;
 174                 }
 175                 delta_LCK = (ThermalValue > pdmpriv->ThermalValue_LCK)?(ThermalValue - pdmpriv->ThermalValue_LCK):(pdmpriv->ThermalValue_LCK - ThermalValue);
 176                 delta_IQK = (ThermalValue > pdmpriv->ThermalValue_IQK)?(ThermalValue - pdmpriv->ThermalValue_IQK):(pdmpriv->ThermalValue_IQK - ThermalValue);
 177
 178                 if (delta_LCK > 1) {
 179                         pdmpriv->ThermalValue_LCK = ThermalValue;
 180                         rtl8192c_PHY_LCCalibrate(Adapter);
 181                 }
 182
 183                 if ((delta > 0 || delta_HP > 0) && pdmpriv->TxPowerTrackControl) {
 184                         if (pHalData->BoardType == BOARD_USB_High_PA) {
 185                                 pdmpriv->bDoneTxpower = true;
 186                                 delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
 187
 188                                 if (delta_HP > index_mapping_HP_NUM-1)
 189                                         index_HP = index_mapping_HP[index_mapping_HP_NUM-1];
 190                                 else
 191                                         index_HP = index_mapping_HP[delta_HP];
 192
 193                                 if (ThermalValue > pHalData->EEPROMThermalMeter)        //set larger Tx power
 194                                 {
 195                                         for (i = 0; i < rf; i++)
 196                                                 OFDM_index[i] = pdmpriv->OFDM_index_HP[i] - index_HP;
 197                                         CCK_index = pdmpriv->CCK_index_HP -index_HP;
 198                                 } else {
 199                                         for (i = 0; i < rf; i++)
 200                                                 OFDM_index[i] = pdmpriv->OFDM_index_HP[i] + index_HP;
 201                                         CCK_index = pdmpriv->CCK_index_HP + index_HP;
 202                                 }
 203
 204                                 delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue);
 205
 206                         } else {
 207                                 if (ThermalValue > pdmpriv->ThermalValue) {
 208                                         for (i = 0; i < rf; i++)
 209                                                 pdmpriv->OFDM_index[i] -= delta;
 210                                         pdmpriv->CCK_index -= delta;
 211                                 } else {
 212                                         for (i = 0; i < rf; i++)
 213                                                 pdmpriv->OFDM_index[i] += delta;
 214                                         pdmpriv->CCK_index += delta;
 215                                 }
 216                         }
 217
 218
 219                         //no adjust
 220                         if (pHalData->BoardType != BOARD_USB_High_PA) {
 221                                 if (ThermalValue > pHalData->EEPROMThermalMeter) {
 222                                         for (i = 0; i < rf; i++)
 223                                                 OFDM_index[i] = pdmpriv->OFDM_index[i]+1;
 224                                         CCK_index = pdmpriv->CCK_index+1;
 225                                 } else {
 226                                         for (i = 0; i < rf; i++)
 227                                                 OFDM_index[i] = pdmpriv->OFDM_index[i];
 228                                         CCK_index = pdmpriv->CCK_index;
 229                                 }
 230
 231 #if MP_DRIVER == 1
 232                                 for (i = 0; i < rf; i++)
 233                                 {
 234                                         if (TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26)
 235                                         {
 236                                                 if (ThermalValue > pHalData->EEPROMThermalMeter)
 237                                                 {
 238                                                         if (delta < 5)
 239                                                                 OFDM_index[i] -= 1;
 240                                                         else
 241                                                                 OFDM_index[i] -= 2;
 242                                                 }
 243                                                 else if (delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter)
 244                                                 {
 245                                                         OFDM_index[i] += 1;
 246                                                 }
 247                                         }
 248                                         else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter)
 249                                         {
 250                                                 if (delta < 5)
 251                                                         OFDM_index[i] -= 1;
 252                                                 else
 253                                                         OFDM_index[i] -= 2;
 254                                         }
 255                                         else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5)
 256                                         {
 257                                                 OFDM_index[i] -= 1;
 258                                         }
 259                                 }
 260
 261                                 {
 262                                         if (TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26)
 263                                         {
 264                                                 if (ThermalValue > pHalData->EEPROMThermalMeter)
 265                                                 {
 266                                                         if (delta < 5)
 267                                                                 CCK_index -= 1;
 268                                                         else
 269                                                                 CCK_index -= 2;
 270                                                 }
 271                                                 else if (delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter)
 272                                                 {
 273                                                         CCK_index += 1;
 274                                                 }
 275                                         }
 276                                         else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter)
 277                                         {
 278                                                 if (delta < 5)
 279                                                         CCK_index -= 1;
 280                                                 else
 281                                                         CCK_index -= 2;
 282                                         }
 283                                         else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5)
 284                                         {
 285                                                 CCK_index -= 1;
 286                                         }
 287                                 }
 288 #endif
 289                         }
 290
 291                         for (i = 0; i < rf; i++)
 292                         {
 293                                 if (OFDM_index[i] > (OFDM_TABLE_SIZE_92C-1))
 294                                         OFDM_index[i] = (OFDM_TABLE_SIZE_92C-1);
 295                                 else if (OFDM_index[i] < OFDM_min_index)
 296                                         OFDM_index[i] = OFDM_min_index;
 297                         }
 298
 299                         if (CCK_index > (CCK_TABLE_SIZE-1))
 300                                 CCK_index = (CCK_TABLE_SIZE-1);
 301                         else if (CCK_index < 0)
 302                                 CCK_index = 0;
 303
 304                         /*if (is2T)
 305                         {
 306                                 DBG_8192C("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n",
 307                                         OFDM_index[0], OFDM_index[1], CCK_index);
 308                         }
 309                         else
 310                         {
 311                                 DBG_8192C("new OFDM_A_index=0x%x, CCK_index=0x%x\n",
 312                                         OFDM_index[0], CCK_index);
 313                         }*/
 314                 }
 315
 316                 if (pdmpriv->TxPowerTrackControl && (delta != 0 || delta_HP != 0))
 317                 {
 318                         //Adujst OFDM Ant_A according to IQK result
 319                         ele_D = (OFDMSwingTable[OFDM_index[0]] & 0xFFC00000)>>22;
 320                         X = pdmpriv->RegE94;
 321                         Y = pdmpriv->RegE9C;
 322
 323                         if (X != 0)
 324                         {
 325                                 if ((X & 0x00000200) != 0)
 326                                         X = X | 0xFFFFFC00;
 327                                 ele_A = ((X * ele_D)>>8)&0x000003FF;
 328
 329                                 //new element C = element D x Y
 330                                 if ((Y & 0x00000200) != 0)
 331                                         Y = Y | 0xFFFFFC00;
 332                                 ele_C = ((Y * ele_D)>>8)&0x000003FF;
 333
 334                                 //wirte new elements A, C, D to regC80 and regC94, element B is always 0
 335                                 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
 336                                 PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
 337
 338                                 value32 = (ele_C&0x000003C0)>>6;
 339                                 PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
 340
 341                                 value32 = ((X * ele_D)>>7)&0x01;
 342                                 PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31, value32);
 343
 344                                 value32 = ((Y * ele_D)>>7)&0x01;
 345                                 PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT29, value32);
 346
 347                         }
 348                         else
 349                         {
 350                                 PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index[0]]);
 351                                 PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
 352                                 PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31|BIT29, 0x00);
 353                         }
 354
 355                         //RTPRINT(FINIT, INIT_IQK, ("TxPwrTracking path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D));
 356
 357                         //Adjust CCK according to IQK result
 358                         if (!pdmpriv->bCCKinCH14) {
 359                                 rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
 360                                 rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
 361                                 rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
 362                                 rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
 363                                 rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
 364                                 rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
 365                                 rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
 366                                 rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
 367                         }
 368                         else {
 369                                 rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
 370                                 rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
 371                                 rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
 372                                 rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
 373                                 rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
 374                                 rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
 375                                 rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
 376                                 rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
 377                         }
 378
 379                         if (is2T)
 380                         {
 381                                 ele_D = (OFDMSwingTable[(u8)OFDM_index[1]] & 0xFFC00000)>>22;
 382
 383                                 //new element A = element D x X
 384                                 X = pdmpriv->RegEB4;
 385                                 Y = pdmpriv->RegEBC;
 386
 387                                 if (X != 0) {
 388                                         if ((X & 0x00000200) != 0)      //consider minus
 389                                                 X = X | 0xFFFFFC00;
 390                                         ele_A = ((X * ele_D)>>8)&0x000003FF;
 391
 392                                         //new element C = element D x Y
 393                                         if ((Y & 0x00000200) != 0)
 394                                                 Y = Y | 0xFFFFFC00;
 395                                         ele_C = ((Y * ele_D)>>8)&0x00003FF;
 396
 397                                         //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
 398                                         value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
 399                                         PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
 400
 401                                         value32 = (ele_C&0x000003C0)>>6;
 402                                         PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
 403
 404                                         value32 = ((X * ele_D)>>7)&0x01;
 405                                         PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27, value32);
 406
 407                                         value32 = ((Y * ele_D)>>7)&0x01;
 408                                         PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT25, value32);
 409
 410                                 }
 411                                 else {
 412                                         PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index[1]]);
 413                                         PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
 414                                         PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27|BIT25, 0x00);
 415                                 }
 416
 417                                 //DBG_8192C("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D);
 418                         }
 419
 420                         /*
 421                         DBG_8192C("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", \
 422                                         PHY_QueryBBReg(Adapter, 0xc80, bMaskDWord),\
 423                                         PHY_QueryBBReg(Adapter, 0xc94, bMaskDWord), \
 424                                         PHY_QueryRFReg(Adapter, RF_PATH_A, 0x24, bMaskDWord));
 425                         */
 426                 }
 427
 428 #if MP_DRIVER == 1
 429                 if (delta_IQK > 1)
 430 #else
 431                 if (delta_IQK > 3)
 432 #endif
 433                 {
 434                         pdmpriv->ThermalValue_IQK = ThermalValue;
 435                         rtl8192c_PHY_IQCalibrate(Adapter,false);
 436                 }
 437
 438                 //update thermal meter value
 439                 if (pdmpriv->TxPowerTrackControl)
 440                         pdmpriv->ThermalValue = ThermalValue;
 441
 442         }
 443
 444         //DBG_8192C("<===dm_TXPowerTrackingCallback_ThermalMeter_92C\n");
 445
 446         pdmpriv->TXPowercount = 0;
 447
 448 }
 449
 450 /*
 451 static  void
 452 odm_InitializeTXPowerTracking_ThermalMeter(
 453         IN      PADAPTER                Adapter)
 454 {
 455         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 456         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 457
 458         //pMgntInfo->bTXPowerTracking = true;
 459         pdmpriv->TXPowercount = 0;
 460         pdmpriv->bTXPowerTrackingInit = false;
 461         pdmpriv->ThermalValue = 0;
 462
 463 #if     (MP_DRIVER != 1)        //for mp driver, turn off txpwrtracking as default
 464         pdmpriv->TxPowerTrackControl = true;
 465 #endif
 466
 467         MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
 468 }
 469
 470
 471 static void
 472 ODM_InitializeTXPowerTracking(
 473         IN      PADAPTER                Adapter)
 474 {
 475         odm_InitializeTXPowerTracking_ThermalMeter(Adapter);
 476 }
 477 */
 478 //
 479 //      Description:
 480 //              - Dispatch TxPower Tracking direct call ONLY for 92s.
 481 //              - We shall NOT schedule Workitem within PASSIVE LEVEL, which will cause system resource
 482 //                 leakage under some platform.
 483 //
 484 //      Assumption:
 485 //              PASSIVE_LEVEL when this routine is called.
 486 //
 487 //      Added by Roger, 2009.06.18.
 488 //
 489 static void
 490 ODM_TXPowerTracking92CDirectCall(
 491             IN  PADAPTER                Adapter)
 492 {
 493         odm_TXPowerTrackingCallback_ThermalMeter_92C(Adapter);
 494 }
 495
 496 static void
 497 odm_CheckTXPowerTracking_ThermalMeter(
 498         IN      PADAPTER                Adapter)
 499 {
 500         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 501         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
 502         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
 503         //u1Byte                                        TxPowerCheckCnt = 5;    //10 sec
 504
 505         //if (!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/)
 506         if (!(podmpriv->SupportAbility & ODM_RF_TX_PWR_TRACK))
 507         {
 508                 return;
 509         }
 510
 511         if (!pdmpriv->TM_Trigger)               //at least delay 1 sec
 512         {
 513                 //pHalData->TxPowerCheckCnt++;  //cosa add for debug
 514                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
 515                 //DBG_8192C("Trigger 92C Thermal Meter!!\n");
 516
 517                 pdmpriv->TM_Trigger = 1;
 518                 return;
 519
 520         }
 521         else
 522         {
 523                 //DBG_8192C("Schedule TxPowerTracking direct call!!\n");
 524                 ODM_TXPowerTracking92CDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
 525                 pdmpriv->TM_Trigger = 0;
 526         }
 527
 528 }
 529
 530
 531 void
 532 rtl8192c_odm_CheckTXPowerTracking(
 533         IN      PADAPTER                Adapter)
 534 {
 535         odm_CheckTXPowerTracking_ThermalMeter(Adapter);
 536 }
 537
 538
 539
 540 #ifdef CONFIG_ANTENNA_DIVERSITY
 541 // Add new function to reset the state of antenna diversity before link.
 542 //
 543 void odm_SwAntDivResetBeforeLink8192C(IN PDM_ODM_T pDM_Odm)
 544 {
 545         SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
 546
 547         pDM_SWAT_Table->SWAS_NoLink_State = 0;
 548 }
 549
 550 // Compare RSSI for deciding antenna
 551 void    odm_AntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
 552 {
 553         //PADAPTER Adapter = pDM_Odm->Adapter ;
 554
 555         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 556         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
 557         if ((0 != pHalData->AntDivCfg) && (!IS_92C_SERIAL(pHalData->VersionID)) )
 558         {
 559                 //DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
 560                 //      src->Rssi,query_rx_pwr_percentage(src->Rssi));
 561                 //select optimum_antenna for before linked =>For antenna diversity
 562                 if (dst->Rssi >=  src->Rssi )//keep org parameter
 563                 {
 564                         src->Rssi = dst->Rssi;
 565                         src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
 566                 }
 567         }
 568 }
 569
 570 // Add new function to reset the state of antenna diversity before link.
 571 u8 odm_AntDivBeforeLink8192C(PADAPTER Adapter )
 572 {
 573
 574         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 575         PDM_ODM_T       pDM_Odm =&pHalData->odmpriv;
 576         SWAT_T          *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
 577         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
 578
 579         // Condition that does not need to use antenna diversity.
 580         if (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))
 581         {
 582                 //DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
 583                 return false;
 584         }
 585
 586         if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
 587         {
 588                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
 589                 return false;
 590         }
 591         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
 592 /*
 593         if (pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
 594         {
 595
 596
 597                 ODM_RT_TRACE(pDM_Odm,COMP_SWAS, DBG_LOUD,
 598                                 ("SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
 599                                 pMgntInfo->RFChangeInProgress,
 600                                 pHalData->eRFPowerState));
 601
 602                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
 603
 604                 return FALSE;
 605         }
 606 */
 607
 608         if (pDM_SWAT_Table->SWAS_NoLink_State == 0) {
 609                 //switch channel
 610                 pDM_SWAT_Table->SWAS_NoLink_State = 1;
 611                 pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
 612
 613                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
 614                 rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, false);
 615                 //DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");
 616                 return true;
 617         }
 618         else
 619         {
 620                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
 621                 return false;
 622         }
 623
 624
 625
 626 }
 627 #endif
 628
 629 //-------------------------------------------------------------------------
 630 //
 631 //      IQK
 632 //
 633 //-------------------------------------------------------------------------
 634 #define MAX_TOLERANCE           5
 635 #define IQK_DELAY_TIME          1       //ms
 636
 637 static u8                       //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
 638 _PHY_PathA_IQK(
 639         IN      PADAPTER        pAdapter,
 640         IN      bool            configPathB
 641         )
 642 {
 643         u32 regEAC, regE94, regE9C, regEA4;
 644         u8 result = 0x00;
 645         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 646
 647         //RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
 648
 649         //path-A IQK setting
 650         //RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
 651         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
 652         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
 653         PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
 654
 655         PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
 656                 IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
 657
 658         //path-B IQK setting
 659         if (configPathB)
 660         {
 661                 PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
 662                 PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
 663                 PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
 664                 PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
 665         }
 666
 667         //LO calibration setting
 668         //RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
 669         PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
 670
 671         //One shot, path A LOK & IQK
 672         //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
 673         PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 674         PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 675
 676         // delay x ms
 677         //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
 678         rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
 679
 680         // Check failed
 681         regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 682         //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
 683         regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
 684         //RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
 685         regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
 686         //RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
 687         regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
 688         //RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
 689
 690         if (!(regEAC & BIT28) &&
 691                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
 692                 (((regE9C & 0x03FF0000)>>16) != 0x42) )
 693                 result |= 0x01;
 694         else                                                    //if Tx not OK, ignore Rx
 695                 return result;
 696
 697         if (!(regEAC & BIT27) &&                //if Tx is OK, check whether Rx is OK
 698                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
 699                 (((regEAC & 0x03FF0000)>>16) != 0x36))
 700                 result |= 0x02;
 701         else
 702                 DBG_8192C("Path A Rx IQK fail!!\n");
 703
 704         return result;
 705
 706
 707 }
 708
 709 static u8                               //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
 710 _PHY_PathB_IQK(
 711         IN      PADAPTER        pAdapter
 712         )
 713 {
 714         u32 regEAC, regEB4, regEBC, regEC4, regECC;
 715         u8      result = 0x00;
 716         //RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n"));
 717
 718         //One shot, path B LOK & IQK
 719         //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
 720         PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
 721         PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
 722
 723         // delay x ms
 724         //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
 725         rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
 726
 727         // Check failed
 728         regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 729         //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
 730         regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord);
 731         //RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4));
 732         regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord);
 733         //RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC));
 734         regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord);
 735         //RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4));
 736         regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord);
 737         //RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC));
 738
 739         if (!(regEAC & BIT31) &&
 740                 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
 741                 (((regEBC & 0x03FF0000)>>16) != 0x42))
 742                 result |= 0x01;
 743         else
 744                 return result;
 745
 746         if (!(regEAC & BIT30) &&
 747                 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
 748                 (((regECC & 0x03FF0000)>>16) != 0x36))
 749                 result |= 0x02;
 750         else
 751                 DBG_8192C("Path B Rx IQK fail!!\n");
 752
 753
 754         return result;
 755
 756 }
 757
 758 static void
 759 _PHY_PathAFillIQKMatrix(
 760         IN      PADAPTER        pAdapter,
 761         IN      bool            bIQKOK,
 762         IN      int                     result[][8],
 763         IN      u8                      final_candidate,
 764         IN      bool            bTxOnly
 765         )
 766 {
 767         u32     Oldval_0, X, TX0_A, reg;
 768         s32     Y, TX0_C;
 769
 770         DBG_8192C("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
 771
 772         if (final_candidate == 0xFF)
 773                 return;
 774         else if (bIQKOK)
 775         {
 776                 Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
 777
 778                 X = result[final_candidate][0];
 779                 if ((X & 0x00000200) != 0)
 780                         X = X | 0xFFFFFC00;
 781                 TX0_A = (X * Oldval_0) >> 8;
 782                 //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX0_A = 0x%lx, Oldval_0 0x%lx\n", X, TX0_A, Oldval_0));
 783                 PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
 784                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
 785
 786                 Y = result[final_candidate][1];
 787                 if ((Y & 0x00000200) != 0)
 788                         Y = Y | 0xFFFFFC00;
 789                 TX0_C = (Y * Oldval_0) >> 8;
 790                 //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX = 0x%lx\n", Y, TX0_C));
 791                 PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
 792                 PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
 793                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
 794
 795                 if (bTxOnly)
 796                 {
 797                         DBG_8192C("_PHY_PathAFillIQKMatrix only Tx OK\n");
 798                         return;
 799                 }
 800
 801                 reg = result[final_candidate][2];
 802                 PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
 803
 804                 reg = result[final_candidate][3] & 0x3F;
 805                 PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
 806
 807                 reg = (result[final_candidate][3] >> 6) & 0xF;
 808                 PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
 809         }
 810 }
 811
 812 static void
 813 _PHY_PathBFillIQKMatrix(
 814         IN      PADAPTER        pAdapter,
 815         IN      bool            bIQKOK,
 816         IN      int                     result[][8],
 817         IN      u8                      final_candidate,
 818         IN      bool            bTxOnly                 //do Tx only
 819         )
 820 {
 821         u32     Oldval_1, X, TX1_A, reg;
 822         s32     Y, TX1_C;
 823
 824         DBG_8192C("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
 825
 826         if (final_candidate == 0xFF)
 827                 return;
 828         else if (bIQKOK)
 829         {
 830                 Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
 831
 832                 X = result[final_candidate][4];
 833                 if ((X & 0x00000200) != 0)
 834                         X = X | 0xFFFFFC00;
 835                 TX1_A = (X * Oldval_1) >> 8;
 836                 //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX1_A = 0x%lx\n", X, TX1_A));
 837                 PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
 838                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
 839
 840                 Y = result[final_candidate][5];
 841                 if ((Y & 0x00000200) != 0)
 842                         Y = Y | 0xFFFFFC00;
 843                 TX1_C = (Y * Oldval_1) >> 8;
 844                 //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX1_C = 0x%lx\n", Y, TX1_C));
 845                 PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
 846                 PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
 847                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
 848
 849                 if (bTxOnly)
 850                         return;
 851
 852                 reg = result[final_candidate][6];
 853                 PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
 854
 855                 reg = result[final_candidate][7] & 0x3F;
 856                 PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
 857
 858                 reg = (result[final_candidate][7] >> 6) & 0xF;
 859                 PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);
 860         }
 861 }
 862
 863 static void
 864 _PHY_SaveADDARegisters(
 865         IN      PADAPTER        pAdapter,
 866         IN      u32*            ADDAReg,
 867         IN      u32*            ADDABackup,
 868         IN      u32                     RegisterNum
 869         )
 870 {
 871         u32     i;
 872
 873         //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
 874         for ( i = 0 ; i < RegisterNum ; i++) {
 875                 ADDABackup[i] = PHY_QueryBBReg(pAdapter, ADDAReg[i], bMaskDWord);
 876         }
 877 }
 878
 879 static void
 880 _PHY_SaveMACRegisters(
 881         IN      PADAPTER        pAdapter,
 882         IN      u32*            MACReg,
 883         IN      u32*            MACBackup
 884         )
 885 {
 886         u32     i;
 887
 888         //RTPRINT(FINIT, INIT_IQK, ("Save MAC parameters.\n"));
 889         for ( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
 890                 MACBackup[i] =rtw_read8(pAdapter, MACReg[i]);
 891         }
 892         MACBackup[i] = rtw_read32(pAdapter, MACReg[i]);
 893
 894 }
 895
 896 static void
 897 _PHY_ReloadADDARegisters(
 898         IN      PADAPTER        pAdapter,
 899         IN      u32*            ADDAReg,
 900         IN      u32*            ADDABackup,
 901         IN      u32                     RegiesterNum
 902         )
 903 {
 904         u32     i;
 905
 906         //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
 907         for (i = 0 ; i < RegiesterNum ; i++) {
 908                 PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
 909         }
 910 }
 911
 912 static void
 913 _PHY_ReloadMACRegisters(
 914         IN      PADAPTER        pAdapter,
 915         IN      u32*            MACReg,
 916         IN      u32*            MACBackup
 917         )
 918 {
 919         u32     i;
 920
 921         //RTPRINT(FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
 922         for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
 923                 rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
 924         }
 925         rtw_write32(pAdapter, MACReg[i], MACBackup[i]);
 926 }
 927
 928 static void
 929 _PHY_PathADDAOn(
 930         IN      PADAPTER        pAdapter,
 931         IN      u32*            ADDAReg,
 932         IN      bool            isPathAOn,
 933         IN      bool            is2T
 934         )
 935 {
 936         u32     pathOn;
 937         u32     i;
 938
 939         //RTPRINT(FINIT, INIT_IQK, ("ADDA ON.\n"));
 940
 941         pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
 942         if (false == is2T) {
 943                 pathOn = 0x0bdb25a0;
 944                 PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
 945         }
 946         else {
 947                 PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, pathOn);
 948         }
 949
 950         for ( i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
 951                 PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, pathOn);
 952         }
 953
 954 }
 955
 956 static void
 957 _PHY_MACSettingCalibration(
 958         IN      PADAPTER        pAdapter,
 959         IN      u32*            MACReg,
 960         IN      u32*            MACBackup
 961         )
 962 {
 963         u32     i = 0;
 964
 965         //RTPRINT(FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
 966
 967         rtw_write8(pAdapter, MACReg[i], 0x3F);
 968
 969         for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
 970                 rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
 971         }
 972         rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
 973
 974 }
 975
 976 static void
 977 _PHY_PathAStandBy(
 978         IN      PADAPTER        pAdapter
 979         )
 980 {
 981         //RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n"));
 982
 983         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0);
 984         PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000);
 985         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
 986 }
 987
 988 static void
 989 _PHY_PIModeSwitch(
 990         IN      PADAPTER        pAdapter,
 991         IN      bool            PIMode
 992         )
 993 {
 994         u32     mode;
 995
 996         //RTPRINT(FINIT, INIT_IQK, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
 997
 998         mode = PIMode ? 0x01000100 : 0x01000000;
 999         PHY_SetBBReg(pAdapter, 0x820, bMaskDWord, mode);
1000         PHY_SetBBReg(pAdapter, 0x828, bMaskDWord, mode);
1001 }
1002
1003 /*
1004 return false => do IQK again
1005 */
1006 static bool
1007 _PHY_SimularityCompare(
1008         IN      PADAPTER        pAdapter,
1009         IN      int             result[][8],
1010         IN      u8               c1,
1011         IN      u8               c2
1012         )
1013 {
1014         u32             i, j, diff, SimularityBitMap, bound = 0;
1015         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1016         u8              final_candidate[2] = {0xFF, 0xFF};      //for path A and path B
1017         bool            bResult = true, is2T = IS_92C_SERIAL( pHalData->VersionID);
1018
1019         if (is2T)
1020                 bound = 8;
1021         else
1022                 bound = 4;
1023
1024         SimularityBitMap = 0;
1025
1026         for ( i = 0; i < bound; i++ )
1027         {
1028                 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
1029                 if (diff > MAX_TOLERANCE)
1030                 {
1031                         if ((i == 2 || i == 6) && !SimularityBitMap)
1032                         {
1033                                 if (result[c1][i]+result[c1][i+1] == 0)
1034                                         final_candidate[(i/4)] = c2;
1035                                 else if (result[c2][i]+result[c2][i+1] == 0)
1036                                         final_candidate[(i/4)] = c1;
1037                                 else
1038                                         SimularityBitMap = SimularityBitMap|(1<<i);
1039                         }
1040                         else
1041                                 SimularityBitMap = SimularityBitMap|(1<<i);
1042                 }
1043         }
1044
1045         if ( SimularityBitMap == 0)
1046         {
1047                 for ( i = 0; i < (bound/4); i++ )
1048                 {
1049                         if (final_candidate[i] != 0xFF)
1050                         {
1051                                 for ( j = i*4; j < (i+1)*4-2; j++)
1052                                         result[3][j] = result[final_candidate[i]][j];
1053                                 bResult = false;
1054                         }
1055                 }
1056                 return bResult;
1057         }
1058         else if (!(SimularityBitMap & 0x0F))                    //path A OK
1059         {
1060                 for (i = 0; i < 4; i++)
1061                         result[3][i] = result[c1][i];
1062                 return false;
1063         }
1064         else if (!(SimularityBitMap & 0xF0) && is2T)    //path B OK
1065         {
1066                 for (i = 4; i < 8; i++)
1067                         result[3][i] = result[c1][i];
1068                 return false;
1069         }
1070         else
1071                 return false;
1072
1073 }
1074
1075 static void
1076 _PHY_IQCalibrate(
1077         IN      PADAPTER        pAdapter,
1078         IN      int             result[][8],
1079         IN      u8              t,
1080         IN      bool            is2T
1081         )
1082 {
1083         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1084         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1085         u32                     i;
1086         u8                      PathAOK, PathBOK;
1087         u32                     ADDA_REG[IQK_ADDA_REG_NUM] = {
1088                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,
1089                                                 rRx_Wait_CCA,           rTx_CCK_RFON,
1090                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,
1091                                                 rTx_OFDM_BBON,  rTx_To_Rx,
1092                                                 rTx_To_Tx,              rRx_CCK,
1093                                                 rRx_OFDM,               rRx_Wait_RIFS,
1094                                                 rRx_TO_Rx,              rStandby,
1095                                                 rSleep,                         rPMPD_ANAEN };
1096
1097         u32                     IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1098                                                 REG_TXPAUSE,            REG_BCN_CTRL,
1099                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1100
1101         u32                     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1102                                                         rOFDM0_TRxPathEnable,           rOFDM0_TRMuxPar,
1103                                                         rFPGA0_XCD_RFInterfaceSW,       rConfig_AntA,   rConfig_AntB,
1104                                                         rFPGA0_XAB_RFInterfaceSW,       rFPGA0_XA_RFInterfaceOE,
1105                                                         rFPGA0_XB_RFInterfaceOE,        rFPGA0_RFMOD
1106                                                         };
1107
1108 #if MP_DRIVER
1109         const u32       retryCount = 9;
1110 #else
1111         const u32       retryCount = 2;
1112 #endif
1113
1114         // Note: IQ calibration must be performed after loading
1115         //              PHY_REG.txt , and radio_a, radio_b.txt
1116
1117         u32 bbvalue;
1118
1119         if (t==0)
1120         {
1121                 bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
1122                 //RTPRINT(FINIT, INIT_IQK, ("PHY_IQCalibrate()==>0x%08lx\n",bbvalue));
1123
1124                 //RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
1125
1126                 // Save ADDA parameters, turn Path A ADDA on
1127                 _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup,IQK_ADDA_REG_NUM);
1128                 _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
1129                 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
1130         }
1131         _PHY_PathADDAOn(pAdapter, ADDA_REG, true, is2T);
1132
1133         if (t==0)
1134         {
1135                 pdmpriv->bRfPiEnable = (u8)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8));
1136         }
1137
1138         if (!pdmpriv->bRfPiEnable) {
1139                 // Switch BB to PI mode to do IQ Calibration.
1140                 _PHY_PIModeSwitch(pAdapter, true);
1141         }
1142
1143         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00);
1144         PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1145         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1146         PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1147         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
1148         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
1149         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
1150         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
1151
1152         if (is2T)
1153         {
1154                 PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
1155                 PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
1156         }
1157
1158         //MAC settings
1159         _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
1160
1161         //Page B init
1162         PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
1163
1164         if (is2T)
1165         {
1166                 PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
1167         }
1168
1169         // IQ calibration setting
1170         //RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
1171         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
1172         PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00);
1173         PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800);
1174
1175         for (i = 0 ; i < retryCount ; i++) {
1176                 PathAOK = _PHY_PathA_IQK(pAdapter, is2T);
1177                 if (PathAOK == 0x03) {
1178                                 DBG_8192C("Path A IQK Success!!\n");
1179                                 result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1180                                 result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1181                                 result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1182                                 result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1183                         break;
1184                 }
1185                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK
1186                 {
1187                         DBG_8192C("Path A IQK Only  Tx Success!!\n");
1188
1189                         result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1190                         result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1191                 }
1192         }
1193
1194         if (0x00 == PathAOK) {
1195                 DBG_8192C("Path A IQK failed!!\n");
1196         }
1197
1198         if (is2T) {
1199                 _PHY_PathAStandBy(pAdapter);
1200
1201                 // Turn Path B ADDA on
1202                 _PHY_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
1203
1204                 for (i = 0 ; i < retryCount ; i++) {
1205                         PathBOK = _PHY_PathB_IQK(pAdapter);
1206                         if (PathBOK == 0x03) {
1207                                 DBG_8192C("Path B IQK Success!!\n");
1208                                 result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1209                                 result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1210                                 result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
1211                                 result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
1212                                 break;
1213                         }
1214                         else if (i == (retryCount - 1) && PathBOK == 0x01)      //Tx IQK OK
1215                         {
1216                                 DBG_8192C("Path B Only Tx IQK Success!!\n");
1217                                 result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1218                                 result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1219                         }
1220                 }
1221
1222                 if (0x00 == PathBOK) {
1223                         DBG_8192C("Path B IQK failed!!\n");
1224                 }
1225         }
1226
1227         //Back to BB mode, load original value
1228         //RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
1229         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0);
1230
1231         if (t!=0)
1232         {
1233                 if (!pdmpriv->bRfPiEnable) {
1234                         // Switch back BB to SI mode after finish IQ Calibration.
1235                         _PHY_PIModeSwitch(pAdapter, false);
1236                 }
1237
1238                 // Reload ADDA power saving parameters
1239                 _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM);
1240
1241                 // Reload MAC parameters
1242                 _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
1243
1244                 // Reload BB parameters
1245                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
1246
1247                 // Restore RX initial gain
1248                 PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
1249                 if (is2T) {
1250                         PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
1251                 }
1252
1253                 //load 0xe30 IQC default value
1254                 PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1255                 PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1256
1257         }
1258         //RTPRINT(FINIT, INIT_IQK, ("_PHY_IQCalibrate() <==\n"));
1259
1260 }
1261
1262
1263 static void
1264 _PHY_LCCalibrate(
1265         IN      PADAPTER        pAdapter,
1266         IN      bool            is2T
1267         )
1268 {
1269         u8      tmpReg;
1270         u32     RF_Amode = 0, RF_Bmode = 0, LC_Cal;
1271
1272         //Check continuous TX and Packet TX
1273         tmpReg = rtw_read8(pAdapter, 0xd03);
1274
1275         if ((tmpReg&0x70) != 0)                 //Deal with contisuous TX case
1276                 rtw_write8(pAdapter, 0xd03, tmpReg&0x8F);       //disable all continuous TX
1277         else                                                    // Deal with Packet TX case
1278                 rtw_write8(pAdapter, REG_TXPAUSE, 0xFF);                        // block all queues
1279
1280         if ((tmpReg&0x70) != 0)
1281         {
1282                 //1. Read original RF mode
1283                 //Path-A
1284                 RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
1285
1286                 //Path-B
1287                 if (is2T)
1288                         RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
1289
1290                 //2. Set RF mode = standby mode
1291                 //Path-A
1292                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1293
1294                 //Path-B
1295                 if (is2T)
1296                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1297         }
1298
1299         //3. Read RF reg18
1300         LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1301
1302         //4. Set LC calibration begin
1303         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1304
1305         #ifdef CONFIG_LONG_DELAY_ISSUE
1306         rtw_msleep_os(100);
1307         #else
1308         rtw_mdelay_os(100);
1309         #endif
1310
1311         //Restore original situation
1312         if ((tmpReg&0x70) != 0) //Deal with contisuous TX case
1313         {
1314                 //Path-A
1315                 rtw_write8(pAdapter, 0xd03, tmpReg);
1316                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1317
1318                 //Path-B
1319                 if (is2T)
1320                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1321         }
1322         else // Deal with Packet TX case
1323         {
1324                 rtw_write8(pAdapter, REG_TXPAUSE, 0x00);
1325         }
1326
1327 }
1328
1329
1330 //Analog Pre-distortion calibration
1331 #define         APK_BB_REG_NUM  8
1332 #define         APK_CURVE_REG_NUM 4
1333 #define         PATH_NUM                2
1334
1335 static void
1336 _PHY_APCalibrate(
1337         IN      PADAPTER        pAdapter,
1338         IN      char            delta,
1339         IN      bool            is2T
1340         )
1341 {
1342         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1343         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1344
1345         u32                     regD[PATH_NUM];
1346         u32                     tmpReg, index, offset, i, apkbound;
1347         u8                      path, pathbound = PATH_NUM;
1348         u32                     BB_backup[APK_BB_REG_NUM];
1349         u32                     BB_REG[APK_BB_REG_NUM] = {
1350                                                 rFPGA1_TxBlock,         rOFDM0_TRxPathEnable,
1351                                                 rFPGA0_RFMOD,   rOFDM0_TRMuxPar,
1352                                                 rFPGA0_XCD_RFInterfaceSW,       rFPGA0_XAB_RFInterfaceSW,
1353                                                 rFPGA0_XA_RFInterfaceOE,        rFPGA0_XB_RFInterfaceOE };
1354         u32                     BB_AP_MODE[APK_BB_REG_NUM] = {
1355                                                 0x00000020, 0x00a05430, 0x02040000,
1356                                                 0x000800e4, 0x00204000 };
1357         u32                     BB_normal_AP_MODE[APK_BB_REG_NUM] = {
1358                                                 0x00000020, 0x00a05430, 0x02040000,
1359                                                 0x000800e4, 0x22204000 };
1360
1361         u32                     AFE_backup[IQK_ADDA_REG_NUM];
1362         u32                     AFE_REG[IQK_ADDA_REG_NUM] = {
1363                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,
1364                                                 rRx_Wait_CCA,           rTx_CCK_RFON,
1365                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,
1366                                                 rTx_OFDM_BBON,  rTx_To_Rx,
1367                                                 rTx_To_Tx,              rRx_CCK,
1368                                                 rRx_OFDM,               rRx_Wait_RIFS,
1369                                                 rRx_TO_Rx,              rStandby,
1370                                                 rSleep,                         rPMPD_ANAEN };
1371
1372         u32                     MAC_backup[IQK_MAC_REG_NUM];
1373         u32                     MAC_REG[IQK_MAC_REG_NUM] = {
1374                                                 REG_TXPAUSE,            REG_BCN_CTRL,
1375                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1376
1377         u32                     APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1378                                         {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1379                                         {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1380                                         };
1381
1382         u32                     APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1383                                         {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},  //path settings equal to path b settings
1384                                         {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1385                                         };
1386
1387         u32                     APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1388                                         {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1389                                         {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1390                                         };
1391
1392         u32                     APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1393                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},  //path settings equal to path b settings
1394                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1395                                         };
1396         u32                     AFE_on_off[PATH_NUM] = {
1397                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on
1398
1399         u32                     APK_offset[PATH_NUM] = {
1400                                         rConfig_AntA, rConfig_AntB};
1401
1402         u32                     APK_normal_offset[PATH_NUM] = {
1403                                         rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
1404
1405         u32                     APK_value[PATH_NUM] = {
1406                                         0x92fc0000, 0x12fc0000};
1407
1408         u32                     APK_normal_value[PATH_NUM] = {
1409                                         0x92680000, 0x12680000};
1410
1411         char                    APK_delta_mapping[APK_BB_REG_NUM][13] = {
1412                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1413                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1414                                         {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1415                                         {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1416                                         {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1417                                         };
1418
1419         u32                     APK_normal_setting_value_1[13] = {
1420                                         0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1421                                         0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1422                                         0x12680000, 0x00880000, 0x00880000
1423                                         };
1424
1425         u32                     APK_normal_setting_value_2[16] = {
1426                                         0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1427                                         0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1428                                         0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1429                                         0x00050006
1430                                         };
1431
1432         u32                     APK_result[PATH_NUM][APK_BB_REG_NUM];   //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
1433         //u32                   AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
1434
1435         int                     BB_offset, delta_V, delta_offset;
1436
1437 #if (MP_DRIVER == 1)
1438         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;
1439
1440         pMptCtx->APK_bound[0] = 45;
1441         pMptCtx->APK_bound[1] = 52;
1442 #endif
1443
1444         //RTPRINT(FINIT, INIT_IQK, ("==>PHY_APCalibrate() delta %d\n", delta));
1445
1446         //RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s %s\n", (is2T ? "2T2R" : "1T1R"), (isNormal ? "Normal chip" : "Test chip")));
1447
1448         if (!is2T)
1449                 pathbound = 1;
1450
1451         //2 FOR NORMAL CHIP SETTINGS
1452
1453 // Temporarily do not allow normal driver to do the following settings because these offset
1454 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
1455 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
1456 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
1457 #if (MP_DRIVER != 1)
1458         return;
1459 #endif
1460
1461         //settings adjust for normal chip
1462         for (index = 0; index < PATH_NUM; index ++)
1463         {
1464                 APK_offset[index] = APK_normal_offset[index];
1465                 APK_value[index] = APK_normal_value[index];
1466                 AFE_on_off[index] = 0x6fdb25a4;
1467         }
1468
1469         for (index = 0; index < APK_BB_REG_NUM; index ++)
1470         {
1471                 for (path = 0; path < pathbound; path++)
1472                 {
1473                         APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
1474                         APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
1475                 }
1476                 BB_AP_MODE[index] = BB_normal_AP_MODE[index];
1477         }
1478
1479         apkbound = 6;
1480
1481         //save BB default value
1482         for (index = 0; index < APK_BB_REG_NUM ; index++)
1483         {
1484                 if (index == 0)         //skip
1485                         continue;
1486                 BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord);
1487         }
1488
1489         //save MAC default value
1490         _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
1491
1492         //save AFE default value
1493         _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
1494
1495         for (path = 0; path < pathbound; path++)
1496         {
1497                 if (path == RF_PATH_A)
1498                 {
1499                         //path A APK
1500                         //load APK setting
1501                         //path-A
1502                         offset = rPdp_AntA;
1503                         for (index = 0; index < 11; index ++)
1504                         {
1505                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1506                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1507
1508                                 offset += 0x04;
1509                         }
1510
1511                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
1512
1513                         offset = rConfig_AntA;
1514                         for (; index < 13; index ++)
1515                         {
1516                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1517                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1518
1519                                 offset += 0x04;
1520                         }
1521
1522                         //page-B1
1523                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
1524
1525                         //path A
1526                         offset = rPdp_AntA;
1527                         for (index = 0; index < 16; index++)
1528                         {
1529                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
1530                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1531
1532                                 offset += 0x04;
1533                         }
1534                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
1535                 }
1536                 else if (path == RF_PATH_B)
1537                 {
1538                         //path B APK
1539                         //load APK setting
1540                         //path-B
1541                         offset = rPdp_AntB;
1542                         for (index = 0; index < 10; index ++)
1543                         {
1544                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1545                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1546
1547                                 offset += 0x04;
1548                         }
1549                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
1550
1551                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
1552
1553                         offset = rConfig_AntA;
1554                         index = 11;
1555                         for (; index < 13; index ++) //offset 0xb68, 0xb6c
1556                         {
1557                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1558                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1559
1560                                 offset += 0x04;
1561                         }
1562
1563                         //page-B1
1564                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
1565
1566                         //path B
1567                         offset = 0xb60;
1568                         for (index = 0; index < 16; index++)
1569                         {
1570                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
1571                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
1572
1573                                 offset += 0x04;
1574                         }
1575                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
1576                 }
1577
1578                 //save RF default value
1579                 regD[path] = PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask);
1580
1581                 //Path A AFE all on, path B AFE All off or vise versa
1582                 for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
1583                         PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
1584                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, 0xe70, bMaskDWord)));
1585
1586                 //BB to AP mode
1587                 if (path == 0)
1588                 {
1589                         for (index = 0; index < APK_BB_REG_NUM ; index++)
1590                         {
1591                                 if (index == 0)         //skip
1592                                         continue;
1593                                 else if (index < 5)
1594                                         PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
1595                                 else if (BB_REG[index] == 0x870)
1596                                         PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
1597                                 else
1598                                         PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0);
1599                         }
1600                         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1601                         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1602                 }
1603                 else            //path B
1604                 {
1605                         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
1606                         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
1607                 }
1608
1609                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord)));
1610
1611                 //MAC settings
1612                 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
1613
1614                 if (path == RF_PATH_A)  //Path B to standby mode
1615                 {
1616                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000);
1617                 }
1618                 else                    //Path A to standby mode
1619                 {
1620                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000);
1621                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
1622                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103);
1623                 }
1624
1625                 delta_offset = ((delta+14)/2);
1626                 if (delta_offset < 0)
1627                         delta_offset = 0;
1628                 else if (delta_offset > 12)
1629                         delta_offset = 12;
1630
1631                 //AP calibration
1632                 for (index = 0; index < APK_BB_REG_NUM; index++)
1633                 {
1634                         if (index != 1)         //only DO PA11+PAD01001, AP RF setting
1635                                 continue;
1636
1637                         tmpReg = APK_RF_init_value[path][index];
1638 #if 1
1639                         if (!pdmpriv->bAPKThermalMeterIgnore)
1640                         {
1641                                 BB_offset = (tmpReg & 0xF0000) >> 16;
1642
1643                                 if (!(tmpReg & BIT15)) //sign bit 0
1644                                 {
1645                                         BB_offset = -BB_offset;
1646                                 }
1647
1648                                 delta_V = APK_delta_mapping[index][delta_offset];
1649
1650                                 BB_offset += delta_V;
1651
1652                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() APK num %d delta_V %d delta_offset %d\n", index, delta_V, delta_offset));
1653
1654                                 if (BB_offset < 0)
1655                                 {
1656                                         tmpReg = tmpReg & (~BIT15);
1657                                         BB_offset = -BB_offset;
1658                                 }
1659                                 else
1660                                 {
1661                                         tmpReg = tmpReg | BIT15;
1662                                 }
1663                                 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
1664                         }
1665 #endif
1666
1667                                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_IPA_A, bRFRegOffsetMask, 0x8992e);
1668                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]);
1669                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg);
1670
1671                         // PA11+PAD01111, one shot
1672                         i = 0;
1673                         do
1674                         {
1675                                 PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80000000);
1676                                 {
1677                                         PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]);
1678                                         rtw_mdelay_os(3);
1679                                         PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]);
1680                                         #ifdef CONFIG_LONG_DELAY_ISSUE
1681                                         rtw_msleep_os(20);
1682                                         #else
1683                                         rtw_mdelay_os(20);
1684                                         #endif
1685                                 }
1686                                 PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
1687
1688                                 if (path == RF_PATH_A)
1689                                         tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000);
1690                                 else
1691                                         tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000);
1692
1693                                 i++;
1694                         }
1695                         while (tmpReg > apkbound && i < 4);
1696
1697                         APK_result[path][index] = tmpReg;
1698                 }
1699         }
1700
1701         //reload MAC default value
1702         _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
1703
1704         //reload BB default value
1705         for (index = 0; index < APK_BB_REG_NUM ; index++)
1706         {
1707                 if (index == 0)         //skip
1708                         continue;
1709                 PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]);
1710         }
1711
1712         //reload AFE default value
1713         _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
1714
1715         //reload RF path default value
1716         for (path = 0; path < pathbound; path++)
1717         {
1718                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]);
1719                 if (path == RF_PATH_B)
1720                 {
1721                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
1722                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101);
1723                 }
1724
1725                 //note no index == 0
1726                 if (APK_result[path][1] > 6)
1727                         APK_result[path][1] = 6;
1728                 //RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
1729         }
1730
1731         //RTPRINT(FINIT, INIT_IQK, ("\n"));
1732
1733
1734         for (path = 0; path < pathbound; path++)
1735         {
1736                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask,
1737                 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
1738                 if (path == RF_PATH_A)
1739                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
1740                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
1741                 else
1742                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
1743                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
1744                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask,
1745                 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
1746         }
1747
1748         pdmpriv->bAPKdone = true;
1749
1750         //RTPRINT(FINIT, INIT_IQK, ("<==PHY_APCalibrate()\n"));
1751 }
1752
1753 void
1754 rtl8192c_PHY_IQCalibrate(
1755         IN      PADAPTER        pAdapter,
1756         IN      bool            bReCovery
1757         )
1758 {
1759         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1760         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1761         s32                     result[4][8];   //last is final result
1762         u8                      i, final_candidate;
1763         bool            bPathAOK, bPathBOK;
1764         s32                     RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
1765         bool            is12simular, is13simular, is23simular;
1766         bool            bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
1767         u32                     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1768                                         rOFDM0_XARxIQImbalance,         rOFDM0_XBRxIQImbalance,
1769                                         rOFDM0_ECCAThreshold,   rOFDM0_AGCRSSITable,
1770                                         rOFDM0_XATxIQImbalance,         rOFDM0_XBTxIQImbalance,
1771                                         rOFDM0_XCTxAFE,                         rOFDM0_XDTxAFE,
1772                                         rOFDM0_RxIQExtAnta};
1773
1774
1775 #if MP_DRIVER == 1
1776         bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
1777         bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
1778         bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
1779 #endif
1780
1781         //ignore IQK when continuous Tx
1782         if (bStartContTx || bSingleTone || bCarrierSuppression)
1783                 return;
1784
1785 #if DISABLE_BB_RF
1786         return;
1787 #endif
1788
1789         if (bReCovery)
1790         {
1791                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
1792                 return;
1793         }
1794         DBG_8192C("IQK:Start!!!\n");
1795
1796         for (i = 0; i < 8; i++)
1797         {
1798                 result[0][i] = 0;
1799                 result[1][i] = 0;
1800                 result[2][i] = 0;
1801                 result[3][i] = 0;
1802         }
1803         final_candidate = 0xff;
1804         bPathAOK = false;
1805         bPathBOK = false;
1806         is12simular = false;
1807         is23simular = false;
1808         is13simular = false;
1809
1810         for (i=0; i<3; i++)
1811         {
1812                 if (IS_92C_SERIAL( pHalData->VersionID)) {
1813                          _PHY_IQCalibrate(pAdapter, result, i, true);
1814                 }
1815                 else {
1816                         // For 88C 1T1R
1817                         _PHY_IQCalibrate(pAdapter, result, i, false);
1818                 }
1819
1820                 if (i == 1)
1821                 {
1822                         is12simular = _PHY_SimularityCompare(pAdapter, result, 0, 1);
1823                         if (is12simular)
1824                         {
1825                                 final_candidate = 0;
1826                                 break;
1827                         }
1828                 }
1829
1830                 if (i == 2)
1831                 {
1832                         is13simular = _PHY_SimularityCompare(pAdapter, result, 0, 2);
1833                         if (is13simular)
1834                         {
1835                                 final_candidate = 0;
1836                                 break;
1837                         }
1838
1839                         is23simular = _PHY_SimularityCompare(pAdapter, result, 1, 2);
1840                         if (is23simular)
1841                                 final_candidate = 1;
1842                         else
1843                         {
1844                                 for (i = 0; i < 8; i++)
1845                                         RegTmp += result[3][i];
1846
1847                                 if (RegTmp != 0)
1848                                         final_candidate = 3;
1849                                 else
1850                                         final_candidate = 0xFF;
1851                         }
1852                 }
1853         }
1854
1855         for (i=0; i<4; i++)
1856         {
1857                 RegE94 = result[i][0];
1858                 RegE9C = result[i][1];
1859                 RegEA4 = result[i][2];
1860                 RegEAC = result[i][3];
1861                 RegEB4 = result[i][4];
1862                 RegEBC = result[i][5];
1863                 RegEC4 = result[i][6];
1864                 RegECC = result[i][7];
1865                 //RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%lx RegE9C=%lx RegEA4=%lx RegEAC=%lx RegEB4=%lx RegEBC=%lx RegEC4=%lx RegECC=%lx\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
1866         }
1867
1868         if (final_candidate != 0xff)
1869         {
1870                 pdmpriv->RegE94 = RegE94 = result[final_candidate][0];
1871                 pdmpriv->RegE9C = RegE9C = result[final_candidate][1];
1872                 RegEA4 = result[final_candidate][2];
1873                 RegEAC = result[final_candidate][3];
1874                 pdmpriv->RegEB4 = RegEB4 = result[final_candidate][4];
1875                 pdmpriv->RegEBC = RegEBC = result[final_candidate][5];
1876                 RegEC4 = result[final_candidate][6];
1877                 RegECC = result[final_candidate][7];
1878                 DBG_8192C("IQK: final_candidate is %x\n", final_candidate);
1879                 DBG_8192C("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC);
1880                 bPathAOK = bPathBOK = true;
1881         }
1882         else
1883         {
1884                 RegE94 = RegEB4 = pdmpriv->RegE94 = pdmpriv->RegEB4 = 0x100;    //X default value
1885                 RegE9C = RegEBC = pdmpriv->RegE9C = pdmpriv->RegEBC = 0x0;              //Y default value
1886         }
1887
1888         if ((RegE94 != 0)/*&&(RegEA4 != 0)*/)
1889                 _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
1890
1891         if (IS_92C_SERIAL( pHalData->VersionID)) {
1892                 if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
1893                 _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
1894         }
1895
1896         _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
1897
1898 }
1899
1900
1901 void
1902 rtl8192c_PHY_LCCalibrate(
1903         IN      PADAPTER        pAdapter
1904         )
1905 {
1906         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1907         struct mlme_ext_priv    *pmlmeext = &pAdapter->mlmeextpriv;
1908         bool            bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
1909
1910 #if MP_DRIVER == 1
1911         bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
1912         bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
1913         bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
1914 #endif
1915
1916 #if DISABLE_BB_RF
1917         return;
1918 #endif
1919
1920         //ignore IQK when continuous Tx
1921         if (bStartContTx || bSingleTone || bCarrierSuppression)
1922                 return;
1923
1924         if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
1925                 return;
1926
1927         if (IS_92C_SERIAL( pHalData->VersionID)) {
1928                 _PHY_LCCalibrate(pAdapter, true);
1929         }
1930         else {
1931                 // For 88C 1T1R
1932                 _PHY_LCCalibrate(pAdapter, false);
1933         }
1934 }
1935
1936 void rtl8192c_PHY_APCalibrate(PADAPTER pAdapter, char delta)
1937 {
1938         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1939         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1940
1941         //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
1942         return;
1943
1944 #if DISABLE_BB_RF
1945         return;
1946 #endif
1947
1948         if (pdmpriv->bAPKdone)
1949                 return;
1950
1951         if (IS_92C_SERIAL( pHalData->VersionID)) {
1952                 _PHY_APCalibrate(pAdapter, delta, true);
1953         }
1954         else {
1955                 // For 88C 1T1R
1956                 _PHY_APCalibrate(pAdapter, delta, false);
1957         }
1958 }