hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 //============================================================
  22 // include files
  23 //============================================================
  24
  25 #include "odm_precomp.h"
  26
  27
  28
  29 const u2Byte dB_Invert_Table[8][12] = {
  30         {       1,              1,              1,              2,              2,              2,              2,              3,              3,              3,              4,              4},
  31         {       4,              5,              6,              6,              7,              8,              9,              10,             11,             13,             14,             16},
  32         {       18,             20,             22,             25,             28,             32,             35,             40,             45,             50,             56,             63},
  33         {       71,             79,             89,             100,    112,    126,    141,    158,    178,    200,    224,    251},
  34         {       282,    316,    355,    398,    447,    501,    562,    631,    708,    794,    891,    1000},
  35         {       1122,   1259,   1413,   1585,   1778,   1995,   2239,   2512,   2818,   3162,   3548,   3981},
  36         {       4467,   5012,   5623,   6310,   7079,   7943,   8913,   10000,  11220,  12589,  14125,  15849},
  37         {       17783,  19953,  22387,  25119,  28184,  31623,  35481,  39811,  44668,  50119,  56234,  65535}};
  38
  39 // 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test.
  40 //u1Byte                        tmpNumBssDesc;
  41 //RT_WLAN_BSS   tmpbssDesc[MAX_BSS_DESC];
  42
  43 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
  44 static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
  45 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MARVELL         92U_AP          SELF_AP(DownLink/Tx)
  46 { 0x5e4322,             0xa44f,                 0x5e4322,               0x5ea32b,               0x5ea422,       0x5ea322,       0x3ea430,       0x5ea44f,       0x5e4322,       0x5e4322};
  47
  48
  49 static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
  50 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MARVELL         92U_AP          SELF_AP(UpLink/Rx)
  51 { 0xa44f,               0x5ea44f,       0x5e4322,               0x5ea42b,               0xa44f,                 0xa630,                 0x5ea630,       0xa44f,         0xa42b,         0xa42b};
  52
  53 static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
  54 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MARVELL         92U_AP          SELF_AP
  55 { 0x4322,               0xa44f,                 0x5e4322,               0xa42b,                         0x5e4322,       0x4322,                 0xa42b,         0xa44f,         0x5e4322,       0x5ea42b};
  56
  57
  58 //============================================================
  59 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
  60
  61
  62 //avoid to warn in FreeBSD ==> To DO modify
  63 u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
  64 {          // UL                        DL
  65         {0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP
  66         {0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP
  67         {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 2:unknown AP => realtek_92SE
  68         {0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP
  69         {0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP
  70         {0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP
  71         //{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP
  72         {0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP
  73         //{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP
  74         {0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP
  75         //{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP
  76         {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP
  77         {0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP
  78 //      {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP
  79 };
  80 //============================================================
  81 // EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22
  82 //============================================================
  83 #elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
  84 enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
  85
  86 static const struct ParaRecord rtl_ap_EDCA[] =
  87 {
  88 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
  89      {0,     7,      4,      10,     0},            //BK
  90      {0,     3,      4,      6,      0},             //BE
  91      {0,     1,      3,      4,      188},         //VI
  92      {0,     1,      2,      3,      102},         //VO
  93      {0,     1,      3,      4,      94},          //VI_AG
  94      {0,     1,      2,      3,      47},          //VO_AG
  95 };
  96
  97 static const struct ParaRecord rtl_sta_EDCA[] =
  98 {
  99 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
 100      {0,     7,      4,      10,     0},
 101      {0,     3,      4,      10,     0},
 102      {0,     2,      3,      4,      188},
 103      {0,     2,      2,      3,      102},
 104      {0,     2,      3,      4,      94},
 105      {0,     2,      2,      3,      47},
 106 };
 107 #endif
 108
 109 //============================================================
 110 // Global var
 111 //============================================================
 112 u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
 113         0x7f8001fe, // 0, +6.0dB
 114         0x788001e2, // 1, +5.5dB
 115         0x71c001c7, // 2, +5.0dB
 116         0x6b8001ae, // 3, +4.5dB
 117         0x65400195, // 4, +4.0dB
 118         0x5fc0017f, // 5, +3.5dB
 119         0x5a400169, // 6, +3.0dB
 120         0x55400155, // 7, +2.5dB
 121         0x50800142, // 8, +2.0dB
 122         0x4c000130, // 9, +1.5dB
 123         0x47c0011f, // 10, +1.0dB
 124         0x43c0010f, // 11, +0.5dB
 125         0x40000100, // 12, +0dB
 126         0x3c8000f2, // 13, -0.5dB
 127         0x390000e4, // 14, -1.0dB
 128         0x35c000d7, // 15, -1.5dB
 129         0x32c000cb, // 16, -2.0dB
 130         0x300000c0, // 17, -2.5dB
 131         0x2d4000b5, // 18, -3.0dB
 132         0x2ac000ab, // 19, -3.5dB
 133         0x288000a2, // 20, -4.0dB
 134         0x26000098, // 21, -4.5dB
 135         0x24000090, // 22, -5.0dB
 136         0x22000088, // 23, -5.5dB
 137         0x20000080, // 24, -6.0dB
 138         0x1e400079, // 25, -6.5dB
 139         0x1c800072, // 26, -7.0dB
 140         0x1b00006c, // 27. -7.5dB
 141         0x19800066, // 28, -8.0dB
 142         0x18000060, // 29, -8.5dB
 143         0x16c0005b, // 30, -9.0dB
 144         0x15800056, // 31, -9.5dB
 145         0x14400051, // 32, -10.0dB
 146         0x1300004c, // 33, -10.5dB
 147         0x12000048, // 34, -11.0dB
 148         0x11000044, // 35, -11.5dB
 149         0x10000040, // 36, -12.0dB
 150         0x0f00003c,// 37, -12.5dB
 151         0x0e400039,// 38, -13.0dB
 152         0x0d800036,// 39, -13.5dB
 153         0x0cc00033,// 40, -14.0dB
 154         0x0c000030,// 41, -14.5dB
 155         0x0b40002d,// 42, -15.0dB
 156 };
 157
 158
 159 u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
 160         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       // 0, +0dB
 161         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 1, -0.5dB
 162         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 2, -1.0dB
 163         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 3, -1.5dB
 164         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 4, -2.0dB
 165         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 5, -2.5dB
 166         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 6, -3.0dB
 167         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 7, -3.5dB
 168         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 8, -4.0dB
 169         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 9, -4.5dB
 170         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 10, -5.0dB
 171         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 11, -5.5dB
 172         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       // 12, -6.0dB
 173         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 13, -6.5dB
 174         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 14, -7.0dB
 175         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 15, -7.5dB
 176         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 177         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 17, -8.5dB
 178         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 18, -9.0dB
 179         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 19, -9.5dB
 180         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 20, -10.0dB
 181         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 21, -10.5dB
 182         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 22, -11.0dB
 183         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       // 23, -11.5dB
 184         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       // 24, -12.0dB
 185         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       // 25, -12.5dB
 186         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       // 26, -13.0dB
 187         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       // 27, -13.5dB
 188         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       // 28, -14.0dB
 189         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       // 29, -14.5dB
 190         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       // 30, -15.0dB
 191         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       // 31, -15.5dB
 192         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        // 32, -16.0dB
 193 };
 194
 195
 196 u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
 197         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       // 0, +0dB
 198         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 1, -0.5dB
 199         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 2, -1.0dB
 200         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 3, -1.5dB
 201         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 4, -2.0dB
 202         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 5, -2.5dB
 203         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 6, -3.0dB
 204         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 7, -3.5dB
 205         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 8, -4.0dB
 206         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 9, -4.5dB
 207         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 10, -5.0dB
 208         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 11, -5.5dB
 209         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 12, -6.0dB
 210         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 13, -6.5dB
 211         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 14, -7.0dB
 212         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 15, -7.5dB
 213         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 214         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 17, -8.5dB
 215         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 18, -9.0dB
 216         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 19, -9.5dB
 217         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 20, -10.0dB
 218         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 21, -10.5dB
 219         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 22, -11.0dB
 220         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 23, -11.5dB
 221         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 24, -12.0dB
 222         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       // 25, -12.5dB
 223         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 26, -13.0dB
 224         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 27, -13.5dB
 225         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 28, -14.0dB
 226         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 29, -14.5dB
 227         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 30, -15.0dB
 228         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 31, -15.5dB
 229         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        // 32, -16.0dB
 230 };
 231
 232
 233 #ifdef AP_BUILD_WORKAROUND
 234
 235 unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
 236         /*  +6.0dB */ 0x7f8001fe,
 237         /*  +5.5dB */ 0x788001e2,
 238         /*  +5.0dB */ 0x71c001c7,
 239         /*  +4.5dB */ 0x6b8001ae,
 240         /*  +4.0dB */ 0x65400195,
 241         /*  +3.5dB */ 0x5fc0017f,
 242         /*  +3.0dB */ 0x5a400169,
 243         /*  +2.5dB */ 0x55400155,
 244         /*  +2.0dB */ 0x50800142,
 245         /*  +1.5dB */ 0x4c000130,
 246         /*  +1.0dB */ 0x47c0011f,
 247         /*  +0.5dB */ 0x43c0010f,
 248         /*   0.0dB */ 0x40000100,
 249         /*  -0.5dB */ 0x3c8000f2,
 250         /*  -1.0dB */ 0x390000e4,
 251         /*  -1.5dB */ 0x35c000d7,
 252         /*  -2.0dB */ 0x32c000cb,
 253         /*  -2.5dB */ 0x300000c0,
 254         /*  -3.0dB */ 0x2d4000b5,
 255         /*  -3.5dB */ 0x2ac000ab,
 256         /*  -4.0dB */ 0x288000a2,
 257         /*  -4.5dB */ 0x26000098,
 258         /*  -5.0dB */ 0x24000090,
 259         /*  -5.5dB */ 0x22000088,
 260         /*  -6.0dB */ 0x20000080,
 261         /*  -6.5dB */ 0x1a00006c,
 262         /*  -7.0dB */ 0x1c800072,
 263         /*  -7.5dB */ 0x18000060,
 264         /*  -8.0dB */ 0x19800066,
 265         /*  -8.5dB */ 0x15800056,
 266         /*  -9.0dB */ 0x26c0005b,
 267         /*  -9.5dB */ 0x14400051,
 268         /* -10.0dB */ 0x24400051,
 269         /* -10.5dB */ 0x1300004c,
 270         /* -11.0dB */ 0x12000048,
 271         /* -11.5dB */ 0x11000044,
 272         /* -12.0dB */ 0x10000040
 273 };
 274 #endif
 275
 276 //============================================================
 277 // Local Function predefine.
 278 //============================================================
 279
 280 //START------------COMMON INFO RELATED---------------//
 281 void
 282 odm_CommonInfoSelfInit(
 283                 PDM_ODM_T               pDM_Odm
 284         );
 285
 286 void
 287 odm_CommonInfoSelfUpdate(
 288                 PDM_ODM_T               pDM_Odm
 289         );
 290
 291 void
 292 odm_CmnInfoInit_Debug(
 293                 PDM_ODM_T               pDM_Odm
 294         );
 295
 296 void
 297 odm_CmnInfoHook_Debug(
 298                 PDM_ODM_T               pDM_Odm
 299         );
 300
 301 void
 302 odm_CmnInfoUpdate_Debug(
 303                 PDM_ODM_T               pDM_Odm
 304         );
 305 /*
 306 void
 307 odm_FindMinimumRSSI(
 308                 PDM_ODM_T               pDM_Odm
 309         );
 310
 311 void
 312 odm_IsLinked(
 313                 PDM_ODM_T               pDM_Odm
 314         );
 315 */
 316 //END------------COMMON INFO RELATED---------------//
 317
 318 //START---------------DIG---------------------------//
 319 void
 320 odm_FalseAlarmCounterStatistics(
 321                 PDM_ODM_T               pDM_Odm
 322         );
 323
 324 void
 325 odm_DIGInit(
 326                 PDM_ODM_T               pDM_Odm
 327         );
 328
 329 void
 330 odm_DIG(
 331                 PDM_ODM_T               pDM_Odm
 332         );
 333
 334 void
 335 odm_CCKPacketDetectionThresh(
 336                 PDM_ODM_T               pDM_Odm
 337         );
 338 //END---------------DIG---------------------------//
 339
 340 //START-------BB POWER SAVE-----------------------//
 341 void
 342 odm_DynamicBBPowerSavingInit(
 343                 PDM_ODM_T               pDM_Odm
 344         );
 345
 346 void
 347 odm_DynamicBBPowerSaving(
 348                 PDM_ODM_T               pDM_Odm
 349         );
 350
 351 void
 352 odm_1R_CCA(
 353                 PDM_ODM_T               pDM_Odm
 354         );
 355 //END---------BB POWER SAVE-----------------------//
 356
 357 //START-----------------PSD-----------------------//
 358 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP))
 359 //============================================================
 360 // Function predefine.
 361 //============================================================
 362 void    odm_PathDiversityInit_92C(      PADAPTER        Adapter);
 363 void    odm_2TPathDiversityInit_92C(    PADAPTER        Adapter);
 364 void    odm_1TPathDiversityInit_92C(    PADAPTER        Adapter);
 365 bool    odm_IsConnected_92C(PADAPTER    Adapter);
 366 void    odm_PathDiversityAfterLink_92C( PADAPTER        Adapter);
 367
 368 void
 369 odm_CCKTXPathDiversityCallback(
 370         PRT_TIMER               pTimer
 371         );
 372
 373 void
 374 odm_CCKTXPathDiversityWorkItemCallback(
 375     void *            pContext
 376     );
 377
 378 void
 379 odm_PathDivChkAntSwitchCallback(
 380         PRT_TIMER               pTimer
 381         );
 382
 383 void
 384 odm_PathDivChkAntSwitchWorkitemCallback(
 385     void *            pContext
 386     );
 387
 388 void    odm_SetRespPath_92C(            PADAPTER        Adapter,        u1Byte  DefaultRespPath);
 389 void    odm_OFDMTXPathDiversity_92C(    PADAPTER        Adapter);
 390 void    odm_CCKTXPathDiversity_92C(     PADAPTER        Adapter);
 391 void    odm_ResetPathDiversity_92C(             PADAPTER        Adapter);
 392
 393 //Start-------------------- RX High Power------------------------//
 394 void    odm_RXHPInit(           PDM_ODM_T               pDM_Odm);
 395 void    odm_RXHP(               PDM_ODM_T               pDM_Odm);
 396 void    odm_Write_RXHP( PDM_ODM_T       pDM_Odm);
 397
 398 void    odm_PSD_RXHP(           PDM_ODM_T       pDM_Odm);
 399 void    odm_PSD_RXHPCallback(   PRT_TIMER               pTimer);
 400 void    odm_PSD_RXHPWorkitemCallback(   void *            pContext);
 401 //End--------------------- RX High Power -----------------------//
 402
 403 void
 404 odm_PathDivInit(        PDM_ODM_T       pDM_Odm);
 405
 406 void
 407 odm_SetRespPath_92C(
 408         PADAPTER        Adapter,
 409         u1Byte  DefaultRespPath
 410         );
 411
 412 #endif
 413 //END-------------------PSD-----------------------//
 414
 415 void
 416 odm_RefreshRateAdaptiveMaskMP(
 417                 PDM_ODM_T               pDM_Odm
 418         );
 419
 420 void
 421 odm_RefreshRateAdaptiveMaskCE(
 422                 PDM_ODM_T               pDM_Odm
 423         );
 424
 425 void
 426 odm_RefreshRateAdaptiveMaskAPADSL(
 427                 PDM_ODM_T               pDM_Odm
 428         );
 429
 430 void
 431 odm_DynamicTxPowerInit(
 432                 PDM_ODM_T               pDM_Odm
 433         );
 434
 435 void
 436 odm_DynamicTxPowerRestorePowerIndex(
 437         PDM_ODM_T       pDM_Odm
 438         );
 439
 440 void
 441 odm_DynamicTxPowerNIC(
 442         PDM_ODM_T       pDM_Odm
 443         );
 444
 445 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
 446 void
 447 odm_DynamicTxPowerSavePowerIndex(
 448                 PDM_ODM_T               pDM_Odm
 449         );
 450
 451 void
 452 odm_DynamicTxPowerWritePowerIndex(
 453         PDM_ODM_T       pDM_Odm,
 454         u1Byte          Value);
 455
 456 void
 457 odm_DynamicTxPower_92C(
 458         PDM_ODM_T       pDM_Odm
 459         );
 460
 461 void
 462 odm_DynamicTxPower_92D(
 463         PDM_ODM_T       pDM_Odm
 464         );
 465 #endif
 466
 467
 468 void
 469 odm_RSSIMonitorInit(
 470         PDM_ODM_T       pDM_Odm
 471         );
 472
 473 void
 474 odm_RSSIMonitorCheckMP(
 475         PDM_ODM_T       pDM_Odm
 476         );
 477
 478 void
 479 odm_RSSIMonitorCheckCE(
 480                 PDM_ODM_T               pDM_Odm
 481         );
 482 void
 483 odm_RSSIMonitorCheckAP(
 484                 PDM_ODM_T               pDM_Odm
 485         );
 486
 487
 488
 489 void
 490 odm_RSSIMonitorCheck(
 491                 PDM_ODM_T               pDM_Odm
 492         );
 493 void
 494 odm_DynamicTxPower(
 495                 PDM_ODM_T               pDM_Odm
 496         );
 497
 498 void
 499 odm_DynamicTxPowerAP(
 500                 PDM_ODM_T               pDM_Odm
 501         );
 502
 503
 504 void
 505 odm_SwAntDivInit(
 506                 PDM_ODM_T               pDM_Odm
 507         );
 508
 509 void
 510 odm_SwAntDivInit_NIC(
 511                 PDM_ODM_T               pDM_Odm
 512         );
 513
 514 void
 515 odm_SwAntDivChkAntSwitch(
 516                 PDM_ODM_T               pDM_Odm,
 517                 u1Byte                  Step
 518         );
 519
 520 void
 521 odm_SwAntDivChkAntSwitchNIC(
 522                 PDM_ODM_T               pDM_Odm,
 523                 u1Byte          Step
 524         );
 525
 526
 527 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
 528 void
 529 odm_SwAntDivChkAntSwitchCallback(
 530         PRT_TIMER               pTimer
 531 );
 532 void
 533 odm_SwAntDivChkAntSwitchWorkitemCallback(
 534     void *            pContext
 535     );
 536 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
 537 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 538 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 539 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 540 #endif
 541
 542
 543
 544 void
 545 odm_GlobalAdapterCheck(
 546                 void
 547         );
 548
 549 void
 550 odm_RefreshRateAdaptiveMask(
 551                 PDM_ODM_T               pDM_Odm
 552         );
 553
 554 void
 555 ODM_TXPowerTrackingCheck(
 556                 PDM_ODM_T               pDM_Odm
 557         );
 558
 559 void
 560 odm_TXPowerTrackingCheckAP(
 561                 PDM_ODM_T               pDM_Odm
 562         );
 563
 564
 565
 566
 567
 568
 569
 570 void
 571 odm_RateAdaptiveMaskInit(
 572         PDM_ODM_T       pDM_Odm
 573         );
 574
 575 void
 576 odm_TXPowerTrackingThermalMeterInit(
 577         PDM_ODM_T       pDM_Odm
 578         );
 579
 580
 581 void
 582 odm_TXPowerTrackingInit(
 583         PDM_ODM_T       pDM_Odm
 584         );
 585
 586 void
 587 odm_TXPowerTrackingCheckMP(
 588         PDM_ODM_T       pDM_Odm
 589         );
 590
 591
 592 void
 593 odm_TXPowerTrackingCheckCE(
 594         PDM_ODM_T       pDM_Odm
 595         );
 596
 597 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP))
 598
 599 void
 600 ODM_RateAdaptiveStateApInit(
 601         PADAPTER        Adapter ,
 602         PRT_WLAN_STA  pEntry
 603         );
 604
 605 void
 606 odm_TXPowerTrackingCallbackThermalMeter92C(
 607             PADAPTER    Adapter
 608             );
 609
 610 void
 611 odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
 612         PADAPTER        Adapter
 613         );
 614
 615 void
 616 odm_TXPowerTrackingCallbackThermalMeter92D(
 617             PADAPTER    Adapter
 618             );
 619
 620 void
 621 odm_TXPowerTrackingDirectCall92C(
 622             PADAPTER            Adapter
 623             );
 624
 625 void
 626 odm_TXPowerTrackingThermalMeterCheck(
 627         PADAPTER                Adapter
 628         );
 629
 630 #endif
 631
 632 void
 633 odm_EdcaTurboCheck(
 634                 PDM_ODM_T               pDM_Odm
 635         );
 636 void
 637 ODM_EdcaTurboInit(
 638         PDM_ODM_T               pDM_Odm
 639 );
 640
 641 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
 642 void
 643 odm_EdcaTurboCheckMP(
 644                 PDM_ODM_T               pDM_Odm
 645         );
 646
 647 //check if edca turbo is disabled
 648 bool
 649 odm_IsEdcaTurboDisable(
 650         PDM_ODM_T       pDM_Odm
 651 );
 652 //choose edca paramter for special IOT case
 653 void
 654 ODM_EdcaParaSelByIot(
 655         PDM_ODM_T       pDM_Odm,
 656         u4Byte          *EDCA_BE_UL,
 657         u4Byte          *EDCA_BE_DL
 658         );
 659 //check if it is UL or DL
 660 void
 661 odm_EdcaChooseTrafficIdx(
 662         PDM_ODM_T       pDM_Odm,
 663         u8Byte          cur_tx_bytes,
 664         u8Byte          cur_rx_bytes,
 665         bool            bBiasOnRx,
 666         bool            *pbIsCurRDLState
 667         );
 668
 669 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
 670 void
 671 odm_EdcaTurboCheckCE(
 672                 PDM_ODM_T               pDM_Odm
 673         );
 674 #else
 675 void
 676 odm_IotEngine(
 677         PDM_ODM_T       pDM_Odm
 678         );
 679
 680 void
 681 odm_EdcaParaInit(
 682         PDM_ODM_T       pDM_Odm
 683         );
 684 #endif
 685
 686
 687
 688 #define         RxDefaultAnt1           0x65a9
 689 #define RxDefaultAnt2           0x569a
 690
 691 void
 692 odm_InitHybridAntDiv(
 693         PDM_ODM_T       pDM_Odm
 694         );
 695
 696 bool
 697 odm_StaDefAntSel(
 698         PDM_ODM_T       pDM_Odm,
 699         u4Byte  OFDM_Ant1_Cnt,
 700         u4Byte  OFDM_Ant2_Cnt,
 701         u4Byte  CCK_Ant1_Cnt,
 702         u4Byte  CCK_Ant2_Cnt,
 703         u1Byte          *pDefAnt
 704         );
 705
 706 void
 707 odm_SetRxIdleAnt(
 708         PDM_ODM_T       pDM_Odm,
 709         u1Byte  Ant,
 710           bool   bDualPath
 711 );
 712
 713
 714
 715 void odm_HwAntDiv(PDM_ODM_T     pDM_Odm);
 716
 717 //============================================================
 718 //3 Export Interface
 719 //============================================================
 720
 721 //
 722 // 2011/09/21 MH Add to describe different team necessary resource allocate??
 723 //
 724 void
 725 ODM_DMInit(
 726                 PDM_ODM_T               pDM_Odm
 727         )
 728 {
 729
 730 #if (FPGA_TWO_MAC_VERIFICATION == 1)
 731         odm_RateAdaptiveMaskInit(pDM_Odm);
 732         return;
 733 #endif
 734
 735         //2012.05.03 Luke: For all IC series
 736         odm_CommonInfoSelfInit(pDM_Odm);
 737         odm_CmnInfoInit_Debug(pDM_Odm);
 738         odm_DIGInit(pDM_Odm);
 739         odm_RateAdaptiveMaskInit(pDM_Odm);
 740
 741         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 742         {
 743
 744         }
 745         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 746         {
 747                 #if (RTL8188E_SUPPORT == 1)
 748                 odm_PrimaryCCA_Init(pDM_Odm);    // Gary
 749                 #endif
 750                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 751                 odm_DynamicTxPowerInit(pDM_Odm);
 752                 odm_TXPowerTrackingInit(pDM_Odm);
 753                 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
 754              odm_PSDMonitorInit(pDM_Odm);
 755                 odm_RXHPInit(pDM_Odm);
 756                 odm_PathDivInit(pDM_Odm); //92D Path Div Init   //Neil Chen
 757                 #endif
 758                 ODM_EdcaTurboInit(pDM_Odm);
 759                 #if (RTL8188E_SUPPORT == 1)
 760                 ODM_RAInfo_Init_all(pDM_Odm);
 761                 #endif
 762                 if (    ( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV )     ||
 763                         ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV )    ||
 764                         ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV ))
 765                 {
 766                         odm_InitHybridAntDiv(pDM_Odm);
 767                 }
 768                 else if ( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 769                 {
 770                         odm_SwAntDivInit(pDM_Odm);
 771                 }
 772         }
 773 }
 774
 775 //
 776 // 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
 777 // You can not add any dummy function here, be care, you can only use DM structure
 778 // to perform any new ODM_DM.
 779 //
 780 void
 781 ODM_DMWatchdog(
 782                 PDM_ODM_T               pDM_Odm
 783         )
 784 {
 785         //2012.05.03 Luke: For all IC series
 786         odm_GlobalAdapterCheck();
 787         odm_CmnInfoHook_Debug(pDM_Odm);
 788         odm_CmnInfoUpdate_Debug(pDM_Odm);
 789         odm_CommonInfoSelfUpdate(pDM_Odm);
 790         odm_FalseAlarmCounterStatistics(pDM_Odm);
 791         odm_RSSIMonitorCheck(pDM_Odm);
 792
 793 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 794         //8723A or 8189ES platform
 795         //NeilChen--2012--08--24--
 796         //Fix Leave LPS issue
 797         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&// in LPS mode
 798             ((pDM_Odm->SupportICType & (ODM_RTL8723A ) )||
 799             (pDM_Odm->SupportICType & (ODM_RTL8188E) &&((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO))))) {
 800                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
 801                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 802                         odm_DIGbyRSSI_LPS(pDM_Odm);
 803         } else
 804 #endif
 805         {
 806                 odm_DIG(pDM_Odm);
 807         }
 808
 809
 810         odm_CCKPacketDetectionThresh(pDM_Odm);
 811
 812         if (*(pDM_Odm->pbPowerSaving)==true)
 813                 return;
 814
 815         odm_RefreshRateAdaptiveMask(pDM_Odm);
 816
 817         #if (RTL8192D_SUPPORT == 1)
 818         ODM_DynamicEarlyMode(pDM_Odm);
 819         #endif
 820         odm_DynamicBBPowerSaving(pDM_Odm);
 821         #if (RTL8188E_SUPPORT == 1)
 822         odm_DynamicPrimaryCCA(pDM_Odm);
 823         #endif
 824         if (    ( pDM_Odm->AntDivType ==  CG_TRX_HW_ANTDIV )    ||
 825                 ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV )    ||
 826                 ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV ))
 827         {
 828                 odm_HwAntDiv(pDM_Odm);
 829         }
 830         else if ( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 831         {
 832                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
 833         }
 834
 835         if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 836         {
 837
 838         }
 839         else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 840         {
 841                 ODM_TXPowerTrackingCheck(pDM_Odm);
 842               odm_EdcaTurboCheck(pDM_Odm);
 843                 odm_DynamicTxPower(pDM_Odm);
 844                 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
 845                 odm_RXHP(pDM_Odm);
 846                 #endif
 847         }
 848 }
 849
 850
 851 //
 852 // Init /.. Fixed HW value. Only init time.
 853 //
 854 void
 855 ODM_CmnInfoInit(
 856                 PDM_ODM_T               pDM_Odm,
 857                 ODM_CMNINFO_E   CmnInfo,
 858                 u4Byte                  Value
 859         )
 860 {
 861         //ODM_RT_TRACE(pDM_Odm,);
 862
 863         //
 864         // This section is used for init value
 865         //
 866         switch  (CmnInfo)
 867         {
 868                 //
 869                 // Fixed ODM value.
 870                 //
 871                 case    ODM_CMNINFO_ABILITY:
 872                         pDM_Odm->SupportAbility = (u4Byte)Value;
 873                         break;
 874                 case    ODM_CMNINFO_PLATFORM:
 875                         pDM_Odm->SupportPlatform = (u1Byte)Value;
 876                         break;
 877
 878                 case    ODM_CMNINFO_INTERFACE:
 879                         pDM_Odm->SupportInterface = (u1Byte)Value;
 880                         break;
 881
 882                 case    ODM_CMNINFO_MP_TEST_CHIP:
 883                         pDM_Odm->bIsMPChip= (u1Byte)Value;
 884                         break;
 885
 886                 case    ODM_CMNINFO_IC_TYPE:
 887                         pDM_Odm->SupportICType = Value;
 888                         break;
 889
 890                 case    ODM_CMNINFO_CUT_VER:
 891                         pDM_Odm->CutVersion = (u1Byte)Value;
 892                         break;
 893
 894                 case    ODM_CMNINFO_FAB_VER:
 895                         pDM_Odm->FabVersion = (u1Byte)Value;
 896                         break;
 897
 898                 case    ODM_CMNINFO_RF_TYPE:
 899                         pDM_Odm->RFType = (u1Byte)Value;
 900                         break;
 901
 902                 case    ODM_CMNINFO_RF_ANTENNA_TYPE:
 903                         pDM_Odm->AntDivType= (u1Byte)Value;
 904                         break;
 905
 906                 case    ODM_CMNINFO_BOARD_TYPE:
 907                         pDM_Odm->BoardType = (u1Byte)Value;
 908                         break;
 909
 910                 case    ODM_CMNINFO_EXT_LNA:
 911                         pDM_Odm->ExtLNA = (u1Byte)Value;
 912                         break;
 913
 914                 case    ODM_CMNINFO_EXT_PA:
 915                         pDM_Odm->ExtPA = (u1Byte)Value;
 916                         break;
 917
 918                 case    ODM_CMNINFO_EXT_TRSW:
 919                         pDM_Odm->ExtTRSW = (u1Byte)Value;
 920                         break;
 921                 case    ODM_CMNINFO_PATCH_ID:
 922                         pDM_Odm->PatchID = (u1Byte)Value;
 923                         break;
 924                 case    ODM_CMNINFO_BINHCT_TEST:
 925                         pDM_Odm->bInHctTest = (bool)Value;
 926                         break;
 927                 case    ODM_CMNINFO_BWIFI_TEST:
 928                         pDM_Odm->bWIFITest = (bool)Value;
 929                         break;
 930
 931                 case    ODM_CMNINFO_SMART_CONCURRENT:
 932                         pDM_Odm->bDualMacSmartConcurrent = (bool )Value;
 933                         break;
 934
 935                 //To remove the compiler warning, must add an empty default statement to handle the other values.
 936                 default:
 937                         //do nothing
 938                         break;
 939
 940         }
 941
 942         //
 943         // Tx power tracking BB swing table.
 944         // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB
 945         //
 946         pDM_Odm->BbSwingIdxOfdm                 = 12; // Set defalut value as index 12.
 947         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 948         pDM_Odm->BbSwingFlagOfdm                = false;
 949
 950 }
 951
 952
 953 void
 954 ODM_CmnInfoHook(
 955                 PDM_ODM_T               pDM_Odm,
 956                 ODM_CMNINFO_E   CmnInfo,
 957                 void *                  pValue
 958         )
 959 {
 960         //
 961         // Hook call by reference pointer.
 962         //
 963         switch  (CmnInfo)
 964         {
 965                 //
 966                 // Dynamic call by reference pointer.
 967                 //
 968                 case    ODM_CMNINFO_MAC_PHY_MODE:
 969                         pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
 970                         break;
 971
 972                 case    ODM_CMNINFO_TX_UNI:
 973                         pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue;
 974                         break;
 975
 976                 case    ODM_CMNINFO_RX_UNI:
 977                         pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue;
 978                         break;
 979
 980                 case    ODM_CMNINFO_WM_MODE:
 981                         pDM_Odm->pWirelessMode = (u1Byte *)pValue;
 982                         break;
 983
 984                 case    ODM_CMNINFO_BAND:
 985                         pDM_Odm->pBandType = (u1Byte *)pValue;
 986                         break;
 987
 988                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
 989                         pDM_Odm->pSecChOffset = (u1Byte *)pValue;
 990                         break;
 991
 992                 case    ODM_CMNINFO_SEC_MODE:
 993                         pDM_Odm->pSecurity = (u1Byte *)pValue;
 994                         break;
 995
 996                 case    ODM_CMNINFO_BW:
 997                         pDM_Odm->pBandWidth = (u1Byte *)pValue;
 998                         break;
 999
1000                 case    ODM_CMNINFO_CHNL:
1001                         pDM_Odm->pChannel = (u1Byte *)pValue;
1002                         break;
1003
1004                 case    ODM_CMNINFO_DMSP_GET_VALUE:
1005                         pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
1006                         break;
1007
1008                 case    ODM_CMNINFO_BUDDY_ADAPTOR:
1009                         pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue;
1010                         break;
1011
1012                 case    ODM_CMNINFO_DMSP_IS_MASTER:
1013                         pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
1014                         break;
1015
1016                 case    ODM_CMNINFO_SCAN:
1017                         pDM_Odm->pbScanInProcess = (bool *)pValue;
1018                         break;
1019
1020                 case    ODM_CMNINFO_POWER_SAVING:
1021                         pDM_Odm->pbPowerSaving = (bool *)pValue;
1022                         break;
1023
1024                 case    ODM_CMNINFO_ONE_PATH_CCA:
1025                         pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
1026                         break;
1027
1028                 case    ODM_CMNINFO_DRV_STOP:
1029                         pDM_Odm->pbDriverStopped =  (bool *)pValue;
1030                         break;
1031
1032                 case    ODM_CMNINFO_PNP_IN:
1033                         pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (bool *)pValue;
1034                         break;
1035
1036                 case    ODM_CMNINFO_INIT_ON:
1037                         pDM_Odm->pinit_adpt_in_progress =  (bool *)pValue;
1038                         break;
1039
1040                 case    ODM_CMNINFO_ANT_TEST:
1041                         pDM_Odm->pAntennaTest =  (u1Byte *)pValue;
1042                         break;
1043
1044                 case    ODM_CMNINFO_NET_CLOSED:
1045                         pDM_Odm->pbNet_closed = (bool *)pValue;
1046                         break;
1047                 case    ODM_CMNINFO_MP_MODE:
1048                         pDM_Odm->mp_mode = (u1Byte *)pValue;
1049                         break;
1050
1051                 //case  ODM_CMNINFO_BT_COEXIST:
1052                 //      pDM_Odm->BTCoexist = (bool *)pValue;
1053
1054                 //case  ODM_CMNINFO_STA_STATUS:
1055                         //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue;
1056                         //break;
1057
1058                 //case  ODM_CMNINFO_PHY_STATUS:
1059                 //      pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue;
1060                 //      break;
1061
1062                 //case  ODM_CMNINFO_MAC_STATUS:
1063                 //      pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue;
1064                 //      break;
1065                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1066                 default:
1067                         //do nothing
1068                         break;
1069
1070         }
1071
1072 }
1073
1074
1075 void
1076 ODM_CmnInfoPtrArrayHook(
1077                 PDM_ODM_T               pDM_Odm,
1078                 ODM_CMNINFO_E   CmnInfo,
1079                 u2Byte                  Index,
1080                 void *                  pValue
1081         )
1082 {
1083         //
1084         // Hook call by reference pointer.
1085         //
1086         switch  (CmnInfo)
1087         {
1088                 //
1089                 // Dynamic call by reference pointer.
1090                 //
1091                 case    ODM_CMNINFO_STA_STATUS:
1092                         pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue;
1093                         break;
1094                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1095                 default:
1096                         //do nothing
1097                         break;
1098         }
1099
1100 }
1101
1102
1103 //
1104 // Update Band/CHannel/.. The values are dynamic but non-per-packet.
1105 //
1106 void
1107 ODM_CmnInfoUpdate(
1108                 PDM_ODM_T               pDM_Odm,
1109                 u4Byte                  CmnInfo,
1110                 u8Byte                  Value
1111         )
1112 {
1113         //
1114         // This init variable may be changed in run time.
1115         //
1116         switch  (CmnInfo)
1117         {
1118                 case    ODM_CMNINFO_ABILITY:
1119                         pDM_Odm->SupportAbility = (u4Byte)Value;
1120                         break;
1121
1122                 case    ODM_CMNINFO_RF_TYPE:
1123                         pDM_Odm->RFType = (u1Byte)Value;
1124                         break;
1125
1126                 case    ODM_CMNINFO_WIFI_DIRECT:
1127                         pDM_Odm->bWIFI_Direct = (bool)Value;
1128                         break;
1129
1130                 case    ODM_CMNINFO_WIFI_DISPLAY:
1131                         pDM_Odm->bWIFI_Display = (bool)Value;
1132                         break;
1133
1134                 case    ODM_CMNINFO_LINK:
1135                         pDM_Odm->bLinked = (bool)Value;
1136                         break;
1137
1138                 case    ODM_CMNINFO_RSSI_MIN:
1139                         pDM_Odm->RSSI_Min= (u1Byte)Value;
1140                         break;
1141
1142                 case    ODM_CMNINFO_DBG_COMP:
1143                         pDM_Odm->DebugComponents = Value;
1144                         break;
1145
1146                 case    ODM_CMNINFO_DBG_LEVEL:
1147                         pDM_Odm->DebugLevel = (u4Byte)Value;
1148                         break;
1149                 case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
1150                         pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
1151                         break;
1152
1153                 case    ODM_CMNINFO_RA_THRESHOLD_LOW:
1154                         pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
1155                         break;
1156 #if (BT_30_SUPPORT == 1)
1157                 // The following is for BT HS mode and BT coexist mechanism.
1158                 case ODM_CMNINFO_BT_DISABLED:
1159                         pDM_Odm->bBtDisabled = (bool)Value;
1160                         break;
1161
1162                 case    ODM_CMNINFO_BT_OPERATION:
1163                         pDM_Odm->bBtHsOperation = (bool)Value;
1164                         break;
1165
1166                 case ODM_CMNINFO_BT_DIG:
1167                         pDM_Odm->btHsDigVal = (u1Byte)Value;
1168                         break;
1169
1170                 case    ODM_CMNINFO_BT_BUSY:
1171                         pDM_Odm->bBtBusy = (bool)Value;
1172                         break;
1173
1174                 case    ODM_CMNINFO_BT_DISABLE_EDCA:
1175                         pDM_Odm->bBtDisableEdcaTurbo = (bool)Value;
1176                         break;
1177 #endif
1178
1179         }
1180
1181
1182 }
1183
1184 void
1185 odm_CommonInfoSelfInit(
1186                 PDM_ODM_T               pDM_Odm
1187         )
1188 {
1189         pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
1190         pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
1191 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
1192         pDM_Odm->pbNet_closed = &pDM_Odm->bool_temp;
1193 #endif
1194         if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
1195         {
1196 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
1197                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1198 #elif (defined(CONFIG_SW_ANTENNA_DIVERSITY))
1199                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
1200 #endif
1201         }
1202         if (pDM_Odm->SupportICType & (ODM_RTL8723A))
1203                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
1204
1205         ODM_InitDebugSetting(pDM_Odm);
1206 }
1207
1208 void
1209 odm_CommonInfoSelfUpdate(
1210                 PDM_ODM_T               pDM_Odm
1211         )
1212 {
1213         u1Byte  EntryCnt=0;
1214         u1Byte  i;
1215         PSTA_INFO_T     pEntry;
1216
1217 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
1218
1219         PADAPTER        Adapter =  pDM_Odm->Adapter;
1220         PMGNT_INFO      pMgntInfo = &Adapter->MgntInfo;
1221
1222         pEntry = pDM_Odm->pODM_StaInfo[0];
1223         if (pMgntInfo->mAssoc)
1224         {
1225                 pEntry->bUsed=true;
1226                 for (i=0; i<6; i++)
1227                         pEntry->MacAddr[i] = pMgntInfo->Bssid[i];
1228         }
1229         else
1230         {
1231                 pEntry->bUsed=false;
1232                 for (i=0; i<6; i++)
1233                         pEntry->MacAddr[i] = 0;
1234         }
1235 #endif
1236
1237
1238         if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1239         {
1240                 if (*(pDM_Odm->pSecChOffset) == 1)
1241                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2;
1242                 else if (*(pDM_Odm->pSecChOffset) == 2)
1243                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2;
1244         }
1245         else
1246                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
1247
1248         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1249         {
1250                 pEntry = pDM_Odm->pODM_StaInfo[i];
1251                 if (IS_STA_VALID(pEntry))
1252                         EntryCnt++;
1253         }
1254         if (EntryCnt == 1)
1255                 pDM_Odm->bOneEntryOnly = true;
1256         else
1257                 pDM_Odm->bOneEntryOnly = false;
1258 }
1259
1260 void
1261 odm_CmnInfoInit_Debug(
1262                 PDM_ODM_T               pDM_Odm
1263         )
1264 {
1265         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
1266         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) );
1267         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) );
1268         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) );
1269         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) );
1270         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) );
1271         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) );
1272         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) );
1273         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) );
1274         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) );
1275         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) );
1276         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) );
1277         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) );
1278         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) );
1279         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) );
1280         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) );
1281
1282 }
1283
1284 void
1285 odm_CmnInfoHook_Debug(
1286                 PDM_ODM_T               pDM_Odm
1287         )
1288 {
1289         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
1290         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) );
1291         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) );
1292         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) );
1293         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) );
1294         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) );
1295         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) );
1296         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) );
1297
1298 #if (RTL8192D_SUPPORT==1)
1299         if (pDM_Odm->pBandType)
1300             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) );
1301         if (pDM_Odm->pMacPhyMode)
1302             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) );
1303         if (pDM_Odm->pBuddyAdapter)
1304             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) );
1305         if (pDM_Odm->pBuddyAdapter)
1306             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) );
1307         if (pDM_Odm->pbMasterOfDMSP)
1308             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) );
1309 #endif
1310         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) );
1311         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) );
1312
1313         if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1314                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) );
1315 }
1316
1317 void
1318 odm_CmnInfoUpdate_Debug(
1319                 PDM_ODM_T               pDM_Odm
1320         )
1321 {
1322         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
1323         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) );
1324         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) );
1325         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) );
1326         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) );
1327 }
1328
1329 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
1330 void
1331 ODM_InitAllWorkItems(PDM_ODM_T  pDM_Odm )
1332 {
1333 #if USE_WORKITEM
1334         PADAPTER                pAdapter = pDM_Odm->Adapter;
1335
1336         ODM_InitializeWorkItem( pDM_Odm,
1337                                                         &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem,
1338                                                         (RT_WORKITEM_CALL_BACK)odm_SwAntDivChkAntSwitchWorkitemCallback,
1339                                                         (void *)pAdapter,
1340                                                         "AntennaSwitchWorkitem"
1341         );
1342
1343         ODM_InitializeWorkItem(
1344                 pDM_Odm,
1345                 &(pDM_Odm->PathDivSwitchWorkitem),
1346                 (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback,
1347                 (void *)pAdapter,
1348                 "SWAS_WorkItem");
1349
1350         ODM_InitializeWorkItem(
1351                 pDM_Odm,
1352                 &(pDM_Odm->CCKPathDiversityWorkitem),
1353                 (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback,
1354                 (void *)pAdapter,
1355                 "CCKTXPathDiversityWorkItem");
1356 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
1357 #if (RTL8188E_SUPPORT == 1)
1358         ODM_InitializeWorkItem(
1359                 pDM_Odm,
1360                 &(pDM_Odm->FastAntTrainingWorkitem),
1361                 (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback,
1362                 (void *)pAdapter,
1363                 "FastAntTrainingWorkitem");
1364 #endif
1365 #endif
1366         ODM_InitializeWorkItem(
1367                 pDM_Odm,
1368                 &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem),
1369                 (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback,
1370                 (void *)pAdapter,
1371                 "PSDRXHP_WorkItem");
1372 #endif
1373 }
1374
1375 void
1376 ODM_FreeAllWorkItems(PDM_ODM_T  pDM_Odm )
1377 {
1378 #if USE_WORKITEM
1379         ODM_FreeWorkItem(       &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem));
1380
1381         ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem));
1382
1383         ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem));
1384
1385         ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem));
1386
1387         ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem));
1388 #endif
1389
1390 }
1391 #endif
1392
1393 /*
1394 void
1395 odm_FindMinimumRSSI(
1396                 PDM_ODM_T               pDM_Odm
1397         )
1398 {
1399         u4Byte  i;
1400         u1Byte  RSSI_Min = 0xFF;
1401
1402         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1403         {
1404 //              if (pDM_Odm->pODM_StaInfo[i] != NULL)
1405                 if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1406                 {
1407                         if (pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min)
1408                         {
1409                                 RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave;
1410                         }
1411                 }
1412         }
1413
1414         pDM_Odm->RSSI_Min = RSSI_Min;
1415
1416 }
1417
1418 void
1419 odm_IsLinked(
1420                 PDM_ODM_T               pDM_Odm
1421         )
1422 {
1423         u4Byte i;
1424         bool Linked = false;
1425
1426         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1427         {
1428                         if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1429                         {
1430                                 Linked = true;
1431                                 break;
1432                         }
1433
1434         }
1435
1436         pDM_Odm->bLinked = Linked;
1437 }
1438 */
1439
1440
1441 //3============================================================
1442 //3 DIG
1443 //3============================================================
1444 /*-----------------------------------------------------------------------------
1445  * Function:    odm_DIGInit()
1446  *
1447  * Overview:    Set DIG scheme init value.
1448  *
1449  * Input:               NONE
1450  *
1451  * Output:              NONE
1452  *
1453  * Return:              NONE
1454  *
1455  * Revised History:
1456  *      When            Who             Remark
1457  *
1458  *---------------------------------------------------------------------------*/
1459 void
1460 ODM_ChangeDynamicInitGainThresh(
1461         PDM_ODM_T       pDM_Odm,
1462         u4Byte          DM_Type,
1463         u4Byte          DM_Value
1464         )
1465 {
1466         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1467
1468         if (DM_Type == DIG_TYPE_THRESH_HIGH)
1469         {
1470                 pDM_DigTable->RssiHighThresh = DM_Value;
1471         }
1472         else if (DM_Type == DIG_TYPE_THRESH_LOW)
1473         {
1474                 pDM_DigTable->RssiLowThresh = DM_Value;
1475         }
1476         else if (DM_Type == DIG_TYPE_ENABLE)
1477         {
1478                 pDM_DigTable->Dig_Enable_Flag   = true;
1479         }
1480         else if (DM_Type == DIG_TYPE_DISABLE)
1481         {
1482                 pDM_DigTable->Dig_Enable_Flag = false;
1483         }
1484         else if (DM_Type == DIG_TYPE_BACKOFF)
1485         {
1486                 if (DM_Value > 30)
1487                         DM_Value = 30;
1488                 pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
1489         }
1490         else if (DM_Type == DIG_TYPE_RX_GAIN_MIN)
1491         {
1492                 if (DM_Value == 0)
1493                         DM_Value = 0x1;
1494                 pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
1495         }
1496         else if (DM_Type == DIG_TYPE_RX_GAIN_MAX)
1497         {
1498                 if (DM_Value > 0x50)
1499                         DM_Value = 0x50;
1500                 pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
1501         }
1502 }       /* DM_ChangeDynamicInitGainThresh */
1503
1504 int getIGIForDiff(int value_IGI)
1505 {
1506         #define ONERCCA_LOW_TH          0x30
1507         #define ONERCCA_LOW_DIFF        8
1508
1509         if (value_IGI < ONERCCA_LOW_TH) {
1510                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
1511                         return ONERCCA_LOW_TH;
1512                 else
1513                         return value_IGI + ONERCCA_LOW_DIFF;
1514         } else {
1515                 return value_IGI;
1516         }
1517 }
1518
1519
1520 // Add by Neil Chen to enable edcca to MP Platform
1521 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
1522
1523 void
1524 odm_EnableEDCCA(
1525                 PDM_ODM_T               pDM_Odm
1526 )
1527 {
1528
1529         // This should be moved out of OUTSRC
1530         PADAPTER                pAdapter        = pDM_Odm->Adapter;
1531         // Enable EDCCA. The value is suggested by SD3 Wilson.
1532
1533         //
1534         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
1535         //
1536         if ((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
1537         {
1538                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
1539                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
1540                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
1541
1542         }
1543         else
1544         {
1545                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
1546                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
1547                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
1548         }
1549
1550         //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
1551 }
1552
1553 void
1554 odm_DisableEDCCA(
1555                 PDM_ODM_T               pDM_Odm
1556 )
1557 {
1558         // Disable EDCCA..
1559         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
1560         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
1561 }
1562
1563 //
1564 // Description: According to initial gain value to determine to enable or disable EDCCA.
1565 //
1566 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
1567 //
1568 void
1569 odm_DynamicEDCCA(
1570                 PDM_ODM_T               pDM_Odm
1571 )
1572 {
1573         PADAPTER                pAdapter        = pDM_Odm->Adapter;
1574         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1575         u1Byte  RegC50, RegC58;
1576         bool    bEDCCAenable = false;
1577
1578         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
1579         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
1580
1581
1582         if ((RegC50 > 0x28 && RegC58 > 0x28) ||
1583                 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
1584                 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
1585         {
1586                 if (!pHalData->bPreEdccaEnable)
1587                 {
1588                         odm_EnableEDCCA(pDM_Odm);
1589                         pHalData->bPreEdccaEnable = true;
1590                 }
1591
1592         }
1593         else if ((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
1594         {
1595                 if (pHalData->bPreEdccaEnable)
1596                 {
1597                         odm_DisableEDCCA(pDM_Odm);
1598                         pHalData->bPreEdccaEnable = false;
1599                 }
1600         }
1601 }
1602
1603
1604 #endif    // end MP platform support
1605
1606 void
1607 ODM_Write_DIG(
1608         PDM_ODM_T               pDM_Odm,
1609         u1Byte                  CurrentIGI
1610         )
1611 {
1612         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1613
1614         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n",
1615                 ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
1616
1617         if (pDM_DigTable->CurIGValue != CurrentIGI)//if (pDM_DigTable->PreIGValue != CurrentIGI)
1618         {
1619                 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP))
1620                 {
1621                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1622                                 if (pDM_Odm->SupportICType != ODM_RTL8188E)
1623                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1624                 }
1625                 else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1626                 {
1627                         switch (*(pDM_Odm->pOnePathCCA))
1628                         {
1629                         case ODM_CCA_2R:
1630                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1631                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
1632                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1633                                 break;
1634                         case ODM_CCA_1R_A:
1635                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1636                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
1637                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
1638                                 break;
1639                         case ODM_CCA_1R_B:
1640                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
1641                                         if (pDM_Odm->SupportICType != ODM_RTL8188E)
1642                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1643                                         break;
1644                                 }
1645                 }
1646                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n",CurrentIGI));
1647                 //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue;
1648                 pDM_DigTable->CurIGValue = CurrentIGI;
1649         }
1650         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n",CurrentIGI));
1651
1652 // Add by Neil Chen to enable edcca to MP Platform
1653 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
1654         // Adjust EDCCA.
1655         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1656                 odm_DynamicEDCCA(pDM_Odm);
1657 #endif
1658
1659
1660 }
1661
1662
1663 //Need LPS mode for CE platform --2012--08--24---
1664 //8723AS/8189ES
1665 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1666
1667 void
1668 odm_DIGbyRSSI_LPS(
1669                 PDM_ODM_T               pDM_Odm
1670         )
1671 {
1672         PADAPTER                                        pAdapter =pDM_Odm->Adapter;
1673         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1674         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1675
1676         u1Byte  RSSI_Lower=DM_DIG_MIN_NIC;   //0x1E or 0x1C
1677         u1Byte  bFwCurrentInPSMode = false;
1678         u1Byte  CurrentIGI=pDM_Odm->RSSI_Min;
1679
1680         if (! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E)))
1681                 return;
1682
1683         CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
1684 #ifdef CONFIG_LPS
1685         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
1686 #endif
1687
1688         // Using FW PS mode to make IGI
1689         if (bFwCurrentInPSMode)
1690         {
1691                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n"));
1692                 //Adjust by  FA in LPS MODE
1693                 if (pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS)
1694                         CurrentIGI = CurrentIGI+2;
1695                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
1696                         CurrentIGI = CurrentIGI+1;
1697                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
1698                         CurrentIGI = CurrentIGI-1;
1699         }
1700         else
1701         {
1702                 CurrentIGI = RSSI_Lower;
1703         }
1704
1705         //Lower bound checking
1706
1707         //RSSI Lower bound check
1708         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
1709                 RSSI_Lower =(pDM_Odm->RSSI_Min-10);
1710         else
1711                 RSSI_Lower =DM_DIG_MIN_NIC;
1712
1713         //Upper and Lower Bound checking
1714          if (CurrentIGI > DM_DIG_MAX_NIC)
1715                 CurrentIGI=DM_DIG_MAX_NIC;
1716          else if (CurrentIGI < RSSI_Lower)
1717                 CurrentIGI =RSSI_Lower;
1718
1719         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1720
1721 }
1722 #endif
1723
1724
1725 void
1726 odm_DIGInit(
1727                 PDM_ODM_T               pDM_Odm
1728         )
1729 {
1730         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1731
1732         //pDM_DigTable->Dig_Enable_Flag = true;
1733         //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
1734         pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
1735         //pDM_DigTable->PreIGValue = 0x0;
1736         //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
1737         //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
1738         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
1739         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
1740         pDM_DigTable->FALowThresh       = DMfalseALARM_THRESH_LOW;
1741         pDM_DigTable->FAHighThresh      = DMfalseALARM_THRESH_HIGH;
1742         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR)
1743         {
1744                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1745                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
1746         }
1747         else
1748         {
1749                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1750                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
1751         }
1752         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
1753         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
1754         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
1755         pDM_DigTable->PreCCK_CCAThres = 0xFF;
1756         pDM_DigTable->CurCCK_CCAThres = 0x83;
1757         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
1758         pDM_DigTable->LargeFAHit = 0;
1759         pDM_DigTable->Recover_cnt = 0;
1760         pDM_DigTable->DIG_Dynamic_MIN_0 =DM_DIG_MIN_NIC;
1761         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
1762         pDM_DigTable->bMediaConnect_0 = false;
1763         pDM_DigTable->bMediaConnect_1 = false;
1764
1765         //To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error
1766         pDM_Odm->bDMInitialGainEnable = true;
1767
1768 }
1769
1770
1771 void
1772 odm_DIG(
1773                 PDM_ODM_T               pDM_Odm
1774         )
1775 {
1776
1777         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1778         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1779         pRXHP_T                                         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
1780         u1Byte                                          DIG_Dynamic_MIN;
1781         u1Byte                                          DIG_MaxOfMin;
1782         bool                                            FirstConnect, FirstDisConnect;
1783         u1Byte                                          dm_dig_max, dm_dig_min;
1784         u1Byte                                          CurrentIGI = pDM_DigTable->CurIGValue;
1785
1786 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
1787 // This should be moved out of OUTSRC
1788         PADAPTER                pAdapter        = pDM_Odm->Adapter;
1789 #if OS_WIN_FROM_WIN7(OS_VERSION)
1790         if (IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
1791         {
1792                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test\n"));
1793                 return;
1794         }
1795 #endif
1796 #if (BT_30_SUPPORT == 1)
1797         if (pDM_Odm->bBtHsOperation)
1798         {
1799                 odm_DigForBtHsMode(pDM_Odm);
1800                 return;
1801         }
1802 #endif
1803
1804         if (pRX_HP_Table->RXHP_flag == 1)
1805         {
1806                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation\n"));
1807                 return;
1808         }
1809 #endif  //end ODM_MP type
1810
1811 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1812 #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
1813         if ((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
1814         {
1815                 printk("pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min);
1816                 ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi);
1817                 return;
1818         }
1819 #endif
1820 #endif
1821 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1822         prtl8192cd_priv priv                    = pDM_Odm->priv;
1823         if (!((priv->up_time > 5) && (priv->up_time % 2)) )
1824         {
1825                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period\n"));
1826                 return;
1827         }
1828 #endif
1829
1830         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
1831         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
1832                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
1833                 return;
1834         }
1835
1836         if (*(pDM_Odm->pbScanInProcess)) {
1837                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n"));
1838                 return;
1839         }
1840
1841         //add by Neil Chen to avoid PSD is processing
1842         if (pDM_Odm->bDMInitialGainEnable == false) {
1843                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n"));
1844                 return;
1845         }
1846
1847         if (pDM_Odm->SupportICType == ODM_RTL8192D) {
1848                 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) {
1849                         if (*(pDM_Odm->pbMasterOfDMSP)) {
1850                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1851                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == false);
1852                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == true);
1853                         } else {
1854                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
1855                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == false);
1856                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == true);
1857                         }
1858                 } else {
1859                         if (*(pDM_Odm->pBandType) == ODM_BAND_5G) {
1860                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1861                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == false);
1862                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == true);
1863                         } else {
1864                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
1865                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == false);
1866                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == true);
1867                         }
1868                 }
1869         } else {
1870                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1871                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == false);
1872                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == true);
1873         }
1874
1875         //1 Boundary Decision
1876         if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) &&
1877                 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA))
1878         {
1879                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
1880
1881                         dm_dig_max = DM_DIG_MAX_AP_HP;
1882                         dm_dig_min = DM_DIG_MIN_AP_HP;
1883                 } else {
1884                         dm_dig_max = DM_DIG_MAX_NIC_HP;
1885                         dm_dig_min = DM_DIG_MIN_NIC_HP;
1886                 }
1887                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
1888         } else {
1889                 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1890                 {
1891 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1892 #ifdef DFS
1893                         if (!priv->pmib->dot11DFSEntry.disable_DFS &&
1894                                 (OPMODE & WIFI_AP_STATE) &&
1895                                 (((pDM_Odm->ControlChannel >= 52) &&
1896                                 (pDM_Odm->ControlChannel <= 64)) ||
1897                                 ((pDM_Odm->ControlChannel >= 100) &&
1898                                 (pDM_Odm->ControlChannel <= 140))))
1899                                 dm_dig_max = 0x24;
1900                         else
1901 #endif
1902                         if (priv->pmib->dot11RFEntry.tx2path) {
1903                                 if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B)
1904                                         dm_dig_max = 0x2A;
1905                                 else
1906                                         dm_dig_max = 0x32;
1907                         }
1908                         else
1909 #endif
1910                         dm_dig_max = DM_DIG_MAX_AP;
1911                         dm_dig_min = DM_DIG_MIN_AP;
1912                         DIG_MaxOfMin = dm_dig_max;
1913                 }
1914                 else
1915                 {
1916                         dm_dig_max = DM_DIG_MAX_NIC;
1917                         dm_dig_min = DM_DIG_MIN_NIC;
1918                         DIG_MaxOfMin = DM_DIG_MAX_AP;
1919                 }
1920         }
1921
1922
1923         if (pDM_Odm->bLinked)
1924         {
1925               //2 8723A Series, offset need to be 10 //neil
1926                 if (pDM_Odm->SupportICType==(ODM_RTL8723A))
1927                 {
1928                         //2 Upper Bound
1929                         if (( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC )
1930                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1931                         else if (( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC )
1932                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
1933                         else
1934                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
1935
1936                         //2 If BT is Concurrent, need to set Lower Bound
1937
1938 #if (BT_30_SUPPORT == 1)
1939                         if (pDM_Odm->bBtBusy)
1940                         {
1941                                 if (pDM_Odm->RSSI_Min>10)
1942                                 {
1943                                 if ((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC)
1944                                         DIG_Dynamic_MIN = DM_DIG_MAX_NIC;
1945                                 else if ((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC)
1946                                                 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
1947                                         else
1948                                                 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10;
1949                                 }
1950                                 else
1951                                         DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
1952                         }
1953                         else
1954 #endif
1955                         {
1956                                 DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
1957                         }
1958                 }
1959                 else
1960                 {
1961                 //2 Modify DIG upper bound
1962                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max )
1963                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
1964                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min )
1965                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
1966                         else
1967                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
1968
1969
1970                 //2 Modify DIG lower bound
1971                         if (pDM_Odm->bOneEntryOnly)
1972                         {
1973                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
1974                                         DIG_Dynamic_MIN = dm_dig_min;
1975                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
1976                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
1977                                 else
1978                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
1979                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=true,  DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN));
1980                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min));
1981                         }
1982                         //1 Lower Bound for 88E AntDiv
1983 #if (RTL8188E_SUPPORT == 1)
1984                         else if ((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1985                         {
1986                                 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
1987                                 {
1988                                         DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
1989                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n",pDM_DigTable->AntDiv_RSSI_max));
1990                                 }
1991                         }
1992 #endif
1993                         else
1994                         {
1995                                 DIG_Dynamic_MIN=dm_dig_min;
1996                         }
1997                 }
1998         }
1999         else
2000         {
2001                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
2002                 DIG_Dynamic_MIN = dm_dig_min;
2003                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
2004         }
2005
2006         //1 Modify DIG lower bound, deal with abnormally large false alarm
2007         if (pFalseAlmCnt->Cnt_all > 10000)
2008         {
2009                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n"));
2010
2011                 if (pDM_DigTable->LargeFAHit != 3)
2012                 pDM_DigTable->LargeFAHit++;
2013                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI)//if (pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
2014                 {
2015                         pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
2016                         pDM_DigTable->LargeFAHit = 1;
2017                 }
2018
2019                 if (pDM_DigTable->LargeFAHit >= 3)
2020                 {
2021                         if ((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max)
2022                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
2023                         else
2024                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
2025                         pDM_DigTable->Recover_cnt = 3600; //3600=2hr
2026                 }
2027
2028         }
2029         else
2030         {
2031                 //Recovery mechanism for IGI lower bound
2032                 if (pDM_DigTable->Recover_cnt != 0)
2033                         pDM_DigTable->Recover_cnt --;
2034                 else
2035                 {
2036                         if (pDM_DigTable->LargeFAHit < 3)
2037                         {
2038                                 if ((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN)
2039                                 {
2040                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN;
2041                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN;
2042                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
2043                                 }
2044                                 else
2045                                 {
2046                                         pDM_DigTable->ForbiddenIGI --;
2047                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
2048                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
2049                                 }
2050                         }
2051                         else
2052                         {
2053                                 pDM_DigTable->LargeFAHit = 0;
2054                         }
2055                 }
2056         }
2057         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit));
2058
2059         //1 Adjust initial gain by false alarm
2060         if (pDM_Odm->bLinked)
2061         {
2062                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
2063                 if (FirstConnect)
2064                 {
2065                         CurrentIGI = pDM_Odm->RSSI_Min;
2066                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
2067                 }
2068                 else
2069                 {
2070                         if (pDM_Odm->SupportICType == ODM_RTL8192D)
2071                         {
2072                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
2073                                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
2074                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
2075                                         CurrentIGI = CurrentIGI + 1; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
2076                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
2077                                         CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
2078                         }
2079                         else
2080                         {
2081 #if (BT_30_SUPPORT == 1)
2082                                 if (pDM_Odm->bBtBusy)
2083                                 {
2084                                         if (pFalseAlmCnt->Cnt_all > 0x300)
2085                                                 CurrentIGI = CurrentIGI + 2;
2086                                         else if (pFalseAlmCnt->Cnt_all > 0x250)
2087                                                 CurrentIGI = CurrentIGI + 1;
2088                                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
2089                                                 CurrentIGI = CurrentIGI -1;
2090                                 }
2091                                 else
2092 #endif
2093                                 {
2094                                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
2095                                                 CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
2096                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
2097                                                 CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
2098                                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
2099                                                 CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
2100
2101
2102                         }
2103                 }
2104         }
2105         }
2106         else
2107         {
2108                 //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min
2109                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
2110                 if (FirstDisConnect)
2111                 {
2112                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
2113                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n"));
2114                 }
2115                 else
2116                 {
2117                 //2012.03.30 LukeLee: enable DIG before link but with very high thresholds
2118              if (pFalseAlmCnt->Cnt_all > 10000)
2119                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
2120                 else if (pFalseAlmCnt->Cnt_all > 8000)
2121                         CurrentIGI = CurrentIGI + 1;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
2122                 else if (pFalseAlmCnt->Cnt_all < 500)
2123                         CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
2124                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n"));
2125                 }
2126         }
2127         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
2128         //1 Check initial gain by upper/lower bound
2129 /*
2130         if (pDM_DigTable->CurIGValue > pDM_DigTable->rx_gain_range_max)
2131                 pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_max;
2132         if (pDM_DigTable->CurIGValue < pDM_DigTable->rx_gain_range_min)
2133                 pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min;
2134 */
2135         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
2136                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
2137         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
2138                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
2139
2140         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
2141                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
2142         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
2143         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
2144
2145         //2 High power RSSI threshold
2146 #if (DM_ODM_SUPPORT_TYPE & ODM_MP)
2147 {
2148         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
2149
2150         // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue
2151         u8Byte                  curTxOkCnt=0, curRxOkCnt=0;
2152         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
2153
2154         u8Byte                  OKCntAll=0;
2155         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
2156         //u8Byte                        CurByteCnt=0, PreByteCnt=0;
2157
2158         curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
2159         curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
2160         lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast;
2161         lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast;
2162         //----------------------------------------------------------end for LC Mocca issue
2163         if ((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD))
2164         {
2165                 // High power IGI lower bound
2166                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
2167                 if (CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND)
2168                 {
2169                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue));
2170                         //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
2171                         CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
2172                 }
2173         }
2174         if ((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter))
2175                 {
2176                         if (pHalData->UndecoratedSmoothedPWDB > 0x28)
2177                         {
2178                                 if (CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
2179                                 {
2180                                         //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
2181                                         CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
2182                                 }
2183                 }
2184         }
2185 }
2186 #endif
2187
2188 #if (RTL8192D_SUPPORT==1)
2189         if (pDM_Odm->SupportICType == ODM_RTL8192D)
2190         {
2191                 //sherry  delete DualMacSmartConncurrent 20110517
2192                 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
2193                 {
2194                         ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
2195                         if (*(pDM_Odm->pbMasterOfDMSP))
2196                         {
2197                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
2198                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
2199                         }
2200                         else
2201                         {
2202                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
2203                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
2204                         }
2205                 }
2206                 else
2207                 {
2208                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2209                         if (*(pDM_Odm->pBandType) == ODM_BAND_5G)
2210                         {
2211                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
2212                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
2213                         }
2214                         else
2215                         {
2216                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
2217                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
2218                         }
2219                 }
2220         }
2221         else
2222 #endif
2223         {
2224                 ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2225                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
2226                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
2227         }
2228
2229 }
2230
2231 //3============================================================
2232 //3 FASLE ALARM CHECK
2233 //3============================================================
2234
2235 void
2236 odm_FalseAlarmCounterStatistics(
2237                 PDM_ODM_T               pDM_Odm
2238         )
2239 {
2240         u4Byte ret_value;
2241         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
2242
2243 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2244         prtl8192cd_priv priv            = pDM_Odm->priv;
2245         if ( (priv->auto_channel != 0) && (priv->auto_channel != 2) )
2246                 return;
2247 #endif
2248
2249 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2250         if ((pDM_Odm->SupportICType == ODM_RTL8192D) &&
2251                 (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&&    ////modify by Guo.Mingzhi 2011-12-29
2252                 (!(*(pDM_Odm->pbMasterOfDMSP))))
2253         {
2254                 odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm);
2255                 return;
2256         }
2257 #endif
2258
2259         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
2260                 return;
2261
2262 //      if (pDM_Odm->SupportICType != ODM_RTL8812)
2263         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2264         {
2265
2266         //hold ofdm counter
2267                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter
2268                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter
2269
2270                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
2271         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
2272         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
2273                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
2274         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
2275         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
2276                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
2277         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
2278         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
2279                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
2280         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
2281
2282         FalseAlmCnt->Cnt_Ofdm_fail =    FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
2283                                                                 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
2284                                                                 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
2285
2286 #if (RTL8188E_SUPPORT==1)
2287         if (pDM_Odm->SupportICType == ODM_RTL8188E)
2288         {
2289                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
2290                 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
2291                 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
2292         }
2293 #endif
2294
2295 #if (RTL8192D_SUPPORT==1)
2296         if (pDM_Odm->SupportICType == ODM_RTL8192D)
2297         {
2298                 odm_GetCCKFalseAlarm_92D(pDM_Odm);
2299         }
2300         else
2301 #endif
2302         {
2303                 //hold cck counter
2304                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
2305                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
2306
2307                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
2308                 FalseAlmCnt->Cnt_Cck_fail = ret_value;
2309                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
2310                 FalseAlmCnt->Cnt_Cck_fail +=  (ret_value& 0xff)<<8;
2311
2312                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
2313                 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
2314         }
2315
2316         FalseAlmCnt->Cnt_all = (        FalseAlmCnt->Cnt_Fast_Fsync +
2317                                                 FalseAlmCnt->Cnt_SB_Search_fail +
2318                                                 FalseAlmCnt->Cnt_Parity_Fail +
2319                                                 FalseAlmCnt->Cnt_Rate_Illegal +
2320                                                 FalseAlmCnt->Cnt_Crc8_fail +
2321                                                 FalseAlmCnt->Cnt_Mcs_fail +
2322                                                 FalseAlmCnt->Cnt_Cck_fail);
2323
2324         FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
2325
2326 #if (RTL8192C_SUPPORT==1)
2327         if (pDM_Odm->SupportICType == ODM_RTL8192C)
2328                 odm_ResetFACounter_92C(pDM_Odm);
2329 #endif
2330
2331 #if (RTL8192D_SUPPORT==1)
2332         if (pDM_Odm->SupportICType == ODM_RTL8192D)
2333                 odm_ResetFACounter_92D(pDM_Odm);
2334 #endif
2335
2336         if (pDM_Odm->SupportICType >=ODM_RTL8723A)
2337         {
2338                 //reset false alarm counter registers
2339                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
2340                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
2341                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
2342                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
2343                 //update ofdm counter
2344                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter
2345                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter
2346
2347                 //reset CCK CCA counter
2348                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
2349                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
2350                 //reset CCK FA counter
2351                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
2352                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
2353         }
2354
2355         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
2356         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
2357                 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
2358         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
2359                 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
2360         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
2361                 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
2362         }
2363         else //FOR ODM_IC_11AC_SERIES
2364         {
2365                 //read OFDM FA counter
2366                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
2367                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
2368                 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
2369
2370                 // reset OFDM FA coutner
2371                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
2372                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
2373                 // reset CCK FA counter
2374                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
2375                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
2376         }
2377         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n",       FalseAlmCnt->Cnt_Cck_fail));
2378         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
2379         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n",  FalseAlmCnt->Cnt_all));
2380 }
2381
2382 //3============================================================
2383 //3 CCK Packet Detect Threshold
2384 //3============================================================
2385
2386 void
2387 odm_CCKPacketDetectionThresh(
2388                 PDM_ODM_T               pDM_Odm
2389         )
2390 {
2391
2392         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2393         u1Byte  CurCCK_CCAThres;
2394         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
2395
2396 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2397 //modify by Guo.Mingzhi 2011-12-29
2398         if (pDM_Odm->bDualMacSmartConcurrent == true)
2399 //      if (pDM_Odm->bDualMacSmartConcurrent == false)
2400                 return;
2401 #if (BT_30_SUPPORT == 1)
2402         if (pDM_Odm->bBtHsOperation)
2403         {
2404                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n"));
2405                 ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd);
2406                 return;
2407         }
2408 #endif
2409 #endif
2410
2411         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
2412                 return;
2413
2414         if (pDM_Odm->ExtLNA)
2415                 return;
2416
2417         if (pDM_Odm->bLinked)
2418         {
2419                 if (pDM_Odm->RSSI_Min > 25)
2420                         CurCCK_CCAThres = 0xcd;
2421                 else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10))
2422                         CurCCK_CCAThres = 0x83;
2423                 else
2424                 {
2425                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
2426                                 CurCCK_CCAThres = 0x83;
2427                         else
2428                                 CurCCK_CCAThres = 0x40;
2429                 }
2430         }
2431         else
2432         {
2433                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
2434                         CurCCK_CCAThres = 0x83;
2435                 else
2436                         CurCCK_CCAThres = 0x40;
2437         }
2438
2439 #if (RTL8192D_SUPPORT==1)
2440         if (pDM_Odm->SupportICType == ODM_RTL8192D)
2441                 ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres);
2442         else
2443 #endif
2444                 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
2445 }
2446
2447 void
2448 ODM_Write_CCK_CCA_Thres(
2449         PDM_ODM_T               pDM_Odm,
2450         u1Byte                  CurCCK_CCAThres
2451         )
2452 {
2453         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2454
2455         if (pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres)             //modify by Guo.Mingzhi 2012-01-03
2456         {
2457                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres);
2458         }
2459         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
2460         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
2461
2462 }
2463
2464 //3============================================================
2465 //3 BB Power Save
2466 //3============================================================
2467 void
2468 odm_DynamicBBPowerSavingInit(
2469                 PDM_ODM_T               pDM_Odm
2470         )
2471 {
2472         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
2473
2474         pDM_PSTable->PreCCAState = CCA_MAX;
2475         pDM_PSTable->CurCCAState = CCA_MAX;
2476         pDM_PSTable->PreRFState = RF_MAX;
2477         pDM_PSTable->CurRFState = RF_MAX;
2478         pDM_PSTable->Rssi_val_min = 0;
2479         pDM_PSTable->initialize = 0;
2480 }
2481
2482
2483 void
2484 odm_DynamicBBPowerSaving(
2485                 PDM_ODM_T               pDM_Odm
2486         )
2487 {
2488 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
2489
2490         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
2491                 return;
2492         if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
2493                 return;
2494         if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE)))
2495                 return;
2496
2497         //1 2.Power Saving for 92C
2498         if ((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
2499         {
2500                 odm_1R_CCA(pDM_Odm);
2501         }
2502
2503         // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
2504         // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
2505         //1 3.Power Saving for 88C
2506         else
2507         {
2508                 ODM_RF_Saving(pDM_Odm, false);
2509         }
2510 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2511
2512 }
2513
2514 void
2515 odm_1R_CCA(
2516         PDM_ODM_T       pDM_Odm
2517         )
2518 {
2519         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
2520
2521         if (pDM_Odm->RSSI_Min!= 0xFF)
2522         {
2523
2524                 if (pDM_PSTable->PreCCAState == CCA_2R)
2525                 {
2526                         if (pDM_Odm->RSSI_Min >= 35)
2527                                 pDM_PSTable->CurCCAState = CCA_1R;
2528                         else
2529                                 pDM_PSTable->CurCCAState = CCA_2R;
2530
2531                 }
2532                 else {
2533                         if (pDM_Odm->RSSI_Min <= 30)
2534                                 pDM_PSTable->CurCCAState = CCA_2R;
2535                         else
2536                                 pDM_PSTable->CurCCAState = CCA_1R;
2537                 }
2538         }
2539         else {
2540                 pDM_PSTable->CurCCAState=CCA_MAX;
2541         }
2542
2543         if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
2544         {
2545                 if (pDM_PSTable->CurCCAState == CCA_1R)
2546                 {
2547                         if (  pDM_Odm->RFType ==ODM_2T2R )
2548                         {
2549                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x13);
2550                                 //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
2551                         }
2552                         else
2553                         {
2554                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x23);
2555                                 //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
2556                         }
2557                 }
2558                 else
2559                 {
2560                         ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x33);
2561                         //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
2562                 }
2563                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
2564         }
2565         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
2566 }
2567
2568 void
2569 ODM_RF_Saving(
2570         PDM_ODM_T       pDM_Odm,
2571         u1Byte          bForceInNormal
2572         )
2573 {
2574 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
2575         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
2576         u1Byte  Rssi_Up_bound = 30 ;
2577         u1Byte  Rssi_Low_bound = 25;
2578         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2579         if (pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
2580         {
2581                 Rssi_Up_bound = 50 ;
2582                 Rssi_Low_bound = 45;
2583         }
2584         #endif
2585         if (pDM_PSTable->initialize == 0) {
2586
2587                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
2588                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
2589                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
2590                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
2591                 //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
2592                 pDM_PSTable->initialize = 1;
2593         }
2594
2595         if (!bForceInNormal)
2596         {
2597                 if (pDM_Odm->RSSI_Min != 0xFF)
2598                 {
2599                         if (pDM_PSTable->PreRFState == RF_Normal)
2600                         {
2601                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
2602                                         pDM_PSTable->CurRFState = RF_Save;
2603                                 else
2604                                         pDM_PSTable->CurRFState = RF_Normal;
2605                         }
2606                         else {
2607                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
2608                                         pDM_PSTable->CurRFState = RF_Normal;
2609                                 else
2610                                         pDM_PSTable->CurRFState = RF_Save;
2611                         }
2612                 }
2613                 else
2614                         pDM_PSTable->CurRFState=RF_MAX;
2615         }
2616         else
2617         {
2618                 pDM_PSTable->CurRFState = RF_Normal;
2619         }
2620
2621         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
2622         {
2623                 if (pDM_PSTable->CurRFState == RF_Save)
2624                 {
2625                         // <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
2626                         // Suggested by SD3 Yu-Nan. 2011.01.20.
2627                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
2628                         {
2629                                 ODM_SetBBReg(pDM_Odm, 0x874  , BIT5, 0x1); //Reg874[5]=1b'1
2630                         }
2631                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
2632                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
2633                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
2634                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
2635                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
2636                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
2637                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
2638                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
2639                 }
2640                 else
2641                 {
2642                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1CC000, pDM_PSTable->Reg874);
2643                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
2644                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
2645                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
2646                         ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
2647
2648                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
2649                         {
2650                                 ODM_SetBBReg(pDM_Odm,0x874  , BIT5, 0x0); //Reg874[5]=1b'0
2651                         }
2652                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
2653                 }
2654                 pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
2655         }
2656 #endif
2657 }
2658
2659
2660 //3============================================================
2661 //3 RATR MASK
2662 //3============================================================
2663 //3============================================================
2664 //3 Rate Adaptive
2665 //3============================================================
2666
2667 void
2668 odm_RateAdaptiveMaskInit(
2669         PDM_ODM_T       pDM_Odm
2670         )
2671 {
2672         PODM_RATE_ADAPTIVE      pOdmRA = &pDM_Odm->RateAdaptive;
2673
2674 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2675         PMGNT_INFO                              pMgntInfo = &pDM_Odm->Adapter->MgntInfo;
2676         PRATE_ADAPTIVE                  pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive;
2677
2678         pRA->RATRState = DM_RATR_STA_INIT;
2679         if (pMgntInfo->DM_Type == DM_Type_ByDriver)
2680                 pMgntInfo->bUseRAMask = true;
2681         else
2682                 pMgntInfo->bUseRAMask = false;
2683
2684 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2685         pOdmRA->Type = DM_Type_ByDriver;
2686         if (pOdmRA->Type == DM_Type_ByDriver)
2687                 pDM_Odm->bUseRAMask = true;
2688         else
2689                 pDM_Odm->bUseRAMask = false;
2690
2691 #endif
2692
2693         pOdmRA->RATRState = DM_RATR_STA_INIT;
2694         pOdmRA->HighRSSIThresh = 50;
2695         pOdmRA->LowRSSIThresh = 20;
2696 }
2697
2698 #if (DM_ODM_SUPPORT_TYPE & ODM_MP)
2699 void
2700 ODM_RateAdaptiveStateApInit(
2701         PADAPTER        Adapter ,
2702         PRT_WLAN_STA  pEntry
2703         )
2704 {
2705         PRATE_ADAPTIVE  pRA = (PRATE_ADAPTIVE)&pEntry->RateAdaptive;
2706         pRA->RATRState = DM_RATR_STA_INIT;
2707 }
2708 #endif
2709
2710 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2711 u4Byte ODM_Get_Rate_Bitmap(
2712         PDM_ODM_T       pDM_Odm,
2713         u4Byte          macid,
2714         u4Byte          ra_mask,
2715         u1Byte          rssi_level)
2716 {
2717         PSTA_INFO_T     pEntry;
2718         u4Byte  rate_bitmap = 0x0fffffff;
2719         u1Byte  WirelessMode;
2720         //u1Byte        WirelessMode =*(pDM_Odm->pWirelessMode);
2721
2722
2723         pEntry = pDM_Odm->pODM_StaInfo[macid];
2724         if (!IS_STA_VALID(pEntry))
2725                 return ra_mask;
2726
2727         WirelessMode = pEntry->wireless_mode;
2728
2729         switch (WirelessMode)
2730         {
2731                 case ODM_WM_B:
2732                         if (ra_mask & 0x0000000c)               //11M or 5.5M enable
2733                                 rate_bitmap = 0x0000000d;
2734                         else
2735                                 rate_bitmap = 0x0000000f;
2736                         break;
2737
2738                 case (ODM_WM_A|ODM_WM_G):
2739                         if (rssi_level == DM_RATR_STA_HIGH)
2740                                 rate_bitmap = 0x00000f00;
2741                         else
2742                                 rate_bitmap = 0x00000ff0;
2743                         break;
2744
2745                 case (ODM_WM_B|ODM_WM_G):
2746                         if (rssi_level == DM_RATR_STA_HIGH)
2747                                 rate_bitmap = 0x00000f00;
2748                         else if (rssi_level == DM_RATR_STA_MIDDLE)
2749                                 rate_bitmap = 0x00000ff0;
2750                         else
2751                                 rate_bitmap = 0x00000ff5;
2752                         break;
2753
2754                 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G)    :
2755                 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G)   :
2756                         {
2757                                 if (    pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R)
2758                                 {
2759                                         if (rssi_level == DM_RATR_STA_HIGH)
2760                                         {
2761                                                 rate_bitmap = 0x000f0000;
2762                                         }
2763                                         else if (rssi_level == DM_RATR_STA_MIDDLE)
2764                                         {
2765                                                 rate_bitmap = 0x000ff000;
2766                                         }
2767                                         else {
2768                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
2769                                                         rate_bitmap = 0x000ff015;
2770                                                 else
2771                                                         rate_bitmap = 0x000ff005;
2772                                         }
2773                                 }
2774                                 else
2775                                 {
2776                                         if (rssi_level == DM_RATR_STA_HIGH)
2777                                         {
2778                                                 rate_bitmap = 0x0f8f0000;
2779                                         }
2780                                         else if (rssi_level == DM_RATR_STA_MIDDLE)
2781                                         {
2782                                                 rate_bitmap = 0x0f8ff000;
2783                                         }
2784                                         else
2785                                         {
2786                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
2787                                                         rate_bitmap = 0x0f8ff015;
2788                                                 else
2789                                                         rate_bitmap = 0x0f8ff005;
2790                                         }
2791                                 }
2792                         }
2793                         break;
2794                 default:
2795                 //case WIRELESS_11_24N:
2796                 //case WIRELESS_11_5N:
2797                         if (pDM_Odm->RFType == RF_1T2R)
2798                                 rate_bitmap = 0x000fffff;
2799                         else
2800                                 rate_bitmap = 0x0fffffff;
2801                         break;
2802
2803         }
2804
2805         //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",__func__,rssi_level,WirelessMode,rate_bitmap);
2806         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",rssi_level,WirelessMode,rate_bitmap));
2807
2808         return rate_bitmap;
2809
2810 }
2811 #endif
2812
2813 /*-----------------------------------------------------------------------------
2814  * Function:    odm_RefreshRateAdaptiveMask()
2815  *
2816  * Overview:    Update rate table mask according to rssi
2817  *
2818  * Input:               NONE
2819  *
2820  * Output:              NONE
2821  *
2822  * Return:              NONE
2823  *
2824  * Revised History:
2825  *      When            Who             Remark
2826  *      05/27/2009      hpfan   Create Version 0.
2827  *
2828  *---------------------------------------------------------------------------*/
2829 void
2830 odm_RefreshRateAdaptiveMask(
2831                 PDM_ODM_T               pDM_Odm
2832         )
2833 {
2834         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
2835                 return;
2836         //
2837         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
2838         // at the same time. In the stage2/3, we need to prive universal interface and merge all
2839         // HW dynamic mechanism.
2840         //
2841         switch  (pDM_Odm->SupportPlatform)
2842         {
2843                 case    ODM_MP:
2844                         odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
2845                         break;
2846
2847                 case    ODM_CE:
2848                         odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
2849                         break;
2850
2851                 case    ODM_AP:
2852                 case    ODM_ADSL:
2853                         odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
2854                         break;
2855         }
2856
2857 }
2858
2859 void
2860 odm_RefreshRateAdaptiveMaskMP(
2861                 PDM_ODM_T               pDM_Odm
2862         )
2863 {
2864 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2865         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
2866         PADAPTER                                pTargetAdapter = NULL;
2867         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(pAdapter);
2868         PMGNT_INFO                              pMgntInfo = GetDefaultMgntInfo(pAdapter);
2869         //PRATE_ADAPTIVE                        pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive;
2870         PODM_RATE_ADAPTIVE              pRA = &pDM_Odm->RateAdaptive;
2871
2872         if (pAdapter->bDriverStopped)
2873         {
2874                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
2875                 return;
2876         }
2877
2878         if (!pMgntInfo->bUseRAMask)
2879         {
2880                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
2881                 return;
2882         }
2883
2884         // if default port is connected, update RA table for default port (infrastructure mode only)
2885         if (pAdapter->MgntInfo.mAssoc && (!ACTING_AS_AP(pAdapter)))
2886         {
2887                 if ( ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pRA->RATRState) )
2888                 {
2889                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid);
2890                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pRA->RATRState));
2891                         pAdapter->HalFunc.UpdateHalRAMaskHandler(
2892                                                                         pAdapter,
2893                                                                         false,
2894                                                                         0,
2895                                                                         NULL,
2896                                                                         NULL,
2897                                                                         pRA->RATRState,
2898                                                                         RAMask_Normal);
2899                 }
2900         }
2901
2902         //
2903         // The following part configure AP/VWifi/IBSS rate adaptive mask.
2904         //
2905
2906         if (pMgntInfo->mIbss)
2907         {
2908                 // Target: AP/IBSS peer.
2909                 pTargetAdapter = GetDefaultAdapter(pAdapter);
2910         }
2911         else
2912         {
2913                 pTargetAdapter = GetFirstAPAdapter(pAdapter);
2914         }
2915
2916         // if extension port (softap) is started, updaet RA table for more than one clients associate
2917         if (pTargetAdapter != NULL)
2918         {
2919                 int     i;
2920                 PRT_WLAN_STA    pEntry;
2921                 PRATE_ADAPTIVE     pEntryRA;
2922
2923                 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
2924                 {
2925                         pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
2926                         if (NULL != pEntry)
2927                         {
2928                                 if (pEntry->bAssociated)
2929                                 {
2930                                         pEntryRA = &pEntry->RateAdaptive;
2931                                         if ( ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntryRA->RATRState) )
2932                                         {
2933                                                 ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
2934                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntryRA->RATRState));
2935                                                 pAdapter->HalFunc.UpdateHalRAMaskHandler(
2936                                                                                         pTargetAdapter,
2937                                                                                         false,
2938                                                                                         pEntry->AID+1,
2939                                                                                         pEntry->MacAddr,
2940                                                                                         pEntry,
2941                                                                                         pEntryRA->RATRState,
2942                                                                                         RAMask_Normal);
2943                                         }
2944                                 }
2945                         }
2946                 }
2947         }
2948
2949         if (pMgntInfo->bSetTXPowerTrainingByOid)
2950                 pMgntInfo->bSetTXPowerTrainingByOid = false;
2951 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
2952 }
2953
2954
2955 void
2956 odm_RefreshRateAdaptiveMaskCE(
2957                 PDM_ODM_T               pDM_Odm
2958         )
2959 {
2960 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2961         u1Byte  i;
2962         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
2963
2964         if (pAdapter->bDriverStopped)
2965         {
2966                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
2967                 return;
2968         }
2969
2970         if (!pDM_Odm->bUseRAMask)
2971         {
2972                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
2973                 return;
2974         }
2975
2976         //printk("==> %s\n",__func__);
2977
2978         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
2979                 PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
2980                 if (IS_STA_VALID(pstat) ) {
2981                         if ( true == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level) )
2982                         {
2983                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
2984                                 //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level);
2985                                 rtw_hal_update_ra_mask(pAdapter,i,pstat->rssi_level);
2986                         }
2987
2988                 }
2989         }
2990
2991 #endif
2992 }
2993
2994 void
2995 odm_RefreshRateAdaptiveMaskAPADSL(
2996                 PDM_ODM_T               pDM_Odm
2997         )
2998 {
2999 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
3000         struct rtl8192cd_priv *priv = pDM_Odm->priv;
3001         struct stat_info        *pstat;
3002
3003         if (!priv->pmib->dot11StationConfigEntry.autoRate)
3004                 return;
3005
3006         if (list_empty(&priv->asoc_list))
3007                 return;
3008
3009         list_for_each_entry(pstat, &priv->asoc_list, asoc_list) {
3010                 if (ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, false, &pstat->rssi_level) ) {
3011                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr);
3012                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level));
3013
3014                         add_update_RATid(priv, pstat);
3015                 }
3016         }
3017 #endif
3018 }
3019
3020 // Return Value: bool
3021 // - true: RATRState is changed.
3022 bool
3023 ODM_RAStateCheck(
3024                 PDM_ODM_T               pDM_Odm,
3025                 s4Byte                  RSSI,
3026                 bool                    bForceUpdate,
3027                 pu1Byte                 pRATRState
3028         )
3029 {
3030         PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
3031         const u1Byte GoUpGap = 5;
3032         u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh;
3033         u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh;
3034         u1Byte RATRState;
3035
3036         // Threshold Adjustment:
3037         // when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
3038         // Here GoUpGap is added to solve the boundary's level alternation issue.
3039         switch (*pRATRState)
3040         {
3041                 case DM_RATR_STA_INIT:
3042                 case DM_RATR_STA_HIGH:
3043                         break;
3044
3045                 case DM_RATR_STA_MIDDLE:
3046                         HighRSSIThreshForRA += GoUpGap;
3047                         break;
3048
3049                 case DM_RATR_STA_LOW:
3050                         HighRSSIThreshForRA += GoUpGap;
3051                         LowRSSIThreshForRA += GoUpGap;
3052                         break;
3053
3054                 default:
3055                         ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState) );
3056                         break;
3057         }
3058
3059         // Decide RATRState by RSSI.
3060         if (RSSI > HighRSSIThreshForRA)
3061                 RATRState = DM_RATR_STA_HIGH;
3062         else if (RSSI > LowRSSIThreshForRA)
3063                 RATRState = DM_RATR_STA_MIDDLE;
3064         else
3065                 RATRState = DM_RATR_STA_LOW;
3066         //printk("==>%s,RATRState:0x%02x ,RSSI:%d\n",__func__,RATRState,RSSI);
3067
3068         if ( *pRATRState!=RATRState || bForceUpdate)
3069         {
3070                 ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) );
3071                 *pRATRState = RATRState;
3072                 return true;
3073         }
3074
3075         return false;
3076 }
3077
3078
3079 //============================================================
3080
3081 //3============================================================
3082 //3 Dynamic Tx Power
3083 //3============================================================
3084
3085 void
3086 odm_DynamicTxPowerInit(
3087                 PDM_ODM_T               pDM_Odm
3088         )
3089 {
3090 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3091         PADAPTER        Adapter = pDM_Odm->Adapter;
3092         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
3093         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
3094
3095         #if DEV_BUS_TYPE==RT_USB_INTERFACE
3096         if (RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
3097         {
3098                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
3099                 pMgntInfo->bDynamicTxPowerEnable = true;
3100         }
3101         else
3102         #else
3103         //so 92c pci do not need dynamic tx power? vivi check it later
3104         if (IS_HARDWARE_TYPE_8192D(Adapter))
3105                 pMgntInfo->bDynamicTxPowerEnable = true;
3106         else
3107                 pMgntInfo->bDynamicTxPowerEnable = false;
3108         #endif
3109
3110
3111         pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
3112         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3113 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3114         PADAPTER        Adapter = pDM_Odm->Adapter;
3115         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3116         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3117         pdmpriv->bDynamicTxPowerEnable = false;
3118
3119         #if (RTL8192C_SUPPORT==1)
3120
3121         #ifdef CONFIG_INTEL_PROXIM
3122         if ((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==true))
3123         #else
3124         if (pHalData->BoardType == BOARD_USB_High_PA)
3125         #endif
3126
3127         {
3128                 //odm_SavePowerIndex(Adapter);
3129                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
3130                 pdmpriv->bDynamicTxPowerEnable = true;
3131         }
3132         else
3133         #endif
3134
3135         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
3136         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3137
3138 #endif
3139
3140 }
3141
3142 void
3143 odm_DynamicTxPowerSavePowerIndex(
3144                 PDM_ODM_T               pDM_Odm
3145         )
3146 {
3147         u1Byte          index;
3148         u4Byte          Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
3149
3150 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3151         PADAPTER        Adapter = pDM_Odm->Adapter;
3152         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3153         for (index = 0; index< 6; index++)
3154                 pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
3155 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3156         PADAPTER        Adapter = pDM_Odm->Adapter;
3157         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3158         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3159         for (index = 0; index< 6; index++)
3160                 pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
3161 #endif
3162 }
3163
3164 void
3165 odm_DynamicTxPowerRestorePowerIndex(
3166                 PDM_ODM_T               pDM_Odm
3167         )
3168 {
3169         u1Byte                  index;
3170         PADAPTER                Adapter = pDM_Odm->Adapter;
3171
3172 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
3173         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3174         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
3175 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3176         for (index = 0; index< 6; index++)
3177                 PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
3178 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3179         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3180         for (index = 0; index< 6; index++)
3181                 rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
3182 #endif
3183 #endif
3184 }
3185
3186 void
3187 odm_DynamicTxPowerWritePowerIndex(
3188         PDM_ODM_T       pDM_Odm,
3189         u1Byte          Value)
3190 {
3191
3192         u1Byte                  index;
3193         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
3194
3195         for (index = 0; index< 6; index++)
3196                 //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
3197                 ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
3198
3199 }
3200
3201
3202 void
3203 odm_DynamicTxPower(
3204                 PDM_ODM_T               pDM_Odm
3205         )
3206 {
3207         //
3208         // For AP/ADSL use prtl8192cd_priv
3209         // For CE/NIC use PADAPTER
3210         //
3211         //PADAPTER              pAdapter = pDM_Odm->Adapter;
3212 //      prtl8192cd_priv priv            = pDM_Odm->priv;
3213
3214         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
3215                 return;
3216
3217         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
3218         if (pDM_Odm->ExtPA == false)
3219                 return;
3220
3221
3222         //
3223         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
3224         // at the same time. In the stage2/3, we need to prive universal interface and merge all
3225         // HW dynamic mechanism.
3226         //
3227         switch  (pDM_Odm->SupportPlatform)
3228         {
3229                 case    ODM_MP:
3230                 case    ODM_CE:
3231                         odm_DynamicTxPowerNIC(pDM_Odm);
3232                         break;
3233                 case    ODM_AP:
3234                         odm_DynamicTxPowerAP(pDM_Odm);
3235                         break;
3236
3237                 case    ODM_ADSL:
3238                         //odm_DIGAP(pDM_Odm);
3239                         break;
3240         }
3241
3242
3243 }
3244
3245
3246 void
3247 odm_DynamicTxPowerNIC(
3248                 PDM_ODM_T               pDM_Odm
3249         )
3250 {
3251         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
3252                 return;
3253
3254 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
3255
3256         if (pDM_Odm->SupportICType == ODM_RTL8192C)
3257         {
3258                 odm_DynamicTxPower_92C(pDM_Odm);
3259         }
3260         else if (pDM_Odm->SupportICType == ODM_RTL8192D)
3261         {
3262                 odm_DynamicTxPower_92D(pDM_Odm);
3263         }
3264         else if (pDM_Odm->SupportICType & ODM_RTL8188E)
3265         {
3266                 // Add Later.
3267         }
3268         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
3269         {
3270                 // ???
3271                 // This part need to be redefined.
3272         }
3273 #endif
3274 }
3275
3276 void
3277 odm_DynamicTxPowerAP(
3278                 PDM_ODM_T               pDM_Odm
3279
3280         )
3281 {
3282 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3283         prtl8192cd_priv priv            = pDM_Odm->priv;
3284         s4Byte i;
3285
3286         if (!priv->pshare->rf_ft_var.tx_pwr_ctrl)
3287                 return;
3288
3289 #ifdef HIGH_POWER_EXT_PA
3290         if (pDM_Odm->ExtPA)
3291                 tx_power_control(priv);
3292 #endif
3293
3294         /*
3295          *      Check if station is near by to use lower tx power
3296          */
3297
3298         if ((priv->up_time % 3) == 0 )  {
3299                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
3300                         PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
3301                         if (IS_STA_VALID(pstat) ) {
3302                                 if ((pstat->hp_level == 0) && (pstat->rssi > TX_POWER_NEAR_FIELD_THRESH_AP+4))
3303                                         pstat->hp_level = 1;
3304                                 else if ((pstat->hp_level == 1) && (pstat->rssi < TX_POWER_NEAR_FIELD_THRESH_AP))
3305                                         pstat->hp_level = 0;
3306                         }
3307                 }
3308         }
3309
3310 #endif
3311 }
3312
3313
3314 void
3315 odm_DynamicTxPower_92C(
3316         PDM_ODM_T       pDM_Odm
3317         )
3318 {
3319 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3320         PADAPTER Adapter = pDM_Odm->Adapter;
3321         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
3322         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
3323         s4Byte                          UndecoratedSmoothedPWDB;
3324
3325
3326         // STA not connected and AP not connected
3327         if ((!pMgntInfo->bMediaConnect) &&
3328                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
3329         {
3330                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any\n"));
3331                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3332
3333                 //the LastDTPlvl should reset when disconnect,
3334                 //otherwise the tx power level wouldn't change when disconnect and connect again.
3335                 // Maddest 20091220.
3336                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
3337                 return;
3338         }
3339
3340 #if (INTEL_PROXIMITY_SUPPORT == 1)
3341         // Intel set fixed tx power
3342         if (pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
3343         {
3344                 switch (pMgntInfo->IntelProximityModeInfo.PowerOutput) {
3345                         case 1:
3346                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
3347                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
3348                                 break;
3349                         case 2:
3350                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
3351                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_70\n"));
3352                                 break;
3353                         case 3:
3354                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
3355                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_50\n"));
3356                                 break;
3357                         case 4:
3358                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
3359                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_35\n"));
3360                                 break;
3361                         case 5:
3362                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
3363                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_15\n"));
3364                                 break;
3365                         default:
3366                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
3367                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
3368                                 break;
3369                 }
3370         }
3371         else
3372 #endif
3373         {
3374                 if (    (pMgntInfo->bDynamicTxPowerEnable != true) ||
3375                         (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
3376                         pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
3377                 {
3378                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3379                 }
3380                 else
3381                 {
3382                         if (pMgntInfo->bMediaConnect)   // Default port
3383                         {
3384                                 if (ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter))
3385                                 {
3386                                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
3387                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3388                                 }
3389                                 else
3390                                 {
3391                                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
3392                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3393                                 }
3394                         }
3395                         else // associated entry pwdb
3396                         {
3397                                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
3398                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3399                         }
3400
3401                         if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
3402                         {
3403                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
3404                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
3405                         }
3406                         else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
3407                                 (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
3408                         {
3409                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3410                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3411                         }
3412                         else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
3413                         {
3414                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3415                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
3416                         }
3417                 }
3418         }
3419         if ( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl )
3420         {
3421                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d\n" , pHalData->CurrentChannel));
3422                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3423                 if (    (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) &&
3424                         (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal
3425                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
3426                 else if (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
3427                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
3428                 else if (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
3429                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
3430         }
3431         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
3432
3433
3434 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3435
3436         #if (RTL8192C_SUPPORT==1)
3437         PADAPTER Adapter = pDM_Odm->Adapter;
3438         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3439         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3440         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
3441         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
3442         int     UndecoratedSmoothedPWDB;
3443
3444         if (!pdmpriv->bDynamicTxPowerEnable)
3445                 return;
3446
3447 #ifdef CONFIG_INTEL_PROXIM
3448         if (Adapter->proximity.proxim_on== true) {
3449                 struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
3450                 // Intel set fixed tx power
3451                 printk("\n %s  Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d\n",__func__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
3452                 if (prox_priv!=NULL) {
3453                         if (prox_priv->proxim_modeinfo->power_output> 0)
3454                         {
3455                                 switch (prox_priv->proxim_modeinfo->power_output)
3456                                 {
3457                                         case 1:
3458                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_100;
3459                                                 printk("TxHighPwrLevel_100\n");
3460                                                 break;
3461                                         case 2:
3462                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_70;
3463                                                 printk("TxHighPwrLevel_70\n");
3464                                                 break;
3465                                         case 3:
3466                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_50;
3467                                                 printk("TxHighPwrLevel_50\n");
3468                                                 break;
3469                                         case 4:
3470                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_35;
3471                                                 printk("TxHighPwrLevel_35\n");
3472                                                 break;
3473                                         case 5:
3474                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_15;
3475                                                 printk("TxHighPwrLevel_15\n");
3476                                                 break;
3477                                         default:
3478                                                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
3479                                                 printk("TxHighPwrLevel_100\n");
3480                                                 break;
3481                                 }
3482                         }
3483                 }
3484         }
3485         else
3486 #endif
3487         {
3488                 // STA not connected and AP not connected
3489                 if ((check_fwstate(pmlmepriv, _FW_LINKED) != true) &&
3490                         (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
3491                 {
3492                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any\n"));
3493                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3494
3495                         //the LastDTPlvl should reset when disconnect,
3496                         //otherwise the tx power level wouldn't change when disconnect and connect again.
3497                         // Maddest 20091220.
3498                         pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
3499                         return;
3500                 }
3501
3502                 if (check_fwstate(pmlmepriv, _FW_LINKED) == true)       // Default port
3503                 {
3504                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
3505                 }
3506                 else // associated entry pwdb
3507                 {
3508                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
3509                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3510                 }
3511
3512                 if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
3513                 {
3514                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
3515                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
3516                 }
3517                 else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
3518                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
3519                 {
3520                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3521                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3522                 }
3523                 else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
3524                 {
3525                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3526                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
3527                 }
3528         }
3529         if ( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
3530         {
3531                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3532                 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal  or HP2 -> Normal
3533                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
3534                 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
3535                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
3536                 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
3537                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
3538         }
3539         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
3540         #endif
3541 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3542
3543 }
3544
3545
3546 void
3547 odm_DynamicTxPower_92D(
3548         PDM_ODM_T       pDM_Odm
3549         )
3550 {
3551 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3552         PADAPTER Adapter = pDM_Odm->Adapter;
3553         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
3554         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
3555         s4Byte                          UndecoratedSmoothedPWDB;
3556
3557         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
3558         bool            bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter);
3559         u1Byte          HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
3560
3561
3562         // If dynamic high power is disabled.
3563         if ( (pMgntInfo->bDynamicTxPowerEnable != true) ||
3564                 (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
3565                 pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
3566         {
3567                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3568                 return;
3569         }
3570
3571         // STA not connected and AP not connected
3572         if ((!pMgntInfo->bMediaConnect) &&
3573                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
3574         {
3575                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any\n"));
3576                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3577
3578                 //the LastDTPlvl should reset when disconnect,
3579                 //otherwise the tx power level wouldn't change when disconnect and connect again.
3580                 // Maddest 20091220.
3581                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
3582                 return;
3583         }
3584
3585         if (pMgntInfo->bMediaConnect)   // Default port
3586         {
3587                 if (ACTING_AS_AP(Adapter) || pMgntInfo->mIbss)
3588                 {
3589                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
3590                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3591                 }
3592                 else
3593                 {
3594                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
3595                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3596                 }
3597         }
3598         else // associated entry pwdb
3599         {
3600                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
3601                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3602         }
3603
3604         if (IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType92D == 1) {
3605                 if (UndecoratedSmoothedPWDB >= 0x33)
3606                 {
3607                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
3608                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
3609                 }
3610                 else if ((UndecoratedSmoothedPWDB <0x33) &&
3611                         (UndecoratedSmoothedPWDB >= 0x2b) )
3612                 {
3613                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3614                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3615                 }
3616                 else if (UndecoratedSmoothedPWDB < 0x2b)
3617                 {
3618                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3619                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
3620                 }
3621
3622         }
3623         else
3624
3625         {
3626                 if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
3627                 {
3628                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3629                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
3630                 }
3631                 else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
3632                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
3633                 {
3634                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3635                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3636                 }
3637                 else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
3638                 {
3639                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3640                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
3641                 }
3642
3643         }
3644
3645 //sherry  delete flag 20110517
3646         if (bGetValueFromBuddyAdapter)
3647         {
3648                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1\n"));
3649                 if (Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
3650                 {
3651                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value\n"));
3652                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
3653                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
3654                         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3655                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
3656                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = false;
3657                 }
3658         }
3659
3660         if ( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) )
3661         {
3662                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d\n" , pHalData->CurrentChannel));
3663                         if (Adapter->DualMacSmartConcurrent == true)
3664                         {
3665                                 if (BuddyAdapter == NULL)
3666                                 {
3667                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case\n"));
3668                                         if (!Adapter->bSlaveOfDMSP)
3669                                         {
3670                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3671                                         }
3672                                 }
3673                                 else
3674                                 {
3675                                         if (pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
3676                                         {
3677                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP\n"));
3678                                                 if (Adapter->bSlaveOfDMSP)
3679                                                 {
3680                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
3681                                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = true;
3682                                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
3683                                                 }
3684                                                 else
3685                                                 {
3686                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
3687                                                         if (!bGetValueFromBuddyAdapter)
3688                                                         {
3689                                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0\n"));
3690                                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3691                                                         }
3692                                                 }
3693                                         }
3694                                         else
3695                                         {
3696                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
3697                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3698                                         }
3699                                 }
3700                         }
3701                         else
3702                         {
3703                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
3704                         }
3705
3706                 }
3707         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
3708 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3709 #if (RTL8192D_SUPPORT==1)
3710         PADAPTER Adapter = pDM_Odm->Adapter;
3711         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3712         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
3713
3714         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3715         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3716         int     UndecoratedSmoothedPWDB;
3717         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
3718         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
3719         bool            bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
3720         u8              HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
3721         #endif
3722
3723         // If dynamic high power is disabled.
3724         if ( (pdmpriv->bDynamicTxPowerEnable != true) ||
3725                 (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
3726         {
3727                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3728                 return;
3729         }
3730
3731         // STA not connected and AP not connected
3732         if ((check_fwstate(pmlmepriv, _FW_LINKED) != true) &&
3733                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
3734         {
3735                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any\n"));
3736                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3737                 //the LastDTPlvl should reset when disconnect,
3738                 //otherwise the tx power level wouldn't change when disconnect and connect again.
3739                 // Maddest 20091220.
3740                 pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
3741                 return;
3742         }
3743
3744         if (check_fwstate(pmlmepriv, _FW_LINKED) == true)       // Default port
3745         {
3746         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
3747         }
3748         else // associated entry pwdb
3749         {
3750                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
3751                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", UndecoratedSmoothedPWDB));
3752         }
3753 #if TX_POWER_FOR_5G_BAND == 1
3754         if (pHalData->CurrentBandType92D == BAND_ON_5G) {
3755                 if (UndecoratedSmoothedPWDB >= 0x33)
3756                 {
3757                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
3758                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
3759                 }
3760                 else if ((UndecoratedSmoothedPWDB <0x33) &&
3761                         (UndecoratedSmoothedPWDB >= 0x2b) )
3762                 {
3763                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3764                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3765                 }
3766                 else if (UndecoratedSmoothedPWDB < 0x2b)
3767                 {
3768                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3769                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
3770                 }
3771         }
3772         else
3773 #endif
3774         {
3775                 if (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
3776                 {
3777                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
3778                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
3779                 }
3780                 else if ((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
3781                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
3782                 {
3783                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
3784                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
3785                 }
3786                 else if (UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
3787                 {
3788                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
3789                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
3790                 }
3791         }
3792 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
3793         if (bGetValueFromBuddyAdapter)
3794         {
3795                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1\n"));
3796                 if (Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
3797                 {
3798                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value\n"));
3799                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
3800                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
3801                         PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
3802                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
3803                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = false;
3804                 }
3805         }
3806 #endif
3807
3808         if ( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
3809         {
3810                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d\n" , pHalData->CurrentChannel));
3811 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
3812                 if (BuddyAdapter == NULL)
3813                 {
3814                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case\n"));
3815                         if (!Adapter->bSlaveOfDMSP)
3816                         {
3817                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
3818                         }
3819                 }
3820                 else
3821                 {
3822                         if (pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
3823                         {
3824                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP\n"));
3825                                 if (Adapter->bSlaveOfDMSP)
3826                                 {
3827                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case \n"));
3828                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = true;
3829                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
3830                                 }
3831                                 else
3832                                 {
3833                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case \n"));
3834                                         if (!bGetValueFromBuddyAdapter)
3835                                         {
3836                                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0\n"));
3837                                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
3838                                         }
3839                                 }
3840                         }
3841                         else
3842                         {
3843                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
3844                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
3845                         }
3846                 }
3847 #else
3848                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
3849 #endif
3850         }
3851         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
3852 #endif
3853 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3854
3855 }
3856
3857
3858 //3============================================================
3859 //3 RSSI Monitor
3860 //3============================================================
3861
3862 void
3863 odm_RSSIMonitorInit(
3864         PDM_ODM_T       pDM_Odm
3865         )
3866 {
3867 }
3868
3869 void
3870 odm_RSSIMonitorCheck(
3871                 PDM_ODM_T               pDM_Odm
3872         )
3873 {
3874         //
3875         // For AP/ADSL use prtl8192cd_priv
3876         // For CE/NIC use PADAPTER
3877         //
3878         PADAPTER                pAdapter = pDM_Odm->Adapter;
3879         prtl8192cd_priv priv            = pDM_Odm->priv;
3880
3881         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
3882                 return;
3883
3884         //
3885         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
3886         // at the same time. In the stage2/3, we need to prive universal interface and merge all
3887         // HW dynamic mechanism.
3888         //
3889         switch  (pDM_Odm->SupportPlatform)
3890         {
3891                 case    ODM_MP:
3892                         odm_RSSIMonitorCheckMP(pDM_Odm);
3893                         break;
3894
3895                 case    ODM_CE:
3896                         odm_RSSIMonitorCheckCE(pDM_Odm);
3897                         break;
3898
3899                 case    ODM_AP:
3900                         odm_RSSIMonitorCheckAP(pDM_Odm);
3901                         break;
3902
3903                 case    ODM_ADSL:
3904                         //odm_DIGAP(pDM_Odm);
3905                         break;
3906         }
3907
3908 }       // odm_RSSIMonitorCheck
3909
3910
3911 void
3912 odm_RSSIMonitorCheckMP(
3913         PDM_ODM_T       pDM_Odm
3914         )
3915 {
3916 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3917         PADAPTER        Adapter = pDM_Odm->Adapter;
3918         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3919         PRT_WLAN_STA    pEntry;
3920         u1Byte                  i;
3921         s4Byte                  tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
3922
3923         RTPRINT(FDM, DM_PWDB, ("pHalData->UndecoratedSmoothedPWDB = 0x%x( %d)\n",
3924                 pHalData->UndecoratedSmoothedPWDB,
3925                 pHalData->UndecoratedSmoothedPWDB));
3926
3927         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
3928         {
3929                 if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
3930                 {
3931                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
3932                 }
3933                 else
3934                 {
3935                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
3936                 }
3937
3938                 if (pEntry!=NULL)
3939                 {
3940                         if (pEntry->bAssociated)
3941                         {
3942                                 RTPRINT_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr);
3943                                 RTPRINT(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n",
3944                                         pEntry->rssi_stat.UndecoratedSmoothedPWDB,
3945                                         pEntry->rssi_stat.UndecoratedSmoothedPWDB));
3946                                 if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
3947                                         tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
3948                                 if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
3949                                         tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
3950                         }
3951                 }
3952                 else
3953                 {
3954                         break;
3955                 }
3956         }
3957
3958         if (tmpEntryMaxPWDB != 0)       // If associated entry is found
3959         {
3960                 pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
3961                 RTPRINT(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n",
3962                         tmpEntryMaxPWDB, tmpEntryMaxPWDB));
3963         }
3964         else
3965         {
3966                 pHalData->EntryMaxUndecoratedSmoothedPWDB = 0;
3967         }
3968         if (tmpEntryMinPWDB != 0xff) // If associated entry is found
3969         {
3970                 pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
3971                 RTPRINT(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n",
3972                                         tmpEntryMinPWDB, tmpEntryMinPWDB));
3973         }
3974         else
3975         {
3976                 pHalData->EntryMinUndecoratedSmoothedPWDB = 0;
3977         }
3978
3979         // Indicate Rx signal strength to FW.
3980         if (Adapter->MgntInfo.bUseRAMask)
3981         {
3982                 u1Byte  H2C_Parameter[3] ={0};
3983         //      DbgPrint("RxSS: %lx =%ld\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB);
3984                 H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF);
3985                 H2C_Parameter[1] = 0x20;   // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
3986
3987                 ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter);
3988         }
3989         else
3990         {
3991                 PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB);
3992                 //DbgPrint("0x4fe write %x %d\n", pHalData->UndecoratedSmoothedPWDB, pHalData->UndecoratedSmoothedPWDB);
3993         }
3994 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
3995 }
3996
3997 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3998 //
3999 //sherry move from DUSC to here 20110517
4000 //
4001 static void
4002 FindMinimumRSSI_Dmsp(
4003         PADAPTER        pAdapter
4004 )
4005 {
4006 }
4007
4008 static void
4009 FindMinimumRSSI(
4010 PADAPTER        pAdapter
4011         )
4012 {
4013         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4014         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4015         struct mlme_priv        *pmlmepriv = &pAdapter->mlmepriv;
4016
4017         //1 1.Determine the minimum RSSI
4018
4019
4020 #ifdef CONFIG_CONCURRENT_MODE
4021         //      FindMinimumRSSI()       per-adapter
4022         if (rtw_buddy_adapter_up(pAdapter)) {
4023                 PADAPTER pbuddy_adapter = pAdapter->pbuddy_adapter;
4024                 PHAL_DATA_TYPE  pbuddy_HalData = GET_HAL_DATA(pbuddy_adapter);
4025                 struct dm_priv *pbuddy_dmpriv = &pbuddy_HalData->dmpriv;
4026
4027                 if ((pdmpriv->EntryMinUndecoratedSmoothedPWDB != 0) &&
4028                   (pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB != 0))
4029                 {
4030
4031                         if (pdmpriv->EntryMinUndecoratedSmoothedPWDB > pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB)
4032                                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB;
4033              }
4034                 else
4035                 {
4036                         if (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)
4037                               pdmpriv->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB;
4038
4039                 }
4040         }
4041 #endif
4042
4043         if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) &&
4044                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
4045                 pdmpriv->MinUndecoratedPWDBForDM = 0;
4046         if (check_fwstate(pmlmepriv, _FW_LINKED) == true)       // Default port
4047         {
4048                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4049         }
4050         else // associated entry pwdb
4051         {
4052                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4053                 //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("AP Ext Port or disconnet PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM));
4054         }
4055         #if (RTL8192D_SUPPORT==1)
4056         FindMinimumRSSI_Dmsp(pAdapter);
4057         #endif
4058 }
4059 #endif
4060
4061 void
4062 odm_RSSIMonitorCheckCE(
4063                 PDM_ODM_T               pDM_Odm
4064         )
4065 {
4066 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4067         PADAPTER        Adapter = pDM_Odm->Adapter;
4068         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4069         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4070         int     i;
4071         int     tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
4072         u8      sta_cnt=0;
4073         u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi
4074
4075         if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)
4076                 #ifdef CONFIG_CONCURRENT_MODE
4077                 && !check_buddy_fwstate(Adapter, _FW_LINKED)
4078                 #endif
4079         ) {
4080                 return;
4081         }
4082
4083         //if (check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == true)
4084         {
4085                 #if 1
4086                 struct sta_info *psta;
4087                 struct sta_priv *pstapriv = &Adapter->stapriv;
4088                 u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
4089
4090                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
4091                         if (IS_STA_VALID(psta = pDM_Odm->pODM_StaInfo[i])
4092                                 && (psta->state & WIFI_ASOC_STATE)
4093                                 && _rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) == false
4094                                 && _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN) == false
4095                                 #ifdef CONFIG_CONCURRENT_MODE
4096                                 && (!Adapter->pbuddy_adapter || _rtw_memcmp(psta->hwaddr, myid(&Adapter->pbuddy_adapter->eeprompriv), ETH_ALEN) == false)
4097                                 #endif
4098                                 ) {
4099                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
4100                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
4101
4102                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
4103                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
4104
4105                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
4106                                                 #if (RTL8192D_SUPPORT==1)
4107                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
4108                                                 #else
4109                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
4110                                                 #endif
4111                                         }
4112                         }
4113                 }
4114                 #else
4115                 unsigned long irqL;
4116                 _list   *plist, *phead;
4117                 struct sta_info *psta;
4118                 struct sta_priv *pstapriv = &Adapter->stapriv;
4119                 u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
4120
4121                 _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
4122
4123                 for (i=0; i< NUM_STA; i++)
4124                 {
4125                         phead = &(pstapriv->sta_hash[i]);
4126                         plist = get_next(phead);
4127
4128                         while ((rtw_end_of_queue_search(phead, plist)) == false)
4129                         {
4130                                 psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
4131
4132                                 plist = get_next(plist);
4133
4134                                 if (_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) ||
4135                                         _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN))
4136                                         continue;
4137
4138                                 if (psta->state & WIFI_ASOC_STATE)
4139                                 {
4140
4141                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
4142                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
4143
4144                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
4145                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
4146
4147                                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
4148                                                 //printk("%s==> mac_id(%d),rssi(%d)\n",__func__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB);
4149                                                 #if (RTL8192D_SUPPORT==1)
4150                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
4151                                                 #else
4152                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
4153                                                 #endif
4154                                         }
4155                                 }
4156
4157                         }
4158
4159                 }
4160
4161                 _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
4162                 #endif
4163
4164                 //printk("%s==> sta_cnt(%d)\n",__func__,sta_cnt);
4165
4166                 for (i=0; i< sta_cnt; i++)
4167                 {
4168                         if (PWDB_rssi[i] != (0)) {
4169                                 if (pHalData->fw_ractrl == true)// Report every sta's RSSI to FW
4170                                 {
4171                                         #if (RTL8192D_SUPPORT==1)
4172                                         FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i]));
4173                                         #elif ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
4174                                         rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]);
4175                                         #endif
4176                                 }
4177                                 else {
4178                                         #if ((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1))
4179                                         ODM_RA_SetRSSI_8188E(
4180                                         &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
4181                                         #endif
4182                                 }
4183                         }
4184                 }
4185         }
4186
4187         if (tmpEntryMaxPWDB != 0)       // If associated entry is found
4188         {
4189                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
4190         }
4191         else
4192         {
4193                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
4194         }
4195
4196         if (tmpEntryMinPWDB != 0xff) // If associated entry is found
4197         {
4198                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
4199         }
4200         else
4201         {
4202                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
4203         }
4204
4205         FindMinimumRSSI(Adapter);
4206         ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
4207 #endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4208 }
4209 void
4210 odm_RSSIMonitorCheckAP(
4211                 PDM_ODM_T               pDM_Odm
4212         )
4213 {
4214 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4215
4216         u4Byte i;
4217         PSTA_INFO_T pstat;
4218
4219         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
4220         {
4221                 pstat = pDM_Odm->pODM_StaInfo[i];
4222                 if (IS_STA_VALID(pstat) )
4223                 {
4224 #ifdef STA_EXT
4225                         if (REMAP_AID(pstat) < (FW_NUM_STAT - 1))
4226 #endif
4227                                 add_update_rssi(pDM_Odm->priv, pstat);
4228
4229                 }
4230         }
4231 #endif
4232
4233 }
4234
4235 void
4236 ODM_InitAllTimers(
4237         PDM_ODM_T       pDM_Odm
4238         )
4239 {
4240         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer,
4241                 (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer");
4242
4243 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
4244 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
4245 #if (RTL8188E_SUPPORT == 1)
4246         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer,
4247                 (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer");
4248 #endif
4249 #endif
4250 #endif
4251
4252 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4253         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer,
4254                 (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer");
4255         //
4256         //Path Diversity
4257         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
4258         //
4259         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer,
4260                 (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer");
4261
4262         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer,
4263                 (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer");
4264
4265         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer,
4266                 (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer");
4267 #endif
4268 }
4269
4270 void
4271 ODM_CancelAllTimers(
4272         PDM_ODM_T       pDM_Odm
4273         )
4274 {
4275 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4276         //
4277         // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in
4278         // win7 platform.
4279         //
4280         HAL_ADAPTER_STS_CHK(pDM_Odm)
4281 #endif
4282
4283         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
4284
4285 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4286
4287 #if (RTL8188E_SUPPORT == 1)
4288         ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
4289 #endif
4290         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
4291         //
4292         //Path Diversity
4293         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
4294         //
4295         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
4296
4297         ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
4298
4299         ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
4300 #endif
4301 }
4302
4303
4304 void
4305 ODM_ReleaseAllTimers(
4306         PDM_ODM_T       pDM_Odm
4307         )
4308 {
4309         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
4310
4311 #if (RTL8188E_SUPPORT == 1)
4312         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
4313 #endif
4314
4315 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4316
4317         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer);
4318         //
4319         //Path Diversity
4320         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
4321         //
4322         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
4323
4324         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
4325
4326         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
4327 #endif
4328 }
4329
4330
4331
4332 //#endif
4333 //3============================================================
4334 //3 Tx Power Tracking
4335 //3============================================================
4336
4337 void
4338 odm_TXPowerTrackingInit(
4339         PDM_ODM_T       pDM_Odm
4340         )
4341 {
4342         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
4343 }
4344
4345
4346 void
4347 odm_TXPowerTrackingThermalMeterInit(
4348         PDM_ODM_T       pDM_Odm
4349         )
4350 {
4351 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4352         PADAPTER                Adapter = pDM_Odm->Adapter;
4353         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
4354         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4355
4356         pMgntInfo->bTXPowerTracking = true;
4357         pHalData->TXPowercount       = 0;
4358         pHalData->bTXPowerTrackingInit = false;
4359         #if     MP_DRIVER != 1                                  //for mp driver, turn off txpwrtracking as default
4360         pHalData->TxPowerTrackControl = true;
4361         #endif//#if     (MP_DRIVER != 1)
4362         ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking));
4363 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4364         {
4365                 PADAPTER                Adapter = pDM_Odm->Adapter;
4366                 HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4367                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4368
4369                 pdmpriv->bTXPowerTracking = true;
4370                 pdmpriv->TXPowercount = 0;
4371                 pdmpriv->bTXPowerTrackingInit = false;
4372
4373                 if (*(pDM_Odm->mp_mode) != 1)
4374                         pdmpriv->TxPowerTrackControl = true;
4375                 MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
4376
4377         }
4378 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
4379         #ifdef RTL8188E_SUPPORT
4380         {
4381                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
4382                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
4383                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
4384                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
4385         }
4386         #endif
4387 #endif
4388
4389     pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
4390 }
4391
4392
4393 void
4394 ODM_TXPowerTrackingCheck(
4395                 PDM_ODM_T               pDM_Odm
4396         )
4397 {
4398         //
4399         // For AP/ADSL use prtl8192cd_priv
4400         // For CE/NIC use PADAPTER
4401         //
4402         PADAPTER                pAdapter = pDM_Odm->Adapter;
4403         prtl8192cd_priv priv            = pDM_Odm->priv;
4404
4405         //if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
4406                 //return;
4407
4408         //
4409         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4410         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4411         // HW dynamic mechanism.
4412         //
4413         switch  (pDM_Odm->SupportPlatform)
4414         {
4415                 case    ODM_MP:
4416                         odm_TXPowerTrackingCheckMP(pDM_Odm);
4417                         break;
4418
4419                 case    ODM_CE:
4420                         odm_TXPowerTrackingCheckCE(pDM_Odm);
4421                         break;
4422
4423                 case    ODM_AP:
4424                         odm_TXPowerTrackingCheckAP(pDM_Odm);
4425                         break;
4426
4427                 case    ODM_ADSL:
4428                         //odm_DIGAP(pDM_Odm);
4429                         break;
4430         }
4431
4432 }
4433
4434 void
4435 odm_TXPowerTrackingCheckCE(
4436                 PDM_ODM_T               pDM_Odm
4437         )
4438 {
4439 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4440         PADAPTER        Adapter = pDM_Odm->Adapter;
4441         #if ( (RTL8192C_SUPPORT==1) ||  (RTL8723A_SUPPORT==1) )
4442         rtl8192c_odm_CheckTXPowerTracking(Adapter);
4443         #endif
4444
4445         #if (RTL8192D_SUPPORT==1)
4446         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
4447         if (!Adapter->bSlaveOfDMSP)
4448         #endif
4449                 rtl8192d_odm_CheckTXPowerTracking(Adapter);
4450         #endif
4451         #if (RTL8188E_SUPPORT==1)
4452
4453         //if (!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/)
4454         if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
4455         {
4456                 return;
4457         }
4458
4459         if (!pDM_Odm->RFCalibrateInfo.TM_Trigger)               //at least delay 1 sec
4460         {
4461                 //pHalData->TxPowerCheckCnt++;  //cosa add for debug
4462                 //ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
4463                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
4464                 //DBG_8192C("Trigger 92C Thermal Meter!!\n");
4465
4466                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
4467                 return;
4468
4469         }
4470         else
4471         {
4472                 //DBG_8192C("Schedule TxPowerTracking direct call!!\n");
4473                 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
4474                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
4475         }
4476         #endif
4477
4478 #endif
4479 }
4480
4481 void
4482 odm_TXPowerTrackingCheckMP(
4483                 PDM_ODM_T               pDM_Odm
4484         )
4485 {
4486 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4487         PADAPTER        Adapter = pDM_Odm->Adapter;
4488
4489         if (ODM_CheckPowerStatus(Adapter) == false)
4490                 return;
4491
4492         if (IS_HARDWARE_TYPE_8723A(Adapter))
4493                 return;
4494
4495         if (!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == false)
4496                 odm_TXPowerTrackingThermalMeterCheck(Adapter);
4497 #endif
4498
4499 }
4500
4501
4502 void
4503 odm_TXPowerTrackingCheckAP(
4504                 PDM_ODM_T               pDM_Odm
4505         )
4506 {
4507 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4508         prtl8192cd_priv priv            = pDM_Odm->priv;
4509
4510 #endif
4511
4512 }
4513
4514 //antenna mapping info
4515 // 1: right-side antenna
4516 // 2/0: left-side antenna
4517 //PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1
4518 //PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2
4519 // We select left antenna as default antenna in initial process, modify it as needed
4520 //
4521
4522 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
4523
4524 void
4525 odm_TXPowerTrackingThermalMeterCheck(
4526         PADAPTER                Adapter
4527         )
4528 {
4529 #ifndef AP_BUILD_WORKAROUND
4530 #if (HAL_CODE_BASE==RTL8192_C)
4531         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4532         //HAL_DATA_TYPE                 *pHalData = GET_HAL_DATA(Adapter);
4533         static u1Byte                   TM_Trigger = 0;
4534         //u1Byte                                        TxPowerCheckCnt = 5;    //10 sec
4535
4536         if (!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/)
4537         {
4538                 return;
4539         }
4540
4541         if (!TM_Trigger)                //at least delay 1 sec
4542         {
4543                 if (IS_HARDWARE_TYPE_8192D(Adapter))
4544                         PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03);
4545                 else if (IS_HARDWARE_TYPE_8188E(Adapter))
4546                         PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
4547                 else
4548                         PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
4549                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n"));
4550
4551                 TM_Trigger = 1;
4552                 return;
4553         }
4554         else
4555         {
4556                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
4557                 odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
4558                 TM_Trigger = 0;
4559         }
4560 #endif
4561 #endif
4562 }
4563
4564 #endif
4565
4566
4567
4568 //3============================================================
4569 //3 SW Antenna Diversity
4570 //3============================================================
4571 #if (defined(CONFIG_SW_ANTENNA_DIVERSITY))
4572 void
4573 odm_SwAntDivInit(
4574                 PDM_ODM_T               pDM_Odm
4575         )
4576 {
4577 #if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
4578         odm_SwAntDivInit_NIC(pDM_Odm);
4579 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
4580         dm_SW_AntennaSwitchInit(pDM_Odm->priv);
4581 #endif
4582 }
4583 #if (RTL8723A_SUPPORT==1)
4584 // Only for 8723A SW ANT DIV INIT--2012--07--17
4585 void
4586 odm_SwAntDivInit_NIC_8723A(
4587         PDM_ODM_T               pDM_Odm)
4588 {
4589         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4590         PADAPTER                Adapter = pDM_Odm->Adapter;
4591         u1Byte                  btAntNum=BT_GetPGAntNum(Adapter);
4592
4593
4594         if (IS_HARDWARE_TYPE_8723A(Adapter))
4595         {
4596                 pDM_SWAT_Table->ANTA_ON =true;
4597
4598                 // Set default antenna B status by PG
4599                 if (btAntNum == Ant_x2)
4600                         pDM_SWAT_Table->ANTB_ON = true;
4601                 else if (btAntNum ==Ant_x1)
4602                         pDM_SWAT_Table->ANTB_ON = false;
4603                 else
4604                         pDM_SWAT_Table->ANTB_ON = true;
4605         }
4606
4607 }
4608 #endif
4609 void
4610 odm_SwAntDivInit_NIC(
4611                 PDM_ODM_T               pDM_Odm
4612         )
4613 {
4614         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4615 // Init SW ANT DIV mechanism for 8723AE/AU/AS// Neil Chen--2012--07--17---
4616 // CE/AP/ADSL no using SW ANT DIV for 8723A Series IC
4617 //#if (DM_ODM_SUPPORT_TYPE==ODM_MP)
4618 #if (RTL8723A_SUPPORT==1)
4619         if (pDM_Odm->SupportICType == ODM_RTL8723A)
4620         {
4621                 odm_SwAntDivInit_NIC_8723A(pDM_Odm);
4622         }
4623 #endif
4624         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n"));
4625         pDM_SWAT_Table->RSSI_sum_A = 0;
4626         pDM_SWAT_Table->RSSI_cnt_A = 0;
4627         pDM_SWAT_Table->RSSI_sum_B = 0;
4628         pDM_SWAT_Table->RSSI_cnt_B = 0;
4629         pDM_SWAT_Table->CurAntenna = Antenna_A;
4630         pDM_SWAT_Table->PreAntenna = Antenna_A;
4631         pDM_SWAT_Table->try_flag = 0xff;
4632         pDM_SWAT_Table->PreRSSI = 0;
4633         pDM_SWAT_Table->SWAS_NoLink_State = 0;
4634         pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
4635         pDM_SWAT_Table->SelectAntennaMap=0xAA;
4636         pDM_SWAT_Table->lastTxOkCnt = 0;
4637         pDM_SWAT_Table->lastRxOkCnt = 0;
4638         pDM_SWAT_Table->TXByteCnt_A = 0;
4639         pDM_SWAT_Table->TXByteCnt_B = 0;
4640         pDM_SWAT_Table->RXByteCnt_A = 0;
4641         pDM_SWAT_Table->RXByteCnt_B = 0;
4642         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
4643         pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860);
4644 }
4645
4646 //
4647 // 20100514 Joseph:
4648 // Add new function to reset the state of antenna diversity before link.
4649 //
4650 void
4651 ODM_SwAntDivResetBeforeLink(
4652                 PDM_ODM_T               pDM_Odm
4653         )
4654 {
4655
4656         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4657
4658         pDM_SWAT_Table->SWAS_NoLink_State = 0;
4659
4660 }
4661
4662 //
4663 // 20100514 Luke/Joseph:
4664 // Add new function to reset antenna diversity state after link.
4665 //
4666 void
4667 ODM_SwAntDivRestAfterLink(
4668         PDM_ODM_T       pDM_Odm
4669         )
4670 {
4671         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4672
4673         pDM_SWAT_Table->RSSI_cnt_A = 0;
4674         pDM_SWAT_Table->RSSI_cnt_B = 0;
4675         pDM_Odm->RSSI_test = false;
4676         pDM_SWAT_Table->try_flag = 0xff;
4677         pDM_SWAT_Table->RSSI_Trying = 0;
4678         pDM_SWAT_Table->SelectAntennaMap=0xAA;
4679 }
4680
4681 void
4682 ODM_SwAntDivChkPerPktRssi(
4683         PDM_ODM_T       pDM_Odm,
4684         u1Byte          StationID,
4685         PODM_PHY_INFO_T pPhyInfo
4686         )
4687 {
4688         SWAT_T          *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4689
4690         if (!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV)))
4691                 return;
4692
4693         if (StationID == pDM_SWAT_Table->RSSI_target)
4694         {
4695                 //1 RSSI for SW Antenna Switch
4696                 if (pDM_SWAT_Table->CurAntenna == Antenna_A)
4697                 {
4698                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
4699                         pDM_SWAT_Table->RSSI_cnt_A++;
4700                 }
4701                 else
4702                 {
4703                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
4704                         pDM_SWAT_Table->RSSI_cnt_B++;
4705
4706                 }
4707         }
4708
4709 }
4710
4711 //
4712 void
4713 odm_SwAntDivChkAntSwitch(
4714                 PDM_ODM_T               pDM_Odm,
4715                 u1Byte                  Step
4716         )
4717 {
4718         //
4719         // For AP/ADSL use prtl8192cd_priv
4720         // For CE/NIC use PADAPTER
4721         //
4722         PADAPTER                pAdapter = pDM_Odm->Adapter;
4723         prtl8192cd_priv priv            = pDM_Odm->priv;
4724
4725         //
4726         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4727         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4728         // HW dynamic mechanism.
4729         //
4730         switch  (pDM_Odm->SupportPlatform)
4731         {
4732                 case    ODM_MP:
4733                 case    ODM_CE:
4734                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
4735                         break;
4736
4737                 case    ODM_AP:
4738                 case    ODM_ADSL:
4739 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP |ODM_ADSL))
4740                         if (priv->pshare->rf_ft_var.antSw_enable && (priv->up_time % 4==1))
4741                                 dm_SW_AntennaSwitch(priv, SWAW_STEP_PEAK);
4742 #endif
4743                         break;
4744         }
4745
4746 }
4747
4748 //
4749 // 20100514 Luke/Joseph:
4750 // Add new function for antenna diversity after link.
4751 // This is the main function of antenna diversity after link.
4752 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
4753 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
4754 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
4755 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
4756 // listened on the air with the RSSI of original antenna.
4757 // It chooses the antenna with better RSSI.
4758 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
4759 // penalty to get next try.
4760
4761
4762 void
4763 ODM_SetAntenna(
4764         PDM_ODM_T       pDM_Odm,
4765         u1Byte          Antenna)
4766 {
4767         ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
4768 }
4769 //--------------------------------2012--09--06--
4770 //Note: Antenna_Main--> Antenna_A
4771 //        Antenna_Aux---> Antenna_B
4772 //----------------------------------
4773 void
4774 odm_SwAntDivChkAntSwitchNIC(
4775                 PDM_ODM_T               pDM_Odm,
4776                 u1Byte          Step
4777         )
4778 {
4779 #if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
4780         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
4781         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4782         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4783         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
4784         u1Byte                  nextAntenna=Antenna_B;
4785         //static u8Byte         lastTxOkCnt=0, lastRxOkCnt=0;
4786         u8Byte                  curTxOkCnt, curRxOkCnt;
4787         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
4788         u8Byte                  CurByteCnt=0, PreByteCnt=0;
4789         //static u1Byte         TrafficLoad = TRAFFIC_LOW;
4790         u1Byte                  Score_A=0, Score_B=0;
4791         u1Byte                  i;
4792
4793         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
4794                 return;
4795
4796         if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E))
4797                 return;
4798
4799         if ((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
4800                 return;
4801
4802         if (pDM_Odm->SupportPlatform & ODM_MP)
4803         {
4804                 if (*(pDM_Odm->pAntennaTest))
4805                         return;
4806         }
4807
4808         if ((pDM_SWAT_Table->ANTA_ON == false) ||(pDM_SWAT_Table->ANTB_ON == false))
4809         {
4810                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
4811                                 ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n"));
4812                 return;
4813         }
4814
4815         // Radio off: Status reset to default and return.
4816         if (*(pDM_Odm->pbPowerSaving)==true) //pHalData->eRFPowerState==eRfOff
4817         {
4818                 ODM_SwAntDivRestAfterLink(pDM_Odm);
4819                 return;
4820         }
4821
4822
4823         // Handling step mismatch condition.
4824         // Peak step is not finished at last time. Recover the variable and check again.
4825         if (    Step != pDM_SWAT_Table->try_flag        )
4826         {
4827                 ODM_SwAntDivRestAfterLink(pDM_Odm);
4828         }
4829
4830 #if  (DM_ODM_SUPPORT_TYPE &( ODM_MP| ODM_CE ))
4831
4832         if (pDM_SWAT_Table->try_flag == 0xff)
4833         {
4834                 pDM_SWAT_Table->RSSI_target = 0xff;
4835
4836                 #if (DM_ODM_SUPPORT_TYPE & ODM_CE)
4837                 {
4838                         u1Byte                  index = 0;
4839                         PSTA_INFO_T             pEntry = NULL;
4840
4841
4842                         for (index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
4843                         {
4844                                 pEntry =  pDM_Odm->pODM_StaInfo[i];
4845                                 if (IS_STA_VALID(pEntry) ) {
4846                                         break;
4847                                 }
4848                         }
4849                         if (pEntry == NULL)
4850                         {
4851                                 ODM_SwAntDivRestAfterLink(pDM_Odm);
4852                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
4853                                 return;
4854                         }
4855                         else
4856                         {
4857                                 pDM_SWAT_Table->RSSI_target = index;
4858                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
4859                         }
4860                 }
4861                 #elif (DM_ODM_SUPPORT_TYPE & ODM_MP)
4862                 {
4863                         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
4864                         PMGNT_INFO      pMgntInfo=&pAdapter->MgntInfo;
4865
4866                         // Select RSSI checking target
4867                         if (pMgntInfo->mAssoc && !ACTING_AS_AP(pAdapter))
4868                         {
4869                                 // Target: Infrastructure mode AP.
4870                                 //pDM_SWAT_Table->RSSI_target = NULL;
4871                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): RSSI_target is DEF AP!\n"));
4872                         }
4873                         else
4874                         {
4875                                 u1Byte                  index = 0;
4876                                 PSTA_INFO_T             pEntry = NULL;
4877                                 PADAPTER                pTargetAdapter = NULL;
4878
4879                                 if (pMgntInfo->mIbss )
4880                                 {
4881                                         // Target: AP/IBSS peer.
4882                                         pTargetAdapter = pAdapter;
4883                                 }
4884                                 else
4885                                 {
4886                                         pTargetAdapter = GetFirstAPAdapter(pAdapter);
4887                                 }
4888
4889                                 if (pTargetAdapter != NULL)
4890                                 {
4891                                         for (index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
4892                                         {
4893
4894                                                 pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
4895                                                 if (pEntry != NULL)
4896                                                 {
4897                                                         if (pEntry->bAssociated)
4898                                                                 break;
4899                                                 }
4900
4901                                         }
4902
4903                                 }
4904
4905                                 if (pEntry == NULL)
4906                                 {
4907                                         ODM_SwAntDivRestAfterLink(pDM_Odm);
4908                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
4909                                         return;
4910                                 }
4911                                 else
4912                                 {
4913                                         //pDM_SWAT_Table->RSSI_target = pEntry;
4914                                         pDM_SWAT_Table->RSSI_target = index;
4915                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
4916                                 }
4917                         }//end if (pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
4918
4919                 }
4920                 #endif
4921
4922                 pDM_SWAT_Table->RSSI_cnt_A = 0;
4923                 pDM_SWAT_Table->RSSI_cnt_B = 0;
4924                 pDM_SWAT_Table->try_flag = 0;
4925                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
4926                 return;
4927         }
4928         else
4929         {
4930 #if (DM_ODM_SUPPORT_TYPE &( ODM_MP))
4931                 //PADAPTER      Adapter = pDM_Odm->Adapter;
4932                 curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt;
4933                 curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt;
4934                 pDM_SWAT_Table->lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast;
4935                 pDM_SWAT_Table->lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast;
4936 #else
4937                 curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt;
4938                 curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt;
4939                 pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
4940                 pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
4941 #endif
4942              ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curTxOkCnt = %lld\n",curTxOkCnt));
4943                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curRxOkCnt = %lld\n",curRxOkCnt));
4944                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastTxOkCnt = %lld\n",pDM_SWAT_Table->lastTxOkCnt));
4945                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastRxOkCnt = %lld\n",pDM_SWAT_Table->lastRxOkCnt));
4946
4947                 if (pDM_SWAT_Table->try_flag == 1)
4948                 {
4949                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
4950                         {
4951                                 pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt;
4952                                 pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt;
4953                         }
4954                         else
4955                         {
4956                                 pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt;
4957                                 pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt;
4958                         }
4959
4960                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
4961                         pDM_SWAT_Table->RSSI_Trying--;
4962                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
4963                         if (pDM_SWAT_Table->RSSI_Trying == 0)
4964                         {
4965                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B);
4966                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A);
4967
4968                                 if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
4969                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
4970                                         PreByteCnt = PreByteCnt*9;
4971                                 else if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
4972                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
4973                                         PreByteCnt = PreByteCnt*2;
4974
4975                                 if (pDM_SWAT_Table->RSSI_cnt_A > 0)
4976                                         RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
4977                                 else
4978                                         RSSI_A = 0;
4979                                 if (pDM_SWAT_Table->RSSI_cnt_B > 0)
4980                                         RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
4981                                 else
4982                                         RSSI_B = 0;
4983                                 curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
4984                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A;
4985                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
4986                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s\n",
4987                                 (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
4988                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
4989                                         RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
4990                         }
4991
4992                 }
4993                 else
4994                 {
4995
4996                         if (pDM_SWAT_Table->RSSI_cnt_A > 0)
4997                                 RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
4998                         else
4999                                 RSSI_A = 0;
5000                         if (pDM_SWAT_Table->RSSI_cnt_B > 0)
5001                                 RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
5002                         else
5003                                 RSSI_B = 0;
5004                         curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
5005                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B;
5006                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
5007                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s\n",
5008                         (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
5009
5010                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
5011                                 RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
5012                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
5013                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
5014                 }
5015
5016                 //1 Trying State
5017                 if ((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
5018                 {
5019
5020                         if (pDM_SWAT_Table->TestMode == TP_MODE)
5021                         {
5022                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE"));
5023                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt));
5024                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt));
5025                                 if (CurByteCnt < PreByteCnt)
5026                                 {
5027                                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
5028                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
5029                                         else
5030                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
5031                                 }
5032                                 else
5033                                 {
5034                                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
5035                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
5036                                         else
5037                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
5038                                 }
5039                                 for (i= 0; i<8; i++)
5040                                 {
5041                                         if (((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
5042                                                 Score_A++;
5043                                         else
5044                                                 Score_B++;
5045                                 }
5046                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
5047                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B));
5048
5049                                 if (pDM_SWAT_Table->CurAntenna == Antenna_A)
5050                                 {
5051                                         nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B;
5052                                 }
5053                                 else
5054                                 {
5055                                         nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A;
5056                                 }
5057                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
5058                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s\n",
5059                                 //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B")));
5060
5061                                 if (nextAntenna != pDM_SWAT_Table->CurAntenna)
5062                                 {
5063                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
5064                                 }
5065                                 else
5066                                 {
5067                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
5068                                 }
5069                         }
5070
5071                         if (pDM_SWAT_Table->TestMode == RSSI_MODE)
5072                         {
5073                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE"));
5074                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
5075                                 if (curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
5076                                 {
5077                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
5078                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
5079                                 }
5080                                 else // current anntena is good
5081                                 {
5082                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
5083                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
5084                                 }
5085                         }
5086                         pDM_SWAT_Table->try_flag = 0;
5087                         pDM_Odm->RSSI_test = false;
5088                         pDM_SWAT_Table->RSSI_sum_A = 0;
5089                         pDM_SWAT_Table->RSSI_cnt_A = 0;
5090                         pDM_SWAT_Table->RSSI_sum_B = 0;
5091                         pDM_SWAT_Table->RSSI_cnt_B = 0;
5092                         pDM_SWAT_Table->TXByteCnt_A = 0;
5093                         pDM_SWAT_Table->TXByteCnt_B = 0;
5094                         pDM_SWAT_Table->RXByteCnt_A = 0;
5095                         pDM_SWAT_Table->RXByteCnt_B = 0;
5096
5097                 }
5098
5099                 //1 Normal State
5100                 else if (pDM_SWAT_Table->try_flag == 0)
5101                 {
5102                         if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
5103                         {
5104                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if (PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
5105                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
5106                                 else
5107                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
5108                         }
5109                         else if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
5110                                 {
5111                                 if ((curTxOkCnt+curRxOkCnt) > 3750000) //if (PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
5112                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
5113                                 else
5114                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
5115                         }
5116                         if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
5117                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
5118                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
5119
5120                         //Prepare To Try Antenna
5121                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
5122                                         pDM_SWAT_Table->try_flag = 1;
5123                                         pDM_Odm->RSSI_test = true;
5124                         if ((curRxOkCnt+curTxOkCnt) > 1000)
5125                         {
5126                                 pDM_SWAT_Table->RSSI_Trying = 4;
5127                                 pDM_SWAT_Table->TestMode = TP_MODE;
5128                                 }
5129                                 else
5130                                 {
5131                                 pDM_SWAT_Table->RSSI_Trying = 2;
5132                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
5133
5134                         }
5135                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
5136
5137
5138                         pDM_SWAT_Table->RSSI_sum_A = 0;
5139                         pDM_SWAT_Table->RSSI_cnt_A = 0;
5140                         pDM_SWAT_Table->RSSI_sum_B = 0;
5141                         pDM_SWAT_Table->RSSI_cnt_B = 0;
5142                 }
5143         }
5144
5145         //1 4.Change TRX antenna
5146         if (nextAntenna != pDM_SWAT_Table->CurAntenna)
5147         {
5148                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n "));
5149                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna);
5150                 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5151                 ODM_SetAntenna(pDM_Odm,nextAntenna);
5152                 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
5153                 {
5154                         bool bEnqueue;
5155                         bEnqueue = (pDM_Odm->SupportInterface ==  ODM_ITRF_PCIE)?false :true;
5156                         rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue);
5157                 }
5158                 #endif
5159
5160         }
5161
5162         //1 5.Reset Statistics
5163         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
5164         pDM_SWAT_Table->CurAntenna = nextAntenna;
5165         pDM_SWAT_Table->PreRSSI = curRSSI;
5166
5167         //1 6.Set next timer
5168         {
5169                 PADAPTER                pAdapter = pDM_Odm->Adapter;
5170                 HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5171
5172
5173         if (pDM_SWAT_Table->RSSI_Trying == 0)
5174                 return;
5175
5176         if (pDM_SWAT_Table->RSSI_Trying%2 == 0)
5177         {
5178                 if (pDM_SWAT_Table->TestMode == TP_MODE)
5179                 {
5180                         if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
5181                         {
5182                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 10 ); //ms
5183                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms
5184
5185                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n"));
5186                         }
5187                         else if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
5188                         {
5189                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 50 ); //ms
5190                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms
5191                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n"));
5192                         }
5193                 }
5194                 else
5195                 {
5196                         //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms
5197                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
5198                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"));
5199                 }
5200         }
5201         else
5202         {
5203                 if (pDM_SWAT_Table->TestMode == TP_MODE)
5204                 {
5205                         if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
5206                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 90 ); //ms
5207                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms
5208                         else if (pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
5209                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 100 ); //ms
5210                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms
5211                 }
5212                 else
5213                         //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms
5214                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms
5215         }
5216         }
5217 #endif  // #if (DM_ODM_SUPPORT_TYPE  & (ODM_MP|ODM_CE))
5218 #endif  // #if (RTL8192C_SUPPORT==1)
5219 }
5220
5221
5222 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5223
5224 u1Byte
5225 odm_SwAntDivSelectChkChnl(
5226         PADAPTER        Adapter
5227         )
5228 {
5229 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
5230         u1Byte  index, target_chnl=0;
5231         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
5232         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
5233         u1Byte  chnl_peer_cnt[14] = {0};
5234
5235         if (Adapter->MgntInfo.tmpNumBssDesc==0)
5236         {
5237                 return 0;
5238         }
5239         else
5240         {
5241                 // 20100519 Joseph: Select checking channel from current scan list.
5242                 // We just choose the channel with most APs to be the test scan channel.
5243                 for (index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
5244                 {
5245                         // Add by hpfan: prevent access invalid channel number
5246                         // TODO: Verify channel number by channel plan
5247                         if (Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber == 0 ||
5248                                 Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber > 13)
5249                                 continue;
5250
5251                         chnl_peer_cnt[Adapter->MgntInfo.tmpbssDesc[index].ChannelNumber-1]++;
5252                 }
5253                 for (index=0; index<14; index++)
5254                 {
5255                         if (chnl_peer_cnt[index]>chnl_peer_cnt[target_chnl])
5256                                 target_chnl = index;
5257                 }
5258                 target_chnl+=1;
5259                 ODM_RT_TRACE(pDM_Odm,COMP_SWAS, DBG_LOUD,
5260                         ("odm_SwAntDivSelectChkChnl(): Channel %d is select as test channel.\n", target_chnl));
5261
5262                 return target_chnl;
5263         }
5264 #else
5265         return  0;
5266 #endif
5267 }
5268
5269
5270 void
5271 odm_SwAntDivConsructChkScanChnl(
5272         PADAPTER        Adapter,
5273         u1Byte          ChkChnl
5274         )
5275 {
5276
5277         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
5278         PRT_CHANNEL_LIST        pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo);
5279         u1Byte                          index;
5280
5281         if (ChkChnl==0)
5282         {
5283                 // 20100519 Joseph: Original antenna scanned nothing.
5284                 // Test antenna shall scan all channel with half period in this condition.
5285                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL);
5286                 for (index=0; index<pChannelList->ChannelLen; index++)
5287                         pChannelList->ChannelInfo[index].ScanPeriod /= 2;
5288         }
5289         else
5290         {
5291                 // The using of this CustomizedScanRequest is a trick to rescan the two channels
5292                 //      under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest.
5293                 CUSTOMIZED_SCAN_REQUEST CustomScanReq;
5294
5295                 CustomScanReq.bEnabled = true;
5296                 CustomScanReq.Channels[0] = ChkChnl;
5297                 CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber;
5298                 CustomScanReq.nChannels = 2;
5299                 CustomScanReq.ScanType = SCAN_ACTIVE;
5300                 CustomScanReq.Duration = DEFAULT_ACTIVE_SCAN_PERIOD;
5301
5302                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL);
5303         }
5304
5305 }
5306 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5307
5308 //
5309 // 20100514 Luke/Joseph:
5310 // Callback function for 500ms antenna test trying.
5311 //
5312 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5313 void
5314 odm_SwAntDivChkAntSwitchCallback(
5315         PRT_TIMER               pTimer
5316 )
5317 {
5318         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
5319         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5320         pSWAT_T         pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;
5321
5322         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
5323         #if USE_WORKITEM
5324         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
5325         #else
5326         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
5327         #endif
5328 #else
5329         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
5330         #endif
5331
5332 }
5333 void
5334 odm_SwAntDivChkAntSwitchWorkitemCallback(
5335     void *            pContext
5336     )
5337 {
5338
5339         PADAPTER                pAdapter = (PADAPTER)pContext;
5340         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5341
5342         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
5343
5344 }
5345 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
5346 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
5347 {
5348         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
5349         PADAPTER        padapter = pDM_Odm->Adapter;
5350         if (padapter->net_closed == true)
5351             return;
5352         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
5353 }
5354 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
5355 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
5356 {
5357         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
5358         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
5359 }
5360 #endif
5361
5362 #else //#if (defined(CONFIG_SW_ANTENNA_DIVERSITY))
5363
5364 void odm_SwAntDivInit(          PDM_ODM_T               pDM_Odm ) {}
5365 void ODM_SwAntDivChkPerPktRssi(
5366         PDM_ODM_T       pDM_Odm,
5367         u1Byte          StationID,
5368         PODM_PHY_INFO_T pPhyInfo
5369         ) {}
5370 void odm_SwAntDivChkAntSwitch(
5371                 PDM_ODM_T               pDM_Odm,
5372                 u1Byte                  Step
5373         ) {}
5374 void ODM_SwAntDivResetBeforeLink(               PDM_ODM_T               pDM_Odm ) {}
5375 void ODM_SwAntDivRestAfterLink(         PDM_ODM_T               pDM_Odm ) {}
5376 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5377 u1Byte odm_SwAntDivSelectChkChnl(       PADAPTER        Adapter ) {     return 0;}
5378 void
5379 odm_SwAntDivConsructChkScanChnl(
5380         PADAPTER        Adapter,
5381         u1Byte          ChkChnl
5382         ) {}
5383 #endif
5384 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5385 void odm_SwAntDivChkAntSwitchCallback(  PRT_TIMER               pTimer) {}
5386 void odm_SwAntDivChkAntSwitchWorkitemCallback(    void *            pContext    ) {}
5387 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
5388 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) {}
5389 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
5390 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) {}
5391 #endif
5392
5393 #endif //#if (defined(CONFIG_SW_ANTENNA_DIVERSITY))
5394
5395 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
5396 #if ((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY)))
5397 bool
5398 ODM_SwAntDivCheckBeforeLink8192C(
5399                 PDM_ODM_T               pDM_Odm
5400         )
5401 {
5402
5403 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
5404         PADAPTER Adapter = pDM_Odm->Adapter;
5405         HAL_DATA_TYPE   *pHalData=NULL;
5406         PMGNT_INFO              pMgntInfo = NULL;
5407         //pSWAT_T                       pDM_SWAT_Table = &Adapter->DM_SWAT_Table;
5408         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5409         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;
5410
5411         s1Byte                  Score = 0;
5412         PRT_WLAN_BSS    pTmpBssDesc;
5413         PRT_WLAN_BSS    pTestBssDesc;
5414
5415         u1Byte                  target_chnl = 0;
5416         u1Byte                  index;
5417
5418 return false;
5419         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
5420         {       // The ODM structure is not initialized.
5421                 return false;
5422         }
5423         // 2012/04/26 MH Prevent no-checked IC to execute antenna diversity.
5424         if (pDM_Odm->SupportICType == ODM_RTL8188E && pDM_Odm->SupportInterface != ODM_ITRF_PCIE)
5425                 return false;
5426         pHalData = GET_HAL_DATA(Adapter);
5427         pMgntInfo = &Adapter->MgntInfo;
5428
5429         // Condition that does not need to use antenna diversity.
5430         if (IS_8723_SERIES(pHalData->VersionID) ||
5431                 IS_92C_SERIAL(pHalData->VersionID) ||
5432                 (pHalData->AntDivCfg==0) ||
5433                 pMgntInfo->AntennaTest ||
5434                 Adapter->bInHctTest)
5435         {
5436                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5437                                 ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism.\n"));
5438                 return false;
5439         }
5440
5441         if (IS_8723_SERIES(pHalData->VersionID) || IS_92C_SERIAL(pHalData->VersionID) )
5442         {
5443                 if ((pDM_SWAT_Table->ANTA_ON == false) ||(pDM_SWAT_Table->ANTB_ON == false))
5444                 {
5445                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5446                                         ("ODM_SwAntDivCheckBeforeLink8192C(): No AntDiv Mechanism, Antenna A or B is off\n"));
5447                         return false;
5448                 }
5449         }
5450
5451         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
5452         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
5453         if (pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
5454         {
5455                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
5456
5457                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5458                                 ("ODM_SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
5459                                 pMgntInfo->RFChangeInProgress,
5460                                 pHalData->eRFPowerState));
5461
5462                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
5463
5464                 return false;
5465         }
5466         else
5467         {
5468                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
5469         }
5470
5471         //1 Run AntDiv mechanism "Before Link" part.
5472         if (pDM_SWAT_Table->SWAS_NoLink_State == 0)
5473         {
5474                 //1 Prepare to do Scan again to check current antenna state.
5475
5476                 // Set check state to next step.
5477                 pDM_SWAT_Table->SWAS_NoLink_State = 1;
5478
5479                 // Copy Current Scan list.
5480                 Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc;
5481                 PlatformMoveMemory((void *)Adapter->MgntInfo.tmpbssDesc, (void *)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
5482
5483                 if (pDM_Odm->SupportICType == ODM_RTL8188E)
5484                 {
5485                         if (pDM_FatTable->RxIdleAnt == MAIN_ANT)
5486                                 ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT);
5487                         else
5488                                 ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
5489
5490                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5491                                 ("ODM_SwAntDivCheckBeforeLink8192C: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
5492                 }
5493                 if (pDM_Odm->SupportICType != ODM_RTL8188E)
5494                 {
5495                 // Switch Antenna to another one.
5496                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
5497                 pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
5498
5499                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5500                         ("ODM_SwAntDivCheckBeforeLink8192C: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
5501                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
5502                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
5503                         ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
5504                 }
5505                 // Go back to scan function again.
5506                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Scan one more time\n"));
5507                 pMgntInfo->ScanStep=0;
5508                 target_chnl = odm_SwAntDivSelectChkChnl(Adapter);
5509                 odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl);
5510                 HTReleaseChnlOpLock(Adapter);
5511                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
5512
5513                 return true;
5514         }
5515         else
5516         {
5517                 //1 ScanComple() is called after antenna swiched.
5518                 //1 Check scan result and determine which antenna is going
5519                 //1 to be used.
5520
5521                 for (index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
5522                 {
5523                         pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]);
5524                         pTestBssDesc = &(pMgntInfo->bssDesc[index]);
5525
5526                         if (PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
5527                         {
5528                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C(): ERROR!! This shall not happen.\n"));
5529                                 continue;
5530                         }
5531
5532                         if (pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
5533                         {
5534                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score++\n"));
5535                                 RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
5536                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
5537
5538                                 Score++;
5539                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
5540                         }
5541                         else if (pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
5542                         {
5543                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink8192C: Compare scan entry: Score--\n"));
5544                                 RT_PRINT_STR(ODM_COMP_ANT_DIV, ODM_DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
5545                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
5546                                 Score--;
5547                         }
5548
5549                 }
5550
5551                 if (pDM_Odm->SupportICType == ODM_RTL8188E)
5552                 {
5553                 if (pMgntInfo->NumBssDesc!=0 && Score<=0)
5554                 {
5555                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5556                                         ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
5557                 }
5558                 else
5559                 {
5560                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5561                                         ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
5562
5563                                 if (pDM_FatTable->RxIdleAnt == MAIN_ANT)
5564                                         ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT);
5565                                 else
5566                                         ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
5567                         }
5568                 }
5569
5570                 if (pDM_Odm->SupportICType != ODM_RTL8188E)
5571                                 {
5572                         if (pMgntInfo->NumBssDesc!=0 && Score<=0)
5573                                 {
5574                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5575                                         ("ODM_SwAntDivCheckBeforeLink8192C(): Using Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_A":"Antenna_B"));
5576
5577                                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
5578                         }
5579                         else
5580                         {
5581                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
5582                                         ("ODM_SwAntDivCheckBeforeLink8192C(): Remain Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"Antenna_B":"Antenna_A"));
5583
5584                                 pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
5585
5586                                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
5587                         pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
5588                         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
5589                 }
5590                 }
5591                 // Check state reset to default and wait for next time.
5592                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
5593
5594                 return false;
5595         }
5596 #else
5597                 return  false;
5598 #endif
5599
5600 return false;
5601 }
5602 #else
5603 bool
5604 ODM_SwAntDivCheckBeforeLink8192C(
5605                 PDM_ODM_T               pDM_Odm
5606         )
5607 {
5608
5609         return false;
5610
5611 }
5612 #endif //#if ((defined(CONFIG_SW_ANTENNA_DIVERSITY))||(defined(CONFIG_HW_ANTENNA_DIVERSITY)))
5613 #endif //#if (DM_ODM_SUPPORT_TYPE==ODM_MP)
5614
5615
5616 //3============================================================
5617 //3 SW Antenna Diversity
5618 //3============================================================
5619
5620 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
5621 void
5622 odm_InitHybridAntDiv_88C_92D(
5623         PDM_ODM_T       pDM_Odm
5624         )
5625 {
5626
5627 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
5628         struct rtl8192cd_priv *priv=pDM_Odm->priv;
5629 #endif
5630         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5631         u1Byte                  bTxPathSel=0;           //0:Path-A   1:Path-B
5632         u1Byte                  i;
5633
5634         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
5635
5636         //whether to do antenna diversity or not
5637 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
5638         if (priv==NULL) return;
5639         if (!priv->pshare->rf_ft_var.antHw_enable)
5640                 return;
5641
5642         #ifdef SW_ANT_SWITCH
5643         priv->pshare->rf_ft_var.antSw_enable =0;
5644         #endif
5645 #endif
5646
5647         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
5648                 return;
5649
5650
5651         bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?false:true;
5652
5653         ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1
5654         ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info
5655         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL
5656         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna
5657         // check HW setting: ANTSEL pin connection
5658         #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
5659         ODM_Write2Byte(pDM_Odm,ODM_REG_RF_PIN_11N, (ODM_Read2Byte(pDM_Odm,0x804)&0xf0ff )| BIT(8) );    // b11-b8=0001,update RFPin setting
5660         #endif
5661
5662         // only AP support different path selection temperarly
5663         if (!bTxPathSel) {                 //PATH-A
5664                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control
5665                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1);         //select TX ANTESEL from path A
5666         }
5667         else    {
5668                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control
5669                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0);                 //select ANTESEL from path B
5670         }
5671
5672         //Set OFDM HW RX Antenna Diversity
5673         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB
5674         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold
5675         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1);       // Decide final antenna by comparing 2 antennas' pwdb
5676
5677         //Set CCK HW RX Antenna Diversity
5678         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample
5679         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4
5680         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0
5681         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16)
5682
5683
5684         //Enable HW Antenna Diversity
5685         if (!bTxPathSel)                 //PATH-A
5686                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1);        // Enable Hardware antenna switch
5687         else
5688                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1);        // Enable Hardware antenna switch
5689         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity
5690
5691         pDM_SWAT_Table->CurAntenna=0;                   //choose left antenna as default antenna
5692         pDM_SWAT_Table->PreAntenna=0;
5693         for (i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
5694         {
5695                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
5696                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
5697                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
5698                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
5699                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
5700                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
5701         }
5702         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n"));
5703 }
5704
5705
5706 void
5707 odm_InitHybridAntDiv(
5708         PDM_ODM_T       pDM_Odm
5709         )
5710 {
5711         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
5712         {
5713                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
5714                 return;
5715         }
5716
5717         if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
5718         {
5719 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
5720                 odm_InitHybridAntDiv_88C_92D(pDM_Odm);
5721 #endif
5722         }
5723         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
5724         {
5725 #if (RTL8188E_SUPPORT == 1)
5726                 ODM_AntennaDiversityInit_88E(pDM_Odm);
5727 #endif
5728         }
5729
5730 }
5731
5732
5733 bool
5734 odm_StaDefAntSel(
5735         PDM_ODM_T       pDM_Odm,
5736         u4Byte          OFDM_Ant1_Cnt,
5737         u4Byte          OFDM_Ant2_Cnt,
5738         u4Byte          CCK_Ant1_Cnt,
5739         u4Byte          CCK_Ant2_Cnt,
5740         u1Byte          *pDefAnt
5741
5742         )
5743 {
5744 #if 1
5745         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n"));
5746
5747         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt));
5748         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt));
5749
5750
5751         if (((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)) {
5752                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n"));
5753                 return  false;
5754         }
5755
5756         if (OFDM_Ant1_Cnt || OFDM_Ant2_Cnt )    {
5757                 //if RX OFDM packet number larger than 0
5758                 if (OFDM_Ant1_Cnt > OFDM_Ant2_Cnt)
5759                         (*pDefAnt)=1;
5760                 else
5761                         (*pDefAnt)=0;
5762         }
5763         // else if RX CCK packet number larger than 10
5764         else if ((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 )
5765         {
5766                 if (CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt))
5767                         (*pDefAnt)=1;
5768                 else if (CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt))
5769                         (*pDefAnt)=0;
5770                 else if (CCK_Ant1_Cnt > CCK_Ant2_Cnt)
5771                         (*pDefAnt)=0;
5772                 else
5773                         (*pDefAnt)=1;
5774
5775         }
5776
5777         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2"));
5778
5779 #endif
5780         //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
5781         //(*pDefAnt)= (u1Byte) antsel;
5782
5783
5784
5785
5786         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n"));
5787
5788         return true;
5789
5790
5791 }
5792
5793
5794 void
5795 odm_SetRxIdleAnt(
5796         PDM_ODM_T       pDM_Odm,
5797         u1Byte  Ant,
5798           bool   bDualPath
5799 )
5800 {
5801         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5802
5803         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n"));
5804
5805         if (Ant != pDM_SWAT_Table->RxIdleAnt)
5806         {
5807         //for path-A
5808         if (Ant==1)
5809                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9);   //right-side antenna
5810         else
5811                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a);   //left-side antenna
5812
5813         //for path-B
5814         if (bDualPath) {
5815                         if (Ant==0)
5816                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9);   //right-side antenna
5817                 else
5818                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a);  //left-side antenna
5819                 }
5820         }
5821                 pDM_SWAT_Table->RxIdleAnt = Ant;
5822         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s  Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a));
5823
5824         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n"));
5825
5826         }
5827
5828 void
5829 ODM_AntselStatistics_88C(
5830                 PDM_ODM_T               pDM_Odm,
5831                 u1Byte                  MacId,
5832                 u4Byte                  PWDBAll,
5833                 bool                    isCCKrate
5834 )
5835 {
5836         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5837
5838         if (pDM_SWAT_Table->antsel == 1)
5839         {
5840                 if (isCCKrate)
5841                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
5842                 else
5843                 {
5844                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
5845                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
5846                 }
5847         }
5848         else
5849         {
5850                 if (isCCKrate)
5851                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
5852                 else
5853                 {
5854                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
5855                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
5856                 }
5857         }
5858
5859 }
5860
5861
5862
5863
5864 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
5865 void
5866 ODM_SetTxAntByTxInfo_88C_92D(
5867                 PDM_ODM_T               pDM_Odm,
5868                 pu1Byte                 pDesc,
5869                 u1Byte                  macId
5870 )
5871 {
5872         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5873         u1Byte                  antsel;
5874
5875         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
5876                 return;
5877
5878         if (pDM_SWAT_Table->RxIdleAnt == 1)
5879                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?0:1;
5880         else
5881                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?1:0;
5882
5883         SET_TX_DESC_ANTSEL_A_92C(pDesc, antsel);
5884         //SET_TX_DESC_ANTSEL_B_92C(pDesc, antsel);
5885         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId]));
5886 }
5887 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
5888 void
5889 ODM_SetTxAntByTxInfo_88C_92D(
5890                 PDM_ODM_T               pDM_Odm
5891 )
5892 {
5893
5894 }
5895 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
5896 void
5897 ODM_SetTxAntByTxInfo_88C_92D(
5898                 PDM_ODM_T               pDM_Odm
5899 )
5900 {
5901
5902 }
5903 #endif
5904
5905 void
5906 odm_HwAntDiv_92C_92D(
5907         PDM_ODM_T       pDM_Odm
5908 )
5909 {
5910         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
5911         u4Byte                  RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
5912         u1Byte                  RxIdleAnt, i;
5913         bool            bRet=false;
5914         PSTA_INFO_T     pEntry;
5915
5916 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
5917         struct rtl8192cd_priv *priv=pDM_Odm->priv;
5918         //if test, return
5919         if (priv->pshare->rf_ft_var.CurAntenna & 0x80)
5920                 return;
5921 #endif
5922
5923         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
5924
5925         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))                                    //if don't support antenna diveristy
5926         {
5927                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n"));
5928                 return;
5929         }
5930
5931         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
5932         {
5933                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n"));
5934                 return;
5935         }
5936
5937 #if (DM_ODM_SUPPORT_TYPE&(ODM_MP|ODM_CE))
5938         if (!pDM_Odm->bLinked)
5939         {
5940                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is false\n"));
5941                 return;
5942         }
5943 #endif
5944
5945         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
5946         {
5947                 pEntry = pDM_Odm->pODM_StaInfo[i];
5948                 if (IS_STA_VALID(pEntry))
5949                 {
5950
5951                         RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]);
5952                         RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]);
5953
5954                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d,  RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2));
5955
5956                         if (RSSI_Ant1 ||RSSI_Ant2)
5957                         {
5958 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
5959                                 if (pDM_Odm->pODM_StaInfo[i]->expire_to)
5960 #endif
5961                                 {
5962                                         RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2;
5963                                         if ((!RSSI) || ( RSSI < RSSI_Min) ) {
5964                                                 pDM_SWAT_Table->TargetSTA = i;
5965                                                 RSSI_Min = RSSI;
5966                                         }
5967                                 }
5968         }
5969                         ///STA: found out default antenna
5970                         bRet=odm_StaDefAntSel(pDM_Odm,
5971                                                  pDM_SWAT_Table->OFDM_Ant1_Cnt[i],
5972                                                  pDM_SWAT_Table->OFDM_Ant2_Cnt[i],
5973                                                  pDM_SWAT_Table->CCK_Ant1_Cnt[i],
5974                                                  pDM_SWAT_Table->CCK_Ant2_Cnt[i],
5975                                                  &pDM_SWAT_Table->TxAnt[i]);
5976
5977                         //if Tx antenna selection: successful
5978                         if (bRet) {
5979                                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
5980                                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
5981                                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
5982                                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
5983                                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
5984                                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
5985                         }
5986                 }
5987         }
5988
5989         //set RX Idle Ant
5990         RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA];
5991         odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, false);
5992
5993 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
5994 #ifdef TX_SHORTCUT
5995         if (!priv->pmib->dot11OperationEntry.disable_txsc) {
5996                 plist = phead->next;
5997                 while (plist != phead)  {
5998                         pstat = list_entry(plist, struct stat_info, asoc_list);
5999                         if (pstat->expire_to) {
6000                                 for (i=0; i<TX_SC_ENTRY_NUM; i++) {
6001                                         struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
6002                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
6003                                         if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
6004                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
6005                                         pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
6006                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
6007                                         if ((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
6008                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
6009                                 }
6010                         }
6011
6012                         if (plist == plist->next)
6013                                 break;
6014                         plist = plist->next;
6015                 };
6016         }
6017 #endif
6018 #endif
6019
6020         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n"));
6021
6022 }
6023
6024 void
6025 odm_HwAntDiv(
6026         PDM_ODM_T       pDM_Odm
6027 )
6028 {
6029         if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
6030         {
6031                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
6032                 return;
6033         }
6034
6035         if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
6036         {
6037 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
6038                 odm_HwAntDiv_92C_92D(pDM_Odm);
6039 #endif
6040         }
6041         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
6042         {
6043 #if (RTL8188E_SUPPORT == 1)
6044                 ODM_AntennaDiversity_88E(pDM_Odm);
6045 #endif
6046         }
6047
6048 }
6049
6050
6051 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
6052
6053 u1Byte
6054 ODM_Diversity_AntennaSelect(
6055         PDM_ODM_T       pDM_Odm,
6056         u1Byte  *data
6057 )
6058 {
6059         struct rtl8192cd_priv *priv=pDM_Odm->priv;
6060
6061         int ant = _atoi(data, 16);
6062
6063         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ODM_Diversity_AntennaSelect==============>\n"));
6064
6065         #ifdef PCIE_POWER_SAVING
6066         PCIeWakeUp(priv, POWER_DOWN_T0);
6067         #endif
6068
6069         if (ant==Antenna_B || ant==Antenna_A)
6070         {
6071                 if ( !priv->pshare->rf_ft_var.antSw_select) {
6072                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(8)| BIT(9) );  //  ANTSEL A as SW control
6073                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
6074                         PHY_SetBBReg(priv, 0x860, 0x300, ant);
6075                 } else {
6076                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(24)| BIT(25) ); // ANTSEL B as HW control
6077                         PHY_SetBBReg(priv, 0x864, 0x300, ant);
6078                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));               // rx OFDM SW control
6079                 }
6080
6081                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));       // rx CCK SW control
6082                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc
6083                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
6084
6085                 priv->pshare->rf_ft_var.antHw_enable = 0;
6086                 priv->pshare->rf_ft_var.CurAntenna  = (ant%2);
6087
6088                 #ifdef SW_ANT_SWITCH
6089                 priv->pshare->rf_ft_var.antSw_enable = 0;
6090                 priv->pshare->DM_SWAT_Table.CurAntenna = ant;
6091                 priv->pshare->RSSI_test =0;
6092                 #endif
6093         }
6094         else if (ant==0) {
6095
6096                 if ( !priv->pshare->rf_ft_var.antSw_select)  {
6097                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(8)| BIT(9)) );
6098                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) | BIT(7));   // OFDM HW control
6099                 } else {
6100                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(24)| BIT(25)) );
6101                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) | BIT(7));   // OFDM HW control
6102                 }
6103
6104                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) | BIT(7));   // CCK HW control
6105                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) | BIT(21) ); // by tx desc
6106                 priv->pshare->rf_ft_var.CurAntenna = 0;
6107                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
6108                 priv->pshare->rf_ft_var.antHw_enable = 1;
6109 #ifdef SW_ANT_SWITCH
6110                 priv->pshare->rf_ft_var.antSw_enable = 0;
6111                 priv->pshare->RSSI_test =0;
6112 #endif
6113         }
6114 #ifdef SW_ANT_SWITCH
6115         else if (ant==3) {
6116                 if (!priv->pshare->rf_ft_var.antSw_enable) {
6117
6118                         dm_SW_AntennaSwitchInit(priv);
6119                         ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
6120                         priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes;
6121                         priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes;
6122                 }
6123                 if ( !priv->pshare->rf_ft_var.antSw_select)
6124                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
6125                 else
6126                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));       // rx OFDM SW control
6127
6128                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));               // rx CCK SW control
6129                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21)));      // select ant by tx desc
6130                 priv->pshare->rf_ft_var.antHw_enable = 0;
6131                 priv->pshare->rf_ft_var.antSw_enable = 1;
6132
6133         }
6134 #endif
6135         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============ODM_Diversity_AntennaSelect\n"));
6136
6137         return 1;
6138 }
6139 #endif
6140
6141 #else //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
6142
6143 void odm_InitHybridAntDiv(      PDM_ODM_T       pDM_Odm         ) {}
6144 void odm_HwAntDiv(      PDM_ODM_T       pDM_Odm) {}
6145 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6146 void ODM_SetTxAntByTxInfo_88C_92D(
6147                 PDM_ODM_T               pDM_Odm,
6148                 pu1Byte                 pDesc,
6149                 u1Byte                  macId
6150 ) {}
6151 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6152 void ODM_SetTxAntByTxInfo_88C_92D(              PDM_ODM_T               pDM_Odm) { }
6153 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
6154 void ODM_SetTxAntByTxInfo_88C_92D(              PDM_ODM_T               pDM_Odm) { }
6155 #endif
6156
6157 #endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
6158
6159
6160
6161 //============================================================
6162 //EDCA Turbo
6163 //============================================================
6164 void
6165 ODM_EdcaTurboInit(
6166            PDM_ODM_T            pDM_Odm)
6167 {
6168
6169 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
6170         odm_EdcaParaInit(pDM_Odm);
6171 #elif (DM_ODM_SUPPORT_TYPE==ODM_MP)
6172         PADAPTER        Adapter = NULL;
6173         HAL_DATA_TYPE   *pHalData = NULL;
6174
6175         if (pDM_Odm->Adapter==NULL)     {
6176                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n"));
6177                 return;
6178         }
6179
6180         Adapter=pDM_Odm->Adapter;
6181         pHalData=GET_HAL_DATA(Adapter);
6182
6183         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
6184         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
6185         pHalData->bIsAnyNonBEPkts = false;
6186
6187 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6188         PADAPTER        Adapter = pDM_Odm->Adapter;
6189         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
6190         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
6191         Adapter->recvpriv.bIsAnyNonBEPkts =false;
6192
6193 #endif
6194         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
6195         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
6196         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
6197         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
6198
6199
6200 }       // ODM_InitEdcaTurbo
6201
6202 void
6203 odm_EdcaTurboCheck(
6204                 PDM_ODM_T               pDM_Odm
6205         )
6206 {
6207         //
6208         // For AP/ADSL use prtl8192cd_priv
6209         // For CE/NIC use PADAPTER
6210         //
6211         PADAPTER                pAdapter = pDM_Odm->Adapter;
6212         prtl8192cd_priv priv            = pDM_Odm->priv;
6213
6214         //
6215         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
6216         // at the same time. In the stage2/3, we need to prive universal interface and merge all
6217         // HW dynamic mechanism.
6218         //
6219         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
6220
6221         if (!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
6222                 return;
6223
6224         switch  (pDM_Odm->SupportPlatform)
6225         {
6226                 case    ODM_MP:
6227
6228 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6229                         odm_EdcaTurboCheckMP(pDM_Odm);
6230 #endif
6231                         break;
6232
6233                 case    ODM_CE:
6234 #if (DM_ODM_SUPPORT_TYPE==ODM_CE)
6235                         odm_EdcaTurboCheckCE(pDM_Odm);
6236 #endif
6237                         break;
6238
6239                 case    ODM_AP:
6240                 case    ODM_ADSL:
6241
6242 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
6243                 odm_IotEngine(pDM_Odm);
6244 #endif
6245                         break;
6246         }
6247         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
6248
6249 }       // odm_CheckEdcaTurbo
6250
6251 #if (DM_ODM_SUPPORT_TYPE==ODM_CE)
6252
6253
6254 void
6255 odm_EdcaTurboCheckCE(
6256                 PDM_ODM_T               pDM_Odm
6257         )
6258 {
6259
6260 #if (DM_ODM_SUPPORT_TYPE==ODM_CE)
6261
6262         PADAPTER                       Adapter = pDM_Odm->Adapter;
6263
6264         u32     trafficIndex;
6265         u32     edca_param;
6266         u64     cur_tx_bytes = 0;
6267         u64     cur_rx_bytes = 0;
6268         u8      bbtchange = false;
6269         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6270         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
6271         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
6272         struct registry_priv    *pregpriv = &Adapter->registrypriv;
6273         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
6274         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
6275
6276
6277         if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
6278         {
6279                 goto dm_CheckEdcaTurbo_EXIT;
6280         }
6281
6282         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
6283         {
6284                 goto dm_CheckEdcaTurbo_EXIT;
6285         }
6286
6287 #ifdef CONFIG_BT_COEXIST
6288         if (BT_DisableEDCATurbo(Adapter))
6289         {
6290                 goto dm_CheckEdcaTurbo_EXIT;
6291         }
6292 #endif
6293
6294         // Check if the status needs to be changed.
6295         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
6296         {
6297                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
6298                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
6299
6300                 //traffic, TX or RX
6301                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)||(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS))
6302                 {
6303                         if (cur_tx_bytes > (cur_rx_bytes << 2))
6304                         { // Uplink TP is present.
6305                                 trafficIndex = UP_LINK;
6306                         }
6307                         else
6308                         { // Balance TP is present.
6309                                 trafficIndex = DOWN_LINK;
6310                         }
6311                 }
6312                 else
6313                 {
6314                         if (cur_rx_bytes > (cur_tx_bytes << 2))
6315                         { // Downlink TP is present.
6316                                 trafficIndex = DOWN_LINK;
6317                         }
6318                         else
6319                         { // Balance TP is present.
6320                                 trafficIndex = UP_LINK;
6321                         }
6322                 }
6323
6324                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
6325                 {
6326                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
6327                         {
6328                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
6329                         }
6330                         else
6331                         {
6332                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
6333                         }
6334
6335                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
6336
6337                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
6338                 }
6339
6340                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
6341         }
6342         else
6343         {
6344                 //
6345                 // Turn Off EDCA turbo here.
6346                 // Restore original EDCA according to the declaration of AP.
6347                 //
6348                  if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
6349                 {
6350                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
6351                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
6352                 }
6353         }
6354
6355 dm_CheckEdcaTurbo_EXIT:
6356         // Set variables for next time.
6357         precvpriv->bIsAnyNonBEPkts = false;
6358         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
6359         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
6360 #endif
6361 }
6362
6363
6364 #elif (DM_ODM_SUPPORT_TYPE==ODM_MP)
6365 void
6366 odm_EdcaTurboCheckMP(
6367                 PDM_ODM_T               pDM_Odm
6368         )
6369 {
6370
6371
6372         PADAPTER                       Adapter = pDM_Odm->Adapter;
6373         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6374
6375 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6376         PADAPTER                        pDefaultAdapter = GetDefaultAdapter(Adapter);
6377         PADAPTER                        pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
6378         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
6379         PSTA_QOS                        pStaQos = Adapter->MgntInfo.pStaQos;
6380         //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn
6381         u8Byte                          Ext_curTxOkCnt = 0;
6382         u8Byte                          Ext_curRxOkCnt = 0;
6383         static u8Byte                   Ext_lastTxOkCnt = 0;
6384         static u8Byte                   Ext_lastRxOkCnt = 0;
6385         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
6386         u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
6387
6388 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6389         struct dm_priv          *pdmpriv = &pHalData->dmpriv;
6390         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
6391         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
6392         struct registry_priv    *pregpriv = &Adapter->registrypriv;
6393         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
6394         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
6395         #ifdef CONFIG_BT_COEXIST
6396         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
6397         #endif
6398        u1Byte bbtchange =false;
6399 #endif
6400         // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
6401         u8Byte                          curTxOkCnt = 0;
6402         u8Byte                          curRxOkCnt = 0;
6403         u8Byte                  lastTxOkCnt = 0;
6404         u8Byte                  lastRxOkCnt = 0;
6405         u4Byte                          EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[pMgntInfo->IOTPeer];
6406         u4Byte                          EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[pMgntInfo->IOTPeer];
6407        u4Byte                         EDCA_BE = 0x5ea42b;
6408         u4Byte                         IOTPeer=0;
6409         bool                      *pbIsCurRDLState=NULL;
6410         bool                      bLastIsCurRDLState=false;
6411         bool                             bBiasOnRx=false;
6412         bool                            bEdcaTurboOn=false;
6413
6414
6415         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>"));
6416         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
6417
6418 ////===============================
6419 ////list paramter for different platform
6420 ////===============================
6421         bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState;
6422         pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState);
6423 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6424        // Caculate TX/RX TP:
6425         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
6426         curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
6427         if (pExtAdapter == NULL)
6428                 pExtAdapter = pDefaultAdapter;
6429
6430         Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt;
6431         Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt;
6432         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
6433         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
6434         if (TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
6435         {
6436                 curTxOkCnt = Ext_curTxOkCnt ;
6437                 curRxOkCnt = Ext_curRxOkCnt ;
6438         }
6439         //
6440         IOTPeer=pMgntInfo->IOTPeer;
6441         bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?true:false;
6442         bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts) && (!pMgntInfo->bDisableFrameBursting))?true:false;
6443         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx  bDisableFrameBursting : 0x%lx \n",pHalData->bIsAnyNonBEPkts,pMgntInfo->bDisableFrameBursting));
6444
6445 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6446         // Caculate TX/RX TP:
6447         curTxOkCnt = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
6448         curRxOkCnt = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
6449         #ifdef CONFIG_BT_COEXIST
6450         if (pbtpriv->BT_Coexist)
6451         {
6452                 if ( (pbtpriv->BT_EDCA[UP_LINK]!=0) ||  (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
6453                         bbtchange = true;
6454         }
6455         #endif
6456         IOTPeer=pmlmeinfo->assoc_AP_vendor;
6457         bBiasOnRx=((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))?true:false;
6458         bEdcaTurboOn=(bbtchange || (!precvpriv->bIsAnyNonBEPkts))?true:false;
6459         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bbtchange : 0x%lx  bIsAnyNonBEPkts : 0x%lx \n",bbtchange,precvpriv->bIsAnyNonBEPkts));
6460 #endif
6461
6462
6463 ////===============================
6464 ////check if edca turbo is disabled
6465 ////===============================
6466         if (odm_IsEdcaTurboDisable(pDM_Odm))
6467                 goto dm_CheckEdcaTurbo_EXIT;
6468
6469
6470 ////===============================
6471 ////remove iot case out
6472 ////===============================
6473         ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL);
6474
6475
6476 ////===============================
6477 ////Check if the status needs to be changed.
6478 ////===============================
6479         if (bEdcaTurboOn)
6480         {
6481                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx));
6482                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx\n",curTxOkCnt));
6483                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx\n",curRxOkCnt));
6484                 if (bBiasOnRx)
6485                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   true,  pbIsCurRDLState);
6486                 else
6487                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   false,  pbIsCurRDLState);
6488
6489 //modify by Guo.Mingzhi 2011-12-29
6490                         EDCA_BE=((*pbIsCurRDLState)==true)?EDCA_BE_DL:EDCA_BE_UL;
6491                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
6492                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE));
6493
6494 //             if (((*pbIsCurRDLState)!=bLastIsCurRDLState)||(!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
6495 //              {
6496 //                      EDCA_BE=((*pbIsCurRDLState)==true)?EDCA_BE_DL:EDCA_BE_UL;
6497 //                      ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
6498  //             }
6499                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
6500
6501                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx  EDCA_BE_UL : 0x%lx  EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE));
6502
6503         }
6504         else
6505         {
6506                 // Turn Off EDCA turbo here.
6507                 // Restore original EDCA according to the declaration of AP.
6508                  if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
6509                 {
6510 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6511                         Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) );
6512 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6513                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, pHalData->AcParam_BE);
6514 #endif
6515
6516                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
6517                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE));
6518
6519                 }
6520         }
6521
6522 ////===============================
6523 ////Set variables for next time.
6524 ////===============================
6525 dm_CheckEdcaTurbo_EXIT:
6526 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6527         pHalData->bIsAnyNonBEPkts = false;
6528         pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
6529         pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
6530         pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast;
6531         pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast;
6532 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6533         precvpriv->bIsAnyNonBEPkts = false;
6534         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
6535         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
6536 #endif
6537
6538 }
6539
6540
6541 //check if edca turbo is disabled
6542 bool
6543 odm_IsEdcaTurboDisable(
6544         PDM_ODM_T       pDM_Odm
6545 )
6546 {
6547         PADAPTER                       Adapter = pDM_Odm->Adapter;
6548         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6549
6550 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6551         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
6552         u4Byte                         IOTPeer=pMgntInfo->IOTPeer;
6553 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6554         struct registry_priv    *pregpriv = &Adapter->registrypriv;
6555         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
6556         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
6557         u4Byte                         IOTPeer=pmlmeinfo->assoc_AP_vendor;
6558         u1Byte                         WirelessMode=0xFF;                   //invalid value
6559
6560         if (pDM_Odm->pWirelessMode!=NULL)
6561                 WirelessMode=*(pDM_Odm->pWirelessMode);
6562
6563 #endif
6564
6565 #if (BT_30_SUPPORT == 1)
6566         if (pDM_Odm->bBtDisableEdcaTurbo)
6567         {
6568                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
6569                 return true;
6570         }
6571 #endif
6572
6573         if ((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))||
6574                 (pDM_Odm->bWIFITest)||
6575                 (IOTPeer>= HT_IOT_PEER_MAX))
6576         {
6577                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
6578                 return true;
6579         }
6580
6581
6582 #if (DM_ODM_SUPPORT_TYPE ==ODM_MP)
6583         // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue
6584         // 2. User may disable EDCA Turbo mode with OID settings.
6585         if ((pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) ||pHalData->bForcedDisableTurboEDCA) {
6586                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n"));
6587                 return  true;
6588                 }
6589
6590 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6591         //suggested by Jr.Luke: open TXOP for B/G/BG/A mode 2012-0215
6592         if ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)||(WirelessMode==ODM_WM_G)||(WirelessMode=ODM_WM_A))
6593                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)|0x5E0000);
6594
6595         if (pDM_Odm->SupportICType==ODM_RTL8192D)               {
6596                 if ((pregpriv->wifi_spec == 1)  || (pmlmeext->cur_wireless_mode == WIRELESS_11B)) {
6597                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("92D:EdcaTurboDisable\n"));
6598                         return true;
6599                 }
6600         }
6601         else
6602         {
6603                 if ((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)) {
6604                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("Others:EdcaTurboDisable\n"));
6605                         return true;
6606                 }
6607         }
6608 #ifdef CONFIG_BT_COEXIST
6609         if (BT_DisableEDCATurbo(Adapter))
6610         {
6611                 goto dm_CheckEdcaTurbo_EXIT;
6612         }
6613 #endif
6614
6615 #endif
6616
6617         return  false;
6618
6619
6620 }
6621
6622 //add iot case here: for MP/CE
6623 void
6624 ODM_EdcaParaSelByIot(
6625         PDM_ODM_T       pDM_Odm,
6626         u4Byte          *EDCA_BE_UL,
6627         u4Byte          *EDCA_BE_DL
6628         )
6629 {
6630
6631         PADAPTER                       Adapter = pDM_Odm->Adapter;
6632         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6633         u4Byte                         IOTPeer=0;
6634         u4Byte                         ICType=pDM_Odm->SupportICType;
6635         u1Byte                         WirelessMode=0xFF;                   //invalid value
6636         u4Byte                          RFType=pDM_Odm->RFType;
6637
6638 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6639         PADAPTER                        pDefaultAdapter = GetDefaultAdapter(Adapter);
6640         PADAPTER                        pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
6641         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
6642         u1Byte                          TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
6643
6644 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6645         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
6646         #ifdef CONFIG_BT_COEXIST
6647         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
6648         #endif
6649        u1Byte bbtchange =false;
6650 #endif
6651
6652         if (pDM_Odm->pWirelessMode!=NULL)
6653                 WirelessMode=*(pDM_Odm->pWirelessMode);
6654
6655 ///////////////////////////////////////////////////////////
6656 ////list paramter for different platform
6657 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6658         IOTPeer=pMgntInfo->IOTPeer;
6659         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
6660
6661 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6662         IOTPeer=pmlmeinfo->assoc_AP_vendor;
6663         #ifdef CONFIG_BT_COEXIST
6664         if (pbtpriv->BT_Coexist)
6665         {
6666                 if ( (pbtpriv->BT_EDCA[UP_LINK]!=0) ||  (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
6667                         bbtchange = true;
6668         }
6669         #endif
6670
6671 #endif
6672
6673         if (ICType==ODM_RTL8192D)
6674         {
6675                 // Single PHY
6676                 if (pDM_Odm->RFType==ODM_2T2R)
6677                 {
6678                         (*EDCA_BE_UL) = 0x60a42b;    //0x5ea42b;
6679                         (*EDCA_BE_DL) = 0x60a42b;    //0x5ea42b;
6680
6681                 }
6682                 else
6683                 {
6684                         (*EDCA_BE_UL) = 0x6ea42b;
6685                         (*EDCA_BE_DL) = 0x6ea42b;
6686                 }
6687
6688         }
6689 ////============================
6690 /// IOT case for MP
6691 ////============================
6692 #if (DM_ODM_SUPPORT_TYPE==ODM_MP)
6693         else
6694         {
6695
6696                 if (pDM_Odm->SupportInterface==ODM_ITRF_PCIE) {
6697                         if ((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))                        {
6698                                 (*EDCA_BE_UL) = 0x60a42b;
6699                                 (*EDCA_BE_DL) = 0x60a42b;
6700                         }
6701                         else
6702                         {
6703                                 (*EDCA_BE_UL) = 0x6ea42b;
6704                                 (*EDCA_BE_DL) = 0x6ea42b;
6705                         }
6706                 }
6707         }
6708
6709         if (TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
6710         {
6711                 (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer];
6712                 (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer];
6713         }
6714
6715         #if (INTEL_PROXIMITY_SUPPORT == 1)
6716         if (pMgntInfo->IntelClassModeInfo.bEnableCA == true)
6717         {
6718                 (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
6719         }
6720         else
6721         #endif
6722         {
6723                 if ((!pMgntInfo->bDisableFrameBursting) &&
6724                         (pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE)))
6725                 {// To check whether we shall force turn on TXOP configuration.
6726                         if (!((*EDCA_BE_UL) & 0xffff0000))
6727                                 (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL.
6728                         if (!((*EDCA_BE_DL) & 0xffff0000))
6729                                 (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL.
6730                 }
6731
6732                 //92D txop can't be set to 0x3e for cisco1250
6733                 if ((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
6734                 {
6735                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
6736                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
6737                 }
6738                 //merge from 92s_92c_merge temp brunch v2445    20120215
6739                 else if ((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
6740                 {
6741                         (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
6742                 }
6743                 else if ((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
6744                 {
6745                         (*EDCA_BE_DL) = 0xa630;
6746                 }
6747
6748                 else if (IOTPeer == HT_IOT_PEER_MARVELL)
6749                 {
6750                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
6751                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
6752                 }
6753                 else if (IOTPeer == HT_IOT_PEER_ATHEROS)
6754                 {
6755                         // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
6756                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
6757                 }
6758         }
6759 ////============================
6760 /// IOT case for CE
6761 ////============================
6762 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
6763
6764         if (RFType==ODM_RTL8192D)
6765         {
6766                 if ((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
6767                 {
6768                         (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
6769                         (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
6770                 }
6771                 else if ((IOTPeer == HT_IOT_PEER_AIRGO) &&
6772                         ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G))))
6773                         (*EDCA_BE_DL)=0x00a630;
6774
6775                 else if ((IOTPeer== HT_IOT_PEER_ATHEROS) &&
6776                                         (WirelessMode&ODM_WM_N5G) &&
6777                                         (Adapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ))
6778                         (*EDCA_BE_DL)=0xa42b;
6779
6780         }
6781         //92C IOT case:
6782         else
6783         {
6784                 #ifdef CONFIG_BT_COEXIST
6785                 if (bbtchange)
6786                 {
6787                         (*EDCA_BE_UL) = pbtpriv->BT_EDCA[UP_LINK];
6788                         (*EDCA_BE_DL) = pbtpriv->BT_EDCA[DOWN_LINK];
6789                 }
6790                 else
6791                 #endif
6792                 {
6793                         if ((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
6794                         {
6795                                 (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
6796                                 (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
6797                         }
6798                         else
6799                         {
6800                                 (*EDCA_BE_UL)=EDCAParam[HT_IOT_PEER_UNKNOWN][UP_LINK];
6801                                 (*EDCA_BE_DL)=EDCAParam[HT_IOT_PEER_UNKNOWN][DOWN_LINK];
6802                         }
6803                 }
6804                 if (pDM_Odm->SupportInterface==ODM_ITRF_PCIE) {
6805                         if ((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))
6806                         {
6807                                 (*EDCA_BE_UL) = 0x60a42b;
6808                                 (*EDCA_BE_DL) = 0x60a42b;
6809                         }
6810                         else
6811                         {
6812                                 (*EDCA_BE_UL) = 0x6ea42b;
6813                                 (*EDCA_BE_DL) = 0x6ea42b;
6814                         }
6815                 }
6816
6817         }
6818 #endif
6819
6820         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL)));
6821
6822 }
6823
6824
6825 void
6826 odm_EdcaChooseTrafficIdx(
6827         PDM_ODM_T               pDM_Odm,
6828         u8Byte                          cur_tx_bytes,
6829         u8Byte                          cur_rx_bytes,
6830         bool                    bBiasOnRx,
6831         bool            *pbIsCurRDLState
6832         )
6833 {
6834
6835
6836         if (bBiasOnRx)
6837         {
6838
6839                 if (cur_tx_bytes>(cur_rx_bytes*4))
6840                 {
6841                         *pbIsCurRDLState=false;
6842                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n "));
6843
6844                 }
6845                 else
6846                 {
6847                         *pbIsCurRDLState=true;
6848                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
6849
6850                 }
6851         }
6852         else
6853         {
6854                 if (cur_rx_bytes>(cur_tx_bytes*4))
6855                 {
6856                         *pbIsCurRDLState=true;
6857                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink        Traffic\n"));
6858
6859                 }
6860                 else
6861                 {
6862                         *pbIsCurRDLState=false;
6863                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
6864                 }
6865         }
6866
6867         return ;
6868 }
6869
6870 #endif
6871
6872 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
6873
6874 void odm_EdcaParaInit(
6875         PDM_ODM_T       pDM_Odm
6876         )
6877 {
6878         prtl8192cd_priv priv            = pDM_Odm->priv;
6879         int   mode=priv->pmib->dot11BssType.net_work_type;
6880
6881         static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time;
6882         struct ParaRecord EDCA[4];
6883
6884          memset(EDCA, 0, 4*sizeof(struct ParaRecord));
6885
6886         sifs_time = 10;
6887         slot_time = 20;
6888
6889         if (mode & (ODM_WM_N24G|ODM_WM_N5G))
6890                 sifs_time = 16;
6891
6892         if (mode & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G|ODM_WM_A))
6893                 slot_time = 9;
6894
6895
6896 #if ((defined(RTL_MANUAL_EDCA))&&(DM_ODM_SUPPORT_TYPE==ODM_AP))
6897          if ( priv->pmib->dot11QosEntry.ManualEDCA ) {
6898                  if ( OPMODE & WIFI_AP_STATE )
6899                          memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord));
6900                  else
6901                          memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord));
6902
6903                 #ifdef WIFI_WMM
6904                 if (QOS_ENABLE)
6905                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
6906                 else
6907                 #endif
6908                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
6909
6910         } else
6911         #endif //RTL_MANUAL_EDCA
6912         {
6913
6914                  if (OPMODE & WIFI_AP_STATE)
6915                  {
6916                         memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord));
6917
6918                         if (mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
6919                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
6920                         else
6921                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord));
6922                  }
6923                  else
6924                  {
6925                         memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord));
6926
6927                         if (mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
6928                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
6929                         else
6930                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord));
6931                  }
6932
6933         #ifdef WIFI_WMM
6934                 if (QOS_ENABLE)
6935                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
6936                 else
6937         #endif
6938
6939 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
6940                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
6941 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
6942                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + 2* slot_time));
6943 #endif
6944
6945
6946         }
6947
6948         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VO_PARAM, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time));
6949         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time));
6950         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BK_PARAM, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time));
6951 //      ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00);
6952
6953         priv->pshare->iot_mode_enable = 0;
6954 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
6955         if (priv->pshare->rf_ft_var.wifi_beq_iot)
6956                 priv->pshare->iot_mode_VI_exist = 0;
6957
6958         #ifdef WMM_VIBE_PRI
6959         priv->pshare->iot_mode_BE_exist = 0;
6960         #endif
6961
6962         #ifdef LOW_TP_TXOP
6963         priv->pshare->BE_cwmax_enhance = 0;
6964         #endif
6965
6966 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
6967       priv->pshare->iot_mode_BE_exist = 0;
6968 #endif
6969         priv->pshare->iot_mode_VO_exist = 0;
6970 }
6971
6972 bool
6973 ODM_ChooseIotMainSTA(
6974         PDM_ODM_T               pDM_Odm,
6975         PSTA_INFO_T             pstat
6976         )
6977 {
6978         prtl8192cd_priv priv = pDM_Odm->priv;
6979         bool            bhighTP_found_pstat=false;
6980
6981         if ((GET_ROOT(priv)->up_time % 2) == 0) {
6982                 unsigned int tx_2s_avg = 0;
6983                 unsigned int rx_2s_avg = 0;
6984                 int i=0, aggReady=0;
6985                 unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes);
6986
6987                 pstat->current_tx_bytes += pstat->tx_byte_cnt;
6988                 pstat->current_rx_bytes += pstat->rx_byte_cnt;
6989
6990                 if (total_sum != 0) {
6991                         if (total_sum <= 100) {
6992                         tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum);
6993                         rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum);
6994                         } else {
6995                                 tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100));
6996                                 rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100));
6997                         }
6998
6999                 }
7000
7001 #if (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7002                 if (pstat->ht_cap_len) {
7003                         if ((tx_2s_avg + rx_2s_avg) >=25 /*50*/) {
7004
7005                                         priv->pshare->highTP_found_pstat = pstat;
7006                                         bhighTP_found_pstat=true;
7007                                 }
7008                         }
7009 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
7010                 for (i=0; i<8; i++)
7011                         aggReady += (pstat->ADDBA_ready[i]);
7012                 if (pstat->ht_cap_len && aggReady)
7013                 {
7014                         if ((tx_2s_avg + rx_2s_avg >= 25)) {
7015                                 priv->pshare->highTP_found_pstat = pstat;
7016                         }
7017
7018                 #ifdef CLIENT_MODE
7019                         if (OPMODE & WIFI_STATION_STATE) {
7020 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
7021                                 if ((pstat->IOTPeer==HT_IOT_PEER_RALINK) && ((tx_2s_avg + rx_2s_avg) >= 45))
7022 #else
7023                                 if (pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45))
7024 #endif
7025                                         priv->pshare->highTP_found_pstat = pstat;
7026                 }
7027                 #endif
7028         }
7029 #endif
7030         } else {
7031                 pstat->current_tx_bytes = pstat->tx_byte_cnt;
7032                 pstat->current_rx_bytes = pstat->rx_byte_cnt;
7033         }
7034
7035         return bhighTP_found_pstat;
7036 }
7037
7038
7039 #ifdef WIFI_WMM
7040 void
7041 ODM_IotEdcaSwitch(
7042         PDM_ODM_T               pDM_Odm,
7043         unsigned char           enable
7044         )
7045 {
7046         prtl8192cd_priv priv    = pDM_Odm->priv;
7047         int   mode=priv->pmib->dot11BssType.net_work_type;
7048         unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94;
7049         unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs;
7050
7051 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7052         if (!(!priv->pmib->dot11OperationEntry.wifi_specific ||
7053                 ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7054         #ifdef CLIENT_MODE
7055                 || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7056         #endif
7057                 ))
7058                 return;
7059 #endif
7060
7061         if ((mode & (ODM_WM_N24G|ODM_WM_N5G)) && (priv->pshare->ht_sta_num
7062         #ifdef WDS
7063                 || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
7064         #endif
7065                 ))
7066                 sifs_time = 16;
7067
7068         if (mode & (ODM_WM_N24G|ODM_WM_N5G|ODM_WM_G|ODM_WM_A)) {
7069                 slot_time = 9;
7070         }
7071         else
7072         {
7073                 BE_TXOP = 94;
7074                 VI_TXOP = 188;
7075         }
7076
7077 #if (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7078         if (priv->pshare->iot_mode_VO_exist) {
7079                 // to separate AC_VI and AC_BE to avoid using the same EDCA settings
7080                 if (priv->pshare->iot_mode_BE_exist) {
7081                         vi_cw_max = 5;
7082                         vi_cw_min = 3;
7083                 } else {
7084                         vi_cw_max = 6;
7085                         vi_cw_min = 4;
7086                 }
7087         }
7088         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
7089
7090         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
7091
7092
7093 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
7094         if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) {
7095                 if (priv->pshare->iot_mode_VO_exist) {
7096         #ifdef WMM_VIBE_PRI
7097                         if (priv->pshare->iot_mode_BE_exist)
7098                         {
7099                                 vi_cw_max = 5;
7100                                 vi_cw_min = 3;
7101                                 vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
7102                         }
7103                         else
7104         #endif
7105                         {
7106                         vi_cw_max = 6;
7107                         vi_cw_min = 4;
7108                         vi_aifs = 0x2b;
7109                         }
7110                 }
7111                 else {
7112                         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
7113                 }
7114
7115                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)
7116                         | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
7117         }
7118 #endif
7119
7120
7121
7122 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7123         if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist)
7124                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (10 << 12) | (4 << 8) | 0x4f);
7125         else if (!enable)
7126 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7127         if (!enable)                                 //if iot is disable ,maintain original BEQ PARAM
7128 #endif
7129                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8)
7130                         | (sifs_time + 3 * slot_time));
7131         else
7132         {
7133                 int txop_enlarge;
7134                 int txop;
7135                 unsigned int cw_max;
7136                 unsigned int txop_close;
7137
7138         #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
7139                         cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6);
7140                         txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0);
7141
7142                         if (priv->pshare->txop_enlarge == 0xe)   //if intel case
7143                                 txop = (txop_close ? 0 : (BE_TXOP*2));
7144                         else                                                        //if other case
7145                                 txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge));
7146         #else
7147                         cw_max=6;
7148                         if ((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd))
7149                                 txop=BE_TXOP*2;
7150                         else
7151                                 txop=BE_TXOP*priv->pshare->txop_enlarge;
7152
7153         #endif
7154
7155                 if (priv->pshare->ht_sta_num
7156         #ifdef WDS
7157                         || ((OPMODE & WIFI_AP_STATE) && (mode & (ODM_WM_N24G|ODM_WM_N5G)) &&
7158                         priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
7159         #endif
7160                         )
7161                         {
7162
7163                         if (priv->pshare->txop_enlarge == 0xe) {
7164                                 // is intel client, use a different edca value
7165                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f);
7166                                 priv->pshare->txop_enlarge = 2;
7167                         }
7168 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7169         #ifndef LOW_TP_TXOP
7170                          else if (priv->pshare->txop_enlarge == 0xd) {
7171                                 // is intel ralink, use a different edca value
7172                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | (4 << 12) | (3 << 8) | 0x19);
7173                                 priv->pshare->txop_enlarge = 2;
7174                         }
7175         #endif
7176 #endif
7177                         else
7178                         {
7179                                 if (pDM_Odm->RFType==ODM_2T2R)
7180                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
7181                                                 (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
7182                                 else
7183                                 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)
7184                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
7185                                                 (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
7186                                 #else
7187                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
7188                                                 (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
7189
7190                                 #endif
7191                         }
7192                 } else {
7193  #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
7194                          ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
7195  #else
7196                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (BE_TXOP*2 << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
7197
7198  #endif
7199               }
7200
7201         }
7202 }
7203 #endif
7204
7205 void
7206 odm_IotEngine(
7207         PDM_ODM_T       pDM_Odm
7208         )
7209 {
7210
7211         struct rtl8192cd_priv *priv=pDM_Odm->priv;
7212         PSTA_INFO_T pstat = NULL;
7213         u4Byte i;
7214
7215 #ifdef WIFI_WMM
7216         unsigned int switch_turbo = 0;
7217 #endif
7218 ////////////////////////////////////////////////////////
7219 //  if EDCA Turbo function is not supported or Manual EDCA Setting
7220 //  then return
7221 ////////////////////////////////////////////////////////
7222         if (!(pDM_Odm->SupportAbility&ODM_MAC_EDCA_TURBO)) {
7223                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO NOT SUPPORTED\n"));
7224                 return;
7225         }
7226
7227 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM))
7228         if (priv->pmib->dot11QosEntry.ManualEDCA) {
7229                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: MANUAL SETTING\n"));
7230                 return ;
7231         }
7232 #endif
7233
7234 #if !(DM_ODM_SUPPORT_TYPE &ODM_AP)
7235  //////////////////////////////////////////////////////
7236  //find high TP STA every 2s
7237 //////////////////////////////////////////////////////
7238         if ((GET_ROOT(priv)->up_time % 2) == 0)
7239                 priv->pshare->highTP_found_pstat==NULL;
7240
7241
7242         //find highTP STA
7243         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
7244                 pstat = pDM_Odm->pODM_StaInfo[i];
7245                 if (IS_STA_VALID(pstat) && (ODM_ChooseIotMainSTA(pDM_Odm, pstat)))       //find the correct station
7246                                 break;
7247         }
7248
7249  //////////////////////////////////////////////////////
7250  //if highTP STA is not found, then return
7251  //////////////////////////////////////////////////////
7252         if (priv->pshare->highTP_found_pstat==NULL)     {
7253                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: NO HT STA FOUND\n"));
7254                 return;
7255         }
7256 #endif
7257
7258         pstat=priv->pshare->highTP_found_pstat;
7259
7260
7261 #ifdef WIFI_WMM
7262         if (QOS_ENABLE) {
7263                 if (!priv->pmib->dot11OperationEntry.wifi_specific
7264                 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7265                         ||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7266                 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7267                         || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
7268                 #endif
7269                         ) {
7270                         if (priv->pshare->iot_mode_enable &&
7271                                 ((priv->pshare->phw->VO_pkt_count > 50) ||
7272                                  (priv->pshare->phw->VI_pkt_count > 50) ||
7273                                  (priv->pshare->phw->BK_pkt_count > 50))) {
7274                                 priv->pshare->iot_mode_enable = 0;
7275                                 switch_turbo++;
7276                         } else if ((!priv->pshare->iot_mode_enable) &&
7277                                 ((priv->pshare->phw->VO_pkt_count < 50) &&
7278                                  (priv->pshare->phw->VI_pkt_count < 50) &&
7279                                  (priv->pshare->phw->BK_pkt_count < 50))) {
7280                                 priv->pshare->iot_mode_enable++;
7281                                 switch_turbo++;
7282                         }
7283                 }
7284
7285
7286                 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7287                 if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific)
7288                 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7289                 if (priv->pmib->dot11OperationEntry.wifi_specific)
7290                 #endif
7291                 {
7292                         if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) {
7293                                 priv->pshare->iot_mode_VO_exist++;
7294                                 switch_turbo++;
7295                         } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) {
7296                                 priv->pshare->iot_mode_VO_exist = 0;
7297                                 switch_turbo++;
7298                         }
7299 #if ((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
7300                         if (priv->pshare->iot_mode_VO_exist) {
7301                                 //printk("[%s %d] BE_pkt_count=%d\n", __func__, __LINE__, priv->pshare->phw->BE_pkt_count);
7302                                 if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) {
7303                                         priv->pshare->iot_mode_BE_exist++;
7304                                         switch_turbo++;
7305                                 } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) {
7306                                         priv->pshare->iot_mode_BE_exist = 0;
7307                                         switch_turbo++;
7308                                 }
7309                         }
7310 #endif
7311
7312 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7313                         if (priv->pshare->rf_ft_var.wifi_beq_iot)
7314                         {
7315                                 if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) {
7316                                         priv->pshare->iot_mode_VI_exist++;
7317                                         switch_turbo++;
7318                                 } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) {
7319                                         priv->pshare->iot_mode_VI_exist = 0;
7320                                         switch_turbo++;
7321                                 }
7322                         }
7323 #endif
7324
7325                 }
7326                 else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) {
7327                    if (priv->pshare->txop_enlarge) {
7328                            priv->pshare->txop_enlarge = 0;
7329                            if (priv->pshare->iot_mode_enable)
7330                                         switch_turbo++;
7331                                 }
7332                 }
7333
7334 #if (defined(CLIENT_MODE) && (DM_ODM_SUPPORT_TYPE==ODM_AP))
7335         if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7336         {
7337             if (priv->pshare->iot_mode_enable &&
7338                 (((priv->pshare->phw->VO_pkt_count > 50) ||
7339                  (priv->pshare->phw->VI_pkt_count > 50) ||
7340                  (priv->pshare->phw->BK_pkt_count > 50)) ||
7341                  (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3]))))
7342             {
7343                 priv->pshare->iot_mode_enable = 0;
7344                 switch_turbo++;
7345             }
7346             else if ((!priv->pshare->iot_mode_enable) &&
7347                 (((priv->pshare->phw->VO_pkt_count < 50) &&
7348                  (priv->pshare->phw->VI_pkt_count < 50) &&
7349                  (priv->pshare->phw->BK_pkt_count < 50)) &&
7350                  (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3]))))
7351             {
7352                 priv->pshare->iot_mode_enable++;
7353                 switch_turbo++;
7354             }
7355         }
7356 #endif
7357
7358                 priv->pshare->phw->VO_pkt_count = 0;
7359                 priv->pshare->phw->VI_pkt_count = 0;
7360                 priv->pshare->phw->BK_pkt_count = 0;
7361
7362         #if ((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
7363                 priv->pshare->phw->BE_pkt_count = 0;
7364         #endif
7365
7366         #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7367                 if (priv->pshare->rf_ft_var.wifi_beq_iot)
7368                         priv->pshare->phw->VI_rx_pkt_count = 0;
7369                 #endif
7370
7371         }
7372 #endif
7373
7374         if ((priv->up_time % 2) == 0) {
7375                 /*
7376                  * decide EDCA content for different chip vendor
7377                  */
7378 #ifdef WIFI_WMM
7379         #if (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
7380                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
7381
7382         #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
7383                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific ||
7384                         ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7385                 #ifdef CLIENT_MODE
7386             || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7387                 #endif
7388         #endif
7389                 ))
7390
7391                 {
7392
7393                         if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) {
7394 #ifdef LOW_TP_TXOP
7395 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
7396                                 if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
7397 #else
7398                                 if (pstat->is_intel_sta)
7399 #endif
7400                                 {
7401                                         if (priv->pshare->txop_enlarge != 0xe)
7402                                         {
7403                                                 priv->pshare->txop_enlarge = 0xe;
7404
7405                                                 if (priv->pshare->iot_mode_enable)
7406                                                         switch_turbo++;
7407                                         }
7408                                 }
7409                                 else if (priv->pshare->txop_enlarge != 2)
7410                                 {
7411                                         priv->pshare->txop_enlarge = 2;
7412                                         if (priv->pshare->iot_mode_enable)
7413                                                 switch_turbo++;
7414                                 }
7415 #else
7416                                 if (priv->pshare->txop_enlarge != 2)
7417                                 {
7418 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
7419                                         if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
7420 #else
7421                                         if (pstat->is_intel_sta)
7422 #endif
7423                                                 priv->pshare->txop_enlarge = 0xe;
7424 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
7425                                         else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
7426 #else
7427                                         else if (pstat->is_ralink_sta)
7428 #endif
7429                                                 priv->pshare->txop_enlarge = 0xd;
7430                                         else
7431                                                 priv->pshare->txop_enlarge = 2;
7432
7433                                         if (priv->pshare->iot_mode_enable)
7434                                                 switch_turbo++;
7435                                 }
7436 #endif
7437                         }
7438                         else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
7439                         {
7440                                 if (priv->pshare->txop_enlarge) {
7441                                         priv->pshare->txop_enlarge = 0;
7442                                         if (priv->pshare->iot_mode_enable)
7443                                                 switch_turbo++;
7444                                 }
7445                         }
7446
7447 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&( defined LOW_TP_TXOP))
7448                         // for Intel IOT, need to enlarge CW MAX from 6 to 10
7449                         if (pstat && pstat->is_intel_sta && (((pstat->tx_avarage+pstat->rx_avarage)>>10) <
7450                                         priv->pshare->rf_ft_var.cwmax_enhance_thd))
7451                         {
7452                                 if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable)
7453                                 {
7454                                         priv->pshare->BE_cwmax_enhance = 1;
7455                                         switch_turbo++;
7456                                 }
7457                         } else {
7458                                 if (priv->pshare->BE_cwmax_enhance) {
7459                                         priv->pshare->BE_cwmax_enhance = 0;
7460                                         switch_turbo++;
7461                                 }
7462                         }
7463 #endif
7464                 }
7465 #endif
7466                 priv->pshare->current_tx_bytes = 0;
7467                 priv->pshare->current_rx_bytes = 0;
7468         }
7469
7470 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined( SW_TX_QUEUE))
7471         if ((priv->assoc_num > 1) && (AMPDU_ENABLE))
7472         {
7473         if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd) {
7474                         if ((priv->swq_en == 0)) {
7475                                 switch_turbo++;
7476                                 if (priv->pshare->txop_enlarge == 0)
7477                                         priv->pshare->txop_enlarge = 2;
7478                                 priv->swq_en = 1;
7479                                 }
7480                         else
7481                         {
7482                                 if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))
7483                                 {
7484                                         priv->pshare->txop_enlarge = 2;
7485                                         switch_turbo--;
7486                                 }
7487                         }
7488                 }
7489                 else if (priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd) {
7490                         priv->swq_en = 0;
7491                 }
7492                 else if ((priv->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))        {
7493                         priv->pshare->txop_enlarge = 2;
7494                 switch_turbo--;
7495         }
7496     }
7497 #endif
7498
7499 #ifdef WIFI_WMM
7500 #ifdef LOW_TP_TXOP
7501         if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2))
7502                 && QOS_ENABLE) {
7503                 if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) {
7504                         unsigned int thd_tp;
7505                         unsigned char under_thd;
7506                         unsigned int curr_tp;
7507
7508                         if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G))
7509                         {
7510                                 // Determine the upper bound throughput threshold.
7511                                 if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G)) {
7512                                         if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num)
7513                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
7514                                         else
7515                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n;
7516                                 }
7517                                 else
7518                                         thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
7519
7520                                 // Determine to close txop.
7521                                 curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17);
7522                                 if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low)
7523                                         under_thd = 1;
7524                                 else
7525                                         under_thd = 0;
7526                         }
7527                         else
7528                         {
7529                                 under_thd = 0;
7530                         }
7531
7532                         if (switch_turbo)
7533                         {
7534                                 priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
7535                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
7536                         }
7537                         else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) {
7538                                 priv->pshare->rf_ft_var.low_tp_txop_count++;
7539                                 if (priv->pshare->rf_ft_var.low_tp_txop_close) {
7540                                         priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;;
7541                                 }
7542                                 if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay)
7543
7544                                 {
7545                                         priv->pshare->rf_ft_var.low_tp_txop_count = 0;
7546                                         priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
7547                                         switch_turbo++;
7548                                 }
7549                         }
7550                         else
7551                         {
7552                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
7553                         }
7554                 }
7555         }
7556 #endif
7557
7558         if (switch_turbo)
7559                 ODM_IotEdcaSwitch( pDM_Odm, priv->pshare->iot_mode_enable );
7560 #endif
7561 }
7562 #endif
7563
7564
7565 #if ( DM_ODM_SUPPORT_TYPE == ODM_MP)
7566 //
7567 // 2011/07/26 MH Add an API for testing IQK fail case.
7568 //
7569 bool
7570 ODM_CheckPowerStatus(
7571         PADAPTER                Adapter)
7572 {
7573
7574         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
7575         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
7576         RT_RF_POWER_STATE       rtState;
7577         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);
7578
7579         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
7580         if (pMgntInfo->init_adpt_in_progress == true)
7581         {
7582                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return true, due to initadapter"));
7583                 return  true;
7584         }
7585
7586         //
7587         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
7588         //
7589         Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
7590         if (Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
7591         {
7592                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return false, due to %d/%d/%d\n",
7593                 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
7594                 return  false;
7595         }
7596         return  true;
7597 }
7598 #endif
7599
7600 // need to ODM CE Platform
7601 //move to here for ANT detection mechanism using
7602
7603 #if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE))
7604 u4Byte
7605 GetPSDData(
7606         PDM_ODM_T       pDM_Odm,
7607         unsigned int    point,
7608         u1Byte initial_gain_psd)
7609 {
7610         //unsigned int  val, rfval;
7611         //int   psd_report;
7612         u4Byte  psd_report;
7613
7614         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
7615         //Debug Message
7616         //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord);
7617         //DbgPrint("Reg908 = 0x%x\n",val);
7618         //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord);
7619         //rfval = PHY_QueryRFReg(Adapter, RF_PATH_A, 0x00, bRFRegOffsetMask);
7620         //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval);
7621         //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n",
7622                 //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval);
7623
7624         //Set DCO frequency index, offset=(40MHz/SamplePts)*point
7625         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
7626
7627         //Start PSD calculation, Reg808[22]=0->1
7628         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
7629         //Need to wait for HW PSD report
7630         ODM_StallExecution(30);
7631         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
7632         //Read PSD report, Reg8B4[15:0]
7633         psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
7634
7635         psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
7636         return psd_report;
7637
7638 }
7639
7640 u4Byte
7641 ConvertTo_dB(
7642         u4Byte  Value)
7643 {
7644         u1Byte i;
7645         u1Byte j;
7646         u4Byte dB;
7647
7648         Value = Value & 0xFFFF;
7649
7650         for (i=0;i<8;i++)
7651         {
7652                 if (Value <= dB_Invert_Table[i][11])
7653                 {
7654                         break;
7655                 }
7656         }
7657
7658         if (i >= 8)
7659         {
7660                 return (96);    // maximum 96 dB
7661         }
7662
7663         for (j=0;j<12;j++)
7664         {
7665                 if (Value <= dB_Invert_Table[i][j])
7666                 {
7667                         break;
7668                 }
7669         }
7670
7671         dB = i*12 + j + 1;
7672
7673         return (dB);
7674 }
7675
7676 #endif
7677
7678 //
7679 // LukeLee:
7680 // PSD function will be moved to FW in future IC, but now is only implemented in MP platform
7681 // So PSD function will not be incorporated to common ODM
7682 //
7683 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
7684
7685 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD
7686 #define MODE_40M                0       //0:20M, 1:40M
7687 #define PSD_TH2         3
7688 #define PSD_CHM 20   // Minimum channel number for BT AFH
7689 #define SIR_STEP_SIZE   3
7690 #define   Smooth_Size_1         5
7691 #define Smooth_TH_1     3
7692 #define   Smooth_Size_2         10
7693 #define Smooth_TH_2     4
7694 #define   Smooth_Size_3         20
7695 #define Smooth_TH_3     4
7696 #define   Smooth_Step_Size 5
7697 #define Adaptive_SIR    1
7698 //#if (RTL8723_FPGA_VERIFICATION == 1)
7699 //#define       PSD_RESCAN              1
7700 //#else
7701 //#define       PSD_RESCAN              4
7702 //#endif
7703 #define SCAN_INTERVAL   700 //ms
7704 #define SYN_Length              5    // for 92D
7705
7706 #define LNA_Low_Gain_1                      0x64
7707 #define LNA_Low_Gain_2                      0x5A
7708 #define LNA_Low_Gain_3                      0x58
7709
7710 #define pw_th_10dB                                      0x0
7711 #define pw_th_16dB                                      0x3
7712
7713 #define FA_RXHP_TH1                           5000
7714 #define FA_RXHP_TH2                           1500
7715 #define FA_RXHP_TH3                             800
7716 #define FA_RXHP_TH4                             600
7717 #define FA_RXHP_TH5                             500
7718
7719 #define Idle_Mode                                       0
7720 #define High_TP_Mode                            1
7721 #define Low_TP_Mode                             2
7722
7723
7724 void
7725 odm_PSDMonitorInit(
7726         PDM_ODM_T       pDM_Odm)
7727 {
7728 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
7729         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
7730         //PSD Monitor Setting
7731         //Which path in ADC/DAC is turnned on for PSD: both I/Q
7732         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);
7733         //Ageraged number: 8
7734         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);
7735         pDM_Odm->bPSDinProcess = false;
7736         pDM_Odm->bUserAssignLevel = false;
7737
7738         //pDM_Odm->bDMInitialGainEnable=true;           //change the initialization to DIGinit
7739         //Set Debug Port
7740         //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);
7741         //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD
7742         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan
7743         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte1, 0x32); // PSDDelay
7744         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval
7745
7746         //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms
7747 #endif
7748 }
7749
7750 void
7751 PatchDCTone(
7752         PDM_ODM_T       pDM_Odm,
7753         pu4Byte         PSD_report,
7754         u1Byte          initial_gain_psd
7755 )
7756 {
7757         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
7758         //PADAPTER      pAdapter;
7759
7760         u4Byte  psd_report;
7761
7762         //2 Switch to CH11 to patch CH9 and CH13 DC tone
7763         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 11);
7764
7765         if (pDM_Odm->SupportICType== ODM_RTL8192D)
7766         {
7767                 if ((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
7768                 {
7769                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 11);
7770                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, 0xfffff, 0x643BC);
7771                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, 0xfffff, 0xFC038);
7772                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x77C1A);
7773                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, 0xfffff, 0x41289);
7774                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, 0xfffff, 0x01840);
7775                 }
7776                 else
7777                 {
7778                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, 0xfffff, 0x643BC);
7779                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, 0xfffff, 0xFC038);
7780                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x77C1A);
7781                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, 0xfffff, 0x41289);
7782                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, 0xfffff, 0x01840);
7783                 }
7784         }
7785
7786         //Ch9 DC tone patch
7787         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
7788         PSD_report[50] = psd_report;
7789         //Ch13 DC tone patch
7790         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
7791         PSD_report[70] = psd_report;
7792
7793         //2 Switch to CH3 to patch CH1 and CH5 DC tone
7794         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, 3);
7795
7796
7797         if (pDM_Odm->SupportICType==ODM_RTL8192D)
7798         {
7799                 if ((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
7800                 {
7801                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, 3);
7802                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, 0xfffff, 0x643BC);
7803                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, 0xfffff, 0xFC038);
7804                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, 0xfffff, 0x07C1A);
7805                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, 0xfffff, 0x61289);
7806                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, 0xfffff, 0x01C41);
7807                 }
7808                 else
7809                 {
7810                         //PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, 0xfffff, 0x643BC);
7811                         //PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, 0xfffff, 0xFC038);
7812                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, 0xfffff, 0x07C1A);
7813                         //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, 0xfffff, 0x61289);
7814                         //PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, 0xfffff, 0x01C41);
7815                 }
7816         }
7817
7818         //Ch1 DC tone patch
7819         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
7820         PSD_report[10] = psd_report;
7821         //Ch5 DC tone patch
7822         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
7823         PSD_report[30] = psd_report;
7824
7825 }
7826
7827
7828 void
7829 GoodChannelDecision(
7830         PDM_ODM_T       pDM_Odm,
7831         ps4Byte         PSD_report,
7832         pu1Byte         PSD_bitmap,
7833         u1Byte          RSSI_BT,
7834         pu1Byte         PSD_bitmap_memory)
7835 {
7836         pRXHP_T                 pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
7837         //s4Byte        TH1 =  SSBT-0x15;    // modify TH by Neil Chen
7838         s4Byte  TH1= RSSI_BT+0x14;
7839         s4Byte  TH2 = RSSI_BT+85;
7840         //u2Byte    TH3;
7841 //      s4Byte  RegB34;
7842         u1Byte  bitmap, Smooth_size[3], Smooth_TH[3];
7843         //u1Byte        psd_bit;
7844         u4Byte  i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];
7845         int             start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;
7846
7847 //      RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;
7848
7849         if ((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))
7850        {
7851             TH1 = RSSI_BT + 0x14;
7852         }
7853
7854         Smooth_size[0]=Smooth_Size_1;
7855         Smooth_size[1]=Smooth_Size_2;
7856         Smooth_size[2]=Smooth_Size_3;
7857         Smooth_TH[0]=Smooth_TH_1;
7858         Smooth_TH[1]=Smooth_TH_2;
7859         Smooth_TH[2]=Smooth_TH_3;
7860         Smooth_Interval[0]=16;
7861         Smooth_Interval[1]=15;
7862         Smooth_Interval[2]=13;
7863         good_cnt = 0;
7864         if (pDM_Odm->SupportICType==ODM_RTL8723A)
7865         {
7866                 //2 Threshold
7867
7868                 if (RSSI_BT >=41)
7869                         TH1 = 113;
7870                 else if (RSSI_BT >=38)   // >= -15dBm
7871                         TH1 = 105;                              //0x69
7872                 else if ((RSSI_BT >=33)&(RSSI_BT <38))
7873                         TH1 = 99+(RSSI_BT-33);         //0x63
7874                 else if ((RSSI_BT >=26)&(RSSI_BT<33))
7875                         TH1 = 99-(33-RSSI_BT)+2;     //0x5e
7876                 else if ((RSSI_BT >=24)&(RSSI_BT<26))
7877                         TH1 = 88-((RSSI_BT-24)*3);   //0x58
7878                 else if ((RSSI_BT >=18)&(RSSI_BT<24))
7879                         TH1 = 77+((RSSI_BT-18)*2);
7880                 else if ((RSSI_BT >=14)&(RSSI_BT<18))
7881                         TH1 = 63+((RSSI_BT-14)*2);
7882                 else if ((RSSI_BT >=8)&(RSSI_BT<14))
7883                         TH1 = 58+((RSSI_BT-8)*2);
7884                 else if ((RSSI_BT >=3)&(RSSI_BT<8))
7885                         TH1 = 52+(RSSI_BT-3);
7886                 else
7887                         TH1 = 51;
7888         }
7889
7890         for (i = 0; i< 10; i++)
7891                 PSD_bitmap[i] = 0;
7892
7893
7894          // Add By Gary
7895        for (i=0; i<80; i++)
7896                 pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;
7897         // End
7898
7899
7900
7901         if (pDM_Odm->SupportICType==ODM_RTL8723A)
7902         {
7903                 TH1 =TH1-SIR_STEP_SIZE;
7904         }
7905         while (good_cnt < PSD_CHMIN)
7906         {
7907                 good_cnt = 0;
7908                 if (pDM_Odm->SupportICType==ODM_RTL8723A)
7909                 {
7910                 if (TH1 ==TH2)
7911                         break;
7912                 if ((TH1+SIR_STEP_SIZE) < TH2)
7913                         TH1 += SIR_STEP_SIZE;
7914                 else
7915                         TH1 = TH2;
7916                 }
7917                 else
7918                 {
7919                         if (TH1==(RSSI_BT+0x1E))
7920                              break;
7921                         if ((TH1+2) < (RSSI_BT+0x1E))
7922                                 TH1+=3;
7923                         else
7924                                 TH1 = RSSI_BT+0x1E;
7925
7926                 }
7927                 ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));
7928
7929                 for (i = 0; i< 80; i++)
7930                 {
7931                         if (PSD_report[i] < TH1)
7932                         {
7933                                 byte_idx = i / 8;
7934                                 bit_idx = i -8*byte_idx;
7935                                 bitmap = PSD_bitmap[byte_idx];
7936                                 PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);
7937                         }
7938                 }
7939
7940 #if DBG
7941                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));
7942                 for (n=0;n<10;n++)
7943                 {
7944                         //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);
7945                         for (i = 0; i<8; i++)
7946                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
7947                 }
7948 #endif
7949
7950                 //1 Start of smoothing function
7951
7952                 for (j=0;j<3;j++)
7953                 {
7954                         start_byte_idx=0;
7955                         start_bit_idx=0;
7956                         for (n=0; n<Smooth_Interval[j]; n++)
7957                         {
7958                                 good_cnt_smoothing = 0;
7959                                 cur_bit_idx = start_bit_idx;
7960                                 cur_byte_idx = start_byte_idx;
7961                                 for ( i=0; i < Smooth_size[j]; i++)
7962                                 {
7963                                         NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
7964                                         if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)
7965                                                 good_cnt_smoothing++;
7966
7967                                 }
7968
7969                                 if ( good_cnt_smoothing < Smooth_TH[j] )
7970                                 {
7971                                         cur_bit_idx = start_bit_idx;
7972                                         cur_byte_idx = start_byte_idx;
7973                                         for ( i=0; i< Smooth_size[j] ; i++)
7974                                         {
7975                                                 NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
7976                                                 PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));
7977                                         }
7978                                 }
7979                                 start_bit_idx =  start_bit_idx + Smooth_Step_Size;
7980                                 while ( (start_bit_idx)  > 7 )
7981                                 {
7982                                         start_byte_idx= start_byte_idx+start_bit_idx/8;
7983                                         start_bit_idx = start_bit_idx%8;
7984                                 }
7985                         }
7986
7987                         ODM_RT_TRACE(   pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));
7988                         for (n=0;n<10;n++)
7989                         {
7990                                 for (i = 0; i<8; i++)
7991                                 {
7992                                         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
7993
7994                                         if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1)  //----- Add By Gary
7995                                         {
7996                                            pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;
7997                                         }                                                  // ------end by Gary
7998                                 }
7999                         }
8000
8001                 }
8002
8003
8004                 good_cnt = 0;
8005                 for ( i = 0; i < 10; i++)
8006                 {
8007                         for (n = 0; n < 8; n++)
8008                                 if ((PSD_bitmap[i]& BIT(n)) != 0)
8009                                         good_cnt++;
8010                 }
8011                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: good channel cnt = %u",good_cnt));
8012         }
8013
8014         //RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));
8015         for (i = 0; i <10; i++)
8016                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));
8017 /*
8018         //Update bitmap memory
8019         for (i = 0; i < 80; i++)
8020         {
8021                 byte_idx = i / 8;
8022                 bit_idx = i -8*byte_idx;
8023                 psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;
8024                 bitmap = PSD_bitmap_memory[i];
8025                 PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;
8026         }
8027 */
8028 }
8029
8030
8031
8032 void
8033 odm_PSD_Monitor(
8034         PDM_ODM_T       pDM_Odm
8035 )
8036 {
8037         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8038         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
8039
8040
8041        unsigned int             pts, start_point, stop_point, initial_gain ;
8042         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
8043         static u1Byte           psd_cnt=0;
8044         static u4Byte           PSD_report[80], PSD_report_tmp;
8045         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
8046         u1Byte                  H2C_PSD_DATA[5]={0,0,0,0,0};
8047         static u1Byte           H2C_PSD_DATA_last[5] ={0,0,0,0,0};
8048         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
8049                                         0,3,6,10,13,16,19,22,26,29};
8050         u1Byte                  n, i, channel, BBReset,tone_idx;
8051         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
8052         s4Byte                          PSD_skip_start, PSD_skip_stop;
8053         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
8054         u4Byte                  ReScan, Interval, Is40MHz;
8055         u8Byte                  curTxOkCnt, curRxOkCnt;
8056         int                             cur_byte_idx, cur_bit_idx;
8057         PADAPTER                Adapter = pDM_Odm->Adapter;
8058         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
8059         //--------------2G band synthesizer for 92D switch RF channel using-----------------
8060         u1Byte                  group_idx=0;
8061         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;
8062         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel
8063         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}
8064                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14
8065                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8
8066        //--------------------- Add by Gary for Debug setting ----------------------
8067        s4Byte                 psd_result = 0;
8068         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);
8069        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);
8070        //---------------------------------------------------------------------
8071
8072         if (*(pDM_Odm->pbScanInProcess))
8073         {
8074                 if ((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
8075         {
8076                         //pHalData->bPSDactive=false;
8077                         //ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 )
8078                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 900); //ms
8079                         //psd_cnt=0;
8080                 }
8081                 return;
8082         }
8083
8084         ReScan = PSD_RESCAN;
8085         Interval = SCAN_INTERVAL;
8086
8087
8088         //1 Initialization
8089         if (init_memory == 0)
8090         {
8091                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Init memory\n"));
8092                 for (i = 0; i < 80; i++)
8093                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
8094                 init_memory = 1;
8095         }
8096         if (psd_cnt == 0)
8097         {
8098                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
8099                 for (i = 0; i < 80; i++)
8100                         PSD_report[i] = 0;
8101         }
8102         //1 Backup Current Settings
8103         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
8104         //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
8105         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
8106
8107         //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;
8108         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
8109
8110         //2???
8111         Is40MHz = pMgntInfo->pHTInfo->bCurBW40MHz;
8112
8113         ODM_RT_TRACE(pDM_Odm,   COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
8114         //1 Turn off CCK
8115         //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
8116         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
8117         //1 Turn off TX
8118         //Pause TX Queue
8119         //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
8120         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
8121
8122         //Force RX to stop TX immediately
8123         //PHY_SetRFReg(Adapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
8124
8125         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
8126         //1 Turn off RX
8127         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
8128         //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);
8129         //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);
8130
8131         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
8132         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
8133
8134
8135         //Turn off CCA
8136         //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
8137         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
8138
8139         //BB Reset
8140         //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
8141         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
8142
8143         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
8144         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
8145
8146         ODM_Write1Byte(pDM_Odm,  0x02, BBReset&(~BIT0));
8147         ODM_Write1Byte(pDM_Odm,  0x02, BBReset|BIT0);
8148
8149         //1 Leave RX idle low power
8150         //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);
8151
8152         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
8153         //1 Fix initial gain
8154         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
8155         //RSSI_BT = pHalData->RSSI_BT;
8156        //else if ((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))      // Add by Gary
8157        //    RSSI_BT = RSSI_BT_new;
8158
8159         if ((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
8160                 RSSI_BT=pDM_Odm->RSSI_BT;               //need to check C2H to pDM_Odm RSSI BT
8161
8162         else if ((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D))
8163            RSSI_BT = RSSI_BT_new;
8164
8165
8166
8167         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
8168
8169         if (pDM_Odm->SupportICType==ODM_RTL8723A)
8170         {
8171                //Neil add--2011--10--12
8172                 //2 Initial Gain index
8173                 if (RSSI_BT >=35)   // >= -15dBm
8174                         initial_gain_psd = RSSI_BT*2;
8175                 else if ((RSSI_BT >=33)&(RSSI_BT<35))
8176                         initial_gain_psd = RSSI_BT*2+6;
8177                 else if ((RSSI_BT >=24)&(RSSI_BT<33))
8178                         initial_gain_psd = 70-(31-RSSI_BT);
8179                 else if ((RSSI_BT >=19)&(RSSI_BT<24))
8180                         initial_gain_psd = 64-((24-RSSI_BT)*4);
8181                 else if ((RSSI_BT >=14)&(RSSI_BT<19))
8182                         initial_gain_psd = 44-((18-RSSI_BT)*2);
8183                 else if ((RSSI_BT >=8)&(RSSI_BT<14))
8184                         initial_gain_psd = 35-(14-RSSI_BT);
8185                 else
8186                         initial_gain_psd = 0x1B;
8187         }
8188         else
8189         {
8190                 if (rssi_ctrl == 1)        // just for debug!!
8191                         initial_gain_psd = RSSI_BT_new ;
8192                 else
8193                 {
8194                         //need to do
8195                         initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
8196                 }
8197         }
8198         //if (RSSI_BT<0x17)
8199         //      RSSI_BT +=3;
8200         //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);
8201         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
8202
8203         //initialGainUpper = 0x5E;  //Modify by neil chen
8204
8205         if (pDM_Odm->bUserAssignLevel)
8206         {
8207                 pDM_Odm->bUserAssignLevel = false;
8208                 initialGainUpper = 0x7f;
8209         }
8210         else
8211         {
8212                 initialGainUpper = 0x5E;
8213         }
8214
8215         /*
8216         if (initial_gain_psd < 0x1a)
8217                 initial_gain_psd = 0x1a;
8218         if (initial_gain_psd > initialGainUpper)
8219                 initial_gain_psd = initialGainUpper;
8220         */
8221
8222         if (pDM_Odm->SupportICType==ODM_RTL8723A)
8223                 SSBT = RSSI_BT  * 2 +0x3E;
8224         else if ((pDM_Odm->SupportICType==ODM_RTL8192C)||(pDM_Odm->SupportICType==ODM_RTL8192D))
8225         {
8226                 RSSI_BT = initial_gain_psd;
8227                 SSBT = RSSI_BT;
8228         }
8229
8230         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
8231         //      SSBT = RSSI_BT  * 2 +0x3E;
8232         //else if ((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))   // Add by Gary
8233         //{
8234         //      RSSI_BT = initial_gain_psd;
8235         //      SSBT = RSSI_BT;
8236         //}
8237         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
8238         ODM_RT_TRACE(   pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
8239         //DbgPrint("PSD: SSBT= %d", SSBT);
8240         //need to do
8241         //pMgntInfo->bDMInitialGainEnable = false;
8242         pDM_Odm->bDMInitialGainEnable = false;
8243         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;
8244         ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd);
8245         //1 Turn off 3-wire
8246         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
8247
8248         //pts value = 128, 256, 512, 1024
8249         pts = 128;
8250
8251         if (pts == 128)
8252         {
8253                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
8254                 start_point = 64;
8255                 stop_point = 192;
8256         }
8257         else if (pts == 256)
8258         {
8259                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
8260                 start_point = 128;
8261                 stop_point = 384;
8262         }
8263         else if (pts == 512)
8264         {
8265                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
8266                 start_point = 256;
8267                 stop_point = 768;
8268         }
8269         else
8270         {
8271                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
8272                 start_point = 512;
8273                 stop_point = 1536;
8274         }
8275
8276
8277 //3 Skip WLAN channels if WLAN busy
8278
8279         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
8280         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
8281         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
8282         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
8283
8284         PSD_skip_start=80;
8285         PSD_skip_stop = 0;
8286         wlan_channel = CurrentChannel & 0x0f;
8287
8288         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d\n", wlan_channel, Is40MHz));
8289         if (pDM_Odm->SupportICType==ODM_RTL8723A)
8290         {
8291 #if (BT_30_SUPPORT == 1)
8292                 if (pDM_Odm->bBtHsOperation)
8293                 {
8294                         if (pDM_Odm->bLinked)
8295                         {
8296                                 if (Is40MHz)
8297                                 {
8298                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
8299                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
8300                                 }
8301                                 else
8302                                 {
8303                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
8304                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
8305                                 }
8306                         }
8307                         else
8308                         {
8309                                 // mask for 40MHz
8310                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
8311                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
8312                         }
8313                         if (PSD_skip_start < 0)
8314                                 PSD_skip_start = 0;
8315                         if (PSD_skip_stop >80)
8316                                 PSD_skip_stop = 80;
8317                 }
8318                 else
8319 #endif
8320                 {
8321                 if ((curRxOkCnt+curTxOkCnt) > 5)
8322                 {
8323                         if (Is40MHz)
8324                         {
8325                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
8326                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
8327                         }
8328                         else
8329                         {
8330                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
8331                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
8332                         }
8333
8334                         if (PSD_skip_start < 0)
8335                                 PSD_skip_start = 0;
8336                         if (PSD_skip_stop >80)
8337                                 PSD_skip_stop = 80;
8338                 }
8339         }
8340         }
8341         else
8342         {
8343                 if ((curRxOkCnt+curTxOkCnt) > 1000)
8344                 {
8345                         PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
8346                         PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
8347                 }
8348         }
8349
8350         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d\n", PSD_skip_start, PSD_skip_stop));
8351
8352         for (n=0;n<80;n++)
8353         {
8354                 if ((n%20)==0)
8355                 {
8356                         channel = (n/20)*4 + 1;
8357                         /*
8358                         if (pDM_Odm->SupportICType==ODM_RTL8192D)
8359                         {
8360                                 switch (channel)
8361                                 {
8362                                         case 1:
8363                                         case 9:
8364                                                 group_idx = 0;
8365                                                 break;
8366                                         case 5:
8367                                                 group_idx = 2;
8368                                                 break;
8369                                         case 13:
8370                                                 group_idx = 1;
8371                                                 break;
8372                                 }
8373
8374                                 if ((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY))
8375                                 {
8376                                         for (i = 0; i < SYN_Length; i++)
8377                                                 ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
8378
8379                                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
8380                                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel);
8381                                 }
8382                                 else  // DualMAC_DualPHY 2G
8383                                 {
8384                                         for (i = 0; i < SYN_Length; i++)
8385                                                 ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
8386
8387                                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
8388                                 }
8389                         }
8390                         else */
8391                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
8392                 }
8393                 tone_idx = n%20;
8394                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
8395                 {
8396                         PSD_report[n] = SSBT;
8397                         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped\n", n));
8398                 }
8399                 else
8400                 {
8401                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
8402
8403                         if ( PSD_report_tmp > PSD_report[n])
8404                                 PSD_report[n] = PSD_report_tmp;
8405
8406                 }
8407         }
8408
8409         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
8410
8411        //----end
8412         //1 Turn on RX
8413         //Rx AGC on
8414         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
8415         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
8416         //CCK on
8417         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
8418         //1 Turn on TX
8419         //Resume TX Queue
8420
8421         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);
8422         //Turn on 3-wire
8423         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
8424         //1 Restore Current Settings
8425         //Resume DIG
8426         pDM_Odm->bDMInitialGainEnable = true;
8427         ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);
8428         // restore originl center frequency
8429         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
8430
8431         /*
8432         if (pDM_Odm->SupportICType==ODM_RTL8192D)
8433         {
8434                 if ((pHalData->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY))
8435                 {
8436                         PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);
8437                         PHY_SetRFReg(Adapter, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);
8438                         PHY_SetRFReg(Adapter, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);
8439                         PHY_SetRFReg(Adapter, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);
8440                         PHY_SetRFReg(Adapter, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);
8441                         PHY_SetRFReg(Adapter, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);
8442                 }
8443                 else     // DualMAC_DualPHY
8444                 {
8445                         PHY_SetRFReg(Adapter, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);
8446                         PHY_SetRFReg(Adapter, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);
8447                         PHY_SetRFReg(Adapter, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);
8448                         PHY_SetRFReg(Adapter, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);
8449                         PHY_SetRFReg(Adapter, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);
8450                 }
8451         }*/
8452         //Turn on CCA
8453         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
8454         //Restore RX idle low power
8455         if (RxIdleLowPwr == true)
8456                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
8457
8458         psd_cnt++;
8459         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d\n",psd_cnt));
8460         if (psd_cnt < ReScan)
8461                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval);
8462         else
8463         {
8464                 psd_cnt = 0;
8465                 for (i=0;i<80;i++)
8466                         //DbgPrint("psd_report[%d]=     %d\n", 2402+i, PSD_report[i]);
8467                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d\n", 2402+i, PSD_report[i]));
8468
8469
8470                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
8471
8472                 if (pDM_Odm->SupportICType==ODM_RTL8723A)
8473                 {
8474                         cur_byte_idx=0;
8475                         cur_bit_idx=0;
8476
8477                         //2 Restore H2C PSD Data to Last Data
8478                         H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];
8479                         H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];
8480                         H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];
8481                         H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];
8482                         H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];
8483
8484
8485                         //2 Translate 80bit channel map to 40bit channel
8486                         for ( i=0;i<5;i++)
8487                         {
8488                                 for (n=0;n<8;n++)
8489                                 {
8490                                         cur_byte_idx = i*2 + n/4;
8491                                         cur_bit_idx = (n%4)*2;
8492                                         if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))
8493                                                 H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);
8494                                 }
8495                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));
8496                         }
8497
8498                         //3 To Compare the difference
8499                         for ( i=0;i<5;i++)
8500                         {
8501                                 if (H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])
8502                                 {
8503                                         FillH2CCmd(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);
8504                                         ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("Need to Update the AFH Map\n"));
8505                                         break;
8506                                 }
8507                                 else
8508                                 {
8509                                         if (i==5)
8510                                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("Not need to Update\n"));
8511                                 }
8512                         }
8513                         //pHalData->bPSDactive=false;
8514                         ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 900);
8515                         ODM_RT_TRACE(   pDM_Odm,COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
8516                 }
8517         }
8518 }
8519 /*
8520 //Neil for Get BT RSSI
8521 // Be Triggered by BT C2H CMD
8522 void
8523 ODM_PSDGetRSSI(
8524         u1Byte  RSSI_BT)
8525 {
8526
8527
8528 }
8529
8530 */
8531
8532 void
8533 ODM_PSDMonitor(
8534         PDM_ODM_T       pDM_Odm
8535         )
8536 {
8537         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
8538
8539         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
8540
8541         if (pDM_Odm->SupportICType == ODM_RTL8723A)   //may need to add other IC type
8542         {
8543                 if (pDM_Odm->SupportInterface==ODM_ITRF_PCIE)
8544                 {
8545 #if (BT_30_SUPPORT == 1)
8546                         if (pDM_Odm->bBtDisabled) //need to check upper layer connection
8547                 {
8548                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));
8549                    return;
8550                 }
8551 #endif
8552                         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));
8553                 //if (pHalData->bPSDactive ==false)
8554                 //{
8555                         pDM_Odm->bPSDinProcess = true;
8556                         //pHalData->bPSDactive=true;
8557                         odm_PSD_Monitor(pDM_Odm);
8558                         pDM_Odm->bPSDinProcess = false;
8559                 }
8560         }
8561
8562 }
8563 void
8564 odm_PSDMonitorCallback(
8565         PRT_TIMER               pTimer
8566 )
8567 {
8568         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
8569        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
8570         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
8571
8572
8573 #if USE_WORKITEM
8574         PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);
8575 #else
8576         ODM_PSDMonitor(pDM_Odm);
8577 #endif
8578 }
8579
8580 void
8581 odm_PSDMonitorWorkItemCallback(
8582     void *            pContext
8583     )
8584 {
8585         PADAPTER        Adapter = (PADAPTER)pContext;
8586         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
8587         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
8588
8589
8590         ODM_PSDMonitor(pDM_Odm);
8591 }
8592
8593
8594
8595  //cosa debug tool need to modify
8596
8597 void
8598 ODM_PSDDbgControl(
8599         PADAPTER        Adapter,
8600         u4Byte          mode,
8601         u4Byte          btRssi
8602         )
8603 {
8604 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
8605         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
8606         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
8607
8608         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));
8609         if (mode)
8610         {
8611                 pDM_Odm->RSSI_BT = (u1Byte)btRssi;
8612                 pDM_Odm->bUserAssignLevel = true;
8613                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms
8614         }
8615         else
8616         {
8617                 ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
8618         }
8619 #endif
8620 }
8621
8622
8623 //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
8624
8625 void    odm_RXHPInit(
8626                 PDM_ODM_T               pDM_Odm)
8627 {
8628 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
8629         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
8630         u1Byte                  index;
8631
8632         pRX_HP_Table->RXHP_enable = true;
8633         pRX_HP_Table->RXHP_flag = 0;
8634         pRX_HP_Table->PSD_func_trigger = 0;
8635         pRX_HP_Table->Pre_IGI = 0x20;
8636         pRX_HP_Table->Cur_IGI = 0x20;
8637         pRX_HP_Table->Cur_pw_th = pw_th_10dB;
8638         pRX_HP_Table->Pre_pw_th = pw_th_10dB;
8639         for (index=0; index<80; index++)
8640                 pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;
8641
8642 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8643         pRX_HP_Table->TP_Mode = Idle_Mode;
8644 #endif
8645 #endif
8646 }
8647
8648 void odm_RXHP(
8649                 PDM_ODM_T               pDM_Odm)
8650 {
8651 #if ( DM_ODM_SUPPORT_TYPE & (ODM_MP))
8652 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
8653         PADAPTER        Adapter =  pDM_Odm->Adapter;
8654         PMGNT_INFO      pMgntInfo = &(Adapter->MgntInfo);
8655         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;
8656         pRXHP_T         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
8657        PFALSE_ALARM_STATISTICS          FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
8658
8659         u1Byte                  i, j, sum;
8660         u1Byte                  Is40MHz;
8661         s1Byte                  Intf_diff_idx, MIN_Intf_diff_idx = 16;
8662        s4Byte                   cur_channel;
8663        u1Byte                   ch_map_intf_5M[17] = {0};
8664        static u4Byte            FA_TH = 0;
8665         static u1Byte           psd_intf_flag = 0;
8666         static s4Byte           curRssi = 0;
8667        static s4Byte            preRssi = 0;
8668         static u1Byte           PSDTriggerCnt = 1;
8669
8670         u1Byte                  RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31);   // for debug!!
8671
8672 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8673         static s8Byte           lastTxOkCnt = 0, lastRxOkCnt = 0;
8674        s8Byte                   curTxOkCnt, curRxOkCnt;
8675         s8Byte                  curTPOkCnt;
8676         s8Byte                  TP_Acc3, TP_Acc5;
8677         static s8Byte           TP_Buff[5] = {0};
8678         static u1Byte           pre_state = 0, pre_state_flag = 0;
8679         static u1Byte           Intf_HighTP_flag = 0, De_counter = 16;
8680         static u1Byte           TP_Degrade_flag = 0;
8681 #endif
8682         static u1Byte           LatchCnt = 0;
8683
8684         if ((pDM_Odm->SupportICType == ODM_RTL8723A)||(pDM_Odm->SupportICType == ODM_RTL8188E))
8685                 return;
8686         //AGC RX High Power Mode is only applied on 2G band in 92D!!!
8687         if (pDM_Odm->SupportICType == ODM_RTL8192D)
8688         {
8689                 if (*(pDM_Odm->pBandType) != ODM_BAND_2_4G)
8690                         return;
8691         }
8692
8693         if (!(pDM_Odm->SupportAbility==ODM_BB_RXHP))
8694                 return;
8695
8696
8697         //RX HP ON/OFF
8698         if (RX_HP_enable == 1)
8699                 pRX_HP_Table->RXHP_enable = false;
8700         else
8701                 pRX_HP_Table->RXHP_enable = true;
8702
8703         if (pRX_HP_Table->RXHP_enable == false)
8704         {
8705                 if (pRX_HP_Table->RXHP_flag == 1)
8706                 {
8707                         pRX_HP_Table->RXHP_flag = 0;
8708                         psd_intf_flag = 0;
8709                 }
8710                 return;
8711         }
8712
8713 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8714         //2 Record current TP for USB interface
8715         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
8716         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
8717         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
8718         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
8719
8720         curTPOkCnt = curTxOkCnt+curRxOkCnt;
8721         TP_Buff[0] = curTPOkCnt;    // current TP
8722         TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);
8723         TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);
8724
8725         if (TP_Acc5 < 1000)
8726                 pRX_HP_Table->TP_Mode = Idle_Mode;
8727         else if ((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))
8728                 pRX_HP_Table->TP_Mode = Low_TP_Mode;
8729         else
8730                 pRX_HP_Table->TP_Mode = High_TP_Mode;
8731
8732         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
8733         // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.
8734         // When LatchCnt = 0, we would Get PSD result.
8735         if (TP_Degrade_flag == 1)
8736         {
8737                 LatchCnt--;
8738                 if (LatchCnt == 0)
8739                 {
8740                         TP_Degrade_flag = 0;
8741                 }
8742         }
8743         // When PSD function triggered by TP degrade 20%, and Interference Flag = 1
8744         // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.
8745         if (Intf_HighTP_flag == 1)
8746         {
8747                 De_counter--;
8748                 if (De_counter == 0)
8749                 {
8750                         Intf_HighTP_flag = 0;
8751                         psd_intf_flag = 0;
8752                 }
8753         }
8754 #endif
8755
8756         //2 AGC RX High Power Mode by PSD only applied to STA Mode
8757         //3 NOT applied 1. Ad Hoc Mode.
8758         //3 NOT applied 2. AP Mode
8759         if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))
8760         {
8761                 Is40MHz = *(pDM_Odm->pBandWidth);
8762                 curRssi = pDM_Odm->RSSI_Min;
8763                 cur_channel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;
8764                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
8765                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
8766                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
8767                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
8768                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
8769         //2 PSD function would be triggered
8770         //3 1. Every 4 sec for PCIE
8771         //3 2. Before TP Mode (Idle TP<4kbps) for USB
8772         //3 3. After TP Mode (High TP) for USB
8773                 if ((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0))   // Only RSSI>TH and RX_HP_flag=0 will Do PSD process
8774                 {
8775 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8776                         //2 Before TP Mode ==> PSD would be trigger every 4 sec
8777                         if (pRX_HP_Table->TP_Mode == Idle_Mode)         //2.1 less wlan traffic <4kbps
8778                         {
8779 #endif
8780                                 if (PSDTriggerCnt == 1)
8781                                 {
8782                                         odm_PSD_RXHP(pDM_Odm);
8783                                         pRX_HP_Table->PSD_func_trigger = 1;
8784                                         PSDTriggerCnt = 0;
8785                                 }
8786                                 else
8787                                 {
8788                                         PSDTriggerCnt++;
8789                                 }
8790 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8791                         }
8792                         //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function
8793                         if (pRX_HP_Table->TP_Mode == High_TP_Mode)
8794                         {
8795                                 if ((pre_state_flag == 0)&&(LatchCnt == 0))
8796                                 {
8797                                         // TP var < 5%
8798                                         if ((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))
8799                                         {
8800                                                 pre_state++;
8801                                                 if (pre_state == 3)      // hit pre_state condition => consecutive 3 times
8802                                                 {
8803                                                         pre_state_flag = 1;
8804                                                         pre_state = 0;
8805                                                 }
8806
8807                                         }
8808                                         else
8809                                         {
8810                                                 pre_state = 0;
8811                                         }
8812                                 }
8813                                 //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%
8814                                 if (pre_state_flag == 1)
8815                                 {
8816                                         if (((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3))      // degrade 20%
8817                                         {
8818                                                 odm_PSD_RXHP(pDM_Odm);
8819                                                 pRX_HP_Table->PSD_func_trigger = 1;
8820                                                 TP_Degrade_flag = 1;
8821                                                 LatchCnt = 2;
8822                                                 pre_state_flag = 0;
8823                                         }
8824                                         else if (((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])
8825                                         {
8826                                                 odm_PSD_RXHP(pDM_Odm);
8827                                                 pRX_HP_Table->PSD_func_trigger = 1;
8828                                                 TP_Degrade_flag = 1;
8829                                                 LatchCnt = 2;
8830                                                 pre_state_flag = 0;
8831                                         }
8832                                         else if (((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])
8833                                         {
8834                                                 odm_PSD_RXHP(pDM_Odm);
8835                                                 pRX_HP_Table->PSD_func_trigger = 1;
8836                                                 TP_Degrade_flag = 1;
8837                                                 LatchCnt = 2;
8838                                                 pre_state_flag = 0;
8839                                         }
8840                                 }
8841                         }
8842 #endif
8843 }
8844
8845 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8846                 for (i=0;i<4;i++)
8847                 {
8848                         TP_Buff[4-i] = TP_Buff[3-i];
8849                 }
8850 #endif
8851                 //2 Update PSD bitmap according to PSD report
8852                 if ((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))
8853                 {
8854                         //2 Separate 80M bandwidth into 16 group with smaller 5M BW.
8855                         for (i = 0 ; i < 16 ; i++)
8856                         {
8857                                 sum = 0;
8858                                 for (j = 0; j < 5 ; j++)
8859                                         sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];
8860
8861                                 if (sum < 5)
8862                                 {
8863                                         ch_map_intf_5M[i] = 1;  // interference flag
8864                                 }
8865                         }
8866                         //=============just for debug=========================
8867                         //for (i=0;i<16;i++)
8868                                 //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);
8869                         //===============================================
8870                         //2 Mask target channel 5M index
8871                         for (i = 0; i < (4+4*Is40MHz) ; i++)
8872                         {
8873                                 ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0;
8874                         }
8875
8876                         psd_intf_flag = 0;
8877                         for (i = 0; i < 16; i++)
8878                         {
8879                                 if (ch_map_intf_5M[i] == 1)
8880                         {
8881                                 psd_intf_flag = 1;            // interference is detected!!!
8882                                 break;
8883                                 }
8884                         }
8885
8886 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
8887                         if (pRX_HP_Table->TP_Mode!=Idle_Mode)
8888                         {
8889                                 if (psd_intf_flag == 1)     // to avoid psd_intf_flag always 1
8890                                 {
8891                                         Intf_HighTP_flag = 1;
8892                                         De_counter = 32;     // 0x1E -> 0x3E needs 32 times by each IGI step =1
8893                                 }
8894                         }
8895 #endif
8896                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
8897                         //2 Distance between target channel and interference
8898                         for (i = 0; i < 16; i++)
8899                         {
8900                                 if (ch_map_intf_5M[i] == 1)
8901                                 {
8902                                         Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz));
8903                                 if (Intf_diff_idx < MIN_Intf_diff_idx)
8904                                                 MIN_Intf_diff_idx = Intf_diff_idx;    // the min difference index between interference and target
8905                                 }
8906                         }
8907                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
8908                         //2 Choose False Alarm Threshold
8909                         switch (MIN_Intf_diff_idx) {
8910                                 case 0:
8911                                 case 1:
8912                                 case 2:
8913                                 case 3:
8914                                         FA_TH = FA_RXHP_TH1;
8915                                 break;
8916                                 case 4:                         // CH5
8917                                 case 5:                         // CH6
8918                                         FA_TH = FA_RXHP_TH2;
8919                                 break;
8920                                 case 6:                         // CH7
8921                                 case 7:                         // CH8
8922                                         FA_TH = FA_RXHP_TH3;
8923                                         break;
8924                         case 8:                         // CH9
8925                                 case 9:                         //CH10
8926                                         FA_TH = FA_RXHP_TH4;
8927                                         break;
8928                                 case 10:
8929                                 case 11:
8930                                 case 12:
8931                                 case 13:
8932                                 case 14:
8933                                 case 15:
8934                                         FA_TH = FA_RXHP_TH5;
8935                                         break;
8936                 }
8937                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
8938                         pRX_HP_Table->PSD_func_trigger = 0;
8939                 }
8940                 //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode
8941                 if (pRX_HP_Table->RXHP_flag == 1)
8942                 {
8943                 if ((curRssi > 80)&&(preRssi < 80))
8944                 {
8945                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
8946                 }
8947                 else if ((curRssi < 80)&&(preRssi > 80))
8948                 {
8949                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
8950                         }
8951                 else if ((curRssi > 72)&&(preRssi < 72))
8952                         {
8953                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
8954                 }
8955                 else if ((curRssi < 72)&&( preRssi > 72))
8956                         {
8957                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
8958                 }
8959                 else if (curRssi < 68)           //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode
8960                 {
8961                                 pRX_HP_Table->Cur_pw_th = pw_th_10dB;
8962                                 pRX_HP_Table->RXHP_flag = 0;    // Back to Normal DIG Mode
8963                                 psd_intf_flag = 0;
8964                         }
8965                 }
8966                 else    // pRX_HP_Table->RXHP_flag == 0
8967                 {
8968                         //1 Decide whether to enter AGC RX High Power Mode
8969                         if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) &&
8970                                 (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))
8971                         {
8972                                 if (curRssi > 80)
8973                                 {
8974                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
8975                                 }
8976                                 else if (curRssi > 72)
8977                         {
8978                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
8979                                 }
8980                                 else
8981                                 {
8982                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
8983                                 }
8984                                 pRX_HP_Table->Cur_pw_th = pw_th_16dB;           //RegC54[9:8]=2'b11: to enter AGC Flow 3
8985                                 pRX_HP_Table->First_time_enter = true;
8986                                 pRX_HP_Table->RXHP_flag = 1;    //      RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode
8987                         }
8988                 }
8989                 preRssi = curRssi;
8990                 odm_Write_RXHP(pDM_Odm);
8991         }
8992 #endif //#if ( DM_ODM_SUPPORT_TYPE & (ODM_MP))
8993 #endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
8994 }
8995
8996 void odm_Write_RXHP(
8997         PDM_ODM_T       pDM_Odm)
8998 {
8999         pRXHP_T         pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
9000         u4Byte          currentIGI;
9001
9002         if (pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)
9003         {
9004                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
9005                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
9006         }
9007
9008         if (pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)
9009 {
9010                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th);  // RegC54[9:8]=2'b11:  AGC Flow 3
9011         }
9012
9013         if (pRX_HP_Table->RXHP_flag == 0)
9014         {
9015                 pRX_HP_Table->Cur_IGI = 0x20;
9016         }
9017         else
9018         {
9019                 currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
9020                 if (currentIGI<0x50)
9021                 {
9022                         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
9023                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
9024                 }
9025         }
9026         pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;
9027         pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;
9028
9029 }
9030
9031 void
9032 odm_PSD_RXHP(
9033         PDM_ODM_T       pDM_Odm
9034 )
9035 {
9036         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
9037         PADAPTER                Adapter =  pDM_Odm->Adapter;
9038         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
9039         unsigned int            pts, start_point, stop_point, initial_gain ;
9040         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
9041         static u1Byte           psd_cnt=0;
9042         static u4Byte           PSD_report[80], PSD_report_tmp;
9043         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
9044         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
9045                                         0,3,6,10,13,16,19,22,26,29};
9046         u1Byte                  n, i, channel, BBReset,tone_idx;
9047         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
9048         s4Byte                          PSD_skip_start, PSD_skip_stop;
9049         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
9050         u4Byte                  ReScan, Interval, Is40MHz;
9051         u8Byte                  curTxOkCnt, curRxOkCnt;
9052         //--------------2G band synthesizer for 92D switch RF channel using-----------------
9053         u1Byte                  group_idx=0;
9054         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;
9055         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel
9056         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}
9057                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14
9058                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8
9059        //--------------------- Add by Gary for Debug setting ----------------------
9060        s4Byte                 psd_result = 0;
9061         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);
9062        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);
9063        //---------------------------------------------------------------------
9064
9065         if (pMgntInfo->bScanInProgress)
9066         {
9067                 return;
9068         }
9069
9070         ReScan = PSD_RESCAN;
9071         Interval = SCAN_INTERVAL;
9072
9073
9074         //1 Initialization
9075         if (init_memory == 0)
9076         {
9077                 RT_TRACE(       COMP_PSD, DBG_LOUD,("Init memory\n"));
9078                 for (i = 0; i < 80; i++)
9079                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
9080                 init_memory = 1;
9081         }
9082         if (psd_cnt == 0)
9083         {
9084                 RT_TRACE(COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
9085                 for (i = 0; i < 80; i++)
9086                         PSD_report[i] = 0;
9087         }
9088
9089         //1 Backup Current Settings
9090         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
9091         if (pDM_Odm->SupportICType == ODM_RTL8192D)
9092         {
9093                 //2 Record Current synthesizer parameters based on current channel
9094                 if ((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
9095                 {
9096                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord);
9097                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord);
9098                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord);
9099                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord);
9100                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord);
9101         }
9102                 else     // DualMAC_DualPHY 2G
9103                 {
9104                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord);
9105                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord);
9106                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord);
9107                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord);
9108                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord);
9109                 }
9110         }
9111         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
9112         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
9113         Is40MHz = *(pDM_Odm->pBandWidth);
9114         ODM_RT_TRACE(pDM_Odm,   COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
9115         //1 Turn off CCK
9116         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
9117         //1 Turn off TX
9118         //Pause TX Queue
9119         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);
9120         //Force RX to stop TX immediately
9121         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
9122         //1 Turn off RX
9123         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
9124         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
9125         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
9126         //Turn off CCA
9127         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
9128         //BB Reset
9129         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
9130         ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
9131         ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
9132         //1 Leave RX idle low power
9133         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
9134         //1 Fix initial gain
9135         RSSI_BT = RSSI_BT_new;
9136         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
9137
9138         if (rssi_ctrl == 1)        // just for debug!!
9139                 initial_gain_psd = RSSI_BT_new;
9140         else
9141                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
9142
9143         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
9144
9145         initialGainUpper = 0x54;
9146
9147         RSSI_BT = initial_gain_psd;
9148         //SSBT = RSSI_BT;
9149
9150         //RT_TRACE(     COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
9151         RT_TRACE(       COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
9152
9153         pDM_Odm->bDMInitialGainEnable = false;
9154         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;
9155         ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd);
9156         //1 Turn off 3-wire
9157         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
9158
9159         //pts value = 128, 256, 512, 1024
9160         pts = 128;
9161
9162         if (pts == 128)
9163         {
9164                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
9165                 start_point = 64;
9166                 stop_point = 192;
9167         }
9168         else if (pts == 256)
9169         {
9170                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
9171                 start_point = 128;
9172                 stop_point = 384;
9173         }
9174         else if (pts == 512)
9175         {
9176                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
9177                 start_point = 256;
9178                 stop_point = 768;
9179         }
9180         else
9181         {
9182                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
9183                 start_point = 512;
9184                 stop_point = 1536;
9185         }
9186
9187
9188 //3 Skip WLAN channels if WLAN busy
9189         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
9190         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
9191         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
9192         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
9193
9194         PSD_skip_start=80;
9195         PSD_skip_stop = 0;
9196         wlan_channel = CurrentChannel & 0x0f;
9197
9198         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d\n", wlan_channel, Is40MHz));
9199
9200         if ((curRxOkCnt+curTxOkCnt) > 1000)
9201         {
9202                 PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
9203                 PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
9204         }
9205
9206         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d\n", PSD_skip_start, PSD_skip_stop));
9207
9208         for (n=0;n<80;n++)
9209         {
9210                 if ((n%20)==0)
9211                 {
9212                         channel = (n/20)*4 + 1;
9213                         if (pDM_Odm->SupportICType == ODM_RTL8192D)
9214                         {
9215                                 switch (channel)
9216                                 {
9217                                         case 1:
9218                                         case 9:
9219                                                 group_idx = 0;
9220                                                 break;
9221                                         case 5:
9222                                                 group_idx = 2;
9223                                                 break;
9224                                         case 13:
9225                                                 group_idx = 1;
9226                                                 break;
9227                                 }
9228                                 if ((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
9229                 {
9230                                         for (i = 0; i < SYN_Length; i++)
9231                                                 ODM_SetRFReg(pDM_Odm, RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
9232
9233                                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
9234                                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, 0x3FF, channel);
9235                                 }
9236                                 else  // DualMAC_DualPHY 2G
9237                         {
9238                                         for (i = 0; i < SYN_Length; i++)
9239                                                 ODM_SetRFReg(pDM_Odm, RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
9240
9241                                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
9242                                 }
9243                         }
9244                         else
9245                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
9246                         }
9247                 tone_idx = n%20;
9248                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
9249                 {
9250                         PSD_report[n] = initial_gain_psd;//SSBT;
9251                         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped\n", n));
9252                 }
9253                 else
9254                 {
9255                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
9256
9257                         if ( PSD_report_tmp > PSD_report[n])
9258                                 PSD_report[n] = PSD_report_tmp;
9259
9260                 }
9261         }
9262
9263         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
9264
9265        //----end
9266         //1 Turn on RX
9267         //Rx AGC on
9268         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
9269         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
9270         //CCK on
9271         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
9272         //1 Turn on TX
9273         //Resume TX Queue
9274         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
9275         //Turn on 3-wire
9276         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
9277         //1 Restore Current Settings
9278         //Resume DIG
9279         pDM_Odm->bDMInitialGainEnable= true;
9280         ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);
9281         // restore originl center frequency
9282         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
9283         if (pDM_Odm->SupportICType == ODM_RTL8192D)
9284         {
9285                 if ((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
9286                 {
9287                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);
9288                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);
9289                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);
9290                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);
9291                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);
9292                         ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);
9293                 }
9294                 else     // DualMAC_DualPHY
9295                 {
9296                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);
9297                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);
9298                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);
9299                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);
9300                         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);
9301                 }
9302         }
9303         //Turn on CCA
9304         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
9305         //Restore RX idle low power
9306         if (RxIdleLowPwr == true)
9307                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
9308
9309         psd_cnt++;
9310         //gPrint("psd cnt=%d\n", psd_cnt);
9311         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d\n",psd_cnt));
9312         if (psd_cnt < ReScan)
9313         {
9314                 ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval);  //ms
9315         }
9316         else
9317                         {
9318                 psd_cnt = 0;
9319                 for (i=0;i<80;i++)
9320                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d\n", 2402+i, PSD_report[i]));
9321                         //DbgPrint("psd_report[%d]=     %d\n", 2402+i, PSD_report[i]);
9322
9323                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
9324
9325                         }
9326                 }
9327
9328 void
9329 odm_PSD_RXHPCallback(
9330         PRT_TIMER               pTimer
9331 )
9332 {
9333         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
9334         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
9335         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
9336         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
9337
9338 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
9339         #if USE_WORKITEM
9340         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
9341         #else
9342         odm_PSD_RXHP(pDM_Odm);
9343         #endif
9344 #else
9345         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
9346 #endif
9347
9348         }
9349
9350 void
9351 odm_PSD_RXHPWorkitemCallback(
9352     void *            pContext
9353     )
9354 {
9355         PADAPTER        pAdapter = (PADAPTER)pContext;
9356         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
9357         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
9358
9359         odm_PSD_RXHP(pDM_Odm);
9360 }
9361
9362 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
9363
9364 //
9365 // 2011/09/22 MH Add for 92D global spin lock utilization.
9366 //
9367 void
9368 odm_GlobalAdapterCheck(
9369                 void
9370         )
9371 {
9372
9373 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
9374
9375         //sherry delete flag 20110517
9376 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
9377                         ACQUIRE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList);
9378 #else
9379                         ACQUIRE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList);
9380 #endif
9381
9382 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
9383                         RELEASE_GLOBAL_SPINLOCK(&GlobalSpinlockForGlobalAdapterList);
9384 #else
9385                         RELEASE_GLOBAL_MUTEX(GlobalMutexForGlobalAdapterList);
9386 #endif
9387
9388 #endif
9389
9390 }       // odm_GlobalAdapterCheck
9391
9392
9393
9394 //
9395 // 2011/12/02 MH Copy from MP oursrc for temporarily test.
9396 //
9397 #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
9398 void
9399 odm_OFDMTXPathDiversity_92C(
9400         PADAPTER        Adapter)
9401 {
9402 //      HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
9403         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
9404         PRT_WLAN_STA    pEntry;
9405         u1Byte  i, DefaultRespPath = 0;
9406         s4Byte  MinRSSI = 0xFF;
9407         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
9408         pDM_PDTable->OFDMTXPath = 0;
9409
9410         //1 Default Port
9411         if (pMgntInfo->mAssoc)
9412         {
9413                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n",
9414                         Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1]));
9415                 if (Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1])
9416                 {
9417                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0);
9418                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[1];
9419                         DefaultRespPath = 0;
9420                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n"));
9421                 }
9422                 else
9423                 {
9424                         pDM_PDTable->OFDMTXPath =  pDM_PDTable->OFDMTXPath | BIT0;
9425                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[0];
9426                         DefaultRespPath = 1;
9427                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n"));
9428                 }
9429                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath));
9430         }
9431         //1 Extension Port
9432         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
9433         {
9434                 if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
9435                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
9436                 else
9437                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
9438
9439                 if (pEntry!=NULL)
9440                 {
9441                         if (pEntry->bAssociated)
9442                         {
9443                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n",
9444                                         pEntry->AID+1, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1]));
9445
9446                                 if (pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1])
9447                                 {
9448                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AID+1));
9449                                         //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AID+1));
9450                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AID+1));
9451                                         if (pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI)
9452                                         {
9453                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1];
9454                                                 DefaultRespPath = 0;
9455                                         }
9456                                 }
9457                                 else
9458                                 {
9459                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AID+1);
9460                                         //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AID+1));
9461                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AID+1));
9462                                         if (pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI)
9463                                         {
9464                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0];
9465                                                 DefaultRespPath = 1;
9466                                         }
9467                                 }
9468                         }
9469                 }
9470                 else
9471                 {
9472                         break;
9473                 }
9474         }
9475
9476         pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath;
9477 }
9478
9479
9480 bool
9481 odm_IsConnected_92C(
9482         PADAPTER        Adapter
9483 )
9484 {
9485         PRT_WLAN_STA    pEntry;
9486         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
9487         u4Byte          i;
9488         bool            bConnected=false;
9489
9490         if (pMgntInfo->mAssoc)
9491         {
9492                 bConnected = true;
9493         }
9494         else
9495         {
9496                 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
9497                 {
9498                         if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
9499                                 pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
9500                         else
9501                                 pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
9502
9503                         if (pEntry!=NULL)
9504                         {
9505                                 if (pEntry->bAssociated)
9506                                 {
9507                                         bConnected = true;
9508                                         break;
9509                                 }
9510                         }
9511                         else
9512                         {
9513                                 break;
9514                         }
9515                 }
9516         }
9517         return  bConnected;
9518 }
9519
9520
9521 void
9522 odm_ResetPathDiversity_92C(
9523                 PADAPTER        Adapter
9524 )
9525 {
9526         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
9527         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
9528         PRT_WLAN_STA    pEntry;
9529         u4Byte  i;
9530
9531         pHalData->RSSI_test = false;
9532         pDM_PDTable->CCK_Pkt_Cnt = 0;
9533         pDM_PDTable->OFDM_Pkt_Cnt = 0;
9534         pHalData->CCK_Pkt_Cnt =0;
9535         pHalData->OFDM_Pkt_Cnt =0;
9536
9537         if (pDM_PDTable->CCKPathDivEnable == true)
9538                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); //RX path = PathAB
9539
9540         for (i=0; i<2; i++)
9541         {
9542                 pDM_PDTable->RSSI_CCK_Path_cnt[i]=0;
9543                 pDM_PDTable->RSSI_CCK_Path[i] = 0;
9544         }
9545         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
9546         {
9547                 if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
9548                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
9549                 else
9550                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
9551
9552                 if (pEntry!=NULL)
9553                 {
9554                         pEntry->rssi_stat.CCK_Pkt_Cnt = 0;
9555                         pEntry->rssi_stat.OFDM_Pkt_Cnt = 0;
9556                         for (i=0; i<2; i++)
9557                         {
9558                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] = 0;
9559                                 pEntry->rssi_stat.RSSI_CCK_Path[i] = 0;
9560                         }
9561                 }
9562                 else
9563                         break;
9564         }
9565 }
9566
9567
9568 void
9569 odm_CCKTXPathDiversity_92C(
9570         PADAPTER        Adapter
9571 )
9572 {
9573         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
9574         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
9575         PRT_WLAN_STA    pEntry;
9576         s4Byte  MinRSSI = 0xFF;
9577         u1Byte  i, DefaultRespPath = 0;
9578 //      bool    bBModePathDiv = false;
9579         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
9580
9581         //1 Default Port
9582         if (pMgntInfo->mAssoc)
9583         {
9584                 if (pHalData->OFDM_Pkt_Cnt == 0)
9585                 {
9586                         for (i=0; i<2; i++)
9587                         {
9588                                 if (pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded
9589                                         pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1);
9590                                 else
9591                                         pDM_PDTable->RSSI_CCK_Path[i] = 0;
9592                         }
9593                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n",
9594                                 pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1]));
9595                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n",
9596                                 pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1]));
9597
9598                         if (pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1])
9599                         {
9600                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
9601                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
9602                                 DefaultRespPath = 0;
9603                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
9604                         }
9605                         else if (pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1])
9606                         {
9607                                 pDM_PDTable->CCKTXPath =  pDM_PDTable->CCKTXPath | BIT0;
9608                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[0];
9609                                 DefaultRespPath = 1;
9610                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n"));
9611                         }
9612                         else
9613                         {
9614                                 if ((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI))
9615                                 {
9616                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
9617                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
9618                                         MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
9619                                         DefaultRespPath = 0;
9620                                 }
9621                                 else
9622                                 {
9623                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n"));
9624                                 }
9625                         }
9626                 }
9627                 else //Follow OFDM decision
9628                 {
9629                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0);
9630                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n",
9631                                 pDM_PDTable->CCKTXPath &BIT0));
9632                 }
9633         }
9634         //1 Extension Port
9635         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
9636         {
9637                 if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
9638                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
9639                 else
9640                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
9641
9642                 if (pEntry!=NULL)
9643                 {
9644                         if (pEntry->bAssociated)
9645                         {
9646                                 if (pEntry->rssi_stat.OFDM_Pkt_Cnt == 0)
9647                                 {
9648                                         for (i=0; i<2; i++)
9649                                         {
9650                                                 if (pEntry->rssi_stat.RSSI_CCK_Path_cnt[i] > 1)
9651                                                         pEntry->rssi_stat.RSSI_CCK_Path[i] = pEntry->rssi_stat.RSSI_CCK_Path[i] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[i]-1);
9652                                                 else
9653                                                         pEntry->rssi_stat.RSSI_CCK_Path[i] = 0;
9654                                         }
9655                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n",
9656                                                 pEntry->AID+1, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1]));
9657
9658                                         if (pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1])
9659                                         {
9660                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1));
9661                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1));
9662                                                 if (pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI)
9663                                                 {
9664                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
9665                                                         DefaultRespPath = 0;
9666                                                 }
9667                                         }
9668                                         else if (pEntry->rssi_stat.RSSI_CCK_Path[0] <pEntry->rssi_stat.RSSI_CCK_Path[1])
9669                                         {
9670                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AID+1);
9671                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AID+1));
9672                                                 if (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)
9673                                                 {
9674                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0];
9675                                                         DefaultRespPath = 1;
9676                                                 }
9677                                         }
9678                                         else
9679                                         {
9680                                                 if ((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI))
9681                                                 {
9682                                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AID+1));
9683                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
9684                                                         DefaultRespPath = 0;
9685                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AID+1));
9686                                                 }
9687                                                 else
9688                                                 {
9689                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AID+1));
9690                                                 }
9691                                         }
9692                                 }
9693                                 else //Follow OFDM decision
9694                                 {
9695                                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AID+1)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AID+1));
9696                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n",
9697                                                 pEntry->AID+1, (pDM_PDTable->CCKTXPath & BIT(pEntry->AID+1))>>(pEntry->AID+1)));
9698                                 }
9699                         }
9700                 }
9701                 else
9702                 {
9703                         break;
9704                 }
9705         }
9706
9707         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI));
9708
9709         if (MinRSSI == 0xFF)
9710                 DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
9711
9712         pDM_PDTable->CCKDefaultRespPath = DefaultRespPath;
9713 }
9714
9715
9716
9717 void
9718 odm_PathDiversityAfterLink_92C(
9719         PADAPTER        Adapter
9720 )
9721 {
9722         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
9723         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
9724         pPD_T           pDM_PDTable = &Adapter->DM_PDTable;
9725         u1Byte          DefaultRespPath=0;
9726
9727         if ((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff))
9728         {
9729                 if (pHalData->PathDivCfg == 0)
9730                 {
9731                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("No ODM_TXPathDiversity()\n"));
9732                 }
9733                 else
9734                 {
9735                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("2T ODM_TXPathDiversity()\n"));
9736                 }
9737                 return;
9738         }
9739         if (!odm_IsConnected_92C(Adapter))
9740         {
9741                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n"));
9742                 return;
9743         }
9744
9745
9746         if (pDM_PDTable->TrainingState == 0)
9747         {
9748                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n"));
9749                 odm_OFDMTXPathDiversity_92C(Adapter);
9750
9751                 if ((pDM_PDTable->CCKPathDivEnable == true) && (pDM_PDTable->OFDM_Pkt_Cnt < 100))
9752                 {
9753                         //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n"));
9754
9755                         if (pDM_PDTable->CCK_Pkt_Cnt > 300)
9756                                 pDM_PDTable->Timer = 20;
9757                         else if (pDM_PDTable->CCK_Pkt_Cnt > 100)
9758                                 pDM_PDTable->Timer = 60;
9759                         else
9760                                 pDM_PDTable->Timer = 250;
9761                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer));
9762
9763                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // RX path = PathA
9764                         pDM_PDTable->TrainingState = 1;
9765                         pHalData->RSSI_test = true;
9766                         ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
9767                 }
9768                 else
9769                 {
9770                         pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath;
9771                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
9772                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n"));
9773                         odm_SetRespPath_92C(Adapter, DefaultRespPath);
9774                         odm_ResetPathDiversity_92C(Adapter);
9775                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
9776                 }
9777         }
9778         else if (pDM_PDTable->TrainingState == 1)
9779         {
9780                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n"));
9781                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // RX path = PathB
9782                 pDM_PDTable->TrainingState = 2;
9783                 ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
9784         }
9785         else
9786         {
9787                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n"));
9788                 pDM_PDTable->TrainingState = 0;
9789                 odm_CCKTXPathDiversity_92C(Adapter);
9790                 if (pDM_PDTable->OFDM_Pkt_Cnt != 0)
9791                 {
9792                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
9793                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n"));
9794                 }
9795                 else
9796                 {
9797                         DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
9798                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n"));
9799                 }
9800                 odm_SetRespPath_92C(Adapter, DefaultRespPath);
9801                 odm_ResetPathDiversity_92C(Adapter);
9802                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
9803         }
9804
9805 }
9806
9807
9808
9809 void
9810 odm_CCKTXPathDiversityCallback(
9811         PRT_TIMER               pTimer
9812 )
9813 {
9814 #if USE_WORKITEM
9815        PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
9816        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
9817            PDM_ODM_T            pDM_Odm = &pHalData->DM_OutSrc;
9818 #else
9819         PADAPTER        Adapter = (PADAPTER)pTimer->Adapter;
9820 #endif
9821
9822 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
9823 #if USE_WORKITEM
9824         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
9825 #else
9826         odm_PathDiversityAfterLink_92C(Adapter);
9827 #endif
9828 #else
9829         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
9830 #endif
9831
9832 }
9833
9834
9835 void
9836 odm_CCKTXPathDiversityWorkItemCallback(
9837     void *            pContext
9838     )
9839 {
9840         PADAPTER        Adapter = (PADAPTER)pContext;
9841
9842         odm_CCKTXPathDiversity_92C(Adapter);
9843 }
9844
9845
9846 void
9847 ODM_CCKPathDiversityChkPerPktRssi(
9848         PADAPTER                Adapter,
9849         bool                    bIsDefPort,
9850         bool                    bMatchBSSID,
9851         PRT_WLAN_STA    pEntry,
9852         PRT_RFD                 pRfd,
9853         pu1Byte                 pDesc
9854         )
9855 {
9856         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
9857         bool                    bCount = false;
9858         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
9859         //bool  isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc);
9860 #if DEV_BUS_TYPE != RT_SDIO_INTERFACE
9861         bool    isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc);
9862 #else  //below code would be removed if we have verified SDIO
9863         bool    isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc);
9864 #endif
9865
9866         if ((pHalData->PathDivCfg != 1) || (pHalData->RSSI_test == false))
9867                 return;
9868
9869         if (pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
9870                 bCount = true;
9871         else if (pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
9872                 bCount = true;
9873
9874         if (bCount && isCCKrate)
9875         {
9876                 if (pDM_PDTable->TrainingState == 1 )
9877                 {
9878                         if (pEntry)
9879                         {
9880                                 if (pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0)
9881                                         pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
9882                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++;
9883                         }
9884                         else
9885                         {
9886                                 if (pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0)
9887                                         pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
9888                                 pDM_PDTable->RSSI_CCK_Path_cnt[0]++;
9889                         }
9890                 }
9891                 else if (pDM_PDTable->TrainingState == 2 )
9892                 {
9893                         if (pEntry)
9894                         {
9895                                 if (pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0)
9896                                         pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
9897                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++;
9898                         }
9899                         else
9900                         {
9901                                 if (pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0)
9902                                         pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
9903                                 pDM_PDTable->RSSI_CCK_Path_cnt[1]++;
9904                         }
9905                 }
9906         }
9907 }
9908
9909
9910 bool
9911 ODM_PathDiversityBeforeLink92C(
9912         //PADAPTER      Adapter
9913                 PDM_ODM_T               pDM_Odm
9914         )
9915 {
9916 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
9917         PADAPTER                Adapter = pDM_Odm->Adapter;
9918         HAL_DATA_TYPE*  pHalData = NULL;
9919         PMGNT_INFO              pMgntInfo = NULL;
9920         //pSWAT_T               pDM_SWAT_Table = &Adapter->DM_SWAT_Table;
9921         pPD_T                   pDM_PDTable = NULL;
9922
9923         s1Byte                  Score = 0;
9924         PRT_WLAN_BSS    pTmpBssDesc;
9925         PRT_WLAN_BSS    pTestBssDesc;
9926
9927         u1Byte                  target_chnl = 0;
9928         u1Byte                  index;
9929
9930         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
9931         {       // The ODM structure is not initialized.
9932                 return false;
9933         }
9934         pHalData = GET_HAL_DATA(Adapter);
9935         pMgntInfo = &Adapter->MgntInfo;
9936         pDM_PDTable = &Adapter->DM_PDTable;
9937
9938         // Condition that does not need to use path diversity.
9939         if ((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest )
9940         {
9941                 RT_TRACE(COMP_SWAS, DBG_LOUD,
9942                                 ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n"));
9943                 return false;
9944         }
9945
9946         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
9947         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
9948         if (pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
9949         {
9950                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
9951
9952                 RT_TRACE(COMP_SWAS, DBG_LOUD,
9953                                 ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
9954                                 pMgntInfo->RFChangeInProgress,
9955                                 pHalData->eRFPowerState));
9956
9957                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
9958                 pDM_PDTable->PathDiv_NoLink_State = 0;
9959
9960                 return false;
9961         }
9962         else
9963         {
9964                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
9965         }
9966
9967         //1 Run AntDiv mechanism "Before Link" part.
9968         //if (pDM_SWAT_Table->SWAS_NoLink_State == 0)
9969         if (pDM_PDTable->PathDiv_NoLink_State == 0)
9970         {
9971                 //1 Prepare to do Scan again to check current antenna state.
9972
9973                 // Set check state to next step.
9974                 //pDM_SWAT_Table->SWAS_NoLink_State = 1;
9975                 pDM_PDTable->PathDiv_NoLink_State = 1;
9976
9977                 // Copy Current Scan list.
9978                 Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc;
9979                 PlatformMoveMemory((void *)Adapter->MgntInfo.tmpbssDesc, (void *)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
9980
9981                 // Switch Antenna to another one.
9982                 if (pDM_PDTable->DefaultRespPath == 0)
9983                 {
9984                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // TRX path = PathB
9985                         odm_SetRespPath_92C(Adapter, 1);
9986                         pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
9987                         pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
9988                 }
9989                 else
9990                 {
9991                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // TRX path = PathA
9992                         odm_SetRespPath_92C(Adapter, 0);
9993                         pDM_PDTable->OFDMTXPath = 0x0;
9994                         pDM_PDTable->CCKTXPath = 0x0;
9995                 }
9996
9997                 // Go back to scan function again.
9998                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
9999                 pMgntInfo->ScanStep=0;
10000                 target_chnl = odm_SwAntDivSelectChkChnl(Adapter);
10001                 odm_SwAntDivConsructChkScanChnl(Adapter, target_chnl);
10002                 HTReleaseChnlOpLock(Adapter);
10003                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
10004
10005                 return true;
10006         }
10007         else
10008         {
10009                 //1 ScanComple() is called after antenna swiched.
10010                 //1 Check scan result and determine which antenna is going
10011                 //1 to be used.
10012
10013                 for (index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
10014                 {
10015                         pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]);
10016                         pTestBssDesc = &(pMgntInfo->bssDesc[index]);
10017
10018                         if (PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
10019                         {
10020                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n"));
10021                                 continue;
10022                         }
10023
10024                         if (pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
10025                         {
10026                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n"));
10027                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
10028                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
10029
10030                                 Score++;
10031                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
10032                         }
10033                         else if (pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
10034                         {
10035                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n"));
10036                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
10037                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
10038                                 Score--;
10039                         }
10040
10041                 }
10042
10043                 if (pMgntInfo->NumBssDesc!=0 && Score<=0)
10044                 {
10045                         RT_TRACE(COMP_SWAS, DBG_LOUD,
10046                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
10047
10048                         //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
10049                 }
10050                 else
10051                 {
10052                         RT_TRACE(COMP_SWAS, DBG_LOUD,
10053                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
10054
10055                         if (pDM_PDTable->DefaultRespPath == 0)
10056                         {
10057                                 pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
10058                                 pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
10059                                 odm_SetRespPath_92C(Adapter, 1);
10060                         }
10061                         else
10062                         {
10063                                 pDM_PDTable->OFDMTXPath = 0x0;
10064                                 pDM_PDTable->CCKTXPath = 0x0;
10065                                 odm_SetRespPath_92C(Adapter, 0);
10066                         }
10067                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); // RX path = PathAB
10068
10069                         //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
10070
10071                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
10072                         //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
10073                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
10074                 }
10075
10076                 // Check state reset to default and wait for next time.
10077                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
10078                 pDM_PDTable->PathDiv_NoLink_State = 0;
10079
10080                 return false;
10081         }
10082 #else
10083                 return  false;
10084 #endif
10085
10086 }
10087
10088
10089 //Neil Chen---2011--06--22
10090 //----92D Path Diversity----//
10091 //#ifdef PathDiv92D
10092 //==================================
10093 //3 Path Diversity
10094 //==================================
10095 //
10096 // 20100514 Luke/Joseph:
10097 // Add new function for antenna diversity after link.
10098 // This is the main function of antenna diversity after link.
10099 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
10100 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
10101 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
10102 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
10103 // listened on the air with the RSSI of original antenna.
10104 // It chooses the antenna with better RSSI.
10105 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
10106 // penalty to get next try.
10107 //
10108 //
10109 // 20100503 Joseph:
10110 // Add new function SwAntDivCheck8192C().
10111 // This is the main function of Antenna diversity function before link.
10112 // Mainly, it just retains last scan result and scan again.
10113 // After that, it compares the scan result to see which one gets better RSSI.
10114 // It selects antenna with better receiving power and returns better scan result.
10115 //
10116
10117
10118 //
10119 // 20100514 Luke/Joseph:
10120 // This function is used to gather the RSSI information for antenna testing.
10121 // It selects the RSSI of the peer STA that we want to know.
10122 //
10123 void
10124 ODM_PathDivChkPerPktRssi(
10125         PADAPTER                Adapter,
10126         bool                    bIsDefPort,
10127         bool                    bMatchBSSID,
10128         PRT_WLAN_STA    pEntry,
10129         PRT_RFD                 pRfd
10130         )
10131 {
10132         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10133         bool                    bCount = false;
10134         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
10135         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
10136
10137         if (pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
10138                 bCount = true;
10139         else if (pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
10140                 bCount = true;
10141
10142         if (bCount)
10143         {
10144                 //1 RSSI for SW Antenna Switch
10145                 if (pDM_SWAT_Table->CurAntenna == Antenna_A)
10146                 {
10147                         pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll;
10148                         pHalData->RSSI_cnt_A++;
10149                 }
10150                 else
10151                 {
10152                         pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll;
10153                         pHalData->RSSI_cnt_B++;
10154
10155                 }
10156         }
10157 }
10158
10159
10160
10161 //
10162 // 20100514 Luke/Joseph:
10163 // Add new function to reset antenna diversity state after link.
10164 //
10165 void
10166 ODM_PathDivRestAfterLink(
10167         PDM_ODM_T               pDM_Odm
10168         )
10169 {
10170         PADAPTER                Adapter=pDM_Odm->Adapter;
10171         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10172         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
10173
10174         pHalData->RSSI_cnt_A = 0;
10175         pHalData->RSSI_cnt_B = 0;
10176         pHalData->RSSI_test = false;
10177         pDM_SWAT_Table->try_flag = 0x0;       // NOT 0xff
10178         pDM_SWAT_Table->RSSI_Trying = 0;
10179         pDM_SWAT_Table->SelectAntennaMap=0xAA;
10180         pDM_SWAT_Table->CurAntenna = Antenna_A;
10181 }
10182
10183
10184 //
10185 // 20100514 Luke/Joseph:
10186 // Callback function for 500ms antenna test trying.
10187 //
10188 void
10189 odm_PathDivChkAntSwitchCallback(
10190         PRT_TIMER               pTimer
10191 )
10192 {
10193         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
10194         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10195         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
10196
10197 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10198
10199 #if USE_WORKITEM
10200         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
10201 #else
10202         odm_PathDivChkAntSwitch(pDM_Odm);
10203 #endif
10204 #else
10205         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
10206 #endif
10207
10208 //odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE);
10209
10210 }
10211
10212
10213 void odm_PathDivChkAntSwitchWorkitemCallback(void *pContext)
10214 {
10215         PADAPTER        pAdapter = (PADAPTER)pContext;
10216         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
10217         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
10218
10219         odm_PathDivChkAntSwitch(pDM_Odm);
10220 }
10221
10222
10223  //MAC0_ACCESS_PHY1
10224
10225 // 2011-06-22 Neil Chen & Gary Hsin
10226 // Refer to Jr.Luke's SW ANT DIV
10227 // 92D Path Diversity Main function
10228 // refer to 88C software antenna diversity
10229 //
10230 void
10231 odm_PathDivChkAntSwitch(
10232         PDM_ODM_T               pDM_Odm
10233         //PADAPTER              Adapter,
10234         //u1Byte                        Step
10235 )
10236 {
10237         PADAPTER                Adapter = pDM_Odm->Adapter;
10238         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10239         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
10240
10241
10242         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
10243         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
10244         u1Byte                  nextAntenna=Antenna_B;
10245         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
10246         u8Byte                  curTxOkCnt, curRxOkCnt;
10247         static u8Byte           TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
10248         u8Byte                  CurByteCnt=0, PreByteCnt=0;
10249         static u1Byte           TrafficLoad = TRAFFIC_LOW;
10250         u1Byte                  Score_A=0, Score_B=0;
10251         u1Byte                  i=0x0;
10252        // Neil Chen
10253        static u1Byte        pathdiv_para=0x0;
10254        static u1Byte        switchfirsttime=0x00;
10255         // u1Byte                 regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27);
10256         u1Byte                  regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27);
10257
10258
10259        //u1Byte                 reg637 =0x0;
10260        static u1Byte        fw_value=0x0;
10261         u1Byte                 n=0;
10262        static u8Byte            lastTxOkCnt_tmp=0, lastRxOkCnt_tmp=0;
10263         //u8Byte                        curTxOkCnt_tmp, curRxOkCnt_tmp;
10264        PADAPTER            BuddyAdapter = Adapter->BuddyAdapter;     // another adapter MAC
10265         // Path Diversity   //Neil Chen--2011--06--22
10266
10267         //u1Byte                 PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31);
10268         u1Byte                 PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31);
10269         u1Byte                 PathDiv_Enable = pHalData->bPathDiv_Enable;
10270
10271
10272         //DbgPrint("Path Div PG Value:%x\n",PathDiv_Enable);
10273        if ((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType92D == BAND_ON_2_4G))
10274        {
10275            return;
10276        }
10277         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n"));
10278
10279        // The first time to switch path excluding 2nd, 3rd, ....etc....
10280         if (switchfirsttime==0)
10281         {
10282             if (regB33==0)
10283             {
10284                pDM_SWAT_Table->CurAntenna = Antenna_A;    // Default MAC0_5G-->Path A (current antenna)
10285             }
10286         }
10287
10288         // Condition that does not need to use antenna diversity.
10289         if (pDM_Odm->SupportICType != ODM_RTL8192D)
10290         {
10291                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n"));
10292                 return;
10293         }
10294
10295         // Radio off: Status reset to default and return.
10296         if (pHalData->eRFPowerState==eRfOff)
10297         {
10298                 //ODM_SwAntDivRestAfterLink(Adapter);
10299                 return;
10300         }
10301
10302        /*
10303         // Handling step mismatch condition.
10304         // Peak step is not finished at last time. Recover the variable and check again.
10305         if (    Step != pDM_SWAT_Table->try_flag        )
10306         {
10307                 ODM_SwAntDivRestAfterLink(Adapter);
10308         } */
10309
10310         if (pDM_SWAT_Table->try_flag == 0xff)
10311         {
10312                 // Select RSSI checking target
10313                 if (pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
10314                 {
10315                         // Target: Infrastructure mode AP.
10316                         pHalData->RSSI_target = NULL;
10317                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n"));
10318                 }
10319                 else
10320                 {
10321                         u1Byte                  index = 0;
10322                         PRT_WLAN_STA    pEntry = NULL;
10323                         PADAPTER                pTargetAdapter = NULL;
10324
10325                         if (    pMgntInfo->mIbss || ACTING_AS_AP(Adapter) )
10326                         {
10327                                 // Target: AP/IBSS peer.
10328                                 pTargetAdapter = Adapter;
10329                         }
10330                         else if (IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
10331                         {
10332                                 // Target: VWIFI peer.
10333                                 pTargetAdapter = GetFirstExtAdapter(Adapter);
10334                         }
10335
10336                         if (pTargetAdapter != NULL)
10337                         {
10338                                 for (index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
10339                                 {
10340                                         pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
10341                                         if (pEntry != NULL)
10342                                         {
10343                                                 if (pEntry->bAssociated)
10344                                                         break;
10345                                         }
10346                                 }
10347                         }
10348
10349                         if (pEntry == NULL)
10350                         {
10351                                 ODM_PathDivRestAfterLink(pDM_Odm);
10352                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
10353                                 return;
10354                         }
10355                         else
10356                         {
10357                                 pHalData->RSSI_target = pEntry;
10358                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
10359                         }
10360                 }
10361
10362                 pHalData->RSSI_cnt_A = 0;
10363                 pHalData->RSSI_cnt_B = 0;
10364                 pDM_SWAT_Table->try_flag = 0;
10365                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
10366                 return;
10367         }
10368         else
10369         {
10370                // 1st step
10371                 curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
10372                 curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
10373                 lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
10374                 lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
10375
10376                 if (pDM_SWAT_Table->try_flag == 1)   // Training State
10377                 {
10378                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
10379                         {
10380                                 TXByteCnt_A += curTxOkCnt;
10381                                 RXByteCnt_A += curRxOkCnt;
10382                         }
10383                         else
10384                         {
10385                                 TXByteCnt_B += curTxOkCnt;
10386                                 RXByteCnt_B += curRxOkCnt;
10387                         }
10388
10389                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
10390                         pDM_SWAT_Table->RSSI_Trying--;
10391                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
10392                         if (pDM_SWAT_Table->RSSI_Trying == 0)
10393                         {
10394                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B);
10395                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A);
10396
10397                                 if (TrafficLoad == TRAFFIC_HIGH)
10398                                 {
10399                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
10400                                         PreByteCnt =PreByteCnt*9;
10401                                 }
10402                                 else if (TrafficLoad == TRAFFIC_LOW)
10403                                 {
10404                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
10405                                         PreByteCnt =PreByteCnt*2;
10406                                 }
10407                                 if (pHalData->RSSI_cnt_A > 0)
10408                                         RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
10409                                 else
10410                                         RSSI_A = 0;
10411                                 if (pHalData->RSSI_cnt_B > 0)
10412                                         RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
10413                              else
10414                                         RSSI_B = 0;
10415                                 curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
10416                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A;
10417                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
10418                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s\n",
10419                                 (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
10420                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
10421                                         RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
10422                         }
10423
10424                 }
10425                 else   // try_flag=0
10426                 {
10427
10428                         if (pHalData->RSSI_cnt_A > 0)
10429                                 RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
10430                         else
10431                                 RSSI_A = 0;
10432                         if (pHalData->RSSI_cnt_B > 0)
10433                                 RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
10434                         else
10435                                 RSSI_B = 0;
10436                         curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
10437                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B;
10438                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
10439                        ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s\n",
10440                         (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
10441
10442                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
10443                                 RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
10444                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
10445                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
10446                 }
10447
10448                 //1 Trying State
10449                 if ((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
10450                 {
10451
10452                         if (pDM_SWAT_Table->TestMode == TP_MODE)
10453                         {
10454                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE"));
10455                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt));
10456                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt));
10457                                 if (CurByteCnt < PreByteCnt)
10458                                 {
10459                                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
10460                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
10461                                         else
10462                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
10463                                 }
10464                                 else
10465                                 {
10466                                         if (pDM_SWAT_Table->CurAntenna == Antenna_A)
10467                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
10468                                         else
10469                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
10470                                 }
10471                                 for (i= 0; i<8; i++)
10472                                 {
10473                                         if (((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
10474                                                 Score_A++;
10475                                         else
10476                                                 Score_B++;
10477                                 }
10478                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
10479                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B));
10480
10481                                 if (pDM_SWAT_Table->CurAntenna == Antenna_A)
10482                                 {
10483                                         nextAntenna = (Score_A >= Score_B)?Antenna_A:Antenna_B;
10484                                 }
10485                                 else
10486                                 {
10487                                         nextAntenna = (Score_B >= Score_A)?Antenna_B:Antenna_A;
10488                                 }
10489                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
10490                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s\n",
10491                                 (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
10492
10493                                 if (nextAntenna != pDM_SWAT_Table->CurAntenna)
10494                                 {
10495                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna"));
10496                                 }
10497                                 else
10498                                 {
10499                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n"));
10500                                 }
10501                         }
10502
10503
10504                         if (pDM_SWAT_Table->TestMode == RSSI_MODE)
10505                         {
10506                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE"));
10507                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
10508                                 if (curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
10509                                 {
10510                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Switch back to another antenna"));
10511                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
10512                                 }
10513                                 else // current anntena is good
10514                                 {
10515                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
10516                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: current anntena is good\n"));
10517                                 }
10518                         }
10519
10520                         pDM_SWAT_Table->try_flag = 0;
10521                         pHalData->RSSI_test = false;
10522                         pHalData->RSSI_sum_A = 0;
10523                         pHalData->RSSI_cnt_A = 0;
10524                         pHalData->RSSI_sum_B = 0;
10525                         pHalData->RSSI_cnt_B = 0;
10526                         TXByteCnt_A = 0;
10527                         TXByteCnt_B = 0;
10528                         RXByteCnt_A = 0;
10529                         RXByteCnt_B = 0;
10530
10531                 }
10532
10533                 //1 Normal State
10534                 else if (pDM_SWAT_Table->try_flag == 0)
10535                 {
10536                         if (TrafficLoad == TRAFFIC_HIGH)
10537                         {
10538                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if (PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
10539                                         TrafficLoad = TRAFFIC_HIGH;
10540                                 else
10541                                         TrafficLoad = TRAFFIC_LOW;
10542                         }
10543                         else if (TrafficLoad == TRAFFIC_LOW)
10544                                 {
10545                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if (PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
10546                                         TrafficLoad = TRAFFIC_HIGH;
10547                                 else
10548                                         TrafficLoad = TRAFFIC_LOW;
10549                         }
10550                         if (TrafficLoad == TRAFFIC_HIGH)
10551                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
10552                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
10553
10554                         //Prepare To Try Antenna
10555                                 nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
10556                                 pDM_SWAT_Table->try_flag = 1;
10557                                 pHalData->RSSI_test = true;
10558                         if ((curRxOkCnt+curTxOkCnt) > 1000)
10559                         {
10560 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10561                             pDM_SWAT_Table->RSSI_Trying = 4;
10562 #else
10563                             pDM_SWAT_Table->RSSI_Trying = 2;
10564 #endif
10565                                 pDM_SWAT_Table->TestMode = TP_MODE;
10566                         }
10567                         else
10568                         {
10569                                 pDM_SWAT_Table->RSSI_Trying = 2;
10570                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
10571
10572                         }
10573
10574                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
10575                         pHalData->RSSI_sum_A = 0;
10576                         pHalData->RSSI_cnt_A = 0;
10577                         pHalData->RSSI_sum_B = 0;
10578                         pHalData->RSSI_cnt_B = 0;
10579                 } // end of try_flag=0
10580         }
10581
10582         //1 4.Change TRX antenna
10583         if (nextAntenna != pDM_SWAT_Table->CurAntenna)
10584         {
10585
10586                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n "));
10587                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C
10588                 if (nextAntenna==Antenna_A)
10589                 {
10590                     ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n "));
10591                     pathdiv_para = 0x02;   //02 to switchback to RF path A
10592                     fw_value = 0x03;
10593 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10594                  odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
10595 #else
10596                  ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
10597 #endif
10598                 }
10599                else if (nextAntenna==Antenna_B)
10600                {
10601                    ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n "));
10602                    if (switchfirsttime==0)  // First Time To Enter Path Diversity
10603                    {
10604                        switchfirsttime=0x01;
10605                       pathdiv_para = 0x00;
10606                           fw_value=0x00;    // to backup RF Path A Releated Registers
10607
10608 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10609                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
10610 #else
10611                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
10612                      //for (u1Byte n=0; n<80,n++)
10613                      //{
10614                      //delay_us(500);
10615                           ODM_delay_ms(500);
10616                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
10617
10618                          fw_value=0x01;         // to backup RF Path A Releated Registers
10619                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
10620 #endif
10621                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n "));
10622                    }
10623                     else
10624                     {
10625                         pathdiv_para = 0x01;
10626                          fw_value = 0x02;
10627 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10628                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
10629 #else
10630                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
10631 #endif
10632                     }
10633                }
10634            //   odm_PathDiversity_8192D(Adapter, pathdiv_para);
10635         }
10636
10637         //1 5.Reset Statistics
10638         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
10639         pDM_SWAT_Table->CurAntenna = nextAntenna;
10640         pDM_SWAT_Table->PreRSSI = curRSSI;
10641        //lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
10642        //lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
10643
10644         //1 6.Set next timer
10645
10646         if (pDM_SWAT_Table->RSSI_Trying == 0)
10647                 return;
10648
10649         if (pDM_SWAT_Table->RSSI_Trying%2 == 0)
10650         {
10651                 if (pDM_SWAT_Table->TestMode == TP_MODE)
10652                 {
10653                         if (TrafficLoad == TRAFFIC_HIGH)
10654                         {
10655 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10656                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms
10657                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n"));
10658 #else
10659                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms
10660                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n"));
10661 #endif
10662                         }
10663                         else if (TrafficLoad == TRAFFIC_LOW)
10664                         {
10665                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms
10666                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n"));
10667                         }
10668                 }
10669                 else   // TestMode == RSSI_MODE
10670                 {
10671                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
10672                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n"));
10673                 }
10674         }
10675         else
10676         {
10677                 if (pDM_SWAT_Table->TestMode == TP_MODE)
10678                 {
10679                         if (TrafficLoad == TRAFFIC_HIGH)
10680
10681 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
10682                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms
10683                                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n"));
10684 #else
10685                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms
10686 #endif
10687                         else if (TrafficLoad == TRAFFIC_LOW)
10688                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms
10689                 }
10690                 else
10691                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
10692         }
10693 }
10694
10695 //==================================================
10696 //3 PathDiv End
10697 //==================================================
10698
10699 void
10700 odm_SetRespPath_92C(
10701         PADAPTER        Adapter,
10702         u1Byte  DefaultRespPath
10703         )
10704 {
10705         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
10706
10707         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath));
10708         if (DefaultRespPath != pDM_PDTable->DefaultRespPath)
10709         {
10710                 if (DefaultRespPath == 0)
10711                 {
10712                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15);
10713                 }
10714                 else
10715                 {
10716                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A);
10717                 }
10718         }
10719         pDM_PDTable->DefaultRespPath = DefaultRespPath;
10720 }
10721
10722
10723 void
10724 ODM_FillTXPathInTXDESC(
10725                 PADAPTER        Adapter,
10726                 PRT_TCB         pTcb,
10727                 pu1Byte         pDesc
10728 )
10729 {
10730         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10731         u4Byte  TXPath;
10732         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
10733
10734         //2011.09.05  Add by Luke Lee for path diversity
10735         if (pHalData->PathDivCfg == 1)
10736         {
10737                 TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0;
10738                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath));
10739                 //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath);
10740                 if (TXPath == 0)
10741                 {
10742                         SET_TX_DESC_TX_ANTL_92C(pDesc,1);
10743                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,1);
10744                 }
10745                 else
10746                 {
10747                         SET_TX_DESC_TX_ANTL_92C(pDesc,2);
10748                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,2);
10749                 }
10750                 TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0;
10751                 if (TXPath == 0)
10752                 {
10753                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1);
10754                 }
10755                 else
10756                 {
10757                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2);
10758                 }
10759         }
10760 }
10761
10762 //Only for MP //Neil Chen--2012--0502--
10763 void
10764 odm_PathDivInit(
10765 PDM_ODM_T       pDM_Odm)
10766 {
10767         pPATHDIV_PARA   pathIQK = &pDM_Odm->pathIQK;
10768
10769         pathIQK->org_2g_RegC14=0x0;
10770         pathIQK->org_2g_RegC4C=0x0;
10771         pathIQK->org_2g_RegC80=0x0;
10772         pathIQK->org_2g_RegC94=0x0;
10773         pathIQK->org_2g_RegCA0=0x0;
10774         pathIQK->org_5g_RegC14=0x0;
10775         pathIQK->org_5g_RegCA0=0x0;
10776         pathIQK->org_5g_RegE30=0x0;
10777         pathIQK->swt_2g_RegC14=0x0;
10778         pathIQK->swt_2g_RegC4C=0x0;
10779         pathIQK->swt_2g_RegC80=0x0;
10780         pathIQK->swt_2g_RegC94=0x0;
10781         pathIQK->swt_2g_RegCA0=0x0;
10782         pathIQK->swt_5g_RegC14=0x0;
10783         pathIQK->swt_5g_RegCA0=0x0;
10784         pathIQK->swt_5g_RegE30=0x0;
10785
10786 }
10787 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
10788
10789 #if ((DM_ODM_SUPPORT_TYPE == ODM_MP)||(DM_ODM_SUPPORT_TYPE == ODM_CE))
10790
10791
10792 //
10793 // Description:
10794 //      Set Single/Dual Antenna default setting for products that do not do detection in advance.
10795 //
10796 // Added by Joseph, 2012.03.22
10797 //
10798 void
10799 ODM_SingleDualAntennaDefaultSetting(
10800                 PDM_ODM_T               pDM_Odm
10801         )
10802 {
10803         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
10804         pDM_SWAT_Table->ANTA_ON=true;
10805         pDM_SWAT_Table->ANTB_ON=true;
10806 }
10807
10808
10809 //2 8723A ANT DETECT
10810
10811
10812 void
10813 odm_PHY_SaveAFERegisters(
10814         PDM_ODM_T       pDM_Odm,
10815         pu4Byte         AFEReg,
10816         pu4Byte         AFEBackup,
10817         u4Byte          RegisterNum
10818         )
10819 {
10820         u4Byte  i;
10821
10822         //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
10823         for ( i = 0 ; i < RegisterNum ; i++) {
10824                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
10825         }
10826 }
10827
10828 void
10829 odm_PHY_ReloadAFERegisters(
10830         PDM_ODM_T       pDM_Odm,
10831         pu4Byte         AFEReg,
10832         pu4Byte         AFEBackup,
10833         u4Byte          RegiesterNum
10834         )
10835 {
10836         u4Byte  i;
10837
10838         //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
10839         for (i = 0 ; i < RegiesterNum; i++)
10840         {
10841
10842                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
10843         }
10844 }
10845
10846 //2 8723A ANT DETECT
10847 //
10848 // Description:
10849 //      Implement IQK single tone for RF DPK loopback and BB PSD scanning.
10850 //      This function is cooperated with BB team Neil.
10851 //
10852 // Added by Roger, 2011.12.15
10853 //
10854 bool
10855 ODM_SingleDualAntennaDetection(
10856                 PDM_ODM_T               pDM_Odm,
10857                 u1Byte                  mode
10858         )
10859 {
10860
10861         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
10862         u4Byte          CurrentChannel,RfLoopReg;
10863         u1Byte          n;
10864         u4Byte          Reg88c, Regc08, Reg874, Regc50;
10865         u1Byte          initial_gain = 0x5a;
10866         u4Byte          PSD_report_tmp;
10867         u4Byte          AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
10868         bool            bResult = true;
10869         u4Byte          AFE_Backup[16];
10870         u4Byte          AFE_REG_8723A[16] = {
10871                                         rRx_Wait_CCA,   rTx_CCK_RFON,
10872                                         rTx_CCK_BBON,   rTx_OFDM_RFON,
10873                                         rTx_OFDM_BBON,  rTx_To_Rx,
10874                                         rTx_To_Tx,              rRx_CCK,
10875                                         rRx_OFDM,               rRx_Wait_RIFS,
10876                                         rRx_TO_Rx,              rStandby,
10877                                         rSleep,                 rPMPD_ANAEN,
10878                                         rFPGA0_XCD_SwitchControl, rBlue_Tooth};
10879
10880         if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))
10881                 return bResult;
10882
10883         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
10884                 return bResult;
10885
10886         if (pDM_Odm->SupportICType == ODM_RTL8192C)
10887         {
10888                 //Which path in ADC/DAC is turnned on for PSD: both I/Q
10889                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
10890                 //Ageraged number: 8
10891                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
10892                 //pts = 128;
10893                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
10894         }
10895
10896         //1 Backup Current RF/BB Settings
10897
10898         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
10899         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
10900         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
10901         // Step 1: USE IQK to transmitter single tone
10902
10903         ODM_StallExecution(10);
10904
10905         //Store A Path Register 88c, c08, 874, c50
10906         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
10907         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
10908         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
10909         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
10910
10911         // Store AFE Registers
10912         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
10913
10914         //Set PSD 128 pts
10915         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  //128 pts
10916
10917         // To SET CH1 to do
10918         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     //Channel 1
10919
10920         // AFE all on step
10921         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
10922         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
10923         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
10924         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
10925         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
10926         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
10927         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
10928         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
10929         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
10930         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
10931         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
10932         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
10933         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
10934         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
10935         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
10936         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
10937
10938         // 3 wire Disable
10939         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
10940
10941         //BB IQK Setting
10942         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
10943         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
10944
10945         //IQK setting tone@ 4.34Mhz
10946         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
10947         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
10948
10949
10950         //Page B init
10951         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
10952         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
10953         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
10954         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
10955         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
10956         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
10957         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
10958
10959         //RF loop Setting
10960         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
10961
10962         //IQK Single tone start
10963         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
10964         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
10965         ODM_StallExecution(1000);
10966         PSD_report_tmp=0x0;
10967
10968         for (n=0;n<2;n++)
10969         {
10970                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
10971                 if (PSD_report_tmp >AntA_report)
10972                         AntA_report=PSD_report_tmp;
10973         }
10974
10975         PSD_report_tmp=0x0;
10976
10977         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  // change to Antenna B
10978         ODM_StallExecution(10);
10979
10980
10981         for (n=0;n<2;n++)
10982         {
10983                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
10984                 if (PSD_report_tmp > AntB_report)
10985                         AntB_report=PSD_report_tmp;
10986         }
10987
10988         // change to open case
10989         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  // change to Ant A and B all open case
10990         ODM_StallExecution(10);
10991
10992         for (n=0;n<2;n++)
10993         {
10994                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
10995                 if (PSD_report_tmp > AntO_report)
10996                         AntO_report=PSD_report_tmp;
10997         }
10998
10999         //Close IQK Single Tone function
11000         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
11001         PSD_report_tmp = 0x0;
11002
11003         //1 Return to antanna A
11004         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
11005         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
11006         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
11007         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
11008         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
11009         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
11010         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
11011         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
11012
11013         //Reload AFE Registers
11014         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
11015
11016         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
11017         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
11018         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report));
11019
11020
11021         if (pDM_Odm->SupportICType == ODM_RTL8723A)
11022         {
11023         //2 Test Ant B based on Ant A is ON
11024         if (mode==ANTTESTB)
11025         {
11026         if (AntA_report >=      100)
11027         {
11028                 if (AntB_report > (AntA_report+1))
11029                 {
11030                         pDM_SWAT_Table->ANTB_ON=false;
11031                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
11032                 }
11033                 else
11034                 {
11035                         pDM_SWAT_Table->ANTB_ON=true;
11036                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
11037                 }
11038         }
11039         else
11040         {
11041                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
11042                 pDM_SWAT_Table->ANTB_ON=false; // Set Antenna B off as default
11043                 bResult = false;
11044         }
11045         }
11046         //2 Test Ant A and B based on DPDT Open
11047         else if (mode==ANTTESTALL)
11048         {
11049                 if ((AntO_report >=100)&(AntO_report <118))
11050                 {
11051                         if (AntA_report > (AntO_report+1))
11052                         {
11053                                 pDM_SWAT_Table->ANTA_ON=false;
11054                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n"));
11055                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF"));
11056                         }
11057                         else
11058                         {
11059                                 pDM_SWAT_Table->ANTA_ON=true;
11060                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n"));
11061                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON"));
11062                         }
11063
11064                                 if (AntB_report > (AntO_report+2))
11065                         {
11066                                 pDM_SWAT_Table->ANTB_ON=false;
11067                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n"));
11068                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF"));
11069                         }
11070                         else
11071                         {
11072                                 pDM_SWAT_Table->ANTB_ON=true;
11073                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n"));
11074                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON"));
11075                         }
11076                 }
11077         }
11078         }
11079         else if (pDM_Odm->SupportICType == ODM_RTL8192C)
11080         {
11081                 if (AntA_report >=      100)
11082                 {
11083                         if (AntB_report > (AntA_report+2))
11084                         {
11085                                 pDM_SWAT_Table->ANTA_ON=false;
11086                                 pDM_SWAT_Table->ANTB_ON=true;
11087                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
11088                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
11089                         }
11090                         else if (AntA_report > (AntB_report+2))
11091                         {
11092                                 pDM_SWAT_Table->ANTA_ON=true;
11093                                 pDM_SWAT_Table->ANTB_ON=false;
11094                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
11095                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
11096                         }
11097                         else
11098                         {
11099                                 pDM_SWAT_Table->ANTA_ON=true;
11100                                 pDM_SWAT_Table->ANTB_ON=true;
11101                                 RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
11102                         }
11103                 }
11104                 else
11105                 {
11106                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
11107                         pDM_SWAT_Table->ANTA_ON=true; // Set Antenna A on as default
11108                         pDM_SWAT_Table->ANTB_ON=false; // Set Antenna B off as default
11109                         bResult = false;
11110                 }
11111         }
11112         return bResult;
11113
11114 }
11115
11116
11117 #endif   // end odm_CE