1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
23 #if (RTL8723A_SUPPORT == 1)
26 odm_ConfigRFReg_8723A(
30 IN ODM_RF_RADIO_PATH_E RF_PATH,
36 #ifdef CONFIG_LONG_DELAY_ISSUE
42 else if (Addr == 0xfd)
46 else if (Addr == 0xfc)
50 else if (Addr == 0xfb)
54 else if (Addr == 0xfa)
58 else if (Addr == 0xf9)
64 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
65 // Add 1us delay between BB/RF register setting.
72 odm_ConfigRF_RadioA_8723A(
78 u4Byte content = 0x1000; // RF_Content: radioa_txt
79 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
81 odm_ConfigRFReg_8723A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
83 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
87 odm_ConfigRF_RadioB_8723A(
93 u4Byte content = 0x1001; // RF_Content: radiob_txt
94 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
96 odm_ConfigRFReg_8723A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
98 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
104 IN PDM_ODM_T pDM_Odm,
109 ODM_Write1Byte(pDM_Odm, Addr, Data);
110 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
114 odm_ConfigBB_AGC_8723A(
115 IN PDM_ODM_T pDM_Odm,
121 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
122 // Add 1us delay between BB/RF register setting.
125 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
129 odm_ConfigBB_PHY_REG_PG_8723A(
130 IN PDM_ODM_T pDM_Odm,
137 #ifdef CONFIG_LONG_DELAY_ISSUE
142 else if (Addr == 0xfd)
144 else if (Addr == 0xfc)
146 else if (Addr == 0xfb)
148 else if (Addr == 0xfa)
150 else if (Addr == 0xf9)
152 // TODO: ODM_StorePwrIndexDiffRateOffset(...)
153 // storePwrIndexDiffRateOffset(Adapter, Addr, Bitmask, Data);
155 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
159 odm_ConfigBB_PHY_8723A(
160 IN PDM_ODM_T pDM_Odm,
167 #ifdef CONFIG_LONG_DELAY_ISSUE
172 else if (Addr == 0xfd)
174 else if (Addr == 0xfc)
176 else if (Addr == 0xfb)
178 else if (Addr == 0xfa)
180 else if (Addr == 0xf9)
182 else if (Addr == 0xa24)
183 pDM_Odm->RFCalibrateInfo.RegA24 = Data;
184 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
186 // Add 1us delay between BB/RF register setting.
189 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));