hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_conf.h>
  23 #include <osdep_service.h>
  24 #include <drv_types.h>
  25 #include <rtw_efuse.h>
  26
  27
  28 #include <HalPwrSeqCmd.h>
  29 #include <Hal8723PwrSeq.h>
  30 #include <rtl8723a_hal.h>
  31 #include <rtl8723a_led.h>
  32 #include <linux/ieee80211.h>
  33
  34 #ifdef CONFIG_IOL
  35 #include <rtw_iol.h>
  36 #endif
  37
  38 #ifdef CONFIG_EFUSE_CONFIG_FILE
  39 #include <linux/fs.h>
  40 #include <asm/uaccess.h>
  41 #endif //CONFIG_EFUSE_CONFIG_FILE
  42
  43 #include <usb_ops.h>
  44 #include <usb_hal.h>
  45 #include <usb_osintf.h>
  46
  47 #if DISABLE_BB_RF
  48         #define         HAL_MAC_ENABLE  0
  49         #define         HAL_BB_ENABLE           0
  50         #define         HAL_RF_ENABLE           0
  51 #else
  52         #define         HAL_MAC_ENABLE  1
  53         #define         HAL_BB_ENABLE           1
  54         #define         HAL_RF_ENABLE           1
  55 #endif
  56
  57
  58 static VOID
  59 _ConfigChipOutEP(
  60         PADAPTER        pAdapter,
  61         u8              NumOutPipe
  62         )
  63 {
  64         u8                      value8;
  65         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  66
  67         pHalData->OutEpQueueSel = 0;
  68         pHalData->OutEpNumber   = 0;
  69
  70         // Normal and High queue
  71         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  72
  73         if(value8 & USB_NORMAL_SIE_EP_MASK){
  74                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  75                 pHalData->OutEpNumber++;
  76         }
  77
  78         if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
  79                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  80                 pHalData->OutEpNumber++;
  81         }
  82
  83         // Low queue
  84         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  85         if(value8 & USB_NORMAL_SIE_EP_MASK){
  86                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  87                 pHalData->OutEpNumber++;
  88         }
  89
  90         // TODO: Error recovery for this case
  91         //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber));
  92
  93 }
  94
  95 static bool HalUsbSetQueuePipeMapping8192CUsb(
  96         PADAPTER        pAdapter,
  97         u8              NumInPipe,
  98         u8              NumOutPipe
  99         )
 100 {
 101         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
 102         bool                    result          = _FALSE;
 103
 104         _ConfigChipOutEP(pAdapter, NumOutPipe);
 105
 106         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
 107         if(1 == pHalData->OutEpNumber){
 108                 if(1 != NumInPipe){
 109                         return result;
 110                 }
 111         }
 112
 113         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
 114
 115         return result;
 116
 117 }
 118
 119 void rtl8192cu_interface_configure(_adapter *padapter)
 120 {
 121         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 122         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 123
 124         if (pdvobjpriv->ishighspeed == _TRUE)
 125         {
 126                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
 127         }
 128         else
 129         {
 130                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 131         }
 132
 133         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 134
 135 #ifdef CONFIG_USB_TX_AGGREGATION
 136         pHalData->UsbTxAggMode          = 1;
 137         pHalData->UsbTxAggDescNum       = 0x6;  // only 4 bits
 138 #endif
 139
 140 #ifdef CONFIG_USB_RX_AGGREGATION
 141         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 142         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 143         pHalData->UsbRxAggBlockTimeout  = 0x6;
 144         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 145         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 146 #endif
 147
 148         HalUsbSetQueuePipeMapping8192CUsb(padapter,
 149                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 150
 151 }
 152
 153 static u8 _InitPowerOn(PADAPTER padapter)
 154 {
 155         u8              status = _SUCCESS;
 156         u16                     value16=0;
 157         u8                      value8 = 0;
 158
 159         // RSV_CTRL 0x1C[7:0] = 0x00                    // unlock ISO/CLK/Power control register
 160         rtw_write8(padapter, REG_RSV_CTRL, 0x0);
 161
 162         // HW Power on sequence
 163         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_enable_flow ))
 164                                 return _FAIL;
 165
 166         // 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051
 167                         value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
 168                         rtw_write8(padapter,REG_APS_FSMCO+2,(value8|BIT3));
 169
 170                         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 171                         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 172                         value16 = rtw_read16(padapter, REG_CR);
 173                         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 174                                                 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC | CALTMR_EN);
 175                         rtw_write16(padapter, REG_CR, value16);
 176
 177         //for Efuse PG, suggest by Jackie 2011.11.23
 178         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
 179
 180         return status;
 181 }
 182
 183
 184 static void _dbg_dump_macreg(_adapter *padapter)
 185 {
 186         u32 offset = 0;
 187         u32 val32 = 0;
 188         u32 index =0 ;
 189         for(index=0;index<64;index++)
 190         {
 191                 offset = index*4;
 192                 val32 = rtw_read32(padapter,offset);
 193                 DBG_8723A("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 194         }
 195 }
 196
 197 //-------------------------------------------------------------------------
 198 //
 199 // LLT R/W/Init function
 200 //
 201 //-------------------------------------------------------------------------
 202 static u8 _LLTWrite(
 203   PADAPTER      Adapter,
 204         u32             address,
 205         u32             data
 206         )
 207 {
 208         u8      status = _SUCCESS;
 209         int             count = 0;
 210         u32             value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 211
 212         rtw_write32(Adapter, REG_LLT_INIT, value);
 213
 214         //polling
 215         do{
 216
 217                 value = rtw_read32(Adapter, REG_LLT_INIT);
 218                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 219                         break;
 220                 }
 221
 222                 if(count > POLLING_LLT_THRESHOLD){
 223                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
 224                         status = _FAIL;
 225                         break;
 226                 }
 227         }while(count++);
 228
 229         return status;
 230
 231 }
 232
 233
 234 static u8 _LLTRead(
 235   PADAPTER      Adapter,
 236         u32             address
 237         )
 238 {
 239         int             count = 0;
 240         u32             value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
 241
 242         rtw_write32(Adapter, REG_LLT_INIT, value);
 243
 244         //polling and get value
 245         do{
 246
 247                 value = rtw_read32(Adapter, REG_LLT_INIT);
 248                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 249                         return (u8)value;
 250                 }
 251
 252                 if(count > POLLING_LLT_THRESHOLD){
 253                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
 254                         break;
 255                 }
 256         }while(count++);
 257
 258         return 0xFF;
 259
 260 }
 261
 262
 263 //---------------------------------------------------------------
 264 //
 265 //      MAC init functions
 266 //
 267 //---------------------------------------------------------------
 268 static VOID
 269 _SetMacID(
 270   PADAPTER Adapter, u8* MacID
 271         )
 272 {
 273         u32 i;
 274         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 275 #ifdef  CONFIG_CONCURRENT_MODE
 276                 if(Adapter->iface_type == IFACE_PORT1)
 277                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 278                 else
 279 #endif
 280                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 281         }
 282 }
 283
 284 static VOID
 285 _SetBSSID(
 286   PADAPTER Adapter, u8* BSSID
 287         )
 288 {
 289         u32 i;
 290         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 291 #ifdef  CONFIG_CONCURRENT_MODE
 292                 if(Adapter->iface_type == IFACE_PORT1)
 293                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 294                 else
 295 #endif
 296                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 297         }
 298 }
 299
 300
 301 // Shall USB interface init this?
 302 static VOID
 303 _InitInterrupt(
 304   PADAPTER Adapter
 305         )
 306 {
 307         u32     value32;
 308
 309         // HISR - turn all on
 310         value32 = 0xFFFFFFFF;
 311         rtw_write32(Adapter, REG_HISR, value32);
 312
 313         // HIMR - turn all on
 314         rtw_write32(Adapter, REG_HIMR, value32);
 315 }
 316
 317
 318 static VOID
 319 _InitQueueReservedPage(
 320   PADAPTER Adapter
 321         )
 322 {
 323         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 324         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 325
 326         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 327         u32                     numHQ           = 0;
 328         u32                     numLQ           = 0;
 329         u32                     numNQ           = 0;
 330         u32                     numPubQ;
 331         u32                     value32;
 332         u8                      value8;
 333         bool            bWiFiConfig     = pregistrypriv->wifi_spec;
 334         //u32                   txQPageNum, txQPageUnit,txQRemainPage;
 335
 336         { //for WMM
 337                 //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
 338
 339                 numPubQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_PUBQ:NORMAL_PAGE_NUM_PUBQ;
 340
 341                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 342                 {
 343                         numHQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
 344                 }
 345
 346                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 347                 {
 348                         numLQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
 349                 }
 350                 // NOTE: This step shall be proceed before writting REG_RQPN.
 351                 if(pHalData->OutEpQueueSel & TX_SELE_NQ){
 352                         numNQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
 353                 }
 354                 value8 = (u8)_NPQ(numNQ);
 355                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 356         }
 357
 358         // TX DMA
 359         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 360         rtw_write32(Adapter, REG_RQPN, value32);
 361 }
 362
 363 static VOID
 364 _InitTxBufferBoundary(
 365   PADAPTER Adapter
 366         )
 367 {
 368         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 369         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 370
 371         u8      txpktbuf_bndy;
 372
 373         if(!pregistrypriv->wifi_spec){
 374                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 375         }
 376         else{//for WMM
 377                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 378         }
 379
 380         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 381         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 382         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 383         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 384 #if 1
 385         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 386 #else
 387         txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
 388         txdmactrl &= ~BCN_HEAD_MASK;
 389         txdmactrl |= BCN_HEAD(txpktbuf_bndy);
 390         PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
 391 #endif
 392 }
 393
 394 static VOID
 395 _InitPageBoundary(
 396   PADAPTER Adapter
 397         )
 398 {
 399         // RX Page Boundary
 400         //srand(static_cast<unsigned int>(time(NULL)) );
 401         u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
 402
 403         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 404
 405         // TODO: ?? shall we set tx boundary?
 406 }
 407
 408
 409 static VOID
 410 _InitNormalChipRegPriority(
 411         PADAPTER        Adapter,
 412         u16             beQ,
 413         u16             bkQ,
 414         u16             viQ,
 415         u16             voQ,
 416         u16             mgtQ,
 417         u16             hiQ
 418         )
 419 {
 420         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 421
 422         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 423                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 424                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 425
 426         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 427 }
 428
 429 static VOID
 430 _InitNormalChipOneOutEpPriority(
 431         PADAPTER Adapter
 432         )
 433 {
 434         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 435
 436         u16     value = 0;
 437         switch(pHalData->OutEpQueueSel)
 438         {
 439                 case TX_SELE_HQ:
 440                         value = QUEUE_HIGH;
 441                         break;
 442                 case TX_SELE_LQ:
 443                         value = QUEUE_LOW;
 444                         break;
 445                 case TX_SELE_NQ:
 446                         value = QUEUE_NORMAL;
 447                         break;
 448                 default:
 449                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 450                         break;
 451         }
 452
 453         _InitNormalChipRegPriority(Adapter,
 454                                                                 value,
 455                                                                 value,
 456                                                                 value,
 457                                                                 value,
 458                                                                 value,
 459                                                                 value
 460                                                                 );
 461
 462 }
 463
 464 static VOID
 465 _InitNormalChipTwoOutEpPriority(
 466         PADAPTER Adapter
 467         )
 468 {
 469         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 470         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 471         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 472
 473
 474         u16     valueHi = 0;
 475         u16     valueLow = 0;
 476
 477         switch(pHalData->OutEpQueueSel)
 478         {
 479                 case (TX_SELE_HQ | TX_SELE_LQ):
 480                         valueHi = QUEUE_HIGH;
 481                         valueLow = QUEUE_LOW;
 482                         break;
 483                 case (TX_SELE_NQ | TX_SELE_LQ):
 484                         valueHi = QUEUE_NORMAL;
 485                         valueLow = QUEUE_LOW;
 486                         break;
 487                 case (TX_SELE_HQ | TX_SELE_NQ):
 488                         valueHi = QUEUE_HIGH;
 489                         valueLow = QUEUE_NORMAL;
 490                         break;
 491                 default:
 492                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 493                         break;
 494         }
 495
 496         if(!pregistrypriv->wifi_spec ){
 497                 beQ             = valueLow;
 498                 bkQ             = valueLow;
 499                 viQ             = valueHi;
 500                 voQ             = valueHi;
 501                 mgtQ    = valueHi;
 502                 hiQ             = valueHi;
 503         }
 504         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 505                 beQ             = valueLow;
 506                 bkQ             = valueHi;
 507                 viQ             = valueHi;
 508                 voQ             = valueLow;
 509                 mgtQ    = valueHi;
 510                 hiQ             = valueHi;
 511         }
 512
 513         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 514
 515 }
 516
 517 static VOID
 518 _InitNormalChipThreeOutEpPriority(
 519         PADAPTER Adapter
 520         )
 521 {
 522         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 523         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 524
 525         if(!pregistrypriv->wifi_spec ){// typical setting
 526                 beQ             = QUEUE_LOW;
 527                 bkQ             = QUEUE_LOW;
 528                 viQ             = QUEUE_NORMAL;
 529                 voQ             = QUEUE_HIGH;
 530                 mgtQ    = QUEUE_HIGH;
 531                 hiQ             = QUEUE_HIGH;
 532         }
 533         else{// for WMM
 534                 beQ             = QUEUE_LOW;
 535                 bkQ             = QUEUE_NORMAL;
 536                 viQ             = QUEUE_NORMAL;
 537                 voQ             = QUEUE_HIGH;
 538                 mgtQ    = QUEUE_HIGH;
 539                 hiQ             = QUEUE_HIGH;
 540         }
 541         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 542 }
 543
 544 static VOID
 545 _InitNormalChipQueuePriority(
 546         PADAPTER Adapter
 547         )
 548 {
 549         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 550
 551         switch(pHalData->OutEpNumber)
 552         {
 553                 case 1:
 554                         _InitNormalChipOneOutEpPriority(Adapter);
 555                         break;
 556                 case 2:
 557                         _InitNormalChipTwoOutEpPriority(Adapter);
 558                         break;
 559                 case 3:
 560                         _InitNormalChipThreeOutEpPriority(Adapter);
 561                         break;
 562                 default:
 563                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 564                         break;
 565         }
 566
 567
 568 }
 569
 570 static VOID
 571 _InitQueuePriority(
 572   PADAPTER Adapter
 573         )
 574 {
 575         _InitNormalChipQueuePriority(Adapter);
 576 }
 577
 578 static VOID
 579 _InitHardwareDropIncorrectBulkOut(
 580   PADAPTER Adapter
 581         )
 582 {
 583         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 584         value32 |= DROP_DATA_EN;
 585         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 586 }
 587
 588 static VOID
 589 _InitNetworkType(
 590   PADAPTER Adapter
 591         )
 592 {
 593         u32     value32;
 594
 595         value32 = rtw_read32(Adapter, REG_CR);
 596
 597         // TODO: use the other function to set network type
 598 #if RTL8191C_FPGA_NETWORKTYPE_ADHOC
 599         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 600 #else
 601         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 602 #endif
 603         rtw_write32(Adapter, REG_CR, value32);
 604 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 605 }
 606
 607 static VOID
 608 _InitTransferPageSize(
 609   PADAPTER Adapter
 610         )
 611 {
 612         // Tx page size is always 128.
 613
 614         u8      value8;
 615         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 616         rtw_write8(Adapter, REG_PBP, value8);
 617 }
 618
 619 static VOID
 620 _InitDriverInfoSize(
 621   PADAPTER      Adapter,
 622         u8              drvInfoSize
 623         )
 624 {
 625         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 626 }
 627
 628 static VOID
 629 _InitWMACSetting(
 630   PADAPTER Adapter
 631         )
 632 {
 633         //u4Byte                        value32;
 634         //u16                   value16;
 635         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 636
 637         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 638         //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 639          // don't turn on AAP, it will allow all packets to driver
 640         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 641 #if (1 == RTL8192C_RX_PACKET_INCLUDE_CRC)
 642         pHalData->ReceiveConfig |= ACRC32;
 643 #endif
 644
 645         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 646         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 647
 648         // Accept all multicast address
 649         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 650         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 651
 652
 653         // Accept all data frames
 654         //value16 = 0xFFFF;
 655         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 656
 657         // 2010.09.08 hpfan
 658         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 659         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 660         //value16 = 0x400;
 661         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 662
 663         // Accept all management frames
 664         //value16 = 0xFFFF;
 665         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 666
 667         //enable RX_SHIFT bits
 668         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 669
 670 }
 671
 672 static VOID
 673 _InitAdaptiveCtrl(
 674   PADAPTER Adapter
 675         )
 676 {
 677         u16     value16;
 678         u32     value32;
 679
 680         // Response Rate Set
 681         value32 = rtw_read32(Adapter, REG_RRSR);
 682         value32 &= ~RATE_BITMAP_ALL;
 683         value32 |= RATE_RRSR_CCK_ONLY_1M;
 684         rtw_write32(Adapter, REG_RRSR, value32);
 685
 686         // CF-END Threshold
 687         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 688
 689         // SIFS (used in NAV)
 690         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 691         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 692
 693         // Retry Limit
 694         value16 = _LRL(0x30) | _SRL(0x30);
 695         rtw_write16(Adapter, REG_RL, value16);
 696
 697 }
 698
 699 static VOID
 700 _InitRateFallback(
 701   PADAPTER Adapter
 702         )
 703 {
 704         // Set Data Auto Rate Fallback Retry Count register.
 705         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 706         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 707         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 708         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 709
 710 }
 711
 712
 713 static VOID
 714 _InitEDCA(
 715   PADAPTER Adapter
 716         )
 717 {
 718         // Set Spec SIFS (used in NAV)
 719         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 720         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 721
 722         // Set SIFS for CCK
 723         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 724
 725         // Set SIFS for OFDM
 726         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 727
 728         // TXOP
 729         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 730         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 731         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 732         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 733 }
 734
 735 #ifdef CONFIG_LED
 736 static void _InitHWLed(PADAPTER Adapter)
 737 {
 738         struct led_priv *pledpriv = &(Adapter->ledpriv);
 739
 740         if( pledpriv->LedStrategy != HW_LED)
 741                 return;
 742
 743 // HW led control
 744 // to do ....
 745 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 746
 747 }
 748 #endif //CONFIG_LED
 749
 750 static VOID
 751 _InitRDGSetting(
 752         PADAPTER Adapter
 753         )
 754 {
 755         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 756         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 757         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 758 }
 759
 760 static VOID
 761 _InitRxSetting(
 762         PADAPTER Adapter
 763         )
 764 {
 765         rtw_write32(Adapter, REG_MACID, 0x87654321);
 766         rtw_write32(Adapter, 0x0700, 0x87654321);
 767 }
 768
 769 static VOID
 770 _InitRetryFunction(
 771   PADAPTER Adapter
 772         )
 773 {
 774         u8      value8;
 775
 776         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 777         value8 |= EN_AMPDU_RTY_NEW;
 778         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 779
 780         // Set ACK timeout
 781         rtw_write8(Adapter, REG_ACKTO, 0x40);
 782 }
 783
 784 /*-----------------------------------------------------------------------------
 785  * Function:    usb_AggSettingTxUpdate()
 786  *
 787  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 788  *                      dynamic TX/RX aggreagtion parameters update.
 789  *
 790  * Input:                       PADAPTER
 791  *
 792  * Output/Return:       NONE
 793  *
 794  * Revised History:
 795  *      When            Who             Remark
 796  *      12/10/2010      MHC             Seperate to smaller function.
 797  *
 798  *---------------------------------------------------------------------------*/
 799 static VOID
 800 usb_AggSettingTxUpdate(
 801         PADAPTER                        Adapter
 802         )
 803 {
 804 #ifdef CONFIG_USB_TX_AGGREGATION
 805         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 806         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 807         u32                     value32;
 808
 809         if(Adapter->registrypriv.wifi_spec)
 810                 pHalData->UsbTxAggMode = _FALSE;
 811
 812         if(pHalData->UsbTxAggMode){
 813                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 814                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 815                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 816
 817                 rtw_write32(Adapter, REG_TDECTRL, value32);
 818         }
 819
 820 #endif
 821 }       // usb_AggSettingTxUpdate
 822
 823
 824 /*-----------------------------------------------------------------------------
 825  * Function:    usb_AggSettingRxUpdate()
 826  *
 827  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 828  *                      dynamic TX/RX aggreagtion parameters update.
 829  *
 830  * Input:                       PADAPTER
 831  *
 832  * Output/Return:       NONE
 833  *
 834  * Revised History:
 835  *      When            Who             Remark
 836  *      12/10/2010      MHC             Seperate to smaller function.
 837  *
 838  *---------------------------------------------------------------------------*/
 839 static VOID
 840 usb_AggSettingRxUpdate(
 841         PADAPTER                        Adapter
 842         )
 843 {
 844 #ifdef CONFIG_USB_RX_AGGREGATION
 845         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 846         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 847         u8                      valueDMA;
 848         u8                      valueUSB;
 849
 850         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 851         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 852
 853         switch(pHalData->UsbRxAggMode)
 854         {
 855                 case USB_RX_AGG_DMA:
 856                         valueDMA |= RXDMA_AGG_EN;
 857                         valueUSB &= ~USB_AGG_EN;
 858                         break;
 859                 case USB_RX_AGG_USB:
 860                         valueDMA &= ~RXDMA_AGG_EN;
 861                         valueUSB |= USB_AGG_EN;
 862                         break;
 863                 case USB_RX_AGG_MIX:
 864                         valueDMA |= RXDMA_AGG_EN;
 865                         valueUSB |= USB_AGG_EN;
 866                         break;
 867                 case USB_RX_AGG_DISABLE:
 868                 default:
 869                         valueDMA &= ~RXDMA_AGG_EN;
 870                         valueUSB &= ~USB_AGG_EN;
 871                         break;
 872         }
 873
 874         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 875         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 876
 877         switch(pHalData->UsbRxAggMode)
 878         {
 879                 case USB_RX_AGG_DMA:
 880                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 881                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 882                         break;
 883                 case USB_RX_AGG_USB:
 884                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 885                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 886                         break;
 887                 case USB_RX_AGG_MIX:
 888                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 889                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 890                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 891                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 892                         break;
 893                 case USB_RX_AGG_DISABLE:
 894                 default:
 895                         // TODO:
 896                         break;
 897         }
 898
 899         switch(PBP_128)
 900         {
 901                 case PBP_128:
 902                         pHalData->HwRxPageSize = 128;
 903                         break;
 904                 case PBP_64:
 905                         pHalData->HwRxPageSize = 64;
 906                         break;
 907                 case PBP_256:
 908                         pHalData->HwRxPageSize = 256;
 909                         break;
 910                 case PBP_512:
 911                         pHalData->HwRxPageSize = 512;
 912                         break;
 913                 case PBP_1024:
 914                         pHalData->HwRxPageSize = 1024;
 915                         break;
 916                 default:
 917                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 918                         break;
 919         }
 920 #endif
 921 }       // usb_AggSettingRxUpdate
 922
 923 static VOID
 924 InitUsbAggregationSetting(
 925   PADAPTER Adapter
 926         )
 927 {
 928         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 929
 930         // Tx aggregation setting
 931         usb_AggSettingTxUpdate(Adapter);
 932
 933         // Rx aggregation setting
 934         usb_AggSettingRxUpdate(Adapter);
 935
 936         // 201/12/10 MH Add for USB agg mode dynamic switch.
 937         pHalData->UsbRxHighSpeedMode = _FALSE;
 938 }
 939
 940 /*-----------------------------------------------------------------------------
 941  * Function:    USB_AggModeSwitch()
 942  *
 943  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
 944  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
 945  *                      need to monitor the influence of FTP/network share.
 946  *                      For TX mode, we are still ubder investigation.
 947  *
 948  * Input:               PADAPTER
 949  *
 950  * Output:              NONE
 951  *
 952  * Return:              NONE
 953  *
 954  * Revised History:
 955  *      When            Who             Remark
 956  *      12/10/2010      MHC             Create Version 0.
 957  *
 958  *---------------------------------------------------------------------------*/
 959 VOID
 960 USB_AggModeSwitch(
 961         PADAPTER                        Adapter
 962         )
 963 {
 964 #if 0
 965         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 966         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
 967
 968         //pHalData->UsbRxHighSpeedMode = FALSE;
 969         // How to measure the RX speed? We assume that when traffic is more than
 970         if (pMgntInfo->bRegAggDMEnable == _FALSE)
 971         {
 972                 return; // Inf not support.
 973         }
 974
 975
 976         if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _TRUE &&
 977                 pHalData->UsbRxHighSpeedMode == _FALSE)
 978         {
 979                 pHalData->UsbRxHighSpeedMode = _TRUE;
 980                 DBG_8723A("UsbAggModeSwitchCheck to HIGH\n");
 981         }
 982         else if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _FALSE &&
 983                 pHalData->UsbRxHighSpeedMode == _TRUE)
 984         {
 985                 pHalData->UsbRxHighSpeedMode = _FALSE;
 986                 DBG_8723A("UsbAggModeSwitchCheck to LOW\n");
 987         }
 988         else
 989         {
 990                 return;
 991         }
 992
 993         // 2010/12/10 MH Add for USB Aggregation judgement we need to
 994         //if( pMgntInfo->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
 995                 //                      pMgntInfo->LinkDetectInfo.NumTxOkInPeriod > 4000 )
 996
 997 #ifdef CONFIG_USB_TX_AGGREGATION
 998         //usb_AggSettingTxUpdate(Adapter);
 999 #endif
1000
1001 #ifdef CONFIG_USB_RX_AGGREGATION
1002         if (pHalData->UsbRxHighSpeedMode == _TRUE)
1003         {
1004                 // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
1005                 // USB mode
1006                 pHalData->UsbRxAggBlockCount            = 40;
1007                 pHalData->UsbRxAggBlockTimeout  = 5;
1008                 // Mix mode
1009                 pHalData->UsbRxAggPageCount             = 72;
1010                 pHalData->UsbRxAggPageTimeout   = 6;
1011         }
1012         else
1013         {
1014                 // USB mode
1015                 pHalData->UsbRxAggBlockCount            = pMgntInfo->RegUsbRxAggBlockCount;
1016                 pHalData->UsbRxAggBlockTimeout  = pMgntInfo->RegUsbRxAggBlockTimeout;
1017                 // Mix mode
1018                 pHalData->UsbRxAggPageCount             = pMgntInfo->RegUsbRxAggPageCount;
1019                 pHalData->UsbRxAggPageTimeout   = pMgntInfo->RegUsbRxAggPageTimeout;
1020         }
1021 #endif
1022 #endif
1023 }       // USB_AggModeSwitch
1024
1025 static VOID
1026 _InitOperationMode(
1027         PADAPTER                        Adapter
1028         )
1029 {
1030 #if 0//gtest
1031         PHAL_DATA_8192CUSB      pHalData = GetHalData8192CUsb(Adapter);
1032         u1Byte                          regBwOpMode = 0;
1033         u4Byte                          regRATR = 0, regRRSR = 0;
1034
1035
1036         //1 This part need to modified according to the rate set we filtered!!
1037         //
1038         // Set RRSR, RATR, and REG_BWOPMODE registers
1039         //
1040         switch(Adapter->RegWirelessMode)
1041         {
1042                 case WIRELESS_MODE_B:
1043                         regBwOpMode = BW_OPMODE_20MHZ;
1044                         regRATR = RATE_ALL_CCK;
1045                         regRRSR = RATE_ALL_CCK;
1046                         break;
1047                 case WIRELESS_MODE_A:
1048                         ASSERT(FALSE);
1049 #if 0
1050                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1051                         regRATR = RATE_ALL_OFDM_AG;
1052                         regRRSR = RATE_ALL_OFDM_AG;
1053 #endif
1054                         break;
1055                 case WIRELESS_MODE_G:
1056                         regBwOpMode = BW_OPMODE_20MHZ;
1057                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1058                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1059                         break;
1060                 case WIRELESS_MODE_AUTO:
1061                         if (Adapter->bInHctTest)
1062                         {
1063                             regBwOpMode = BW_OPMODE_20MHZ;
1064                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1065                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1066                         }
1067                         else
1068                         {
1069                             regBwOpMode = BW_OPMODE_20MHZ;
1070                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1071                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1072                         }
1073                         break;
1074                 case WIRELESS_MODE_N_24G:
1075                         // It support CCK rate by default.
1076                         // CCK rate will be filtered out only when associated AP does not support it.
1077                         regBwOpMode = BW_OPMODE_20MHZ;
1078                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1079                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1080                         break;
1081                 case WIRELESS_MODE_N_5G:
1082                         ASSERT(FALSE);
1083 #if 0
1084                         regBwOpMode = BW_OPMODE_5G;
1085                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1086                         regRRSR = RATE_ALL_OFDM_AG;
1087 #endif
1088                         break;
1089         }
1090
1091         // Ziv ????????
1092         //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
1093         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1094
1095         // For Min Spacing configuration.
1096         switch(pHalData->RF_Type)
1097         {
1098                 case RF_1T2R:
1099                 case RF_1T1R:
1100                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter: RF_Type%s\n", (pHalData->RF_Type==RF_1T1R? "(1T1R)":"(1T2R)")));
1101                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
1102                         break;
1103                 case RF_2T2R:
1104                 case RF_2T2R_GREEN:
1105                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter:RF_Type(2T2R)\n"));
1106                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
1107                         break;
1108         }
1109
1110         rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, Adapter->MgntInfo.MinSpaceCfg);
1111 #endif
1112 }
1113
1114 static VOID
1115 _InitRFType(
1116         PADAPTER Adapter
1117         )
1118 {
1119         struct registry_priv     *pregpriv = &Adapter->registrypriv;
1120         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1121         bool                    is92CU          = IS_92C_SERIAL(pHalData->VersionID);
1122
1123 #if     DISABLE_BB_RF
1124         pHalData->rf_chip       = RF_PSEUDO_11N;
1125         return;
1126 #endif
1127
1128         pHalData->rf_chip       = RF_6052;
1129
1130         if(_FALSE == is92CU){
1131                 pHalData->rf_type = RF_1T1R;
1132                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
1133                 return;
1134         }
1135
1136         // TODO: Consider that EEPROM set 92CU to 1T1R later.
1137         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
1138         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
1139         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1140
1141 }
1142
1143 static VOID _InitAdhocWorkaroundParams(PADAPTER Adapter)
1144 {
1145 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1146         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1147         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1148         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1149         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1150         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1151 #endif
1152 }
1153
1154 // Set CCK and OFDM Block "ON"
1155 static VOID _BBTurnOnBlock(
1156         PADAPTER                Adapter
1157         )
1158 {
1159 #if (DISABLE_BB_RF)
1160         return;
1161 #endif
1162
1163         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1164         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1165 }
1166
1167 #define MgntActSet_RF_State(...)
1168 static void _RfPowerSave(PADAPTER padapter)
1169 {
1170 #if 0
1171         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1172         struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv;
1173         rt_rf_power_state eRfPowerStateToSet;
1174         u8 u1bTmp;
1175
1176
1177 #if (DISABLE_BB_RF)
1178         return;
1179 #endif
1180         //
1181         // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1182         // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1183         // call init_adapter. May cause some problem??
1184         //
1185         // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1186         // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1187         // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1188         // Added by tynli. 2010.03.30.
1189         ppwrctrl->rf_pwrstate = rf_on;
1190         RT_CLEAR_PS_LEVEL(ppwrctrl, RT_RF_OFF_LEVL_HALT_NIC);
1191         //Added by chiyokolin, 2011.10.12 for Tx
1192         rtw_write8(padapter, REG_TXPAUSE, 0x00);
1193
1194         // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1195         // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1196
1197         eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(padapter);
1198         ppwrctrl->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
1199         ppwrctrl->rfoff_reason |= (ppwrctrl->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
1200
1201         if (ppwrctrl->rfoff_reason & RF_CHANGE_BY_HW)
1202                 ppwrctrl->b_hw_radio_off = _TRUE;
1203
1204         if (ppwrctrl->reg_rfoff == _TRUE)
1205         {
1206                 // User disable RF via registry.
1207                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
1208                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
1209
1210 //              if (padapter->bSlaveOfDMSP)
1211 //                      return;
1212         }
1213         else if (ppwrctrl->rfoff_reason > RF_CHANGE_BY_PS)
1214         {
1215                 // H/W or S/W RF OFF before sleep.
1216                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
1217                 MgntActSet_RF_State(padapter, rf_off, ppwrctrl->rfoff_reason, _TRUE);
1218         }
1219         else
1220         {
1221                 // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
1222 #if 0
1223 //              if (RT_GetInterfaceSelection(padapter)==INTF_SEL2_MINICARD &&
1224                 if ((pHalData->BoardType == BOARD_MINICARD) &&
1225                         (padapter->MgntInfo.PowerSaveControl.bGpioRfSw))
1226                 {
1227                         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet));
1228                         if (eRfPowerStateToSet == rf_off)
1229                         {
1230                                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
1231                                 ppwrctrl->b_hw_radio_off = _TRUE;
1232                         }
1233                         else
1234                         {
1235                                 ppwrctrl->rf_pwrstate = rf_off;
1236                                 ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1237                                 ppwrctrl->b_hw_radio_off = _FALSE;
1238                                 MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1239                         }
1240                 }
1241                 else
1242 #endif
1243                 {
1244                         ppwrctrl->rf_pwrstate = rf_off;
1245                         ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1246                         MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1247                 }
1248
1249                 ppwrctrl->rfoff_reason = 0;
1250                 ppwrctrl->b_hw_radio_off = _FALSE;
1251                 ppwrctrl->rf_pwrstate = rf_on;
1252                 if (padapter->ledpriv.LedControlHandler)
1253                         padapter->ledpriv.LedControlHandler(padapter, LED_CTL_POWER_ON);
1254         }
1255
1256         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1257         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1258         if (pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1259         {
1260                 // Enable register area 0x0-0xc.
1261                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
1262
1263                 //
1264                 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1265                 // our HW will be set in power-down mode if PDn source from all  functions are configured.
1266                 // 2010.10.06.
1267                 //
1268                 u1bTmp = rtw_read8(padapter, REG_MULTI_FUNC_CTRL);
1269                 u1bTmp |= WL_HWPDN_EN;
1270                 rtw_write8(padapter, REG_MULTI_FUNC_CTRL, u1bTmp);
1271         }
1272 #endif
1273 }
1274
1275 enum {
1276         Antenna_Lfet = 1,
1277         Antenna_Right = 2,
1278 };
1279
1280 //
1281 // 2010/08/09 MH Add for power down check.
1282 //
1283 static bool
1284 HalDetectPwrDownMode(
1285  PADAPTER                               Adapter
1286         )
1287 {
1288         u8      tmpvalue;
1289         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(Adapter);
1290         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1291
1292         EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue);
1293
1294         // 2010/08/25 MH INF priority > PDN Efuse value.
1295         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
1296         {
1297                 pHalData->pwrdown = _TRUE;
1298         }
1299         else
1300         {
1301                 pHalData->pwrdown = _FALSE;
1302         }
1303
1304         DBG_8723A("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
1305         return pHalData->pwrdown;
1306
1307 }       // HalDetectPwrDownMode
1308
1309
1310 //
1311 // 2010/08/26 MH Add for selective suspend mode check.
1312 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1313 // slim card.
1314 //
1315 static VOID
1316 HalDetectSelectiveSuspendMode(
1317  PADAPTER                               Adapter
1318         )
1319 {
1320         u8      tmpvalue;
1321         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1322         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1323
1324         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1325         // can not use FW to notify host the power state switch.
1326
1327         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1328
1329         DBG_8723A("HalDetectSelectiveSuspendMode(): SS ");
1330         if(tmpvalue & BIT1)
1331         {
1332                 DBG_8723A("Enable\n");
1333         }
1334         else
1335         {
1336                 DBG_8723A("Disable\n");
1337                 pdvobjpriv->RegUsbSS = _FALSE;
1338         }
1339
1340         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1341         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1342         {
1343                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1344
1345                 //if (!pMgntInfo->bRegDongleSS)
1346                 //{
1347                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1348                         pdvobjpriv->RegUsbSS = _FALSE;
1349                 //}
1350         }
1351 }       // HalDetectSelectiveSuspendMode
1352 /*-----------------------------------------------------------------------------
1353  * Function:    HwSuspendModeEnable92Cu()
1354  *
1355  * Overview:    HW suspend mode switch.
1356  *
1357  * Input:               NONE
1358  *
1359  * Output:      NONE
1360  *
1361  * Return:      NONE
1362  *
1363  * Revised History:
1364  *      When            Who             Remark
1365  *      08/23/2010      MHC             HW suspend mode switch test..
1366  *---------------------------------------------------------------------------*/
1367 static VOID
1368 HwSuspendModeEnable92Cu(
1369         PADAPTER        pAdapter,
1370         u8                      Type
1371         )
1372 {
1373 }       // HwSuspendModeEnable92Cu
1374
1375 rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter )
1376 {
1377         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(pAdapter);
1378         u8      val8;
1379         rt_rf_power_state rfpowerstate = rf_off;
1380
1381         if(pAdapter->pwrctrlpriv.bHWPowerdown)
1382         {
1383                 val8 = rtw_read8(pAdapter, REG_HSISR);
1384                 DBG_8723A("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1385                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1386         }
1387         else // rf on/off
1388         {
1389                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1390                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1391                 DBG_8723A("GPIO_IN=%02x\n", val8);
1392                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1393         }
1394         return rfpowerstate;
1395 }       // HalDetectPwrDownMode
1396
1397 void _ps_open_RF(_adapter *padapter);
1398
1399 u32 rtl8723au_hal_init(PADAPTER Adapter)
1400 {
1401         u8      val8 = 0;
1402         u32     boundary, status = _SUCCESS;
1403         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1404         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1405         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1406         u8      is92C = IS_92C_SERIAL(pHalData->VersionID);
1407         rt_rf_power_state               eRfPowerStateToSet;
1408         u32 NavUpper = WiFiNavUpperUs;
1409
1410         u32 init_start_time = rtw_get_current_time();
1411
1412
1413 #ifdef DBG_HAL_INIT_PROFILING
1414
1415         enum HAL_INIT_STAGES {
1416                 HAL_INIT_STAGES_BEGIN = 0,
1417                 HAL_INIT_STAGES_INIT_PW_ON,
1418                 HAL_INIT_STAGES_INIT_LLTT,
1419                 HAL_INIT_STAGES_MISC01,
1420                 HAL_INIT_STAGES_DOWNLOAD_FW,
1421                 HAL_INIT_STAGES_MAC,
1422                 HAL_INIT_STAGES_BB,
1423                 HAL_INIT_STAGES_RF,
1424                 HAL_INIT_STAGES_MISC02,
1425                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1426                 HAL_INIT_STAGES_INIT_SECURITY,
1427                 HAL_INIT_STAGES_MISC11,
1428                 //HAL_INIT_STAGES_RF_PS,
1429                 HAL_INIT_STAGES_IQK,
1430                 HAL_INIT_STAGES_PW_TRACK,
1431                 HAL_INIT_STAGES_LCK,
1432                 HAL_INIT_STAGES_MISC21,
1433                 //HAL_INIT_STAGES_INIT_PABIAS,
1434                 #ifdef CONFIG_BT_COEXIST
1435                 HAL_INIT_STAGES_BT_COEXIST,
1436                 #endif
1437                 //HAL_INIT_STAGES_ANTENNA_SEL,
1438                 HAL_INIT_STAGES_INIT_HAL_DM,
1439                 HAL_INIT_STAGES_MISC31,
1440                 HAL_INIT_STAGES_END,
1441                 HAL_INIT_STAGES_NUM
1442         };
1443
1444         char * hal_init_stages_str[] = {
1445                 "HAL_INIT_STAGES_BEGIN",
1446                 "HAL_INIT_STAGES_INIT_PW_ON",
1447                 "HAL_INIT_STAGES_INIT_LLTT",
1448                 "HAL_INIT_STAGES_MISC01",
1449                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1450                 "HAL_INIT_STAGES_MAC",
1451                 "HAL_INIT_STAGES_BB",
1452                 "HAL_INIT_STAGES_RF",
1453                 "HAL_INIT_STAGES_MISC02",
1454                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1455                 "HAL_INIT_STAGES_INIT_SECURITY",
1456                 "HAL_INIT_STAGES_MISC11",
1457                 //"HAL_INIT_STAGES_RF_PS",
1458                 "HAL_INIT_STAGES_IQK",
1459                 "HAL_INIT_STAGES_PW_TRACK",
1460                 "HAL_INIT_STAGES_LCK",
1461                 "HAL_INIT_STAGES_MISC21",
1462                 //"HAL_INIT_STAGES_INIT_PABIAS",
1463                 #ifdef CONFIG_BT_COEXIST
1464                 "HAL_INIT_STAGES_BT_COEXIST",
1465                 #endif
1466                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1467                 "HAL_INIT_STAGES_INIT_HAL_DM",
1468                 "HAL_INIT_STAGES_MISC31",
1469                 "HAL_INIT_STAGES_END",
1470         };
1471
1472         int hal_init_profiling_i;
1473         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1474
1475         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1476                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1477
1478         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1479 #else
1480         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1481 #endif //DBG_HAL_INIT_PROFILING
1482
1483
1484
1485 _func_enter_;
1486
1487 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1488         if(Adapter->pwrctrlpriv.bkeepfwalive)
1489         {
1490                 _ps_open_RF(Adapter);
1491
1492                 if(pHalData->bIQKInitialized ){
1493                         rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1494                 }
1495                 else{
1496                         rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1497                         pHalData->bIQKInitialized = _TRUE;
1498                 }
1499                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
1500                 rtl8192c_PHY_LCCalibrate(Adapter);
1501
1502                 goto exit;
1503         }
1504
1505 //      pHalData->bMACFuncEnable = _FALSE;
1506         // Check if MAC has already power on. by tynli. 2011.05.27.
1507         val8 = rtw_read8(Adapter, REG_CR);
1508         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1509                          ("%s: REG_CR 0x100=0x%02x\n", __FUNCTION__, val8));
1510         //Fix 92DU-VC S3 hang with the reason is that secondary mac is not initialized.
1511         //0x100 value of first mac is 0xEA while 0x100 value of secondary is 0x00
1512         //by sherry 20111102
1513         if (val8 == 0xEA) {
1514                 pHalData->bMACFuncEnable = _FALSE;
1515         } else {
1516                 pHalData->bMACFuncEnable = _TRUE;
1517                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1518                                  ("%s: MAC has already power on\n", __FUNCTION__));
1519         }
1520
1521 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1522         status = _InitPowerOn(Adapter);
1523         if(status == _FAIL){
1524                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1525                 goto exit;
1526         }
1527
1528 #ifdef CONFIG_BT_COEXIST
1529         //
1530         // 2010/09/23 MH Accordgin to Alfred's siggestion. we need to enable SIC to prevent HW
1531         // to enter suspend mode automatically. If host does not send SOF every 3ms. Or under DTM
1532         // test with rtl8188cu selective suspend enabler filter driver, WIN host will trigger the device to
1533         // enter suspend mode after some test (unknow reason now). We need to prevent the case otherwise
1534         // the register will be 0xea and all TX/RX path stop accidently.
1535         //
1536         //
1537         // 2010/10/01 MH If the OS is XP, host will trigger USB device to enter D3 mode. In CU HW design
1538         // it will enter suspend mode automatically. In slim combo card, the BT clock will be cut off if HW
1539         // enter suspend mode. We need to seperate differet case.
1540         //
1541         if (BT_IsBtExist(Adapter))
1542         {
1543 #if 0
1544 #if OS_WIN_FROM_VISTA(OS_VERSION)
1545                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo win7/vista need not enable SIC\n"));
1546 #else
1547                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo XP enable SIC\n"));
1548                 // 2010/10/15 MH According to Alfre's description, e need to enable bit14 at first an then enable bit12.
1549                 // Otherwise, HW will enter debug mode and 8051 can not work. We need to stay at test mode to enable SIC.
1550                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT14);
1551                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT12);
1552 #endif
1553 #endif
1554         }
1555 #endif // CONFIG_BT_COEXIST
1556
1557 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1558         if (!pregistrypriv->wifi_spec) {
1559                 boundary = TX_PAGE_BOUNDARY;
1560         } else {
1561                 // for WMM
1562                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
1563         }
1564
1565         if (!pHalData->bMACFuncEnable)
1566         {
1567                 status =  InitLLTTable(Adapter, boundary);
1568                 if(status == _FAIL){
1569                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1570                         goto exit;
1571                 }
1572         }
1573
1574
1575 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1576         if(pHalData->bRDGEnable){
1577                 _InitRDGSetting(Adapter);
1578         }
1579
1580
1581 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1582 {
1583         status = rtl8723a_FirmwareDownload(Adapter);
1584         if(status != _SUCCESS)
1585         {
1586                 Adapter->bFWReady = _FALSE;
1587                 pHalData->fw_ractrl = _FALSE;
1588                 DBG_8723A("fw download fail!\n");
1589                 goto exit;
1590         }
1591         else
1592         {
1593                 Adapter->bFWReady = _TRUE;
1594                 pHalData->fw_ractrl = _TRUE;
1595                 DBG_8723A("fw download ok!\n");
1596         }
1597 }
1598
1599         rtl8723a_InitializeFirmwareVars(Adapter);
1600
1601         if(pwrctrlpriv->reg_rfoff == _TRUE){
1602                 pwrctrlpriv->rf_pwrstate = rf_off;
1603         }
1604
1605         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1606         // HW GPIO pin. Before PHY_RFConfig8192C.
1607         //HalDetectPwrDownMode(Adapter);
1608         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1609         //HalDetectSelectiveSuspendMode(Adapter);
1610
1611         // Set RF type for BB/RF configuration
1612         _InitRFType(Adapter);//->_ReadRFType()
1613
1614         // Save target channel
1615         // <Roger_Notes> Current Channel will be updated again later.
1616         pHalData->CurrentChannel = 6;//default set to 6
1617
1618
1619 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1620 #if (HAL_MAC_ENABLE == 1)
1621         status = PHY_MACConfig8723A(Adapter);
1622         if(status == _FAIL)
1623         {
1624                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
1625                 goto exit;
1626         }
1627 #endif
1628
1629
1630 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1631         //
1632         //d. Initialize BB related configurations.
1633         //
1634 #if (HAL_BB_ENABLE == 1)
1635         status = PHY_BBConfig8723A(Adapter);
1636         if(status == _FAIL)
1637         {
1638                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
1639                 goto exit;
1640         }
1641 #endif
1642
1643         //
1644         // 2011/11/15 MH Add for tx power by rate fine tune. We need to call the function after BB config.
1645         // Because the tx power by rate table is inited in BB config.
1646         //
1647 //      HAL_AdjustPwrIndexDiffRateOffset(Adapter);
1648 //      HAL_AdjustPwrIndexbyRegistry(Adapter);
1649
1650 #if 0
1651         // The FW command register update must after MAC and FW init ready.
1652         if (Adapter->bFWReady == TRUE)
1653         {
1654                 if(pDevice->RegUsbSS)
1655                 {
1656                         u1Byte          u1H2CSSRf[3]={0};
1657
1658                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_ON(u1H2CSSRf,  1);
1659                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf, 500);
1660
1661                         FillH2CCmd92C(Adapter, H2C_SELECTIVE_SUSPEND_ROF_CMD, 3, u1H2CSSRf);
1662                         RT_TRACE(COMP_INIT, DBG_LOUD,
1663                         ("SS Set H2C_CMD for FW detect GPIO time=%d\n", GET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf)));
1664                 }
1665                 else
1666                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Non-SS Driver detect GPIO by itself\n"));
1667         }
1668         else
1669         {
1670                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Adapter->bFWReady == FALSE\n"));
1671                 // 2011/02/11 MH If FW is not ready, we can not enter seecitve suspend mode, otherwise,
1672                 // We can not support GPIO/PBC detection by FW with selectiev suspend support.
1673                 pDevice->RegUsbSS = FALSE;
1674         }
1675 #endif
1676
1677
1678 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1679 #if (HAL_RF_ENABLE == 1)
1680         status = PHY_RFConfig8723A(Adapter);
1681         if(status == _FAIL)
1682         {
1683                 DBG_8723A("PHY_RFConfig8723A fault !!\n");
1684                 goto exit;
1685         }
1686
1687         //reducing 80M spur
1688         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
1689         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1690         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
1691         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1692
1693         //RFSW Control
1694         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   //0x804[14]=0
1695         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        //0x870[6:5]=b'11
1696         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); //0x860[6:5]=b'00
1697
1698         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __FUNCTION__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
1699
1700 #endif
1701
1702         //
1703         // Joseph Note: Keep RfRegChnlVal for later use.
1704         //
1705         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
1706         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
1707
1708
1709 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1710         if (!pHalData->bMACFuncEnable) {
1711                 _InitQueueReservedPage(Adapter);
1712                 _InitTxBufferBoundary(Adapter);
1713         }
1714         _InitQueuePriority(Adapter);
1715         _InitPageBoundary(Adapter);
1716         _InitTransferPageSize(Adapter);
1717
1718         // Get Rx PHY status in order to report RSSI and others.
1719         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1720
1721         _InitInterrupt(Adapter);
1722         hal_init_macaddr(Adapter);//set mac_address
1723         _InitNetworkType(Adapter);//set msr
1724         _InitWMACSetting(Adapter);
1725         _InitAdaptiveCtrl(Adapter);
1726         _InitEDCA(Adapter);
1727         _InitRateFallback(Adapter);
1728         _InitRetryFunction(Adapter);
1729         InitUsbAggregationSetting(Adapter);
1730         _InitOperationMode(Adapter);//todo
1731         rtl8723a_InitBeaconParameters(Adapter);
1732         rtl8723a_InitBeaconMaxError(Adapter, _TRUE);
1733
1734 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1735         _InitAdhocWorkaroundParams(Adapter);
1736 #endif
1737
1738 #if ENABLE_USB_DROP_INCORRECT_OUT
1739         _InitHardwareDropIncorrectBulkOut(Adapter);
1740 #endif
1741
1742 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1743         // Enable lifetime check for the four ACs
1744         rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
1745 #ifdef CONFIG_TX_MCAST2UNI
1746         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1747         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1748 #else   // CONFIG_TX_MCAST2UNI
1749         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1750         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1751 #endif  // CONFIG_TX_MCAST2UNI
1752 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1753
1754
1755 #ifdef CONFIG_LED
1756         _InitHWLed(Adapter);
1757 #endif //CONFIG_LED
1758
1759 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1760         _BBTurnOnBlock(Adapter);
1761         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1762
1763 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1764         invalidate_cam_all(Adapter);
1765
1766 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1767         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1768         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
1769
1770         rtl8723a_InitAntenna_Selection(Adapter);
1771
1772         // HW SEQ CTRL
1773         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1774         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1775
1776         //
1777         // Disable BAR, suggested by Scott
1778         // 2010.04.09 add by hpfan
1779         //
1780         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1781
1782         if(pregistrypriv->wifi_spec)
1783                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1784
1785         // Move by Neo for USB SS from above setp
1786         _RfPowerSave(Adapter);
1787
1788         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
1789                 // 2010/08/26 MH Merge from 8192CE.
1790                 //sherry masked that it has been done in _RfPowerSave
1791                 //20110927
1792                 //recovery for 8192cu and 9723Au 20111017
1793                 if(pwrctrlpriv->rf_pwrstate == rf_on)
1794                 {
1795                         if(pHalData->bIQKInitialized ){
1796                                 rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1797                         } else {
1798                                 rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1799                                 pHalData->bIQKInitialized = _TRUE;
1800                         }
1801
1802         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
1803                         rtl8192c_odm_CheckTXPowerTracking(Adapter);
1804
1805         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
1806                         rtl8192c_PHY_LCCalibrate(Adapter);
1807
1808 #ifdef CONFIG_BT_COEXIST
1809                         rtl8723a_SingleDualAntennaDetection(Adapter);
1810 #endif
1811                 }
1812
1813
1814 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1815 #ifdef USB_INTERFERENCE_ISSUE
1816  //fixed USB interface interference issue
1817         rtw_write8(Adapter, 0xfe40, 0xe0);
1818         rtw_write8(Adapter, 0xfe41, 0x8d);
1819         rtw_write8(Adapter, 0xfe42, 0x80);
1820         rtw_write32(Adapter,0x20c,0xfd0320);
1821 #if 1
1822         //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus
1823         if(!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188
1824         {
1825                 // 0xE6=0x94
1826                 rtw_write8(Adapter, 0xFE40, 0xE6);
1827                 rtw_write8(Adapter, 0xFE41, 0x94);
1828                 rtw_write8(Adapter, 0xFE42, 0x80);
1829
1830                 // 0xE0=0x19
1831                 rtw_write8(Adapter, 0xFE40, 0xE0);
1832                 rtw_write8(Adapter, 0xFE41, 0x19);
1833                 rtw_write8(Adapter, 0xFE42, 0x80);
1834
1835                 // 0xE5=0x91
1836                 rtw_write8(Adapter, 0xFE40, 0xE5);
1837                 rtw_write8(Adapter, 0xFE41, 0x91);
1838                 rtw_write8(Adapter, 0xFE42, 0x80);
1839
1840                 // 0xE2=0x81
1841                 rtw_write8(Adapter, 0xFE40, 0xE2);
1842                 rtw_write8(Adapter, 0xFE41, 0x81);
1843                 rtw_write8(Adapter, 0xFE42, 0x80);
1844
1845         }
1846
1847 #endif
1848 #endif //USB_INTERFERENCE_ISSUE
1849
1850 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1851 //      _InitPABias(Adapter);
1852
1853 #ifdef CONFIG_BT_COEXIST
1854 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1855         // Init BT hw config.
1856         BT_InitHwConfig(Adapter);
1857 #endif
1858
1859 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1860         rtl8723a_InitHalDm(Adapter);
1861
1862 #if 0
1863         // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1864         // 2010/05/18 MH For SE series only now. Init GPIO detect time
1865         if(pDevice->RegUsbSS)
1866         {
1867                 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n"));
1868                 GpioDetectTimerStart8192CU(Adapter);    // Disable temporarily
1869         }
1870
1871         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1872         // suspend mode automatically.
1873         HwSuspendModeEnable92Cu(Adapter, _FALSE);
1874 #endif
1875
1876 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1877         rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1878
1879         // 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause.
1880         if (((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000)) {
1881                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
1882                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __FUNCTION__));
1883         }
1884
1885 #ifdef CONFIG_XMIT_ACK
1886         //ack for xmit mgmt frames.
1887         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1888 #endif //CONFIG_XMIT_ACK
1889
1890         //_dbg_dump_macreg(padapter);
1891
1892 exit:
1893 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1894
1895         DBG_8723A("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1896
1897         #ifdef DBG_HAL_INIT_PROFILING
1898         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1899
1900         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1901                 DBG_8723A("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1902                         , hal_init_stages_str[hal_init_profiling_i]
1903                         , hal_init_stages_timestamp[hal_init_profiling_i]
1904                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1905                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1906                 );
1907         }
1908         #endif
1909
1910 _func_exit_;
1911
1912         return status;
1913 }
1914
1915
1916 #define SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1917 #ifdef SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1918 VOID
1919 phy_SsPwrSwitch92CU(
1920         PADAPTER                        Adapter,
1921         rt_rf_power_state       eRFPowerState,
1922         int bRegSSPwrLvl
1923         )
1924 {
1925         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1926         u8                              value8;
1927
1928         switch( eRFPowerState )
1929         {
1930                 case rf_on:
1931                         if (bRegSSPwrLvl == 1)
1932                         {
1933                                 // 1. Enable MAC Clock. Can not be enabled now.
1934                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1935
1936                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1937                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1938                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1939
1940                                 // 3. restore BB, AFE control register.
1941                                 //RF
1942                                 if (pHalData->rf_type ==  RF_2T2R)
1943                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1944                                 else
1945                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1946                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1947                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1948
1949                                 //AFE
1950                                 //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]);
1951                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] );
1952                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 );
1953                                 if (pHalData->rf_type ==  RF_2T2R)
1954                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1955                                 else if (pHalData->rf_type ==  RF_1T1R)
1956                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1957
1958                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1959                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1960                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
1961                                 if (pHalData->rf_type ==  RF_2T2R)
1962                                 {
1963                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
1964                                 }
1965                         }
1966                         else            // Level 2 or others.
1967                         {
1968                                 //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
1969                                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
1970
1971                                 // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
1972                                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
1973                                 rtw_mdelay_os(1);
1974
1975                                 // 1. Enable MAC Clock. Can not be enabled now.
1976                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1977
1978                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1979                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1980                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1981
1982                                 // 3. restore BB, AFE control register.
1983                                 //RF
1984                                 if (pHalData->rf_type ==  RF_2T2R)
1985                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1986                                 else
1987                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1988                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1989                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1990
1991                                 //AFE
1992                                 if (pHalData->rf_type ==  RF_2T2R)
1993                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1994                                 else if (pHalData->rf_type ==  RF_1T1R)
1995                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1996
1997                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1998                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1999                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
2000                                 if (pHalData->rf_type ==  RF_2T2R)
2001                                 {
2002                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
2003                                 }
2004
2005                                 // 5. gated MAC Clock
2006                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2007                                 //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)|(BIT3));
2008
2009                                 {
2010                                         //u8                    eRFPath = RF_PATH_A,value8 = 0, retry = 0;
2011                                         u8              bytetmp;
2012                                         //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2013                                         // 2010/08/12 MH Add for B path under SS test.
2014                                         //if (pHalData->RF_Type ==  RF_2T2R)
2015                                                 //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2016
2017                                         bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
2018                                         rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
2019
2020                                         rtw_mdelay_os(10);
2021
2022                                         // Set BB reset at first
2023                                         rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16
2024
2025                                         // Enable TX
2026                                         rtw_write8(Adapter, REG_TXPAUSE, 0x0);
2027                                 }
2028                                 //CardSelectiveSuspendLeave(Adapter);
2029                         }
2030
2031                         break;
2032
2033                 case rf_sleep:
2034                 case rf_off:
2035                                 value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
2036                                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2037                                         value8 &= ~(BIT0);
2038                                 else
2039                                         value8 &= ~(BIT0|BIT3);
2040                                 if (bRegSSPwrLvl == 1)
2041                                 {
2042                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
2043                                         // Disable RF and BB only for SelectSuspend.
2044
2045                                         // 1. Set BB/RF to shutdown.
2046                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2047                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2048                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2049                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2050                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2051                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2052                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2053                                         if (pHalData->rf_type ==  RF_2T2R)
2054                                         {
2055                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2056                                         }
2057                                         else if (pHalData->rf_type ==  RF_1T1R)
2058                                         {
2059                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2060                                         }
2061                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2062                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2063
2064                                         // 2 .AFE control register to power down. bit[30:22]
2065                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2066                                         if (pHalData->rf_type ==  RF_2T2R)
2067                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2068                                         else if (pHalData->rf_type ==  RF_1T1R)
2069                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2070
2071                                         // 3. issue 3-wire command that RF set to power down.
2072                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2073                                         if (pHalData->rf_type ==  RF_2T2R)
2074                                         {
2075                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2076                                         }
2077
2078                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2079                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2080
2081                                         // 5. gated MAC Clock
2082                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2083                                 }
2084                                 else    // Level 2 or others.
2085                                 {
2086                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
2087                                         {
2088                                                 u8                      eRFPath = RF_PATH_A,value8 = 0;
2089                                                 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2090                                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2091                                                 // 2010/08/12 MH Add for B path under SS test.
2092                                                 //if (pHalData->RF_Type ==  RF_2T2R)
2093                                                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2094
2095                                                 value8 |= APSDOFF;
2096                                                 rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2097
2098                                                 // After switch APSD, we need to delay for stability
2099                                                 rtw_mdelay_os(10);
2100
2101                                                 // Set BB reset at first
2102                                                 value8 = 0 ;
2103                                                 value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2104                                                 rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2105                                         }
2106
2107                                         // Disable RF and BB only for SelectSuspend.
2108
2109                                         // 1. Set BB/RF to shutdown.
2110                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2111                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2112                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2113                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2114                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2115                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2116                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2117                                         if (pHalData->rf_type ==  RF_2T2R)
2118                                         {
2119                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2120                                         }
2121                                         else if (pHalData->rf_type ==  RF_1T1R)
2122                                         {
2123                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2124                                         }
2125                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2126                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2127
2128                                         // 2 .AFE control register to power down. bit[30:22]
2129                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2130                                         if (pHalData->rf_type ==  RF_2T2R)
2131                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2132                                         else if (pHalData->rf_type ==  RF_1T1R)
2133                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2134
2135                                         // 3. issue 3-wire command that RF set to power down.
2136                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2137                                         if (pHalData->rf_type ==  RF_2T2R)
2138                                         {
2139                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2140                                         }
2141
2142                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2143                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2144
2145                                         // 2010/10/13 MH/Isaachsu exchange sequence.
2146                                         //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2147                                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2148                                         rtw_mdelay_os(1);
2149
2150                                         // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2151                                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
2152
2153                                         // 5. gated MAC Clock
2154                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2155                                         //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)& ~(BIT3))
2156
2157                                         //CardSelectiveSuspendEnter(Adapter);
2158                                 }
2159
2160                         break;
2161
2162                 default:
2163                         break;
2164         }
2165
2166 }       // phy_PowerSwitch92CU
2167
2168 void _ps_open_RF(_adapter *padapter) {
2169         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2170         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
2171 }
2172
2173 void _ps_close_RF(_adapter *padapter){
2174         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2175         phy_SsPwrSwitch92CU(padapter, rf_off, 1);
2176 }
2177 #endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU
2178
2179
2180
2181 static VOID
2182 _DisableGPIO(
2183         PADAPTER        Adapter
2184         )
2185 {
2186 /***************************************
2187 j. GPIO_PIN_CTRL 0x44[31:0]=0x000               //
2188 k. Value = GPIO_PIN_CTRL[7:0]
2189 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
2190 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
2191 n. LEDCFG 0x4C[15:0] = 0x8080
2192 ***************************************/
2193         u8      value8;
2194         u16     value16;
2195         u32     value32;
2196
2197         //1. Disable GPIO[7:0]
2198         rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
2199         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
2200         value8 = (u8) (value32&0x000000FF);
2201         value32 |= ((value8<<8) | 0x00FF0000);
2202         rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
2203
2204         //2. Disable GPIO[10:8]
2205         rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
2206             value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
2207         value8 = (u8) (value16&0x000F);
2208         value16 |= ((value8<<4) | 0x0780);
2209         rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
2210
2211         //3. Disable LED0 & 1
2212         rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
2213
2214         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
2215
2216 } //end of _DisableGPIO()
2217
2218 static VOID
2219 _ResetFWDownloadRegister(
2220  PADAPTER                       Adapter
2221         )
2222 {
2223         u32     value32;
2224
2225         value32 = rtw_read32(Adapter, REG_MCUFWDL);
2226         value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
2227         rtw_write32(Adapter, REG_MCUFWDL, value32);
2228         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
2229 }
2230
2231
2232 static int
2233 _DisableRF_AFE(
2234  PADAPTER                       Adapter
2235         )
2236 {
2237         int             rtStatus = _SUCCESS;
2238         u32                     pollingCount = 0;
2239         u8                      value8;
2240
2241         //disable RF/ AFE AD/DA
2242         value8 = APSDOFF;
2243         rtw_write8(Adapter, REG_APSD_CTRL, value8);
2244
2245
2246 #if (RTL8192CU_ASIC_VERIFICATION)
2247
2248         do
2249         {
2250                 if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){
2251                         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n"));
2252                         break;
2253                 }
2254
2255                 if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
2256                         //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n"));
2257                         return _FAIL;
2258                 }
2259
2260         }while(_TRUE);
2261
2262 #endif
2263
2264         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n"));
2265         return rtStatus;
2266
2267 }
2268
2269 static VOID
2270 _ResetBB(
2271  PADAPTER                       Adapter
2272         )
2273 {
2274         u16     value16;
2275
2276         //reset BB
2277         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2278         value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
2279         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2280         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
2281 }
2282
2283 static VOID
2284 _ResetMCU(
2285  PADAPTER                       Adapter
2286         )
2287 {
2288         u16     value16;
2289
2290         // reset MCU
2291         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2292         value16 &= ~FEN_CPUEN;
2293         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2294         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
2295 }
2296
2297 static VOID
2298 _DisableMAC_AFE_PLL(
2299  PADAPTER                       Adapter
2300         )
2301 {
2302         u32     value32;
2303
2304         //disable MAC/ AFE PLL
2305         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2306         value32 |= APDM_MAC;
2307         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2308
2309         value32 |= APFM_OFF;
2310         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2311         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
2312 }
2313
2314 static VOID
2315 _AutoPowerDownToHostOff(
2316         PADAPTER                Adapter
2317         )
2318 {
2319         u32                     value32;
2320         rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
2321
2322         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2323
2324         value32 |= APDM_HOST;//card disable
2325         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2326         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
2327
2328         // set USB suspend
2329         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2330         value32 &= ~AFSM_PCIE;
2331         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2332
2333 }
2334
2335 static VOID
2336 _SetUsbSuspend(
2337  PADAPTER                       Adapter
2338         )
2339 {
2340         u32                     value32;
2341
2342         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2343
2344         // set USB suspend
2345         value32 |= AFSM_HSUS;
2346         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2347
2348         //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
2349         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
2350
2351 }
2352
2353 static VOID
2354 _DisableRFAFEAndResetBB(
2355  PADAPTER                       Adapter
2356         )
2357 {
2358 /**************************************
2359 a.      TXPAUSE 0x522[7:0] = 0xFF             //Pause MAC TX queue
2360 b.      RF path 0 offset 0x00 = 0x00            // disable RF
2361 c.      APSD_CTRL 0x600[7:0] = 0x40
2362 d.      SYS_FUNC_EN 0x02[7:0] = 0x16            //reset BB state machine
2363 e.      SYS_FUNC_EN 0x02[7:0] = 0x14            //reset BB state machine
2364 ***************************************/
2365         u8 eRFPath = 0,value8 = 0;
2366         rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2367         PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2368
2369         value8 |= APSDOFF;
2370         rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2371
2372         value8 = 0 ;
2373         value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2374         rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2375
2376         value8 &=( ~FEN_BB_GLB_RSTn );
2377         rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
2378
2379         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
2380 }
2381
2382 static VOID
2383 _ResetDigitalProcedure1(
2384         PADAPTER                        Adapter,
2385         bool                            bWithoutHWSM
2386         )
2387 {
2388
2389         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2390
2391         if(pHalData->FirmwareVersion <=  0x20){
2392                 #if 0
2393                 /*****************************
2394                 f.      SYS_FUNC_EN 0x03[7:0]=0x54              // reset MAC register, DCORE
2395                 g.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2396                 ******************************/
2397                 u4Byte  value32 = 0;
2398                 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
2399                 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
2400                 #else
2401                 /*****************************
2402                 f.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2403                 g.      SYS_FUNC_EN 0x02[10]= 0                 // reset MCU register, (8051 reset)
2404                 h.      SYS_FUNC_EN 0x02[15-12]= 5              // reset MAC register, DCORE
2405                 i.     SYS_FUNC_EN 0x02[10]= 1                  // enable MCU register, (8051 enable)
2406                 ******************************/
2407                         u16 valu16 = 0;
2408                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2409
2410                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2411                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
2412
2413                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
2414                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
2415
2416                         #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2417                         {
2418                                 u8 val;
2419                                 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2420                                         DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2421                         }
2422                         #endif
2423
2424
2425                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2426                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
2427
2428
2429                 #endif
2430         }
2431         else{
2432                 u8 retry_cnts = 0;
2433
2434                 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
2435                 { //IF fw in RAM code, do reset
2436
2437                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2438                         if(Adapter->bFWReady){
2439                                 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
2440                                 // HRCV INT to influence 8051 reset.
2441                                 rtw_write8(Adapter, REG_FWIMR, 0x20);
2442
2443                                 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
2444
2445                                 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
2446                                 {
2447                                         rtw_udelay_os(50);//PlatformStallExecution(50);//us
2448                                 }
2449
2450                                 if(retry_cnts >= 100){
2451                                         DBG_8723A("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
2452                                         // if 8051 reset fail we trigger GPIO 0 for LA
2453                                         //PlatformEFIOWrite4Byte(       Adapter,
2454                                         //                                              REG_GPIO_PIN_CTRL,
2455                                         //                                              0x00010100);
2456                                         // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
2457                                         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50);   //Reset MAC and Enable 8051
2458                                         rtw_mdelay_os(10);
2459                                 }
2460                                 else {
2461                                         //DBG_8723A("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
2462                                 }
2463                         }
2464                         else {
2465                                 DBG_8723A("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
2466                         }
2467                 }
2468                 else{
2469                         //DBG_8723A("%s =====> 8051 in ROM.\n", __FUNCTION__);
2470                 }
2471
2472                 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2473                 {
2474                         u8 val;
2475                         if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2476                                 DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2477                 }
2478                 #endif
2479
2480                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54);   //Reset MAC and Enable 8051
2481         }
2482
2483         // Clear rpwm value for initial toggle bit trigger.
2484         rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
2485
2486         if(bWithoutHWSM){
2487         /*****************************
2488                 Without HW auto state machine
2489         g.      SYS_CLKR 0x08[15:0] = 0x30A3                    //disable MAC clock
2490         h.      AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2491         i.      AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2492         j.      SYS_ISO_CTRL 0x00[7:0] = 0xF9                   // isolated digital to PON
2493         ******************************/
2494                 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
2495                 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
2496                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2497                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
2498                 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
2499         }
2500         else
2501         {
2502                 // Disable all RF/BB power
2503                 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2504         }
2505         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
2506
2507 }
2508
2509 static VOID
2510 _ResetDigitalProcedure2(
2511         PADAPTER                        Adapter
2512 )
2513 {
2514 /*****************************
2515 k.      SYS_FUNC_EN 0x03[7:0] = 0x44                    // disable ELDR runction
2516 l.      SYS_CLKR 0x08[15:0] = 0x3083                    // disable ELDR clock
2517 m.      SYS_ISO_CTRL 0x01[7:0] = 0x83                   // isolated ELDR to PON
2518 ******************************/
2519         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
2520         //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
2521         //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
2522
2523         rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
2524         rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
2525 }
2526
2527 static VOID
2528 _DisableAnalog(
2529  PADAPTER                       Adapter,
2530  bool                   bWithoutHWSM
2531         )
2532 {
2533         u16 value16 = 0;
2534         u8 value8=0;
2535         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2536
2537         if(bWithoutHWSM){
2538         /*****************************
2539         n.      LDOA15_CTRL 0x20[7:0] = 0x04            // disable A15 power
2540         o.      LDOV12D_CTRL 0x21[7:0] = 0x54           // disable digital core power
2541         r.      When driver call disable, the ASIC will turn off remaining clock automatically
2542         ******************************/
2543
2544                 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
2545                 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
2546
2547                 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
2548                 value8 &= (~LDV12_EN);
2549                 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
2550                 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
2551         }
2552
2553 /*****************************
2554 h.      SPS0_CTRL 0x11[7:0] = 0x23                      //enter PFM mode
2555 i.      APS_FSMCO 0x04[15:0] = 0x4802           // set USB suspend
2556 ******************************/
2557
2558
2559         value8 = 0x23;
2560         if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2561                 value8 |= BIT3;
2562
2563         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2564
2565
2566         if(bWithoutHWSM)
2567         {
2568                 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
2569                 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
2570                 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
2571                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2572         }
2573         else
2574         {
2575                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2576         }
2577
2578         rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
2579
2580         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2581
2582  #if 0
2583         //tynli_test for suspend mode.
2584         if(!bWithoutHWSM){
2585                 rtw_write8(Adapter, 0xfe10, 0x19);
2586         }
2587 #endif
2588
2589         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
2590 }
2591
2592 static void rtl8723au_hw_power_down(_adapter *padapter)
2593 {
2594         u8      u1bTmp;
2595
2596         DBG_8723A("PowerDownRTL8723U\n");
2597
2598
2599         // 1. Run Card Disable Flow
2600         // Done before this function call.
2601
2602         // 2. 0x04[16] = 0                      // reset WLON
2603         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
2604         rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
2605
2606         // 3. 0x04[12:11] = 2b'11 // enable suspend
2607         // Done before this function call.
2608
2609         // 4. 0x04[15] = 1                      // enable PDN
2610         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
2611         rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
2612 }
2613
2614 //
2615 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
2616 // First created by tynli. 2011.01.28.
2617 //
2618 VOID
2619 CardDisableRTL8723U(
2620         PADAPTER                        Adapter
2621 )
2622 {
2623         u8              u1bTmp;
2624 //      PMGNT_INFO      pMgntInfo       = &(Adapter->MgntInfo);
2625
2626         DBG_8723A("CardDisableRTL8723U\n");
2627
2628         // USB-MF Card Disable Flow
2629         // 1. Run LPS WL RFOFF flow
2630         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_enter_lps_flow);
2631
2632         // 2. 0x1F[7:0] = 0             // turn off RF
2633         rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2634
2635         //      ==== Reset digital sequence   ======
2636         if((rtw_read8(Adapter, REG_MCUFWDL)&BIT7) &&
2637                 Adapter->bFWReady) //8051 RAM code
2638         {
2639                 rtl8723a_FirmwareSelfReset(Adapter);
2640         }
2641
2642         // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
2643         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2644         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, (u1bTmp&(~BIT2)));
2645
2646         // g.   MCUFWDL 0x80[1:0]=0                             // reset MCU ready status
2647         rtw_write8(Adapter, REG_MCUFWDL, 0x00);
2648
2649         //      ==== Reset digital sequence end ======
2650 //      if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) )
2651         {
2652                 // Card disable power action flow
2653                 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_disable_flow);
2654         }
2655
2656         // Reset MCU IO Wrapper, added by Roger, 2011.08.30.
2657         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2658         rtw_write8(Adapter, REG_RSV_CTRL+1, (u1bTmp&(~BIT0)));
2659         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2660         rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp|BIT0);
2661
2662         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2663         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2664
2665 }
2666
2667
2668 u32 rtl8723au_hal_deinit(PADAPTER padapter)
2669 {
2670         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(padapter);
2671
2672
2673         DBG_8723A("==> %s\n", __FUNCTION__);
2674
2675 #ifdef CONFIG_BT_COEXIST
2676         BT_HaltProcess(padapter);
2677 #endif
2678         // 2011/02/18 To Fix RU LNA  power leakage problem. We need to execute below below in
2679         // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
2680         // IC. Accord to johnny's opinion, only RU need the support.
2681         CardDisableRTL8723U(padapter);
2682
2683         return _SUCCESS;
2684 }
2685
2686
2687 unsigned int rtl8723au_inirp_init(PADAPTER Adapter)
2688 {
2689         u8 i;
2690         struct recv_buf *precvbuf;
2691         uint    status;
2692         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2693         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2694         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2695         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2696 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2697         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2698         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2699 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2700
2701 _func_enter_;
2702
2703         _read_port = pintfhdl->io_ops._read_port;
2704
2705         status = _SUCCESS;
2706
2707         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2708
2709         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2710
2711         //issue Rx irp to receive data
2712         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2713         for(i=0; i<NR_RECVBUFF; i++)
2714         {
2715                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2716                 {
2717                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2718                         status = _FAIL;
2719                         goto exit;
2720                 }
2721
2722                 precvbuf++;
2723                 precvpriv->free_recv_buf_queue_cnt--;
2724         }
2725
2726 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2727         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2728         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2729         {
2730                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2731                 status = _FAIL;
2732         }
2733         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2734         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2735         pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2736         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2737 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2738
2739 exit:
2740
2741         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2742
2743 _func_exit_;
2744
2745         return status;
2746
2747 }
2748
2749 unsigned int rtl8723au_inirp_deinit(PADAPTER Adapter)
2750 {
2751 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2752         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2753         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2754 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2755         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2756
2757         rtw_read_port_cancel(Adapter);
2758 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2759         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2760         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2761         pHalData->IntrMask[0]=0x0;
2762         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2763         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2764 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2765         return _SUCCESS;
2766 }
2767
2768
2769 static u32
2770 _GetChannelGroup(
2771         u32     channel
2772         )
2773 {
2774         //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2775
2776         if(channel < 3){        // Channel 1~3
2777                 return 0;
2778         }
2779         else if(channel < 9){ // Channel 4~9
2780                 return 1;
2781         }
2782
2783         return 2;                               // Channel 10~14
2784 }
2785
2786
2787 //-------------------------------------------------------------------
2788 //
2789 //      EEPROM/EFUSE Content Parsing
2790 //
2791 //-------------------------------------------------------------------
2792 static void
2793 _ReadIDs(
2794         PADAPTER        Adapter,
2795         u8*             PROMContent,
2796         bool            AutoloadFail
2797         )
2798 {
2799         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2800
2801         if(_FALSE == AutoloadFail){
2802                 // VID, PID
2803                 pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
2804                 pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
2805
2806                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2807                 pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
2808                 pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
2809
2810         }
2811         else{
2812                 pHalData->EEPROMVID      = EEPROM_Default_VID;
2813                 pHalData->EEPROMPID      = EEPROM_Default_PID;
2814
2815                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2816                 pHalData->EEPROMCustomerID      = EEPROM_Default_CustomerID;
2817                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2818
2819         }
2820
2821         // For customized behavior.
2822         if((pHalData->EEPROMVID == 0x103C) || (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2823                 pHalData->CustomerID = RT_CID_819x_HP;
2824
2825         //      Decide CustomerID according to VID/DID or EEPROM
2826         switch(pHalData->EEPROMCustomerID)
2827         {
2828                 case EEPROM_CID_DEFAULT:
2829                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2830                                 pHalData->CustomerID = RT_CID_DLINK;
2831                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2832                                 pHalData->CustomerID = RT_CID_DLINK;
2833                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2834                                 pHalData->CustomerID = RT_CID_DLINK;
2835                         break;
2836                 case EEPROM_CID_WHQL:
2837 /*
2838                         Adapter->bInHctTest = TRUE;
2839
2840                         pMgntInfo->bSupportTurboMode = FALSE;
2841                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2842
2843                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2844                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2845                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2846
2847                         pMgntInfo->keepAliveLevel = 0;
2848
2849                         Adapter->bUnloadDriverwhenS3S4 = FALSE;
2850 */
2851                         break;
2852                 default:
2853                         pHalData->CustomerID = RT_CID_DEFAULT;
2854                         break;
2855
2856         }
2857
2858         MSG_8723A("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
2859         MSG_8723A("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
2860         MSG_8723A("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
2861         MSG_8723A("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
2862
2863         MSG_8723A("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
2864
2865 }
2866
2867
2868 static VOID
2869 _ReadMACAddress(
2870         PADAPTER        Adapter,
2871         u8*             PROMContent,
2872         bool            AutoloadFail
2873         )
2874 {
2875         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2876
2877         if(_FALSE == AutoloadFail){
2878                 //Read Permanent MAC address and set value to hardware
2879                 memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
2880         }
2881         else{
2882                 //Random assigh MAC address
2883                 u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
2884                 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2885                 memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
2886         }
2887         DBG_8723A("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
2888         //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
2889         //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
2890
2891 }
2892
2893 static VOID
2894 _ReadBoardType(
2895         PADAPTER        Adapter,
2896         u8*             PROMContent,
2897         bool            AutoloadFail
2898         )
2899 {
2900         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2901         u32                     value32;
2902         u8                      boardType = BOARD_USB_DONGLE;
2903
2904         if(AutoloadFail){
2905                 if(IS_8723_SERIES(pHalData->VersionID))
2906                         pHalData->rf_type = RF_1T1R;
2907                 else
2908                         pHalData->rf_type = RF_2T2R;
2909
2910                 pHalData->BoardType = boardType;
2911                 return;
2912         }
2913
2914         boardType = PROMContent[EEPROM_NORMAL_BoardType];
2915         boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5]
2916         boardType >>= 5;
2917
2918         pHalData->BoardType = boardType;
2919         MSG_8723A("_ReadBoardType(%x)\n",pHalData->BoardType);
2920
2921         if (boardType == BOARD_USB_High_PA)
2922                 pHalData->ExternalPA = 1;
2923 }
2924
2925
2926 static VOID
2927 _ReadLEDSetting(
2928         PADAPTER        Adapter,
2929         u8*             PROMContent,
2930         bool            AutoloadFail
2931         )
2932 {
2933         struct led_priv *pledpriv = &(Adapter->ledpriv);
2934         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2935 #ifdef CONFIG_SW_LED
2936         pledpriv->bRegUseLed = _TRUE;
2937
2938         //
2939         // Led mode
2940         //
2941         switch(pHalData->CustomerID)
2942         {
2943                 case RT_CID_DEFAULT:
2944                         pledpriv->LedStrategy = SW_LED_MODE1;
2945                         pledpriv->bRegUseLed = _TRUE;
2946                         break;
2947
2948                 case RT_CID_819x_HP:
2949                         pledpriv->LedStrategy = SW_LED_MODE6;
2950                         break;
2951
2952                 default:
2953                         pledpriv->LedStrategy = SW_LED_MODE1;
2954                         break;
2955         }
2956
2957         if( BOARD_MINICARD == pHalData->BoardType )
2958         {
2959                 pledpriv->LedStrategy = SW_LED_MODE6;
2960         }
2961         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2962 #else // HW LED
2963         pledpriv->LedStrategy = HW_LED;
2964 #endif //CONFIG_SW_LED
2965 }
2966
2967 static VOID
2968 _ReadThermalMeter(
2969         PADAPTER        Adapter,
2970         u8*     PROMContent,
2971         bool            AutoloadFail
2972         )
2973 {
2974         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2975         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2976         u8      tempval;
2977
2978         //
2979         // ThermalMeter from EEPROM
2980         //
2981         if(!AutoloadFail)
2982                 tempval = PROMContent[EEPROM_THERMAL_METER];
2983         else
2984                 tempval = EEPROM_Default_ThermalMeter;
2985
2986         pHalData->EEPROMThermalMeter = (tempval&0x1f);  //[4:0]
2987
2988         if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
2989                 pdmpriv->bAPKThermalMeterIgnore = _TRUE;
2990
2991 #if 0
2992         if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
2993                 pHalData->EEPROMThermalMeter = 0x12;
2994 #endif
2995
2996         pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
2997
2998         //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
2999
3000 }
3001
3002 static VOID
3003 _ReadRFSetting(
3004         PADAPTER        Adapter,
3005         u8*     PROMContent,
3006         bool            AutoloadFail
3007         )
3008 {
3009 }
3010
3011
3012 #if 0
3013 static VOID
3014 readAntennaDiversity(
3015         PADAPTER        pAdapter,
3016         u8                      *hwinfo,
3017         bool            AutoLoadFail
3018         )
3019 {
3020
3021         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3022         struct registry_priv    *registry_par = &pAdapter->registrypriv;
3023
3024         if(!AutoLoadFail)
3025         {
3026                 // Antenna Diversity setting.
3027                 if(registry_par->antdiv_cfg == 2) // 2: From Efuse
3028                         pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
3029                 else
3030                         pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON,
3031
3032                 DBG_8723A("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
3033
3034                 //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
3035                 //      pHalData->AntDivCfg = 0;
3036         }
3037         else
3038         {
3039                 pHalData->AntDivCfg = 0;
3040         }
3041
3042 }
3043 #endif
3044 // Read HW power down mode selection
3045 static void _ReadPSSetting(PADAPTER Adapter, u8*PROMContent, u8 AutoloadFail)
3046 {
3047         if(AutoloadFail){
3048                 Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
3049                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
3050         }
3051         else    {
3052                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3053                         Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
3054                 //else
3055                         //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
3056
3057
3058                 //hw power down mode selection , 0:rf-off / 1:power down
3059
3060                 if(Adapter->registrypriv.hwpdn_mode==2)
3061                         Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
3062                 else
3063                         Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
3064
3065                 // decide hw if support remote wakeup function
3066                 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
3067                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
3068
3069                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3070                         //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
3071
3072                 DBG_8723A("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
3073                 Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
3074
3075                 DBG_8723A("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
3076
3077         }
3078
3079 }
3080
3081
3082
3083
3084
3085
3086 VOID
3087 Hal_EfuseParsePIDVID_8723AU(
3088         PADAPTER                pAdapter,
3089         u8*                     hwinfo,
3090         bool                    AutoLoadFail
3091         )
3092 {
3093         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3094
3095         if(AutoLoadFail)
3096         {
3097                 pHalData->EEPROMVID = 0;
3098                 pHalData->EEPROMPID = 0;
3099         }
3100         else
3101         {
3102                         // VID, PID
3103                 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723AU]);
3104                 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723AU]);
3105
3106         }
3107
3108         MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
3109         MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
3110 }
3111
3112
3113 static void
3114 Hal_EfuseParseMACAddr_8723AU(
3115         PADAPTER                padapter,
3116         u8*                     hwinfo,
3117         bool                    AutoLoadFail
3118         )
3119 {
3120         u16                     i, usValue;
3121         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
3122         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3123
3124         if (AutoLoadFail)
3125         {
3126 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
3127                 for (i=0; i<6; i++)
3128                         pEEPROM->mac_addr[i] = sMacAddr[i];
3129         }
3130         else
3131         {
3132                 //Read Permanent MAC address
3133 #if 1
3134                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], ETH_ALEN);
3135 #else
3136                 for(i=0; i<6; i+=2)
3137                 {
3138                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
3139                         *((u16*)(&pEEPROM->mac_addr[i])) = usValue;
3140                 }
3141 #endif
3142         }
3143 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
3144
3145         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
3146                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address=%02x:%02x:%02x:%02x:%02x:%02x\n",
3147                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3148                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3149                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
3150 }
3151
3152
3153 #ifdef CONFIG_EFUSE_CONFIG_FILE
3154 static u32 Hal_readPGDataFromConfigFile(
3155         PADAPTER        padapter)
3156 {
3157         u32 i;
3158         struct file *fp;
3159         mm_segment_t fs;
3160         u8 temp[3];
3161         loff_t pos = 0;
3162         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3163         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
3164
3165
3166         temp[2] = 0; // add end of string '\0'
3167
3168         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
3169         if (IS_ERR(fp)) {
3170                 pEEPROM->bloadfile_fail_flag= _TRUE;
3171                 DBG_8723A("Error, Efuse configure file doesn't exist.\n");
3172                 return _FAIL;
3173         }
3174
3175         fs = get_fs();
3176         set_fs(KERNEL_DS);
3177
3178         DBG_8723A("Efuse configure file:\n");
3179         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
3180                 vfs_read(fp, temp, 2, &pos);
3181                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
3182                 pos += 1; // Filter the space character
3183                 DBG_8723A("%02X \n", PROMContent[i]);
3184         }
3185         DBG_8723A("\n");
3186         set_fs(fs);
3187
3188         filp_close(fp, NULL);
3189
3190         pEEPROM->bloadfile_fail_flag= _FALSE;
3191         return _SUCCESS;
3192 }
3193
3194
3195 static void
3196 Hal_ReadMACAddrFromFile_8723AU(
3197         PADAPTER                padapter
3198         )
3199 {
3200         u32 i;
3201         struct file *fp;
3202         mm_segment_t fs;
3203         u8 source_addr[18];
3204         loff_t pos = 0;
3205         u32 curtime = rtw_get_current_time();
3206         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3207         u8 *head, *end;
3208
3209         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
3210         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
3211
3212         memset(source_addr, 0, 18);
3213         memset(pEEPROM->mac_addr, 0, ETH_ALEN);
3214
3215         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
3216         if (IS_ERR(fp)) {
3217                 pEEPROM->bloadmac_fail_flag = _TRUE;
3218                 DBG_8723A("Error, wifi mac address file doesn't exist.\n");
3219         } else {
3220                 fs = get_fs();
3221                 set_fs(KERNEL_DS);
3222
3223                 DBG_8723A("wifi mac address:\n");
3224                 vfs_read(fp, source_addr, 18, &pos);
3225                 source_addr[17] = ':';
3226
3227                 head = end = source_addr;
3228                 for (i=0; i<ETH_ALEN; i++) {
3229                         while (end && (*end != ':') )
3230                                 end++;
3231
3232                         if (end && (*end == ':') )
3233                                 *end = '\0';
3234
3235                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
3236
3237                         if (end) {
3238                                 end++;
3239                                 head = end;
3240                         }
3241                         DBG_8723A("%02x \n", pEEPROM->mac_addr[i]);
3242                 }
3243                 DBG_8723A("\n");
3244                 set_fs(fs);
3245
3246                 filp_close(fp, NULL);
3247         }
3248
3249         if ((!memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
3250             (!memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
3251                 pEEPROM->mac_addr[0] = 0x00;
3252                 pEEPROM->mac_addr[1] = 0xe0;
3253                 pEEPROM->mac_addr[2] = 0x4c;
3254                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
3255                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
3256                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
3257         }
3258
3259         pEEPROM->bloadmac_fail_flag = _FALSE;
3260
3261          DBG_8723A("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
3262                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3263                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3264                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
3265 }
3266 #endif //CONFIG_EFUSE_CONFIG_FILE
3267
3268
3269 static VOID
3270 readAdapterInfo(
3271         PADAPTER        padapter
3272         )
3273 {
3274         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3275         //PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3276         u8                      hwinfo[HWSET_MAX_SIZE];
3277
3278 #ifdef CONFIG_EFUSE_CONFIG_FILE
3279         Hal_readPGDataFromConfigFile(padapter);
3280 #else //CONFIG_EFUSE_CONFIG_FILE
3281         Hal_InitPGData(padapter, hwinfo);
3282 #endif  //CONFIG_EFUSE_CONFIG_FILE
3283         Hal_EfuseParseIDCode(padapter, hwinfo);
3284         Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3285         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3286 #ifdef CONFIG_EFUSE_CONFIG_FILE
3287         Hal_ReadMACAddrFromFile_8723AU(padapter);
3288 #else //CONFIG_EFUSE_CONFIG_FILE
3289         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3290 #endif
3291         Hal_EfuseParseTxPowerInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3292         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3293         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3294
3295         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3296         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3297         _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3298 //      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3299 //      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3300         Hal_EfuseParseAntennaDiversity(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3301
3302         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3303         Hal_EfuseParseCustomerID(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3304         Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3305         Hal_EfuseParseXtal_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3306         //
3307         // The following part initialize some vars by PG info.
3308         //
3309         Hal_InitChannelPlan(padapter);
3310
3311
3312
3313         //hal_CustomizedBehavior_8723U(Adapter);
3314
3315 //      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
3316         DBG_8723A("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
3317 }
3318
3319 static void _ReadPROMContent(
3320  PADAPTER               Adapter
3321         )
3322 {
3323         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
3324         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3325         u8                      PROMContent[HWSET_MAX_SIZE]={0};
3326         u8                      eeValue;
3327         u32                     i;
3328         u16                     value16;
3329
3330         eeValue = rtw_read8(Adapter, REG_9346CR);
3331         // To check system boot selection.
3332         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
3333         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
3334
3335
3336         DBG_8723A("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
3337                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
3338
3339         readAdapterInfo(Adapter);
3340 }
3341
3342
3343 static VOID
3344 _InitOtherVariable(
3345  PADAPTER               Adapter
3346         )
3347 {
3348         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3349
3350
3351         //if(Adapter->bInHctTest){
3352         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
3353         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
3354         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
3355         //      pMgntInfo->keepAliveLevel = 0;
3356         //}
3357
3358
3359 }
3360
3361 static VOID
3362 _ReadRFType(
3363         PADAPTER        Adapter
3364         )
3365 {
3366         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3367
3368 #if DISABLE_BB_RF
3369         pHalData->rf_chip = RF_PSEUDO_11N;
3370 #else
3371         pHalData->rf_chip = RF_6052;
3372 #endif
3373 }
3374
3375 void _ReadSilmComboMode(PADAPTER Adapter)
3376 {
3377         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3378
3379         pHalData->SlimComboDbg = _FALSE;        // Default is not debug mode.
3380 }
3381
3382 //
3383 //      Description:
3384 //              We should set Efuse cell selection to WiFi cell in default.
3385 //
3386 //      Assumption:
3387 //              PASSIVE_LEVEL
3388 //
3389 //      Added by Roger, 2010.11.23.
3390 //
3391 void
3392 hal_EfuseCellSel(
3393         PADAPTER        Adapter
3394         )
3395 {
3396         u32                     value32;
3397
3398         value32 = rtw_read32(Adapter, EFUSE_TEST);
3399         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
3400         rtw_write32(Adapter, EFUSE_TEST, value32);
3401 }
3402
3403 static int _ReadAdapterInfo8723AU(PADAPTER      Adapter)
3404 {
3405         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3406         u32 start=rtw_get_current_time();
3407
3408         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
3409
3410         //Efuse_InitSomeVar(Adapter);
3411
3412         hal_EfuseCellSel(Adapter);
3413
3414         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
3415         _ReadPROMContent(Adapter);
3416
3417         // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
3418         _ReadSilmComboMode(Adapter);
3419
3420         _InitOtherVariable(Adapter);
3421
3422         //MSG_8723A("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
3423
3424         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", rtw_get_passing_time_ms(start));
3425
3426         return _SUCCESS;
3427 }
3428
3429
3430 static void ReadAdapterInfo8723AU(PADAPTER Adapter)
3431 {
3432         // Read EEPROM size before call any EEPROM function
3433         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
3434
3435         _ReadAdapterInfo8723AU(Adapter);
3436 }
3437
3438
3439 #define GPIO_DEBUG_PORT_NUM 0
3440 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
3441 {
3442
3443         u32 gpioctrl;
3444         DBG_8723A("==> trigger_gpio_0...\n");
3445         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
3446         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
3447         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
3448         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3449         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
3450         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3451         DBG_8723A("<=== trigger_gpio_0...\n");
3452
3453 }
3454
3455 /*
3456  * If variable not handled here,
3457  * some variables will be processed in SetHwReg8723A()
3458  */
3459 void SetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3460 {
3461         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3462
3463 _func_enter_;
3464
3465         switch(variable)
3466         {
3467                 case HW_VAR_RXDMA_AGG_PG_TH:
3468 #ifdef CONFIG_USB_RX_AGGREGATION
3469                         {
3470                                 u8 threshold = *val;
3471                                 if (threshold == 0)
3472                                         threshold = pHalData->UsbRxAggPageCount;
3473                                 SetHwReg8723A(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
3474                         }
3475 #endif
3476                         break;
3477
3478                 case HW_VAR_SET_RPWM:
3479                         rtw_write8(Adapter, REG_USB_HRPWM, *val);
3480                         break;
3481
3482                 case HW_VAR_TRIGGER_GPIO_0:
3483                         rtl8192cu_trigger_gpio_0(Adapter);
3484                         break;
3485
3486                 default:
3487                         SetHwReg8723A(Adapter, variable, val);
3488                         break;
3489         }
3490
3491 _func_exit_;
3492 }
3493
3494 /*
3495  * If variable not handled here,
3496  * some variables will be processed in GetHwReg8723A()
3497  */
3498 void GetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3499 {
3500         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3501
3502 _func_enter_;
3503
3504         switch (variable)
3505         {
3506                 default:
3507                         GetHwReg8723A(Adapter, variable, val);
3508                         break;
3509         }
3510
3511 _func_exit_;
3512 }
3513
3514 //
3515 //      Description:
3516 //              Query setting of specified variable.
3517 //
3518 u8
3519 GetHalDefVar8192CUsb(
3520         PADAPTER                                Adapter,
3521         HAL_DEF_VARIABLE                eVariable,
3522         void *                                  pValue
3523         )
3524 {
3525         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3526         u8                      bResult = _SUCCESS;
3527
3528         switch(eVariable)
3529         {
3530                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3531                         *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
3532                         break;
3533                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3534                         #ifdef CONFIG_ANTENNA_DIVERSITY
3535                         *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
3536                         #endif
3537                         break;
3538                 case HAL_DEF_CURRENT_ANTENNA:
3539                         #ifdef CONFIG_ANTENNA_DIVERSITY
3540                         *(( u8*)pValue) = pHalData->CurAntenna;
3541                         #endif
3542                         break;
3543                 case HAL_DEF_DRVINFO_SZ:
3544                         *(( u32*)pValue) = DRVINFO_SZ;
3545                         break;
3546                 case HAL_DEF_MAX_RECVBUF_SZ:
3547                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
3548                         break;
3549                 case HAL_DEF_RX_PACKET_OFFSET:
3550                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
3551                         break;
3552                 case HAL_DEF_DBG_DUMP_RXPKT:
3553                         *(( u8*)pValue) = pHalData->bDumpRxPkt;
3554                         break;
3555                 case HAL_DEF_DBG_DM_FUNC:
3556                         *(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
3557                         break;
3558                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3559                         *(( u32*)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
3560                         break;
3561                 case HW_DEF_ODM_DBG_FLAG:
3562                         {
3563                                 u8Byte  DebugComponents = *((u32*)pValue);
3564                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3565                                 printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );
3566                         }
3567                         break;
3568                 default:
3569                         //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable));
3570                         bResult = _FAIL;
3571                         break;
3572         }
3573
3574         return bResult;
3575 }
3576
3577
3578
3579
3580 //
3581 //      Description:
3582 //              Change default setting of specified variable.
3583 //
3584 u8
3585 SetHalDefVar8192CUsb(
3586         PADAPTER                                Adapter,
3587         HAL_DEF_VARIABLE                eVariable,
3588         void *                                  pValue
3589         )
3590 {
3591         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3592         u8                      bResult = _SUCCESS;
3593
3594         switch(eVariable)
3595         {
3596                 case HAL_DEF_DBG_DUMP_RXPKT:
3597                         pHalData->bDumpRxPkt = *(( u8*)pValue);
3598                         break;
3599                 case HAL_DEF_DBG_DM_FUNC:
3600                         {
3601                                 u8 dm_func = *(( u8*)pValue);
3602                                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3603                                 DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3604
3605                                 if(dm_func == 0){ //disable all dynamic func
3606                                         podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
3607                                         DBG_8723A("==> Disable all dynamic function...\n");
3608                                 }
3609                                 else if(dm_func == 1){//disable DIG
3610                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
3611                                         DBG_8723A("==> Disable DIG...\n");
3612                                 }
3613                                 else if(dm_func == 2){//disable High power
3614                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
3615                                 }
3616                                 else if(dm_func == 3){//disable tx power tracking
3617                                         podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
3618                                         DBG_8723A("==> Disable tx power tracking...\n");
3619                                 }
3620                                 else if(dm_func == 4){//disable BT coexistence
3621                                         pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
3622                                 }
3623                                 else if(dm_func == 5){//disable antenna diversity
3624                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
3625                                 }
3626                                 else if(dm_func == 6){//turn on all dynamic func
3627                                         if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
3628                                         {
3629                                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3630                                                 pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
3631                                         }
3632                                         pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
3633                                         podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
3634                                         DBG_8723A("==> Turn on all dynamic function...\n");
3635                                 }
3636                         }
3637                         break;
3638                 case HW_DEF_FA_CNT_DUMP:
3639                         {
3640                                 u8 bRSSIDump = *((u8*)pValue);
3641                                 PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
3642                                 if(bRSSIDump)
3643                                         pDM_Odm->DebugComponents        =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
3644                                 else
3645                                         pDM_Odm->DebugComponents        = 0;
3646
3647                         }
3648                         break;
3649                 case HW_DEF_ODM_DBG_FLAG:
3650                         {
3651                                 u8Byte  DebugComponents = *((u8Byte*)pValue);
3652                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3653                                 pDM_Odm->DebugComponents = DebugComponents;
3654                         }
3655                         break;
3656                 default:
3657                         //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
3658                         bResult = _FAIL;
3659                         break;
3660         }
3661
3662         return bResult;
3663 }
3664
3665 /*
3666 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
3667 {
3668         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(padapter);
3669         unsigned int BrateCfg = 0;
3670
3671
3672         if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
3673                 BrateCfg = mask  & 0x15F;
3674         else    //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
3675                 BrateCfg = mask  & 0x159;
3676
3677         BrateCfg |= 0x01; // default enable 1M ACK rate
3678
3679         return BrateCfg;
3680 }
3681 */
3682 void _update_response_rate(_adapter *padapter,unsigned int mask)
3683 {
3684         u8      RateIndex = 0;
3685         // Set RRSR rate table.
3686         rtw_write8(padapter, REG_RRSR, mask&0xff);
3687         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
3688
3689         // Set RTS initial rate
3690         while(mask > 0x1)
3691         {
3692                 mask = (mask>> 1);
3693                 RateIndex++;
3694         }
3695         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
3696 }
3697
3698 void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id,u8 rssi_level )
3699 {
3700         //volatile unsigned int result;
3701         u8      init_rate=0;
3702         u8      networkType, raid;
3703         u32     mask,rate_bitmap;
3704         u8      shortGIrate = _FALSE;
3705         int     supportRateNum = 0;
3706         struct sta_info *psta;
3707         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
3708         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3709         struct mlme_ext_priv    *pmlmeext = &padapter->mlmeextpriv;
3710         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3711         WLAN_BSSID_EX           *cur_network = &(pmlmeinfo->network);
3712 #ifdef CONFIG_CONCURRENT_MODE
3713         if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
3714                 pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
3715 #endif //CONFIG_CONCURRENT_MODE
3716
3717         if (mac_id >= NUM_STA) //CAM_SIZE
3718         {
3719                 return;
3720         }
3721
3722         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
3723         if(psta == NULL)
3724         {
3725                 return;
3726         }
3727
3728         switch (mac_id)
3729         {
3730                 case 0:// for infra mode
3731 #ifdef CONFIG_CONCURRENT_MODE
3732                 case 2:// first station uses macid=0, second station uses macid=2
3733 #endif
3734                         supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
3735                         networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
3736                         //pmlmeext->cur_wireless_mode = networkType;
3737                         raid = networktype_to_raid(networkType);
3738
3739                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3740                         mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
3741
3742
3743                         if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
3744                         {
3745                                 shortGIrate = _TRUE;
3746                         }
3747
3748                         break;
3749
3750                 case 1://for broadcast/multicast
3751                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3752                         if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
3753                                 networkType = WIRELESS_11B;
3754                         else
3755                                 networkType = WIRELESS_11G;
3756                         raid = networktype_to_raid(networkType);
3757
3758                         mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
3759
3760                         break;
3761
3762                 default: //for each sta in IBSS
3763                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3764                         networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
3765                         //pmlmeext->cur_wireless_mode = networkType;
3766                         raid = networktype_to_raid(networkType);
3767
3768                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3769
3770
3771                         //todo: support HT in IBSS
3772
3773                         break;
3774         }
3775
3776         //mask &=0x0fffffff;
3777         rate_bitmap = 0x0fffffff;
3778 #ifdef  CONFIG_ODM_REFRESH_RAMASK
3779         {
3780                 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
3781                 printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
3782                         __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
3783         }
3784 #endif
3785
3786         mask &= rate_bitmap;
3787         mask |= ((raid<<28)&0xf0000000);
3788
3789
3790         init_rate = get_highest_rate_idx(mask)&0x3f;
3791
3792         if(pHalData->fw_ractrl == _TRUE)
3793         {
3794                 u8 arg = 0;
3795
3796                 //arg = (cam_idx-4)&0x1f;//MACID
3797                 arg = mac_id&0x1f;//MACID
3798
3799                 arg |= BIT(7);
3800
3801                 if (shortGIrate==_TRUE)
3802                         arg |= BIT(5);
3803
3804                 DBG_8723A("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
3805
3806                 rtl8192c_set_raid_cmd(padapter, mask, arg);
3807
3808         }
3809         else
3810         {
3811                 if (shortGIrate==_TRUE)
3812                         init_rate |= BIT(6);
3813
3814                 rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
3815         }
3816
3817
3818         //set ra_id
3819         psta->raid = raid;
3820         psta->init_rate = init_rate;
3821
3822         //set correct initial date rate for each mac_id
3823         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
3824 }
3825
3826 static void rtl8723au_init_default_value(PADAPTER padapter)
3827 {
3828         rtl8723a_init_default_value(padapter);
3829 }
3830
3831 static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
3832 {
3833         u8 bResult = _TRUE;
3834         switch(efunc_id){
3835
3836                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
3837                 case HAL_USB_SELECT_SUSPEND:
3838                         {
3839                                 u8 bfwpoll = *(( u8*)val);
3840                                 rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
3841                         }
3842                         break;
3843                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
3844
3845                 default:
3846                         break;
3847         }
3848         return bResult;
3849 }
3850
3851 void rtl8723au_set_hal_ops(_adapter * padapter)
3852 {
3853         struct hal_ops  *pHalFunc = &padapter->HalFunc;
3854
3855 _func_enter_;
3856
3857         padapter->HalData = kzalloc(sizeof(HAL_DATA_TYPE), GFP_KERNEL);
3858         if(padapter->HalData == NULL){
3859                 DBG_8723A("cant not alloc memory for HAL DATA \n");
3860         }
3861         //memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
3862         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
3863
3864         pHalFunc->hal_init = &rtl8723au_hal_init;
3865         pHalFunc->hal_deinit = &rtl8723au_hal_deinit;
3866
3867         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
3868
3869         pHalFunc->inirp_init = &rtl8723au_inirp_init;
3870         pHalFunc->inirp_deinit = &rtl8723au_inirp_deinit;
3871
3872         pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv;
3873         pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv;
3874
3875         pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv;
3876         pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv;
3877 #ifdef CONFIG_SW_LED
3878         pHalFunc->InitSwLeds = &rtl8723au_InitSwLeds;
3879         pHalFunc->DeInitSwLeds = &rtl8723au_DeInitSwLeds;
3880 #else //case of hw led or no led
3881         pHalFunc->InitSwLeds = NULL;
3882         pHalFunc->DeInitSwLeds = NULL;
3883 #endif//CONFIG_SW_LED
3884
3885         pHalFunc->init_default_value = &rtl8723au_init_default_value;
3886         pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure;
3887         pHalFunc->read_adapter_info = &ReadAdapterInfo8723AU;
3888
3889         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
3890         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
3891
3892         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
3893
3894         pHalFunc->SetHwRegHandler = &SetHwReg8723AU;
3895         pHalFunc->GetHwRegHandler = &GetHwReg8723AU;
3896         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
3897         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
3898
3899         pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
3900
3901         pHalFunc->hal_xmit = &rtl8192cu_hal_xmit;
3902         pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit;
3903         pHalFunc->hal_xmitframe_enqueue = &rtl8723au_hal_xmitframe_enqueue;
3904
3905 #ifdef CONFIG_HOSTAPD_MLME
3906         pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
3907 #endif
3908         pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
3909
3910         rtl8723a_set_hal_ops(pHalFunc);
3911
3912 _func_exit_;
3913
3914 }