hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_conf.h>
  23 #include <osdep_service.h>
  24 #include <drv_types.h>
  25 #include <rtw_efuse.h>
  26
  27
  28 #include <HalPwrSeqCmd.h>
  29 #include <Hal8723PwrSeq.h>
  30 #include <rtl8723a_hal.h>
  31 #include <rtl8723a_led.h>
  32
  33 #ifdef CONFIG_IOL
  34 #include <rtw_iol.h>
  35 #endif
  36
  37 #ifdef CONFIG_EFUSE_CONFIG_FILE
  38 #include <linux/fs.h>
  39 #include <asm/uaccess.h>
  40 #endif //CONFIG_EFUSE_CONFIG_FILE
  41
  42 #ifndef CONFIG_USB_HCI
  43
  44 #error "CONFIG_USB_HCI shall be on!\n"
  45
  46 #endif
  47
  48 #include <usb_ops.h>
  49 #include <usb_hal.h>
  50 #include <usb_osintf.h>
  51
  52 #if DISABLE_BB_RF
  53         #define         HAL_MAC_ENABLE  0
  54         #define         HAL_BB_ENABLE           0
  55         #define         HAL_RF_ENABLE           0
  56 #else
  57         #define         HAL_MAC_ENABLE  1
  58         #define         HAL_BB_ENABLE           1
  59         #define         HAL_RF_ENABLE           1
  60 #endif
  61
  62
  63 static VOID
  64 _ConfigChipOutEP(
  65         IN      PADAPTER        pAdapter,
  66         IN      u8              NumOutPipe
  67         )
  68 {
  69         u8                      value8;
  70         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  71
  72         pHalData->OutEpQueueSel = 0;
  73         pHalData->OutEpNumber   = 0;
  74
  75         // Normal and High queue
  76         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  77
  78         if(value8 & USB_NORMAL_SIE_EP_MASK){
  79                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  80                 pHalData->OutEpNumber++;
  81         }
  82
  83         if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
  84                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  85                 pHalData->OutEpNumber++;
  86         }
  87
  88         // Low queue
  89         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  90         if(value8 & USB_NORMAL_SIE_EP_MASK){
  91                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  92                 pHalData->OutEpNumber++;
  93         }
  94
  95         // TODO: Error recovery for this case
  96         //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber));
  97
  98 }
  99
 100 static bool HalUsbSetQueuePipeMapping8192CUsb(
 101         IN      PADAPTER        pAdapter,
 102         IN      u8              NumInPipe,
 103         IN      u8              NumOutPipe
 104         )
 105 {
 106         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
 107         bool                    result          = _FALSE;
 108
 109         _ConfigChipOutEP(pAdapter, NumOutPipe);
 110
 111         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
 112         if(1 == pHalData->OutEpNumber){
 113                 if(1 != NumInPipe){
 114                         return result;
 115                 }
 116         }
 117
 118         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
 119
 120         return result;
 121
 122 }
 123
 124 void rtl8192cu_interface_configure(_adapter *padapter)
 125 {
 126         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 127         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 128
 129         if (pdvobjpriv->ishighspeed == _TRUE)
 130         {
 131                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
 132         }
 133         else
 134         {
 135                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 136         }
 137
 138         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 139
 140 #ifdef CONFIG_USB_TX_AGGREGATION
 141         pHalData->UsbTxAggMode          = 1;
 142         pHalData->UsbTxAggDescNum       = 0x6;  // only 4 bits
 143 #endif
 144
 145 #ifdef CONFIG_USB_RX_AGGREGATION
 146         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 147         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 148         pHalData->UsbRxAggBlockTimeout  = 0x6;
 149         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 150         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 151 #endif
 152
 153         HalUsbSetQueuePipeMapping8192CUsb(padapter,
 154                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 155
 156 }
 157
 158 static u8 _InitPowerOn(PADAPTER padapter)
 159 {
 160         u8              status = _SUCCESS;
 161         u16                     value16=0;
 162         u8                      value8 = 0;
 163
 164         // RSV_CTRL 0x1C[7:0] = 0x00                    // unlock ISO/CLK/Power control register
 165         rtw_write8(padapter, REG_RSV_CTRL, 0x0);
 166
 167         // HW Power on sequence
 168         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_enable_flow ))
 169                                 return _FAIL;
 170
 171         // 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051
 172                         value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
 173                         rtw_write8(padapter,REG_APS_FSMCO+2,(value8|BIT3));
 174
 175                         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 176                         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 177                         value16 = rtw_read16(padapter, REG_CR);
 178                         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 179                                                 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC | CALTMR_EN);
 180                         rtw_write16(padapter, REG_CR, value16);
 181
 182         //for Efuse PG, suggest by Jackie 2011.11.23
 183         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
 184
 185         return status;
 186 }
 187
 188
 189 static void _dbg_dump_macreg(_adapter *padapter)
 190 {
 191         u32 offset = 0;
 192         u32 val32 = 0;
 193         u32 index =0 ;
 194         for(index=0;index<64;index++)
 195         {
 196                 offset = index*4;
 197                 val32 = rtw_read32(padapter,offset);
 198                 DBG_8723A("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 199         }
 200 }
 201
 202 //-------------------------------------------------------------------------
 203 //
 204 // LLT R/W/Init function
 205 //
 206 //-------------------------------------------------------------------------
 207 static u8 _LLTWrite(
 208         IN  PADAPTER    Adapter,
 209         IN      u32             address,
 210         IN      u32             data
 211         )
 212 {
 213         u8      status = _SUCCESS;
 214         int             count = 0;
 215         u32             value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 216
 217         rtw_write32(Adapter, REG_LLT_INIT, value);
 218
 219         //polling
 220         do{
 221
 222                 value = rtw_read32(Adapter, REG_LLT_INIT);
 223                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 224                         break;
 225                 }
 226
 227                 if(count > POLLING_LLT_THRESHOLD){
 228                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
 229                         status = _FAIL;
 230                         break;
 231                 }
 232         }while(count++);
 233
 234         return status;
 235
 236 }
 237
 238
 239 static u8 _LLTRead(
 240         IN  PADAPTER    Adapter,
 241         IN      u32             address
 242         )
 243 {
 244         int             count = 0;
 245         u32             value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
 246
 247         rtw_write32(Adapter, REG_LLT_INIT, value);
 248
 249         //polling and get value
 250         do{
 251
 252                 value = rtw_read32(Adapter, REG_LLT_INIT);
 253                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 254                         return (u8)value;
 255                 }
 256
 257                 if(count > POLLING_LLT_THRESHOLD){
 258                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
 259                         break;
 260                 }
 261         }while(count++);
 262
 263         return 0xFF;
 264
 265 }
 266
 267
 268 //---------------------------------------------------------------
 269 //
 270 //      MAC init functions
 271 //
 272 //---------------------------------------------------------------
 273 static VOID
 274 _SetMacID(
 275         IN  PADAPTER Adapter, u8* MacID
 276         )
 277 {
 278         u32 i;
 279         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 280 #ifdef  CONFIG_CONCURRENT_MODE
 281                 if(Adapter->iface_type == IFACE_PORT1)
 282                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 283                 else
 284 #endif
 285                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 286         }
 287 }
 288
 289 static VOID
 290 _SetBSSID(
 291         IN  PADAPTER Adapter, u8* BSSID
 292         )
 293 {
 294         u32 i;
 295         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 296 #ifdef  CONFIG_CONCURRENT_MODE
 297                 if(Adapter->iface_type == IFACE_PORT1)
 298                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 299                 else
 300 #endif
 301                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 302         }
 303 }
 304
 305
 306 // Shall USB interface init this?
 307 static VOID
 308 _InitInterrupt(
 309         IN  PADAPTER Adapter
 310         )
 311 {
 312         u32     value32;
 313
 314         // HISR - turn all on
 315         value32 = 0xFFFFFFFF;
 316         rtw_write32(Adapter, REG_HISR, value32);
 317
 318         // HIMR - turn all on
 319         rtw_write32(Adapter, REG_HIMR, value32);
 320 }
 321
 322
 323 static VOID
 324 _InitQueueReservedPage(
 325         IN  PADAPTER Adapter
 326         )
 327 {
 328         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 329         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 330
 331         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 332         u32                     numHQ           = 0;
 333         u32                     numLQ           = 0;
 334         u32                     numNQ           = 0;
 335         u32                     numPubQ;
 336         u32                     value32;
 337         u8                      value8;
 338         bool            bWiFiConfig     = pregistrypriv->wifi_spec;
 339         //u32                   txQPageNum, txQPageUnit,txQRemainPage;
 340
 341         { //for WMM
 342                 //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
 343
 344                 numPubQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_PUBQ:NORMAL_PAGE_NUM_PUBQ;
 345
 346                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 347                 {
 348                         numHQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
 349                 }
 350
 351                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 352                 {
 353                         numLQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
 354                 }
 355                 // NOTE: This step shall be proceed before writting REG_RQPN.
 356                 if(pHalData->OutEpQueueSel & TX_SELE_NQ){
 357                         numNQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
 358                 }
 359                 value8 = (u8)_NPQ(numNQ);
 360                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 361         }
 362
 363         // TX DMA
 364         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 365         rtw_write32(Adapter, REG_RQPN, value32);
 366 }
 367
 368 static VOID
 369 _InitTxBufferBoundary(
 370         IN  PADAPTER Adapter
 371         )
 372 {
 373         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 374         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 375
 376         u8      txpktbuf_bndy;
 377
 378         if(!pregistrypriv->wifi_spec){
 379                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 380         }
 381         else{//for WMM
 382                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 383         }
 384
 385         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 386         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 387         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 388         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 389 #if 1
 390         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 391 #else
 392         txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
 393         txdmactrl &= ~BCN_HEAD_MASK;
 394         txdmactrl |= BCN_HEAD(txpktbuf_bndy);
 395         PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
 396 #endif
 397 }
 398
 399 static VOID
 400 _InitPageBoundary(
 401         IN  PADAPTER Adapter
 402         )
 403 {
 404         // RX Page Boundary
 405         //srand(static_cast<unsigned int>(time(NULL)) );
 406         u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
 407
 408         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 409
 410         // TODO: ?? shall we set tx boundary?
 411 }
 412
 413
 414 static VOID
 415 _InitNormalChipRegPriority(
 416         IN      PADAPTER        Adapter,
 417         IN      u16             beQ,
 418         IN      u16             bkQ,
 419         IN      u16             viQ,
 420         IN      u16             voQ,
 421         IN      u16             mgtQ,
 422         IN      u16             hiQ
 423         )
 424 {
 425         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 426
 427         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 428                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 429                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 430
 431         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 432 }
 433
 434 static VOID
 435 _InitNormalChipOneOutEpPriority(
 436         IN      PADAPTER Adapter
 437         )
 438 {
 439         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 440
 441         u16     value = 0;
 442         switch(pHalData->OutEpQueueSel)
 443         {
 444                 case TX_SELE_HQ:
 445                         value = QUEUE_HIGH;
 446                         break;
 447                 case TX_SELE_LQ:
 448                         value = QUEUE_LOW;
 449                         break;
 450                 case TX_SELE_NQ:
 451                         value = QUEUE_NORMAL;
 452                         break;
 453                 default:
 454                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 455                         break;
 456         }
 457
 458         _InitNormalChipRegPriority(Adapter,
 459                                                                 value,
 460                                                                 value,
 461                                                                 value,
 462                                                                 value,
 463                                                                 value,
 464                                                                 value
 465                                                                 );
 466
 467 }
 468
 469 static VOID
 470 _InitNormalChipTwoOutEpPriority(
 471         IN      PADAPTER Adapter
 472         )
 473 {
 474         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 475         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 476         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 477
 478
 479         u16     valueHi = 0;
 480         u16     valueLow = 0;
 481
 482         switch(pHalData->OutEpQueueSel)
 483         {
 484                 case (TX_SELE_HQ | TX_SELE_LQ):
 485                         valueHi = QUEUE_HIGH;
 486                         valueLow = QUEUE_LOW;
 487                         break;
 488                 case (TX_SELE_NQ | TX_SELE_LQ):
 489                         valueHi = QUEUE_NORMAL;
 490                         valueLow = QUEUE_LOW;
 491                         break;
 492                 case (TX_SELE_HQ | TX_SELE_NQ):
 493                         valueHi = QUEUE_HIGH;
 494                         valueLow = QUEUE_NORMAL;
 495                         break;
 496                 default:
 497                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 498                         break;
 499         }
 500
 501         if(!pregistrypriv->wifi_spec ){
 502                 beQ             = valueLow;
 503                 bkQ             = valueLow;
 504                 viQ             = valueHi;
 505                 voQ             = valueHi;
 506                 mgtQ    = valueHi;
 507                 hiQ             = valueHi;
 508         }
 509         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 510                 beQ             = valueLow;
 511                 bkQ             = valueHi;
 512                 viQ             = valueHi;
 513                 voQ             = valueLow;
 514                 mgtQ    = valueHi;
 515                 hiQ             = valueHi;
 516         }
 517
 518         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 519
 520 }
 521
 522 static VOID
 523 _InitNormalChipThreeOutEpPriority(
 524         IN      PADAPTER Adapter
 525         )
 526 {
 527         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 528         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 529
 530         if(!pregistrypriv->wifi_spec ){// typical setting
 531                 beQ             = QUEUE_LOW;
 532                 bkQ             = QUEUE_LOW;
 533                 viQ             = QUEUE_NORMAL;
 534                 voQ             = QUEUE_HIGH;
 535                 mgtQ    = QUEUE_HIGH;
 536                 hiQ             = QUEUE_HIGH;
 537         }
 538         else{// for WMM
 539                 beQ             = QUEUE_LOW;
 540                 bkQ             = QUEUE_NORMAL;
 541                 viQ             = QUEUE_NORMAL;
 542                 voQ             = QUEUE_HIGH;
 543                 mgtQ    = QUEUE_HIGH;
 544                 hiQ             = QUEUE_HIGH;
 545         }
 546         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 547 }
 548
 549 static VOID
 550 _InitNormalChipQueuePriority(
 551         IN      PADAPTER Adapter
 552         )
 553 {
 554         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 555
 556         switch(pHalData->OutEpNumber)
 557         {
 558                 case 1:
 559                         _InitNormalChipOneOutEpPriority(Adapter);
 560                         break;
 561                 case 2:
 562                         _InitNormalChipTwoOutEpPriority(Adapter);
 563                         break;
 564                 case 3:
 565                         _InitNormalChipThreeOutEpPriority(Adapter);
 566                         break;
 567                 default:
 568                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 569                         break;
 570         }
 571
 572
 573 }
 574
 575 static VOID
 576 _InitQueuePriority(
 577         IN  PADAPTER Adapter
 578         )
 579 {
 580         _InitNormalChipQueuePriority(Adapter);
 581 }
 582
 583 static VOID
 584 _InitHardwareDropIncorrectBulkOut(
 585         IN  PADAPTER Adapter
 586         )
 587 {
 588         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 589         value32 |= DROP_DATA_EN;
 590         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 591 }
 592
 593 static VOID
 594 _InitNetworkType(
 595         IN  PADAPTER Adapter
 596         )
 597 {
 598         u32     value32;
 599
 600         value32 = rtw_read32(Adapter, REG_CR);
 601
 602         // TODO: use the other function to set network type
 603 #if RTL8191C_FPGA_NETWORKTYPE_ADHOC
 604         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 605 #else
 606         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 607 #endif
 608         rtw_write32(Adapter, REG_CR, value32);
 609 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 610 }
 611
 612 static VOID
 613 _InitTransferPageSize(
 614         IN  PADAPTER Adapter
 615         )
 616 {
 617         // Tx page size is always 128.
 618
 619         u8      value8;
 620         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 621         rtw_write8(Adapter, REG_PBP, value8);
 622 }
 623
 624 static VOID
 625 _InitDriverInfoSize(
 626         IN  PADAPTER    Adapter,
 627         IN      u8              drvInfoSize
 628         )
 629 {
 630         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 631 }
 632
 633 static VOID
 634 _InitWMACSetting(
 635         IN  PADAPTER Adapter
 636         )
 637 {
 638         //u4Byte                        value32;
 639         //u16                   value16;
 640         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 641
 642         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 643         //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 644          // don't turn on AAP, it will allow all packets to driver
 645         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 646 #if (1 == RTL8192C_RX_PACKET_INCLUDE_CRC)
 647         pHalData->ReceiveConfig |= ACRC32;
 648 #endif
 649
 650         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 651         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 652
 653         // Accept all multicast address
 654         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 655         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 656
 657
 658         // Accept all data frames
 659         //value16 = 0xFFFF;
 660         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 661
 662         // 2010.09.08 hpfan
 663         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 664         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 665         //value16 = 0x400;
 666         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 667
 668         // Accept all management frames
 669         //value16 = 0xFFFF;
 670         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 671
 672         //enable RX_SHIFT bits
 673         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 674
 675 }
 676
 677 static VOID
 678 _InitAdaptiveCtrl(
 679         IN  PADAPTER Adapter
 680         )
 681 {
 682         u16     value16;
 683         u32     value32;
 684
 685         // Response Rate Set
 686         value32 = rtw_read32(Adapter, REG_RRSR);
 687         value32 &= ~RATE_BITMAP_ALL;
 688         value32 |= RATE_RRSR_CCK_ONLY_1M;
 689         rtw_write32(Adapter, REG_RRSR, value32);
 690
 691         // CF-END Threshold
 692         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 693
 694         // SIFS (used in NAV)
 695         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 696         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 697
 698         // Retry Limit
 699         value16 = _LRL(0x30) | _SRL(0x30);
 700         rtw_write16(Adapter, REG_RL, value16);
 701
 702 }
 703
 704 static VOID
 705 _InitRateFallback(
 706         IN  PADAPTER Adapter
 707         )
 708 {
 709         // Set Data Auto Rate Fallback Retry Count register.
 710         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 711         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 712         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 713         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 714
 715 }
 716
 717
 718 static VOID
 719 _InitEDCA(
 720         IN  PADAPTER Adapter
 721         )
 722 {
 723         // Set Spec SIFS (used in NAV)
 724         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 725         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 726
 727         // Set SIFS for CCK
 728         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 729
 730         // Set SIFS for OFDM
 731         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 732
 733         // TXOP
 734         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 735         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 736         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 737         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 738 }
 739
 740 #ifdef CONFIG_LED
 741 static void _InitHWLed(PADAPTER Adapter)
 742 {
 743         struct led_priv *pledpriv = &(Adapter->ledpriv);
 744
 745         if( pledpriv->LedStrategy != HW_LED)
 746                 return;
 747
 748 // HW led control
 749 // to do ....
 750 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 751
 752 }
 753 #endif //CONFIG_LED
 754
 755 static VOID
 756 _InitRDGSetting(
 757         IN      PADAPTER Adapter
 758         )
 759 {
 760         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 761         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 762         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 763 }
 764
 765 static VOID
 766 _InitRxSetting(
 767         IN      PADAPTER Adapter
 768         )
 769 {
 770         rtw_write32(Adapter, REG_MACID, 0x87654321);
 771         rtw_write32(Adapter, 0x0700, 0x87654321);
 772 }
 773
 774 static VOID
 775 _InitRetryFunction(
 776         IN  PADAPTER Adapter
 777         )
 778 {
 779         u8      value8;
 780
 781         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 782         value8 |= EN_AMPDU_RTY_NEW;
 783         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 784
 785         // Set ACK timeout
 786         rtw_write8(Adapter, REG_ACKTO, 0x40);
 787 }
 788
 789 /*-----------------------------------------------------------------------------
 790  * Function:    usb_AggSettingTxUpdate()
 791  *
 792  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 793  *                      dynamic TX/RX aggreagtion parameters update.
 794  *
 795  * Input:                       PADAPTER
 796  *
 797  * Output/Return:       NONE
 798  *
 799  * Revised History:
 800  *      When            Who             Remark
 801  *      12/10/2010      MHC             Seperate to smaller function.
 802  *
 803  *---------------------------------------------------------------------------*/
 804 static VOID
 805 usb_AggSettingTxUpdate(
 806         IN      PADAPTER                        Adapter
 807         )
 808 {
 809 #ifdef CONFIG_USB_TX_AGGREGATION
 810         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 811         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 812         u32                     value32;
 813
 814         if(Adapter->registrypriv.wifi_spec)
 815                 pHalData->UsbTxAggMode = _FALSE;
 816
 817         if(pHalData->UsbTxAggMode){
 818                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 819                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 820                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 821
 822                 rtw_write32(Adapter, REG_TDECTRL, value32);
 823         }
 824
 825 #endif
 826 }       // usb_AggSettingTxUpdate
 827
 828
 829 /*-----------------------------------------------------------------------------
 830  * Function:    usb_AggSettingRxUpdate()
 831  *
 832  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 833  *                      dynamic TX/RX aggreagtion parameters update.
 834  *
 835  * Input:                       PADAPTER
 836  *
 837  * Output/Return:       NONE
 838  *
 839  * Revised History:
 840  *      When            Who             Remark
 841  *      12/10/2010      MHC             Seperate to smaller function.
 842  *
 843  *---------------------------------------------------------------------------*/
 844 static VOID
 845 usb_AggSettingRxUpdate(
 846         IN      PADAPTER                        Adapter
 847         )
 848 {
 849 #ifdef CONFIG_USB_RX_AGGREGATION
 850         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 851         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 852         u8                      valueDMA;
 853         u8                      valueUSB;
 854
 855         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 856         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 857
 858         switch(pHalData->UsbRxAggMode)
 859         {
 860                 case USB_RX_AGG_DMA:
 861                         valueDMA |= RXDMA_AGG_EN;
 862                         valueUSB &= ~USB_AGG_EN;
 863                         break;
 864                 case USB_RX_AGG_USB:
 865                         valueDMA &= ~RXDMA_AGG_EN;
 866                         valueUSB |= USB_AGG_EN;
 867                         break;
 868                 case USB_RX_AGG_MIX:
 869                         valueDMA |= RXDMA_AGG_EN;
 870                         valueUSB |= USB_AGG_EN;
 871                         break;
 872                 case USB_RX_AGG_DISABLE:
 873                 default:
 874                         valueDMA &= ~RXDMA_AGG_EN;
 875                         valueUSB &= ~USB_AGG_EN;
 876                         break;
 877         }
 878
 879         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 880         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 881
 882         switch(pHalData->UsbRxAggMode)
 883         {
 884                 case USB_RX_AGG_DMA:
 885                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 886                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 887                         break;
 888                 case USB_RX_AGG_USB:
 889                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 890                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 891                         break;
 892                 case USB_RX_AGG_MIX:
 893                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 894                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 895                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 896                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 897                         break;
 898                 case USB_RX_AGG_DISABLE:
 899                 default:
 900                         // TODO:
 901                         break;
 902         }
 903
 904         switch(PBP_128)
 905         {
 906                 case PBP_128:
 907                         pHalData->HwRxPageSize = 128;
 908                         break;
 909                 case PBP_64:
 910                         pHalData->HwRxPageSize = 64;
 911                         break;
 912                 case PBP_256:
 913                         pHalData->HwRxPageSize = 256;
 914                         break;
 915                 case PBP_512:
 916                         pHalData->HwRxPageSize = 512;
 917                         break;
 918                 case PBP_1024:
 919                         pHalData->HwRxPageSize = 1024;
 920                         break;
 921                 default:
 922                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 923                         break;
 924         }
 925 #endif
 926 }       // usb_AggSettingRxUpdate
 927
 928 static VOID
 929 InitUsbAggregationSetting(
 930         IN  PADAPTER Adapter
 931         )
 932 {
 933         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 934
 935         // Tx aggregation setting
 936         usb_AggSettingTxUpdate(Adapter);
 937
 938         // Rx aggregation setting
 939         usb_AggSettingRxUpdate(Adapter);
 940
 941         // 201/12/10 MH Add for USB agg mode dynamic switch.
 942         pHalData->UsbRxHighSpeedMode = _FALSE;
 943 }
 944
 945 /*-----------------------------------------------------------------------------
 946  * Function:    USB_AggModeSwitch()
 947  *
 948  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
 949  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
 950  *                      need to monitor the influence of FTP/network share.
 951  *                      For TX mode, we are still ubder investigation.
 952  *
 953  * Input:               PADAPTER
 954  *
 955  * Output:              NONE
 956  *
 957  * Return:              NONE
 958  *
 959  * Revised History:
 960  *      When            Who             Remark
 961  *      12/10/2010      MHC             Create Version 0.
 962  *
 963  *---------------------------------------------------------------------------*/
 964 VOID
 965 USB_AggModeSwitch(
 966         IN      PADAPTER                        Adapter
 967         )
 968 {
 969 #if 0
 970         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 971         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
 972
 973         //pHalData->UsbRxHighSpeedMode = FALSE;
 974         // How to measure the RX speed? We assume that when traffic is more than
 975         if (pMgntInfo->bRegAggDMEnable == _FALSE)
 976         {
 977                 return; // Inf not support.
 978         }
 979
 980
 981         if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _TRUE &&
 982                 pHalData->UsbRxHighSpeedMode == _FALSE)
 983         {
 984                 pHalData->UsbRxHighSpeedMode = _TRUE;
 985                 DBG_8723A("UsbAggModeSwitchCheck to HIGH\n");
 986         }
 987         else if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _FALSE &&
 988                 pHalData->UsbRxHighSpeedMode == _TRUE)
 989         {
 990                 pHalData->UsbRxHighSpeedMode = _FALSE;
 991                 DBG_8723A("UsbAggModeSwitchCheck to LOW\n");
 992         }
 993         else
 994         {
 995                 return;
 996         }
 997
 998         // 2010/12/10 MH Add for USB Aggregation judgement we need to
 999         //if( pMgntInfo->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
1000                 //                      pMgntInfo->LinkDetectInfo.NumTxOkInPeriod > 4000 )
1001
1002 #ifdef CONFIG_USB_TX_AGGREGATION
1003         //usb_AggSettingTxUpdate(Adapter);
1004 #endif
1005
1006 #ifdef CONFIG_USB_RX_AGGREGATION
1007         if (pHalData->UsbRxHighSpeedMode == _TRUE)
1008         {
1009                 // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
1010                 // USB mode
1011                 pHalData->UsbRxAggBlockCount            = 40;
1012                 pHalData->UsbRxAggBlockTimeout  = 5;
1013                 // Mix mode
1014                 pHalData->UsbRxAggPageCount             = 72;
1015                 pHalData->UsbRxAggPageTimeout   = 6;
1016         }
1017         else
1018         {
1019                 // USB mode
1020                 pHalData->UsbRxAggBlockCount            = pMgntInfo->RegUsbRxAggBlockCount;
1021                 pHalData->UsbRxAggBlockTimeout  = pMgntInfo->RegUsbRxAggBlockTimeout;
1022                 // Mix mode
1023                 pHalData->UsbRxAggPageCount             = pMgntInfo->RegUsbRxAggPageCount;
1024                 pHalData->UsbRxAggPageTimeout   = pMgntInfo->RegUsbRxAggPageTimeout;
1025         }
1026 #endif
1027 #endif
1028 }       // USB_AggModeSwitch
1029
1030 static VOID
1031 _InitOperationMode(
1032         IN      PADAPTER                        Adapter
1033         )
1034 {
1035 #if 0//gtest
1036         PHAL_DATA_8192CUSB      pHalData = GetHalData8192CUsb(Adapter);
1037         u1Byte                          regBwOpMode = 0;
1038         u4Byte                          regRATR = 0, regRRSR = 0;
1039
1040
1041         //1 This part need to modified according to the rate set we filtered!!
1042         //
1043         // Set RRSR, RATR, and REG_BWOPMODE registers
1044         //
1045         switch(Adapter->RegWirelessMode)
1046         {
1047                 case WIRELESS_MODE_B:
1048                         regBwOpMode = BW_OPMODE_20MHZ;
1049                         regRATR = RATE_ALL_CCK;
1050                         regRRSR = RATE_ALL_CCK;
1051                         break;
1052                 case WIRELESS_MODE_A:
1053                         ASSERT(FALSE);
1054 #if 0
1055                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1056                         regRATR = RATE_ALL_OFDM_AG;
1057                         regRRSR = RATE_ALL_OFDM_AG;
1058 #endif
1059                         break;
1060                 case WIRELESS_MODE_G:
1061                         regBwOpMode = BW_OPMODE_20MHZ;
1062                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1063                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1064                         break;
1065                 case WIRELESS_MODE_AUTO:
1066                         if (Adapter->bInHctTest)
1067                         {
1068                             regBwOpMode = BW_OPMODE_20MHZ;
1069                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1070                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1071                         }
1072                         else
1073                         {
1074                             regBwOpMode = BW_OPMODE_20MHZ;
1075                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1076                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1077                         }
1078                         break;
1079                 case WIRELESS_MODE_N_24G:
1080                         // It support CCK rate by default.
1081                         // CCK rate will be filtered out only when associated AP does not support it.
1082                         regBwOpMode = BW_OPMODE_20MHZ;
1083                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1084                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1085                         break;
1086                 case WIRELESS_MODE_N_5G:
1087                         ASSERT(FALSE);
1088 #if 0
1089                         regBwOpMode = BW_OPMODE_5G;
1090                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1091                         regRRSR = RATE_ALL_OFDM_AG;
1092 #endif
1093                         break;
1094         }
1095
1096         // Ziv ????????
1097         //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
1098         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1099
1100         // For Min Spacing configuration.
1101         switch(pHalData->RF_Type)
1102         {
1103                 case RF_1T2R:
1104                 case RF_1T1R:
1105                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter: RF_Type%s\n", (pHalData->RF_Type==RF_1T1R? "(1T1R)":"(1T2R)")));
1106                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
1107                         break;
1108                 case RF_2T2R:
1109                 case RF_2T2R_GREEN:
1110                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter:RF_Type(2T2R)\n"));
1111                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
1112                         break;
1113         }
1114
1115         rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, Adapter->MgntInfo.MinSpaceCfg);
1116 #endif
1117 }
1118
1119 static VOID
1120 _InitRFType(
1121         IN      PADAPTER Adapter
1122         )
1123 {
1124         struct registry_priv     *pregpriv = &Adapter->registrypriv;
1125         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1126         bool                    is92CU          = IS_92C_SERIAL(pHalData->VersionID);
1127
1128 #if     DISABLE_BB_RF
1129         pHalData->rf_chip       = RF_PSEUDO_11N;
1130         return;
1131 #endif
1132
1133         pHalData->rf_chip       = RF_6052;
1134
1135         if(_FALSE == is92CU){
1136                 pHalData->rf_type = RF_1T1R;
1137                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
1138                 return;
1139         }
1140
1141         // TODO: Consider that EEPROM set 92CU to 1T1R later.
1142         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
1143         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
1144         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1145
1146 }
1147
1148 static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter)
1149 {
1150 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1151         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1152         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1153         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1154         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1155         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1156 #endif
1157 }
1158
1159 // Set CCK and OFDM Block "ON"
1160 static VOID _BBTurnOnBlock(
1161         IN      PADAPTER                Adapter
1162         )
1163 {
1164 #if (DISABLE_BB_RF)
1165         return;
1166 #endif
1167
1168         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1169         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1170 }
1171
1172 #define MgntActSet_RF_State(...)
1173 static void _RfPowerSave(PADAPTER padapter)
1174 {
1175 #if 0
1176         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1177         struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv;
1178         rt_rf_power_state eRfPowerStateToSet;
1179         u8 u1bTmp;
1180
1181
1182 #if (DISABLE_BB_RF)
1183         return;
1184 #endif
1185         //
1186         // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1187         // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1188         // call init_adapter. May cause some problem??
1189         //
1190         // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1191         // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1192         // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1193         // Added by tynli. 2010.03.30.
1194         ppwrctrl->rf_pwrstate = rf_on;
1195         RT_CLEAR_PS_LEVEL(ppwrctrl, RT_RF_OFF_LEVL_HALT_NIC);
1196         //Added by chiyokolin, 2011.10.12 for Tx
1197         rtw_write8(padapter, REG_TXPAUSE, 0x00);
1198
1199         // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1200         // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1201
1202         eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(padapter);
1203         ppwrctrl->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
1204         ppwrctrl->rfoff_reason |= (ppwrctrl->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
1205
1206         if (ppwrctrl->rfoff_reason & RF_CHANGE_BY_HW)
1207                 ppwrctrl->b_hw_radio_off = _TRUE;
1208
1209         if (ppwrctrl->reg_rfoff == _TRUE)
1210         {
1211                 // User disable RF via registry.
1212                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
1213                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
1214
1215 //              if (padapter->bSlaveOfDMSP)
1216 //                      return;
1217         }
1218         else if (ppwrctrl->rfoff_reason > RF_CHANGE_BY_PS)
1219         {
1220                 // H/W or S/W RF OFF before sleep.
1221                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
1222                 MgntActSet_RF_State(padapter, rf_off, ppwrctrl->rfoff_reason, _TRUE);
1223         }
1224         else
1225         {
1226                 // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
1227 #if 0
1228 //              if (RT_GetInterfaceSelection(padapter)==INTF_SEL2_MINICARD &&
1229                 if ((pHalData->BoardType == BOARD_MINICARD) &&
1230                         (padapter->MgntInfo.PowerSaveControl.bGpioRfSw))
1231                 {
1232                         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet));
1233                         if (eRfPowerStateToSet == rf_off)
1234                         {
1235                                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
1236                                 ppwrctrl->b_hw_radio_off = _TRUE;
1237                         }
1238                         else
1239                         {
1240                                 ppwrctrl->rf_pwrstate = rf_off;
1241                                 ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1242                                 ppwrctrl->b_hw_radio_off = _FALSE;
1243                                 MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1244                         }
1245                 }
1246                 else
1247 #endif
1248                 {
1249                         ppwrctrl->rf_pwrstate = rf_off;
1250                         ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1251                         MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1252                 }
1253
1254                 ppwrctrl->rfoff_reason = 0;
1255                 ppwrctrl->b_hw_radio_off = _FALSE;
1256                 ppwrctrl->rf_pwrstate = rf_on;
1257                 if (padapter->ledpriv.LedControlHandler)
1258                         padapter->ledpriv.LedControlHandler(padapter, LED_CTL_POWER_ON);
1259         }
1260
1261         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1262         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1263         if (pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1264         {
1265                 // Enable register area 0x0-0xc.
1266                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
1267
1268                 //
1269                 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1270                 // our HW will be set in power-down mode if PDn source from all  functions are configured.
1271                 // 2010.10.06.
1272                 //
1273                 u1bTmp = rtw_read8(padapter, REG_MULTI_FUNC_CTRL);
1274                 u1bTmp |= WL_HWPDN_EN;
1275                 rtw_write8(padapter, REG_MULTI_FUNC_CTRL, u1bTmp);
1276         }
1277 #endif
1278 }
1279
1280 enum {
1281         Antenna_Lfet = 1,
1282         Antenna_Right = 2,
1283 };
1284
1285 //
1286 // 2010/08/09 MH Add for power down check.
1287 //
1288 static bool
1289 HalDetectPwrDownMode(
1290         IN PADAPTER                             Adapter
1291         )
1292 {
1293         u8      tmpvalue;
1294         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(Adapter);
1295         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1296
1297         EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue);
1298
1299         // 2010/08/25 MH INF priority > PDN Efuse value.
1300         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
1301         {
1302                 pHalData->pwrdown = _TRUE;
1303         }
1304         else
1305         {
1306                 pHalData->pwrdown = _FALSE;
1307         }
1308
1309         DBG_8723A("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
1310         return pHalData->pwrdown;
1311
1312 }       // HalDetectPwrDownMode
1313
1314
1315 //
1316 // 2010/08/26 MH Add for selective suspend mode check.
1317 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1318 // slim card.
1319 //
1320 static VOID
1321 HalDetectSelectiveSuspendMode(
1322         IN PADAPTER                             Adapter
1323         )
1324 {
1325         u8      tmpvalue;
1326         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1327         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1328
1329         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1330         // can not use FW to notify host the power state switch.
1331
1332         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1333
1334         DBG_8723A("HalDetectSelectiveSuspendMode(): SS ");
1335         if(tmpvalue & BIT1)
1336         {
1337                 DBG_8723A("Enable\n");
1338         }
1339         else
1340         {
1341                 DBG_8723A("Disable\n");
1342                 pdvobjpriv->RegUsbSS = _FALSE;
1343         }
1344
1345         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1346         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1347         {
1348                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1349
1350                 //if (!pMgntInfo->bRegDongleSS)
1351                 //{
1352                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1353                         pdvobjpriv->RegUsbSS = _FALSE;
1354                 //}
1355         }
1356 }       // HalDetectSelectiveSuspendMode
1357 /*-----------------------------------------------------------------------------
1358  * Function:    HwSuspendModeEnable92Cu()
1359  *
1360  * Overview:    HW suspend mode switch.
1361  *
1362  * Input:               NONE
1363  *
1364  * Output:      NONE
1365  *
1366  * Return:      NONE
1367  *
1368  * Revised History:
1369  *      When            Who             Remark
1370  *      08/23/2010      MHC             HW suspend mode switch test..
1371  *---------------------------------------------------------------------------*/
1372 static VOID
1373 HwSuspendModeEnable92Cu(
1374         IN      PADAPTER        pAdapter,
1375         IN      u8                      Type
1376         )
1377 {
1378 }       // HwSuspendModeEnable92Cu
1379
1380 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter )
1381 {
1382         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(pAdapter);
1383         u8      val8;
1384         rt_rf_power_state rfpowerstate = rf_off;
1385
1386         if(pAdapter->pwrctrlpriv.bHWPowerdown)
1387         {
1388                 val8 = rtw_read8(pAdapter, REG_HSISR);
1389                 DBG_8723A("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1390                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1391         }
1392         else // rf on/off
1393         {
1394                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1395                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1396                 DBG_8723A("GPIO_IN=%02x\n", val8);
1397                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1398         }
1399         return rfpowerstate;
1400 }       // HalDetectPwrDownMode
1401
1402 void _ps_open_RF(_adapter *padapter);
1403
1404 u32 rtl8723au_hal_init(PADAPTER Adapter)
1405 {
1406         u8      val8 = 0;
1407         u32     boundary, status = _SUCCESS;
1408         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1409         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1410         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1411         u8      is92C = IS_92C_SERIAL(pHalData->VersionID);
1412         rt_rf_power_state               eRfPowerStateToSet;
1413         u32 NavUpper = WiFiNavUpperUs;
1414
1415         u32 init_start_time = rtw_get_current_time();
1416
1417
1418 #ifdef DBG_HAL_INIT_PROFILING
1419
1420         enum HAL_INIT_STAGES {
1421                 HAL_INIT_STAGES_BEGIN = 0,
1422                 HAL_INIT_STAGES_INIT_PW_ON,
1423                 HAL_INIT_STAGES_INIT_LLTT,
1424                 HAL_INIT_STAGES_MISC01,
1425                 HAL_INIT_STAGES_DOWNLOAD_FW,
1426                 HAL_INIT_STAGES_MAC,
1427                 HAL_INIT_STAGES_BB,
1428                 HAL_INIT_STAGES_RF,
1429                 HAL_INIT_STAGES_MISC02,
1430                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1431                 HAL_INIT_STAGES_INIT_SECURITY,
1432                 HAL_INIT_STAGES_MISC11,
1433                 //HAL_INIT_STAGES_RF_PS,
1434                 HAL_INIT_STAGES_IQK,
1435                 HAL_INIT_STAGES_PW_TRACK,
1436                 HAL_INIT_STAGES_LCK,
1437                 HAL_INIT_STAGES_MISC21,
1438                 //HAL_INIT_STAGES_INIT_PABIAS,
1439                 #ifdef CONFIG_BT_COEXIST
1440                 HAL_INIT_STAGES_BT_COEXIST,
1441                 #endif
1442                 //HAL_INIT_STAGES_ANTENNA_SEL,
1443                 HAL_INIT_STAGES_INIT_HAL_DM,
1444                 HAL_INIT_STAGES_MISC31,
1445                 HAL_INIT_STAGES_END,
1446                 HAL_INIT_STAGES_NUM
1447         };
1448
1449         char * hal_init_stages_str[] = {
1450                 "HAL_INIT_STAGES_BEGIN",
1451                 "HAL_INIT_STAGES_INIT_PW_ON",
1452                 "HAL_INIT_STAGES_INIT_LLTT",
1453                 "HAL_INIT_STAGES_MISC01",
1454                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1455                 "HAL_INIT_STAGES_MAC",
1456                 "HAL_INIT_STAGES_BB",
1457                 "HAL_INIT_STAGES_RF",
1458                 "HAL_INIT_STAGES_MISC02",
1459                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1460                 "HAL_INIT_STAGES_INIT_SECURITY",
1461                 "HAL_INIT_STAGES_MISC11",
1462                 //"HAL_INIT_STAGES_RF_PS",
1463                 "HAL_INIT_STAGES_IQK",
1464                 "HAL_INIT_STAGES_PW_TRACK",
1465                 "HAL_INIT_STAGES_LCK",
1466                 "HAL_INIT_STAGES_MISC21",
1467                 //"HAL_INIT_STAGES_INIT_PABIAS",
1468                 #ifdef CONFIG_BT_COEXIST
1469                 "HAL_INIT_STAGES_BT_COEXIST",
1470                 #endif
1471                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1472                 "HAL_INIT_STAGES_INIT_HAL_DM",
1473                 "HAL_INIT_STAGES_MISC31",
1474                 "HAL_INIT_STAGES_END",
1475         };
1476
1477         int hal_init_profiling_i;
1478         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1479
1480         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1481                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1482
1483         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1484 #else
1485         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1486 #endif //DBG_HAL_INIT_PROFILING
1487
1488
1489
1490 _func_enter_;
1491
1492 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1493         if(Adapter->pwrctrlpriv.bkeepfwalive)
1494         {
1495                 _ps_open_RF(Adapter);
1496
1497                 if(pHalData->bIQKInitialized ){
1498                         rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1499                 }
1500                 else{
1501                         rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1502                         pHalData->bIQKInitialized = _TRUE;
1503                 }
1504                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
1505                 rtl8192c_PHY_LCCalibrate(Adapter);
1506
1507                 goto exit;
1508         }
1509
1510 //      pHalData->bMACFuncEnable = _FALSE;
1511         // Check if MAC has already power on. by tynli. 2011.05.27.
1512         val8 = rtw_read8(Adapter, REG_CR);
1513         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1514                          ("%s: REG_CR 0x100=0x%02x\n", __FUNCTION__, val8));
1515         //Fix 92DU-VC S3 hang with the reason is that secondary mac is not initialized.
1516         //0x100 value of first mac is 0xEA while 0x100 value of secondary is 0x00
1517         //by sherry 20111102
1518         if (val8 == 0xEA) {
1519                 pHalData->bMACFuncEnable = _FALSE;
1520         } else {
1521                 pHalData->bMACFuncEnable = _TRUE;
1522                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1523                                  ("%s: MAC has already power on\n", __FUNCTION__));
1524         }
1525
1526 #if 0
1527         if(bSupportRemoteWakeUp && Adapter->bWakeFromPnpSleep && pHalData->bMACFuncEnable)
1528         {
1529                 if(IS_HARDWARE_TYPE_8723AU(Adapter))
1530                 {
1531                         FW_CTRL_PS_MODE FwPwrMode = FW_PS_ACTIVE_MODE;
1532
1533                         pHalData->H2CStopInsertQueue = FALSE;
1534
1535                         if(pMgntInfo->mAssoc &&
1536                                 pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
1537                                 (pMgntInfo->PowerSaveControl.WoWLANLPSLevel > 0))
1538                         {
1539                                 RT_TRACE(COMP_POWER, DBG_LOUD, ("FwLPS: Active!!\n"));
1540                                 rtw_hal_set_hwreg(Adapter, HW_VAR_H2C_FW_PWRMODE, (pu1Byte)(&FwPwrMode));
1541                         }
1542
1543                         HalSetFWWoWlanMode92C(Adapter, FALSE);
1544
1545                         // Clear WoWLAN event FTISR[WWLAN_INT_EN].
1546                         if(IS_FW_8723A(Adapter) && Adapter->MgntInfo.FirmwareVersion < 10)
1547                         {
1548                                 // Fw revises the bug after version 10.
1549                                 value8 = rtw_read8(Adapter, REG_FTISR+3);
1550                                 rtw_write8(Adapter, REG_FTISR+3, value8|BIT2);
1551                         }
1552
1553                         SimpleInitializeAdapter8192CUsb(Adapter);
1554
1555                         pMgntInfo->init_adpt_in_progress = FALSE;
1556                         return RT_STATUS_SUCCESS;
1557                 }
1558         }
1559 #endif
1560
1561
1562 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1563         status = _InitPowerOn(Adapter);
1564         if(status == _FAIL){
1565                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1566                 goto exit;
1567         }
1568
1569 #ifdef CONFIG_BT_COEXIST
1570         //
1571         // 2010/09/23 MH Accordgin to Alfred's siggestion. we need to enable SIC to prevent HW
1572         // to enter suspend mode automatically. If host does not send SOF every 3ms. Or under DTM
1573         // test with rtl8188cu selective suspend enabler filter driver, WIN host will trigger the device to
1574         // enter suspend mode after some test (unknow reason now). We need to prevent the case otherwise
1575         // the register will be 0xea and all TX/RX path stop accidently.
1576         //
1577         //
1578         // 2010/10/01 MH If the OS is XP, host will trigger USB device to enter D3 mode. In CU HW design
1579         // it will enter suspend mode automatically. In slim combo card, the BT clock will be cut off if HW
1580         // enter suspend mode. We need to seperate differet case.
1581         //
1582         if (BT_IsBtExist(Adapter))
1583         {
1584 #if 0
1585 #if OS_WIN_FROM_VISTA(OS_VERSION)
1586                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo win7/vista need not enable SIC\n"));
1587 #else
1588                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo XP enable SIC\n"));
1589                 // 2010/10/15 MH According to Alfre's description, e need to enable bit14 at first an then enable bit12.
1590                 // Otherwise, HW will enter debug mode and 8051 can not work. We need to stay at test mode to enable SIC.
1591                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT14);
1592                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT12);
1593 #endif
1594 #endif
1595         }
1596 #endif // CONFIG_BT_COEXIST
1597
1598 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1599         if (!pregistrypriv->wifi_spec) {
1600                 boundary = TX_PAGE_BOUNDARY;
1601         } else {
1602                 // for WMM
1603                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
1604         }
1605
1606         if (!pHalData->bMACFuncEnable)
1607         {
1608                 status =  InitLLTTable(Adapter, boundary);
1609                 if(status == _FAIL){
1610                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1611                         goto exit;
1612                 }
1613         }
1614
1615
1616 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1617         if(pHalData->bRDGEnable){
1618                 _InitRDGSetting(Adapter);
1619         }
1620
1621
1622 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1623 {
1624         status = rtl8723a_FirmwareDownload(Adapter);
1625         if(status != _SUCCESS)
1626         {
1627                 Adapter->bFWReady = _FALSE;
1628                 pHalData->fw_ractrl = _FALSE;
1629                 DBG_8723A("fw download fail!\n");
1630                 goto exit;
1631         }
1632         else
1633         {
1634                 Adapter->bFWReady = _TRUE;
1635                 pHalData->fw_ractrl = _TRUE;
1636                 DBG_8723A("fw download ok!\n");
1637         }
1638 }
1639
1640         rtl8723a_InitializeFirmwareVars(Adapter);
1641
1642         if(pwrctrlpriv->reg_rfoff == _TRUE){
1643                 pwrctrlpriv->rf_pwrstate = rf_off;
1644         }
1645
1646         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1647         // HW GPIO pin. Before PHY_RFConfig8192C.
1648         //HalDetectPwrDownMode(Adapter);
1649         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1650         //HalDetectSelectiveSuspendMode(Adapter);
1651
1652         // Set RF type for BB/RF configuration
1653         _InitRFType(Adapter);//->_ReadRFType()
1654
1655         // Save target channel
1656         // <Roger_Notes> Current Channel will be updated again later.
1657         pHalData->CurrentChannel = 6;//default set to 6
1658
1659
1660 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1661 #if (HAL_MAC_ENABLE == 1)
1662         status = PHY_MACConfig8723A(Adapter);
1663         if(status == _FAIL)
1664         {
1665                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
1666                 goto exit;
1667         }
1668 #endif
1669
1670
1671 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1672         //
1673         //d. Initialize BB related configurations.
1674         //
1675 #if (HAL_BB_ENABLE == 1)
1676         status = PHY_BBConfig8723A(Adapter);
1677         if(status == _FAIL)
1678         {
1679                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
1680                 goto exit;
1681         }
1682 #endif
1683
1684         //
1685         // 2011/11/15 MH Add for tx power by rate fine tune. We need to call the function after BB config.
1686         // Because the tx power by rate table is inited in BB config.
1687         //
1688 //      HAL_AdjustPwrIndexDiffRateOffset(Adapter);
1689 //      HAL_AdjustPwrIndexbyRegistry(Adapter);
1690
1691 #if 0
1692         // The FW command register update must after MAC and FW init ready.
1693         if (Adapter->bFWReady == TRUE)
1694         {
1695                 if(pDevice->RegUsbSS)
1696                 {
1697                         u1Byte          u1H2CSSRf[3]={0};
1698
1699                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_ON(u1H2CSSRf,  1);
1700                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf, 500);
1701
1702                         FillH2CCmd92C(Adapter, H2C_SELECTIVE_SUSPEND_ROF_CMD, 3, u1H2CSSRf);
1703                         RT_TRACE(COMP_INIT, DBG_LOUD,
1704                         ("SS Set H2C_CMD for FW detect GPIO time=%d\n", GET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf)));
1705                 }
1706                 else
1707                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Non-SS Driver detect GPIO by itself\n"));
1708         }
1709         else
1710         {
1711                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Adapter->bFWReady == FALSE\n"));
1712                 // 2011/02/11 MH If FW is not ready, we can not enter seecitve suspend mode, otherwise,
1713                 // We can not support GPIO/PBC detection by FW with selectiev suspend support.
1714                 pDevice->RegUsbSS = FALSE;
1715         }
1716 #endif
1717
1718
1719 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1720 #if (HAL_RF_ENABLE == 1)
1721         status = PHY_RFConfig8723A(Adapter);
1722         if(status == _FAIL)
1723         {
1724                 DBG_8723A("PHY_RFConfig8723A fault !!\n");
1725                 goto exit;
1726         }
1727
1728         //reducing 80M spur
1729         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
1730         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1731         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
1732         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1733
1734         //RFSW Control
1735         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   //0x804[14]=0
1736         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        //0x870[6:5]=b'11
1737         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); //0x860[6:5]=b'00
1738
1739         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __FUNCTION__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
1740
1741 #endif
1742
1743         //
1744         // Joseph Note: Keep RfRegChnlVal for later use.
1745         //
1746         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
1747         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
1748
1749
1750 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1751         if (!pHalData->bMACFuncEnable) {
1752                 _InitQueueReservedPage(Adapter);
1753                 _InitTxBufferBoundary(Adapter);
1754         }
1755         _InitQueuePriority(Adapter);
1756         _InitPageBoundary(Adapter);
1757         _InitTransferPageSize(Adapter);
1758
1759         // Get Rx PHY status in order to report RSSI and others.
1760         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1761
1762         _InitInterrupt(Adapter);
1763         hal_init_macaddr(Adapter);//set mac_address
1764         _InitNetworkType(Adapter);//set msr
1765         _InitWMACSetting(Adapter);
1766         _InitAdaptiveCtrl(Adapter);
1767         _InitEDCA(Adapter);
1768         _InitRateFallback(Adapter);
1769         _InitRetryFunction(Adapter);
1770         InitUsbAggregationSetting(Adapter);
1771         _InitOperationMode(Adapter);//todo
1772         rtl8723a_InitBeaconParameters(Adapter);
1773         rtl8723a_InitBeaconMaxError(Adapter, _TRUE);
1774
1775 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1776         _InitAdhocWorkaroundParams(Adapter);
1777 #endif
1778
1779 #if ENABLE_USB_DROP_INCORRECT_OUT
1780         _InitHardwareDropIncorrectBulkOut(Adapter);
1781 #endif
1782
1783 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1784         // Enable lifetime check for the four ACs
1785         rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
1786 #ifdef CONFIG_TX_MCAST2UNI
1787         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1788         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1789 #else   // CONFIG_TX_MCAST2UNI
1790         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1791         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1792 #endif  // CONFIG_TX_MCAST2UNI
1793 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1794
1795
1796 #ifdef CONFIG_LED
1797         _InitHWLed(Adapter);
1798 #endif //CONFIG_LED
1799
1800 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1801         _BBTurnOnBlock(Adapter);
1802         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1803
1804 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1805         invalidate_cam_all(Adapter);
1806
1807 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1808         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1809         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
1810
1811         rtl8723a_InitAntenna_Selection(Adapter);
1812
1813         // HW SEQ CTRL
1814         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1815         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1816
1817         //
1818         // Disable BAR, suggested by Scott
1819         // 2010.04.09 add by hpfan
1820         //
1821         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1822
1823         if(pregistrypriv->wifi_spec)
1824                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1825
1826         // Move by Neo for USB SS from above setp
1827         _RfPowerSave(Adapter);
1828
1829         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
1830                 // 2010/08/26 MH Merge from 8192CE.
1831                 //sherry masked that it has been done in _RfPowerSave
1832                 //20110927
1833                 //recovery for 8192cu and 9723Au 20111017
1834                 if(pwrctrlpriv->rf_pwrstate == rf_on)
1835                 {
1836                         if(pHalData->bIQKInitialized ){
1837                                 rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1838                         } else {
1839                                 rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1840                                 pHalData->bIQKInitialized = _TRUE;
1841                         }
1842
1843         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
1844                         rtl8192c_odm_CheckTXPowerTracking(Adapter);
1845
1846         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
1847                         rtl8192c_PHY_LCCalibrate(Adapter);
1848
1849 #ifdef CONFIG_BT_COEXIST
1850                         rtl8723a_SingleDualAntennaDetection(Adapter);
1851 #endif
1852                 }
1853
1854
1855 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1856 #ifdef USB_INTERFERENCE_ISSUE
1857  //fixed USB interface interference issue
1858         rtw_write8(Adapter, 0xfe40, 0xe0);
1859         rtw_write8(Adapter, 0xfe41, 0x8d);
1860         rtw_write8(Adapter, 0xfe42, 0x80);
1861         rtw_write32(Adapter,0x20c,0xfd0320);
1862 #if 1
1863         //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus
1864         if(!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188
1865         {
1866                 // 0xE6=0x94
1867                 rtw_write8(Adapter, 0xFE40, 0xE6);
1868                 rtw_write8(Adapter, 0xFE41, 0x94);
1869                 rtw_write8(Adapter, 0xFE42, 0x80);
1870
1871                 // 0xE0=0x19
1872                 rtw_write8(Adapter, 0xFE40, 0xE0);
1873                 rtw_write8(Adapter, 0xFE41, 0x19);
1874                 rtw_write8(Adapter, 0xFE42, 0x80);
1875
1876                 // 0xE5=0x91
1877                 rtw_write8(Adapter, 0xFE40, 0xE5);
1878                 rtw_write8(Adapter, 0xFE41, 0x91);
1879                 rtw_write8(Adapter, 0xFE42, 0x80);
1880
1881                 // 0xE2=0x81
1882                 rtw_write8(Adapter, 0xFE40, 0xE2);
1883                 rtw_write8(Adapter, 0xFE41, 0x81);
1884                 rtw_write8(Adapter, 0xFE42, 0x80);
1885
1886         }
1887
1888 #endif
1889 #endif //USB_INTERFERENCE_ISSUE
1890
1891 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1892 //      _InitPABias(Adapter);
1893
1894 #ifdef CONFIG_BT_COEXIST
1895 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1896         // Init BT hw config.
1897         BT_InitHwConfig(Adapter);
1898 #endif
1899
1900 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1901         rtl8723a_InitHalDm(Adapter);
1902
1903 #if 0
1904         // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1905         // 2010/05/18 MH For SE series only now. Init GPIO detect time
1906         if(pDevice->RegUsbSS)
1907         {
1908                 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n"));
1909                 GpioDetectTimerStart8192CU(Adapter);    // Disable temporarily
1910         }
1911
1912         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1913         // suspend mode automatically.
1914         HwSuspendModeEnable92Cu(Adapter, _FALSE);
1915 #endif
1916
1917 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1918         rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1919
1920         // 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause.
1921         if (!IS_HARDWARE_TYPE_8192DU(Adapter) && ((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000))
1922         {
1923                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
1924                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __FUNCTION__));
1925         }
1926         else
1927         {
1928                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: IQK OK\n", __FUNCTION__));
1929         }
1930
1931 #ifdef CONFIG_XMIT_ACK
1932         //ack for xmit mgmt frames.
1933         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1934 #endif //CONFIG_XMIT_ACK
1935
1936         //_dbg_dump_macreg(padapter);
1937
1938 exit:
1939 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1940
1941         DBG_8723A("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1942
1943         #ifdef DBG_HAL_INIT_PROFILING
1944         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1945
1946         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1947                 DBG_8723A("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1948                         , hal_init_stages_str[hal_init_profiling_i]
1949                         , hal_init_stages_timestamp[hal_init_profiling_i]
1950                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1951                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1952                 );
1953         }
1954         #endif
1955
1956 _func_exit_;
1957
1958         return status;
1959 }
1960
1961
1962 #define SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1963 #ifdef SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1964 VOID
1965 phy_SsPwrSwitch92CU(
1966         IN      PADAPTER                        Adapter,
1967         IN      rt_rf_power_state       eRFPowerState,
1968         IN      int bRegSSPwrLvl
1969         )
1970 {
1971         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1972         u8                              value8;
1973
1974         switch( eRFPowerState )
1975         {
1976                 case rf_on:
1977                         if (bRegSSPwrLvl == 1)
1978                         {
1979                                 // 1. Enable MAC Clock. Can not be enabled now.
1980                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1981
1982                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1983                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1984                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1985
1986                                 // 3. restore BB, AFE control register.
1987                                 //RF
1988                                 if (pHalData->rf_type ==  RF_2T2R)
1989                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1990                                 else
1991                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1992                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1993                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1994
1995                                 //AFE
1996                                 //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]);
1997                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] );
1998                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 );
1999                                 if (pHalData->rf_type ==  RF_2T2R)
2000                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
2001                                 else if (pHalData->rf_type ==  RF_1T1R)
2002                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
2003
2004                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
2005                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
2006                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
2007                                 if (pHalData->rf_type ==  RF_2T2R)
2008                                 {
2009                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
2010                                 }
2011                         }
2012                         else            // Level 2 or others.
2013                         {
2014                                 //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2015                                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
2016
2017                                 // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2018                                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
2019                                 rtw_mdelay_os(1);
2020
2021                                 // 1. Enable MAC Clock. Can not be enabled now.
2022                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
2023
2024                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
2025                                 rtw_write8(Adapter, REG_SPS0_CTRL,
2026                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
2027
2028                                 // 3. restore BB, AFE control register.
2029                                 //RF
2030                                 if (pHalData->rf_type ==  RF_2T2R)
2031                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
2032                                 else
2033                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
2034                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
2035                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
2036
2037                                 //AFE
2038                                 if (pHalData->rf_type ==  RF_2T2R)
2039                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
2040                                 else if (pHalData->rf_type ==  RF_1T1R)
2041                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
2042
2043                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
2044                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
2045                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
2046                                 if (pHalData->rf_type ==  RF_2T2R)
2047                                 {
2048                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
2049                                 }
2050
2051                                 // 5. gated MAC Clock
2052                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2053                                 //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)|(BIT3));
2054
2055                                 {
2056                                         //u8                    eRFPath = RF_PATH_A,value8 = 0, retry = 0;
2057                                         u8              bytetmp;
2058                                         //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2059                                         // 2010/08/12 MH Add for B path under SS test.
2060                                         //if (pHalData->RF_Type ==  RF_2T2R)
2061                                                 //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2062
2063                                         bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
2064                                         rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
2065
2066                                         rtw_mdelay_os(10);
2067
2068                                         // Set BB reset at first
2069                                         rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16
2070
2071                                         // Enable TX
2072                                         rtw_write8(Adapter, REG_TXPAUSE, 0x0);
2073                                 }
2074                                 //CardSelectiveSuspendLeave(Adapter);
2075                         }
2076
2077                         break;
2078
2079                 case rf_sleep:
2080                 case rf_off:
2081                                 value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
2082                                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2083                                         value8 &= ~(BIT0);
2084                                 else
2085                                         value8 &= ~(BIT0|BIT3);
2086                                 if (bRegSSPwrLvl == 1)
2087                                 {
2088                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
2089                                         // Disable RF and BB only for SelectSuspend.
2090
2091                                         // 1. Set BB/RF to shutdown.
2092                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2093                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2094                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2095                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2096                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2097                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2098                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2099                                         if (pHalData->rf_type ==  RF_2T2R)
2100                                         {
2101                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2102                                         }
2103                                         else if (pHalData->rf_type ==  RF_1T1R)
2104                                         {
2105                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2106                                         }
2107                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2108                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2109
2110                                         // 2 .AFE control register to power down. bit[30:22]
2111                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2112                                         if (pHalData->rf_type ==  RF_2T2R)
2113                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2114                                         else if (pHalData->rf_type ==  RF_1T1R)
2115                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2116
2117                                         // 3. issue 3-wire command that RF set to power down.
2118                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2119                                         if (pHalData->rf_type ==  RF_2T2R)
2120                                         {
2121                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2122                                         }
2123
2124                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2125                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2126
2127                                         // 5. gated MAC Clock
2128                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2129                                 }
2130                                 else    // Level 2 or others.
2131                                 {
2132                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
2133                                         {
2134                                                 u8                      eRFPath = RF_PATH_A,value8 = 0;
2135                                                 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2136                                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2137                                                 // 2010/08/12 MH Add for B path under SS test.
2138                                                 //if (pHalData->RF_Type ==  RF_2T2R)
2139                                                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2140
2141                                                 value8 |= APSDOFF;
2142                                                 rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2143
2144                                                 // After switch APSD, we need to delay for stability
2145                                                 rtw_mdelay_os(10);
2146
2147                                                 // Set BB reset at first
2148                                                 value8 = 0 ;
2149                                                 value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2150                                                 rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2151                                         }
2152
2153                                         // Disable RF and BB only for SelectSuspend.
2154
2155                                         // 1. Set BB/RF to shutdown.
2156                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2157                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2158                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2159                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2160                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2161                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2162                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2163                                         if (pHalData->rf_type ==  RF_2T2R)
2164                                         {
2165                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2166                                         }
2167                                         else if (pHalData->rf_type ==  RF_1T1R)
2168                                         {
2169                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2170                                         }
2171                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2172                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2173
2174                                         // 2 .AFE control register to power down. bit[30:22]
2175                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2176                                         if (pHalData->rf_type ==  RF_2T2R)
2177                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2178                                         else if (pHalData->rf_type ==  RF_1T1R)
2179                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2180
2181                                         // 3. issue 3-wire command that RF set to power down.
2182                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2183                                         if (pHalData->rf_type ==  RF_2T2R)
2184                                         {
2185                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2186                                         }
2187
2188                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2189                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2190
2191                                         // 2010/10/13 MH/Isaachsu exchange sequence.
2192                                         //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2193                                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2194                                         rtw_mdelay_os(1);
2195
2196                                         // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2197                                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
2198
2199                                         // 5. gated MAC Clock
2200                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2201                                         //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)& ~(BIT3))
2202
2203                                         //CardSelectiveSuspendEnter(Adapter);
2204                                 }
2205
2206                         break;
2207
2208                 default:
2209                         break;
2210         }
2211
2212 }       // phy_PowerSwitch92CU
2213
2214 void _ps_open_RF(_adapter *padapter) {
2215         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2216         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
2217 }
2218
2219 void _ps_close_RF(_adapter *padapter){
2220         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2221         phy_SsPwrSwitch92CU(padapter, rf_off, 1);
2222 }
2223 #endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU
2224
2225
2226
2227 static VOID
2228 _DisableGPIO(
2229         IN      PADAPTER        Adapter
2230         )
2231 {
2232 /***************************************
2233 j. GPIO_PIN_CTRL 0x44[31:0]=0x000               //
2234 k. Value = GPIO_PIN_CTRL[7:0]
2235 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
2236 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
2237 n. LEDCFG 0x4C[15:0] = 0x8080
2238 ***************************************/
2239         u8      value8;
2240         u16     value16;
2241         u32     value32;
2242
2243         //1. Disable GPIO[7:0]
2244         rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
2245         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
2246         value8 = (u8) (value32&0x000000FF);
2247         value32 |= ((value8<<8) | 0x00FF0000);
2248         rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
2249
2250         //2. Disable GPIO[10:8]
2251         rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
2252             value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
2253         value8 = (u8) (value16&0x000F);
2254         value16 |= ((value8<<4) | 0x0780);
2255         rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
2256
2257         //3. Disable LED0 & 1
2258         rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
2259
2260         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
2261
2262 } //end of _DisableGPIO()
2263
2264 static VOID
2265 _ResetFWDownloadRegister(
2266         IN PADAPTER                     Adapter
2267         )
2268 {
2269         u32     value32;
2270
2271         value32 = rtw_read32(Adapter, REG_MCUFWDL);
2272         value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
2273         rtw_write32(Adapter, REG_MCUFWDL, value32);
2274         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
2275 }
2276
2277
2278 static int
2279 _DisableRF_AFE(
2280         IN PADAPTER                     Adapter
2281         )
2282 {
2283         int             rtStatus = _SUCCESS;
2284         u32                     pollingCount = 0;
2285         u8                      value8;
2286
2287         //disable RF/ AFE AD/DA
2288         value8 = APSDOFF;
2289         rtw_write8(Adapter, REG_APSD_CTRL, value8);
2290
2291
2292 #if (RTL8192CU_ASIC_VERIFICATION)
2293
2294         do
2295         {
2296                 if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){
2297                         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n"));
2298                         break;
2299                 }
2300
2301                 if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
2302                         //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n"));
2303                         return _FAIL;
2304                 }
2305
2306         }while(_TRUE);
2307
2308 #endif
2309
2310         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n"));
2311         return rtStatus;
2312
2313 }
2314
2315 static VOID
2316 _ResetBB(
2317         IN PADAPTER                     Adapter
2318         )
2319 {
2320         u16     value16;
2321
2322         //reset BB
2323         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2324         value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
2325         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2326         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
2327 }
2328
2329 static VOID
2330 _ResetMCU(
2331         IN PADAPTER                     Adapter
2332         )
2333 {
2334         u16     value16;
2335
2336         // reset MCU
2337         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2338         value16 &= ~FEN_CPUEN;
2339         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2340         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
2341 }
2342
2343 static VOID
2344 _DisableMAC_AFE_PLL(
2345         IN PADAPTER                     Adapter
2346         )
2347 {
2348         u32     value32;
2349
2350         //disable MAC/ AFE PLL
2351         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2352         value32 |= APDM_MAC;
2353         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2354
2355         value32 |= APFM_OFF;
2356         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2357         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
2358 }
2359
2360 static VOID
2361 _AutoPowerDownToHostOff(
2362         IN      PADAPTER                Adapter
2363         )
2364 {
2365         u32                     value32;
2366         rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
2367
2368         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2369
2370         value32 |= APDM_HOST;//card disable
2371         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2372         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
2373
2374         // set USB suspend
2375         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2376         value32 &= ~AFSM_PCIE;
2377         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2378
2379 }
2380
2381 static VOID
2382 _SetUsbSuspend(
2383         IN PADAPTER                     Adapter
2384         )
2385 {
2386         u32                     value32;
2387
2388         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2389
2390         // set USB suspend
2391         value32 |= AFSM_HSUS;
2392         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2393
2394         //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
2395         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
2396
2397 }
2398
2399 static VOID
2400 _DisableRFAFEAndResetBB(
2401         IN PADAPTER                     Adapter
2402         )
2403 {
2404 /**************************************
2405 a.      TXPAUSE 0x522[7:0] = 0xFF             //Pause MAC TX queue
2406 b.      RF path 0 offset 0x00 = 0x00            // disable RF
2407 c.      APSD_CTRL 0x600[7:0] = 0x40
2408 d.      SYS_FUNC_EN 0x02[7:0] = 0x16            //reset BB state machine
2409 e.      SYS_FUNC_EN 0x02[7:0] = 0x14            //reset BB state machine
2410 ***************************************/
2411         u8 eRFPath = 0,value8 = 0;
2412         rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2413         PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2414
2415         value8 |= APSDOFF;
2416         rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2417
2418         value8 = 0 ;
2419         value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2420         rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2421
2422         value8 &=( ~FEN_BB_GLB_RSTn );
2423         rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
2424
2425         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
2426 }
2427
2428 static VOID
2429 _ResetDigitalProcedure1(
2430         IN      PADAPTER                        Adapter,
2431         IN      bool                            bWithoutHWSM
2432         )
2433 {
2434
2435         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2436
2437         if(pHalData->FirmwareVersion <=  0x20){
2438                 #if 0
2439                 /*****************************
2440                 f.      SYS_FUNC_EN 0x03[7:0]=0x54              // reset MAC register, DCORE
2441                 g.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2442                 ******************************/
2443                 u4Byte  value32 = 0;
2444                 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
2445                 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
2446                 #else
2447                 /*****************************
2448                 f.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2449                 g.      SYS_FUNC_EN 0x02[10]= 0                 // reset MCU register, (8051 reset)
2450                 h.      SYS_FUNC_EN 0x02[15-12]= 5              // reset MAC register, DCORE
2451                 i.     SYS_FUNC_EN 0x02[10]= 1                  // enable MCU register, (8051 enable)
2452                 ******************************/
2453                         u16 valu16 = 0;
2454                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2455
2456                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2457                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
2458
2459                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
2460                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
2461
2462                         #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2463                         {
2464                                 u8 val;
2465                                 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2466                                         DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2467                         }
2468                         #endif
2469
2470
2471                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2472                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
2473
2474
2475                 #endif
2476         }
2477         else{
2478                 u8 retry_cnts = 0;
2479
2480                 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
2481                 { //IF fw in RAM code, do reset
2482
2483                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2484                         if(Adapter->bFWReady){
2485                                 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
2486                                 // HRCV INT to influence 8051 reset.
2487                                 rtw_write8(Adapter, REG_FWIMR, 0x20);
2488
2489                                 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
2490
2491                                 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
2492                                 {
2493                                         rtw_udelay_os(50);//PlatformStallExecution(50);//us
2494                                 }
2495
2496                                 if(retry_cnts >= 100){
2497                                         DBG_8723A("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
2498                                         // if 8051 reset fail we trigger GPIO 0 for LA
2499                                         //PlatformEFIOWrite4Byte(       Adapter,
2500                                         //                                              REG_GPIO_PIN_CTRL,
2501                                         //                                              0x00010100);
2502                                         // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
2503                                         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50);   //Reset MAC and Enable 8051
2504                                         rtw_mdelay_os(10);
2505                                 }
2506                                 else {
2507                                         //DBG_8723A("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
2508                                 }
2509                         }
2510                         else {
2511                                 DBG_8723A("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
2512                         }
2513                 }
2514                 else{
2515                         //DBG_8723A("%s =====> 8051 in ROM.\n", __FUNCTION__);
2516                 }
2517
2518                 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2519                 {
2520                         u8 val;
2521                         if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2522                                 DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2523                 }
2524                 #endif
2525
2526                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54);   //Reset MAC and Enable 8051
2527         }
2528
2529         // Clear rpwm value for initial toggle bit trigger.
2530         rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
2531
2532         if(bWithoutHWSM){
2533         /*****************************
2534                 Without HW auto state machine
2535         g.      SYS_CLKR 0x08[15:0] = 0x30A3                    //disable MAC clock
2536         h.      AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2537         i.      AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2538         j.      SYS_ISO_CTRL 0x00[7:0] = 0xF9                   // isolated digital to PON
2539         ******************************/
2540                 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
2541                 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
2542                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2543                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
2544                 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
2545         }
2546         else
2547         {
2548                 // Disable all RF/BB power
2549                 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2550         }
2551         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
2552
2553 }
2554
2555 static VOID
2556 _ResetDigitalProcedure2(
2557         IN      PADAPTER                        Adapter
2558 )
2559 {
2560 /*****************************
2561 k.      SYS_FUNC_EN 0x03[7:0] = 0x44                    // disable ELDR runction
2562 l.      SYS_CLKR 0x08[15:0] = 0x3083                    // disable ELDR clock
2563 m.      SYS_ISO_CTRL 0x01[7:0] = 0x83                   // isolated ELDR to PON
2564 ******************************/
2565         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
2566         //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
2567         //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
2568
2569         rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
2570         rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
2571 }
2572
2573 static VOID
2574 _DisableAnalog(
2575         IN PADAPTER                     Adapter,
2576         IN bool                 bWithoutHWSM
2577         )
2578 {
2579         u16 value16 = 0;
2580         u8 value8=0;
2581         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2582
2583         if(bWithoutHWSM){
2584         /*****************************
2585         n.      LDOA15_CTRL 0x20[7:0] = 0x04            // disable A15 power
2586         o.      LDOV12D_CTRL 0x21[7:0] = 0x54           // disable digital core power
2587         r.      When driver call disable, the ASIC will turn off remaining clock automatically
2588         ******************************/
2589
2590                 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
2591                 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
2592
2593                 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
2594                 value8 &= (~LDV12_EN);
2595                 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
2596                 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
2597         }
2598
2599 /*****************************
2600 h.      SPS0_CTRL 0x11[7:0] = 0x23                      //enter PFM mode
2601 i.      APS_FSMCO 0x04[15:0] = 0x4802           // set USB suspend
2602 ******************************/
2603
2604
2605         value8 = 0x23;
2606         if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2607                 value8 |= BIT3;
2608
2609         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2610
2611
2612         if(bWithoutHWSM)
2613         {
2614                 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
2615                 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
2616                 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
2617                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2618         }
2619         else
2620         {
2621                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2622         }
2623
2624         rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
2625
2626         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2627
2628  #if 0
2629         //tynli_test for suspend mode.
2630         if(!bWithoutHWSM){
2631                 rtw_write8(Adapter, 0xfe10, 0x19);
2632         }
2633 #endif
2634
2635         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
2636 }
2637
2638 static void rtl8723au_hw_power_down(_adapter *padapter)
2639 {
2640         u8      u1bTmp;
2641
2642         DBG_8723A("PowerDownRTL8723U\n");
2643
2644
2645         // 1. Run Card Disable Flow
2646         // Done before this function call.
2647
2648         // 2. 0x04[16] = 0                      // reset WLON
2649         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
2650         rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
2651
2652         // 3. 0x04[12:11] = 2b'11 // enable suspend
2653         // Done before this function call.
2654
2655         // 4. 0x04[15] = 1                      // enable PDN
2656         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
2657         rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
2658 }
2659
2660 //
2661 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
2662 // First created by tynli. 2011.01.28.
2663 //
2664 VOID
2665 CardDisableRTL8723U(
2666         PADAPTER                        Adapter
2667 )
2668 {
2669         u8              u1bTmp;
2670 //      PMGNT_INFO      pMgntInfo       = &(Adapter->MgntInfo);
2671
2672         DBG_8723A("CardDisableRTL8723U\n");
2673
2674         // USB-MF Card Disable Flow
2675         // 1. Run LPS WL RFOFF flow
2676         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_enter_lps_flow);
2677
2678         // 2. 0x1F[7:0] = 0             // turn off RF
2679         rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2680
2681         //      ==== Reset digital sequence   ======
2682         if((rtw_read8(Adapter, REG_MCUFWDL)&BIT7) &&
2683                 Adapter->bFWReady) //8051 RAM code
2684         {
2685                 rtl8723a_FirmwareSelfReset(Adapter);
2686         }
2687
2688         // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
2689         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2690         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, (u1bTmp&(~BIT2)));
2691
2692         // g.   MCUFWDL 0x80[1:0]=0                             // reset MCU ready status
2693         rtw_write8(Adapter, REG_MCUFWDL, 0x00);
2694
2695         //      ==== Reset digital sequence end ======
2696 //      if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) )
2697         {
2698                 // Card disable power action flow
2699                 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_disable_flow);
2700         }
2701
2702         // Reset MCU IO Wrapper, added by Roger, 2011.08.30.
2703         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2704         rtw_write8(Adapter, REG_RSV_CTRL+1, (u1bTmp&(~BIT0)));
2705         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2706         rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp|BIT0);
2707
2708         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2709         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2710
2711 }
2712
2713
2714 u32 rtl8723au_hal_deinit(PADAPTER padapter)
2715 {
2716         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(padapter);
2717
2718
2719         DBG_8723A("==> %s\n", __FUNCTION__);
2720
2721 #ifdef CONFIG_BT_COEXIST
2722         BT_HaltProcess(padapter);
2723 #endif
2724         // 2011/02/18 To Fix RU LNA  power leakage problem. We need to execute below below in
2725         // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
2726         // IC. Accord to johnny's opinion, only RU need the support.
2727         CardDisableRTL8723U(padapter);
2728
2729         return _SUCCESS;
2730 }
2731
2732
2733 unsigned int rtl8723au_inirp_init(PADAPTER Adapter)
2734 {
2735         u8 i;
2736         struct recv_buf *precvbuf;
2737         uint    status;
2738         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2739         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2740         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2741         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2742 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2743         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2744         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2745 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2746
2747 _func_enter_;
2748
2749         _read_port = pintfhdl->io_ops._read_port;
2750
2751         status = _SUCCESS;
2752
2753         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2754
2755         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2756
2757         //issue Rx irp to receive data
2758         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2759         for(i=0; i<NR_RECVBUFF; i++)
2760         {
2761                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2762                 {
2763                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2764                         status = _FAIL;
2765                         goto exit;
2766                 }
2767
2768                 precvbuf++;
2769                 precvpriv->free_recv_buf_queue_cnt--;
2770         }
2771
2772 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2773         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2774         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2775         {
2776                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2777                 status = _FAIL;
2778         }
2779         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2780         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2781         pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2782         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2783 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2784
2785 exit:
2786
2787         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2788
2789 _func_exit_;
2790
2791         return status;
2792
2793 }
2794
2795 unsigned int rtl8723au_inirp_deinit(PADAPTER Adapter)
2796 {
2797 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2798         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2799         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2800 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2801         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2802
2803         rtw_read_port_cancel(Adapter);
2804 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2805         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2806         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2807         pHalData->IntrMask[0]=0x0;
2808         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2809         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2810 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2811         return _SUCCESS;
2812 }
2813
2814
2815 static u32
2816 _GetChannelGroup(
2817         IN      u32     channel
2818         )
2819 {
2820         //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2821
2822         if(channel < 3){        // Channel 1~3
2823                 return 0;
2824         }
2825         else if(channel < 9){ // Channel 4~9
2826                 return 1;
2827         }
2828
2829         return 2;                               // Channel 10~14
2830 }
2831
2832
2833 //-------------------------------------------------------------------
2834 //
2835 //      EEPROM/EFUSE Content Parsing
2836 //
2837 //-------------------------------------------------------------------
2838 static void
2839 _ReadIDs(
2840         IN      PADAPTER        Adapter,
2841         IN      u8*             PROMContent,
2842         IN      bool            AutoloadFail
2843         )
2844 {
2845         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2846
2847         if(_FALSE == AutoloadFail){
2848                 // VID, PID
2849                 pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
2850                 pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
2851
2852                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2853                 pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
2854                 pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
2855
2856         }
2857         else{
2858                 pHalData->EEPROMVID      = EEPROM_Default_VID;
2859                 pHalData->EEPROMPID      = EEPROM_Default_PID;
2860
2861                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2862                 pHalData->EEPROMCustomerID      = EEPROM_Default_CustomerID;
2863                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2864
2865         }
2866
2867         // For customized behavior.
2868         if((pHalData->EEPROMVID == 0x103C) || (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2869                 pHalData->CustomerID = RT_CID_819x_HP;
2870
2871         //      Decide CustomerID according to VID/DID or EEPROM
2872         switch(pHalData->EEPROMCustomerID)
2873         {
2874                 case EEPROM_CID_DEFAULT:
2875                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2876                                 pHalData->CustomerID = RT_CID_DLINK;
2877                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2878                                 pHalData->CustomerID = RT_CID_DLINK;
2879                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2880                                 pHalData->CustomerID = RT_CID_DLINK;
2881                         break;
2882                 case EEPROM_CID_WHQL:
2883 /*
2884                         Adapter->bInHctTest = TRUE;
2885
2886                         pMgntInfo->bSupportTurboMode = FALSE;
2887                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2888
2889                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2890                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2891                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2892
2893                         pMgntInfo->keepAliveLevel = 0;
2894
2895                         Adapter->bUnloadDriverwhenS3S4 = FALSE;
2896 */
2897                         break;
2898                 default:
2899                         pHalData->CustomerID = RT_CID_DEFAULT;
2900                         break;
2901
2902         }
2903
2904         MSG_8723A("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
2905         MSG_8723A("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
2906         MSG_8723A("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
2907         MSG_8723A("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
2908
2909         MSG_8723A("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
2910
2911 }
2912
2913
2914 static VOID
2915 _ReadMACAddress(
2916         IN      PADAPTER        Adapter,
2917         IN      u8*             PROMContent,
2918         IN      bool            AutoloadFail
2919         )
2920 {
2921         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2922
2923         if(_FALSE == AutoloadFail){
2924                 //Read Permanent MAC address and set value to hardware
2925                 _rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
2926         }
2927         else{
2928                 //Random assigh MAC address
2929                 u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
2930                 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2931                 _rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
2932         }
2933         DBG_8723A("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
2934         //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
2935         //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
2936
2937 }
2938
2939 static VOID
2940 _ReadBoardType(
2941         IN      PADAPTER        Adapter,
2942         IN      u8*             PROMContent,
2943         IN      bool            AutoloadFail
2944         )
2945 {
2946         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2947         u32                     value32;
2948         u8                      boardType = BOARD_USB_DONGLE;
2949
2950         if(AutoloadFail){
2951                 if(IS_8723_SERIES(pHalData->VersionID))
2952                         pHalData->rf_type = RF_1T1R;
2953                 else
2954                         pHalData->rf_type = RF_2T2R;
2955
2956                 pHalData->BoardType = boardType;
2957                 return;
2958         }
2959
2960         boardType = PROMContent[EEPROM_NORMAL_BoardType];
2961         boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5]
2962         boardType >>= 5;
2963
2964         pHalData->BoardType = boardType;
2965         MSG_8723A("_ReadBoardType(%x)\n",pHalData->BoardType);
2966
2967         if (boardType == BOARD_USB_High_PA)
2968                 pHalData->ExternalPA = 1;
2969 }
2970
2971
2972 static VOID
2973 _ReadLEDSetting(
2974         IN      PADAPTER        Adapter,
2975         IN      u8*             PROMContent,
2976         IN      bool            AutoloadFail
2977         )
2978 {
2979         struct led_priv *pledpriv = &(Adapter->ledpriv);
2980         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2981 #ifdef CONFIG_SW_LED
2982         pledpriv->bRegUseLed = _TRUE;
2983
2984         //
2985         // Led mode
2986         //
2987         switch(pHalData->CustomerID)
2988         {
2989                 case RT_CID_DEFAULT:
2990                         pledpriv->LedStrategy = SW_LED_MODE1;
2991                         pledpriv->bRegUseLed = _TRUE;
2992                         break;
2993
2994                 case RT_CID_819x_HP:
2995                         pledpriv->LedStrategy = SW_LED_MODE6;
2996                         break;
2997
2998                 default:
2999                         pledpriv->LedStrategy = SW_LED_MODE1;
3000                         break;
3001         }
3002
3003         if( BOARD_MINICARD == pHalData->BoardType )
3004         {
3005                 pledpriv->LedStrategy = SW_LED_MODE6;
3006         }
3007         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
3008 #else // HW LED
3009         pledpriv->LedStrategy = HW_LED;
3010 #endif //CONFIG_SW_LED
3011 }
3012
3013 static VOID
3014 _ReadThermalMeter(
3015         IN      PADAPTER        Adapter,
3016         IN      u8*     PROMContent,
3017         IN      bool            AutoloadFail
3018         )
3019 {
3020         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3021         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3022         u8      tempval;
3023
3024         //
3025         // ThermalMeter from EEPROM
3026         //
3027         if(!AutoloadFail)
3028                 tempval = PROMContent[EEPROM_THERMAL_METER];
3029         else
3030                 tempval = EEPROM_Default_ThermalMeter;
3031
3032         pHalData->EEPROMThermalMeter = (tempval&0x1f);  //[4:0]
3033
3034         if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
3035                 pdmpriv->bAPKThermalMeterIgnore = _TRUE;
3036
3037 #if 0
3038         if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
3039                 pHalData->EEPROMThermalMeter = 0x12;
3040 #endif
3041
3042         pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
3043
3044         //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
3045
3046 }
3047
3048 static VOID
3049 _ReadRFSetting(
3050         IN      PADAPTER        Adapter,
3051         IN      u8*     PROMContent,
3052         IN      bool            AutoloadFail
3053         )
3054 {
3055 }
3056
3057
3058 #if 0
3059 static VOID
3060 readAntennaDiversity(
3061         IN      PADAPTER        pAdapter,
3062         IN      u8                      *hwinfo,
3063         IN      bool            AutoLoadFail
3064         )
3065 {
3066
3067         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3068         struct registry_priv    *registry_par = &pAdapter->registrypriv;
3069
3070         if(!AutoLoadFail)
3071         {
3072                 // Antenna Diversity setting.
3073                 if(registry_par->antdiv_cfg == 2) // 2: From Efuse
3074                         pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
3075                 else
3076                         pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON,
3077
3078                 DBG_8723A("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
3079
3080                 //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
3081                 //      pHalData->AntDivCfg = 0;
3082         }
3083         else
3084         {
3085                 pHalData->AntDivCfg = 0;
3086         }
3087
3088 }
3089 #endif
3090 // Read HW power down mode selection
3091 static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8  AutoloadFail)
3092 {
3093         if(AutoloadFail){
3094                 Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
3095                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
3096         }
3097         else    {
3098                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3099                         Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
3100                 //else
3101                         //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
3102
3103
3104                 //hw power down mode selection , 0:rf-off / 1:power down
3105
3106                 if(Adapter->registrypriv.hwpdn_mode==2)
3107                         Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
3108                 else
3109                         Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
3110
3111                 // decide hw if support remote wakeup function
3112                 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
3113                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
3114
3115                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3116                         //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
3117
3118                 DBG_8723A("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
3119                 Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
3120
3121                 DBG_8723A("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
3122
3123         }
3124
3125 }
3126
3127
3128
3129
3130
3131
3132 VOID
3133 Hal_EfuseParsePIDVID_8723AU(
3134         IN      PADAPTER                pAdapter,
3135         IN      u8*                     hwinfo,
3136         IN      bool                    AutoLoadFail
3137         )
3138 {
3139         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3140
3141         if(AutoLoadFail)
3142         {
3143                 pHalData->EEPROMVID = 0;
3144                 pHalData->EEPROMPID = 0;
3145         }
3146         else
3147         {
3148                         // VID, PID
3149                 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723AU]);
3150                 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723AU]);
3151
3152         }
3153
3154         MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
3155         MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
3156 }
3157
3158
3159 static void
3160 Hal_EfuseParseMACAddr_8723AU(
3161         IN      PADAPTER                padapter,
3162         IN      u8*                     hwinfo,
3163         IN      bool                    AutoLoadFail
3164         )
3165 {
3166         u16                     i, usValue;
3167         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
3168         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3169
3170         if (AutoLoadFail)
3171         {
3172 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
3173                 for (i=0; i<6; i++)
3174                         pEEPROM->mac_addr[i] = sMacAddr[i];
3175         }
3176         else
3177         {
3178                 //Read Permanent MAC address
3179 #if 1
3180                 _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], ETH_ALEN);
3181 #else
3182                 for(i=0; i<6; i+=2)
3183                 {
3184                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
3185                         *((u16*)(&pEEPROM->mac_addr[i])) = usValue;
3186                 }
3187 #endif
3188         }
3189 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
3190
3191         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
3192                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address=%02x:%02x:%02x:%02x:%02x:%02x\n",
3193                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3194                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3195                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
3196 }
3197
3198
3199 #ifdef CONFIG_EFUSE_CONFIG_FILE
3200 static u32 Hal_readPGDataFromConfigFile(
3201         PADAPTER        padapter)
3202 {
3203         u32 i;
3204         struct file *fp;
3205         mm_segment_t fs;
3206         u8 temp[3];
3207         loff_t pos = 0;
3208         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3209         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
3210
3211
3212         temp[2] = 0; // add end of string '\0'
3213
3214         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
3215         if (IS_ERR(fp)) {
3216                 pEEPROM->bloadfile_fail_flag= _TRUE;
3217                 DBG_8723A("Error, Efuse configure file doesn't exist.\n");
3218                 return _FAIL;
3219         }
3220
3221         fs = get_fs();
3222         set_fs(KERNEL_DS);
3223
3224         DBG_8723A("Efuse configure file:\n");
3225         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
3226                 vfs_read(fp, temp, 2, &pos);
3227                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
3228                 pos += 1; // Filter the space character
3229                 DBG_8723A("%02X \n", PROMContent[i]);
3230         }
3231         DBG_8723A("\n");
3232         set_fs(fs);
3233
3234         filp_close(fp, NULL);
3235
3236         pEEPROM->bloadfile_fail_flag= _FALSE;
3237         return _SUCCESS;
3238 }
3239
3240
3241 static void
3242 Hal_ReadMACAddrFromFile_8723AU(
3243         PADAPTER                padapter
3244         )
3245 {
3246         u32 i;
3247         struct file *fp;
3248         mm_segment_t fs;
3249         u8 source_addr[18];
3250         loff_t pos = 0;
3251         u32 curtime = rtw_get_current_time();
3252         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3253         u8 *head, *end;
3254
3255         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
3256         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
3257
3258         _rtw_memset(source_addr, 0, 18);
3259         _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
3260
3261         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
3262         if (IS_ERR(fp)) {
3263                 pEEPROM->bloadmac_fail_flag = _TRUE;
3264                 DBG_8723A("Error, wifi mac address file doesn't exist.\n");
3265         } else {
3266                 fs = get_fs();
3267                 set_fs(KERNEL_DS);
3268
3269                 DBG_8723A("wifi mac address:\n");
3270                 vfs_read(fp, source_addr, 18, &pos);
3271                 source_addr[17] = ':';
3272
3273                 head = end = source_addr;
3274                 for (i=0; i<ETH_ALEN; i++) {
3275                         while (end && (*end != ':') )
3276                                 end++;
3277
3278                         if (end && (*end == ':') )
3279                                 *end = '\0';
3280
3281                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
3282
3283                         if (end) {
3284                                 end++;
3285                                 head = end;
3286                         }
3287                         DBG_8723A("%02x \n", pEEPROM->mac_addr[i]);
3288                 }
3289                 DBG_8723A("\n");
3290                 set_fs(fs);
3291
3292                 filp_close(fp, NULL);
3293         }
3294
3295         if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
3296                 (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
3297                 pEEPROM->mac_addr[0] = 0x00;
3298                 pEEPROM->mac_addr[1] = 0xe0;
3299                 pEEPROM->mac_addr[2] = 0x4c;
3300                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
3301                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
3302                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
3303         }
3304
3305         pEEPROM->bloadmac_fail_flag = _FALSE;
3306
3307          DBG_8723A("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
3308                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3309                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3310                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
3311 }
3312 #endif //CONFIG_EFUSE_CONFIG_FILE
3313
3314
3315 static VOID
3316 readAdapterInfo(
3317         IN      PADAPTER        padapter
3318         )
3319 {
3320         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3321         //PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3322         u8                      hwinfo[HWSET_MAX_SIZE];
3323
3324 #ifdef CONFIG_EFUSE_CONFIG_FILE
3325         Hal_readPGDataFromConfigFile(padapter);
3326 #else //CONFIG_EFUSE_CONFIG_FILE
3327         Hal_InitPGData(padapter, hwinfo);
3328 #endif  //CONFIG_EFUSE_CONFIG_FILE
3329         Hal_EfuseParseIDCode(padapter, hwinfo);
3330         Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3331         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3332 #ifdef CONFIG_EFUSE_CONFIG_FILE
3333         Hal_ReadMACAddrFromFile_8723AU(padapter);
3334 #else //CONFIG_EFUSE_CONFIG_FILE
3335         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3336 #endif
3337         Hal_EfuseParseTxPowerInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3338         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3339         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3340
3341         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3342         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3343         _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3344 //      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3345 //      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3346         Hal_EfuseParseAntennaDiversity(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3347
3348         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3349         Hal_EfuseParseCustomerID(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3350         Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3351         Hal_EfuseParseXtal_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3352         //
3353         // The following part initialize some vars by PG info.
3354         //
3355         Hal_InitChannelPlan(padapter);
3356
3357
3358
3359         //hal_CustomizedBehavior_8723U(Adapter);
3360
3361 //      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
3362         DBG_8723A("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
3363 }
3364
3365 static void _ReadPROMContent(
3366         IN PADAPTER             Adapter
3367         )
3368 {
3369         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
3370         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3371         u8                      PROMContent[HWSET_MAX_SIZE]={0};
3372         u8                      eeValue;
3373         u32                     i;
3374         u16                     value16;
3375
3376         eeValue = rtw_read8(Adapter, REG_9346CR);
3377         // To check system boot selection.
3378         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
3379         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
3380
3381
3382         DBG_8723A("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
3383                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
3384
3385         //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
3386
3387         //if(IS_HARDWARE_TYPE_8723A(Adapter))
3388         //      readAdapterInfo_8723U(Adapter);
3389         //else
3390                 readAdapterInfo(Adapter);
3391 }
3392
3393
3394 static VOID
3395 _InitOtherVariable(
3396         IN PADAPTER             Adapter
3397         )
3398 {
3399         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3400
3401
3402         //if(Adapter->bInHctTest){
3403         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
3404         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
3405         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
3406         //      pMgntInfo->keepAliveLevel = 0;
3407         //}
3408
3409
3410 }
3411
3412 static VOID
3413 _ReadRFType(
3414         IN      PADAPTER        Adapter
3415         )
3416 {
3417         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3418
3419 #if DISABLE_BB_RF
3420         pHalData->rf_chip = RF_PSEUDO_11N;
3421 #else
3422         pHalData->rf_chip = RF_6052;
3423 #endif
3424 }
3425
3426 void _ReadSilmComboMode(PADAPTER Adapter)
3427 {
3428         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3429
3430         pHalData->SlimComboDbg = _FALSE;        // Default is not debug mode.
3431
3432         // 2010/11/22 MH We need to enter debug mode for TSMA and UMC A cut
3433         //if ((Adapter->chip_type == RTL8188C_8192C) &&
3434 /*
3435         if (IS_HARDWARE_TYPE_8192CU(Adapter) &&
3436                 (pHalData->BoardType == BOARD_USB_COMBO))
3437         {
3438                 switch (pHalData->VersionID)
3439                 {
3440                         case    VERSION_NORMAL_TSMC_CHIP_88C:
3441                         case    VERSION_NORMAL_TSMC_CHIP_92C:
3442                         case    VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
3443                         case    VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
3444                         case    VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
3445                         case    VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
3446                                 if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
3447                                         pHalData->SlimComboDbg = _TRUE;
3448
3449                                 break;
3450
3451                         case    VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
3452                         case    VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
3453                         case    VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
3454                                 // 2011/02/15 MH UNC-B cut ECO fail, we need to support slim combo debug mode.
3455                                 if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
3456                                         pHalData->SlimComboDbg = _TRUE;
3457                                 break;
3458
3459                         default:
3460                                 break;
3461                 }
3462
3463         }
3464 */
3465 }
3466
3467 //
3468 //      Description:
3469 //              We should set Efuse cell selection to WiFi cell in default.
3470 //
3471 //      Assumption:
3472 //              PASSIVE_LEVEL
3473 //
3474 //      Added by Roger, 2010.11.23.
3475 //
3476 void
3477 hal_EfuseCellSel(
3478         IN      PADAPTER        Adapter
3479         )
3480 {
3481         u32                     value32;
3482
3483         value32 = rtw_read32(Adapter, EFUSE_TEST);
3484         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
3485         rtw_write32(Adapter, EFUSE_TEST, value32);
3486 }
3487
3488 static int _ReadAdapterInfo8723AU(PADAPTER      Adapter)
3489 {
3490         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3491         u32 start=rtw_get_current_time();
3492
3493         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
3494
3495         //Efuse_InitSomeVar(Adapter);
3496
3497         hal_EfuseCellSel(Adapter);
3498
3499         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
3500         _ReadPROMContent(Adapter);
3501
3502         // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
3503         _ReadSilmComboMode(Adapter);
3504
3505         _InitOtherVariable(Adapter);
3506
3507         //MSG_8723A("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
3508
3509         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", rtw_get_passing_time_ms(start));
3510
3511         return _SUCCESS;
3512 }
3513
3514
3515 static void ReadAdapterInfo8723AU(PADAPTER Adapter)
3516 {
3517         // Read EEPROM size before call any EEPROM function
3518         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
3519
3520         _ReadAdapterInfo8723AU(Adapter);
3521 }
3522
3523
3524 #define GPIO_DEBUG_PORT_NUM 0
3525 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
3526 {
3527
3528         u32 gpioctrl;
3529         DBG_8723A("==> trigger_gpio_0...\n");
3530         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
3531         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
3532         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
3533         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3534         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
3535         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3536         DBG_8723A("<=== trigger_gpio_0...\n");
3537
3538 }
3539
3540 /*
3541  * If variable not handled here,
3542  * some variables will be processed in SetHwReg8723A()
3543  */
3544 void SetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3545 {
3546         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3547
3548 _func_enter_;
3549
3550         switch(variable)
3551         {
3552                 case HW_VAR_RXDMA_AGG_PG_TH:
3553 #ifdef CONFIG_USB_RX_AGGREGATION
3554                         {
3555                                 u8 threshold = *val;
3556                                 if (threshold == 0)
3557                                         threshold = pHalData->UsbRxAggPageCount;
3558                                 SetHwReg8723A(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
3559                         }
3560 #endif
3561                         break;
3562
3563                 case HW_VAR_SET_RPWM:
3564                         rtw_write8(Adapter, REG_USB_HRPWM, *val);
3565                         break;
3566
3567                 case HW_VAR_TRIGGER_GPIO_0:
3568                         rtl8192cu_trigger_gpio_0(Adapter);
3569                         break;
3570
3571                 default:
3572                         SetHwReg8723A(Adapter, variable, val);
3573                         break;
3574         }
3575
3576 _func_exit_;
3577 }
3578
3579 /*
3580  * If variable not handled here,
3581  * some variables will be processed in GetHwReg8723A()
3582  */
3583 void GetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3584 {
3585         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3586
3587 _func_enter_;
3588
3589         switch (variable)
3590         {
3591                 default:
3592                         GetHwReg8723A(Adapter, variable, val);
3593                         break;
3594         }
3595
3596 _func_exit_;
3597 }
3598
3599 //
3600 //      Description:
3601 //              Query setting of specified variable.
3602 //
3603 u8
3604 GetHalDefVar8192CUsb(
3605         IN      PADAPTER                                Adapter,
3606         IN      HAL_DEF_VARIABLE                eVariable,
3607         IN      PVOID                                   pValue
3608         )
3609 {
3610         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3611         u8                      bResult = _SUCCESS;
3612
3613         switch(eVariable)
3614         {
3615                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3616                         *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
3617                         break;
3618                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3619                         #ifdef CONFIG_ANTENNA_DIVERSITY
3620                         *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
3621                         #endif
3622                         break;
3623                 case HAL_DEF_CURRENT_ANTENNA:
3624                         #ifdef CONFIG_ANTENNA_DIVERSITY
3625                         *(( u8*)pValue) = pHalData->CurAntenna;
3626                         #endif
3627                         break;
3628                 case HAL_DEF_DRVINFO_SZ:
3629                         *(( u32*)pValue) = DRVINFO_SZ;
3630                         break;
3631                 case HAL_DEF_MAX_RECVBUF_SZ:
3632                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
3633                         break;
3634                 case HAL_DEF_RX_PACKET_OFFSET:
3635                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
3636                         break;
3637                 case HAL_DEF_DBG_DUMP_RXPKT:
3638                         *(( u8*)pValue) = pHalData->bDumpRxPkt;
3639                         break;
3640                 case HAL_DEF_DBG_DM_FUNC:
3641                         *(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
3642                         break;
3643                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3644                         *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K;
3645                         break;
3646                 case HW_DEF_ODM_DBG_FLAG:
3647                         {
3648                                 u8Byte  DebugComponents = *((u32*)pValue);
3649                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3650                                 printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );
3651                         }
3652                         break;
3653                 default:
3654                         //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable));
3655                         bResult = _FAIL;
3656                         break;
3657         }
3658
3659         return bResult;
3660 }
3661
3662
3663
3664
3665 //
3666 //      Description:
3667 //              Change default setting of specified variable.
3668 //
3669 u8
3670 SetHalDefVar8192CUsb(
3671         IN      PADAPTER                                Adapter,
3672         IN      HAL_DEF_VARIABLE                eVariable,
3673         IN      PVOID                                   pValue
3674         )
3675 {
3676         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3677         u8                      bResult = _SUCCESS;
3678
3679         switch(eVariable)
3680         {
3681                 case HAL_DEF_DBG_DUMP_RXPKT:
3682                         pHalData->bDumpRxPkt = *(( u8*)pValue);
3683                         break;
3684                 case HAL_DEF_DBG_DM_FUNC:
3685                         {
3686                                 u8 dm_func = *(( u8*)pValue);
3687                                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3688                                 DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3689
3690                                 if(dm_func == 0){ //disable all dynamic func
3691                                         podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
3692                                         DBG_8723A("==> Disable all dynamic function...\n");
3693                                 }
3694                                 else if(dm_func == 1){//disable DIG
3695                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
3696                                         DBG_8723A("==> Disable DIG...\n");
3697                                 }
3698                                 else if(dm_func == 2){//disable High power
3699                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
3700                                 }
3701                                 else if(dm_func == 3){//disable tx power tracking
3702                                         podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
3703                                         DBG_8723A("==> Disable tx power tracking...\n");
3704                                 }
3705                                 else if(dm_func == 4){//disable BT coexistence
3706                                         pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
3707                                 }
3708                                 else if(dm_func == 5){//disable antenna diversity
3709                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
3710                                 }
3711                                 else if(dm_func == 6){//turn on all dynamic func
3712                                         if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
3713                                         {
3714                                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3715                                                 pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
3716                                         }
3717                                         pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
3718                                         podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
3719                                         DBG_8723A("==> Turn on all dynamic function...\n");
3720                                 }
3721                         }
3722                         break;
3723                 case HW_DEF_FA_CNT_DUMP:
3724                         {
3725                                 u8 bRSSIDump = *((u8*)pValue);
3726                                 PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
3727                                 if(bRSSIDump)
3728                                         pDM_Odm->DebugComponents        =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
3729                                 else
3730                                         pDM_Odm->DebugComponents        = 0;
3731
3732                         }
3733                         break;
3734                 case HW_DEF_ODM_DBG_FLAG:
3735                         {
3736                                 u8Byte  DebugComponents = *((u8Byte*)pValue);
3737                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3738                                 pDM_Odm->DebugComponents = DebugComponents;
3739                         }
3740                         break;
3741                 default:
3742                         //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
3743                         bResult = _FAIL;
3744                         break;
3745         }
3746
3747         return bResult;
3748 }
3749
3750 /*
3751 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
3752 {
3753         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(padapter);
3754         unsigned int BrateCfg = 0;
3755
3756
3757         if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
3758                 BrateCfg = mask  & 0x15F;
3759         else    //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
3760                 BrateCfg = mask  & 0x159;
3761
3762         BrateCfg |= 0x01; // default enable 1M ACK rate
3763
3764         return BrateCfg;
3765 }
3766 */
3767 void _update_response_rate(_adapter *padapter,unsigned int mask)
3768 {
3769         u8      RateIndex = 0;
3770         // Set RRSR rate table.
3771         rtw_write8(padapter, REG_RRSR, mask&0xff);
3772         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
3773
3774         // Set RTS initial rate
3775         while(mask > 0x1)
3776         {
3777                 mask = (mask>> 1);
3778                 RateIndex++;
3779         }
3780         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
3781 }
3782
3783 void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id,u8 rssi_level )
3784 {
3785         //volatile unsigned int result;
3786         u8      init_rate=0;
3787         u8      networkType, raid;
3788         u32     mask,rate_bitmap;
3789         u8      shortGIrate = _FALSE;
3790         int     supportRateNum = 0;
3791         struct sta_info *psta;
3792         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
3793         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3794         struct mlme_ext_priv    *pmlmeext = &padapter->mlmeextpriv;
3795         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3796         WLAN_BSSID_EX           *cur_network = &(pmlmeinfo->network);
3797 #ifdef CONFIG_CONCURRENT_MODE
3798         if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
3799                 pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
3800 #endif //CONFIG_CONCURRENT_MODE
3801
3802         if (mac_id >= NUM_STA) //CAM_SIZE
3803         {
3804                 return;
3805         }
3806
3807         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
3808         if(psta == NULL)
3809         {
3810                 return;
3811         }
3812
3813         switch (mac_id)
3814         {
3815                 case 0:// for infra mode
3816 #ifdef CONFIG_CONCURRENT_MODE
3817                 case 2:// first station uses macid=0, second station uses macid=2
3818 #endif
3819                         supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
3820                         networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
3821                         //pmlmeext->cur_wireless_mode = networkType;
3822                         raid = networktype_to_raid(networkType);
3823
3824                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3825                         mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
3826
3827
3828                         if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
3829                         {
3830                                 shortGIrate = _TRUE;
3831                         }
3832
3833                         break;
3834
3835                 case 1://for broadcast/multicast
3836                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3837                         if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
3838                                 networkType = WIRELESS_11B;
3839                         else
3840                                 networkType = WIRELESS_11G;
3841                         raid = networktype_to_raid(networkType);
3842
3843                         mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
3844
3845                         break;
3846
3847                 default: //for each sta in IBSS
3848                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3849                         networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
3850                         //pmlmeext->cur_wireless_mode = networkType;
3851                         raid = networktype_to_raid(networkType);
3852
3853                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3854
3855
3856                         //todo: support HT in IBSS
3857
3858                         break;
3859         }
3860
3861         //mask &=0x0fffffff;
3862         rate_bitmap = 0x0fffffff;
3863 #ifdef  CONFIG_ODM_REFRESH_RAMASK
3864         {
3865                 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
3866                 printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
3867                         __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
3868         }
3869 #endif
3870
3871         mask &= rate_bitmap;
3872         mask |= ((raid<<28)&0xf0000000);
3873
3874
3875         init_rate = get_highest_rate_idx(mask)&0x3f;
3876
3877         if(pHalData->fw_ractrl == _TRUE)
3878         {
3879                 u8 arg = 0;
3880
3881                 //arg = (cam_idx-4)&0x1f;//MACID
3882                 arg = mac_id&0x1f;//MACID
3883
3884                 arg |= BIT(7);
3885
3886                 if (shortGIrate==_TRUE)
3887                         arg |= BIT(5);
3888
3889                 DBG_8723A("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
3890
3891                 rtl8192c_set_raid_cmd(padapter, mask, arg);
3892
3893         }
3894         else
3895         {
3896                 if (shortGIrate==_TRUE)
3897                         init_rate |= BIT(6);
3898
3899                 rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
3900         }
3901
3902
3903         //set ra_id
3904         psta->raid = raid;
3905         psta->init_rate = init_rate;
3906
3907         //set correct initial date rate for each mac_id
3908         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
3909 }
3910
3911 static void rtl8723au_init_default_value(PADAPTER padapter)
3912 {
3913         rtl8723a_init_default_value(padapter);
3914 }
3915
3916 static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
3917 {
3918         u8 bResult = _TRUE;
3919         switch(efunc_id){
3920
3921                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
3922                 case HAL_USB_SELECT_SUSPEND:
3923                         {
3924                                 u8 bfwpoll = *(( u8*)val);
3925                                 rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
3926                         }
3927                         break;
3928                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
3929
3930                 default:
3931                         break;
3932         }
3933         return bResult;
3934 }
3935
3936 void rtl8723au_set_hal_ops(_adapter * padapter)
3937 {
3938         struct hal_ops  *pHalFunc = &padapter->HalFunc;
3939
3940 _func_enter_;
3941
3942         padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
3943         if(padapter->HalData == NULL){
3944                 DBG_8723A("cant not alloc memory for HAL DATA \n");
3945         }
3946         //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
3947         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
3948
3949         pHalFunc->hal_init = &rtl8723au_hal_init;
3950         pHalFunc->hal_deinit = &rtl8723au_hal_deinit;
3951
3952         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
3953
3954         pHalFunc->inirp_init = &rtl8723au_inirp_init;
3955         pHalFunc->inirp_deinit = &rtl8723au_inirp_deinit;
3956
3957         pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv;
3958         pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv;
3959
3960         pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv;
3961         pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv;
3962 #ifdef CONFIG_SW_LED
3963         pHalFunc->InitSwLeds = &rtl8723au_InitSwLeds;
3964         pHalFunc->DeInitSwLeds = &rtl8723au_DeInitSwLeds;
3965 #else //case of hw led or no led
3966         pHalFunc->InitSwLeds = NULL;
3967         pHalFunc->DeInitSwLeds = NULL;
3968 #endif//CONFIG_SW_LED
3969
3970         pHalFunc->init_default_value = &rtl8723au_init_default_value;
3971         pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure;
3972         pHalFunc->read_adapter_info = &ReadAdapterInfo8723AU;
3973
3974         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
3975         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
3976
3977         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
3978
3979         pHalFunc->SetHwRegHandler = &SetHwReg8723AU;
3980         pHalFunc->GetHwRegHandler = &GetHwReg8723AU;
3981         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
3982         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
3983
3984         pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
3985
3986         pHalFunc->hal_xmit = &rtl8192cu_hal_xmit;
3987         pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit;
3988         pHalFunc->hal_xmitframe_enqueue = &rtl8723au_hal_xmitframe_enqueue;
3989
3990 #ifdef CONFIG_HOSTAPD_MLME
3991         pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
3992 #endif
3993         pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
3994
3995         rtl8723a_set_hal_ops(pHalFunc);
3996
3997 _func_exit_;
3998
3999 }