hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_conf.h>
  23 #include <osdep_service.h>
  24 #include <drv_types.h>
  25 #include <rtw_efuse.h>
  26
  27
  28 #include <HalPwrSeqCmd.h>
  29 #include <Hal8723PwrSeq.h>
  30 #include <rtl8723a_hal.h>
  31 #include <rtl8723a_led.h>
  32
  33 #ifdef CONFIG_IOL
  34 #include <rtw_iol.h>
  35 #endif
  36
  37 #ifdef CONFIG_EFUSE_CONFIG_FILE
  38 #include <linux/fs.h>
  39 #include <asm/uaccess.h>
  40 #endif //CONFIG_EFUSE_CONFIG_FILE
  41
  42 #include <usb_ops.h>
  43 #include <usb_hal.h>
  44 #include <usb_osintf.h>
  45
  46 #if DISABLE_BB_RF
  47         #define         HAL_MAC_ENABLE  0
  48         #define         HAL_BB_ENABLE           0
  49         #define         HAL_RF_ENABLE           0
  50 #else
  51         #define         HAL_MAC_ENABLE  1
  52         #define         HAL_BB_ENABLE           1
  53         #define         HAL_RF_ENABLE           1
  54 #endif
  55
  56
  57 static VOID
  58 _ConfigChipOutEP(
  59         IN      PADAPTER        pAdapter,
  60         IN      u8              NumOutPipe
  61         )
  62 {
  63         u8                      value8;
  64         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  65
  66         pHalData->OutEpQueueSel = 0;
  67         pHalData->OutEpNumber   = 0;
  68
  69         // Normal and High queue
  70         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  71
  72         if(value8 & USB_NORMAL_SIE_EP_MASK){
  73                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  74                 pHalData->OutEpNumber++;
  75         }
  76
  77         if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
  78                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  79                 pHalData->OutEpNumber++;
  80         }
  81
  82         // Low queue
  83         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  84         if(value8 & USB_NORMAL_SIE_EP_MASK){
  85                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  86                 pHalData->OutEpNumber++;
  87         }
  88
  89         // TODO: Error recovery for this case
  90         //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber));
  91
  92 }
  93
  94 static bool HalUsbSetQueuePipeMapping8192CUsb(
  95         IN      PADAPTER        pAdapter,
  96         IN      u8              NumInPipe,
  97         IN      u8              NumOutPipe
  98         )
  99 {
 100         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
 101         bool                    result          = _FALSE;
 102
 103         _ConfigChipOutEP(pAdapter, NumOutPipe);
 104
 105         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
 106         if(1 == pHalData->OutEpNumber){
 107                 if(1 != NumInPipe){
 108                         return result;
 109                 }
 110         }
 111
 112         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
 113
 114         return result;
 115
 116 }
 117
 118 void rtl8192cu_interface_configure(_adapter *padapter)
 119 {
 120         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
 121         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 122
 123         if (pdvobjpriv->ishighspeed == _TRUE)
 124         {
 125                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
 126         }
 127         else
 128         {
 129                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 130         }
 131
 132         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 133
 134 #ifdef CONFIG_USB_TX_AGGREGATION
 135         pHalData->UsbTxAggMode          = 1;
 136         pHalData->UsbTxAggDescNum       = 0x6;  // only 4 bits
 137 #endif
 138
 139 #ifdef CONFIG_USB_RX_AGGREGATION
 140         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 141         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 142         pHalData->UsbRxAggBlockTimeout  = 0x6;
 143         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 144         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 145 #endif
 146
 147         HalUsbSetQueuePipeMapping8192CUsb(padapter,
 148                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 149
 150 }
 151
 152 static u8 _InitPowerOn(PADAPTER padapter)
 153 {
 154         u8              status = _SUCCESS;
 155         u16                     value16=0;
 156         u8                      value8 = 0;
 157
 158         // RSV_CTRL 0x1C[7:0] = 0x00                    // unlock ISO/CLK/Power control register
 159         rtw_write8(padapter, REG_RSV_CTRL, 0x0);
 160
 161         // HW Power on sequence
 162         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_enable_flow ))
 163                                 return _FAIL;
 164
 165         // 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051
 166                         value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
 167                         rtw_write8(padapter,REG_APS_FSMCO+2,(value8|BIT3));
 168
 169                         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 170                         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 171                         value16 = rtw_read16(padapter, REG_CR);
 172                         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 173                                                 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC | CALTMR_EN);
 174                         rtw_write16(padapter, REG_CR, value16);
 175
 176         //for Efuse PG, suggest by Jackie 2011.11.23
 177         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
 178
 179         return status;
 180 }
 181
 182
 183 static void _dbg_dump_macreg(_adapter *padapter)
 184 {
 185         u32 offset = 0;
 186         u32 val32 = 0;
 187         u32 index =0 ;
 188         for(index=0;index<64;index++)
 189         {
 190                 offset = index*4;
 191                 val32 = rtw_read32(padapter,offset);
 192                 DBG_8723A("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 193         }
 194 }
 195
 196 //-------------------------------------------------------------------------
 197 //
 198 // LLT R/W/Init function
 199 //
 200 //-------------------------------------------------------------------------
 201 static u8 _LLTWrite(
 202         IN  PADAPTER    Adapter,
 203         IN      u32             address,
 204         IN      u32             data
 205         )
 206 {
 207         u8      status = _SUCCESS;
 208         int             count = 0;
 209         u32             value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 210
 211         rtw_write32(Adapter, REG_LLT_INIT, value);
 212
 213         //polling
 214         do{
 215
 216                 value = rtw_read32(Adapter, REG_LLT_INIT);
 217                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 218                         break;
 219                 }
 220
 221                 if(count > POLLING_LLT_THRESHOLD){
 222                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
 223                         status = _FAIL;
 224                         break;
 225                 }
 226         }while(count++);
 227
 228         return status;
 229
 230 }
 231
 232
 233 static u8 _LLTRead(
 234         IN  PADAPTER    Adapter,
 235         IN      u32             address
 236         )
 237 {
 238         int             count = 0;
 239         u32             value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
 240
 241         rtw_write32(Adapter, REG_LLT_INIT, value);
 242
 243         //polling and get value
 244         do{
 245
 246                 value = rtw_read32(Adapter, REG_LLT_INIT);
 247                 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
 248                         return (u8)value;
 249                 }
 250
 251                 if(count > POLLING_LLT_THRESHOLD){
 252                         //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
 253                         break;
 254                 }
 255         }while(count++);
 256
 257         return 0xFF;
 258
 259 }
 260
 261
 262 //---------------------------------------------------------------
 263 //
 264 //      MAC init functions
 265 //
 266 //---------------------------------------------------------------
 267 static VOID
 268 _SetMacID(
 269         IN  PADAPTER Adapter, u8* MacID
 270         )
 271 {
 272         u32 i;
 273         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 274 #ifdef  CONFIG_CONCURRENT_MODE
 275                 if(Adapter->iface_type == IFACE_PORT1)
 276                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 277                 else
 278 #endif
 279                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 280         }
 281 }
 282
 283 static VOID
 284 _SetBSSID(
 285         IN  PADAPTER Adapter, u8* BSSID
 286         )
 287 {
 288         u32 i;
 289         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 290 #ifdef  CONFIG_CONCURRENT_MODE
 291                 if(Adapter->iface_type == IFACE_PORT1)
 292                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 293                 else
 294 #endif
 295                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 296         }
 297 }
 298
 299
 300 // Shall USB interface init this?
 301 static VOID
 302 _InitInterrupt(
 303         IN  PADAPTER Adapter
 304         )
 305 {
 306         u32     value32;
 307
 308         // HISR - turn all on
 309         value32 = 0xFFFFFFFF;
 310         rtw_write32(Adapter, REG_HISR, value32);
 311
 312         // HIMR - turn all on
 313         rtw_write32(Adapter, REG_HIMR, value32);
 314 }
 315
 316
 317 static VOID
 318 _InitQueueReservedPage(
 319         IN  PADAPTER Adapter
 320         )
 321 {
 322         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 323         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 324
 325         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 326         u32                     numHQ           = 0;
 327         u32                     numLQ           = 0;
 328         u32                     numNQ           = 0;
 329         u32                     numPubQ;
 330         u32                     value32;
 331         u8                      value8;
 332         bool            bWiFiConfig     = pregistrypriv->wifi_spec;
 333         //u32                   txQPageNum, txQPageUnit,txQRemainPage;
 334
 335         { //for WMM
 336                 //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
 337
 338                 numPubQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_PUBQ:NORMAL_PAGE_NUM_PUBQ;
 339
 340                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 341                 {
 342                         numHQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
 343                 }
 344
 345                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 346                 {
 347                         numLQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
 348                 }
 349                 // NOTE: This step shall be proceed before writting REG_RQPN.
 350                 if(pHalData->OutEpQueueSel & TX_SELE_NQ){
 351                         numNQ = bWiFiConfig?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
 352                 }
 353                 value8 = (u8)_NPQ(numNQ);
 354                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 355         }
 356
 357         // TX DMA
 358         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 359         rtw_write32(Adapter, REG_RQPN, value32);
 360 }
 361
 362 static VOID
 363 _InitTxBufferBoundary(
 364         IN  PADAPTER Adapter
 365         )
 366 {
 367         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 368         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 369
 370         u8      txpktbuf_bndy;
 371
 372         if(!pregistrypriv->wifi_spec){
 373                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 374         }
 375         else{//for WMM
 376                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 377         }
 378
 379         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 380         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 381         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 382         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 383 #if 1
 384         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 385 #else
 386         txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
 387         txdmactrl &= ~BCN_HEAD_MASK;
 388         txdmactrl |= BCN_HEAD(txpktbuf_bndy);
 389         PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
 390 #endif
 391 }
 392
 393 static VOID
 394 _InitPageBoundary(
 395         IN  PADAPTER Adapter
 396         )
 397 {
 398         // RX Page Boundary
 399         //srand(static_cast<unsigned int>(time(NULL)) );
 400         u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
 401
 402         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 403
 404         // TODO: ?? shall we set tx boundary?
 405 }
 406
 407
 408 static VOID
 409 _InitNormalChipRegPriority(
 410         IN      PADAPTER        Adapter,
 411         IN      u16             beQ,
 412         IN      u16             bkQ,
 413         IN      u16             viQ,
 414         IN      u16             voQ,
 415         IN      u16             mgtQ,
 416         IN      u16             hiQ
 417         )
 418 {
 419         u16 value16             = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 420
 421         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 422                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 423                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 424
 425         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 426 }
 427
 428 static VOID
 429 _InitNormalChipOneOutEpPriority(
 430         IN      PADAPTER Adapter
 431         )
 432 {
 433         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 434
 435         u16     value = 0;
 436         switch(pHalData->OutEpQueueSel)
 437         {
 438                 case TX_SELE_HQ:
 439                         value = QUEUE_HIGH;
 440                         break;
 441                 case TX_SELE_LQ:
 442                         value = QUEUE_LOW;
 443                         break;
 444                 case TX_SELE_NQ:
 445                         value = QUEUE_NORMAL;
 446                         break;
 447                 default:
 448                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 449                         break;
 450         }
 451
 452         _InitNormalChipRegPriority(Adapter,
 453                                                                 value,
 454                                                                 value,
 455                                                                 value,
 456                                                                 value,
 457                                                                 value,
 458                                                                 value
 459                                                                 );
 460
 461 }
 462
 463 static VOID
 464 _InitNormalChipTwoOutEpPriority(
 465         IN      PADAPTER Adapter
 466         )
 467 {
 468         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 469         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 470         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 471
 472
 473         u16     valueHi = 0;
 474         u16     valueLow = 0;
 475
 476         switch(pHalData->OutEpQueueSel)
 477         {
 478                 case (TX_SELE_HQ | TX_SELE_LQ):
 479                         valueHi = QUEUE_HIGH;
 480                         valueLow = QUEUE_LOW;
 481                         break;
 482                 case (TX_SELE_NQ | TX_SELE_LQ):
 483                         valueHi = QUEUE_NORMAL;
 484                         valueLow = QUEUE_LOW;
 485                         break;
 486                 case (TX_SELE_HQ | TX_SELE_NQ):
 487                         valueHi = QUEUE_HIGH;
 488                         valueLow = QUEUE_NORMAL;
 489                         break;
 490                 default:
 491                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 492                         break;
 493         }
 494
 495         if(!pregistrypriv->wifi_spec ){
 496                 beQ             = valueLow;
 497                 bkQ             = valueLow;
 498                 viQ             = valueHi;
 499                 voQ             = valueHi;
 500                 mgtQ    = valueHi;
 501                 hiQ             = valueHi;
 502         }
 503         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 504                 beQ             = valueLow;
 505                 bkQ             = valueHi;
 506                 viQ             = valueHi;
 507                 voQ             = valueLow;
 508                 mgtQ    = valueHi;
 509                 hiQ             = valueHi;
 510         }
 511
 512         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 513
 514 }
 515
 516 static VOID
 517 _InitNormalChipThreeOutEpPriority(
 518         IN      PADAPTER Adapter
 519         )
 520 {
 521         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 522         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 523
 524         if(!pregistrypriv->wifi_spec ){// typical setting
 525                 beQ             = QUEUE_LOW;
 526                 bkQ             = QUEUE_LOW;
 527                 viQ             = QUEUE_NORMAL;
 528                 voQ             = QUEUE_HIGH;
 529                 mgtQ    = QUEUE_HIGH;
 530                 hiQ             = QUEUE_HIGH;
 531         }
 532         else{// for WMM
 533                 beQ             = QUEUE_LOW;
 534                 bkQ             = QUEUE_NORMAL;
 535                 viQ             = QUEUE_NORMAL;
 536                 voQ             = QUEUE_HIGH;
 537                 mgtQ    = QUEUE_HIGH;
 538                 hiQ             = QUEUE_HIGH;
 539         }
 540         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 541 }
 542
 543 static VOID
 544 _InitNormalChipQueuePriority(
 545         IN      PADAPTER Adapter
 546         )
 547 {
 548         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 549
 550         switch(pHalData->OutEpNumber)
 551         {
 552                 case 1:
 553                         _InitNormalChipOneOutEpPriority(Adapter);
 554                         break;
 555                 case 2:
 556                         _InitNormalChipTwoOutEpPriority(Adapter);
 557                         break;
 558                 case 3:
 559                         _InitNormalChipThreeOutEpPriority(Adapter);
 560                         break;
 561                 default:
 562                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 563                         break;
 564         }
 565
 566
 567 }
 568
 569 static VOID
 570 _InitQueuePriority(
 571         IN  PADAPTER Adapter
 572         )
 573 {
 574         _InitNormalChipQueuePriority(Adapter);
 575 }
 576
 577 static VOID
 578 _InitHardwareDropIncorrectBulkOut(
 579         IN  PADAPTER Adapter
 580         )
 581 {
 582         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 583         value32 |= DROP_DATA_EN;
 584         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 585 }
 586
 587 static VOID
 588 _InitNetworkType(
 589         IN  PADAPTER Adapter
 590         )
 591 {
 592         u32     value32;
 593
 594         value32 = rtw_read32(Adapter, REG_CR);
 595
 596         // TODO: use the other function to set network type
 597 #if RTL8191C_FPGA_NETWORKTYPE_ADHOC
 598         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
 599 #else
 600         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 601 #endif
 602         rtw_write32(Adapter, REG_CR, value32);
 603 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 604 }
 605
 606 static VOID
 607 _InitTransferPageSize(
 608         IN  PADAPTER Adapter
 609         )
 610 {
 611         // Tx page size is always 128.
 612
 613         u8      value8;
 614         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 615         rtw_write8(Adapter, REG_PBP, value8);
 616 }
 617
 618 static VOID
 619 _InitDriverInfoSize(
 620         IN  PADAPTER    Adapter,
 621         IN      u8              drvInfoSize
 622         )
 623 {
 624         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 625 }
 626
 627 static VOID
 628 _InitWMACSetting(
 629         IN  PADAPTER Adapter
 630         )
 631 {
 632         //u4Byte                        value32;
 633         //u16                   value16;
 634         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 635
 636         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 637         //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 638          // don't turn on AAP, it will allow all packets to driver
 639         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 640 #if (1 == RTL8192C_RX_PACKET_INCLUDE_CRC)
 641         pHalData->ReceiveConfig |= ACRC32;
 642 #endif
 643
 644         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 645         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 646
 647         // Accept all multicast address
 648         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 649         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 650
 651
 652         // Accept all data frames
 653         //value16 = 0xFFFF;
 654         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 655
 656         // 2010.09.08 hpfan
 657         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 658         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 659         //value16 = 0x400;
 660         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 661
 662         // Accept all management frames
 663         //value16 = 0xFFFF;
 664         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 665
 666         //enable RX_SHIFT bits
 667         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 668
 669 }
 670
 671 static VOID
 672 _InitAdaptiveCtrl(
 673         IN  PADAPTER Adapter
 674         )
 675 {
 676         u16     value16;
 677         u32     value32;
 678
 679         // Response Rate Set
 680         value32 = rtw_read32(Adapter, REG_RRSR);
 681         value32 &= ~RATE_BITMAP_ALL;
 682         value32 |= RATE_RRSR_CCK_ONLY_1M;
 683         rtw_write32(Adapter, REG_RRSR, value32);
 684
 685         // CF-END Threshold
 686         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 687
 688         // SIFS (used in NAV)
 689         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 690         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 691
 692         // Retry Limit
 693         value16 = _LRL(0x30) | _SRL(0x30);
 694         rtw_write16(Adapter, REG_RL, value16);
 695
 696 }
 697
 698 static VOID
 699 _InitRateFallback(
 700         IN  PADAPTER Adapter
 701         )
 702 {
 703         // Set Data Auto Rate Fallback Retry Count register.
 704         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 705         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 706         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 707         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 708
 709 }
 710
 711
 712 static VOID
 713 _InitEDCA(
 714         IN  PADAPTER Adapter
 715         )
 716 {
 717         // Set Spec SIFS (used in NAV)
 718         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 719         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 720
 721         // Set SIFS for CCK
 722         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 723
 724         // Set SIFS for OFDM
 725         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 726
 727         // TXOP
 728         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 729         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 730         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 731         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 732 }
 733
 734 #ifdef CONFIG_LED
 735 static void _InitHWLed(PADAPTER Adapter)
 736 {
 737         struct led_priv *pledpriv = &(Adapter->ledpriv);
 738
 739         if( pledpriv->LedStrategy != HW_LED)
 740                 return;
 741
 742 // HW led control
 743 // to do ....
 744 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 745
 746 }
 747 #endif //CONFIG_LED
 748
 749 static VOID
 750 _InitRDGSetting(
 751         IN      PADAPTER Adapter
 752         )
 753 {
 754         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 755         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 756         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 757 }
 758
 759 static VOID
 760 _InitRxSetting(
 761         IN      PADAPTER Adapter
 762         )
 763 {
 764         rtw_write32(Adapter, REG_MACID, 0x87654321);
 765         rtw_write32(Adapter, 0x0700, 0x87654321);
 766 }
 767
 768 static VOID
 769 _InitRetryFunction(
 770         IN  PADAPTER Adapter
 771         )
 772 {
 773         u8      value8;
 774
 775         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 776         value8 |= EN_AMPDU_RTY_NEW;
 777         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 778
 779         // Set ACK timeout
 780         rtw_write8(Adapter, REG_ACKTO, 0x40);
 781 }
 782
 783 /*-----------------------------------------------------------------------------
 784  * Function:    usb_AggSettingTxUpdate()
 785  *
 786  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 787  *                      dynamic TX/RX aggreagtion parameters update.
 788  *
 789  * Input:                       PADAPTER
 790  *
 791  * Output/Return:       NONE
 792  *
 793  * Revised History:
 794  *      When            Who             Remark
 795  *      12/10/2010      MHC             Seperate to smaller function.
 796  *
 797  *---------------------------------------------------------------------------*/
 798 static VOID
 799 usb_AggSettingTxUpdate(
 800         IN      PADAPTER                        Adapter
 801         )
 802 {
 803 #ifdef CONFIG_USB_TX_AGGREGATION
 804         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 805         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 806         u32                     value32;
 807
 808         if(Adapter->registrypriv.wifi_spec)
 809                 pHalData->UsbTxAggMode = _FALSE;
 810
 811         if(pHalData->UsbTxAggMode){
 812                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 813                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 814                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 815
 816                 rtw_write32(Adapter, REG_TDECTRL, value32);
 817         }
 818
 819 #endif
 820 }       // usb_AggSettingTxUpdate
 821
 822
 823 /*-----------------------------------------------------------------------------
 824  * Function:    usb_AggSettingRxUpdate()
 825  *
 826  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 827  *                      dynamic TX/RX aggreagtion parameters update.
 828  *
 829  * Input:                       PADAPTER
 830  *
 831  * Output/Return:       NONE
 832  *
 833  * Revised History:
 834  *      When            Who             Remark
 835  *      12/10/2010      MHC             Seperate to smaller function.
 836  *
 837  *---------------------------------------------------------------------------*/
 838 static VOID
 839 usb_AggSettingRxUpdate(
 840         IN      PADAPTER                        Adapter
 841         )
 842 {
 843 #ifdef CONFIG_USB_RX_AGGREGATION
 844         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 845         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 846         u8                      valueDMA;
 847         u8                      valueUSB;
 848
 849         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 850         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 851
 852         switch(pHalData->UsbRxAggMode)
 853         {
 854                 case USB_RX_AGG_DMA:
 855                         valueDMA |= RXDMA_AGG_EN;
 856                         valueUSB &= ~USB_AGG_EN;
 857                         break;
 858                 case USB_RX_AGG_USB:
 859                         valueDMA &= ~RXDMA_AGG_EN;
 860                         valueUSB |= USB_AGG_EN;
 861                         break;
 862                 case USB_RX_AGG_MIX:
 863                         valueDMA |= RXDMA_AGG_EN;
 864                         valueUSB |= USB_AGG_EN;
 865                         break;
 866                 case USB_RX_AGG_DISABLE:
 867                 default:
 868                         valueDMA &= ~RXDMA_AGG_EN;
 869                         valueUSB &= ~USB_AGG_EN;
 870                         break;
 871         }
 872
 873         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 874         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 875
 876         switch(pHalData->UsbRxAggMode)
 877         {
 878                 case USB_RX_AGG_DMA:
 879                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 880                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 881                         break;
 882                 case USB_RX_AGG_USB:
 883                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 884                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 885                         break;
 886                 case USB_RX_AGG_MIX:
 887                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 888                         rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout);
 889                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 890                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 891                         break;
 892                 case USB_RX_AGG_DISABLE:
 893                 default:
 894                         // TODO:
 895                         break;
 896         }
 897
 898         switch(PBP_128)
 899         {
 900                 case PBP_128:
 901                         pHalData->HwRxPageSize = 128;
 902                         break;
 903                 case PBP_64:
 904                         pHalData->HwRxPageSize = 64;
 905                         break;
 906                 case PBP_256:
 907                         pHalData->HwRxPageSize = 256;
 908                         break;
 909                 case PBP_512:
 910                         pHalData->HwRxPageSize = 512;
 911                         break;
 912                 case PBP_1024:
 913                         pHalData->HwRxPageSize = 1024;
 914                         break;
 915                 default:
 916                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 917                         break;
 918         }
 919 #endif
 920 }       // usb_AggSettingRxUpdate
 921
 922 static VOID
 923 InitUsbAggregationSetting(
 924         IN  PADAPTER Adapter
 925         )
 926 {
 927         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 928
 929         // Tx aggregation setting
 930         usb_AggSettingTxUpdate(Adapter);
 931
 932         // Rx aggregation setting
 933         usb_AggSettingRxUpdate(Adapter);
 934
 935         // 201/12/10 MH Add for USB agg mode dynamic switch.
 936         pHalData->UsbRxHighSpeedMode = _FALSE;
 937 }
 938
 939 /*-----------------------------------------------------------------------------
 940  * Function:    USB_AggModeSwitch()
 941  *
 942  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
 943  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
 944  *                      need to monitor the influence of FTP/network share.
 945  *                      For TX mode, we are still ubder investigation.
 946  *
 947  * Input:               PADAPTER
 948  *
 949  * Output:              NONE
 950  *
 951  * Return:              NONE
 952  *
 953  * Revised History:
 954  *      When            Who             Remark
 955  *      12/10/2010      MHC             Create Version 0.
 956  *
 957  *---------------------------------------------------------------------------*/
 958 VOID
 959 USB_AggModeSwitch(
 960         IN      PADAPTER                        Adapter
 961         )
 962 {
 963 #if 0
 964         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 965         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
 966
 967         //pHalData->UsbRxHighSpeedMode = FALSE;
 968         // How to measure the RX speed? We assume that when traffic is more than
 969         if (pMgntInfo->bRegAggDMEnable == _FALSE)
 970         {
 971                 return; // Inf not support.
 972         }
 973
 974
 975         if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _TRUE &&
 976                 pHalData->UsbRxHighSpeedMode == _FALSE)
 977         {
 978                 pHalData->UsbRxHighSpeedMode = _TRUE;
 979                 DBG_8723A("UsbAggModeSwitchCheck to HIGH\n");
 980         }
 981         else if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _FALSE &&
 982                 pHalData->UsbRxHighSpeedMode == _TRUE)
 983         {
 984                 pHalData->UsbRxHighSpeedMode = _FALSE;
 985                 DBG_8723A("UsbAggModeSwitchCheck to LOW\n");
 986         }
 987         else
 988         {
 989                 return;
 990         }
 991
 992         // 2010/12/10 MH Add for USB Aggregation judgement we need to
 993         //if( pMgntInfo->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
 994                 //                      pMgntInfo->LinkDetectInfo.NumTxOkInPeriod > 4000 )
 995
 996 #ifdef CONFIG_USB_TX_AGGREGATION
 997         //usb_AggSettingTxUpdate(Adapter);
 998 #endif
 999
1000 #ifdef CONFIG_USB_RX_AGGREGATION
1001         if (pHalData->UsbRxHighSpeedMode == _TRUE)
1002         {
1003                 // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
1004                 // USB mode
1005                 pHalData->UsbRxAggBlockCount            = 40;
1006                 pHalData->UsbRxAggBlockTimeout  = 5;
1007                 // Mix mode
1008                 pHalData->UsbRxAggPageCount             = 72;
1009                 pHalData->UsbRxAggPageTimeout   = 6;
1010         }
1011         else
1012         {
1013                 // USB mode
1014                 pHalData->UsbRxAggBlockCount            = pMgntInfo->RegUsbRxAggBlockCount;
1015                 pHalData->UsbRxAggBlockTimeout  = pMgntInfo->RegUsbRxAggBlockTimeout;
1016                 // Mix mode
1017                 pHalData->UsbRxAggPageCount             = pMgntInfo->RegUsbRxAggPageCount;
1018                 pHalData->UsbRxAggPageTimeout   = pMgntInfo->RegUsbRxAggPageTimeout;
1019         }
1020 #endif
1021 #endif
1022 }       // USB_AggModeSwitch
1023
1024 static VOID
1025 _InitOperationMode(
1026         IN      PADAPTER                        Adapter
1027         )
1028 {
1029 #if 0//gtest
1030         PHAL_DATA_8192CUSB      pHalData = GetHalData8192CUsb(Adapter);
1031         u1Byte                          regBwOpMode = 0;
1032         u4Byte                          regRATR = 0, regRRSR = 0;
1033
1034
1035         //1 This part need to modified according to the rate set we filtered!!
1036         //
1037         // Set RRSR, RATR, and REG_BWOPMODE registers
1038         //
1039         switch(Adapter->RegWirelessMode)
1040         {
1041                 case WIRELESS_MODE_B:
1042                         regBwOpMode = BW_OPMODE_20MHZ;
1043                         regRATR = RATE_ALL_CCK;
1044                         regRRSR = RATE_ALL_CCK;
1045                         break;
1046                 case WIRELESS_MODE_A:
1047                         ASSERT(FALSE);
1048 #if 0
1049                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1050                         regRATR = RATE_ALL_OFDM_AG;
1051                         regRRSR = RATE_ALL_OFDM_AG;
1052 #endif
1053                         break;
1054                 case WIRELESS_MODE_G:
1055                         regBwOpMode = BW_OPMODE_20MHZ;
1056                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1057                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1058                         break;
1059                 case WIRELESS_MODE_AUTO:
1060                         if (Adapter->bInHctTest)
1061                         {
1062                             regBwOpMode = BW_OPMODE_20MHZ;
1063                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1064                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1065                         }
1066                         else
1067                         {
1068                             regBwOpMode = BW_OPMODE_20MHZ;
1069                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1070                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1071                         }
1072                         break;
1073                 case WIRELESS_MODE_N_24G:
1074                         // It support CCK rate by default.
1075                         // CCK rate will be filtered out only when associated AP does not support it.
1076                         regBwOpMode = BW_OPMODE_20MHZ;
1077                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1078                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1079                         break;
1080                 case WIRELESS_MODE_N_5G:
1081                         ASSERT(FALSE);
1082 #if 0
1083                         regBwOpMode = BW_OPMODE_5G;
1084                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1085                         regRRSR = RATE_ALL_OFDM_AG;
1086 #endif
1087                         break;
1088         }
1089
1090         // Ziv ????????
1091         //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
1092         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
1093
1094         // For Min Spacing configuration.
1095         switch(pHalData->RF_Type)
1096         {
1097                 case RF_1T2R:
1098                 case RF_1T1R:
1099                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter: RF_Type%s\n", (pHalData->RF_Type==RF_1T1R? "(1T1R)":"(1T2R)")));
1100                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
1101                         break;
1102                 case RF_2T2R:
1103                 case RF_2T2R_GREEN:
1104                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter:RF_Type(2T2R)\n"));
1105                         Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
1106                         break;
1107         }
1108
1109         rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, Adapter->MgntInfo.MinSpaceCfg);
1110 #endif
1111 }
1112
1113 static VOID
1114 _InitRFType(
1115         IN      PADAPTER Adapter
1116         )
1117 {
1118         struct registry_priv     *pregpriv = &Adapter->registrypriv;
1119         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1120         bool                    is92CU          = IS_92C_SERIAL(pHalData->VersionID);
1121
1122 #if     DISABLE_BB_RF
1123         pHalData->rf_chip       = RF_PSEUDO_11N;
1124         return;
1125 #endif
1126
1127         pHalData->rf_chip       = RF_6052;
1128
1129         if(_FALSE == is92CU){
1130                 pHalData->rf_type = RF_1T1R;
1131                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
1132                 return;
1133         }
1134
1135         // TODO: Consider that EEPROM set 92CU to 1T1R later.
1136         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
1137         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
1138         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1139
1140 }
1141
1142 static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter)
1143 {
1144 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1145         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1146         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1147         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1148         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1149         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1150 #endif
1151 }
1152
1153 // Set CCK and OFDM Block "ON"
1154 static VOID _BBTurnOnBlock(
1155         IN      PADAPTER                Adapter
1156         )
1157 {
1158 #if (DISABLE_BB_RF)
1159         return;
1160 #endif
1161
1162         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1163         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1164 }
1165
1166 #define MgntActSet_RF_State(...)
1167 static void _RfPowerSave(PADAPTER padapter)
1168 {
1169 #if 0
1170         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1171         struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv;
1172         rt_rf_power_state eRfPowerStateToSet;
1173         u8 u1bTmp;
1174
1175
1176 #if (DISABLE_BB_RF)
1177         return;
1178 #endif
1179         //
1180         // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1181         // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1182         // call init_adapter. May cause some problem??
1183         //
1184         // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1185         // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1186         // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1187         // Added by tynli. 2010.03.30.
1188         ppwrctrl->rf_pwrstate = rf_on;
1189         RT_CLEAR_PS_LEVEL(ppwrctrl, RT_RF_OFF_LEVL_HALT_NIC);
1190         //Added by chiyokolin, 2011.10.12 for Tx
1191         rtw_write8(padapter, REG_TXPAUSE, 0x00);
1192
1193         // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1194         // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1195
1196         eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(padapter);
1197         ppwrctrl->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
1198         ppwrctrl->rfoff_reason |= (ppwrctrl->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
1199
1200         if (ppwrctrl->rfoff_reason & RF_CHANGE_BY_HW)
1201                 ppwrctrl->b_hw_radio_off = _TRUE;
1202
1203         if (ppwrctrl->reg_rfoff == _TRUE)
1204         {
1205                 // User disable RF via registry.
1206                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
1207                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
1208
1209 //              if (padapter->bSlaveOfDMSP)
1210 //                      return;
1211         }
1212         else if (ppwrctrl->rfoff_reason > RF_CHANGE_BY_PS)
1213         {
1214                 // H/W or S/W RF OFF before sleep.
1215                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
1216                 MgntActSet_RF_State(padapter, rf_off, ppwrctrl->rfoff_reason, _TRUE);
1217         }
1218         else
1219         {
1220                 // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
1221 #if 0
1222 //              if (RT_GetInterfaceSelection(padapter)==INTF_SEL2_MINICARD &&
1223                 if ((pHalData->BoardType == BOARD_MINICARD) &&
1224                         (padapter->MgntInfo.PowerSaveControl.bGpioRfSw))
1225                 {
1226                         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet));
1227                         if (eRfPowerStateToSet == rf_off)
1228                         {
1229                                 MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
1230                                 ppwrctrl->b_hw_radio_off = _TRUE;
1231                         }
1232                         else
1233                         {
1234                                 ppwrctrl->rf_pwrstate = rf_off;
1235                                 ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1236                                 ppwrctrl->b_hw_radio_off = _FALSE;
1237                                 MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1238                         }
1239                 }
1240                 else
1241 #endif
1242                 {
1243                         ppwrctrl->rf_pwrstate = rf_off;
1244                         ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT;
1245                         MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE);
1246                 }
1247
1248                 ppwrctrl->rfoff_reason = 0;
1249                 ppwrctrl->b_hw_radio_off = _FALSE;
1250                 ppwrctrl->rf_pwrstate = rf_on;
1251                 if (padapter->ledpriv.LedControlHandler)
1252                         padapter->ledpriv.LedControlHandler(padapter, LED_CTL_POWER_ON);
1253         }
1254
1255         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1256         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1257         if (pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1258         {
1259                 // Enable register area 0x0-0xc.
1260                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
1261
1262                 //
1263                 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1264                 // our HW will be set in power-down mode if PDn source from all  functions are configured.
1265                 // 2010.10.06.
1266                 //
1267                 u1bTmp = rtw_read8(padapter, REG_MULTI_FUNC_CTRL);
1268                 u1bTmp |= WL_HWPDN_EN;
1269                 rtw_write8(padapter, REG_MULTI_FUNC_CTRL, u1bTmp);
1270         }
1271 #endif
1272 }
1273
1274 enum {
1275         Antenna_Lfet = 1,
1276         Antenna_Right = 2,
1277 };
1278
1279 //
1280 // 2010/08/09 MH Add for power down check.
1281 //
1282 static bool
1283 HalDetectPwrDownMode(
1284         IN PADAPTER                             Adapter
1285         )
1286 {
1287         u8      tmpvalue;
1288         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(Adapter);
1289         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1290
1291         EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue);
1292
1293         // 2010/08/25 MH INF priority > PDN Efuse value.
1294         if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
1295         {
1296                 pHalData->pwrdown = _TRUE;
1297         }
1298         else
1299         {
1300                 pHalData->pwrdown = _FALSE;
1301         }
1302
1303         DBG_8723A("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
1304         return pHalData->pwrdown;
1305
1306 }       // HalDetectPwrDownMode
1307
1308
1309 //
1310 // 2010/08/26 MH Add for selective suspend mode check.
1311 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1312 // slim card.
1313 //
1314 static VOID
1315 HalDetectSelectiveSuspendMode(
1316         IN PADAPTER                             Adapter
1317         )
1318 {
1319         u8      tmpvalue;
1320         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1321         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1322
1323         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1324         // can not use FW to notify host the power state switch.
1325
1326         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1327
1328         DBG_8723A("HalDetectSelectiveSuspendMode(): SS ");
1329         if(tmpvalue & BIT1)
1330         {
1331                 DBG_8723A("Enable\n");
1332         }
1333         else
1334         {
1335                 DBG_8723A("Disable\n");
1336                 pdvobjpriv->RegUsbSS = _FALSE;
1337         }
1338
1339         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1340         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1341         {
1342                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1343
1344                 //if (!pMgntInfo->bRegDongleSS)
1345                 //{
1346                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1347                         pdvobjpriv->RegUsbSS = _FALSE;
1348                 //}
1349         }
1350 }       // HalDetectSelectiveSuspendMode
1351 /*-----------------------------------------------------------------------------
1352  * Function:    HwSuspendModeEnable92Cu()
1353  *
1354  * Overview:    HW suspend mode switch.
1355  *
1356  * Input:               NONE
1357  *
1358  * Output:      NONE
1359  *
1360  * Return:      NONE
1361  *
1362  * Revised History:
1363  *      When            Who             Remark
1364  *      08/23/2010      MHC             HW suspend mode switch test..
1365  *---------------------------------------------------------------------------*/
1366 static VOID
1367 HwSuspendModeEnable92Cu(
1368         IN      PADAPTER        pAdapter,
1369         IN      u8                      Type
1370         )
1371 {
1372 }       // HwSuspendModeEnable92Cu
1373
1374 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter )
1375 {
1376         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(pAdapter);
1377         u8      val8;
1378         rt_rf_power_state rfpowerstate = rf_off;
1379
1380         if(pAdapter->pwrctrlpriv.bHWPowerdown)
1381         {
1382                 val8 = rtw_read8(pAdapter, REG_HSISR);
1383                 DBG_8723A("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1384                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1385         }
1386         else // rf on/off
1387         {
1388                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1389                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1390                 DBG_8723A("GPIO_IN=%02x\n", val8);
1391                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1392         }
1393         return rfpowerstate;
1394 }       // HalDetectPwrDownMode
1395
1396 void _ps_open_RF(_adapter *padapter);
1397
1398 u32 rtl8723au_hal_init(PADAPTER Adapter)
1399 {
1400         u8      val8 = 0;
1401         u32     boundary, status = _SUCCESS;
1402         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1403         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
1404         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1405         u8      is92C = IS_92C_SERIAL(pHalData->VersionID);
1406         rt_rf_power_state               eRfPowerStateToSet;
1407         u32 NavUpper = WiFiNavUpperUs;
1408
1409         u32 init_start_time = rtw_get_current_time();
1410
1411
1412 #ifdef DBG_HAL_INIT_PROFILING
1413
1414         enum HAL_INIT_STAGES {
1415                 HAL_INIT_STAGES_BEGIN = 0,
1416                 HAL_INIT_STAGES_INIT_PW_ON,
1417                 HAL_INIT_STAGES_INIT_LLTT,
1418                 HAL_INIT_STAGES_MISC01,
1419                 HAL_INIT_STAGES_DOWNLOAD_FW,
1420                 HAL_INIT_STAGES_MAC,
1421                 HAL_INIT_STAGES_BB,
1422                 HAL_INIT_STAGES_RF,
1423                 HAL_INIT_STAGES_MISC02,
1424                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1425                 HAL_INIT_STAGES_INIT_SECURITY,
1426                 HAL_INIT_STAGES_MISC11,
1427                 //HAL_INIT_STAGES_RF_PS,
1428                 HAL_INIT_STAGES_IQK,
1429                 HAL_INIT_STAGES_PW_TRACK,
1430                 HAL_INIT_STAGES_LCK,
1431                 HAL_INIT_STAGES_MISC21,
1432                 //HAL_INIT_STAGES_INIT_PABIAS,
1433                 #ifdef CONFIG_BT_COEXIST
1434                 HAL_INIT_STAGES_BT_COEXIST,
1435                 #endif
1436                 //HAL_INIT_STAGES_ANTENNA_SEL,
1437                 HAL_INIT_STAGES_INIT_HAL_DM,
1438                 HAL_INIT_STAGES_MISC31,
1439                 HAL_INIT_STAGES_END,
1440                 HAL_INIT_STAGES_NUM
1441         };
1442
1443         char * hal_init_stages_str[] = {
1444                 "HAL_INIT_STAGES_BEGIN",
1445                 "HAL_INIT_STAGES_INIT_PW_ON",
1446                 "HAL_INIT_STAGES_INIT_LLTT",
1447                 "HAL_INIT_STAGES_MISC01",
1448                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1449                 "HAL_INIT_STAGES_MAC",
1450                 "HAL_INIT_STAGES_BB",
1451                 "HAL_INIT_STAGES_RF",
1452                 "HAL_INIT_STAGES_MISC02",
1453                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1454                 "HAL_INIT_STAGES_INIT_SECURITY",
1455                 "HAL_INIT_STAGES_MISC11",
1456                 //"HAL_INIT_STAGES_RF_PS",
1457                 "HAL_INIT_STAGES_IQK",
1458                 "HAL_INIT_STAGES_PW_TRACK",
1459                 "HAL_INIT_STAGES_LCK",
1460                 "HAL_INIT_STAGES_MISC21",
1461                 //"HAL_INIT_STAGES_INIT_PABIAS",
1462                 #ifdef CONFIG_BT_COEXIST
1463                 "HAL_INIT_STAGES_BT_COEXIST",
1464                 #endif
1465                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1466                 "HAL_INIT_STAGES_INIT_HAL_DM",
1467                 "HAL_INIT_STAGES_MISC31",
1468                 "HAL_INIT_STAGES_END",
1469         };
1470
1471         int hal_init_profiling_i;
1472         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1473
1474         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1475                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1476
1477         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1478 #else
1479         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1480 #endif //DBG_HAL_INIT_PROFILING
1481
1482
1483
1484 _func_enter_;
1485
1486 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1487         if(Adapter->pwrctrlpriv.bkeepfwalive)
1488         {
1489                 _ps_open_RF(Adapter);
1490
1491                 if(pHalData->bIQKInitialized ){
1492                         rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1493                 }
1494                 else{
1495                         rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1496                         pHalData->bIQKInitialized = _TRUE;
1497                 }
1498                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
1499                 rtl8192c_PHY_LCCalibrate(Adapter);
1500
1501                 goto exit;
1502         }
1503
1504 //      pHalData->bMACFuncEnable = _FALSE;
1505         // Check if MAC has already power on. by tynli. 2011.05.27.
1506         val8 = rtw_read8(Adapter, REG_CR);
1507         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1508                          ("%s: REG_CR 0x100=0x%02x\n", __FUNCTION__, val8));
1509         //Fix 92DU-VC S3 hang with the reason is that secondary mac is not initialized.
1510         //0x100 value of first mac is 0xEA while 0x100 value of secondary is 0x00
1511         //by sherry 20111102
1512         if (val8 == 0xEA) {
1513                 pHalData->bMACFuncEnable = _FALSE;
1514         } else {
1515                 pHalData->bMACFuncEnable = _TRUE;
1516                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1517                                  ("%s: MAC has already power on\n", __FUNCTION__));
1518         }
1519
1520 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1521         status = _InitPowerOn(Adapter);
1522         if(status == _FAIL){
1523                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1524                 goto exit;
1525         }
1526
1527 #ifdef CONFIG_BT_COEXIST
1528         //
1529         // 2010/09/23 MH Accordgin to Alfred's siggestion. we need to enable SIC to prevent HW
1530         // to enter suspend mode automatically. If host does not send SOF every 3ms. Or under DTM
1531         // test with rtl8188cu selective suspend enabler filter driver, WIN host will trigger the device to
1532         // enter suspend mode after some test (unknow reason now). We need to prevent the case otherwise
1533         // the register will be 0xea and all TX/RX path stop accidently.
1534         //
1535         //
1536         // 2010/10/01 MH If the OS is XP, host will trigger USB device to enter D3 mode. In CU HW design
1537         // it will enter suspend mode automatically. In slim combo card, the BT clock will be cut off if HW
1538         // enter suspend mode. We need to seperate differet case.
1539         //
1540         if (BT_IsBtExist(Adapter))
1541         {
1542 #if 0
1543 #if OS_WIN_FROM_VISTA(OS_VERSION)
1544                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo win7/vista need not enable SIC\n"));
1545 #else
1546                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Slim_combo XP enable SIC\n"));
1547                 // 2010/10/15 MH According to Alfre's description, e need to enable bit14 at first an then enable bit12.
1548                 // Otherwise, HW will enter debug mode and 8051 can not work. We need to stay at test mode to enable SIC.
1549                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT14);
1550                 rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT12);
1551 #endif
1552 #endif
1553         }
1554 #endif // CONFIG_BT_COEXIST
1555
1556 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1557         if (!pregistrypriv->wifi_spec) {
1558                 boundary = TX_PAGE_BOUNDARY;
1559         } else {
1560                 // for WMM
1561                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
1562         }
1563
1564         if (!pHalData->bMACFuncEnable)
1565         {
1566                 status =  InitLLTTable(Adapter, boundary);
1567                 if(status == _FAIL){
1568                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1569                         goto exit;
1570                 }
1571         }
1572
1573
1574 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1575         if(pHalData->bRDGEnable){
1576                 _InitRDGSetting(Adapter);
1577         }
1578
1579
1580 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1581 {
1582         status = rtl8723a_FirmwareDownload(Adapter);
1583         if(status != _SUCCESS)
1584         {
1585                 Adapter->bFWReady = _FALSE;
1586                 pHalData->fw_ractrl = _FALSE;
1587                 DBG_8723A("fw download fail!\n");
1588                 goto exit;
1589         }
1590         else
1591         {
1592                 Adapter->bFWReady = _TRUE;
1593                 pHalData->fw_ractrl = _TRUE;
1594                 DBG_8723A("fw download ok!\n");
1595         }
1596 }
1597
1598         rtl8723a_InitializeFirmwareVars(Adapter);
1599
1600         if(pwrctrlpriv->reg_rfoff == _TRUE){
1601                 pwrctrlpriv->rf_pwrstate = rf_off;
1602         }
1603
1604         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1605         // HW GPIO pin. Before PHY_RFConfig8192C.
1606         //HalDetectPwrDownMode(Adapter);
1607         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1608         //HalDetectSelectiveSuspendMode(Adapter);
1609
1610         // Set RF type for BB/RF configuration
1611         _InitRFType(Adapter);//->_ReadRFType()
1612
1613         // Save target channel
1614         // <Roger_Notes> Current Channel will be updated again later.
1615         pHalData->CurrentChannel = 6;//default set to 6
1616
1617
1618 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1619 #if (HAL_MAC_ENABLE == 1)
1620         status = PHY_MACConfig8723A(Adapter);
1621         if(status == _FAIL)
1622         {
1623                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
1624                 goto exit;
1625         }
1626 #endif
1627
1628
1629 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1630         //
1631         //d. Initialize BB related configurations.
1632         //
1633 #if (HAL_BB_ENABLE == 1)
1634         status = PHY_BBConfig8723A(Adapter);
1635         if(status == _FAIL)
1636         {
1637                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
1638                 goto exit;
1639         }
1640 #endif
1641
1642         //
1643         // 2011/11/15 MH Add for tx power by rate fine tune. We need to call the function after BB config.
1644         // Because the tx power by rate table is inited in BB config.
1645         //
1646 //      HAL_AdjustPwrIndexDiffRateOffset(Adapter);
1647 //      HAL_AdjustPwrIndexbyRegistry(Adapter);
1648
1649 #if 0
1650         // The FW command register update must after MAC and FW init ready.
1651         if (Adapter->bFWReady == TRUE)
1652         {
1653                 if(pDevice->RegUsbSS)
1654                 {
1655                         u1Byte          u1H2CSSRf[3]={0};
1656
1657                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_ON(u1H2CSSRf,  1);
1658                         SET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf, 500);
1659
1660                         FillH2CCmd92C(Adapter, H2C_SELECTIVE_SUSPEND_ROF_CMD, 3, u1H2CSSRf);
1661                         RT_TRACE(COMP_INIT, DBG_LOUD,
1662                         ("SS Set H2C_CMD for FW detect GPIO time=%d\n", GET_H2CCMD_SELECTIVE_SUSPEND_ROF_CMD_GPIO_PERIOD(u1H2CSSRf)));
1663                 }
1664                 else
1665                         RT_TRACE(COMP_INIT, DBG_LOUD, ("Non-SS Driver detect GPIO by itself\n"));
1666         }
1667         else
1668         {
1669                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Adapter->bFWReady == FALSE\n"));
1670                 // 2011/02/11 MH If FW is not ready, we can not enter seecitve suspend mode, otherwise,
1671                 // We can not support GPIO/PBC detection by FW with selectiev suspend support.
1672                 pDevice->RegUsbSS = FALSE;
1673         }
1674 #endif
1675
1676
1677 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1678 #if (HAL_RF_ENABLE == 1)
1679         status = PHY_RFConfig8723A(Adapter);
1680         if(status == _FAIL)
1681         {
1682                 DBG_8723A("PHY_RFConfig8723A fault !!\n");
1683                 goto exit;
1684         }
1685
1686         //reducing 80M spur
1687         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
1688         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1689         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
1690         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
1691
1692         //RFSW Control
1693         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   //0x804[14]=0
1694         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        //0x870[6:5]=b'11
1695         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); //0x860[6:5]=b'00
1696
1697         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __FUNCTION__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
1698
1699 #endif
1700
1701         //
1702         // Joseph Note: Keep RfRegChnlVal for later use.
1703         //
1704         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
1705         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
1706
1707
1708 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1709         if (!pHalData->bMACFuncEnable) {
1710                 _InitQueueReservedPage(Adapter);
1711                 _InitTxBufferBoundary(Adapter);
1712         }
1713         _InitQueuePriority(Adapter);
1714         _InitPageBoundary(Adapter);
1715         _InitTransferPageSize(Adapter);
1716
1717         // Get Rx PHY status in order to report RSSI and others.
1718         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1719
1720         _InitInterrupt(Adapter);
1721         hal_init_macaddr(Adapter);//set mac_address
1722         _InitNetworkType(Adapter);//set msr
1723         _InitWMACSetting(Adapter);
1724         _InitAdaptiveCtrl(Adapter);
1725         _InitEDCA(Adapter);
1726         _InitRateFallback(Adapter);
1727         _InitRetryFunction(Adapter);
1728         InitUsbAggregationSetting(Adapter);
1729         _InitOperationMode(Adapter);//todo
1730         rtl8723a_InitBeaconParameters(Adapter);
1731         rtl8723a_InitBeaconMaxError(Adapter, _TRUE);
1732
1733 #ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
1734         _InitAdhocWorkaroundParams(Adapter);
1735 #endif
1736
1737 #if ENABLE_USB_DROP_INCORRECT_OUT
1738         _InitHardwareDropIncorrectBulkOut(Adapter);
1739 #endif
1740
1741 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1742         // Enable lifetime check for the four ACs
1743         rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
1744 #ifdef CONFIG_TX_MCAST2UNI
1745         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1746         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1747 #else   // CONFIG_TX_MCAST2UNI
1748         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1749         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1750 #endif  // CONFIG_TX_MCAST2UNI
1751 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1752
1753
1754 #ifdef CONFIG_LED
1755         _InitHWLed(Adapter);
1756 #endif //CONFIG_LED
1757
1758 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1759         _BBTurnOnBlock(Adapter);
1760         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1761
1762 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1763         invalidate_cam_all(Adapter);
1764
1765 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1766         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1767         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
1768
1769         rtl8723a_InitAntenna_Selection(Adapter);
1770
1771         // HW SEQ CTRL
1772         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1773         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1774
1775         //
1776         // Disable BAR, suggested by Scott
1777         // 2010.04.09 add by hpfan
1778         //
1779         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1780
1781         if(pregistrypriv->wifi_spec)
1782                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1783
1784         // Move by Neo for USB SS from above setp
1785         _RfPowerSave(Adapter);
1786
1787         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
1788                 // 2010/08/26 MH Merge from 8192CE.
1789                 //sherry masked that it has been done in _RfPowerSave
1790                 //20110927
1791                 //recovery for 8192cu and 9723Au 20111017
1792                 if(pwrctrlpriv->rf_pwrstate == rf_on)
1793                 {
1794                         if(pHalData->bIQKInitialized ){
1795                                 rtl8192c_PHY_IQCalibrate(Adapter,_TRUE);
1796                         } else {
1797                                 rtl8192c_PHY_IQCalibrate(Adapter,_FALSE);
1798                                 pHalData->bIQKInitialized = _TRUE;
1799                         }
1800
1801         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
1802                         rtl8192c_odm_CheckTXPowerTracking(Adapter);
1803
1804         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
1805                         rtl8192c_PHY_LCCalibrate(Adapter);
1806
1807 #ifdef CONFIG_BT_COEXIST
1808                         rtl8723a_SingleDualAntennaDetection(Adapter);
1809 #endif
1810                 }
1811
1812
1813 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1814 #ifdef USB_INTERFERENCE_ISSUE
1815  //fixed USB interface interference issue
1816         rtw_write8(Adapter, 0xfe40, 0xe0);
1817         rtw_write8(Adapter, 0xfe41, 0x8d);
1818         rtw_write8(Adapter, 0xfe42, 0x80);
1819         rtw_write32(Adapter,0x20c,0xfd0320);
1820 #if 1
1821         //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus
1822         if(!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188
1823         {
1824                 // 0xE6=0x94
1825                 rtw_write8(Adapter, 0xFE40, 0xE6);
1826                 rtw_write8(Adapter, 0xFE41, 0x94);
1827                 rtw_write8(Adapter, 0xFE42, 0x80);
1828
1829                 // 0xE0=0x19
1830                 rtw_write8(Adapter, 0xFE40, 0xE0);
1831                 rtw_write8(Adapter, 0xFE41, 0x19);
1832                 rtw_write8(Adapter, 0xFE42, 0x80);
1833
1834                 // 0xE5=0x91
1835                 rtw_write8(Adapter, 0xFE40, 0xE5);
1836                 rtw_write8(Adapter, 0xFE41, 0x91);
1837                 rtw_write8(Adapter, 0xFE42, 0x80);
1838
1839                 // 0xE2=0x81
1840                 rtw_write8(Adapter, 0xFE40, 0xE2);
1841                 rtw_write8(Adapter, 0xFE41, 0x81);
1842                 rtw_write8(Adapter, 0xFE42, 0x80);
1843
1844         }
1845
1846 #endif
1847 #endif //USB_INTERFERENCE_ISSUE
1848
1849 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1850 //      _InitPABias(Adapter);
1851
1852 #ifdef CONFIG_BT_COEXIST
1853 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1854         // Init BT hw config.
1855         BT_InitHwConfig(Adapter);
1856 #endif
1857
1858 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1859         rtl8723a_InitHalDm(Adapter);
1860
1861 #if 0
1862         // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1863         // 2010/05/18 MH For SE series only now. Init GPIO detect time
1864         if(pDevice->RegUsbSS)
1865         {
1866                 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n"));
1867                 GpioDetectTimerStart8192CU(Adapter);    // Disable temporarily
1868         }
1869
1870         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1871         // suspend mode automatically.
1872         HwSuspendModeEnable92Cu(Adapter, _FALSE);
1873 #endif
1874
1875 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1876         rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1877
1878         // 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause.
1879         if (((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000)) {
1880                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
1881                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __FUNCTION__));
1882         }
1883
1884 #ifdef CONFIG_XMIT_ACK
1885         //ack for xmit mgmt frames.
1886         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1887 #endif //CONFIG_XMIT_ACK
1888
1889         //_dbg_dump_macreg(padapter);
1890
1891 exit:
1892 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1893
1894         DBG_8723A("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1895
1896         #ifdef DBG_HAL_INIT_PROFILING
1897         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1898
1899         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1900                 DBG_8723A("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1901                         , hal_init_stages_str[hal_init_profiling_i]
1902                         , hal_init_stages_timestamp[hal_init_profiling_i]
1903                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1904                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1905                 );
1906         }
1907         #endif
1908
1909 _func_exit_;
1910
1911         return status;
1912 }
1913
1914
1915 #define SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1916 #ifdef SYNC_SD7_20110802_phy_SsPwrSwitch92CU
1917 VOID
1918 phy_SsPwrSwitch92CU(
1919         IN      PADAPTER                        Adapter,
1920         IN      rt_rf_power_state       eRFPowerState,
1921         IN      int bRegSSPwrLvl
1922         )
1923 {
1924         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1925         u8                              value8;
1926
1927         switch( eRFPowerState )
1928         {
1929                 case rf_on:
1930                         if (bRegSSPwrLvl == 1)
1931                         {
1932                                 // 1. Enable MAC Clock. Can not be enabled now.
1933                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1934
1935                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1936                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1937                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1938
1939                                 // 3. restore BB, AFE control register.
1940                                 //RF
1941                                 if (pHalData->rf_type ==  RF_2T2R)
1942                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1943                                 else
1944                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1945                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1946                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1947
1948                                 //AFE
1949                                 //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]);
1950                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] );
1951                                 //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 );
1952                                 if (pHalData->rf_type ==  RF_2T2R)
1953                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1954                                 else if (pHalData->rf_type ==  RF_1T1R)
1955                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1956
1957                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1958                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1959                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
1960                                 if (pHalData->rf_type ==  RF_2T2R)
1961                                 {
1962                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
1963                                 }
1964                         }
1965                         else            // Level 2 or others.
1966                         {
1967                                 //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
1968                                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
1969
1970                                 // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
1971                                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
1972                                 rtw_mdelay_os(1);
1973
1974                                 // 1. Enable MAC Clock. Can not be enabled now.
1975                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3));
1976
1977                                 // 2. Force PWM, Enable SPS18_LDO_Marco_Block
1978                                 rtw_write8(Adapter, REG_SPS0_CTRL,
1979                                 rtw_read8(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3));
1980
1981                                 // 3. restore BB, AFE control register.
1982                                 //RF
1983                                 if (pHalData->rf_type ==  RF_2T2R)
1984                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1);
1985                                 else
1986                                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1);
1987                                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
1988                                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
1989
1990                                 //AFE
1991                                 if (pHalData->rf_type ==  RF_2T2R)
1992                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 );
1993                                 else if (pHalData->rf_type ==  RF_1T1R)
1994                                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 );
1995
1996                                 // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode.
1997                                 // We can only prvide a usual value instead and then HW will modify the value by itself.
1998                                 PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0x32D95);
1999                                 if (pHalData->rf_type ==  RF_2T2R)
2000                                 {
2001                                         PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0x32D95);
2002                                 }
2003
2004                                 // 5. gated MAC Clock
2005                                 //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2006                                 //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)|(BIT3));
2007
2008                                 {
2009                                         //u8                    eRFPath = RF_PATH_A,value8 = 0, retry = 0;
2010                                         u8              bytetmp;
2011                                         //PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2012                                         // 2010/08/12 MH Add for B path under SS test.
2013                                         //if (pHalData->RF_Type ==  RF_2T2R)
2014                                                 //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2015
2016                                         bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
2017                                         rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
2018
2019                                         rtw_mdelay_os(10);
2020
2021                                         // Set BB reset at first
2022                                         rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16
2023
2024                                         // Enable TX
2025                                         rtw_write8(Adapter, REG_TXPAUSE, 0x0);
2026                                 }
2027                                 //CardSelectiveSuspendLeave(Adapter);
2028                         }
2029
2030                         break;
2031
2032                 case rf_sleep:
2033                 case rf_off:
2034                                 value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
2035                                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2036                                         value8 &= ~(BIT0);
2037                                 else
2038                                         value8 &= ~(BIT0|BIT3);
2039                                 if (bRegSSPwrLvl == 1)
2040                                 {
2041                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
2042                                         // Disable RF and BB only for SelectSuspend.
2043
2044                                         // 1. Set BB/RF to shutdown.
2045                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2046                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2047                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2048                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2049                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2050                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2051                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2052                                         if (pHalData->rf_type ==  RF_2T2R)
2053                                         {
2054                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2055                                         }
2056                                         else if (pHalData->rf_type ==  RF_1T1R)
2057                                         {
2058                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2059                                         }
2060                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2061                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2062
2063                                         // 2 .AFE control register to power down. bit[30:22]
2064                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2065                                         if (pHalData->rf_type ==  RF_2T2R)
2066                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2067                                         else if (pHalData->rf_type ==  RF_1T1R)
2068                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2069
2070                                         // 3. issue 3-wire command that RF set to power down.
2071                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2072                                         if (pHalData->rf_type ==  RF_2T2R)
2073                                         {
2074                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2075                                         }
2076
2077                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2078                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2079
2080                                         // 5. gated MAC Clock
2081                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2082                                 }
2083                                 else    // Level 2 or others.
2084                                 {
2085                                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
2086                                         {
2087                                                 u8                      eRFPath = RF_PATH_A,value8 = 0;
2088                                                 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2089                                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2090                                                 // 2010/08/12 MH Add for B path under SS test.
2091                                                 //if (pHalData->RF_Type ==  RF_2T2R)
2092                                                         //PHY_SetRFReg(Adapter, RF_PATH_B, 0x0, bMaskByte0, 0x0);
2093
2094                                                 value8 |= APSDOFF;
2095                                                 rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2096
2097                                                 // After switch APSD, we need to delay for stability
2098                                                 rtw_mdelay_os(10);
2099
2100                                                 // Set BB reset at first
2101                                                 value8 = 0 ;
2102                                                 value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2103                                                 rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2104                                         }
2105
2106                                         // Disable RF and BB only for SelectSuspend.
2107
2108                                         // 1. Set BB/RF to shutdown.
2109                                         //      (1) Reg878[5:3]= 0      // RF rx_code for preamble power saving
2110                                         //      (2)Reg878[21:19]= 0     //Turn off RF-B
2111                                         //      (3) RegC04[7:4]= 0      // turn off all paths for packet detection
2112                                         //      (4) Reg800[1] = 1               // enable preamble power saving
2113                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord);
2114                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord);
2115                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
2116                                         if (pHalData->rf_type ==  RF_2T2R)
2117                                         {
2118                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0);
2119                                         }
2120                                         else if (pHalData->rf_type ==  RF_1T1R)
2121                                         {
2122                                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
2123                                         }
2124                                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
2125                                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1);
2126
2127                                         // 2 .AFE control register to power down. bit[30:22]
2128                                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
2129                                         if (pHalData->rf_type ==  RF_2T2R)
2130                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0);
2131                                         else if (pHalData->rf_type ==  RF_1T1R)
2132                                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0);
2133
2134                                         // 3. issue 3-wire command that RF set to power down.
2135                                         PHY_SetRFReg(Adapter,RF_PATH_A, 0, bRFRegOffsetMask,0);
2136                                         if (pHalData->rf_type ==  RF_2T2R)
2137                                         {
2138                                                 PHY_SetRFReg(Adapter,RF_PATH_B, 0, bRFRegOffsetMask,0);
2139                                         }
2140
2141                                         // 4. Force PFM , disable SPS18_LDO_Marco_Block
2142                                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2143
2144                                         // 2010/10/13 MH/Isaachsu exchange sequence.
2145                                         //h.    AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2146                                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2147                                         rtw_mdelay_os(1);
2148
2149                                         // i.   AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2150                                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
2151
2152                                         // 5. gated MAC Clock
2153                                         //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3)));
2154                                         //rtw_write8(Adapter, REG_SYS_CLKR+1, rtw_read8(Adapter, REG_SYS_CLKR+1)& ~(BIT3))
2155
2156                                         //CardSelectiveSuspendEnter(Adapter);
2157                                 }
2158
2159                         break;
2160
2161                 default:
2162                         break;
2163         }
2164
2165 }       // phy_PowerSwitch92CU
2166
2167 void _ps_open_RF(_adapter *padapter) {
2168         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2169         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
2170 }
2171
2172 void _ps_close_RF(_adapter *padapter){
2173         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2174         phy_SsPwrSwitch92CU(padapter, rf_off, 1);
2175 }
2176 #endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU
2177
2178
2179
2180 static VOID
2181 _DisableGPIO(
2182         IN      PADAPTER        Adapter
2183         )
2184 {
2185 /***************************************
2186 j. GPIO_PIN_CTRL 0x44[31:0]=0x000               //
2187 k. Value = GPIO_PIN_CTRL[7:0]
2188 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
2189 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
2190 n. LEDCFG 0x4C[15:0] = 0x8080
2191 ***************************************/
2192         u8      value8;
2193         u16     value16;
2194         u32     value32;
2195
2196         //1. Disable GPIO[7:0]
2197         rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
2198         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
2199         value8 = (u8) (value32&0x000000FF);
2200         value32 |= ((value8<<8) | 0x00FF0000);
2201         rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
2202
2203         //2. Disable GPIO[10:8]
2204         rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
2205             value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
2206         value8 = (u8) (value16&0x000F);
2207         value16 |= ((value8<<4) | 0x0780);
2208         rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
2209
2210         //3. Disable LED0 & 1
2211         rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
2212
2213         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
2214
2215 } //end of _DisableGPIO()
2216
2217 static VOID
2218 _ResetFWDownloadRegister(
2219         IN PADAPTER                     Adapter
2220         )
2221 {
2222         u32     value32;
2223
2224         value32 = rtw_read32(Adapter, REG_MCUFWDL);
2225         value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
2226         rtw_write32(Adapter, REG_MCUFWDL, value32);
2227         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
2228 }
2229
2230
2231 static int
2232 _DisableRF_AFE(
2233         IN PADAPTER                     Adapter
2234         )
2235 {
2236         int             rtStatus = _SUCCESS;
2237         u32                     pollingCount = 0;
2238         u8                      value8;
2239
2240         //disable RF/ AFE AD/DA
2241         value8 = APSDOFF;
2242         rtw_write8(Adapter, REG_APSD_CTRL, value8);
2243
2244
2245 #if (RTL8192CU_ASIC_VERIFICATION)
2246
2247         do
2248         {
2249                 if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){
2250                         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n"));
2251                         break;
2252                 }
2253
2254                 if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
2255                         //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n"));
2256                         return _FAIL;
2257                 }
2258
2259         }while(_TRUE);
2260
2261 #endif
2262
2263         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n"));
2264         return rtStatus;
2265
2266 }
2267
2268 static VOID
2269 _ResetBB(
2270         IN PADAPTER                     Adapter
2271         )
2272 {
2273         u16     value16;
2274
2275         //reset BB
2276         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2277         value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
2278         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2279         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
2280 }
2281
2282 static VOID
2283 _ResetMCU(
2284         IN PADAPTER                     Adapter
2285         )
2286 {
2287         u16     value16;
2288
2289         // reset MCU
2290         value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2291         value16 &= ~FEN_CPUEN;
2292         rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
2293         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
2294 }
2295
2296 static VOID
2297 _DisableMAC_AFE_PLL(
2298         IN PADAPTER                     Adapter
2299         )
2300 {
2301         u32     value32;
2302
2303         //disable MAC/ AFE PLL
2304         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2305         value32 |= APDM_MAC;
2306         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2307
2308         value32 |= APFM_OFF;
2309         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2310         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
2311 }
2312
2313 static VOID
2314 _AutoPowerDownToHostOff(
2315         IN      PADAPTER                Adapter
2316         )
2317 {
2318         u32                     value32;
2319         rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
2320
2321         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2322
2323         value32 |= APDM_HOST;//card disable
2324         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2325         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
2326
2327         // set USB suspend
2328         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2329         value32 &= ~AFSM_PCIE;
2330         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2331
2332 }
2333
2334 static VOID
2335 _SetUsbSuspend(
2336         IN PADAPTER                     Adapter
2337         )
2338 {
2339         u32                     value32;
2340
2341         value32 = rtw_read32(Adapter, REG_APS_FSMCO);
2342
2343         // set USB suspend
2344         value32 |= AFSM_HSUS;
2345         rtw_write32(Adapter, REG_APS_FSMCO, value32);
2346
2347         //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
2348         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
2349
2350 }
2351
2352 static VOID
2353 _DisableRFAFEAndResetBB(
2354         IN PADAPTER                     Adapter
2355         )
2356 {
2357 /**************************************
2358 a.      TXPAUSE 0x522[7:0] = 0xFF             //Pause MAC TX queue
2359 b.      RF path 0 offset 0x00 = 0x00            // disable RF
2360 c.      APSD_CTRL 0x600[7:0] = 0x40
2361 d.      SYS_FUNC_EN 0x02[7:0] = 0x16            //reset BB state machine
2362 e.      SYS_FUNC_EN 0x02[7:0] = 0x14            //reset BB state machine
2363 ***************************************/
2364         u8 eRFPath = 0,value8 = 0;
2365         rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
2366         PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0);
2367
2368         value8 |= APSDOFF;
2369         rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
2370
2371         value8 = 0 ;
2372         value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
2373         rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
2374
2375         value8 &=( ~FEN_BB_GLB_RSTn );
2376         rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
2377
2378         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
2379 }
2380
2381 static VOID
2382 _ResetDigitalProcedure1(
2383         IN      PADAPTER                        Adapter,
2384         IN      bool                            bWithoutHWSM
2385         )
2386 {
2387
2388         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2389
2390         if(pHalData->FirmwareVersion <=  0x20){
2391                 #if 0
2392                 /*****************************
2393                 f.      SYS_FUNC_EN 0x03[7:0]=0x54              // reset MAC register, DCORE
2394                 g.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2395                 ******************************/
2396                 u4Byte  value32 = 0;
2397                 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
2398                 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
2399                 #else
2400                 /*****************************
2401                 f.      MCUFWDL 0x80[7:0]=0                             // reset MCU ready status
2402                 g.      SYS_FUNC_EN 0x02[10]= 0                 // reset MCU register, (8051 reset)
2403                 h.      SYS_FUNC_EN 0x02[15-12]= 5              // reset MAC register, DCORE
2404                 i.     SYS_FUNC_EN 0x02[10]= 1                  // enable MCU register, (8051 enable)
2405                 ******************************/
2406                         u16 valu16 = 0;
2407                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2408
2409                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2410                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
2411
2412                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
2413                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
2414
2415                         #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2416                         {
2417                                 u8 val;
2418                                 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2419                                         DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2420                         }
2421                         #endif
2422
2423
2424                         valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
2425                         rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
2426
2427
2428                 #endif
2429         }
2430         else{
2431                 u8 retry_cnts = 0;
2432
2433                 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
2434                 { //IF fw in RAM code, do reset
2435
2436                         rtw_write8(Adapter, REG_MCUFWDL, 0);
2437                         if(Adapter->bFWReady){
2438                                 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
2439                                 // HRCV INT to influence 8051 reset.
2440                                 rtw_write8(Adapter, REG_FWIMR, 0x20);
2441
2442                                 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
2443
2444                                 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
2445                                 {
2446                                         rtw_udelay_os(50);//PlatformStallExecution(50);//us
2447                                 }
2448
2449                                 if(retry_cnts >= 100){
2450                                         DBG_8723A("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
2451                                         // if 8051 reset fail we trigger GPIO 0 for LA
2452                                         //PlatformEFIOWrite4Byte(       Adapter,
2453                                         //                                              REG_GPIO_PIN_CTRL,
2454                                         //                                              0x00010100);
2455                                         // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
2456                                         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50);   //Reset MAC and Enable 8051
2457                                         rtw_mdelay_os(10);
2458                                 }
2459                                 else {
2460                                         //DBG_8723A("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
2461                                 }
2462                         }
2463                         else {
2464                                 DBG_8723A("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
2465                         }
2466                 }
2467                 else{
2468                         //DBG_8723A("%s =====> 8051 in ROM.\n", __FUNCTION__);
2469                 }
2470
2471                 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
2472                 {
2473                         u8 val;
2474                         if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
2475                                 DBG_8723A("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
2476                 }
2477                 #endif
2478
2479                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54);   //Reset MAC and Enable 8051
2480         }
2481
2482         // Clear rpwm value for initial toggle bit trigger.
2483         rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
2484
2485         if(bWithoutHWSM){
2486         /*****************************
2487                 Without HW auto state machine
2488         g.      SYS_CLKR 0x08[15:0] = 0x30A3                    //disable MAC clock
2489         h.      AFE_PLL_CTRL 0x28[7:0] = 0x80                   //disable AFE PLL
2490         i.      AFE_XTAL_CTRL 0x24[15:0] = 0x880F               //gated AFE DIG_CLOCK
2491         j.      SYS_ISO_CTRL 0x00[7:0] = 0xF9                   // isolated digital to PON
2492         ******************************/
2493                 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
2494                 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
2495                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
2496                 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
2497                 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
2498         }
2499         else
2500         {
2501                 // Disable all RF/BB power
2502                 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2503         }
2504         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
2505
2506 }
2507
2508 static VOID
2509 _ResetDigitalProcedure2(
2510         IN      PADAPTER                        Adapter
2511 )
2512 {
2513 /*****************************
2514 k.      SYS_FUNC_EN 0x03[7:0] = 0x44                    // disable ELDR runction
2515 l.      SYS_CLKR 0x08[15:0] = 0x3083                    // disable ELDR clock
2516 m.      SYS_ISO_CTRL 0x01[7:0] = 0x83                   // isolated ELDR to PON
2517 ******************************/
2518         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
2519         //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
2520         //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
2521
2522         rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
2523         rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
2524 }
2525
2526 static VOID
2527 _DisableAnalog(
2528         IN PADAPTER                     Adapter,
2529         IN bool                 bWithoutHWSM
2530         )
2531 {
2532         u16 value16 = 0;
2533         u8 value8=0;
2534         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2535
2536         if(bWithoutHWSM){
2537         /*****************************
2538         n.      LDOA15_CTRL 0x20[7:0] = 0x04            // disable A15 power
2539         o.      LDOV12D_CTRL 0x21[7:0] = 0x54           // disable digital core power
2540         r.      When driver call disable, the ASIC will turn off remaining clock automatically
2541         ******************************/
2542
2543                 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
2544                 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
2545
2546                 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
2547                 value8 &= (~LDV12_EN);
2548                 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
2549                 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
2550         }
2551
2552 /*****************************
2553 h.      SPS0_CTRL 0x11[7:0] = 0x23                      //enter PFM mode
2554 i.      APS_FSMCO 0x04[15:0] = 0x4802           // set USB suspend
2555 ******************************/
2556
2557
2558         value8 = 0x23;
2559         if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
2560                 value8 |= BIT3;
2561
2562         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
2563
2564
2565         if(bWithoutHWSM)
2566         {
2567                 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
2568                 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
2569                 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
2570                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2571         }
2572         else
2573         {
2574                 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
2575         }
2576
2577         rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
2578
2579         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2580
2581  #if 0
2582         //tynli_test for suspend mode.
2583         if(!bWithoutHWSM){
2584                 rtw_write8(Adapter, 0xfe10, 0x19);
2585         }
2586 #endif
2587
2588         //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
2589 }
2590
2591 static void rtl8723au_hw_power_down(_adapter *padapter)
2592 {
2593         u8      u1bTmp;
2594
2595         DBG_8723A("PowerDownRTL8723U\n");
2596
2597
2598         // 1. Run Card Disable Flow
2599         // Done before this function call.
2600
2601         // 2. 0x04[16] = 0                      // reset WLON
2602         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
2603         rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
2604
2605         // 3. 0x04[12:11] = 2b'11 // enable suspend
2606         // Done before this function call.
2607
2608         // 4. 0x04[15] = 1                      // enable PDN
2609         u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
2610         rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
2611 }
2612
2613 //
2614 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
2615 // First created by tynli. 2011.01.28.
2616 //
2617 VOID
2618 CardDisableRTL8723U(
2619         PADAPTER                        Adapter
2620 )
2621 {
2622         u8              u1bTmp;
2623 //      PMGNT_INFO      pMgntInfo       = &(Adapter->MgntInfo);
2624
2625         DBG_8723A("CardDisableRTL8723U\n");
2626
2627         // USB-MF Card Disable Flow
2628         // 1. Run LPS WL RFOFF flow
2629         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_enter_lps_flow);
2630
2631         // 2. 0x1F[7:0] = 0             // turn off RF
2632         rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2633
2634         //      ==== Reset digital sequence   ======
2635         if((rtw_read8(Adapter, REG_MCUFWDL)&BIT7) &&
2636                 Adapter->bFWReady) //8051 RAM code
2637         {
2638                 rtl8723a_FirmwareSelfReset(Adapter);
2639         }
2640
2641         // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
2642         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2643         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, (u1bTmp&(~BIT2)));
2644
2645         // g.   MCUFWDL 0x80[1:0]=0                             // reset MCU ready status
2646         rtw_write8(Adapter, REG_MCUFWDL, 0x00);
2647
2648         //      ==== Reset digital sequence end ======
2649 //      if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) )
2650         {
2651                 // Card disable power action flow
2652                 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_disable_flow);
2653         }
2654
2655         // Reset MCU IO Wrapper, added by Roger, 2011.08.30.
2656         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2657         rtw_write8(Adapter, REG_RSV_CTRL+1, (u1bTmp&(~BIT0)));
2658         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL+1);
2659         rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp|BIT0);
2660
2661         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2662         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2663
2664 }
2665
2666
2667 u32 rtl8723au_hal_deinit(PADAPTER padapter)
2668 {
2669         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(padapter);
2670
2671
2672         DBG_8723A("==> %s\n", __FUNCTION__);
2673
2674 #ifdef CONFIG_BT_COEXIST
2675         BT_HaltProcess(padapter);
2676 #endif
2677         // 2011/02/18 To Fix RU LNA  power leakage problem. We need to execute below below in
2678         // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
2679         // IC. Accord to johnny's opinion, only RU need the support.
2680         CardDisableRTL8723U(padapter);
2681
2682         return _SUCCESS;
2683 }
2684
2685
2686 unsigned int rtl8723au_inirp_init(PADAPTER Adapter)
2687 {
2688         u8 i;
2689         struct recv_buf *precvbuf;
2690         uint    status;
2691         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2692         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2693         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2694         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2695 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2696         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2697         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2698 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2699
2700 _func_enter_;
2701
2702         _read_port = pintfhdl->io_ops._read_port;
2703
2704         status = _SUCCESS;
2705
2706         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2707
2708         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2709
2710         //issue Rx irp to receive data
2711         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2712         for(i=0; i<NR_RECVBUFF; i++)
2713         {
2714                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2715                 {
2716                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2717                         status = _FAIL;
2718                         goto exit;
2719                 }
2720
2721                 precvbuf++;
2722                 precvpriv->free_recv_buf_queue_cnt--;
2723         }
2724
2725 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2726         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2727         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2728         {
2729                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2730                 status = _FAIL;
2731         }
2732         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2733         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2734         pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2735         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2736 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2737
2738 exit:
2739
2740         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2741
2742 _func_exit_;
2743
2744         return status;
2745
2746 }
2747
2748 unsigned int rtl8723au_inirp_deinit(PADAPTER Adapter)
2749 {
2750 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2751         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2752         HAL_DATA_TYPE   *pHalData=GET_HAL_DATA(Adapter);
2753 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2754         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2755
2756         rtw_read_port_cancel(Adapter);
2757 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2758         pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2759         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2760         pHalData->IntrMask[0]=0x0;
2761         rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2762         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2763 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2764         return _SUCCESS;
2765 }
2766
2767
2768 static u32
2769 _GetChannelGroup(
2770         IN      u32     channel
2771         )
2772 {
2773         //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2774
2775         if(channel < 3){        // Channel 1~3
2776                 return 0;
2777         }
2778         else if(channel < 9){ // Channel 4~9
2779                 return 1;
2780         }
2781
2782         return 2;                               // Channel 10~14
2783 }
2784
2785
2786 //-------------------------------------------------------------------
2787 //
2788 //      EEPROM/EFUSE Content Parsing
2789 //
2790 //-------------------------------------------------------------------
2791 static void
2792 _ReadIDs(
2793         IN      PADAPTER        Adapter,
2794         IN      u8*             PROMContent,
2795         IN      bool            AutoloadFail
2796         )
2797 {
2798         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2799
2800         if(_FALSE == AutoloadFail){
2801                 // VID, PID
2802                 pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
2803                 pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
2804
2805                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2806                 pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
2807                 pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
2808
2809         }
2810         else{
2811                 pHalData->EEPROMVID      = EEPROM_Default_VID;
2812                 pHalData->EEPROMPID      = EEPROM_Default_PID;
2813
2814                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2815                 pHalData->EEPROMCustomerID      = EEPROM_Default_CustomerID;
2816                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2817
2818         }
2819
2820         // For customized behavior.
2821         if((pHalData->EEPROMVID == 0x103C) || (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2822                 pHalData->CustomerID = RT_CID_819x_HP;
2823
2824         //      Decide CustomerID according to VID/DID or EEPROM
2825         switch(pHalData->EEPROMCustomerID)
2826         {
2827                 case EEPROM_CID_DEFAULT:
2828                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2829                                 pHalData->CustomerID = RT_CID_DLINK;
2830                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2831                                 pHalData->CustomerID = RT_CID_DLINK;
2832                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2833                                 pHalData->CustomerID = RT_CID_DLINK;
2834                         break;
2835                 case EEPROM_CID_WHQL:
2836 /*
2837                         Adapter->bInHctTest = TRUE;
2838
2839                         pMgntInfo->bSupportTurboMode = FALSE;
2840                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2841
2842                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2843                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2844                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2845
2846                         pMgntInfo->keepAliveLevel = 0;
2847
2848                         Adapter->bUnloadDriverwhenS3S4 = FALSE;
2849 */
2850                         break;
2851                 default:
2852                         pHalData->CustomerID = RT_CID_DEFAULT;
2853                         break;
2854
2855         }
2856
2857         MSG_8723A("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
2858         MSG_8723A("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
2859         MSG_8723A("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
2860         MSG_8723A("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
2861
2862         MSG_8723A("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
2863
2864 }
2865
2866
2867 static VOID
2868 _ReadMACAddress(
2869         IN      PADAPTER        Adapter,
2870         IN      u8*             PROMContent,
2871         IN      bool            AutoloadFail
2872         )
2873 {
2874         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2875
2876         if(_FALSE == AutoloadFail){
2877                 //Read Permanent MAC address and set value to hardware
2878                 memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);
2879         }
2880         else{
2881                 //Random assigh MAC address
2882                 u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
2883                 //sMacAddr[5] = (u8)GetRandomNumber(1, 254);
2884                 memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);
2885         }
2886         DBG_8723A("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
2887         //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
2888         //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
2889
2890 }
2891
2892 static VOID
2893 _ReadBoardType(
2894         IN      PADAPTER        Adapter,
2895         IN      u8*             PROMContent,
2896         IN      bool            AutoloadFail
2897         )
2898 {
2899         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2900         u32                     value32;
2901         u8                      boardType = BOARD_USB_DONGLE;
2902
2903         if(AutoloadFail){
2904                 if(IS_8723_SERIES(pHalData->VersionID))
2905                         pHalData->rf_type = RF_1T1R;
2906                 else
2907                         pHalData->rf_type = RF_2T2R;
2908
2909                 pHalData->BoardType = boardType;
2910                 return;
2911         }
2912
2913         boardType = PROMContent[EEPROM_NORMAL_BoardType];
2914         boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5]
2915         boardType >>= 5;
2916
2917         pHalData->BoardType = boardType;
2918         MSG_8723A("_ReadBoardType(%x)\n",pHalData->BoardType);
2919
2920         if (boardType == BOARD_USB_High_PA)
2921                 pHalData->ExternalPA = 1;
2922 }
2923
2924
2925 static VOID
2926 _ReadLEDSetting(
2927         IN      PADAPTER        Adapter,
2928         IN      u8*             PROMContent,
2929         IN      bool            AutoloadFail
2930         )
2931 {
2932         struct led_priv *pledpriv = &(Adapter->ledpriv);
2933         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2934 #ifdef CONFIG_SW_LED
2935         pledpriv->bRegUseLed = _TRUE;
2936
2937         //
2938         // Led mode
2939         //
2940         switch(pHalData->CustomerID)
2941         {
2942                 case RT_CID_DEFAULT:
2943                         pledpriv->LedStrategy = SW_LED_MODE1;
2944                         pledpriv->bRegUseLed = _TRUE;
2945                         break;
2946
2947                 case RT_CID_819x_HP:
2948                         pledpriv->LedStrategy = SW_LED_MODE6;
2949                         break;
2950
2951                 default:
2952                         pledpriv->LedStrategy = SW_LED_MODE1;
2953                         break;
2954         }
2955
2956         if( BOARD_MINICARD == pHalData->BoardType )
2957         {
2958                 pledpriv->LedStrategy = SW_LED_MODE6;
2959         }
2960         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2961 #else // HW LED
2962         pledpriv->LedStrategy = HW_LED;
2963 #endif //CONFIG_SW_LED
2964 }
2965
2966 static VOID
2967 _ReadThermalMeter(
2968         IN      PADAPTER        Adapter,
2969         IN      u8*     PROMContent,
2970         IN      bool            AutoloadFail
2971         )
2972 {
2973         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2974         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2975         u8      tempval;
2976
2977         //
2978         // ThermalMeter from EEPROM
2979         //
2980         if(!AutoloadFail)
2981                 tempval = PROMContent[EEPROM_THERMAL_METER];
2982         else
2983                 tempval = EEPROM_Default_ThermalMeter;
2984
2985         pHalData->EEPROMThermalMeter = (tempval&0x1f);  //[4:0]
2986
2987         if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
2988                 pdmpriv->bAPKThermalMeterIgnore = _TRUE;
2989
2990 #if 0
2991         if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
2992                 pHalData->EEPROMThermalMeter = 0x12;
2993 #endif
2994
2995         pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
2996
2997         //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
2998
2999 }
3000
3001 static VOID
3002 _ReadRFSetting(
3003         IN      PADAPTER        Adapter,
3004         IN      u8*     PROMContent,
3005         IN      bool            AutoloadFail
3006         )
3007 {
3008 }
3009
3010
3011 #if 0
3012 static VOID
3013 readAntennaDiversity(
3014         IN      PADAPTER        pAdapter,
3015         IN      u8                      *hwinfo,
3016         IN      bool            AutoLoadFail
3017         )
3018 {
3019
3020         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3021         struct registry_priv    *registry_par = &pAdapter->registrypriv;
3022
3023         if(!AutoLoadFail)
3024         {
3025                 // Antenna Diversity setting.
3026                 if(registry_par->antdiv_cfg == 2) // 2: From Efuse
3027                         pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
3028                 else
3029                         pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON,
3030
3031                 DBG_8723A("### AntDivCfg(%x)\n",pHalData->AntDivCfg);
3032
3033                 //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
3034                 //      pHalData->AntDivCfg = 0;
3035         }
3036         else
3037         {
3038                 pHalData->AntDivCfg = 0;
3039         }
3040
3041 }
3042 #endif
3043 // Read HW power down mode selection
3044 static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8  AutoloadFail)
3045 {
3046         if(AutoloadFail){
3047                 Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
3048                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
3049         }
3050         else    {
3051                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3052                         Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
3053                 //else
3054                         //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
3055
3056
3057                 //hw power down mode selection , 0:rf-off / 1:power down
3058
3059                 if(Adapter->registrypriv.hwpdn_mode==2)
3060                         Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
3061                 else
3062                         Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
3063
3064                 // decide hw if support remote wakeup function
3065                 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
3066                 Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
3067
3068                 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
3069                         //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
3070
3071                 DBG_8723A("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
3072                 Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
3073
3074                 DBG_8723A("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
3075
3076         }
3077
3078 }
3079
3080
3081
3082
3083
3084
3085 VOID
3086 Hal_EfuseParsePIDVID_8723AU(
3087         IN      PADAPTER                pAdapter,
3088         IN      u8*                     hwinfo,
3089         IN      bool                    AutoLoadFail
3090         )
3091 {
3092         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3093
3094         if(AutoLoadFail)
3095         {
3096                 pHalData->EEPROMVID = 0;
3097                 pHalData->EEPROMPID = 0;
3098         }
3099         else
3100         {
3101                         // VID, PID
3102                 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723AU]);
3103                 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723AU]);
3104
3105         }
3106
3107         MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
3108         MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
3109 }
3110
3111
3112 static void
3113 Hal_EfuseParseMACAddr_8723AU(
3114         IN      PADAPTER                padapter,
3115         IN      u8*                     hwinfo,
3116         IN      bool                    AutoLoadFail
3117         )
3118 {
3119         u16                     i, usValue;
3120         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
3121         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3122
3123         if (AutoLoadFail)
3124         {
3125 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
3126                 for (i=0; i<6; i++)
3127                         pEEPROM->mac_addr[i] = sMacAddr[i];
3128         }
3129         else
3130         {
3131                 //Read Permanent MAC address
3132 #if 1
3133                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], ETH_ALEN);
3134 #else
3135                 for(i=0; i<6; i+=2)
3136                 {
3137                         usValue = *(u16*)&hwinfo[EEPROM_MAC_ADDR_8723S+i];
3138                         *((u16*)(&pEEPROM->mac_addr[i])) = usValue;
3139                 }
3140 #endif
3141         }
3142 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
3143
3144         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
3145                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address=%02x:%02x:%02x:%02x:%02x:%02x\n",
3146                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3147                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3148                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
3149 }
3150
3151
3152 #ifdef CONFIG_EFUSE_CONFIG_FILE
3153 static u32 Hal_readPGDataFromConfigFile(
3154         PADAPTER        padapter)
3155 {
3156         u32 i;
3157         struct file *fp;
3158         mm_segment_t fs;
3159         u8 temp[3];
3160         loff_t pos = 0;
3161         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3162         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
3163
3164
3165         temp[2] = 0; // add end of string '\0'
3166
3167         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
3168         if (IS_ERR(fp)) {
3169                 pEEPROM->bloadfile_fail_flag= _TRUE;
3170                 DBG_8723A("Error, Efuse configure file doesn't exist.\n");
3171                 return _FAIL;
3172         }
3173
3174         fs = get_fs();
3175         set_fs(KERNEL_DS);
3176
3177         DBG_8723A("Efuse configure file:\n");
3178         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
3179                 vfs_read(fp, temp, 2, &pos);
3180                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
3181                 pos += 1; // Filter the space character
3182                 DBG_8723A("%02X \n", PROMContent[i]);
3183         }
3184         DBG_8723A("\n");
3185         set_fs(fs);
3186
3187         filp_close(fp, NULL);
3188
3189         pEEPROM->bloadfile_fail_flag= _FALSE;
3190         return _SUCCESS;
3191 }
3192
3193
3194 static void
3195 Hal_ReadMACAddrFromFile_8723AU(
3196         PADAPTER                padapter
3197         )
3198 {
3199         u32 i;
3200         struct file *fp;
3201         mm_segment_t fs;
3202         u8 source_addr[18];
3203         loff_t pos = 0;
3204         u32 curtime = rtw_get_current_time();
3205         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3206         u8 *head, *end;
3207
3208         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
3209         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
3210
3211         memset(source_addr, 0, 18);
3212         memset(pEEPROM->mac_addr, 0, ETH_ALEN);
3213
3214         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
3215         if (IS_ERR(fp)) {
3216                 pEEPROM->bloadmac_fail_flag = _TRUE;
3217                 DBG_8723A("Error, wifi mac address file doesn't exist.\n");
3218         } else {
3219                 fs = get_fs();
3220                 set_fs(KERNEL_DS);
3221
3222                 DBG_8723A("wifi mac address:\n");
3223                 vfs_read(fp, source_addr, 18, &pos);
3224                 source_addr[17] = ':';
3225
3226                 head = end = source_addr;
3227                 for (i=0; i<ETH_ALEN; i++) {
3228                         while (end && (*end != ':') )
3229                                 end++;
3230
3231                         if (end && (*end == ':') )
3232                                 *end = '\0';
3233
3234                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
3235
3236                         if (end) {
3237                                 end++;
3238                                 head = end;
3239                         }
3240                         DBG_8723A("%02x \n", pEEPROM->mac_addr[i]);
3241                 }
3242                 DBG_8723A("\n");
3243                 set_fs(fs);
3244
3245                 filp_close(fp, NULL);
3246         }
3247
3248         if ((!memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
3249             (!memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
3250                 pEEPROM->mac_addr[0] = 0x00;
3251                 pEEPROM->mac_addr[1] = 0xe0;
3252                 pEEPROM->mac_addr[2] = 0x4c;
3253                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
3254                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
3255                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
3256         }
3257
3258         pEEPROM->bloadmac_fail_flag = _FALSE;
3259
3260          DBG_8723A("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
3261                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
3262                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
3263                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
3264 }
3265 #endif //CONFIG_EFUSE_CONFIG_FILE
3266
3267
3268 static VOID
3269 readAdapterInfo(
3270         IN      PADAPTER        padapter
3271         )
3272 {
3273         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3274         //PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3275         u8                      hwinfo[HWSET_MAX_SIZE];
3276
3277 #ifdef CONFIG_EFUSE_CONFIG_FILE
3278         Hal_readPGDataFromConfigFile(padapter);
3279 #else //CONFIG_EFUSE_CONFIG_FILE
3280         Hal_InitPGData(padapter, hwinfo);
3281 #endif  //CONFIG_EFUSE_CONFIG_FILE
3282         Hal_EfuseParseIDCode(padapter, hwinfo);
3283         Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3284         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3285 #ifdef CONFIG_EFUSE_CONFIG_FILE
3286         Hal_ReadMACAddrFromFile_8723AU(padapter);
3287 #else //CONFIG_EFUSE_CONFIG_FILE
3288         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3289 #endif
3290         Hal_EfuseParseTxPowerInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3291         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3292         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3293
3294         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3295         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3296         _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3297 //      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3298 //      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag);
3299         Hal_EfuseParseAntennaDiversity(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3300
3301         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3302         Hal_EfuseParseCustomerID(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3303         Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3304         Hal_EfuseParseXtal_8723A(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
3305         //
3306         // The following part initialize some vars by PG info.
3307         //
3308         Hal_InitChannelPlan(padapter);
3309
3310
3311
3312         //hal_CustomizedBehavior_8723U(Adapter);
3313
3314 //      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
3315         DBG_8723A("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
3316 }
3317
3318 static void _ReadPROMContent(
3319         IN PADAPTER             Adapter
3320         )
3321 {
3322         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
3323         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3324         u8                      PROMContent[HWSET_MAX_SIZE]={0};
3325         u8                      eeValue;
3326         u32                     i;
3327         u16                     value16;
3328
3329         eeValue = rtw_read8(Adapter, REG_9346CR);
3330         // To check system boot selection.
3331         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
3332         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
3333
3334
3335         DBG_8723A("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
3336                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
3337
3338         readAdapterInfo(Adapter);
3339 }
3340
3341
3342 static VOID
3343 _InitOtherVariable(
3344         IN PADAPTER             Adapter
3345         )
3346 {
3347         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3348
3349
3350         //if(Adapter->bInHctTest){
3351         //      pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
3352         //      pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
3353         //      pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
3354         //      pMgntInfo->keepAliveLevel = 0;
3355         //}
3356
3357
3358 }
3359
3360 static VOID
3361 _ReadRFType(
3362         IN      PADAPTER        Adapter
3363         )
3364 {
3365         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3366
3367 #if DISABLE_BB_RF
3368         pHalData->rf_chip = RF_PSEUDO_11N;
3369 #else
3370         pHalData->rf_chip = RF_6052;
3371 #endif
3372 }
3373
3374 void _ReadSilmComboMode(PADAPTER Adapter)
3375 {
3376         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3377
3378         pHalData->SlimComboDbg = _FALSE;        // Default is not debug mode.
3379 }
3380
3381 //
3382 //      Description:
3383 //              We should set Efuse cell selection to WiFi cell in default.
3384 //
3385 //      Assumption:
3386 //              PASSIVE_LEVEL
3387 //
3388 //      Added by Roger, 2010.11.23.
3389 //
3390 void
3391 hal_EfuseCellSel(
3392         IN      PADAPTER        Adapter
3393         )
3394 {
3395         u32                     value32;
3396
3397         value32 = rtw_read32(Adapter, EFUSE_TEST);
3398         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
3399         rtw_write32(Adapter, EFUSE_TEST, value32);
3400 }
3401
3402 static int _ReadAdapterInfo8723AU(PADAPTER      Adapter)
3403 {
3404         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3405         u32 start=rtw_get_current_time();
3406
3407         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
3408
3409         //Efuse_InitSomeVar(Adapter);
3410
3411         hal_EfuseCellSel(Adapter);
3412
3413         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
3414         _ReadPROMContent(Adapter);
3415
3416         // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
3417         _ReadSilmComboMode(Adapter);
3418
3419         _InitOtherVariable(Adapter);
3420
3421         //MSG_8723A("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
3422
3423         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", rtw_get_passing_time_ms(start));
3424
3425         return _SUCCESS;
3426 }
3427
3428
3429 static void ReadAdapterInfo8723AU(PADAPTER Adapter)
3430 {
3431         // Read EEPROM size before call any EEPROM function
3432         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
3433
3434         _ReadAdapterInfo8723AU(Adapter);
3435 }
3436
3437
3438 #define GPIO_DEBUG_PORT_NUM 0
3439 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
3440 {
3441
3442         u32 gpioctrl;
3443         DBG_8723A("==> trigger_gpio_0...\n");
3444         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
3445         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
3446         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
3447         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3448         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
3449         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
3450         DBG_8723A("<=== trigger_gpio_0...\n");
3451
3452 }
3453
3454 /*
3455  * If variable not handled here,
3456  * some variables will be processed in SetHwReg8723A()
3457  */
3458 void SetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3459 {
3460         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3461
3462 _func_enter_;
3463
3464         switch(variable)
3465         {
3466                 case HW_VAR_RXDMA_AGG_PG_TH:
3467 #ifdef CONFIG_USB_RX_AGGREGATION
3468                         {
3469                                 u8 threshold = *val;
3470                                 if (threshold == 0)
3471                                         threshold = pHalData->UsbRxAggPageCount;
3472                                 SetHwReg8723A(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
3473                         }
3474 #endif
3475                         break;
3476
3477                 case HW_VAR_SET_RPWM:
3478                         rtw_write8(Adapter, REG_USB_HRPWM, *val);
3479                         break;
3480
3481                 case HW_VAR_TRIGGER_GPIO_0:
3482                         rtl8192cu_trigger_gpio_0(Adapter);
3483                         break;
3484
3485                 default:
3486                         SetHwReg8723A(Adapter, variable, val);
3487                         break;
3488         }
3489
3490 _func_exit_;
3491 }
3492
3493 /*
3494  * If variable not handled here,
3495  * some variables will be processed in GetHwReg8723A()
3496  */
3497 void GetHwReg8723AU(PADAPTER Adapter, u8 variable, u8* val)
3498 {
3499         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
3500
3501 _func_enter_;
3502
3503         switch (variable)
3504         {
3505                 default:
3506                         GetHwReg8723A(Adapter, variable, val);
3507                         break;
3508         }
3509
3510 _func_exit_;
3511 }
3512
3513 //
3514 //      Description:
3515 //              Query setting of specified variable.
3516 //
3517 u8
3518 GetHalDefVar8192CUsb(
3519         IN      PADAPTER                                Adapter,
3520         IN      HAL_DEF_VARIABLE                eVariable,
3521         IN      void *                                  pValue
3522         )
3523 {
3524         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3525         u8                      bResult = _SUCCESS;
3526
3527         switch(eVariable)
3528         {
3529                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3530                         *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
3531                         break;
3532                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3533                         #ifdef CONFIG_ANTENNA_DIVERSITY
3534                         *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE;
3535                         #endif
3536                         break;
3537                 case HAL_DEF_CURRENT_ANTENNA:
3538                         #ifdef CONFIG_ANTENNA_DIVERSITY
3539                         *(( u8*)pValue) = pHalData->CurAntenna;
3540                         #endif
3541                         break;
3542                 case HAL_DEF_DRVINFO_SZ:
3543                         *(( u32*)pValue) = DRVINFO_SZ;
3544                         break;
3545                 case HAL_DEF_MAX_RECVBUF_SZ:
3546                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
3547                         break;
3548                 case HAL_DEF_RX_PACKET_OFFSET:
3549                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
3550                         break;
3551                 case HAL_DEF_DBG_DUMP_RXPKT:
3552                         *(( u8*)pValue) = pHalData->bDumpRxPkt;
3553                         break;
3554                 case HAL_DEF_DBG_DM_FUNC:
3555                         *(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
3556                         break;
3557                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3558                         *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K;
3559                         break;
3560                 case HW_DEF_ODM_DBG_FLAG:
3561                         {
3562                                 u8Byte  DebugComponents = *((u32*)pValue);
3563                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3564                                 printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );
3565                         }
3566                         break;
3567                 default:
3568                         //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable));
3569                         bResult = _FAIL;
3570                         break;
3571         }
3572
3573         return bResult;
3574 }
3575
3576
3577
3578
3579 //
3580 //      Description:
3581 //              Change default setting of specified variable.
3582 //
3583 u8
3584 SetHalDefVar8192CUsb(
3585         IN      PADAPTER                                Adapter,
3586         IN      HAL_DEF_VARIABLE                eVariable,
3587         IN      void *                                  pValue
3588         )
3589 {
3590         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3591         u8                      bResult = _SUCCESS;
3592
3593         switch(eVariable)
3594         {
3595                 case HAL_DEF_DBG_DUMP_RXPKT:
3596                         pHalData->bDumpRxPkt = *(( u8*)pValue);
3597                         break;
3598                 case HAL_DEF_DBG_DM_FUNC:
3599                         {
3600                                 u8 dm_func = *(( u8*)pValue);
3601                                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3602                                 DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3603
3604                                 if(dm_func == 0){ //disable all dynamic func
3605                                         podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
3606                                         DBG_8723A("==> Disable all dynamic function...\n");
3607                                 }
3608                                 else if(dm_func == 1){//disable DIG
3609                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
3610                                         DBG_8723A("==> Disable DIG...\n");
3611                                 }
3612                                 else if(dm_func == 2){//disable High power
3613                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
3614                                 }
3615                                 else if(dm_func == 3){//disable tx power tracking
3616                                         podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
3617                                         DBG_8723A("==> Disable tx power tracking...\n");
3618                                 }
3619                                 else if(dm_func == 4){//disable BT coexistence
3620                                         pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
3621                                 }
3622                                 else if(dm_func == 5){//disable antenna diversity
3623                                         podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
3624                                 }
3625                                 else if(dm_func == 6){//turn on all dynamic func
3626                                         if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
3627                                         {
3628                                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3629                                                 pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
3630                                         }
3631                                         pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
3632                                         podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
3633                                         DBG_8723A("==> Turn on all dynamic function...\n");
3634                                 }
3635                         }
3636                         break;
3637                 case HW_DEF_FA_CNT_DUMP:
3638                         {
3639                                 u8 bRSSIDump = *((u8*)pValue);
3640                                 PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
3641                                 if(bRSSIDump)
3642                                         pDM_Odm->DebugComponents        =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
3643                                 else
3644                                         pDM_Odm->DebugComponents        = 0;
3645
3646                         }
3647                         break;
3648                 case HW_DEF_ODM_DBG_FLAG:
3649                         {
3650                                 u8Byte  DebugComponents = *((u8Byte*)pValue);
3651                                 PDM_ODM_T       pDM_Odm = &(pHalData->odmpriv);
3652                                 pDM_Odm->DebugComponents = DebugComponents;
3653                         }
3654                         break;
3655                 default:
3656                         //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
3657                         bResult = _FAIL;
3658                         break;
3659         }
3660
3661         return bResult;
3662 }
3663
3664 /*
3665 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
3666 {
3667         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(padapter);
3668         unsigned int BrateCfg = 0;
3669
3670
3671         if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
3672                 BrateCfg = mask  & 0x15F;
3673         else    //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
3674                 BrateCfg = mask  & 0x159;
3675
3676         BrateCfg |= 0x01; // default enable 1M ACK rate
3677
3678         return BrateCfg;
3679 }
3680 */
3681 void _update_response_rate(_adapter *padapter,unsigned int mask)
3682 {
3683         u8      RateIndex = 0;
3684         // Set RRSR rate table.
3685         rtw_write8(padapter, REG_RRSR, mask&0xff);
3686         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
3687
3688         // Set RTS initial rate
3689         while(mask > 0x1)
3690         {
3691                 mask = (mask>> 1);
3692                 RateIndex++;
3693         }
3694         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
3695 }
3696
3697 void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id,u8 rssi_level )
3698 {
3699         //volatile unsigned int result;
3700         u8      init_rate=0;
3701         u8      networkType, raid;
3702         u32     mask,rate_bitmap;
3703         u8      shortGIrate = _FALSE;
3704         int     supportRateNum = 0;
3705         struct sta_info *psta;
3706         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
3707         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3708         struct mlme_ext_priv    *pmlmeext = &padapter->mlmeextpriv;
3709         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3710         WLAN_BSSID_EX           *cur_network = &(pmlmeinfo->network);
3711 #ifdef CONFIG_CONCURRENT_MODE
3712         if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
3713                 pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
3714 #endif //CONFIG_CONCURRENT_MODE
3715
3716         if (mac_id >= NUM_STA) //CAM_SIZE
3717         {
3718                 return;
3719         }
3720
3721         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
3722         if(psta == NULL)
3723         {
3724                 return;
3725         }
3726
3727         switch (mac_id)
3728         {
3729                 case 0:// for infra mode
3730 #ifdef CONFIG_CONCURRENT_MODE
3731                 case 2:// first station uses macid=0, second station uses macid=2
3732 #endif
3733                         supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
3734                         networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
3735                         //pmlmeext->cur_wireless_mode = networkType;
3736                         raid = networktype_to_raid(networkType);
3737
3738                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3739                         mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
3740
3741
3742                         if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
3743                         {
3744                                 shortGIrate = _TRUE;
3745                         }
3746
3747                         break;
3748
3749                 case 1://for broadcast/multicast
3750                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3751                         if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
3752                                 networkType = WIRELESS_11B;
3753                         else
3754                                 networkType = WIRELESS_11G;
3755                         raid = networktype_to_raid(networkType);
3756
3757                         mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
3758
3759                         break;
3760
3761                 default: //for each sta in IBSS
3762                         supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
3763                         networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
3764                         //pmlmeext->cur_wireless_mode = networkType;
3765                         raid = networktype_to_raid(networkType);
3766
3767                         mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
3768
3769
3770                         //todo: support HT in IBSS
3771
3772                         break;
3773         }
3774
3775         //mask &=0x0fffffff;
3776         rate_bitmap = 0x0fffffff;
3777 #ifdef  CONFIG_ODM_REFRESH_RAMASK
3778         {
3779                 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
3780                 printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
3781                         __FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
3782         }
3783 #endif
3784
3785         mask &= rate_bitmap;
3786         mask |= ((raid<<28)&0xf0000000);
3787
3788
3789         init_rate = get_highest_rate_idx(mask)&0x3f;
3790
3791         if(pHalData->fw_ractrl == _TRUE)
3792         {
3793                 u8 arg = 0;
3794
3795                 //arg = (cam_idx-4)&0x1f;//MACID
3796                 arg = mac_id&0x1f;//MACID
3797
3798                 arg |= BIT(7);
3799
3800                 if (shortGIrate==_TRUE)
3801                         arg |= BIT(5);
3802
3803                 DBG_8723A("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
3804
3805                 rtl8192c_set_raid_cmd(padapter, mask, arg);
3806
3807         }
3808         else
3809         {
3810                 if (shortGIrate==_TRUE)
3811                         init_rate |= BIT(6);
3812
3813                 rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
3814         }
3815
3816
3817         //set ra_id
3818         psta->raid = raid;
3819         psta->init_rate = init_rate;
3820
3821         //set correct initial date rate for each mac_id
3822         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
3823 }
3824
3825 static void rtl8723au_init_default_value(PADAPTER padapter)
3826 {
3827         rtl8723a_init_default_value(padapter);
3828 }
3829
3830 static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
3831 {
3832         u8 bResult = _TRUE;
3833         switch(efunc_id){
3834
3835                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
3836                 case HAL_USB_SELECT_SUSPEND:
3837                         {
3838                                 u8 bfwpoll = *(( u8*)val);
3839                                 rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
3840                         }
3841                         break;
3842                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
3843
3844                 default:
3845                         break;
3846         }
3847         return bResult;
3848 }
3849
3850 void rtl8723au_set_hal_ops(_adapter * padapter)
3851 {
3852         struct hal_ops  *pHalFunc = &padapter->HalFunc;
3853
3854 _func_enter_;
3855
3856         padapter->HalData = kzalloc(sizeof(HAL_DATA_TYPE), GFP_KERNEL);
3857         if(padapter->HalData == NULL){
3858                 DBG_8723A("cant not alloc memory for HAL DATA \n");
3859         }
3860         //memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
3861         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
3862
3863         pHalFunc->hal_init = &rtl8723au_hal_init;
3864         pHalFunc->hal_deinit = &rtl8723au_hal_deinit;
3865
3866         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
3867
3868         pHalFunc->inirp_init = &rtl8723au_inirp_init;
3869         pHalFunc->inirp_deinit = &rtl8723au_inirp_deinit;
3870
3871         pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv;
3872         pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv;
3873
3874         pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv;
3875         pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv;
3876 #ifdef CONFIG_SW_LED
3877         pHalFunc->InitSwLeds = &rtl8723au_InitSwLeds;
3878         pHalFunc->DeInitSwLeds = &rtl8723au_DeInitSwLeds;
3879 #else //case of hw led or no led
3880         pHalFunc->InitSwLeds = NULL;
3881         pHalFunc->DeInitSwLeds = NULL;
3882 #endif//CONFIG_SW_LED
3883
3884         pHalFunc->init_default_value = &rtl8723au_init_default_value;
3885         pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure;
3886         pHalFunc->read_adapter_info = &ReadAdapterInfo8723AU;
3887
3888         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
3889         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
3890
3891         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
3892
3893         pHalFunc->SetHwRegHandler = &SetHwReg8723AU;
3894         pHalFunc->GetHwRegHandler = &GetHwReg8723AU;
3895         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
3896         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
3897
3898         pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
3899
3900         pHalFunc->hal_xmit = &rtl8192cu_hal_xmit;
3901         pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit;
3902         pHalFunc->hal_xmitframe_enqueue = &rtl8723au_hal_xmitframe_enqueue;
3903
3904 #ifdef CONFIG_HOSTAPD_MLME
3905         pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
3906 #endif
3907         pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
3908
3909         rtl8723a_set_hal_ops(pHalFunc);
3910
3911 _func_exit_;
3912
3913 }