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Merge branch 'suikan_experimental2' into develop
[trx-305dsp/dsp.git] / hirado / kernel / tools / blackfin-vdsp / sample1_ezkit_bf548 / sample1.ldf
1 /* MANAGED-BY-SYSTEM-BUILDER                                    */
2 /* VisualDSP++ 5.0 Update 8                                     */
3 /* LDF Printer version: 5.8.0.3                                 */
4 /* ldfgen.exe version: 5.8.0.3                                  */
5 /* VDSG version: 5.8.0.3                                        */
6
7 /*
8 ** ADSP-BF548 linker description file generated on Jun 09, 2010 at 22:41:24.
9 **
10 ** Copyright (C) 2000-2010 Analog Devices Inc., All Rights Reserved.
11 **
12 ** This file is generated automatically based upon the options selected
13 ** in the LDF Wizard. Changes to the LDF configuration should be made by
14 ** changing the appropriate options rather than editing this file.
15 **
16 ** Configuration:-
17 **     crt_doj:                                BF548_EZKIT_POST_basiccrt.doj
18 **     processor:                              ADSP-BF548
19 **     product_name:                           VisualDSP++ 5.0 Update 8
20 **     si_revision:                            automatic
21 **     default_silicon_revision_from_archdef:  0.0
22 **     using_cplusplus:                        true
23 **     mem_init:                               false
24 **     use_vdk:                                false
25 **     use_eh:                                 true
26 **     use_argv:                               true
27 **     running_from_internal_memory:           true
28 **     user_heap_src_file:                     C:\Build_tools\ant_build\cvsStage\_5.0ExportBlackfinReGen\Examples\Blackfin\Examples\ADSP-BF548 EZ-KIT Lite\Power_On_Self_Test\BF548_EZKIT_POST_heaptab.c
29 **     libraries_use_stdlib:                   true
30 **     libraries_use_fileio_libs:              false
31 **     libraries_use_ieeefp_emulation_libs:    false
32 **     libraries_use_eh_enabled_libs:          false
33 **     system_heap:                            L1
34 **     system_heap_min_size:                   2k
35 **     system_stack:                           L1
36 **     system_stack_min_size:                  2k
37 **     use_sdram:                              false
38 **
39 */
40
41 ARCHITECTURE(ADSP-BF548)
42
43 SEARCH_DIR($ADI_DSP/Blackfin/lib)
44
45
46 // Workarounds are enabled, exceptions are disabled.
47 #define RT_LIB_NAME(x) lib ## x ## y.dlb
48 #define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
49 #define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
50 #define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
51 #define RT_OBJ_NAME(x) x ## y.doj
52 #define RT_OBJ_NAME_MT(x) x ## mty.doj
53
54
55 $LIBRARIES = 
56
57 /*$VDSG<insert-user-libraries-at-beginning>                     */
58 /* Text inserted between these $VDSG comments will be preserved */
59 /*$VDSG<insert-user-libraries-at-beginning>                     */
60
61    RT_LIB_NAME_MT(small532)
62    ,RT_LIB_NAME_MT(io532)
63    ,RT_LIB_NAME_MT(c532)
64    ,RT_LIB_NAME_MT(event532)
65    ,RT_LIB_NAME(ssl548)
66    ,RT_LIB_NAME(drv548)
67    ,RT_LIB_NAME_MT(x532)
68    ,RT_LIB_NAME_EH_MT(cpp532)
69    ,RT_LIB_NAME_EH_MT(cpprt532)
70    ,RT_LIB_NAME(f64ieee532)
71    ,RT_LIB_NAME(dsp532)
72    ,RT_LIB_NAME(sftflt532)
73    ,RT_LIB_NAME(etsi532)
74    ,RT_OBJ_NAME_MT(idle532)
75    ,RT_LIB_NAME_MT(rt_fileio532)
76
77 /*$VDSG<insert-user-libraries-at-end>                           */
78 /* Text inserted between these $VDSG comments will be preserved */
79 /*$VDSG<insert-user-libraries-at-end>                           */
80
81    ;
82
83 $OBJECTS = 
84
85 /*$VDSG<insert-user-objects-at-beginning>                       */
86 /* Text inserted between these $VDSG comments will be preserved */
87 /*$VDSG<insert-user-objects-at-beginning>                       */
88
89      RT_LIB_NAME(profile532)
90    , $COMMAND_LINE_OBJECTS
91    , "cplbtab548.doj"
92
93 /*$VDSG<insert-user-objects-at-end>                             */
94 /* Text inserted between these $VDSG comments will be preserved */
95 /*$VDSG<insert-user-objects-at-end>                             */
96
97 /*   , RT_OBJ_NAME(crtn548) */
98    ;
99
100 $OBJS_LIBS_INTERNAL = 
101
102 /*$VDSG<insert-libraries-internal>                              */
103 /* Text inserted between these $VDSG comments will be preserved */
104 /*$VDSG<insert-libraries-internal>                              */
105
106    $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}
107
108 /*$VDSG<insert-libraries-internal-end>                          */
109 /* Text inserted between these $VDSG comments will be preserved */
110 /*$VDSG<insert-libraries-internal-end>                          */
111
112    ;
113
114 $OBJS_LIBS_NOT_EXTERNAL = 
115
116 /*$VDSG<insert-libraries-not-external>                          */
117 /* Text inserted between these $VDSG comments will be preserved */
118 /*$VDSG<insert-libraries-not-external>                          */
119
120    $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}
121
122 /*$VDSG<insert-libraries-not-external-end>                      */
123 /* Text inserted between these $VDSG comments will be preserved */
124 /*$VDSG<insert-libraries-not-external-end>                      */
125
126    ;
127
128 $OBJS_LIBS_WITH_AUTO_BREAKPOINTS = 
129
130 /*$VDSG<insert-libraries-with-auto-breakpoints>                 */
131 /* Text inserted between these $VDSG comments will be preserved */
132 /*$VDSG<insert-libraries-with-auto-breakpoints>                 */
133
134    $OBJECTS { FuncName("_main") ||
135    FuncName("___lib_prog_term") ||
136    FuncName("__primIO") ||
137    FuncName("__ov_start") ||
138    FuncName("__ov_end") ||
139    FuncName("__dbg_assert") ||
140    FuncName("__unknown_exception_occurred") ||
141    FuncName("_cplb_init") ||
142    FuncName("__KernelPanic") },
143    $LIBRARIES { FuncName("_main") ||
144    FuncName("___lib_prog_term") ||
145    FuncName("__primIO") ||
146    FuncName("__ov_start") ||
147    FuncName("__ov_end") ||
148    FuncName("__dbg_assert") ||
149    FuncName("__unknown_exception_occurred") ||
150    FuncName("_cplb_init") ||
151    FuncName("__KernelPanic") }
152
153 /*$VDSG<insert-libraries-with-auto-breakpoints-end>             */
154 /* Text inserted between these $VDSG comments will be preserved */
155 /*$VDSG<insert-libraries-with-auto-breakpoints-end>             */
156
157    ;
158
159 $OBJS_LIBS_WITHOUT_AUTO_BREAKPOINTS = 
160
161 /*$VDSG<insert-libraries-without-auto-breakpoints>              */
162 /* Text inserted between these $VDSG comments will be preserved */
163 /*$VDSG<insert-libraries-without-auto-breakpoints>              */
164
165    $OBJECTS { !FuncName("_main") &&
166    !FuncName("___lib_prog_term") &&
167    !FuncName("__primIO") &&
168    !FuncName("__ov_start") &&
169    !FuncName("__ov_end") &&
170    !FuncName("__dbg_assert") &&
171    !FuncName("__unknown_exception_occurred") &&
172    !FuncName("_cplb_init") &&
173    !FuncName("__KernelPanic") },
174    $LIBRARIES { !FuncName("_main") &&
175    !FuncName("___lib_prog_term") &&
176    !FuncName("__primIO") &&
177    !FuncName("__ov_start") &&
178    !FuncName("__ov_end") &&
179    !FuncName("__dbg_assert") &&
180    !FuncName("__unknown_exception_occurred") &&
181    !FuncName("_cplb_init") &&
182    !FuncName("__KernelPanic") }
183
184 /*$VDSG<insert-libraries-without-auto-breakpoints-end>          */
185 /* Text inserted between these $VDSG comments will be preserved */
186 /*$VDSG<insert-libraries-without-auto-breakpoints-end>          */
187
188    ;
189
190
191 /*$VDSG<insert-user-macros>                                     */
192 /* Text inserted between these $VDSG comments will be preserved */
193 /*$VDSG<insert-user-macros>                                     */
194
195
196 /*$VDSG<customize-async-macros>                                 */
197 /* This code is preserved if the LDF is re-generated.           */
198
199
200 #define ASYNC0_MEMTYPE RAM
201 #define ASYNC1_MEMTYPE RAM
202 #define ASYNC2_MEMTYPE RAM
203 #define ASYNC3_MEMTYPE RAM
204
205
206 /*$VDSG<customize-async-macros>                                 */
207
208
209 /*
210 ** Memory map.
211 **
212 ** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers (2MB)
213 ** 0xFFC00000 - 0xFFDFFFFF  System MMR registers (2MB)
214 ** 0xFFB01000 - 0xFFBFFFFF  Reserved
215 ** 0xFFB00000 - 0xFFB00FFF  Scratch SRAM (4K)
216 ** 0xFFA24000 - 0xFFAFFFFF  Reserved
217 ** 0xFFA14000 - 0xFFA23FFF  L1 ROM (64k)
218 ** 0xFFA10000 - 0XFFA13FFF  Code SRAM/CACHE (16K)
219 ** 0xFFA0C000 - 0xFFA0FFFF  Reserved
220 ** 0xFFA08000 - 0xFFA0BFFF  Instruction Bank B SRAM (16K)
221 ** 0xFFA00000 - 0xFFA07FFF  Instruction Bank A SRAM (32K)
222 ** 0xFF908000 - 0xFF9FFFFF  Reserved
223 ** 0xFF904000 - 0xFF907FFF  Data Bank B SRAM/CACHE (16k)
224 ** 0xFF900000 - 0XFF903FFF  Data Bank B SRAM (16k)
225 ** 0xFF808000 - 0xFF8FFFFF  Reserved
226 ** 0xFF804000 - 0xFF807FFF  Data Bank A SRAM/CACHE (16k)
227 ** 0xFF800000 - 0XFF803FFF  Data Bank A SRAM (16k)
228 ** 0xFEB20000 - 0xFF7FFFFF  Reserved
229 ** 0xFEB00000 - 0xFEB1FFFF  L2 SRAM (128K)
230 ** 0xEF001000 - 0xFFAFFFFF  Reserved
231 ** 0xEF000000 - 0xFF8007FF  Boot ROM (2K)
232 ** 0x30000000 - 0xEEFFFFFF  Reserved
233 ** 0x2C000000 - 0x2FFFFFFF  ASYNC MEMORY BANK 3 (64MB)
234 ** 0x28000000 - 0x2BFFFFFF  ASYNC MEMORY BANK 2 (64MB)
235 ** 0x24000000 - 0x27FFFFFF  ASYNC MEMORY BANK 1 (64MB)
236 ** 0x20000000 - 0x23FFFFFF  ASYNC MEMORY BANK 0 (64MB)
237 **            - 0x1FFFFFFF  DDR1 MEM Bank 1 MEMORY (8MB - 256MB)
238 ** 0x00000000               DDR1 MEM Bank 0 MEMORY (8MB - 256MB)
239 ** 
240 ** Notes:
241 ** 0xFF807FEF-0xFF807FFF Required by boot-loader.
242 */
243
244 MEMORY
245 {
246
247    MEM_L1_SCRATCH       { START(0xFFB00000) END(0xFFB00FFF) TYPE(RAM) WIDTH(8) }
248    MEM_L1_CODE_CACHE    { START(0xFFA10000) END(0xFFA13FFF) TYPE(RAM) WIDTH(8) }
249    MEM_L1_CODE          { START(0xFFA00000) END(0xFFA0BFFF) TYPE(RAM) WIDTH(8) }
250
251 /*   MEM_L1_DATA_B_CACHE  { START(0xFF904000) END(0xFF907FFF) TYPE(RAM) WIDTH(8) } */
252    MEM_L1_DATA_B        { START(0xFF900000) END(0xFF903FFF) TYPE(RAM) WIDTH(8) }
253
254 /*   MEM_L1_DATA_A_CACHE  { START(0xFF804000) END(0xFF807FFF) TYPE(RAM) WIDTH(8) } */
255    MEM_L1_DATA_A        { START(0xFF800000) END(0xFF807FFF) TYPE(RAM) WIDTH(8) }
256
257    MEM_L2_SRAM          { START(0xFEB00000) END(0xFEB1FFFF) TYPE(RAM) WIDTH(8) }
258
259    MEM_ASYNC3           { START(0x2C000000) END(0x2FFFFFFF) TYPE(RAM) WIDTH(8) }
260    MEM_ASYNC2           { START(0x28000000) END(0x2BFFFFFF) TYPE(RAM) WIDTH(8) }
261    MEM_ASYNC1           { START(0x24000000) END(0x27FFFFFF) TYPE(RAM) WIDTH(8) }
262    MEM_ASYNC0           { START(0x20000000) END(0x23FFFFFF) TYPE(RAM) WIDTH(8) }
263     /* 
264     ** The EBIU allows for 4 sub-banks to be accessed simultaneously
265     ** The LDF partitions the available SDRAM into 4 16MB banks which makes
266     ** the best use of the EBIU and minimizes memory access stall cycles.
267     ** bank0-heap, bank1-data, bank2-data/bsz, bank3-program
268     ** See theparts  Hardware Reference Manual, SDRAM controller section
269     ** for further information.
270     */
271    MEM_SDRAM0_BANK0     { START(0x00000004) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
272    MEM_SDRAM0_BANK1     { START(0x01000000) END(0x01FFFFFF) TYPE(RAM) WIDTH(8) }
273    MEM_SDRAM0_BANK2     { START(0x02000000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
274    MEM_SDRAM0_BANK3     { START(0x03000000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }
275
276 } /* MEMORY */
277
278 PROCESSOR p0
279 {
280    OUTPUT($COMMAND_LINE_OUTPUT_FILE)
281    RESOLVE(start, 0xFFA00000)
282    RESOLVE(___argv_string, 0xFF800000)
283    KEEP(start, _main)
284    
285    /*$VDSG<insert-user-ldf-commands>                            */
286    /* Text inserted between these $VDSG comments will be preserved */
287    /*$VDSG<insert-user-ldf-commands>                            */
288    
289    SECTIONS
290    {
291       /* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
292       ** "Speculative (and fetches made at boundary of reserved memory
293       ** space) for instruction or data fetches may cause false
294       ** protection exceptions" and "False hardware errors caused by
295       ** fetches at the boundary of reserved memory ".
296       **
297       ** Done by avoiding use of 76 bytes from at the end of blocks
298       ** that are adjacent to reserved memory. Workaround is enabled
299       ** for appropriate silicon revisions (-si-revision switch).
300       */
301       RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76)
302       RESERVE(___wab1=MEMORY_END(MEM_L1_CODE_CACHE) - 75, ___l1 = 76)
303       RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76)
304 /*      RESERVE(___wab3=MEMORY_END(MEM_L1_DATA_B_CACHE) - 75, ___l3 = 76) */
305       RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76)
306 /*      RESERVE(___wab5=MEMORY_END(MEM_L1_DATA_A_CACHE) - 75, ___l5 = 76) */
307       RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76)
308       RESERVE(___wab7=MEMORY_END(MEM_L2_SRAM) - 75, ___l7 = 76)
309       RESERVE(___wab8=MEMORY_END(MEM_ASYNC3) - 75, ___l8 = 76)
310       RESERVE(___wab9=MEMORY_END(MEM_SDRAM0_BANK3) - 75, ___l9 = 76)
311       
312       /*$VDSG<insert-new-sections-at-the-start>                 */
313       /* Text inserted between these $VDSG comments will be preserved */
314       /*$VDSG<insert-new-sections-at-the-start>                 */
315       
316       scratchpad NO_INIT
317       {
318          INPUT_SECTION_ALIGN(4)
319          
320          /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */
321          /* Text inserted between these $VDSG comments will be preserved */
322          /*$VDSG<insert-input-sections-at-the-start-of-scratchpad>  */
323          
324          INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad))
325          
326          /*$VDSG<insert-input-sections-at-the-end-of-scratchpad>  */
327          /* Text inserted between these $VDSG comments will be preserved */
328          /*$VDSG<insert-input-sections-at-the-end-of-scratchpad>  */
329          
330       } > MEM_L1_SCRATCH
331       
332       L1_code
333       {
334          INPUT_SECTION_ALIGN(4)
335          ___l1_code_cache = 0;
336          INPUT_SECTIONS($OBJS_LIBS_WITH_AUTO_BREAKPOINTS(program))
337          INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code))
338          
339          /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
340          /* Text inserted between these $VDSG comments will be preserved */
341          /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
342          
343          INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
344          INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb))
345          INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code))
346          INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program))
347          INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program))
348          INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program))
349          
350          /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
351          /* Text inserted between these $VDSG comments will be preserved */
352          /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
353          
354       } > MEM_L1_CODE
355       
356       L1_data_a_tables
357       {
358          INPUT_SECTION_ALIGN(4)
359          FORCE_CONTIGUITY
360          
361          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables>  */
362          /* Text inserted between these $VDSG comments will be preserved */
363          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_tables>  */
364          
365          INPUT_SECTIONS($OBJECTS(ctor) $LIBRARIES(ctor))
366          INPUT_SECTIONS($OBJECTS(ctorl) $LIBRARIES(ctorl))
367          INPUT_SECTIONS($OBJECTS(.gdt) $LIBRARIES(.gdt))
368          INPUT_SECTIONS($OBJECTS(.gdtl) $LIBRARIES(.gdtl))
369          
370          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables>  */
371          /* Text inserted between these $VDSG comments will be preserved */
372          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_tables>  */
373          
374       } > MEM_L1_DATA_A
375       
376       L1_data_a_1
377       {
378          INPUT_SECTION_ALIGN(4)
379          ___l1_data_cache_a = 0;
380          INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
381          INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data))
382          
383          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_1>  */
384          /* Text inserted between these $VDSG comments will be preserved */
385          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_1>  */
386          
387          RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 4096,4)
388       } > MEM_L1_DATA_A
389       
390       L1_data_a_bsz ZERO_INIT
391       {
392          INPUT_SECTION_ALIGN(4)
393          
394          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_bsz>  */
395          /* Text inserted between these $VDSG comments will be preserved */
396          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_bsz>  */
397          
398          INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz))
399          
400          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_bsz>  */
401          /* Text inserted between these $VDSG comments will be preserved */
402          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_bsz>  */
403          
404       } > MEM_L1_DATA_A
405       
406       bsz_L1_data_a ZERO_INIT
407       {
408          INPUT_SECTION_ALIGN(4)
409          
410          /*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a>  */
411          /* Text inserted between these $VDSG comments will be preserved */
412          /*$VDSG<insert-input-sections-at-the-start-of-bsz_L1_data_a>  */
413          
414          INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz))
415          INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz))
416          INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz))
417          
418          /*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a>  */
419          /* Text inserted between these $VDSG comments will be preserved */
420          /*$VDSG<insert-input-sections-at-the-end-of-bsz_L1_data_a>  */
421          
422       } > MEM_L1_DATA_A
423       
424       L1_data_a
425       {
426          INPUT_SECTION_ALIGN(4)
427          
428          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a>  */
429          /* Text inserted between these $VDSG comments will be preserved */
430          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a>  */
431          
432          INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
433          INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1))
434          INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1))
435          INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
436          INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
437          INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
438          
439          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a>  */
440          /* Text inserted between these $VDSG comments will be preserved */
441          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a>  */
442          
443       } > MEM_L1_DATA_A
444       
445       L1_data_a_2
446       {
447          INPUT_SECTION_ALIGN(4)
448          
449          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_2>  */
450          /* Text inserted between these $VDSG comments will be preserved */
451          /*$VDSG<insert-input-sections-at-the-start-of-L1_data_a_2>  */
452          
453          INPUT_SECTIONS($OBJECTS(vtbl) $LIBRARIES(vtbl))
454          INPUT_SECTIONS($OBJECTS(.frt) $LIBRARIES(.frt))
455          INPUT_SECTIONS($OBJECTS(.rtti) $LIBRARIES(.rtti))
456          INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt))
457          INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht))
458          
459          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_2>  */
460          /* Text inserted between these $VDSG comments will be preserved */
461          /*$VDSG<insert-input-sections-at-the-end-of-L1_data_a_2>  */
462          
463       } > MEM_L1_DATA_A
464       
465       L1_data_a_stack_heap
466       {
467          INPUT_SECTION_ALIGN(4)
468          RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
469          ldf_stack_space = heaps_and_stack_in_L1_data_a;
470          ldf_stack_end = (ldf_stack_space + (((heaps_and_stack_in_L1_data_a_length * 2048) / 4096) - 4)) & 0xfffffffc;
471          ldf_heap_space = ldf_stack_end + 4;
472          ldf_heap_end = (ldf_heap_space + (((heaps_and_stack_in_L1_data_a_length * 2048) / 4096) - 4)) & 0xfffffffc;
473          ldf_heap_length = ldf_heap_end - ldf_heap_space;
474       } > MEM_L1_DATA_A
475       
476       /*$VDSG<insert-new-sections-at-the-end>                   */
477       /* Text inserted between these $VDSG comments will be preserved */
478       /*$VDSG<insert-new-sections-at-the-end>                   */
479       
480    } /* SECTIONS */
481 } /* p0 */
482