hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/arm/aspeed_eeprom.h"
  18 #include "hw/i2c/i2c_mux_pca954x.h"
  19 #include "hw/i2c/smbus_eeprom.h"
  20 #include "hw/misc/pca9552.h"
  21 #include "hw/nvram/eeprom_at24c.h"
  22 #include "hw/sensor/tmp105.h"
  23 #include "hw/misc/led.h"
  24 #include "hw/qdev-properties.h"
  25 #include "sysemu/block-backend.h"
  26 #include "sysemu/reset.h"
  27 #include "hw/loader.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/units.h"
  30 #include "hw/qdev-clock.h"
  31 #include "sysemu/sysemu.h"
  32
  33 static struct arm_boot_info aspeed_board_binfo = {
  34     .board_id = -1, /* device-tree-only board */
  35 };
  36
  37 struct AspeedMachineState {
  38     /* Private */
  39     MachineState parent_obj;
  40     /* Public */
  41
  42     AspeedSoCState soc;
  43     MemoryRegion boot_rom;
  44     bool mmio_exec;
  45     uint32_t uart_chosen;
  46     char *fmc_model;
  47     char *spi_model;
  48 };
  49
  50 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
  51 #if HOST_LONG_BITS == 32
  52 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
  53 #else
  54 #define ASPEED_RAM_SIZE(sz) (sz)
  55 #endif
  56
  57 /* Palmetto hardware value: 0x120CE416 */
  58 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  59         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  60         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  61         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  62         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  63         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  64         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  65         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  66         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  67         SCU_HW_STRAP_SPI_WIDTH |                                        \
  68         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  69         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  70
  71 /* TODO: Find the actual hardware value */
  72 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  73         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  74         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  75         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  76         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  77         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  78         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  79         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  80         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  81         SCU_HW_STRAP_SPI_WIDTH |                                        \
  82         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  83         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  84
  85 /* TODO: Find the actual hardware value */
  86 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  87         AST2500_HW_STRAP1_DEFAULTS |                                    \
  88         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  89         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  90         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  91         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  92         SCU_HW_STRAP_SPI_WIDTH |                                        \
  93         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  94
  95 /* AST2500 evb hardware value: 0xF100C2E6 */
  96 #define AST2500_EVB_HW_STRAP1 ((                                        \
  97         AST2500_HW_STRAP1_DEFAULTS |                                    \
  98         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  99         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 100         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 101         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 102         SCU_HW_STRAP_MAC1_RGMII |                                       \
 103         SCU_HW_STRAP_MAC0_RGMII) &                                      \
 104         ~SCU_HW_STRAP_2ND_BOOT_WDT)
 105
 106 /* Romulus hardware value: 0xF10AD206 */
 107 #define ROMULUS_BMC_HW_STRAP1 (                                         \
 108         AST2500_HW_STRAP1_DEFAULTS |                                    \
 109         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 110         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 111         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 112         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 113         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 114         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 115
 116 /* Sonorapass hardware value: 0xF100D216 */
 117 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 118         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 119         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 120         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 121         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 122         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 123         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 124         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 125         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 126         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 127         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 128         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 129         SCU_AST2500_HW_STRAP_RESERVED1)
 130
 131 #define G220A_BMC_HW_STRAP1 (                                      \
 132         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 133         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 134         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 135         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 136         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 137         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 138         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 139         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 140         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 141         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 142         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 143         SCU_AST2500_HW_STRAP_RESERVED1)
 144
 145 /* FP5280G2 hardware value: 0XF100D286 */
 146 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 147         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 148         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 149         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 150         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 151         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 152         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 153         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 154         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 155         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 156         SCU_HW_STRAP_MAC1_RGMII |                                       \
 157         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 158         SCU_AST2500_HW_STRAP_RESERVED1)
 159
 160 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 161 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 162
 163 /* Quanta-Q71l hardware value */
 164 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 165         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 166         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 167         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 168         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 169         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 170         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 171         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 172         SCU_HW_STRAP_SPI_WIDTH |                                        \
 173         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 174         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 175
 176 /* AST2600 evb hardware value */
 177 #define AST2600_EVB_HW_STRAP1 0x000000C0
 178 #define AST2600_EVB_HW_STRAP2 0x00000003
 179
 180 /* Tacoma hardware value */
 181 #define TACOMA_BMC_HW_STRAP1  0x00000000
 182 #define TACOMA_BMC_HW_STRAP2  0x00000040
 183
 184 /* Rainier hardware value: (QEMU prototype) */
 185 #define RAINIER_BMC_HW_STRAP1 0x00422016
 186 #define RAINIER_BMC_HW_STRAP2 0x80000848
 187
 188 /* Fuji hardware value */
 189 #define FUJI_BMC_HW_STRAP1    0x00000000
 190 #define FUJI_BMC_HW_STRAP2    0x00000000
 191
 192 /* Bletchley hardware value */
 193 /* TODO: Leave same as EVB for now. */
 194 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 195 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 196
 197 /* Qualcomm DC-SCM hardware value */
 198 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 199 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 200
 201 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 202 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 203 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 204 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 205 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 206 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 207 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 208
 209 static void aspeed_write_smpboot(ARMCPU *cpu,
 210                                  const struct arm_boot_info *info)
 211 {
 212     AddressSpace *as = arm_boot_address_space(cpu, info);
 213     static const ARMInsnFixup poll_mailbox_ready[] = {
 214         /*
 215          * r2 = per-cpu go sign value
 216          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 217          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 218          */
 219         { 0xee100fb0 },  /* mrc     p15, 0, r0, c0, c0, 5 */
 220         { 0xe21000ff },  /* ands    r0, r0, #255          */
 221         { 0xe59f201c },  /* ldr     r2, [pc, #28]         */
 222         { 0xe1822000 },  /* orr     r2, r2, r0            */
 223
 224         { 0xe59f1018 },  /* ldr     r1, [pc, #24]         */
 225         { 0xe59f0018 },  /* ldr     r0, [pc, #24]         */
 226
 227         { 0xe320f002 },  /* wfe                           */
 228         { 0xe5904000 },  /* ldr     r4, [r0]              */
 229         { 0xe1520004 },  /* cmp     r2, r4                */
 230         { 0x1afffffb },  /* bne     <wfe>                 */
 231         { 0xe591f000 },  /* ldr     pc, [r1]              */
 232         { AST_SMP_MBOX_GOSIGN },
 233         { AST_SMP_MBOX_FIELD_ENTRY },
 234         { AST_SMP_MBOX_FIELD_GOSIGN },
 235         { 0, FIXUP_TERMINATOR }
 236     };
 237     static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
 238
 239     arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
 240                          poll_mailbox_ready, fixupcontext);
 241 }
 242
 243 static void aspeed_reset_secondary(ARMCPU *cpu,
 244                                    const struct arm_boot_info *info)
 245 {
 246     AddressSpace *as = arm_boot_address_space(cpu, info);
 247     CPUState *cs = CPU(cpu);
 248
 249     /* info->smp_bootreg_addr */
 250     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 251                                MEMTXATTRS_UNSPECIFIED, NULL);
 252     cpu_set_pc(cs, info->smp_loader_start);
 253 }
 254
 255 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 256                            Error **errp)
 257 {
 258     g_autofree void *storage = NULL;
 259     int64_t size;
 260
 261     /* The block backend size should have already been 'validated' by
 262      * the creation of the m25p80 object.
 263      */
 264     size = blk_getlength(blk);
 265     if (size <= 0) {
 266         error_setg(errp, "failed to get flash size");
 267         return;
 268     }
 269
 270     if (rom_size > size) {
 271         rom_size = size;
 272     }
 273
 274     storage = g_malloc0(rom_size);
 275     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 276         error_setg(errp, "failed to read the initial flash content");
 277         return;
 278     }
 279
 280     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 281 }
 282
 283 /*
 284  * Create a ROM and copy the flash contents at the expected address
 285  * (0x0). Boots faster than execute-in-place.
 286  */
 287 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
 288                                     uint64_t rom_size)
 289 {
 290     AspeedSoCState *soc = &bmc->soc;
 291
 292     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
 293                            &error_abort);
 294     memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
 295                                         &bmc->boot_rom, 1);
 296     write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
 297 }
 298
 299 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 300                                       unsigned int count, int unit0)
 301 {
 302     int i;
 303
 304     if (!flashtype) {
 305         return;
 306     }
 307
 308     for (i = 0; i < count; ++i) {
 309         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 310         DeviceState *dev;
 311
 312         dev = qdev_new(flashtype);
 313         if (dinfo) {
 314             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 315         }
 316         qdev_prop_set_uint8(dev, "cs", i);
 317         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 318     }
 319 }
 320
 321 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 322 {
 323         DeviceState *card;
 324
 325         if (!dinfo) {
 326             return;
 327         }
 328         card = qdev_new(TYPE_SD_CARD);
 329         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 330                                 &error_fatal);
 331         qdev_realize_and_unref(card,
 332                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 333                                &error_fatal);
 334 }
 335
 336 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 337 {
 338     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 339     AspeedSoCState *s = &bmc->soc;
 340     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 341     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 342
 343     aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
 344     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 345         if (uart == uart_chosen) {
 346             continue;
 347         }
 348         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 349     }
 350 }
 351
 352 static void aspeed_machine_init(MachineState *machine)
 353 {
 354     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 355     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 356     AspeedSoCClass *sc;
 357     int i;
 358     NICInfo *nd = &nd_table[0];
 359
 360     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 361
 362     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 363
 364     /*
 365      * This will error out if the RAM size is not supported by the
 366      * memory controller of the SoC.
 367      */
 368     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 369                              &error_fatal);
 370
 371     for (i = 0; i < sc->macs_num; i++) {
 372         if ((amc->macs_mask & (1 << i)) && nd->used) {
 373             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 374             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 375             nd++;
 376         }
 377     }
 378
 379     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 380                             &error_abort);
 381     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 382                             &error_abort);
 383     object_property_set_link(OBJECT(&bmc->soc), "memory",
 384                              OBJECT(get_system_memory()), &error_abort);
 385     object_property_set_link(OBJECT(&bmc->soc), "dram",
 386                              OBJECT(machine->ram), &error_abort);
 387     if (machine->kernel_filename) {
 388         /*
 389          * When booting with a -kernel command line there is no u-boot
 390          * that runs to unlock the SCU. In this case set the default to
 391          * be unlocked as the kernel expects
 392          */
 393         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 394                                 ASPEED_SCU_PROT_KEY, &error_abort);
 395     }
 396     connect_serial_hds_to_uarts(bmc);
 397     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 398
 399     if (defaults_enabled()) {
 400         aspeed_board_init_flashes(&bmc->soc.fmc,
 401                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 402                               amc->num_cs, 0);
 403         aspeed_board_init_flashes(&bmc->soc.spi[0],
 404                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 405                               1, amc->num_cs);
 406     }
 407
 408     if (machine->kernel_filename && sc->num_cpus > 1) {
 409         /* With no u-boot we must set up a boot stub for the secondary CPU */
 410         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 411         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 412                                0x80, &error_abort);
 413         memory_region_add_subregion(get_system_memory(),
 414                                     AST_SMP_MAILBOX_BASE, smpboot);
 415
 416         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 417         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 418         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 419     }
 420
 421     aspeed_board_binfo.ram_size = machine->ram_size;
 422     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 423
 424     if (amc->i2c_init) {
 425         amc->i2c_init(bmc);
 426     }
 427
 428     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 429         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 430                            drive_get(IF_SD, 0, i));
 431     }
 432
 433     if (bmc->soc.emmc.num_slots) {
 434         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 435                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 436     }
 437
 438     if (!bmc->mmio_exec) {
 439         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 440
 441         if (mtd0) {
 442             uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 443             aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size);
 444         }
 445     }
 446
 447     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 448 }
 449
 450 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 451 {
 452     AspeedSoCState *soc = &bmc->soc;
 453     DeviceState *dev;
 454     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 455
 456     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 457      * enough to provide basic RTC features. Alarms will be missing */
 458     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 459
 460     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 461                           eeprom_buf);
 462
 463     /* add a TMP423 temperature sensor */
 464     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 465                                          "tmp423", 0x4c));
 466     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 467     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 468     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 469     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 470 }
 471
 472 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 473 {
 474     AspeedSoCState *soc = &bmc->soc;
 475
 476     /*
 477      * The quanta-q71l platform expects tmp75s which are compatible with
 478      * tmp105s.
 479      */
 480     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 481     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 482     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 483
 484     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 485     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 486     /* TODO: Add Memory Riser i2c mux and eeproms. */
 487
 488     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 489     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 490
 491     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 492
 493     /* i2c-7 */
 494     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 495     /*        - i2c@0: pmbus@59 */
 496     /*        - i2c@1: pmbus@58 */
 497     /*        - i2c@2: pmbus@58 */
 498     /*        - i2c@3: pmbus@59 */
 499
 500     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 501     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 502 }
 503
 504 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 505 {
 506     AspeedSoCState *soc = &bmc->soc;
 507     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 508
 509     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 510                           eeprom_buf);
 511
 512     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 513     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 514                      TYPE_TMP105, 0x4d);
 515 }
 516
 517 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 518 {
 519     AspeedSoCState *soc = &bmc->soc;
 520     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 521
 522     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 523                           eeprom_buf);
 524
 525     /* LM75 is compatible with TMP105 driver */
 526     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 527                      TYPE_TMP105, 0x4d);
 528 }
 529
 530 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 531 {
 532     AspeedSoCState *soc = &bmc->soc;
 533
 534     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
 535     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
 536                           yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
 537     /* TMP421 */
 538     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
 539     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
 540     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
 541
 542 }
 543
 544 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 545 {
 546     AspeedSoCState *soc = &bmc->soc;
 547
 548     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 549      * good enough */
 550     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 551 }
 552
 553 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 554 {
 555     AspeedSoCState *soc = &bmc->soc;
 556
 557     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
 558     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
 559                           tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
 560     /* TMP421 */
 561     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
 562     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
 563     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
 564 }
 565
 566 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 567 {
 568     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 569                             TYPE_PCA9552, addr);
 570 }
 571
 572 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 573 {
 574     AspeedSoCState *soc = &bmc->soc;
 575
 576     /* bus 2 : */
 577     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 578     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 579     /* bus 2 : pca9546 @ 0x73 */
 580
 581     /* bus 3 : pca9548 @ 0x70 */
 582
 583     /* bus 4 : */
 584     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 585     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 586                           eeprom4_54);
 587     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 588     create_pca9552(soc, 4, 0x76);
 589     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 590     create_pca9552(soc, 4, 0x77);
 591
 592     /* bus 6 : */
 593     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 594     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 595     /* bus 6 : pca9546 @ 0x73 */
 596
 597     /* bus 8 : */
 598     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 599     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 600                           eeprom8_56);
 601     create_pca9552(soc, 8, 0x60);
 602     create_pca9552(soc, 8, 0x61);
 603     /* bus 8 : adc128d818 @ 0x1d */
 604     /* bus 8 : adc128d818 @ 0x1f */
 605
 606     /*
 607      * bus 13 : pca9548 @ 0x71
 608      *      - channel 3:
 609      *          - tmm421 @ 0x4c
 610      *          - tmp421 @ 0x4e
 611      *          - tmp421 @ 0x4f
 612      */
 613
 614 }
 615
 616 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 617 {
 618     static const struct {
 619         unsigned gpio_id;
 620         LEDColor color;
 621         const char *description;
 622         bool gpio_polarity;
 623     } pca1_leds[] = {
 624         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 625         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 626         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 627     };
 628     AspeedSoCState *soc = &bmc->soc;
 629     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 630     DeviceState *dev;
 631     LEDState *led;
 632
 633     /* Bus 3: TODO bmp280@77 */
 634     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 635     qdev_prop_set_string(dev, "description", "pca1");
 636     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 637                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 638                                 &error_fatal);
 639
 640     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 641         led = led_create_simple(OBJECT(bmc),
 642                                 pca1_leds[i].gpio_polarity,
 643                                 pca1_leds[i].color,
 644                                 pca1_leds[i].description);
 645         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 646                               qdev_get_gpio_in(DEVICE(led), 0));
 647     }
 648     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 649     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 650     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 651     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 652
 653     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 654     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 655                      0x4a);
 656
 657     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 658      * good enough */
 659     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 660
 661     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 662                           eeprom_buf);
 663     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 664     qdev_prop_set_string(dev, "description", "pca0");
 665     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 666                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 667                                 &error_fatal);
 668     /* Bus 11: TODO ucd90160@64 */
 669 }
 670
 671 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 672 {
 673     AspeedSoCState *soc = &bmc->soc;
 674     DeviceState *dev;
 675
 676     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 677                                          "emc1413", 0x4c));
 678     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 679     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 680     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 681
 682     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 683                                          "emc1413", 0x4c));
 684     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 685     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 686     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 687
 688     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 689                                          "emc1413", 0x4c));
 690     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 691     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 692     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 693
 694     static uint8_t eeprom_buf[2 * 1024] = {
 695             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 696             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 697             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 698             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 699             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 700             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 701             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 702     };
 703     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 704                           eeprom_buf);
 705 }
 706
 707 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 708 {
 709     AspeedSoCState *soc = &bmc->soc;
 710     I2CSlave *i2c_mux;
 711
 712     /* The at24c256 */
 713     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 714
 715     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 716     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 717                      0x48);
 718     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 719                      0x49);
 720
 721     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 722                      "pca9546", 0x70);
 723     /* It expects a TMP112 but a TMP105 is compatible */
 724     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 725                      0x4a);
 726
 727     /* It expects a ds3232 but a ds1338 is good enough */
 728     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 729
 730     /* It expects a pca9555 but a pca9552 is compatible */
 731     create_pca9552(soc, 8, 0x30);
 732 }
 733
 734 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 735 {
 736     AspeedSoCState *soc = &bmc->soc;
 737     I2CSlave *i2c_mux;
 738
 739     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 740
 741     create_pca9552(soc, 3, 0x61);
 742
 743     /* The rainier expects a TMP275 but a TMP105 is compatible */
 744     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 745                      0x48);
 746     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 747                      0x49);
 748     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 749                      0x4a);
 750     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 751                                       "pca9546", 0x70);
 752     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 753     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 754     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 755     create_pca9552(soc, 4, 0x60);
 756
 757     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 758                      0x48);
 759     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 760                      0x49);
 761     create_pca9552(soc, 5, 0x60);
 762     create_pca9552(soc, 5, 0x61);
 763     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 764                                       "pca9546", 0x70);
 765     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 766     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 767
 768     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 769                      0x48);
 770     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 771                      0x4a);
 772     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 773                      0x4b);
 774     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 775                                       "pca9546", 0x70);
 776     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 777     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 778     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 779     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 780
 781     create_pca9552(soc, 7, 0x30);
 782     create_pca9552(soc, 7, 0x31);
 783     create_pca9552(soc, 7, 0x32);
 784     create_pca9552(soc, 7, 0x33);
 785     create_pca9552(soc, 7, 0x60);
 786     create_pca9552(soc, 7, 0x61);
 787     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 788     /* Bus 7: TODO si7021-a20@20 */
 789     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 790                      0x48);
 791     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 792     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 793     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 794
 795     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 796                      0x48);
 797     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 798                      0x4a);
 799     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
 800                           64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
 801     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
 802                           64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
 803     create_pca9552(soc, 8, 0x60);
 804     create_pca9552(soc, 8, 0x61);
 805     /* Bus 8: ucd90320@11 */
 806     /* Bus 8: ucd90320@b */
 807     /* Bus 8: ucd90320@c */
 808
 809     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 810     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 811     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 812
 813     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 814     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 815     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 816
 817     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 818                      0x48);
 819     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 820                      0x49);
 821     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 822                                       "pca9546", 0x70);
 823     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 824     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 825     create_pca9552(soc, 11, 0x60);
 826
 827
 828     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 829     create_pca9552(soc, 13, 0x60);
 830
 831     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 832     create_pca9552(soc, 14, 0x60);
 833
 834     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 835     create_pca9552(soc, 15, 0x60);
 836 }
 837
 838 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 839                                  I2CBus **channels)
 840 {
 841     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 842     for (int i = 0; i < 8; i++) {
 843         channels[i] = pca954x_i2c_get_bus(mux, i);
 844     }
 845 }
 846
 847 #define TYPE_LM75 TYPE_TMP105
 848 #define TYPE_TMP75 TYPE_TMP105
 849 #define TYPE_TMP422 "tmp422"
 850
 851 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 852 {
 853     AspeedSoCState *soc = &bmc->soc;
 854     I2CBus *i2c[144] = {};
 855
 856     for (int i = 0; i < 16; i++) {
 857         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 858     }
 859     I2CBus *i2c180 = i2c[2];
 860     I2CBus *i2c480 = i2c[8];
 861     I2CBus *i2c600 = i2c[11];
 862
 863     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 864     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 865     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 866     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 867     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 868     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 869     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 870     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 871     for (int i = 0; i < 8; i++) {
 872         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 873     }
 874
 875     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 876     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 877
 878     /*
 879      * EEPROM 24c64 size is 64Kbits or 8 Kbytes
 880      *        24c02 size is 2Kbits or 256 bytes
 881      */
 882     at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
 883     at24c_eeprom_init(i2c[20], 0x50, 256);
 884     at24c_eeprom_init(i2c[22], 0x52, 256);
 885
 886     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 887     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 888     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 889     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 890
 891     at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
 892     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 893
 894     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 895     at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
 896     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 897     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 898
 899     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 900     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 901
 902     at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
 903     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 904     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 905     at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
 906     at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
 907     at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
 908     at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
 909
 910     at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
 911     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 912     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 913     at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
 914     at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
 915     at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
 916     at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
 917     at24c_eeprom_init(i2c[28], 0x50, 256);
 918
 919     for (int i = 0; i < 8; i++) {
 920         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 921         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 922         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 923         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 924     }
 925 }
 926
 927 #define TYPE_TMP421 "tmp421"
 928
 929 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 930 {
 931     AspeedSoCState *soc = &bmc->soc;
 932     I2CBus *i2c[13] = {};
 933     for (int i = 0; i < 13; i++) {
 934         if ((i == 8) || (i == 11)) {
 935             continue;
 936         }
 937         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 938     }
 939
 940     /* Bus 0 - 5 all have the same config. */
 941     for (int i = 0; i < 6; i++) {
 942         /* Missing model: ti,ina230 @ 0x45 */
 943         /* Missing model: mps,mp5023 @ 0x40 */
 944         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 945         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 946         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 947         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 948         /* Missing model: fsc,fusb302 @ 0x22 */
 949     }
 950
 951     /* Bus 6 */
 952     at24c_eeprom_init(i2c[6], 0x56, 65536);
 953     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 954     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 955
 956
 957     /* Bus 7 */
 958     at24c_eeprom_init(i2c[7], 0x54, 65536);
 959
 960     /* Bus 9 */
 961     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 962
 963     /* Bus 10 */
 964     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 965     /* Missing model: ti,hdc1080 @ 0x40 */
 966     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 967
 968     /* Bus 12 */
 969     /* Missing model: adi,adm1278 @ 0x11 */
 970     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 971     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 972     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 973 }
 974
 975 static void fby35_i2c_init(AspeedMachineState *bmc)
 976 {
 977     AspeedSoCState *soc = &bmc->soc;
 978     I2CBus *i2c[16];
 979
 980     for (int i = 0; i < 16; i++) {
 981         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 982     }
 983
 984     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 985     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 986     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 987     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 988     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 989     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 990
 991     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
 992     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
 993     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
 994                           fby35_nic_fruid_len);
 995     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
 996                           fby35_bb_fruid_len);
 997     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
 998                           fby35_bmc_fruid_len);
 999
1000     /*
1001      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1002      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1003      * each.
1004      */
1005 }
1006
1007 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1008 {
1009     AspeedSoCState *soc = &bmc->soc;
1010
1011     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1012 }
1013
1014 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1015 {
1016     AspeedSoCState *soc = &bmc->soc;
1017     I2CSlave *therm_mux, *cpuvr_mux;
1018
1019     /* Create the generic DC-SCM hardware */
1020     qcom_dc_scm_bmc_i2c_init(bmc);
1021
1022     /* Now create the Firework specific hardware */
1023
1024     /* I2C7 CPUVR MUX */
1025     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1026                                         "pca9546", 0x70);
1027     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1028     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1029     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1030     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1031
1032     /* I2C8 Thermal Diodes*/
1033     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1034                                         "pca9548", 0x70);
1035     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1036     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1037     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1038     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1039     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1040
1041     /* I2C9 Fan Controller (MAX31785) */
1042     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1043     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1044 }
1045
1046 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1047 {
1048     return ASPEED_MACHINE(obj)->mmio_exec;
1049 }
1050
1051 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1052 {
1053     ASPEED_MACHINE(obj)->mmio_exec = value;
1054 }
1055
1056 static void aspeed_machine_instance_init(Object *obj)
1057 {
1058     ASPEED_MACHINE(obj)->mmio_exec = false;
1059 }
1060
1061 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1062 {
1063     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1064     return g_strdup(bmc->fmc_model);
1065 }
1066
1067 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1068 {
1069     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1070
1071     g_free(bmc->fmc_model);
1072     bmc->fmc_model = g_strdup(value);
1073 }
1074
1075 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1076 {
1077     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1078     return g_strdup(bmc->spi_model);
1079 }
1080
1081 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1082 {
1083     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1084
1085     g_free(bmc->spi_model);
1086     bmc->spi_model = g_strdup(value);
1087 }
1088
1089 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1090 {
1091     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1092     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1093     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1094
1095     return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1);
1096 }
1097
1098 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1099 {
1100     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1101     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1102     AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1103     int val;
1104
1105     if (sscanf(value, "uart%u", &val) != 1) {
1106         error_setg(errp, "Bad value for \"uart\" property");
1107         return;
1108     }
1109
1110     /* The number of UART depends on the SoC */
1111     if (val < 1 || val > sc->uarts_num) {
1112         error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num);
1113         return;
1114     }
1115     bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1;
1116 }
1117
1118 static void aspeed_machine_class_props_init(ObjectClass *oc)
1119 {
1120     object_class_property_add_bool(oc, "execute-in-place",
1121                                    aspeed_get_mmio_exec,
1122                                    aspeed_set_mmio_exec);
1123     object_class_property_set_description(oc, "execute-in-place",
1124                            "boot directly from CE0 flash device");
1125
1126     object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1127                                   aspeed_set_bmc_console);
1128     object_class_property_set_description(oc, "bmc-console",
1129                            "Change the default UART to \"uartX\"");
1130
1131     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1132                                    aspeed_set_fmc_model);
1133     object_class_property_set_description(oc, "fmc-model",
1134                                           "Change the FMC Flash model");
1135     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1136                                    aspeed_set_spi_model);
1137     object_class_property_set_description(oc, "spi-model",
1138                                           "Change the SPI Flash model");
1139 }
1140
1141 static int aspeed_soc_num_cpus(const char *soc_name)
1142 {
1143    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1144    return sc->num_cpus;
1145 }
1146
1147 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1148 {
1149     MachineClass *mc = MACHINE_CLASS(oc);
1150     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1151
1152     mc->init = aspeed_machine_init;
1153     mc->no_floppy = 1;
1154     mc->no_cdrom = 1;
1155     mc->no_parallel = 1;
1156     mc->default_ram_id = "ram";
1157     amc->macs_mask = ASPEED_MAC0_ON;
1158     amc->uart_default = ASPEED_DEV_UART5;
1159
1160     aspeed_machine_class_props_init(oc);
1161 }
1162
1163 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1164 {
1165     MachineClass *mc = MACHINE_CLASS(oc);
1166     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1167
1168     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1169     amc->soc_name  = "ast2400-a1";
1170     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1171     amc->fmc_model = "n25q256a";
1172     amc->spi_model = "mx25l25635f";
1173     amc->num_cs    = 1;
1174     amc->i2c_init  = palmetto_bmc_i2c_init;
1175     mc->default_ram_size       = 256 * MiB;
1176     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1177         aspeed_soc_num_cpus(amc->soc_name);
1178 };
1179
1180 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1181 {
1182     MachineClass *mc = MACHINE_CLASS(oc);
1183     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1184
1185     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1186     amc->soc_name  = "ast2400-a1";
1187     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1188     amc->fmc_model = "n25q256a";
1189     amc->spi_model = "mx25l25635e";
1190     amc->num_cs    = 1;
1191     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1192     mc->default_ram_size       = 128 * MiB;
1193     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1194         aspeed_soc_num_cpus(amc->soc_name);
1195 }
1196
1197 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1198                                                         void *data)
1199 {
1200     MachineClass *mc = MACHINE_CLASS(oc);
1201     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1202
1203     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1204     amc->soc_name  = "ast2400-a1";
1205     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1206     amc->fmc_model = "mx25l25635e";
1207     amc->spi_model = "mx25l25635e";
1208     amc->num_cs    = 1;
1209     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1210     amc->i2c_init  = palmetto_bmc_i2c_init;
1211     mc->default_ram_size = 256 * MiB;
1212 }
1213
1214 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1215                                                             void *data)
1216 {
1217     MachineClass *mc = MACHINE_CLASS(oc);
1218     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1219
1220     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1221     amc->soc_name  = "ast2500-a1";
1222     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1223     amc->fmc_model = "mx25l25635e";
1224     amc->spi_model = "mx25l25635e";
1225     amc->num_cs    = 1;
1226     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1227     amc->i2c_init  = palmetto_bmc_i2c_init;
1228     mc->default_ram_size = 512 * MiB;
1229     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1230         aspeed_soc_num_cpus(amc->soc_name);
1231 }
1232
1233 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1234 {
1235     MachineClass *mc = MACHINE_CLASS(oc);
1236     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1237
1238     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1239     amc->soc_name  = "ast2500-a1";
1240     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1241     amc->fmc_model = "mx25l25635e";
1242     amc->spi_model = "mx25l25635f";
1243     amc->num_cs    = 1;
1244     amc->i2c_init  = ast2500_evb_i2c_init;
1245     mc->default_ram_size       = 512 * MiB;
1246     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1247         aspeed_soc_num_cpus(amc->soc_name);
1248 };
1249
1250 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1251 {
1252     MachineClass *mc = MACHINE_CLASS(oc);
1253     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1254
1255     mc->desc       = "Facebook YosemiteV2 BMC (ARM1176)";
1256     amc->soc_name  = "ast2500-a1";
1257     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1258     amc->hw_strap2 = 0;
1259     amc->fmc_model = "n25q256a";
1260     amc->spi_model = "mx25l25635e";
1261     amc->num_cs    = 2;
1262     amc->i2c_init  = yosemitev2_bmc_i2c_init;
1263     mc->default_ram_size       = 512 * MiB;
1264     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1265         aspeed_soc_num_cpus(amc->soc_name);
1266 };
1267
1268 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1269 {
1270     MachineClass *mc = MACHINE_CLASS(oc);
1271     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1272
1273     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1274     amc->soc_name  = "ast2500-a1";
1275     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1276     amc->fmc_model = "n25q256a";
1277     amc->spi_model = "mx66l1g45g";
1278     amc->num_cs    = 2;
1279     amc->i2c_init  = romulus_bmc_i2c_init;
1280     mc->default_ram_size       = 512 * MiB;
1281     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1282         aspeed_soc_num_cpus(amc->soc_name);
1283 };
1284
1285 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1286 {
1287     MachineClass *mc = MACHINE_CLASS(oc);
1288     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1289
1290     mc->desc       = "Facebook Tiogapass BMC (ARM1176)";
1291     amc->soc_name  = "ast2500-a1";
1292     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1293     amc->hw_strap2 = 0;
1294     amc->fmc_model = "n25q256a";
1295     amc->spi_model = "mx25l25635e";
1296     amc->num_cs    = 2;
1297     amc->i2c_init  = tiogapass_bmc_i2c_init;
1298     mc->default_ram_size       = 1 * GiB;
1299     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1300         aspeed_soc_num_cpus(amc->soc_name);
1301         aspeed_soc_num_cpus(amc->soc_name);
1302 };
1303
1304 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1305 {
1306     MachineClass *mc = MACHINE_CLASS(oc);
1307     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1308
1309     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1310     amc->soc_name  = "ast2500-a1";
1311     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1312     amc->fmc_model = "mx66l1g45g";
1313     amc->spi_model = "mx66l1g45g";
1314     amc->num_cs    = 2;
1315     amc->i2c_init  = sonorapass_bmc_i2c_init;
1316     mc->default_ram_size       = 512 * MiB;
1317     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1318         aspeed_soc_num_cpus(amc->soc_name);
1319 };
1320
1321 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1322 {
1323     MachineClass *mc = MACHINE_CLASS(oc);
1324     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1325
1326     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1327     amc->soc_name  = "ast2500-a1";
1328     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1329     amc->fmc_model = "mx25l25635f";
1330     amc->spi_model = "mx66l1g45g";
1331     amc->num_cs    = 2;
1332     amc->i2c_init  = witherspoon_bmc_i2c_init;
1333     mc->default_ram_size = 512 * MiB;
1334     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1335         aspeed_soc_num_cpus(amc->soc_name);
1336 };
1337
1338 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1339 {
1340     MachineClass *mc = MACHINE_CLASS(oc);
1341     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1342
1343     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1344     amc->soc_name  = "ast2600-a3";
1345     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1346     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1347     amc->fmc_model = "mx66u51235f";
1348     amc->spi_model = "mx66u51235f";
1349     amc->num_cs    = 1;
1350     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1351                      ASPEED_MAC3_ON;
1352     amc->i2c_init  = ast2600_evb_i2c_init;
1353     mc->default_ram_size = 1 * GiB;
1354     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1355         aspeed_soc_num_cpus(amc->soc_name);
1356 };
1357
1358 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1359 {
1360     MachineClass *mc = MACHINE_CLASS(oc);
1361     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1362
1363     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1364     amc->soc_name  = "ast2600-a3";
1365     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1366     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1367     amc->fmc_model = "mx66l1g45g";
1368     amc->spi_model = "mx66l1g45g";
1369     amc->num_cs    = 2;
1370     amc->macs_mask  = ASPEED_MAC2_ON;
1371     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1372     mc->default_ram_size = 1 * GiB;
1373     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1374         aspeed_soc_num_cpus(amc->soc_name);
1375 };
1376
1377 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1378 {
1379     MachineClass *mc = MACHINE_CLASS(oc);
1380     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1381
1382     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1383     amc->soc_name  = "ast2500-a1";
1384     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1385     amc->fmc_model = "n25q512a";
1386     amc->spi_model = "mx25l25635e";
1387     amc->num_cs    = 2;
1388     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1389     amc->i2c_init  = g220a_bmc_i2c_init;
1390     mc->default_ram_size = 1024 * MiB;
1391     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1392         aspeed_soc_num_cpus(amc->soc_name);
1393 };
1394
1395 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1396 {
1397     MachineClass *mc = MACHINE_CLASS(oc);
1398     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1399
1400     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1401     amc->soc_name  = "ast2500-a1";
1402     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1403     amc->fmc_model = "n25q512a";
1404     amc->spi_model = "mx25l25635e";
1405     amc->num_cs    = 2;
1406     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1407     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1408     mc->default_ram_size = 512 * MiB;
1409     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1410         aspeed_soc_num_cpus(amc->soc_name);
1411 };
1412
1413 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1414 {
1415     MachineClass *mc = MACHINE_CLASS(oc);
1416     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1417
1418     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1419     amc->soc_name  = "ast2600-a3";
1420     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1421     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1422     amc->fmc_model = "mx66l1g45g";
1423     amc->spi_model = "mx66l1g45g";
1424     amc->num_cs    = 2;
1425     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1426     amc->i2c_init  = rainier_bmc_i2c_init;
1427     mc->default_ram_size = 1 * GiB;
1428     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1429         aspeed_soc_num_cpus(amc->soc_name);
1430 };
1431
1432 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1433
1434 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1435 {
1436     MachineClass *mc = MACHINE_CLASS(oc);
1437     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1438
1439     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1440     amc->soc_name = "ast2600-a3";
1441     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1442     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1443     amc->fmc_model = "mx66l1g45g";
1444     amc->spi_model = "mx66l1g45g";
1445     amc->num_cs = 2;
1446     amc->macs_mask = ASPEED_MAC3_ON;
1447     amc->i2c_init = fuji_bmc_i2c_init;
1448     amc->uart_default = ASPEED_DEV_UART1;
1449     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1450     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1451         aspeed_soc_num_cpus(amc->soc_name);
1452 };
1453
1454 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1455
1456 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1457 {
1458     MachineClass *mc = MACHINE_CLASS(oc);
1459     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1460
1461     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1462     amc->soc_name  = "ast2600-a3";
1463     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1464     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1465     amc->fmc_model = "w25q01jvq";
1466     amc->spi_model = NULL;
1467     amc->num_cs    = 2;
1468     amc->macs_mask = ASPEED_MAC2_ON;
1469     amc->i2c_init  = bletchley_bmc_i2c_init;
1470     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1471     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1472         aspeed_soc_num_cpus(amc->soc_name);
1473 }
1474
1475 static void fby35_reset(MachineState *state, ShutdownCause reason)
1476 {
1477     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1478     AspeedGPIOState *gpio = &bmc->soc.gpio;
1479
1480     qemu_devices_reset(reason);
1481
1482     /* Board ID: 7 (Class-1, 4 slots) */
1483     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1484     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1485     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1486     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1487
1488     /* Slot presence pins, inverse polarity. (False means present) */
1489     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1490     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1491     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1492     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1493
1494     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1495     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1496     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1497     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1498     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1499 }
1500
1501 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1502 {
1503     MachineClass *mc = MACHINE_CLASS(oc);
1504     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1505
1506     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1507     mc->reset      = fby35_reset;
1508     amc->fmc_model = "mx66l1g45g";
1509     amc->num_cs    = 2;
1510     amc->macs_mask = ASPEED_MAC3_ON;
1511     amc->i2c_init  = fby35_i2c_init;
1512     /* FIXME: Replace this macro with something more general */
1513     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1514 }
1515
1516 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1517 /* Main SYSCLK frequency in Hz (200MHz) */
1518 #define SYSCLK_FRQ 200000000ULL
1519
1520 static void aspeed_minibmc_machine_init(MachineState *machine)
1521 {
1522     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1523     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1524     Clock *sysclk;
1525
1526     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1527     clock_set_hz(sysclk, SYSCLK_FRQ);
1528
1529     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1530     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1531
1532     object_property_set_link(OBJECT(&bmc->soc), "memory",
1533                              OBJECT(get_system_memory()), &error_abort);
1534     connect_serial_hds_to_uarts(bmc);
1535     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1536
1537     aspeed_board_init_flashes(&bmc->soc.fmc,
1538                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1539                               amc->num_cs,
1540                               0);
1541
1542     aspeed_board_init_flashes(&bmc->soc.spi[0],
1543                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1544                               amc->num_cs, amc->num_cs);
1545
1546     aspeed_board_init_flashes(&bmc->soc.spi[1],
1547                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1548                               amc->num_cs, (amc->num_cs * 2));
1549
1550     if (amc->i2c_init) {
1551         amc->i2c_init(bmc);
1552     }
1553
1554     armv7m_load_kernel(ARM_CPU(first_cpu),
1555                        machine->kernel_filename,
1556                        0,
1557                        AST1030_INTERNAL_FLASH_SIZE);
1558 }
1559
1560 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1561 {
1562     AspeedSoCState *soc = &bmc->soc;
1563
1564     /* U10 24C08 connects to SDA/SCL Group 1 by default */
1565     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1566     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1567
1568     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1569     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1570 }
1571
1572 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1573                                                           void *data)
1574 {
1575     MachineClass *mc = MACHINE_CLASS(oc);
1576     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1577
1578     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1579     amc->soc_name = "ast1030-a1";
1580     amc->hw_strap1 = 0;
1581     amc->hw_strap2 = 0;
1582     mc->init = aspeed_minibmc_machine_init;
1583     amc->i2c_init = ast1030_evb_i2c_init;
1584     mc->default_ram_size = 0;
1585     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1586     amc->fmc_model = "sst25vf032b";
1587     amc->spi_model = "sst25vf032b";
1588     amc->num_cs = 2;
1589     amc->macs_mask = 0;
1590 }
1591
1592 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1593                                                      void *data)
1594 {
1595     MachineClass *mc = MACHINE_CLASS(oc);
1596     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1597
1598     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1599     amc->soc_name  = "ast2600-a3";
1600     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1601     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1602     amc->fmc_model = "n25q512a";
1603     amc->spi_model = "n25q512a";
1604     amc->num_cs    = 2;
1605     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1606     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1607     mc->default_ram_size = 1 * GiB;
1608     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1609         aspeed_soc_num_cpus(amc->soc_name);
1610 };
1611
1612 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1613                                                     void *data)
1614 {
1615     MachineClass *mc = MACHINE_CLASS(oc);
1616     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1617
1618     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1619     amc->soc_name  = "ast2600-a3";
1620     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1621     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1622     amc->fmc_model = "n25q512a";
1623     amc->spi_model = "n25q512a";
1624     amc->num_cs    = 2;
1625     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1626     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1627     mc->default_ram_size = 1 * GiB;
1628     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1629         aspeed_soc_num_cpus(amc->soc_name);
1630 };
1631
1632 static const TypeInfo aspeed_machine_types[] = {
1633     {
1634         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1635         .parent        = TYPE_ASPEED_MACHINE,
1636         .class_init    = aspeed_machine_palmetto_class_init,
1637     }, {
1638         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1639         .parent        = TYPE_ASPEED_MACHINE,
1640         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1641     }, {
1642         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1643         .parent        = TYPE_ASPEED_MACHINE,
1644         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1645     }, {
1646         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1647         .parent        = TYPE_ASPEED_MACHINE,
1648         .class_init    = aspeed_machine_ast2500_evb_class_init,
1649     }, {
1650         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1651         .parent        = TYPE_ASPEED_MACHINE,
1652         .class_init    = aspeed_machine_romulus_class_init,
1653     }, {
1654         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1655         .parent        = TYPE_ASPEED_MACHINE,
1656         .class_init    = aspeed_machine_sonorapass_class_init,
1657     }, {
1658         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1659         .parent        = TYPE_ASPEED_MACHINE,
1660         .class_init    = aspeed_machine_witherspoon_class_init,
1661     }, {
1662         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1663         .parent        = TYPE_ASPEED_MACHINE,
1664         .class_init    = aspeed_machine_ast2600_evb_class_init,
1665     }, {
1666         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1667         .parent        = TYPE_ASPEED_MACHINE,
1668         .class_init    = aspeed_machine_yosemitev2_class_init,
1669     }, {
1670         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1671         .parent        = TYPE_ASPEED_MACHINE,
1672         .class_init    = aspeed_machine_tacoma_class_init,
1673     }, {
1674         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
1675         .parent        = TYPE_ASPEED_MACHINE,
1676         .class_init    = aspeed_machine_tiogapass_class_init,
1677     }, {
1678         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1679         .parent        = TYPE_ASPEED_MACHINE,
1680         .class_init    = aspeed_machine_g220a_class_init,
1681     }, {
1682         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1683         .parent        = TYPE_ASPEED_MACHINE,
1684         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1685     }, {
1686         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1687         .parent        = TYPE_ASPEED_MACHINE,
1688         .class_init    = aspeed_machine_qcom_firework_class_init,
1689     }, {
1690         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1691         .parent        = TYPE_ASPEED_MACHINE,
1692         .class_init    = aspeed_machine_fp5280g2_class_init,
1693     }, {
1694         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1695         .parent        = TYPE_ASPEED_MACHINE,
1696         .class_init    = aspeed_machine_quanta_q71l_class_init,
1697     }, {
1698         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1699         .parent        = TYPE_ASPEED_MACHINE,
1700         .class_init    = aspeed_machine_rainier_class_init,
1701     }, {
1702         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1703         .parent        = TYPE_ASPEED_MACHINE,
1704         .class_init    = aspeed_machine_fuji_class_init,
1705     }, {
1706         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1707         .parent        = TYPE_ASPEED_MACHINE,
1708         .class_init    = aspeed_machine_bletchley_class_init,
1709     }, {
1710         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1711         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1712         .class_init    = aspeed_machine_fby35_class_init,
1713     }, {
1714         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1715         .parent         = TYPE_ASPEED_MACHINE,
1716         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1717     }, {
1718         .name          = TYPE_ASPEED_MACHINE,
1719         .parent        = TYPE_MACHINE,
1720         .instance_size = sizeof(AspeedMachineState),
1721         .instance_init = aspeed_machine_instance_init,
1722         .class_size    = sizeof(AspeedMachineClass),
1723         .class_init    = aspeed_machine_class_init,
1724         .abstract      = true,
1725     }
1726 };
1727
1728 DEFINE_TYPES(aspeed_machine_types)