hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/arm/aspeed_eeprom.h"
  18 #include "hw/i2c/i2c_mux_pca954x.h"
  19 #include "hw/i2c/smbus_eeprom.h"
  20 #include "hw/misc/pca9552.h"
  21 #include "hw/nvram/eeprom_at24c.h"
  22 #include "hw/sensor/tmp105.h"
  23 #include "hw/misc/led.h"
  24 #include "hw/qdev-properties.h"
  25 #include "sysemu/block-backend.h"
  26 #include "sysemu/reset.h"
  27 #include "hw/loader.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/units.h"
  30 #include "hw/qdev-clock.h"
  31 #include "sysemu/sysemu.h"
  32
  33 static struct arm_boot_info aspeed_board_binfo = {
  34     .board_id = -1, /* device-tree-only board */
  35 };
  36
  37 struct AspeedMachineState {
  38     /* Private */
  39     MachineState parent_obj;
  40     /* Public */
  41
  42     AspeedSoCState soc;
  43     bool mmio_exec;
  44     char *fmc_model;
  45     char *spi_model;
  46 };
  47
  48 /* Palmetto hardware value: 0x120CE416 */
  49 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  50         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  51         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  52         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  53         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  54         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  55         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  56         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  57         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  58         SCU_HW_STRAP_SPI_WIDTH |                                        \
  59         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  60         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  61
  62 /* TODO: Find the actual hardware value */
  63 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  64         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  65         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  66         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  67         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  68         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  69         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  70         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  71         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  72         SCU_HW_STRAP_SPI_WIDTH |                                        \
  73         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  74         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  75
  76 /* TODO: Find the actual hardware value */
  77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  78         AST2500_HW_STRAP1_DEFAULTS |                                    \
  79         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  80         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  81         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  82         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  83         SCU_HW_STRAP_SPI_WIDTH |                                        \
  84         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  85
  86 /* AST2500 evb hardware value: 0xF100C2E6 */
  87 #define AST2500_EVB_HW_STRAP1 ((                                        \
  88         AST2500_HW_STRAP1_DEFAULTS |                                    \
  89         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  90         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  91         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  92         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  93         SCU_HW_STRAP_MAC1_RGMII |                                       \
  94         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  95         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  96
  97 /* Romulus hardware value: 0xF10AD206 */
  98 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  99         AST2500_HW_STRAP1_DEFAULTS |                                    \
 100         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 101         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 102         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 103         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 104         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 105         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 106
 107 /* Sonorapass hardware value: 0xF100D216 */
 108 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 109         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 110         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 111         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 112         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 113         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 114         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 115         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 116         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 117         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 118         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 119         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 120         SCU_AST2500_HW_STRAP_RESERVED1)
 121
 122 #define G220A_BMC_HW_STRAP1 (                                      \
 123         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 124         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 125         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 126         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 127         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 128         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 129         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 130         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 131         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 132         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 133         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 134         SCU_AST2500_HW_STRAP_RESERVED1)
 135
 136 /* FP5280G2 hardware value: 0XF100D286 */
 137 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 138         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 139         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 140         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 141         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 142         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 143         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 144         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 145         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 146         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 147         SCU_HW_STRAP_MAC1_RGMII |                                       \
 148         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 149         SCU_AST2500_HW_STRAP_RESERVED1)
 150
 151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 153
 154 /* Quanta-Q71l hardware value */
 155 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 156         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 157         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 158         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 159         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 160         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 161         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 162         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 163         SCU_HW_STRAP_SPI_WIDTH |                                        \
 164         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 165         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 166
 167 /* AST2600 evb hardware value */
 168 #define AST2600_EVB_HW_STRAP1 0x000000C0
 169 #define AST2600_EVB_HW_STRAP2 0x00000003
 170
 171 /* Tacoma hardware value */
 172 #define TACOMA_BMC_HW_STRAP1  0x00000000
 173 #define TACOMA_BMC_HW_STRAP2  0x00000040
 174
 175 /* Rainier hardware value: (QEMU prototype) */
 176 #define RAINIER_BMC_HW_STRAP1 0x00422016
 177 #define RAINIER_BMC_HW_STRAP2 0x80000848
 178
 179 /* Fuji hardware value */
 180 #define FUJI_BMC_HW_STRAP1    0x00000000
 181 #define FUJI_BMC_HW_STRAP2    0x00000000
 182
 183 /* Bletchley hardware value */
 184 /* TODO: Leave same as EVB for now. */
 185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 187
 188 /* Qualcomm DC-SCM hardware value */
 189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 191
 192 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 193 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 194 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 195 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 196 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 197 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 198 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 199
 200 static void aspeed_write_smpboot(ARMCPU *cpu,
 201                                  const struct arm_boot_info *info)
 202 {
 203     static const uint32_t poll_mailbox_ready[] = {
 204         /*
 205          * r2 = per-cpu go sign value
 206          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 207          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 208          */
 209         0xee100fb0,  /* mrc     p15, 0, r0, c0, c0, 5 */
 210         0xe21000ff,  /* ands    r0, r0, #255          */
 211         0xe59f201c,  /* ldr     r2, [pc, #28]         */
 212         0xe1822000,  /* orr     r2, r2, r0            */
 213
 214         0xe59f1018,  /* ldr     r1, [pc, #24]         */
 215         0xe59f0018,  /* ldr     r0, [pc, #24]         */
 216
 217         0xe320f002,  /* wfe                           */
 218         0xe5904000,  /* ldr     r4, [r0]              */
 219         0xe1520004,  /* cmp     r2, r4                */
 220         0x1afffffb,  /* bne     <wfe>                 */
 221         0xe591f000,  /* ldr     pc, [r1]              */
 222         AST_SMP_MBOX_GOSIGN,
 223         AST_SMP_MBOX_FIELD_ENTRY,
 224         AST_SMP_MBOX_FIELD_GOSIGN,
 225     };
 226
 227     rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
 228                        sizeof(poll_mailbox_ready),
 229                        info->smp_loader_start);
 230 }
 231
 232 static void aspeed_reset_secondary(ARMCPU *cpu,
 233                                    const struct arm_boot_info *info)
 234 {
 235     AddressSpace *as = arm_boot_address_space(cpu, info);
 236     CPUState *cs = CPU(cpu);
 237
 238     /* info->smp_bootreg_addr */
 239     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 240                                MEMTXATTRS_UNSPECIFIED, NULL);
 241     cpu_set_pc(cs, info->smp_loader_start);
 242 }
 243
 244 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 245                            Error **errp)
 246 {
 247     g_autofree void *storage = NULL;
 248     int64_t size;
 249
 250     /* The block backend size should have already been 'validated' by
 251      * the creation of the m25p80 object.
 252      */
 253     size = blk_getlength(blk);
 254     if (size <= 0) {
 255         error_setg(errp, "failed to get flash size");
 256         return;
 257     }
 258
 259     if (rom_size > size) {
 260         rom_size = size;
 261     }
 262
 263     storage = g_malloc0(rom_size);
 264     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 265         error_setg(errp, "failed to read the initial flash content");
 266         return;
 267     }
 268
 269     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 270 }
 271
 272 /*
 273  * Create a ROM and copy the flash contents at the expected address
 274  * (0x0). Boots faster than execute-in-place.
 275  */
 276 static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
 277                                     uint64_t rom_size)
 278 {
 279     MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 280
 281     memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
 282                            &error_abort);
 283     memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
 284                                         boot_rom, 1);
 285     write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
 286 }
 287
 288 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 289                                       unsigned int count, int unit0)
 290 {
 291     int i;
 292
 293     if (!flashtype) {
 294         return;
 295     }
 296
 297     for (i = 0; i < count; ++i) {
 298         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 299         qemu_irq cs_line;
 300         DeviceState *dev;
 301
 302         dev = qdev_new(flashtype);
 303         if (dinfo) {
 304             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 305         }
 306         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 307
 308         cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 309         qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
 310     }
 311 }
 312
 313 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 314 {
 315         DeviceState *card;
 316
 317         if (!dinfo) {
 318             return;
 319         }
 320         card = qdev_new(TYPE_SD_CARD);
 321         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 322                                 &error_fatal);
 323         qdev_realize_and_unref(card,
 324                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 325                                &error_fatal);
 326 }
 327
 328 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 329 {
 330     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 331     AspeedSoCState *s = &bmc->soc;
 332     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 333
 334     aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
 335     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 336         if (uart == amc->uart_default) {
 337             continue;
 338         }
 339         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 340     }
 341 }
 342
 343 static void aspeed_machine_init(MachineState *machine)
 344 {
 345     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 346     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 347     AspeedSoCClass *sc;
 348     int i;
 349     NICInfo *nd = &nd_table[0];
 350
 351     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 352
 353     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 354
 355     /*
 356      * This will error out if the RAM size is not supported by the
 357      * memory controller of the SoC.
 358      */
 359     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 360                              &error_fatal);
 361
 362     for (i = 0; i < sc->macs_num; i++) {
 363         if ((amc->macs_mask & (1 << i)) && nd->used) {
 364             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 365             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 366             nd++;
 367         }
 368     }
 369
 370     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 371                             &error_abort);
 372     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 373                             &error_abort);
 374     object_property_set_link(OBJECT(&bmc->soc), "memory",
 375                              OBJECT(get_system_memory()), &error_abort);
 376     object_property_set_link(OBJECT(&bmc->soc), "dram",
 377                              OBJECT(machine->ram), &error_abort);
 378     if (machine->kernel_filename) {
 379         /*
 380          * When booting with a -kernel command line there is no u-boot
 381          * that runs to unlock the SCU. In this case set the default to
 382          * be unlocked as the kernel expects
 383          */
 384         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 385                                 ASPEED_SCU_PROT_KEY, &error_abort);
 386     }
 387     connect_serial_hds_to_uarts(bmc);
 388     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 389
 390     aspeed_board_init_flashes(&bmc->soc.fmc,
 391                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 392                               amc->num_cs, 0);
 393     aspeed_board_init_flashes(&bmc->soc.spi[0],
 394                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 395                               1, amc->num_cs);
 396
 397     if (machine->kernel_filename && sc->num_cpus > 1) {
 398         /* With no u-boot we must set up a boot stub for the secondary CPU */
 399         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 400         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 401                                0x80, &error_abort);
 402         memory_region_add_subregion(get_system_memory(),
 403                                     AST_SMP_MAILBOX_BASE, smpboot);
 404
 405         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 406         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 407         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 408     }
 409
 410     aspeed_board_binfo.ram_size = machine->ram_size;
 411     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 412
 413     if (amc->i2c_init) {
 414         amc->i2c_init(bmc);
 415     }
 416
 417     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 418         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 419                            drive_get(IF_SD, 0, i));
 420     }
 421
 422     if (bmc->soc.emmc.num_slots) {
 423         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 424                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 425     }
 426
 427     if (!bmc->mmio_exec) {
 428         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 429
 430         if (mtd0) {
 431             uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 432             aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
 433                                     rom_size);
 434         }
 435     }
 436
 437     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 438 }
 439
 440 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 441 {
 442     AspeedSoCState *soc = &bmc->soc;
 443     DeviceState *dev;
 444     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 445
 446     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 447      * enough to provide basic RTC features. Alarms will be missing */
 448     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 449
 450     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 451                           eeprom_buf);
 452
 453     /* add a TMP423 temperature sensor */
 454     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 455                                          "tmp423", 0x4c));
 456     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 457     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 458     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 459     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 460 }
 461
 462 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 463 {
 464     AspeedSoCState *soc = &bmc->soc;
 465
 466     /*
 467      * The quanta-q71l platform expects tmp75s which are compatible with
 468      * tmp105s.
 469      */
 470     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 471     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 472     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 473
 474     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 475     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 476     /* TODO: Add Memory Riser i2c mux and eeproms. */
 477
 478     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 479     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 480
 481     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 482
 483     /* i2c-7 */
 484     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 485     /*        - i2c@0: pmbus@59 */
 486     /*        - i2c@1: pmbus@58 */
 487     /*        - i2c@2: pmbus@58 */
 488     /*        - i2c@3: pmbus@59 */
 489
 490     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 491     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 492 }
 493
 494 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 495 {
 496     AspeedSoCState *soc = &bmc->soc;
 497     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 498
 499     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 500                           eeprom_buf);
 501
 502     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 503     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 504                      TYPE_TMP105, 0x4d);
 505 }
 506
 507 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 508 {
 509     AspeedSoCState *soc = &bmc->soc;
 510     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 511
 512     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 513                           eeprom_buf);
 514
 515     /* LM75 is compatible with TMP105 driver */
 516     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 517                      TYPE_TMP105, 0x4d);
 518 }
 519
 520 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 521 {
 522     AspeedSoCState *soc = &bmc->soc;
 523
 524     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
 525     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
 526                           yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
 527     /* TMP421 */
 528     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
 529     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
 530     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
 531
 532 }
 533
 534 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 535 {
 536     AspeedSoCState *soc = &bmc->soc;
 537
 538     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 539      * good enough */
 540     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 541 }
 542
 543 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 544 {
 545     AspeedSoCState *soc = &bmc->soc;
 546
 547     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
 548     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
 549                           tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
 550 }
 551
 552 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 553 {
 554     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 555                             TYPE_PCA9552, addr);
 556 }
 557
 558 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 559 {
 560     AspeedSoCState *soc = &bmc->soc;
 561
 562     /* bus 2 : */
 563     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 564     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 565     /* bus 2 : pca9546 @ 0x73 */
 566
 567     /* bus 3 : pca9548 @ 0x70 */
 568
 569     /* bus 4 : */
 570     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 571     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 572                           eeprom4_54);
 573     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 574     create_pca9552(soc, 4, 0x76);
 575     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 576     create_pca9552(soc, 4, 0x77);
 577
 578     /* bus 6 : */
 579     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 580     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 581     /* bus 6 : pca9546 @ 0x73 */
 582
 583     /* bus 8 : */
 584     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 585     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 586                           eeprom8_56);
 587     create_pca9552(soc, 8, 0x60);
 588     create_pca9552(soc, 8, 0x61);
 589     /* bus 8 : adc128d818 @ 0x1d */
 590     /* bus 8 : adc128d818 @ 0x1f */
 591
 592     /*
 593      * bus 13 : pca9548 @ 0x71
 594      *      - channel 3:
 595      *          - tmm421 @ 0x4c
 596      *          - tmp421 @ 0x4e
 597      *          - tmp421 @ 0x4f
 598      */
 599
 600 }
 601
 602 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 603 {
 604     static const struct {
 605         unsigned gpio_id;
 606         LEDColor color;
 607         const char *description;
 608         bool gpio_polarity;
 609     } pca1_leds[] = {
 610         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 611         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 612         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 613     };
 614     AspeedSoCState *soc = &bmc->soc;
 615     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 616     DeviceState *dev;
 617     LEDState *led;
 618
 619     /* Bus 3: TODO bmp280@77 */
 620     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 621     qdev_prop_set_string(dev, "description", "pca1");
 622     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 623                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 624                                 &error_fatal);
 625
 626     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 627         led = led_create_simple(OBJECT(bmc),
 628                                 pca1_leds[i].gpio_polarity,
 629                                 pca1_leds[i].color,
 630                                 pca1_leds[i].description);
 631         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 632                               qdev_get_gpio_in(DEVICE(led), 0));
 633     }
 634     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 635     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 636     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 637     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 638
 639     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 640     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 641                      0x4a);
 642
 643     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 644      * good enough */
 645     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 646
 647     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 648                           eeprom_buf);
 649     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 650     qdev_prop_set_string(dev, "description", "pca0");
 651     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 652                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 653                                 &error_fatal);
 654     /* Bus 11: TODO ucd90160@64 */
 655 }
 656
 657 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 658 {
 659     AspeedSoCState *soc = &bmc->soc;
 660     DeviceState *dev;
 661
 662     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 663                                          "emc1413", 0x4c));
 664     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 665     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 666     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 667
 668     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 669                                          "emc1413", 0x4c));
 670     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 671     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 672     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 673
 674     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 675                                          "emc1413", 0x4c));
 676     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 677     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 678     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 679
 680     static uint8_t eeprom_buf[2 * 1024] = {
 681             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 682             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 683             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 684             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 685             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 686             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 687             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 688     };
 689     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 690                           eeprom_buf);
 691 }
 692
 693 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 694 {
 695     AspeedSoCState *soc = &bmc->soc;
 696     I2CSlave *i2c_mux;
 697
 698     /* The at24c256 */
 699     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 700
 701     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 702     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 703                      0x48);
 704     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 705                      0x49);
 706
 707     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 708                      "pca9546", 0x70);
 709     /* It expects a TMP112 but a TMP105 is compatible */
 710     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 711                      0x4a);
 712
 713     /* It expects a ds3232 but a ds1338 is good enough */
 714     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 715
 716     /* It expects a pca9555 but a pca9552 is compatible */
 717     create_pca9552(soc, 8, 0x30);
 718 }
 719
 720 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 721 {
 722     AspeedSoCState *soc = &bmc->soc;
 723     I2CSlave *i2c_mux;
 724
 725     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 726
 727     create_pca9552(soc, 3, 0x61);
 728
 729     /* The rainier expects a TMP275 but a TMP105 is compatible */
 730     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 731                      0x48);
 732     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 733                      0x49);
 734     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 735                      0x4a);
 736     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 737                                       "pca9546", 0x70);
 738     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 739     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 740     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 741     create_pca9552(soc, 4, 0x60);
 742
 743     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 744                      0x48);
 745     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 746                      0x49);
 747     create_pca9552(soc, 5, 0x60);
 748     create_pca9552(soc, 5, 0x61);
 749     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 750                                       "pca9546", 0x70);
 751     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 752     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 753
 754     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 755                      0x48);
 756     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 757                      0x4a);
 758     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 759                      0x4b);
 760     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 761                                       "pca9546", 0x70);
 762     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 763     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 764     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 765     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 766
 767     create_pca9552(soc, 7, 0x30);
 768     create_pca9552(soc, 7, 0x31);
 769     create_pca9552(soc, 7, 0x32);
 770     create_pca9552(soc, 7, 0x33);
 771     create_pca9552(soc, 7, 0x60);
 772     create_pca9552(soc, 7, 0x61);
 773     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 774     /* Bus 7: TODO si7021-a20@20 */
 775     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 776                      0x48);
 777     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 778     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 779     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 780
 781     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 782                      0x48);
 783     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 784                      0x4a);
 785     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
 786     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 787     create_pca9552(soc, 8, 0x60);
 788     create_pca9552(soc, 8, 0x61);
 789     /* Bus 8: ucd90320@11 */
 790     /* Bus 8: ucd90320@b */
 791     /* Bus 8: ucd90320@c */
 792
 793     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 794     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 795     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 796
 797     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 798     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 799     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 800
 801     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 802                      0x48);
 803     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 804                      0x49);
 805     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 806                                       "pca9546", 0x70);
 807     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 808     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 809     create_pca9552(soc, 11, 0x60);
 810
 811
 812     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 813     create_pca9552(soc, 13, 0x60);
 814
 815     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 816     create_pca9552(soc, 14, 0x60);
 817
 818     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 819     create_pca9552(soc, 15, 0x60);
 820 }
 821
 822 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 823                                  I2CBus **channels)
 824 {
 825     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 826     for (int i = 0; i < 8; i++) {
 827         channels[i] = pca954x_i2c_get_bus(mux, i);
 828     }
 829 }
 830
 831 #define TYPE_LM75 TYPE_TMP105
 832 #define TYPE_TMP75 TYPE_TMP105
 833 #define TYPE_TMP422 "tmp422"
 834
 835 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 836 {
 837     AspeedSoCState *soc = &bmc->soc;
 838     I2CBus *i2c[144] = {};
 839
 840     for (int i = 0; i < 16; i++) {
 841         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 842     }
 843     I2CBus *i2c180 = i2c[2];
 844     I2CBus *i2c480 = i2c[8];
 845     I2CBus *i2c600 = i2c[11];
 846
 847     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 848     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 849     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 850     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 851     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 852     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 853     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 854     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 855     for (int i = 0; i < 8; i++) {
 856         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 857     }
 858
 859     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 860     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 861
 862     /*
 863      * EEPROM 24c64 size is 64Kbits or 8 Kbytes
 864      *        24c02 size is 2Kbits or 256 bytes
 865      */
 866     at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
 867     at24c_eeprom_init(i2c[20], 0x50, 256);
 868     at24c_eeprom_init(i2c[22], 0x52, 256);
 869
 870     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 871     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 872     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 873     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 874
 875     at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
 876     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 877
 878     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 879     at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
 880     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 881     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 882
 883     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 884     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 885
 886     at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
 887     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 888     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 889     at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
 890     at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
 891     at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
 892     at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
 893
 894     at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
 895     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 896     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 897     at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
 898     at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
 899     at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
 900     at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
 901     at24c_eeprom_init(i2c[28], 0x50, 256);
 902
 903     for (int i = 0; i < 8; i++) {
 904         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 905         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 906         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 907         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 908     }
 909 }
 910
 911 #define TYPE_TMP421 "tmp421"
 912
 913 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 914 {
 915     AspeedSoCState *soc = &bmc->soc;
 916     I2CBus *i2c[13] = {};
 917     for (int i = 0; i < 13; i++) {
 918         if ((i == 8) || (i == 11)) {
 919             continue;
 920         }
 921         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 922     }
 923
 924     /* Bus 0 - 5 all have the same config. */
 925     for (int i = 0; i < 6; i++) {
 926         /* Missing model: ti,ina230 @ 0x45 */
 927         /* Missing model: mps,mp5023 @ 0x40 */
 928         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 929         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 930         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 931         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 932         /* Missing model: fsc,fusb302 @ 0x22 */
 933     }
 934
 935     /* Bus 6 */
 936     at24c_eeprom_init(i2c[6], 0x56, 65536);
 937     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 938     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 939
 940
 941     /* Bus 7 */
 942     at24c_eeprom_init(i2c[7], 0x54, 65536);
 943
 944     /* Bus 9 */
 945     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 946
 947     /* Bus 10 */
 948     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 949     /* Missing model: ti,hdc1080 @ 0x40 */
 950     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 951
 952     /* Bus 12 */
 953     /* Missing model: adi,adm1278 @ 0x11 */
 954     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 955     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 956     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 957 }
 958
 959 static void fby35_i2c_init(AspeedMachineState *bmc)
 960 {
 961     AspeedSoCState *soc = &bmc->soc;
 962     I2CBus *i2c[16];
 963
 964     for (int i = 0; i < 16; i++) {
 965         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 966     }
 967
 968     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 969     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 970     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 971     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 972     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 973     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 974
 975     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
 976     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
 977     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
 978                           fby35_nic_fruid_len);
 979     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
 980                           fby35_bb_fruid_len);
 981     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
 982                           fby35_bmc_fruid_len);
 983
 984     /*
 985      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
 986      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
 987      * each.
 988      */
 989 }
 990
 991 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 992 {
 993     AspeedSoCState *soc = &bmc->soc;
 994
 995     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 996 }
 997
 998 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 999 {
1000     AspeedSoCState *soc = &bmc->soc;
1001     I2CSlave *therm_mux, *cpuvr_mux;
1002
1003     /* Create the generic DC-SCM hardware */
1004     qcom_dc_scm_bmc_i2c_init(bmc);
1005
1006     /* Now create the Firework specific hardware */
1007
1008     /* I2C7 CPUVR MUX */
1009     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1010                                         "pca9546", 0x70);
1011     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1012     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1013     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1014     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1015
1016     /* I2C8 Thermal Diodes*/
1017     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1018                                         "pca9548", 0x70);
1019     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1020     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1021     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1022     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1023     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1024
1025     /* I2C9 Fan Controller (MAX31785) */
1026     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1027     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1028 }
1029
1030 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1031 {
1032     return ASPEED_MACHINE(obj)->mmio_exec;
1033 }
1034
1035 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1036 {
1037     ASPEED_MACHINE(obj)->mmio_exec = value;
1038 }
1039
1040 static void aspeed_machine_instance_init(Object *obj)
1041 {
1042     ASPEED_MACHINE(obj)->mmio_exec = false;
1043 }
1044
1045 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1046 {
1047     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1048     return g_strdup(bmc->fmc_model);
1049 }
1050
1051 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1052 {
1053     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1054
1055     g_free(bmc->fmc_model);
1056     bmc->fmc_model = g_strdup(value);
1057 }
1058
1059 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1060 {
1061     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1062     return g_strdup(bmc->spi_model);
1063 }
1064
1065 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1066 {
1067     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1068
1069     g_free(bmc->spi_model);
1070     bmc->spi_model = g_strdup(value);
1071 }
1072
1073 static void aspeed_machine_class_props_init(ObjectClass *oc)
1074 {
1075     object_class_property_add_bool(oc, "execute-in-place",
1076                                    aspeed_get_mmio_exec,
1077                                    aspeed_set_mmio_exec);
1078     object_class_property_set_description(oc, "execute-in-place",
1079                            "boot directly from CE0 flash device");
1080
1081     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1082                                    aspeed_set_fmc_model);
1083     object_class_property_set_description(oc, "fmc-model",
1084                                           "Change the FMC Flash model");
1085     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1086                                    aspeed_set_spi_model);
1087     object_class_property_set_description(oc, "spi-model",
1088                                           "Change the SPI Flash model");
1089 }
1090
1091 static int aspeed_soc_num_cpus(const char *soc_name)
1092 {
1093    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1094    return sc->num_cpus;
1095 }
1096
1097 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1098 {
1099     MachineClass *mc = MACHINE_CLASS(oc);
1100     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1101
1102     mc->init = aspeed_machine_init;
1103     mc->no_floppy = 1;
1104     mc->no_cdrom = 1;
1105     mc->no_parallel = 1;
1106     mc->default_ram_id = "ram";
1107     amc->macs_mask = ASPEED_MAC0_ON;
1108     amc->uart_default = ASPEED_DEV_UART5;
1109
1110     aspeed_machine_class_props_init(oc);
1111 }
1112
1113 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1114 {
1115     MachineClass *mc = MACHINE_CLASS(oc);
1116     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1117
1118     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1119     amc->soc_name  = "ast2400-a1";
1120     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1121     amc->fmc_model = "n25q256a";
1122     amc->spi_model = "mx25l25635f";
1123     amc->num_cs    = 1;
1124     amc->i2c_init  = palmetto_bmc_i2c_init;
1125     mc->default_ram_size       = 256 * MiB;
1126     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1127         aspeed_soc_num_cpus(amc->soc_name);
1128 };
1129
1130 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1131 {
1132     MachineClass *mc = MACHINE_CLASS(oc);
1133     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1134
1135     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1136     amc->soc_name  = "ast2400-a1";
1137     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1138     amc->fmc_model = "n25q256a";
1139     amc->spi_model = "mx25l25635e";
1140     amc->num_cs    = 1;
1141     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1142     mc->default_ram_size       = 128 * MiB;
1143     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1144         aspeed_soc_num_cpus(amc->soc_name);
1145 }
1146
1147 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1148                                                         void *data)
1149 {
1150     MachineClass *mc = MACHINE_CLASS(oc);
1151     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1152
1153     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1154     amc->soc_name  = "ast2400-a1";
1155     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1156     amc->fmc_model = "mx25l25635e";
1157     amc->spi_model = "mx25l25635e";
1158     amc->num_cs    = 1;
1159     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1160     amc->i2c_init  = palmetto_bmc_i2c_init;
1161     mc->default_ram_size = 256 * MiB;
1162 }
1163
1164 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1165                                                             void *data)
1166 {
1167     MachineClass *mc = MACHINE_CLASS(oc);
1168     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1169
1170     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1171     amc->soc_name  = "ast2500-a1";
1172     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1173     amc->fmc_model = "mx25l25635e";
1174     amc->spi_model = "mx25l25635e";
1175     amc->num_cs    = 1;
1176     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1177     amc->i2c_init  = palmetto_bmc_i2c_init;
1178     mc->default_ram_size = 512 * MiB;
1179     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1180         aspeed_soc_num_cpus(amc->soc_name);
1181 }
1182
1183 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1184 {
1185     MachineClass *mc = MACHINE_CLASS(oc);
1186     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1187
1188     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1189     amc->soc_name  = "ast2500-a1";
1190     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1191     amc->fmc_model = "mx25l25635e";
1192     amc->spi_model = "mx25l25635f";
1193     amc->num_cs    = 1;
1194     amc->i2c_init  = ast2500_evb_i2c_init;
1195     mc->default_ram_size       = 512 * MiB;
1196     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1197         aspeed_soc_num_cpus(amc->soc_name);
1198 };
1199
1200 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1201 {
1202     MachineClass *mc = MACHINE_CLASS(oc);
1203     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1204
1205     mc->desc       = "Facebook YosemiteV2 BMC (ARM1176)";
1206     amc->soc_name  = "ast2500-a1";
1207     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1208     amc->hw_strap2 = 0;
1209     amc->fmc_model = "n25q256a";
1210     amc->spi_model = "mx25l25635e";
1211     amc->num_cs    = 2;
1212     amc->i2c_init  = yosemitev2_bmc_i2c_init;
1213     mc->default_ram_size       = 512 * MiB;
1214     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1215         aspeed_soc_num_cpus(amc->soc_name);
1216 };
1217
1218 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1219 {
1220     MachineClass *mc = MACHINE_CLASS(oc);
1221     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1222
1223     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1224     amc->soc_name  = "ast2500-a1";
1225     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1226     amc->fmc_model = "n25q256a";
1227     amc->spi_model = "mx66l1g45g";
1228     amc->num_cs    = 2;
1229     amc->i2c_init  = romulus_bmc_i2c_init;
1230     mc->default_ram_size       = 512 * MiB;
1231     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1232         aspeed_soc_num_cpus(amc->soc_name);
1233 };
1234
1235 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1236 {
1237     MachineClass *mc = MACHINE_CLASS(oc);
1238     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1239
1240     mc->desc       = "Facebook Tiogapass BMC (ARM1176)";
1241     amc->soc_name  = "ast2500-a1";
1242     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1243     amc->hw_strap2 = 0;
1244     amc->fmc_model = "n25q256a";
1245     amc->spi_model = "mx25l25635e";
1246     amc->num_cs    = 2;
1247     amc->i2c_init  = tiogapass_bmc_i2c_init;
1248     mc->default_ram_size       = 1 * GiB;
1249     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1250         aspeed_soc_num_cpus(amc->soc_name);
1251         aspeed_soc_num_cpus(amc->soc_name);
1252 };
1253
1254 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1255 {
1256     MachineClass *mc = MACHINE_CLASS(oc);
1257     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1258
1259     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1260     amc->soc_name  = "ast2500-a1";
1261     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1262     amc->fmc_model = "mx66l1g45g";
1263     amc->spi_model = "mx66l1g45g";
1264     amc->num_cs    = 2;
1265     amc->i2c_init  = sonorapass_bmc_i2c_init;
1266     mc->default_ram_size       = 512 * MiB;
1267     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1268         aspeed_soc_num_cpus(amc->soc_name);
1269 };
1270
1271 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1272 {
1273     MachineClass *mc = MACHINE_CLASS(oc);
1274     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1275
1276     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1277     amc->soc_name  = "ast2500-a1";
1278     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1279     amc->fmc_model = "mx25l25635f";
1280     amc->spi_model = "mx66l1g45g";
1281     amc->num_cs    = 2;
1282     amc->i2c_init  = witherspoon_bmc_i2c_init;
1283     mc->default_ram_size = 512 * MiB;
1284     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1285         aspeed_soc_num_cpus(amc->soc_name);
1286 };
1287
1288 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1289 {
1290     MachineClass *mc = MACHINE_CLASS(oc);
1291     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1292
1293     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1294     amc->soc_name  = "ast2600-a3";
1295     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1296     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1297     amc->fmc_model = "mx66u51235f";
1298     amc->spi_model = "mx66u51235f";
1299     amc->num_cs    = 1;
1300     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1301                      ASPEED_MAC3_ON;
1302     amc->i2c_init  = ast2600_evb_i2c_init;
1303     mc->default_ram_size = 1 * GiB;
1304     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1305         aspeed_soc_num_cpus(amc->soc_name);
1306 };
1307
1308 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1309 {
1310     MachineClass *mc = MACHINE_CLASS(oc);
1311     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1312
1313     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1314     amc->soc_name  = "ast2600-a3";
1315     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1316     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1317     amc->fmc_model = "mx66l1g45g";
1318     amc->spi_model = "mx66l1g45g";
1319     amc->num_cs    = 2;
1320     amc->macs_mask  = ASPEED_MAC2_ON;
1321     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1322     mc->default_ram_size = 1 * GiB;
1323     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1324         aspeed_soc_num_cpus(amc->soc_name);
1325 };
1326
1327 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1328 {
1329     MachineClass *mc = MACHINE_CLASS(oc);
1330     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1331
1332     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1333     amc->soc_name  = "ast2500-a1";
1334     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1335     amc->fmc_model = "n25q512a";
1336     amc->spi_model = "mx25l25635e";
1337     amc->num_cs    = 2;
1338     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1339     amc->i2c_init  = g220a_bmc_i2c_init;
1340     mc->default_ram_size = 1024 * MiB;
1341     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1342         aspeed_soc_num_cpus(amc->soc_name);
1343 };
1344
1345 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1346 {
1347     MachineClass *mc = MACHINE_CLASS(oc);
1348     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1349
1350     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1351     amc->soc_name  = "ast2500-a1";
1352     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1353     amc->fmc_model = "n25q512a";
1354     amc->spi_model = "mx25l25635e";
1355     amc->num_cs    = 2;
1356     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1357     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1358     mc->default_ram_size = 512 * MiB;
1359     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1360         aspeed_soc_num_cpus(amc->soc_name);
1361 };
1362
1363 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1364 {
1365     MachineClass *mc = MACHINE_CLASS(oc);
1366     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1367
1368     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1369     amc->soc_name  = "ast2600-a3";
1370     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1371     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1372     amc->fmc_model = "mx66l1g45g";
1373     amc->spi_model = "mx66l1g45g";
1374     amc->num_cs    = 2;
1375     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1376     amc->i2c_init  = rainier_bmc_i2c_init;
1377     mc->default_ram_size = 1 * GiB;
1378     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1379         aspeed_soc_num_cpus(amc->soc_name);
1380 };
1381
1382 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1383 #if HOST_LONG_BITS == 32
1384 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1385 #else
1386 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1387 #endif
1388
1389 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1390 {
1391     MachineClass *mc = MACHINE_CLASS(oc);
1392     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1393
1394     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1395     amc->soc_name = "ast2600-a3";
1396     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1397     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1398     amc->fmc_model = "mx66l1g45g";
1399     amc->spi_model = "mx66l1g45g";
1400     amc->num_cs = 2;
1401     amc->macs_mask = ASPEED_MAC3_ON;
1402     amc->i2c_init = fuji_bmc_i2c_init;
1403     amc->uart_default = ASPEED_DEV_UART1;
1404     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1405     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1406         aspeed_soc_num_cpus(amc->soc_name);
1407 };
1408
1409 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1410 #if HOST_LONG_BITS == 32
1411 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1412 #else
1413 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1414 #endif
1415
1416 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1417 {
1418     MachineClass *mc = MACHINE_CLASS(oc);
1419     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1420
1421     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1422     amc->soc_name  = "ast2600-a3";
1423     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1424     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1425     amc->fmc_model = "w25q01jvq";
1426     amc->spi_model = NULL;
1427     amc->num_cs    = 2;
1428     amc->macs_mask = ASPEED_MAC2_ON;
1429     amc->i2c_init  = bletchley_bmc_i2c_init;
1430     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1431     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1432         aspeed_soc_num_cpus(amc->soc_name);
1433 }
1434
1435 static void fby35_reset(MachineState *state, ShutdownCause reason)
1436 {
1437     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1438     AspeedGPIOState *gpio = &bmc->soc.gpio;
1439
1440     qemu_devices_reset(reason);
1441
1442     /* Board ID: 7 (Class-1, 4 slots) */
1443     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1444     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1445     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1446     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1447
1448     /* Slot presence pins, inverse polarity. (False means present) */
1449     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1450     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1451     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1452     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1453
1454     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1455     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1456     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1457     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1458     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1459 }
1460
1461 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1462 {
1463     MachineClass *mc = MACHINE_CLASS(oc);
1464     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1465
1466     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1467     mc->reset      = fby35_reset;
1468     amc->fmc_model = "mx66l1g45g";
1469     amc->num_cs    = 2;
1470     amc->macs_mask = ASPEED_MAC3_ON;
1471     amc->i2c_init  = fby35_i2c_init;
1472     /* FIXME: Replace this macro with something more general */
1473     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1474 }
1475
1476 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1477 /* Main SYSCLK frequency in Hz (200MHz) */
1478 #define SYSCLK_FRQ 200000000ULL
1479
1480 static void aspeed_minibmc_machine_init(MachineState *machine)
1481 {
1482     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1483     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1484     Clock *sysclk;
1485
1486     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1487     clock_set_hz(sysclk, SYSCLK_FRQ);
1488
1489     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1490     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1491
1492     object_property_set_link(OBJECT(&bmc->soc), "memory",
1493                              OBJECT(get_system_memory()), &error_abort);
1494     connect_serial_hds_to_uarts(bmc);
1495     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1496
1497     aspeed_board_init_flashes(&bmc->soc.fmc,
1498                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1499                               amc->num_cs,
1500                               0);
1501
1502     aspeed_board_init_flashes(&bmc->soc.spi[0],
1503                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1504                               amc->num_cs, amc->num_cs);
1505
1506     aspeed_board_init_flashes(&bmc->soc.spi[1],
1507                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1508                               amc->num_cs, (amc->num_cs * 2));
1509
1510     if (amc->i2c_init) {
1511         amc->i2c_init(bmc);
1512     }
1513
1514     armv7m_load_kernel(ARM_CPU(first_cpu),
1515                        machine->kernel_filename,
1516                        0,
1517                        AST1030_INTERNAL_FLASH_SIZE);
1518 }
1519
1520 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1521 {
1522     AspeedSoCState *soc = &bmc->soc;
1523
1524     /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1525     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1526     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1527
1528     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1529     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1530 }
1531
1532 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1533                                                           void *data)
1534 {
1535     MachineClass *mc = MACHINE_CLASS(oc);
1536     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1537
1538     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1539     amc->soc_name = "ast1030-a1";
1540     amc->hw_strap1 = 0;
1541     amc->hw_strap2 = 0;
1542     mc->init = aspeed_minibmc_machine_init;
1543     amc->i2c_init = ast1030_evb_i2c_init;
1544     mc->default_ram_size = 0;
1545     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1546     amc->fmc_model = "sst25vf032b";
1547     amc->spi_model = "sst25vf032b";
1548     amc->num_cs = 2;
1549     amc->macs_mask = 0;
1550 }
1551
1552 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1553                                                      void *data)
1554 {
1555     MachineClass *mc = MACHINE_CLASS(oc);
1556     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1557
1558     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1559     amc->soc_name  = "ast2600-a3";
1560     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1561     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1562     amc->fmc_model = "n25q512a";
1563     amc->spi_model = "n25q512a";
1564     amc->num_cs    = 2;
1565     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1566     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1567     mc->default_ram_size = 1 * GiB;
1568     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1569         aspeed_soc_num_cpus(amc->soc_name);
1570 };
1571
1572 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1573                                                     void *data)
1574 {
1575     MachineClass *mc = MACHINE_CLASS(oc);
1576     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1577
1578     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1579     amc->soc_name  = "ast2600-a3";
1580     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1581     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1582     amc->fmc_model = "n25q512a";
1583     amc->spi_model = "n25q512a";
1584     amc->num_cs    = 2;
1585     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1586     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1587     mc->default_ram_size = 1 * GiB;
1588     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1589         aspeed_soc_num_cpus(amc->soc_name);
1590 };
1591
1592 static const TypeInfo aspeed_machine_types[] = {
1593     {
1594         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1595         .parent        = TYPE_ASPEED_MACHINE,
1596         .class_init    = aspeed_machine_palmetto_class_init,
1597     }, {
1598         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1599         .parent        = TYPE_ASPEED_MACHINE,
1600         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1601     }, {
1602         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1603         .parent        = TYPE_ASPEED_MACHINE,
1604         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1605     }, {
1606         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1607         .parent        = TYPE_ASPEED_MACHINE,
1608         .class_init    = aspeed_machine_ast2500_evb_class_init,
1609     }, {
1610         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1611         .parent        = TYPE_ASPEED_MACHINE,
1612         .class_init    = aspeed_machine_romulus_class_init,
1613     }, {
1614         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1615         .parent        = TYPE_ASPEED_MACHINE,
1616         .class_init    = aspeed_machine_sonorapass_class_init,
1617     }, {
1618         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1619         .parent        = TYPE_ASPEED_MACHINE,
1620         .class_init    = aspeed_machine_witherspoon_class_init,
1621     }, {
1622         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1623         .parent        = TYPE_ASPEED_MACHINE,
1624         .class_init    = aspeed_machine_ast2600_evb_class_init,
1625     }, {
1626         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1627         .parent        = TYPE_ASPEED_MACHINE,
1628         .class_init    = aspeed_machine_yosemitev2_class_init,
1629     }, {
1630         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1631         .parent        = TYPE_ASPEED_MACHINE,
1632         .class_init    = aspeed_machine_tacoma_class_init,
1633     }, {
1634         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
1635         .parent        = TYPE_ASPEED_MACHINE,
1636         .class_init    = aspeed_machine_tiogapass_class_init,
1637     }, {
1638         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1639         .parent        = TYPE_ASPEED_MACHINE,
1640         .class_init    = aspeed_machine_g220a_class_init,
1641     }, {
1642         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1643         .parent        = TYPE_ASPEED_MACHINE,
1644         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1645     }, {
1646         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1647         .parent        = TYPE_ASPEED_MACHINE,
1648         .class_init    = aspeed_machine_qcom_firework_class_init,
1649     }, {
1650         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1651         .parent        = TYPE_ASPEED_MACHINE,
1652         .class_init    = aspeed_machine_fp5280g2_class_init,
1653     }, {
1654         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1655         .parent        = TYPE_ASPEED_MACHINE,
1656         .class_init    = aspeed_machine_quanta_q71l_class_init,
1657     }, {
1658         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1659         .parent        = TYPE_ASPEED_MACHINE,
1660         .class_init    = aspeed_machine_rainier_class_init,
1661     }, {
1662         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1663         .parent        = TYPE_ASPEED_MACHINE,
1664         .class_init    = aspeed_machine_fuji_class_init,
1665     }, {
1666         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1667         .parent        = TYPE_ASPEED_MACHINE,
1668         .class_init    = aspeed_machine_bletchley_class_init,
1669     }, {
1670         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1671         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1672         .class_init    = aspeed_machine_fby35_class_init,
1673     }, {
1674         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1675         .parent         = TYPE_ASPEED_MACHINE,
1676         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1677     }, {
1678         .name          = TYPE_ASPEED_MACHINE,
1679         .parent        = TYPE_MACHINE,
1680         .instance_size = sizeof(AspeedMachineState),
1681         .instance_init = aspeed_machine_instance_init,
1682         .class_size    = sizeof(AspeedMachineClass),
1683         .class_init    = aspeed_machine_class_init,
1684         .abstract      = true,
1685     }
1686 };
1687
1688 DEFINE_TYPES(aspeed_machine_types)