hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/i2c/i2c_mux_pca954x.h"
  18 #include "hw/i2c/smbus_eeprom.h"
  19 #include "hw/misc/pca9552.h"
  20 #include "hw/sensor/tmp105.h"
  21 #include "hw/misc/led.h"
  22 #include "hw/qdev-properties.h"
  23 #include "sysemu/block-backend.h"
  24 #include "sysemu/reset.h"
  25 #include "hw/loader.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/units.h"
  28 #include "hw/qdev-clock.h"
  29 #include "sysemu/sysemu.h"
  30
  31 static struct arm_boot_info aspeed_board_binfo = {
  32     .board_id = -1, /* device-tree-only board */
  33 };
  34
  35 struct AspeedMachineState {
  36     /* Private */
  37     MachineState parent_obj;
  38     /* Public */
  39
  40     AspeedSoCState soc;
  41     bool mmio_exec;
  42     char *fmc_model;
  43     char *spi_model;
  44 };
  45
  46 /* Palmetto hardware value: 0x120CE416 */
  47 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  48         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  49         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  50         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  51         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  52         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  53         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  54         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  55         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  56         SCU_HW_STRAP_SPI_WIDTH |                                        \
  57         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  58         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  59
  60 /* TODO: Find the actual hardware value */
  61 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  62         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  63         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  64         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  65         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  66         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  67         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  68         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  69         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  70         SCU_HW_STRAP_SPI_WIDTH |                                        \
  71         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  72         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  73
  74 /* TODO: Find the actual hardware value */
  75 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  76         AST2500_HW_STRAP1_DEFAULTS |                                    \
  77         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  78         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  79         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  80         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  81         SCU_HW_STRAP_SPI_WIDTH |                                        \
  82         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  83
  84 /* AST2500 evb hardware value: 0xF100C2E6 */
  85 #define AST2500_EVB_HW_STRAP1 ((                                        \
  86         AST2500_HW_STRAP1_DEFAULTS |                                    \
  87         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  88         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  89         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  90         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  91         SCU_HW_STRAP_MAC1_RGMII |                                       \
  92         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  93         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  94
  95 /* Romulus hardware value: 0xF10AD206 */
  96 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  97         AST2500_HW_STRAP1_DEFAULTS |                                    \
  98         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  99         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 100         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 101         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 102         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 103         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 104
 105 /* Sonorapass hardware value: 0xF100D216 */
 106 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 107         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 108         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 109         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 110         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 111         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 112         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 113         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 114         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 115         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 116         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 117         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 118         SCU_AST2500_HW_STRAP_RESERVED1)
 119
 120 #define G220A_BMC_HW_STRAP1 (                                      \
 121         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 122         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 123         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 124         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 125         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 126         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 127         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 128         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 129         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 130         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 131         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 132         SCU_AST2500_HW_STRAP_RESERVED1)
 133
 134 /* FP5280G2 hardware value: 0XF100D286 */
 135 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 136         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 137         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 138         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 139         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 140         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 141         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 142         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 143         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 144         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 145         SCU_HW_STRAP_MAC1_RGMII |                                       \
 146         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 147         SCU_AST2500_HW_STRAP_RESERVED1)
 148
 149 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 150 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 151
 152 /* Quanta-Q71l hardware value */
 153 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 154         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 155         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 156         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 157         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 158         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 159         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 160         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 161         SCU_HW_STRAP_SPI_WIDTH |                                        \
 162         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 163         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 164
 165 /* AST2600 evb hardware value */
 166 #define AST2600_EVB_HW_STRAP1 0x000000C0
 167 #define AST2600_EVB_HW_STRAP2 0x00000003
 168
 169 /* Tacoma hardware value */
 170 #define TACOMA_BMC_HW_STRAP1  0x00000000
 171 #define TACOMA_BMC_HW_STRAP2  0x00000040
 172
 173 /* Rainier hardware value: (QEMU prototype) */
 174 #define RAINIER_BMC_HW_STRAP1 0x00422016
 175 #define RAINIER_BMC_HW_STRAP2 0x80000848
 176
 177 /* Fuji hardware value */
 178 #define FUJI_BMC_HW_STRAP1    0x00000000
 179 #define FUJI_BMC_HW_STRAP2    0x00000000
 180
 181 /* Bletchley hardware value */
 182 /* TODO: Leave same as EVB for now. */
 183 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 184 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 185
 186 /* Qualcomm DC-SCM hardware value */
 187 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 188 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 189
 190 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 191 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 192 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 193 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 194 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 195 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 196 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 197
 198 static void aspeed_write_smpboot(ARMCPU *cpu,
 199                                  const struct arm_boot_info *info)
 200 {
 201     static const uint32_t poll_mailbox_ready[] = {
 202         /*
 203          * r2 = per-cpu go sign value
 204          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 205          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 206          */
 207         0xee100fb0,  /* mrc     p15, 0, r0, c0, c0, 5 */
 208         0xe21000ff,  /* ands    r0, r0, #255          */
 209         0xe59f201c,  /* ldr     r2, [pc, #28]         */
 210         0xe1822000,  /* orr     r2, r2, r0            */
 211
 212         0xe59f1018,  /* ldr     r1, [pc, #24]         */
 213         0xe59f0018,  /* ldr     r0, [pc, #24]         */
 214
 215         0xe320f002,  /* wfe                           */
 216         0xe5904000,  /* ldr     r4, [r0]              */
 217         0xe1520004,  /* cmp     r2, r4                */
 218         0x1afffffb,  /* bne     <wfe>                 */
 219         0xe591f000,  /* ldr     pc, [r1]              */
 220         AST_SMP_MBOX_GOSIGN,
 221         AST_SMP_MBOX_FIELD_ENTRY,
 222         AST_SMP_MBOX_FIELD_GOSIGN,
 223     };
 224
 225     rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
 226                        sizeof(poll_mailbox_ready),
 227                        info->smp_loader_start);
 228 }
 229
 230 static void aspeed_reset_secondary(ARMCPU *cpu,
 231                                    const struct arm_boot_info *info)
 232 {
 233     AddressSpace *as = arm_boot_address_space(cpu, info);
 234     CPUState *cs = CPU(cpu);
 235
 236     /* info->smp_bootreg_addr */
 237     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 238                                MEMTXATTRS_UNSPECIFIED, NULL);
 239     cpu_set_pc(cs, info->smp_loader_start);
 240 }
 241
 242 #define FIRMWARE_ADDR 0x0
 243
 244 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
 245                            Error **errp)
 246 {
 247     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 248     g_autofree void *storage = NULL;
 249     int64_t size;
 250
 251     /* The block backend size should have already been 'validated' by
 252      * the creation of the m25p80 object.
 253      */
 254     size = blk_getlength(blk);
 255     if (size <= 0) {
 256         error_setg(errp, "failed to get flash size");
 257         return;
 258     }
 259
 260     if (rom_size > size) {
 261         rom_size = size;
 262     }
 263
 264     storage = g_malloc0(rom_size);
 265     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 266         error_setg(errp, "failed to read the initial flash content");
 267         return;
 268     }
 269
 270     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 271 }
 272
 273 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 274                                       unsigned int count, int unit0)
 275 {
 276     int i;
 277
 278     if (!flashtype) {
 279         return;
 280     }
 281
 282     for (i = 0; i < count; ++i) {
 283         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 284         qemu_irq cs_line;
 285         DeviceState *dev;
 286
 287         dev = qdev_new(flashtype);
 288         if (dinfo) {
 289             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 290         }
 291         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 292
 293         cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 294         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
 295     }
 296 }
 297
 298 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 299 {
 300         DeviceState *card;
 301
 302         if (!dinfo) {
 303             return;
 304         }
 305         card = qdev_new(TYPE_SD_CARD);
 306         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 307                                 &error_fatal);
 308         qdev_realize_and_unref(card,
 309                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 310                                &error_fatal);
 311 }
 312
 313 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 314 {
 315     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 316     AspeedSoCState *s = &bmc->soc;
 317     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 318
 319     aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
 320     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 321         if (uart == amc->uart_default) {
 322             continue;
 323         }
 324         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 325     }
 326 }
 327
 328 static void aspeed_machine_init(MachineState *machine)
 329 {
 330     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 331     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 332     AspeedSoCClass *sc;
 333     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
 334     int i;
 335     NICInfo *nd = &nd_table[0];
 336
 337     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 338
 339     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 340
 341     /*
 342      * This will error out if the RAM size is not supported by the
 343      * memory controller of the SoC.
 344      */
 345     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 346                              &error_fatal);
 347
 348     for (i = 0; i < sc->macs_num; i++) {
 349         if ((amc->macs_mask & (1 << i)) && nd->used) {
 350             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 351             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 352             nd++;
 353         }
 354     }
 355
 356     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 357                             &error_abort);
 358     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 359                             &error_abort);
 360     object_property_set_link(OBJECT(&bmc->soc), "memory",
 361                              OBJECT(get_system_memory()), &error_abort);
 362     object_property_set_link(OBJECT(&bmc->soc), "dram",
 363                              OBJECT(machine->ram), &error_abort);
 364     if (machine->kernel_filename) {
 365         /*
 366          * When booting with a -kernel command line there is no u-boot
 367          * that runs to unlock the SCU. In this case set the default to
 368          * be unlocked as the kernel expects
 369          */
 370         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 371                                 ASPEED_SCU_PROT_KEY, &error_abort);
 372     }
 373     connect_serial_hds_to_uarts(bmc);
 374     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 375
 376     aspeed_board_init_flashes(&bmc->soc.fmc,
 377                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 378                               amc->num_cs, 0);
 379     aspeed_board_init_flashes(&bmc->soc.spi[0],
 380                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 381                               1, amc->num_cs);
 382
 383     /* Install first FMC flash content as a boot rom. */
 384     if (drive0) {
 385         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
 386         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 387         uint64_t size = memory_region_size(&fl->mmio);
 388
 389         /*
 390          * create a ROM region using the default mapping window size of
 391          * the flash module. The window size is 64MB for the AST2400
 392          * SoC and 128MB for the AST2500 SoC, which is twice as big as
 393          * needed by the flash modules of the Aspeed machines.
 394          */
 395         if (ASPEED_MACHINE(machine)->mmio_exec) {
 396             memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
 397                                      &fl->mmio, 0, size);
 398             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 399                                         boot_rom);
 400         } else {
 401             memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
 402                                    size, &error_abort);
 403             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 404                                         boot_rom);
 405             write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
 406         }
 407     }
 408
 409     if (machine->kernel_filename && sc->num_cpus > 1) {
 410         /* With no u-boot we must set up a boot stub for the secondary CPU */
 411         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 412         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 413                                0x80, &error_abort);
 414         memory_region_add_subregion(get_system_memory(),
 415                                     AST_SMP_MAILBOX_BASE, smpboot);
 416
 417         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 418         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 419         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 420     }
 421
 422     aspeed_board_binfo.ram_size = machine->ram_size;
 423     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 424
 425     if (amc->i2c_init) {
 426         amc->i2c_init(bmc);
 427     }
 428
 429     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 430         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 431                            drive_get(IF_SD, 0, i));
 432     }
 433
 434     if (bmc->soc.emmc.num_slots) {
 435         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 436                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 437     }
 438
 439     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 440 }
 441
 442 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
 443 {
 444     I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
 445     DeviceState *dev = DEVICE(i2c_dev);
 446
 447     qdev_prop_set_uint32(dev, "rom-size", rsize);
 448     i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
 449 }
 450
 451 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 452 {
 453     AspeedSoCState *soc = &bmc->soc;
 454     DeviceState *dev;
 455     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 456
 457     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 458      * enough to provide basic RTC features. Alarms will be missing */
 459     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 460
 461     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 462                           eeprom_buf);
 463
 464     /* add a TMP423 temperature sensor */
 465     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 466                                          "tmp423", 0x4c));
 467     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 468     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 469     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 470     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 471 }
 472
 473 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 474 {
 475     AspeedSoCState *soc = &bmc->soc;
 476
 477     /*
 478      * The quanta-q71l platform expects tmp75s which are compatible with
 479      * tmp105s.
 480      */
 481     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 482     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 483     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 484
 485     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 486     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 487     /* TODO: Add Memory Riser i2c mux and eeproms. */
 488
 489     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 490     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 491
 492     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 493
 494     /* i2c-7 */
 495     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 496     /*        - i2c@0: pmbus@59 */
 497     /*        - i2c@1: pmbus@58 */
 498     /*        - i2c@2: pmbus@58 */
 499     /*        - i2c@3: pmbus@59 */
 500
 501     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 502     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 503 }
 504
 505 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 506 {
 507     AspeedSoCState *soc = &bmc->soc;
 508     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 509
 510     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 511                           eeprom_buf);
 512
 513     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 514     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 515                      TYPE_TMP105, 0x4d);
 516 }
 517
 518 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 519 {
 520     AspeedSoCState *soc = &bmc->soc;
 521     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 522
 523     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 524                           eeprom_buf);
 525
 526     /* LM75 is compatible with TMP105 driver */
 527     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 528                      TYPE_TMP105, 0x4d);
 529 }
 530
 531 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 532 {
 533     AspeedSoCState *soc = &bmc->soc;
 534
 535     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 536      * good enough */
 537     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 538 }
 539
 540 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 541 {
 542     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 543                             TYPE_PCA9552, addr);
 544 }
 545
 546 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 547 {
 548     AspeedSoCState *soc = &bmc->soc;
 549
 550     /* bus 2 : */
 551     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 552     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 553     /* bus 2 : pca9546 @ 0x73 */
 554
 555     /* bus 3 : pca9548 @ 0x70 */
 556
 557     /* bus 4 : */
 558     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 559     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 560                           eeprom4_54);
 561     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 562     create_pca9552(soc, 4, 0x76);
 563     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 564     create_pca9552(soc, 4, 0x77);
 565
 566     /* bus 6 : */
 567     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 568     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 569     /* bus 6 : pca9546 @ 0x73 */
 570
 571     /* bus 8 : */
 572     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 573     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 574                           eeprom8_56);
 575     create_pca9552(soc, 8, 0x60);
 576     create_pca9552(soc, 8, 0x61);
 577     /* bus 8 : adc128d818 @ 0x1d */
 578     /* bus 8 : adc128d818 @ 0x1f */
 579
 580     /*
 581      * bus 13 : pca9548 @ 0x71
 582      *      - channel 3:
 583      *          - tmm421 @ 0x4c
 584      *          - tmp421 @ 0x4e
 585      *          - tmp421 @ 0x4f
 586      */
 587
 588 }
 589
 590 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 591 {
 592     static const struct {
 593         unsigned gpio_id;
 594         LEDColor color;
 595         const char *description;
 596         bool gpio_polarity;
 597     } pca1_leds[] = {
 598         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 599         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 600         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 601     };
 602     AspeedSoCState *soc = &bmc->soc;
 603     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 604     DeviceState *dev;
 605     LEDState *led;
 606
 607     /* Bus 3: TODO bmp280@77 */
 608     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 609     qdev_prop_set_string(dev, "description", "pca1");
 610     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 611                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 612                                 &error_fatal);
 613
 614     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 615         led = led_create_simple(OBJECT(bmc),
 616                                 pca1_leds[i].gpio_polarity,
 617                                 pca1_leds[i].color,
 618                                 pca1_leds[i].description);
 619         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 620                               qdev_get_gpio_in(DEVICE(led), 0));
 621     }
 622     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 623     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 624     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 625     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 626
 627     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 628     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 629                      0x4a);
 630
 631     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 632      * good enough */
 633     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 634
 635     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 636                           eeprom_buf);
 637     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 638     qdev_prop_set_string(dev, "description", "pca0");
 639     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 640                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 641                                 &error_fatal);
 642     /* Bus 11: TODO ucd90160@64 */
 643 }
 644
 645 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 646 {
 647     AspeedSoCState *soc = &bmc->soc;
 648     DeviceState *dev;
 649
 650     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 651                                          "emc1413", 0x4c));
 652     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 653     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 654     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 655
 656     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 657                                          "emc1413", 0x4c));
 658     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 659     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 660     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 661
 662     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 663                                          "emc1413", 0x4c));
 664     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 665     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 666     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 667
 668     static uint8_t eeprom_buf[2 * 1024] = {
 669             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 670             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 671             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 672             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 673             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 674             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 675             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 676     };
 677     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 678                           eeprom_buf);
 679 }
 680
 681 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
 682 {
 683     I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
 684     DeviceState *dev = DEVICE(i2c_dev);
 685
 686     qdev_prop_set_uint32(dev, "rom-size", rsize);
 687     i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
 688 }
 689
 690 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 691 {
 692     AspeedSoCState *soc = &bmc->soc;
 693     I2CSlave *i2c_mux;
 694
 695     /* The at24c256 */
 696     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 697
 698     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 699     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 700                      0x48);
 701     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 702                      0x49);
 703
 704     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 705                      "pca9546", 0x70);
 706     /* It expects a TMP112 but a TMP105 is compatible */
 707     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 708                      0x4a);
 709
 710     /* It expects a ds3232 but a ds1338 is good enough */
 711     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 712
 713     /* It expects a pca9555 but a pca9552 is compatible */
 714     create_pca9552(soc, 8, 0x30);
 715 }
 716
 717 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 718 {
 719     AspeedSoCState *soc = &bmc->soc;
 720     I2CSlave *i2c_mux;
 721
 722     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 723
 724     create_pca9552(soc, 3, 0x61);
 725
 726     /* The rainier expects a TMP275 but a TMP105 is compatible */
 727     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 728                      0x48);
 729     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 730                      0x49);
 731     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 732                      0x4a);
 733     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 734                                       "pca9546", 0x70);
 735     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 736     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 737     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 738     create_pca9552(soc, 4, 0x60);
 739
 740     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 741                      0x48);
 742     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 743                      0x49);
 744     create_pca9552(soc, 5, 0x60);
 745     create_pca9552(soc, 5, 0x61);
 746     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 747                                       "pca9546", 0x70);
 748     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 749     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 750
 751     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 752                      0x48);
 753     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 754                      0x4a);
 755     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 756                      0x4b);
 757     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 758                                       "pca9546", 0x70);
 759     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 760     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 761     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 762     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 763
 764     create_pca9552(soc, 7, 0x30);
 765     create_pca9552(soc, 7, 0x31);
 766     create_pca9552(soc, 7, 0x32);
 767     create_pca9552(soc, 7, 0x33);
 768     create_pca9552(soc, 7, 0x60);
 769     create_pca9552(soc, 7, 0x61);
 770     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 771     /* Bus 7: TODO si7021-a20@20 */
 772     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 773                      0x48);
 774     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 775     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 776     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 777
 778     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 779                      0x48);
 780     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 781                      0x4a);
 782     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
 783     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 784     create_pca9552(soc, 8, 0x60);
 785     create_pca9552(soc, 8, 0x61);
 786     /* Bus 8: ucd90320@11 */
 787     /* Bus 8: ucd90320@b */
 788     /* Bus 8: ucd90320@c */
 789
 790     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 791     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 792     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 793
 794     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 795     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 796     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 797
 798     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 799                      0x48);
 800     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 801                      0x49);
 802     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 803                                       "pca9546", 0x70);
 804     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 805     aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 806     create_pca9552(soc, 11, 0x60);
 807
 808
 809     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 810     create_pca9552(soc, 13, 0x60);
 811
 812     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 813     create_pca9552(soc, 14, 0x60);
 814
 815     aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 816     create_pca9552(soc, 15, 0x60);
 817 }
 818
 819 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 820                                  I2CBus **channels)
 821 {
 822     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 823     for (int i = 0; i < 8; i++) {
 824         channels[i] = pca954x_i2c_get_bus(mux, i);
 825     }
 826 }
 827
 828 #define TYPE_LM75 TYPE_TMP105
 829 #define TYPE_TMP75 TYPE_TMP105
 830 #define TYPE_TMP422 "tmp422"
 831
 832 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 833 {
 834     AspeedSoCState *soc = &bmc->soc;
 835     I2CBus *i2c[144] = {};
 836
 837     for (int i = 0; i < 16; i++) {
 838         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 839     }
 840     I2CBus *i2c180 = i2c[2];
 841     I2CBus *i2c480 = i2c[8];
 842     I2CBus *i2c600 = i2c[11];
 843
 844     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 845     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 846     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 847     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 848     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 849     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 850     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 851     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 852     for (int i = 0; i < 8; i++) {
 853         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 854     }
 855
 856     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 857     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 858
 859     aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
 860     aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
 861     aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
 862
 863     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 864     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 865     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 866     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 867
 868     aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
 869     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 870
 871     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 872     aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
 873     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 874     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 875
 876     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 877     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 878
 879     aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
 880     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 881     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 882     aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
 883     aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
 884     aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
 885     aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
 886
 887     aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
 888     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 889     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 890     aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
 891     aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
 892     aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
 893     aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
 894     aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
 895
 896     for (int i = 0; i < 8; i++) {
 897         aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 898         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 899         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 900         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 901     }
 902 }
 903
 904 #define TYPE_TMP421 "tmp421"
 905
 906 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 907 {
 908     AspeedSoCState *soc = &bmc->soc;
 909     I2CBus *i2c[13] = {};
 910     for (int i = 0; i < 13; i++) {
 911         if ((i == 8) || (i == 11)) {
 912             continue;
 913         }
 914         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 915     }
 916
 917     /* Bus 0 - 5 all have the same config. */
 918     for (int i = 0; i < 6; i++) {
 919         /* Missing model: ti,ina230 @ 0x45 */
 920         /* Missing model: mps,mp5023 @ 0x40 */
 921         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 922         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 923         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 924         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 925         /* Missing model: fsc,fusb302 @ 0x22 */
 926     }
 927
 928     /* Bus 6 */
 929     at24c_eeprom_init(i2c[6], 0x56, 65536);
 930     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 931     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 932
 933
 934     /* Bus 7 */
 935     at24c_eeprom_init(i2c[7], 0x54, 65536);
 936
 937     /* Bus 9 */
 938     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 939
 940     /* Bus 10 */
 941     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 942     /* Missing model: ti,hdc1080 @ 0x40 */
 943     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 944
 945     /* Bus 12 */
 946     /* Missing model: adi,adm1278 @ 0x11 */
 947     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 948     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 949     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 950 }
 951
 952 static void fby35_i2c_init(AspeedMachineState *bmc)
 953 {
 954     AspeedSoCState *soc = &bmc->soc;
 955     I2CBus *i2c[16];
 956
 957     for (int i = 0; i < 16; i++) {
 958         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 959     }
 960
 961     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 962     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 963     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 964     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 965     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 966     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 967
 968     aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
 969     aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
 970     aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
 971     aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
 972     aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
 973
 974     /*
 975      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
 976      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
 977      * each.
 978      */
 979 }
 980
 981 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 982 {
 983     AspeedSoCState *soc = &bmc->soc;
 984
 985     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 986 }
 987
 988 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 989 {
 990     AspeedSoCState *soc = &bmc->soc;
 991     I2CSlave *therm_mux, *cpuvr_mux;
 992
 993     /* Create the generic DC-SCM hardware */
 994     qcom_dc_scm_bmc_i2c_init(bmc);
 995
 996     /* Now create the Firework specific hardware */
 997
 998     /* I2C7 CPUVR MUX */
 999     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1000                                         "pca9546", 0x70);
1001     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1002     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1003     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1004     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1005
1006     /* I2C8 Thermal Diodes*/
1007     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1008                                         "pca9548", 0x70);
1009     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1010     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1011     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1012     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1013     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1014
1015     /* I2C9 Fan Controller (MAX31785) */
1016     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1017     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1018 }
1019
1020 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1021 {
1022     return ASPEED_MACHINE(obj)->mmio_exec;
1023 }
1024
1025 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1026 {
1027     ASPEED_MACHINE(obj)->mmio_exec = value;
1028 }
1029
1030 static void aspeed_machine_instance_init(Object *obj)
1031 {
1032     ASPEED_MACHINE(obj)->mmio_exec = false;
1033 }
1034
1035 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1036 {
1037     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1038     return g_strdup(bmc->fmc_model);
1039 }
1040
1041 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1042 {
1043     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1044
1045     g_free(bmc->fmc_model);
1046     bmc->fmc_model = g_strdup(value);
1047 }
1048
1049 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1050 {
1051     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1052     return g_strdup(bmc->spi_model);
1053 }
1054
1055 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1056 {
1057     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1058
1059     g_free(bmc->spi_model);
1060     bmc->spi_model = g_strdup(value);
1061 }
1062
1063 static void aspeed_machine_class_props_init(ObjectClass *oc)
1064 {
1065     object_class_property_add_bool(oc, "execute-in-place",
1066                                    aspeed_get_mmio_exec,
1067                                    aspeed_set_mmio_exec);
1068     object_class_property_set_description(oc, "execute-in-place",
1069                            "boot directly from CE0 flash device");
1070
1071     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1072                                    aspeed_set_fmc_model);
1073     object_class_property_set_description(oc, "fmc-model",
1074                                           "Change the FMC Flash model");
1075     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1076                                    aspeed_set_spi_model);
1077     object_class_property_set_description(oc, "spi-model",
1078                                           "Change the SPI Flash model");
1079 }
1080
1081 static int aspeed_soc_num_cpus(const char *soc_name)
1082 {
1083    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1084    return sc->num_cpus;
1085 }
1086
1087 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1088 {
1089     MachineClass *mc = MACHINE_CLASS(oc);
1090     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1091
1092     mc->init = aspeed_machine_init;
1093     mc->no_floppy = 1;
1094     mc->no_cdrom = 1;
1095     mc->no_parallel = 1;
1096     mc->default_ram_id = "ram";
1097     amc->macs_mask = ASPEED_MAC0_ON;
1098     amc->uart_default = ASPEED_DEV_UART5;
1099
1100     aspeed_machine_class_props_init(oc);
1101 }
1102
1103 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1104 {
1105     MachineClass *mc = MACHINE_CLASS(oc);
1106     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1107
1108     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1109     amc->soc_name  = "ast2400-a1";
1110     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1111     amc->fmc_model = "n25q256a";
1112     amc->spi_model = "mx25l25635f";
1113     amc->num_cs    = 1;
1114     amc->i2c_init  = palmetto_bmc_i2c_init;
1115     mc->default_ram_size       = 256 * MiB;
1116     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1117         aspeed_soc_num_cpus(amc->soc_name);
1118 };
1119
1120 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1121 {
1122     MachineClass *mc = MACHINE_CLASS(oc);
1123     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1124
1125     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1126     amc->soc_name  = "ast2400-a1";
1127     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1128     amc->fmc_model = "n25q256a";
1129     amc->spi_model = "mx25l25635e";
1130     amc->num_cs    = 1;
1131     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1132     mc->default_ram_size       = 128 * MiB;
1133     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1134         aspeed_soc_num_cpus(amc->soc_name);
1135 }
1136
1137 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1138                                                         void *data)
1139 {
1140     MachineClass *mc = MACHINE_CLASS(oc);
1141     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1142
1143     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1144     amc->soc_name  = "ast2400-a1";
1145     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1146     amc->fmc_model = "mx25l25635e";
1147     amc->spi_model = "mx25l25635e";
1148     amc->num_cs    = 1;
1149     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1150     amc->i2c_init  = palmetto_bmc_i2c_init;
1151     mc->default_ram_size = 256 * MiB;
1152 }
1153
1154 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1155                                                             void *data)
1156 {
1157     MachineClass *mc = MACHINE_CLASS(oc);
1158     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1159
1160     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1161     amc->soc_name  = "ast2500-a1";
1162     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1163     amc->fmc_model = "mx25l25635e";
1164     amc->spi_model = "mx25l25635e";
1165     amc->num_cs    = 1;
1166     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1167     amc->i2c_init  = palmetto_bmc_i2c_init;
1168     mc->default_ram_size = 512 * MiB;
1169     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1170         aspeed_soc_num_cpus(amc->soc_name);
1171 }
1172
1173 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1174 {
1175     MachineClass *mc = MACHINE_CLASS(oc);
1176     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1177
1178     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1179     amc->soc_name  = "ast2500-a1";
1180     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1181     amc->fmc_model = "mx25l25635e";
1182     amc->spi_model = "mx25l25635f";
1183     amc->num_cs    = 1;
1184     amc->i2c_init  = ast2500_evb_i2c_init;
1185     mc->default_ram_size       = 512 * MiB;
1186     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1187         aspeed_soc_num_cpus(amc->soc_name);
1188 };
1189
1190 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1191 {
1192     MachineClass *mc = MACHINE_CLASS(oc);
1193     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1194
1195     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1196     amc->soc_name  = "ast2500-a1";
1197     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1198     amc->fmc_model = "n25q256a";
1199     amc->spi_model = "mx66l1g45g";
1200     amc->num_cs    = 2;
1201     amc->i2c_init  = romulus_bmc_i2c_init;
1202     mc->default_ram_size       = 512 * MiB;
1203     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1204         aspeed_soc_num_cpus(amc->soc_name);
1205 };
1206
1207 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1208 {
1209     MachineClass *mc = MACHINE_CLASS(oc);
1210     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1211
1212     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1213     amc->soc_name  = "ast2500-a1";
1214     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1215     amc->fmc_model = "mx66l1g45g";
1216     amc->spi_model = "mx66l1g45g";
1217     amc->num_cs    = 2;
1218     amc->i2c_init  = sonorapass_bmc_i2c_init;
1219     mc->default_ram_size       = 512 * MiB;
1220     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1221         aspeed_soc_num_cpus(amc->soc_name);
1222 };
1223
1224 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1225 {
1226     MachineClass *mc = MACHINE_CLASS(oc);
1227     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1228
1229     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1230     amc->soc_name  = "ast2500-a1";
1231     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1232     amc->fmc_model = "mx25l25635f";
1233     amc->spi_model = "mx66l1g45g";
1234     amc->num_cs    = 2;
1235     amc->i2c_init  = witherspoon_bmc_i2c_init;
1236     mc->default_ram_size = 512 * MiB;
1237     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1238         aspeed_soc_num_cpus(amc->soc_name);
1239 };
1240
1241 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1242 {
1243     MachineClass *mc = MACHINE_CLASS(oc);
1244     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1245
1246     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1247     amc->soc_name  = "ast2600-a3";
1248     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1249     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1250     amc->fmc_model = "mx66u51235f";
1251     amc->spi_model = "mx66u51235f";
1252     amc->num_cs    = 1;
1253     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1254                      ASPEED_MAC3_ON;
1255     amc->i2c_init  = ast2600_evb_i2c_init;
1256     mc->default_ram_size = 1 * GiB;
1257     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1258         aspeed_soc_num_cpus(amc->soc_name);
1259 };
1260
1261 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1262 {
1263     MachineClass *mc = MACHINE_CLASS(oc);
1264     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1265
1266     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1267     amc->soc_name  = "ast2600-a3";
1268     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1269     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1270     amc->fmc_model = "mx66l1g45g";
1271     amc->spi_model = "mx66l1g45g";
1272     amc->num_cs    = 2;
1273     amc->macs_mask  = ASPEED_MAC2_ON;
1274     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1275     mc->default_ram_size = 1 * GiB;
1276     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1277         aspeed_soc_num_cpus(amc->soc_name);
1278 };
1279
1280 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1281 {
1282     MachineClass *mc = MACHINE_CLASS(oc);
1283     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1284
1285     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1286     amc->soc_name  = "ast2500-a1";
1287     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1288     amc->fmc_model = "n25q512a";
1289     amc->spi_model = "mx25l25635e";
1290     amc->num_cs    = 2;
1291     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1292     amc->i2c_init  = g220a_bmc_i2c_init;
1293     mc->default_ram_size = 1024 * MiB;
1294     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1295         aspeed_soc_num_cpus(amc->soc_name);
1296 };
1297
1298 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1299 {
1300     MachineClass *mc = MACHINE_CLASS(oc);
1301     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1302
1303     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1304     amc->soc_name  = "ast2500-a1";
1305     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1306     amc->fmc_model = "n25q512a";
1307     amc->spi_model = "mx25l25635e";
1308     amc->num_cs    = 2;
1309     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1310     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1311     mc->default_ram_size = 512 * MiB;
1312     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1313         aspeed_soc_num_cpus(amc->soc_name);
1314 };
1315
1316 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1317 {
1318     MachineClass *mc = MACHINE_CLASS(oc);
1319     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1320
1321     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1322     amc->soc_name  = "ast2600-a3";
1323     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1324     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1325     amc->fmc_model = "mx66l1g45g";
1326     amc->spi_model = "mx66l1g45g";
1327     amc->num_cs    = 2;
1328     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1329     amc->i2c_init  = rainier_bmc_i2c_init;
1330     mc->default_ram_size = 1 * GiB;
1331     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1332         aspeed_soc_num_cpus(amc->soc_name);
1333 };
1334
1335 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1336 #if HOST_LONG_BITS == 32
1337 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1338 #else
1339 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1340 #endif
1341
1342 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1343 {
1344     MachineClass *mc = MACHINE_CLASS(oc);
1345     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1346
1347     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1348     amc->soc_name = "ast2600-a3";
1349     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1350     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1351     amc->fmc_model = "mx66l1g45g";
1352     amc->spi_model = "mx66l1g45g";
1353     amc->num_cs = 2;
1354     amc->macs_mask = ASPEED_MAC3_ON;
1355     amc->i2c_init = fuji_bmc_i2c_init;
1356     amc->uart_default = ASPEED_DEV_UART1;
1357     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1358     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1359         aspeed_soc_num_cpus(amc->soc_name);
1360 };
1361
1362 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1363 #if HOST_LONG_BITS == 32
1364 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1365 #else
1366 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1367 #endif
1368
1369 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1370 {
1371     MachineClass *mc = MACHINE_CLASS(oc);
1372     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1373
1374     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1375     amc->soc_name  = "ast2600-a3";
1376     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1377     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1378     amc->fmc_model = "w25q01jvq";
1379     amc->spi_model = NULL;
1380     amc->num_cs    = 2;
1381     amc->macs_mask = ASPEED_MAC2_ON;
1382     amc->i2c_init  = bletchley_bmc_i2c_init;
1383     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1384     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1385         aspeed_soc_num_cpus(amc->soc_name);
1386 }
1387
1388 static void fby35_reset(MachineState *state, ShutdownCause reason)
1389 {
1390     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1391     AspeedGPIOState *gpio = &bmc->soc.gpio;
1392
1393     qemu_devices_reset(reason);
1394
1395     /* Board ID: 7 (Class-1, 4 slots) */
1396     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1397     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1398     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1399     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1400
1401     /* Slot presence pins, inverse polarity. (False means present) */
1402     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1403     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1404     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1405     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1406
1407     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1408     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1409     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1410     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1411     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1412 }
1413
1414 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1415 {
1416     MachineClass *mc = MACHINE_CLASS(oc);
1417     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1418
1419     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1420     mc->reset      = fby35_reset;
1421     amc->fmc_model = "mx66l1g45g";
1422     amc->num_cs    = 2;
1423     amc->macs_mask = ASPEED_MAC3_ON;
1424     amc->i2c_init  = fby35_i2c_init;
1425     /* FIXME: Replace this macro with something more general */
1426     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1427 }
1428
1429 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1430 /* Main SYSCLK frequency in Hz (200MHz) */
1431 #define SYSCLK_FRQ 200000000ULL
1432
1433 static void aspeed_minibmc_machine_init(MachineState *machine)
1434 {
1435     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1436     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1437     Clock *sysclk;
1438
1439     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1440     clock_set_hz(sysclk, SYSCLK_FRQ);
1441
1442     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1443     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1444
1445     object_property_set_link(OBJECT(&bmc->soc), "memory",
1446                              OBJECT(get_system_memory()), &error_abort);
1447     connect_serial_hds_to_uarts(bmc);
1448     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1449
1450     aspeed_board_init_flashes(&bmc->soc.fmc,
1451                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1452                               amc->num_cs,
1453                               0);
1454
1455     aspeed_board_init_flashes(&bmc->soc.spi[0],
1456                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1457                               amc->num_cs, amc->num_cs);
1458
1459     aspeed_board_init_flashes(&bmc->soc.spi[1],
1460                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1461                               amc->num_cs, (amc->num_cs * 2));
1462
1463     if (amc->i2c_init) {
1464         amc->i2c_init(bmc);
1465     }
1466
1467     armv7m_load_kernel(ARM_CPU(first_cpu),
1468                        machine->kernel_filename,
1469                        0,
1470                        AST1030_INTERNAL_FLASH_SIZE);
1471 }
1472
1473 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1474 {
1475     AspeedSoCState *soc = &bmc->soc;
1476
1477     /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1478     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1479     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1480
1481     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1482     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1483 }
1484
1485 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1486                                                           void *data)
1487 {
1488     MachineClass *mc = MACHINE_CLASS(oc);
1489     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1490
1491     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1492     amc->soc_name = "ast1030-a1";
1493     amc->hw_strap1 = 0;
1494     amc->hw_strap2 = 0;
1495     mc->init = aspeed_minibmc_machine_init;
1496     amc->i2c_init = ast1030_evb_i2c_init;
1497     mc->default_ram_size = 0;
1498     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1499     amc->fmc_model = "sst25vf032b";
1500     amc->spi_model = "sst25vf032b";
1501     amc->num_cs = 2;
1502     amc->macs_mask = 0;
1503 }
1504
1505 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1506                                                      void *data)
1507 {
1508     MachineClass *mc = MACHINE_CLASS(oc);
1509     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1510
1511     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1512     amc->soc_name  = "ast2600-a3";
1513     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1514     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1515     amc->fmc_model = "n25q512a";
1516     amc->spi_model = "n25q512a";
1517     amc->num_cs    = 2;
1518     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1519     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1520     mc->default_ram_size = 1 * GiB;
1521     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1522         aspeed_soc_num_cpus(amc->soc_name);
1523 };
1524
1525 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1526                                                     void *data)
1527 {
1528     MachineClass *mc = MACHINE_CLASS(oc);
1529     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1530
1531     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1532     amc->soc_name  = "ast2600-a3";
1533     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1534     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1535     amc->fmc_model = "n25q512a";
1536     amc->spi_model = "n25q512a";
1537     amc->num_cs    = 2;
1538     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1539     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1540     mc->default_ram_size = 1 * GiB;
1541     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1542         aspeed_soc_num_cpus(amc->soc_name);
1543 };
1544
1545 static const TypeInfo aspeed_machine_types[] = {
1546     {
1547         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1548         .parent        = TYPE_ASPEED_MACHINE,
1549         .class_init    = aspeed_machine_palmetto_class_init,
1550     }, {
1551         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1552         .parent        = TYPE_ASPEED_MACHINE,
1553         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1554     }, {
1555         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1556         .parent        = TYPE_ASPEED_MACHINE,
1557         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1558     }, {
1559         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1560         .parent        = TYPE_ASPEED_MACHINE,
1561         .class_init    = aspeed_machine_ast2500_evb_class_init,
1562     }, {
1563         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1564         .parent        = TYPE_ASPEED_MACHINE,
1565         .class_init    = aspeed_machine_romulus_class_init,
1566     }, {
1567         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1568         .parent        = TYPE_ASPEED_MACHINE,
1569         .class_init    = aspeed_machine_sonorapass_class_init,
1570     }, {
1571         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1572         .parent        = TYPE_ASPEED_MACHINE,
1573         .class_init    = aspeed_machine_witherspoon_class_init,
1574     }, {
1575         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1576         .parent        = TYPE_ASPEED_MACHINE,
1577         .class_init    = aspeed_machine_ast2600_evb_class_init,
1578     }, {
1579         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1580         .parent        = TYPE_ASPEED_MACHINE,
1581         .class_init    = aspeed_machine_tacoma_class_init,
1582     }, {
1583         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1584         .parent        = TYPE_ASPEED_MACHINE,
1585         .class_init    = aspeed_machine_g220a_class_init,
1586     }, {
1587         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1588         .parent        = TYPE_ASPEED_MACHINE,
1589         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1590     }, {
1591         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1592         .parent        = TYPE_ASPEED_MACHINE,
1593         .class_init    = aspeed_machine_qcom_firework_class_init,
1594     }, {
1595         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1596         .parent        = TYPE_ASPEED_MACHINE,
1597         .class_init    = aspeed_machine_fp5280g2_class_init,
1598     }, {
1599         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1600         .parent        = TYPE_ASPEED_MACHINE,
1601         .class_init    = aspeed_machine_quanta_q71l_class_init,
1602     }, {
1603         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1604         .parent        = TYPE_ASPEED_MACHINE,
1605         .class_init    = aspeed_machine_rainier_class_init,
1606     }, {
1607         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1608         .parent        = TYPE_ASPEED_MACHINE,
1609         .class_init    = aspeed_machine_fuji_class_init,
1610     }, {
1611         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1612         .parent        = TYPE_ASPEED_MACHINE,
1613         .class_init    = aspeed_machine_bletchley_class_init,
1614     }, {
1615         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1616         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1617         .class_init    = aspeed_machine_fby35_class_init,
1618     }, {
1619         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1620         .parent         = TYPE_ASPEED_MACHINE,
1621         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1622     }, {
1623         .name          = TYPE_ASPEED_MACHINE,
1624         .parent        = TYPE_MACHINE,
1625         .instance_size = sizeof(AspeedMachineState),
1626         .instance_init = aspeed_machine_instance_init,
1627         .class_size    = sizeof(AspeedMachineClass),
1628         .class_init    = aspeed_machine_class_init,
1629         .abstract      = true,
1630     }
1631 };
1632
1633 DEFINE_TYPES(aspeed_machine_types)