hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/arm/aspeed_eeprom.h"
  18 #include "hw/i2c/i2c_mux_pca954x.h"
  19 #include "hw/i2c/smbus_eeprom.h"
  20 #include "hw/misc/pca9552.h"
  21 #include "hw/nvram/eeprom_at24c.h"
  22 #include "hw/sensor/tmp105.h"
  23 #include "hw/misc/led.h"
  24 #include "hw/qdev-properties.h"
  25 #include "sysemu/block-backend.h"
  26 #include "sysemu/reset.h"
  27 #include "hw/loader.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/units.h"
  30 #include "hw/qdev-clock.h"
  31 #include "sysemu/sysemu.h"
  32
  33 static struct arm_boot_info aspeed_board_binfo = {
  34     .board_id = -1, /* device-tree-only board */
  35 };
  36
  37 struct AspeedMachineState {
  38     /* Private */
  39     MachineState parent_obj;
  40     /* Public */
  41
  42     AspeedSoCState soc;
  43     bool mmio_exec;
  44     char *fmc_model;
  45     char *spi_model;
  46 };
  47
  48 /* Palmetto hardware value: 0x120CE416 */
  49 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  50         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  51         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  52         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  53         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  54         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  55         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  56         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  57         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  58         SCU_HW_STRAP_SPI_WIDTH |                                        \
  59         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  60         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  61
  62 /* TODO: Find the actual hardware value */
  63 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  64         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  65         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  66         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  67         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  68         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  69         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  70         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  71         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  72         SCU_HW_STRAP_SPI_WIDTH |                                        \
  73         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  74         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  75
  76 /* TODO: Find the actual hardware value */
  77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  78         AST2500_HW_STRAP1_DEFAULTS |                                    \
  79         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  80         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  81         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  82         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  83         SCU_HW_STRAP_SPI_WIDTH |                                        \
  84         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  85
  86 /* AST2500 evb hardware value: 0xF100C2E6 */
  87 #define AST2500_EVB_HW_STRAP1 ((                                        \
  88         AST2500_HW_STRAP1_DEFAULTS |                                    \
  89         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  90         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  91         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  92         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  93         SCU_HW_STRAP_MAC1_RGMII |                                       \
  94         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  95         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  96
  97 /* Romulus hardware value: 0xF10AD206 */
  98 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  99         AST2500_HW_STRAP1_DEFAULTS |                                    \
 100         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 101         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 102         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 103         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 104         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 105         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 106
 107 /* Sonorapass hardware value: 0xF100D216 */
 108 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 109         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 110         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 111         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 112         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 113         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 114         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 115         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 116         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 117         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 118         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 119         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 120         SCU_AST2500_HW_STRAP_RESERVED1)
 121
 122 #define G220A_BMC_HW_STRAP1 (                                      \
 123         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 124         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 125         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 126         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 127         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 128         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 129         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 130         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 131         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 132         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 133         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 134         SCU_AST2500_HW_STRAP_RESERVED1)
 135
 136 /* FP5280G2 hardware value: 0XF100D286 */
 137 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 138         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 139         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 140         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 141         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 142         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 143         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 144         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 145         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 146         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 147         SCU_HW_STRAP_MAC1_RGMII |                                       \
 148         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 149         SCU_AST2500_HW_STRAP_RESERVED1)
 150
 151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 153
 154 /* Quanta-Q71l hardware value */
 155 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 156         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 157         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 158         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 159         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 160         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 161         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 162         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 163         SCU_HW_STRAP_SPI_WIDTH |                                        \
 164         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 165         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 166
 167 /* AST2600 evb hardware value */
 168 #define AST2600_EVB_HW_STRAP1 0x000000C0
 169 #define AST2600_EVB_HW_STRAP2 0x00000003
 170
 171 /* Tacoma hardware value */
 172 #define TACOMA_BMC_HW_STRAP1  0x00000000
 173 #define TACOMA_BMC_HW_STRAP2  0x00000040
 174
 175 /* Rainier hardware value: (QEMU prototype) */
 176 #define RAINIER_BMC_HW_STRAP1 0x00422016
 177 #define RAINIER_BMC_HW_STRAP2 0x80000848
 178
 179 /* Fuji hardware value */
 180 #define FUJI_BMC_HW_STRAP1    0x00000000
 181 #define FUJI_BMC_HW_STRAP2    0x00000000
 182
 183 /* Bletchley hardware value */
 184 /* TODO: Leave same as EVB for now. */
 185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 187
 188 /* Qualcomm DC-SCM hardware value */
 189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 191
 192 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 193 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 194 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 195 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 196 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 197 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 198 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 199
 200 static void aspeed_write_smpboot(ARMCPU *cpu,
 201                                  const struct arm_boot_info *info)
 202 {
 203     static const uint32_t poll_mailbox_ready[] = {
 204         /*
 205          * r2 = per-cpu go sign value
 206          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 207          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 208          */
 209         0xee100fb0,  /* mrc     p15, 0, r0, c0, c0, 5 */
 210         0xe21000ff,  /* ands    r0, r0, #255          */
 211         0xe59f201c,  /* ldr     r2, [pc, #28]         */
 212         0xe1822000,  /* orr     r2, r2, r0            */
 213
 214         0xe59f1018,  /* ldr     r1, [pc, #24]         */
 215         0xe59f0018,  /* ldr     r0, [pc, #24]         */
 216
 217         0xe320f002,  /* wfe                           */
 218         0xe5904000,  /* ldr     r4, [r0]              */
 219         0xe1520004,  /* cmp     r2, r4                */
 220         0x1afffffb,  /* bne     <wfe>                 */
 221         0xe591f000,  /* ldr     pc, [r1]              */
 222         AST_SMP_MBOX_GOSIGN,
 223         AST_SMP_MBOX_FIELD_ENTRY,
 224         AST_SMP_MBOX_FIELD_GOSIGN,
 225     };
 226
 227     rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
 228                        sizeof(poll_mailbox_ready),
 229                        info->smp_loader_start);
 230 }
 231
 232 static void aspeed_reset_secondary(ARMCPU *cpu,
 233                                    const struct arm_boot_info *info)
 234 {
 235     AddressSpace *as = arm_boot_address_space(cpu, info);
 236     CPUState *cs = CPU(cpu);
 237
 238     /* info->smp_bootreg_addr */
 239     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 240                                MEMTXATTRS_UNSPECIFIED, NULL);
 241     cpu_set_pc(cs, info->smp_loader_start);
 242 }
 243
 244 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 245                            Error **errp)
 246 {
 247     g_autofree void *storage = NULL;
 248     int64_t size;
 249
 250     /* The block backend size should have already been 'validated' by
 251      * the creation of the m25p80 object.
 252      */
 253     size = blk_getlength(blk);
 254     if (size <= 0) {
 255         error_setg(errp, "failed to get flash size");
 256         return;
 257     }
 258
 259     if (rom_size > size) {
 260         rom_size = size;
 261     }
 262
 263     storage = g_malloc0(rom_size);
 264     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 265         error_setg(errp, "failed to read the initial flash content");
 266         return;
 267     }
 268
 269     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 270 }
 271
 272 /*
 273  * Create a ROM and copy the flash contents at the expected address
 274  * (0x0). Boots faster than execute-in-place.
 275  */
 276 static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
 277                                     uint64_t rom_size)
 278 {
 279     MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 280
 281     memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
 282                            &error_abort);
 283     memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
 284                                         boot_rom, 1);
 285     write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
 286 }
 287
 288 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 289                                       unsigned int count, int unit0)
 290 {
 291     int i;
 292
 293     if (!flashtype) {
 294         return;
 295     }
 296
 297     for (i = 0; i < count; ++i) {
 298         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 299         qemu_irq cs_line;
 300         DeviceState *dev;
 301
 302         dev = qdev_new(flashtype);
 303         if (dinfo) {
 304             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 305         }
 306         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 307
 308         cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 309         qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
 310     }
 311 }
 312
 313 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 314 {
 315         DeviceState *card;
 316
 317         if (!dinfo) {
 318             return;
 319         }
 320         card = qdev_new(TYPE_SD_CARD);
 321         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 322                                 &error_fatal);
 323         qdev_realize_and_unref(card,
 324                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 325                                &error_fatal);
 326 }
 327
 328 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 329 {
 330     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 331     AspeedSoCState *s = &bmc->soc;
 332     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 333
 334     aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
 335     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 336         if (uart == amc->uart_default) {
 337             continue;
 338         }
 339         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 340     }
 341 }
 342
 343 static void aspeed_machine_init(MachineState *machine)
 344 {
 345     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 346     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 347     AspeedSoCClass *sc;
 348     int i;
 349     NICInfo *nd = &nd_table[0];
 350
 351     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 352
 353     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 354
 355     /*
 356      * This will error out if the RAM size is not supported by the
 357      * memory controller of the SoC.
 358      */
 359     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 360                              &error_fatal);
 361
 362     for (i = 0; i < sc->macs_num; i++) {
 363         if ((amc->macs_mask & (1 << i)) && nd->used) {
 364             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 365             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 366             nd++;
 367         }
 368     }
 369
 370     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 371                             &error_abort);
 372     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 373                             &error_abort);
 374     object_property_set_link(OBJECT(&bmc->soc), "memory",
 375                              OBJECT(get_system_memory()), &error_abort);
 376     object_property_set_link(OBJECT(&bmc->soc), "dram",
 377                              OBJECT(machine->ram), &error_abort);
 378     if (machine->kernel_filename) {
 379         /*
 380          * When booting with a -kernel command line there is no u-boot
 381          * that runs to unlock the SCU. In this case set the default to
 382          * be unlocked as the kernel expects
 383          */
 384         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 385                                 ASPEED_SCU_PROT_KEY, &error_abort);
 386     }
 387     connect_serial_hds_to_uarts(bmc);
 388     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 389
 390     aspeed_board_init_flashes(&bmc->soc.fmc,
 391                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 392                               amc->num_cs, 0);
 393     aspeed_board_init_flashes(&bmc->soc.spi[0],
 394                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 395                               1, amc->num_cs);
 396
 397     if (machine->kernel_filename && sc->num_cpus > 1) {
 398         /* With no u-boot we must set up a boot stub for the secondary CPU */
 399         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 400         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 401                                0x80, &error_abort);
 402         memory_region_add_subregion(get_system_memory(),
 403                                     AST_SMP_MAILBOX_BASE, smpboot);
 404
 405         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 406         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 407         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 408     }
 409
 410     aspeed_board_binfo.ram_size = machine->ram_size;
 411     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 412
 413     if (amc->i2c_init) {
 414         amc->i2c_init(bmc);
 415     }
 416
 417     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 418         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 419                            drive_get(IF_SD, 0, i));
 420     }
 421
 422     if (bmc->soc.emmc.num_slots) {
 423         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 424                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 425     }
 426
 427     if (!bmc->mmio_exec) {
 428         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 429
 430         if (mtd0) {
 431             uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 432             aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
 433                                     rom_size);
 434         }
 435     }
 436
 437     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 438 }
 439
 440 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 441 {
 442     AspeedSoCState *soc = &bmc->soc;
 443     DeviceState *dev;
 444     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 445
 446     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 447      * enough to provide basic RTC features. Alarms will be missing */
 448     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 449
 450     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 451                           eeprom_buf);
 452
 453     /* add a TMP423 temperature sensor */
 454     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 455                                          "tmp423", 0x4c));
 456     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 457     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 458     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 459     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 460 }
 461
 462 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 463 {
 464     AspeedSoCState *soc = &bmc->soc;
 465
 466     /*
 467      * The quanta-q71l platform expects tmp75s which are compatible with
 468      * tmp105s.
 469      */
 470     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 471     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 472     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 473
 474     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 475     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 476     /* TODO: Add Memory Riser i2c mux and eeproms. */
 477
 478     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 479     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 480
 481     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 482
 483     /* i2c-7 */
 484     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 485     /*        - i2c@0: pmbus@59 */
 486     /*        - i2c@1: pmbus@58 */
 487     /*        - i2c@2: pmbus@58 */
 488     /*        - i2c@3: pmbus@59 */
 489
 490     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 491     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 492 }
 493
 494 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 495 {
 496     AspeedSoCState *soc = &bmc->soc;
 497     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 498
 499     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 500                           eeprom_buf);
 501
 502     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 503     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 504                      TYPE_TMP105, 0x4d);
 505 }
 506
 507 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 508 {
 509     AspeedSoCState *soc = &bmc->soc;
 510     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 511
 512     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 513                           eeprom_buf);
 514
 515     /* LM75 is compatible with TMP105 driver */
 516     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 517                      TYPE_TMP105, 0x4d);
 518 }
 519
 520 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 521 {
 522     AspeedSoCState *soc = &bmc->soc;
 523
 524     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
 525     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
 526                           yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
 527 }
 528
 529 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 530 {
 531     AspeedSoCState *soc = &bmc->soc;
 532
 533     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 534      * good enough */
 535     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 536 }
 537
 538 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 539 {
 540     AspeedSoCState *soc = &bmc->soc;
 541
 542     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
 543     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
 544                           tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
 545 }
 546
 547 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 548 {
 549     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 550                             TYPE_PCA9552, addr);
 551 }
 552
 553 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 554 {
 555     AspeedSoCState *soc = &bmc->soc;
 556
 557     /* bus 2 : */
 558     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 559     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 560     /* bus 2 : pca9546 @ 0x73 */
 561
 562     /* bus 3 : pca9548 @ 0x70 */
 563
 564     /* bus 4 : */
 565     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 566     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 567                           eeprom4_54);
 568     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 569     create_pca9552(soc, 4, 0x76);
 570     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 571     create_pca9552(soc, 4, 0x77);
 572
 573     /* bus 6 : */
 574     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 575     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 576     /* bus 6 : pca9546 @ 0x73 */
 577
 578     /* bus 8 : */
 579     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 580     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 581                           eeprom8_56);
 582     create_pca9552(soc, 8, 0x60);
 583     create_pca9552(soc, 8, 0x61);
 584     /* bus 8 : adc128d818 @ 0x1d */
 585     /* bus 8 : adc128d818 @ 0x1f */
 586
 587     /*
 588      * bus 13 : pca9548 @ 0x71
 589      *      - channel 3:
 590      *          - tmm421 @ 0x4c
 591      *          - tmp421 @ 0x4e
 592      *          - tmp421 @ 0x4f
 593      */
 594
 595 }
 596
 597 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 598 {
 599     static const struct {
 600         unsigned gpio_id;
 601         LEDColor color;
 602         const char *description;
 603         bool gpio_polarity;
 604     } pca1_leds[] = {
 605         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 606         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 607         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 608     };
 609     AspeedSoCState *soc = &bmc->soc;
 610     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 611     DeviceState *dev;
 612     LEDState *led;
 613
 614     /* Bus 3: TODO bmp280@77 */
 615     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 616     qdev_prop_set_string(dev, "description", "pca1");
 617     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 618                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 619                                 &error_fatal);
 620
 621     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 622         led = led_create_simple(OBJECT(bmc),
 623                                 pca1_leds[i].gpio_polarity,
 624                                 pca1_leds[i].color,
 625                                 pca1_leds[i].description);
 626         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 627                               qdev_get_gpio_in(DEVICE(led), 0));
 628     }
 629     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 630     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 631     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 632     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 633
 634     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 635     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 636                      0x4a);
 637
 638     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 639      * good enough */
 640     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 641
 642     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 643                           eeprom_buf);
 644     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 645     qdev_prop_set_string(dev, "description", "pca0");
 646     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 647                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 648                                 &error_fatal);
 649     /* Bus 11: TODO ucd90160@64 */
 650 }
 651
 652 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 653 {
 654     AspeedSoCState *soc = &bmc->soc;
 655     DeviceState *dev;
 656
 657     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 658                                          "emc1413", 0x4c));
 659     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 660     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 661     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 662
 663     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 664                                          "emc1413", 0x4c));
 665     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 666     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 667     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 668
 669     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 670                                          "emc1413", 0x4c));
 671     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 672     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 673     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 674
 675     static uint8_t eeprom_buf[2 * 1024] = {
 676             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 677             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 678             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 679             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 680             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 681             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 682             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 683     };
 684     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 685                           eeprom_buf);
 686 }
 687
 688 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 689 {
 690     AspeedSoCState *soc = &bmc->soc;
 691     I2CSlave *i2c_mux;
 692
 693     /* The at24c256 */
 694     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 695
 696     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 697     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 698                      0x48);
 699     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 700                      0x49);
 701
 702     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 703                      "pca9546", 0x70);
 704     /* It expects a TMP112 but a TMP105 is compatible */
 705     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 706                      0x4a);
 707
 708     /* It expects a ds3232 but a ds1338 is good enough */
 709     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 710
 711     /* It expects a pca9555 but a pca9552 is compatible */
 712     create_pca9552(soc, 8, 0x30);
 713 }
 714
 715 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 716 {
 717     AspeedSoCState *soc = &bmc->soc;
 718     I2CSlave *i2c_mux;
 719
 720     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 721
 722     create_pca9552(soc, 3, 0x61);
 723
 724     /* The rainier expects a TMP275 but a TMP105 is compatible */
 725     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 726                      0x48);
 727     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 728                      0x49);
 729     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 730                      0x4a);
 731     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 732                                       "pca9546", 0x70);
 733     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 734     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 735     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 736     create_pca9552(soc, 4, 0x60);
 737
 738     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 739                      0x48);
 740     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 741                      0x49);
 742     create_pca9552(soc, 5, 0x60);
 743     create_pca9552(soc, 5, 0x61);
 744     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 745                                       "pca9546", 0x70);
 746     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 747     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 748
 749     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 750                      0x48);
 751     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 752                      0x4a);
 753     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 754                      0x4b);
 755     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 756                                       "pca9546", 0x70);
 757     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 758     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 759     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 760     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 761
 762     create_pca9552(soc, 7, 0x30);
 763     create_pca9552(soc, 7, 0x31);
 764     create_pca9552(soc, 7, 0x32);
 765     create_pca9552(soc, 7, 0x33);
 766     create_pca9552(soc, 7, 0x60);
 767     create_pca9552(soc, 7, 0x61);
 768     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 769     /* Bus 7: TODO si7021-a20@20 */
 770     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 771                      0x48);
 772     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 773     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 774     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 775
 776     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 777                      0x48);
 778     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 779                      0x4a);
 780     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
 781     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 782     create_pca9552(soc, 8, 0x60);
 783     create_pca9552(soc, 8, 0x61);
 784     /* Bus 8: ucd90320@11 */
 785     /* Bus 8: ucd90320@b */
 786     /* Bus 8: ucd90320@c */
 787
 788     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 789     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 790     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 791
 792     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 793     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 794     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 795
 796     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 797                      0x48);
 798     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 799                      0x49);
 800     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 801                                       "pca9546", 0x70);
 802     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 803     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 804     create_pca9552(soc, 11, 0x60);
 805
 806
 807     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 808     create_pca9552(soc, 13, 0x60);
 809
 810     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 811     create_pca9552(soc, 14, 0x60);
 812
 813     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 814     create_pca9552(soc, 15, 0x60);
 815 }
 816
 817 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 818                                  I2CBus **channels)
 819 {
 820     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 821     for (int i = 0; i < 8; i++) {
 822         channels[i] = pca954x_i2c_get_bus(mux, i);
 823     }
 824 }
 825
 826 #define TYPE_LM75 TYPE_TMP105
 827 #define TYPE_TMP75 TYPE_TMP105
 828 #define TYPE_TMP422 "tmp422"
 829
 830 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 831 {
 832     AspeedSoCState *soc = &bmc->soc;
 833     I2CBus *i2c[144] = {};
 834
 835     for (int i = 0; i < 16; i++) {
 836         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 837     }
 838     I2CBus *i2c180 = i2c[2];
 839     I2CBus *i2c480 = i2c[8];
 840     I2CBus *i2c600 = i2c[11];
 841
 842     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 843     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 844     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 845     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 846     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 847     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 848     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 849     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 850     for (int i = 0; i < 8; i++) {
 851         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 852     }
 853
 854     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 855     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 856
 857     /*
 858      * EEPROM 24c64 size is 64Kbits or 8 Kbytes
 859      *        24c02 size is 2Kbits or 256 bytes
 860      */
 861     at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
 862     at24c_eeprom_init(i2c[20], 0x50, 256);
 863     at24c_eeprom_init(i2c[22], 0x52, 256);
 864
 865     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 866     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 867     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 868     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 869
 870     at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
 871     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 872
 873     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 874     at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
 875     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 876     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 877
 878     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 879     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 880
 881     at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
 882     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 883     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 884     at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
 885     at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
 886     at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
 887     at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
 888
 889     at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
 890     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 891     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 892     at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
 893     at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
 894     at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
 895     at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
 896     at24c_eeprom_init(i2c[28], 0x50, 256);
 897
 898     for (int i = 0; i < 8; i++) {
 899         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 900         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 901         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 902         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 903     }
 904 }
 905
 906 #define TYPE_TMP421 "tmp421"
 907
 908 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 909 {
 910     AspeedSoCState *soc = &bmc->soc;
 911     I2CBus *i2c[13] = {};
 912     for (int i = 0; i < 13; i++) {
 913         if ((i == 8) || (i == 11)) {
 914             continue;
 915         }
 916         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 917     }
 918
 919     /* Bus 0 - 5 all have the same config. */
 920     for (int i = 0; i < 6; i++) {
 921         /* Missing model: ti,ina230 @ 0x45 */
 922         /* Missing model: mps,mp5023 @ 0x40 */
 923         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 924         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 925         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 926         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 927         /* Missing model: fsc,fusb302 @ 0x22 */
 928     }
 929
 930     /* Bus 6 */
 931     at24c_eeprom_init(i2c[6], 0x56, 65536);
 932     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 933     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 934
 935
 936     /* Bus 7 */
 937     at24c_eeprom_init(i2c[7], 0x54, 65536);
 938
 939     /* Bus 9 */
 940     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 941
 942     /* Bus 10 */
 943     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 944     /* Missing model: ti,hdc1080 @ 0x40 */
 945     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 946
 947     /* Bus 12 */
 948     /* Missing model: adi,adm1278 @ 0x11 */
 949     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 950     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 951     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 952 }
 953
 954 static void fby35_i2c_init(AspeedMachineState *bmc)
 955 {
 956     AspeedSoCState *soc = &bmc->soc;
 957     I2CBus *i2c[16];
 958
 959     for (int i = 0; i < 16; i++) {
 960         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 961     }
 962
 963     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 964     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 965     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 966     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 967     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 968     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 969
 970     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
 971     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
 972     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
 973                           fby35_nic_fruid_len);
 974     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
 975                           fby35_bb_fruid_len);
 976     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
 977                           fby35_bmc_fruid_len);
 978
 979     /*
 980      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
 981      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
 982      * each.
 983      */
 984 }
 985
 986 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 987 {
 988     AspeedSoCState *soc = &bmc->soc;
 989
 990     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 991 }
 992
 993 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 994 {
 995     AspeedSoCState *soc = &bmc->soc;
 996     I2CSlave *therm_mux, *cpuvr_mux;
 997
 998     /* Create the generic DC-SCM hardware */
 999     qcom_dc_scm_bmc_i2c_init(bmc);
1000
1001     /* Now create the Firework specific hardware */
1002
1003     /* I2C7 CPUVR MUX */
1004     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1005                                         "pca9546", 0x70);
1006     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1007     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1008     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1009     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1010
1011     /* I2C8 Thermal Diodes*/
1012     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1013                                         "pca9548", 0x70);
1014     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1015     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1016     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1017     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1018     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1019
1020     /* I2C9 Fan Controller (MAX31785) */
1021     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1022     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1023 }
1024
1025 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1026 {
1027     return ASPEED_MACHINE(obj)->mmio_exec;
1028 }
1029
1030 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1031 {
1032     ASPEED_MACHINE(obj)->mmio_exec = value;
1033 }
1034
1035 static void aspeed_machine_instance_init(Object *obj)
1036 {
1037     ASPEED_MACHINE(obj)->mmio_exec = false;
1038 }
1039
1040 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1041 {
1042     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1043     return g_strdup(bmc->fmc_model);
1044 }
1045
1046 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1047 {
1048     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1049
1050     g_free(bmc->fmc_model);
1051     bmc->fmc_model = g_strdup(value);
1052 }
1053
1054 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1055 {
1056     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1057     return g_strdup(bmc->spi_model);
1058 }
1059
1060 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1061 {
1062     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1063
1064     g_free(bmc->spi_model);
1065     bmc->spi_model = g_strdup(value);
1066 }
1067
1068 static void aspeed_machine_class_props_init(ObjectClass *oc)
1069 {
1070     object_class_property_add_bool(oc, "execute-in-place",
1071                                    aspeed_get_mmio_exec,
1072                                    aspeed_set_mmio_exec);
1073     object_class_property_set_description(oc, "execute-in-place",
1074                            "boot directly from CE0 flash device");
1075
1076     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1077                                    aspeed_set_fmc_model);
1078     object_class_property_set_description(oc, "fmc-model",
1079                                           "Change the FMC Flash model");
1080     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1081                                    aspeed_set_spi_model);
1082     object_class_property_set_description(oc, "spi-model",
1083                                           "Change the SPI Flash model");
1084 }
1085
1086 static int aspeed_soc_num_cpus(const char *soc_name)
1087 {
1088    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1089    return sc->num_cpus;
1090 }
1091
1092 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1093 {
1094     MachineClass *mc = MACHINE_CLASS(oc);
1095     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1096
1097     mc->init = aspeed_machine_init;
1098     mc->no_floppy = 1;
1099     mc->no_cdrom = 1;
1100     mc->no_parallel = 1;
1101     mc->default_ram_id = "ram";
1102     amc->macs_mask = ASPEED_MAC0_ON;
1103     amc->uart_default = ASPEED_DEV_UART5;
1104
1105     aspeed_machine_class_props_init(oc);
1106 }
1107
1108 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1109 {
1110     MachineClass *mc = MACHINE_CLASS(oc);
1111     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1112
1113     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1114     amc->soc_name  = "ast2400-a1";
1115     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1116     amc->fmc_model = "n25q256a";
1117     amc->spi_model = "mx25l25635f";
1118     amc->num_cs    = 1;
1119     amc->i2c_init  = palmetto_bmc_i2c_init;
1120     mc->default_ram_size       = 256 * MiB;
1121     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1122         aspeed_soc_num_cpus(amc->soc_name);
1123 };
1124
1125 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1126 {
1127     MachineClass *mc = MACHINE_CLASS(oc);
1128     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1129
1130     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1131     amc->soc_name  = "ast2400-a1";
1132     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1133     amc->fmc_model = "n25q256a";
1134     amc->spi_model = "mx25l25635e";
1135     amc->num_cs    = 1;
1136     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1137     mc->default_ram_size       = 128 * MiB;
1138     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1139         aspeed_soc_num_cpus(amc->soc_name);
1140 }
1141
1142 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1143                                                         void *data)
1144 {
1145     MachineClass *mc = MACHINE_CLASS(oc);
1146     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1147
1148     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1149     amc->soc_name  = "ast2400-a1";
1150     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1151     amc->fmc_model = "mx25l25635e";
1152     amc->spi_model = "mx25l25635e";
1153     amc->num_cs    = 1;
1154     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1155     amc->i2c_init  = palmetto_bmc_i2c_init;
1156     mc->default_ram_size = 256 * MiB;
1157 }
1158
1159 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1160                                                             void *data)
1161 {
1162     MachineClass *mc = MACHINE_CLASS(oc);
1163     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1164
1165     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1166     amc->soc_name  = "ast2500-a1";
1167     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1168     amc->fmc_model = "mx25l25635e";
1169     amc->spi_model = "mx25l25635e";
1170     amc->num_cs    = 1;
1171     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1172     amc->i2c_init  = palmetto_bmc_i2c_init;
1173     mc->default_ram_size = 512 * MiB;
1174     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1175         aspeed_soc_num_cpus(amc->soc_name);
1176 }
1177
1178 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1179 {
1180     MachineClass *mc = MACHINE_CLASS(oc);
1181     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1182
1183     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1184     amc->soc_name  = "ast2500-a1";
1185     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1186     amc->fmc_model = "mx25l25635e";
1187     amc->spi_model = "mx25l25635f";
1188     amc->num_cs    = 1;
1189     amc->i2c_init  = ast2500_evb_i2c_init;
1190     mc->default_ram_size       = 512 * MiB;
1191     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1192         aspeed_soc_num_cpus(amc->soc_name);
1193 };
1194
1195 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1196 {
1197     MachineClass *mc = MACHINE_CLASS(oc);
1198     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1199
1200     mc->desc       = "Facebook YosemiteV2 BMC (ARM1176)";
1201     amc->soc_name  = "ast2500-a1";
1202     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1203     amc->hw_strap2 = 0;
1204     amc->fmc_model = "n25q256a";
1205     amc->spi_model = "mx25l25635e";
1206     amc->num_cs    = 2;
1207     amc->i2c_init  = yosemitev2_bmc_i2c_init;
1208     mc->default_ram_size       = 512 * MiB;
1209     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1210         aspeed_soc_num_cpus(amc->soc_name);
1211 };
1212
1213 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1214 {
1215     MachineClass *mc = MACHINE_CLASS(oc);
1216     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1217
1218     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1219     amc->soc_name  = "ast2500-a1";
1220     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1221     amc->fmc_model = "n25q256a";
1222     amc->spi_model = "mx66l1g45g";
1223     amc->num_cs    = 2;
1224     amc->i2c_init  = romulus_bmc_i2c_init;
1225     mc->default_ram_size       = 512 * MiB;
1226     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1227         aspeed_soc_num_cpus(amc->soc_name);
1228 };
1229
1230 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1231 {
1232     MachineClass *mc = MACHINE_CLASS(oc);
1233     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1234
1235     mc->desc       = "Facebook Tiogapass BMC (ARM1176)";
1236     amc->soc_name  = "ast2500-a1";
1237     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1238     amc->hw_strap2 = 0;
1239     amc->fmc_model = "n25q256a";
1240     amc->spi_model = "mx25l25635e";
1241     amc->num_cs    = 2;
1242     amc->i2c_init  = tiogapass_bmc_i2c_init;
1243     mc->default_ram_size       = 1 * GiB;
1244     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1245         aspeed_soc_num_cpus(amc->soc_name);
1246         aspeed_soc_num_cpus(amc->soc_name);
1247 };
1248
1249 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1250 {
1251     MachineClass *mc = MACHINE_CLASS(oc);
1252     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1253
1254     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1255     amc->soc_name  = "ast2500-a1";
1256     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1257     amc->fmc_model = "mx66l1g45g";
1258     amc->spi_model = "mx66l1g45g";
1259     amc->num_cs    = 2;
1260     amc->i2c_init  = sonorapass_bmc_i2c_init;
1261     mc->default_ram_size       = 512 * MiB;
1262     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1263         aspeed_soc_num_cpus(amc->soc_name);
1264 };
1265
1266 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1267 {
1268     MachineClass *mc = MACHINE_CLASS(oc);
1269     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1270
1271     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1272     amc->soc_name  = "ast2500-a1";
1273     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1274     amc->fmc_model = "mx25l25635f";
1275     amc->spi_model = "mx66l1g45g";
1276     amc->num_cs    = 2;
1277     amc->i2c_init  = witherspoon_bmc_i2c_init;
1278     mc->default_ram_size = 512 * MiB;
1279     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1280         aspeed_soc_num_cpus(amc->soc_name);
1281 };
1282
1283 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1284 {
1285     MachineClass *mc = MACHINE_CLASS(oc);
1286     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1287
1288     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1289     amc->soc_name  = "ast2600-a3";
1290     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1291     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1292     amc->fmc_model = "mx66u51235f";
1293     amc->spi_model = "mx66u51235f";
1294     amc->num_cs    = 1;
1295     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1296                      ASPEED_MAC3_ON;
1297     amc->i2c_init  = ast2600_evb_i2c_init;
1298     mc->default_ram_size = 1 * GiB;
1299     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1300         aspeed_soc_num_cpus(amc->soc_name);
1301 };
1302
1303 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1304 {
1305     MachineClass *mc = MACHINE_CLASS(oc);
1306     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1307
1308     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1309     amc->soc_name  = "ast2600-a3";
1310     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1311     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1312     amc->fmc_model = "mx66l1g45g";
1313     amc->spi_model = "mx66l1g45g";
1314     amc->num_cs    = 2;
1315     amc->macs_mask  = ASPEED_MAC2_ON;
1316     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1317     mc->default_ram_size = 1 * GiB;
1318     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1319         aspeed_soc_num_cpus(amc->soc_name);
1320 };
1321
1322 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1323 {
1324     MachineClass *mc = MACHINE_CLASS(oc);
1325     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1326
1327     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1328     amc->soc_name  = "ast2500-a1";
1329     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1330     amc->fmc_model = "n25q512a";
1331     amc->spi_model = "mx25l25635e";
1332     amc->num_cs    = 2;
1333     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1334     amc->i2c_init  = g220a_bmc_i2c_init;
1335     mc->default_ram_size = 1024 * MiB;
1336     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1337         aspeed_soc_num_cpus(amc->soc_name);
1338 };
1339
1340 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1341 {
1342     MachineClass *mc = MACHINE_CLASS(oc);
1343     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1344
1345     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1346     amc->soc_name  = "ast2500-a1";
1347     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1348     amc->fmc_model = "n25q512a";
1349     amc->spi_model = "mx25l25635e";
1350     amc->num_cs    = 2;
1351     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1352     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1353     mc->default_ram_size = 512 * MiB;
1354     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1355         aspeed_soc_num_cpus(amc->soc_name);
1356 };
1357
1358 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1359 {
1360     MachineClass *mc = MACHINE_CLASS(oc);
1361     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1362
1363     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1364     amc->soc_name  = "ast2600-a3";
1365     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1366     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1367     amc->fmc_model = "mx66l1g45g";
1368     amc->spi_model = "mx66l1g45g";
1369     amc->num_cs    = 2;
1370     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1371     amc->i2c_init  = rainier_bmc_i2c_init;
1372     mc->default_ram_size = 1 * GiB;
1373     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1374         aspeed_soc_num_cpus(amc->soc_name);
1375 };
1376
1377 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1378 #if HOST_LONG_BITS == 32
1379 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1380 #else
1381 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1382 #endif
1383
1384 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1385 {
1386     MachineClass *mc = MACHINE_CLASS(oc);
1387     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1388
1389     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1390     amc->soc_name = "ast2600-a3";
1391     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1392     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1393     amc->fmc_model = "mx66l1g45g";
1394     amc->spi_model = "mx66l1g45g";
1395     amc->num_cs = 2;
1396     amc->macs_mask = ASPEED_MAC3_ON;
1397     amc->i2c_init = fuji_bmc_i2c_init;
1398     amc->uart_default = ASPEED_DEV_UART1;
1399     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1400     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1401         aspeed_soc_num_cpus(amc->soc_name);
1402 };
1403
1404 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1405 #if HOST_LONG_BITS == 32
1406 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1407 #else
1408 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1409 #endif
1410
1411 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1412 {
1413     MachineClass *mc = MACHINE_CLASS(oc);
1414     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1415
1416     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1417     amc->soc_name  = "ast2600-a3";
1418     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1419     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1420     amc->fmc_model = "w25q01jvq";
1421     amc->spi_model = NULL;
1422     amc->num_cs    = 2;
1423     amc->macs_mask = ASPEED_MAC2_ON;
1424     amc->i2c_init  = bletchley_bmc_i2c_init;
1425     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1426     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1427         aspeed_soc_num_cpus(amc->soc_name);
1428 }
1429
1430 static void fby35_reset(MachineState *state, ShutdownCause reason)
1431 {
1432     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1433     AspeedGPIOState *gpio = &bmc->soc.gpio;
1434
1435     qemu_devices_reset(reason);
1436
1437     /* Board ID: 7 (Class-1, 4 slots) */
1438     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1439     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1440     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1441     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1442
1443     /* Slot presence pins, inverse polarity. (False means present) */
1444     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1445     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1446     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1447     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1448
1449     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1450     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1451     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1452     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1453     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1454 }
1455
1456 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1457 {
1458     MachineClass *mc = MACHINE_CLASS(oc);
1459     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1460
1461     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1462     mc->reset      = fby35_reset;
1463     amc->fmc_model = "mx66l1g45g";
1464     amc->num_cs    = 2;
1465     amc->macs_mask = ASPEED_MAC3_ON;
1466     amc->i2c_init  = fby35_i2c_init;
1467     /* FIXME: Replace this macro with something more general */
1468     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1469 }
1470
1471 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1472 /* Main SYSCLK frequency in Hz (200MHz) */
1473 #define SYSCLK_FRQ 200000000ULL
1474
1475 static void aspeed_minibmc_machine_init(MachineState *machine)
1476 {
1477     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1478     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1479     Clock *sysclk;
1480
1481     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1482     clock_set_hz(sysclk, SYSCLK_FRQ);
1483
1484     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1485     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1486
1487     object_property_set_link(OBJECT(&bmc->soc), "memory",
1488                              OBJECT(get_system_memory()), &error_abort);
1489     connect_serial_hds_to_uarts(bmc);
1490     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1491
1492     aspeed_board_init_flashes(&bmc->soc.fmc,
1493                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1494                               amc->num_cs,
1495                               0);
1496
1497     aspeed_board_init_flashes(&bmc->soc.spi[0],
1498                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1499                               amc->num_cs, amc->num_cs);
1500
1501     aspeed_board_init_flashes(&bmc->soc.spi[1],
1502                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1503                               amc->num_cs, (amc->num_cs * 2));
1504
1505     if (amc->i2c_init) {
1506         amc->i2c_init(bmc);
1507     }
1508
1509     armv7m_load_kernel(ARM_CPU(first_cpu),
1510                        machine->kernel_filename,
1511                        0,
1512                        AST1030_INTERNAL_FLASH_SIZE);
1513 }
1514
1515 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1516 {
1517     AspeedSoCState *soc = &bmc->soc;
1518
1519     /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1520     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1521     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1522
1523     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1524     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1525 }
1526
1527 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1528                                                           void *data)
1529 {
1530     MachineClass *mc = MACHINE_CLASS(oc);
1531     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1532
1533     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1534     amc->soc_name = "ast1030-a1";
1535     amc->hw_strap1 = 0;
1536     amc->hw_strap2 = 0;
1537     mc->init = aspeed_minibmc_machine_init;
1538     amc->i2c_init = ast1030_evb_i2c_init;
1539     mc->default_ram_size = 0;
1540     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1541     amc->fmc_model = "sst25vf032b";
1542     amc->spi_model = "sst25vf032b";
1543     amc->num_cs = 2;
1544     amc->macs_mask = 0;
1545 }
1546
1547 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1548                                                      void *data)
1549 {
1550     MachineClass *mc = MACHINE_CLASS(oc);
1551     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1552
1553     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1554     amc->soc_name  = "ast2600-a3";
1555     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1556     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1557     amc->fmc_model = "n25q512a";
1558     amc->spi_model = "n25q512a";
1559     amc->num_cs    = 2;
1560     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1561     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1562     mc->default_ram_size = 1 * GiB;
1563     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1564         aspeed_soc_num_cpus(amc->soc_name);
1565 };
1566
1567 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1568                                                     void *data)
1569 {
1570     MachineClass *mc = MACHINE_CLASS(oc);
1571     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1572
1573     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1574     amc->soc_name  = "ast2600-a3";
1575     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1576     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1577     amc->fmc_model = "n25q512a";
1578     amc->spi_model = "n25q512a";
1579     amc->num_cs    = 2;
1580     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1581     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1582     mc->default_ram_size = 1 * GiB;
1583     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1584         aspeed_soc_num_cpus(amc->soc_name);
1585 };
1586
1587 static const TypeInfo aspeed_machine_types[] = {
1588     {
1589         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1590         .parent        = TYPE_ASPEED_MACHINE,
1591         .class_init    = aspeed_machine_palmetto_class_init,
1592     }, {
1593         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1594         .parent        = TYPE_ASPEED_MACHINE,
1595         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1596     }, {
1597         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1598         .parent        = TYPE_ASPEED_MACHINE,
1599         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1600     }, {
1601         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1602         .parent        = TYPE_ASPEED_MACHINE,
1603         .class_init    = aspeed_machine_ast2500_evb_class_init,
1604     }, {
1605         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1606         .parent        = TYPE_ASPEED_MACHINE,
1607         .class_init    = aspeed_machine_romulus_class_init,
1608     }, {
1609         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1610         .parent        = TYPE_ASPEED_MACHINE,
1611         .class_init    = aspeed_machine_sonorapass_class_init,
1612     }, {
1613         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1614         .parent        = TYPE_ASPEED_MACHINE,
1615         .class_init    = aspeed_machine_witherspoon_class_init,
1616     }, {
1617         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1618         .parent        = TYPE_ASPEED_MACHINE,
1619         .class_init    = aspeed_machine_ast2600_evb_class_init,
1620     }, {
1621         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1622         .parent        = TYPE_ASPEED_MACHINE,
1623         .class_init    = aspeed_machine_yosemitev2_class_init,
1624     }, {
1625         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1626         .parent        = TYPE_ASPEED_MACHINE,
1627         .class_init    = aspeed_machine_tacoma_class_init,
1628     }, {
1629         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
1630         .parent        = TYPE_ASPEED_MACHINE,
1631         .class_init    = aspeed_machine_tiogapass_class_init,
1632     }, {
1633         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1634         .parent        = TYPE_ASPEED_MACHINE,
1635         .class_init    = aspeed_machine_g220a_class_init,
1636     }, {
1637         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1638         .parent        = TYPE_ASPEED_MACHINE,
1639         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1640     }, {
1641         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1642         .parent        = TYPE_ASPEED_MACHINE,
1643         .class_init    = aspeed_machine_qcom_firework_class_init,
1644     }, {
1645         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1646         .parent        = TYPE_ASPEED_MACHINE,
1647         .class_init    = aspeed_machine_fp5280g2_class_init,
1648     }, {
1649         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1650         .parent        = TYPE_ASPEED_MACHINE,
1651         .class_init    = aspeed_machine_quanta_q71l_class_init,
1652     }, {
1653         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1654         .parent        = TYPE_ASPEED_MACHINE,
1655         .class_init    = aspeed_machine_rainier_class_init,
1656     }, {
1657         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1658         .parent        = TYPE_ASPEED_MACHINE,
1659         .class_init    = aspeed_machine_fuji_class_init,
1660     }, {
1661         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1662         .parent        = TYPE_ASPEED_MACHINE,
1663         .class_init    = aspeed_machine_bletchley_class_init,
1664     }, {
1665         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1666         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1667         .class_init    = aspeed_machine_fby35_class_init,
1668     }, {
1669         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1670         .parent         = TYPE_ASPEED_MACHINE,
1671         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1672     }, {
1673         .name          = TYPE_ASPEED_MACHINE,
1674         .parent        = TYPE_MACHINE,
1675         .instance_size = sizeof(AspeedMachineState),
1676         .instance_init = aspeed_machine_instance_init,
1677         .class_size    = sizeof(AspeedMachineClass),
1678         .class_init    = aspeed_machine_class_init,
1679         .abstract      = true,
1680     }
1681 };
1682
1683 DEFINE_TYPES(aspeed_machine_types)