hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/arm/aspeed_eeprom.h"
  18 #include "hw/i2c/i2c_mux_pca954x.h"
  19 #include "hw/i2c/smbus_eeprom.h"
  20 #include "hw/misc/pca9552.h"
  21 #include "hw/nvram/eeprom_at24c.h"
  22 #include "hw/sensor/tmp105.h"
  23 #include "hw/misc/led.h"
  24 #include "hw/qdev-properties.h"
  25 #include "sysemu/block-backend.h"
  26 #include "sysemu/reset.h"
  27 #include "hw/loader.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/units.h"
  30 #include "hw/qdev-clock.h"
  31 #include "sysemu/sysemu.h"
  32
  33 static struct arm_boot_info aspeed_board_binfo = {
  34     .board_id = -1, /* device-tree-only board */
  35 };
  36
  37 struct AspeedMachineState {
  38     /* Private */
  39     MachineState parent_obj;
  40     /* Public */
  41
  42     AspeedSoCState soc;
  43     bool mmio_exec;
  44     char *fmc_model;
  45     char *spi_model;
  46 };
  47
  48 /* Palmetto hardware value: 0x120CE416 */
  49 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  50         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  51         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  52         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  53         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  54         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  55         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  56         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  57         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  58         SCU_HW_STRAP_SPI_WIDTH |                                        \
  59         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  60         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  61
  62 /* TODO: Find the actual hardware value */
  63 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  64         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  65         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  66         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  67         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  68         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  69         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  70         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  71         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  72         SCU_HW_STRAP_SPI_WIDTH |                                        \
  73         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  74         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  75
  76 /* TODO: Find the actual hardware value */
  77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  78         AST2500_HW_STRAP1_DEFAULTS |                                    \
  79         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  80         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  81         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  82         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  83         SCU_HW_STRAP_SPI_WIDTH |                                        \
  84         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  85
  86 /* AST2500 evb hardware value: 0xF100C2E6 */
  87 #define AST2500_EVB_HW_STRAP1 ((                                        \
  88         AST2500_HW_STRAP1_DEFAULTS |                                    \
  89         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  90         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  91         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  92         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  93         SCU_HW_STRAP_MAC1_RGMII |                                       \
  94         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  95         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  96
  97 /* Romulus hardware value: 0xF10AD206 */
  98 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  99         AST2500_HW_STRAP1_DEFAULTS |                                    \
 100         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 101         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 102         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 103         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 104         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 105         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 106
 107 /* Sonorapass hardware value: 0xF100D216 */
 108 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 109         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 110         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 111         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 112         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 113         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 114         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 115         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 116         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 117         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 118         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 119         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 120         SCU_AST2500_HW_STRAP_RESERVED1)
 121
 122 #define G220A_BMC_HW_STRAP1 (                                      \
 123         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 124         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 125         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 126         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 127         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 128         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 129         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 130         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 131         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 132         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 133         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 134         SCU_AST2500_HW_STRAP_RESERVED1)
 135
 136 /* FP5280G2 hardware value: 0XF100D286 */
 137 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 138         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 139         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 140         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 141         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 142         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 143         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 144         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 145         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 146         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 147         SCU_HW_STRAP_MAC1_RGMII |                                       \
 148         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 149         SCU_AST2500_HW_STRAP_RESERVED1)
 150
 151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 153
 154 /* Quanta-Q71l hardware value */
 155 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 156         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 157         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 158         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 159         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 160         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 161         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 162         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 163         SCU_HW_STRAP_SPI_WIDTH |                                        \
 164         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 165         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 166
 167 /* AST2600 evb hardware value */
 168 #define AST2600_EVB_HW_STRAP1 0x000000C0
 169 #define AST2600_EVB_HW_STRAP2 0x00000003
 170
 171 /* Tacoma hardware value */
 172 #define TACOMA_BMC_HW_STRAP1  0x00000000
 173 #define TACOMA_BMC_HW_STRAP2  0x00000040
 174
 175 /* Rainier hardware value: (QEMU prototype) */
 176 #define RAINIER_BMC_HW_STRAP1 0x00422016
 177 #define RAINIER_BMC_HW_STRAP2 0x80000848
 178
 179 /* Fuji hardware value */
 180 #define FUJI_BMC_HW_STRAP1    0x00000000
 181 #define FUJI_BMC_HW_STRAP2    0x00000000
 182
 183 /* Bletchley hardware value */
 184 /* TODO: Leave same as EVB for now. */
 185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 187
 188 /* Qualcomm DC-SCM hardware value */
 189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 191
 192 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 193 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 194 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 195 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 196 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 197 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 198 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 199
 200 static void aspeed_write_smpboot(ARMCPU *cpu,
 201                                  const struct arm_boot_info *info)
 202 {
 203     static const uint32_t poll_mailbox_ready[] = {
 204         /*
 205          * r2 = per-cpu go sign value
 206          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 207          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 208          */
 209         0xee100fb0,  /* mrc     p15, 0, r0, c0, c0, 5 */
 210         0xe21000ff,  /* ands    r0, r0, #255          */
 211         0xe59f201c,  /* ldr     r2, [pc, #28]         */
 212         0xe1822000,  /* orr     r2, r2, r0            */
 213
 214         0xe59f1018,  /* ldr     r1, [pc, #24]         */
 215         0xe59f0018,  /* ldr     r0, [pc, #24]         */
 216
 217         0xe320f002,  /* wfe                           */
 218         0xe5904000,  /* ldr     r4, [r0]              */
 219         0xe1520004,  /* cmp     r2, r4                */
 220         0x1afffffb,  /* bne     <wfe>                 */
 221         0xe591f000,  /* ldr     pc, [r1]              */
 222         AST_SMP_MBOX_GOSIGN,
 223         AST_SMP_MBOX_FIELD_ENTRY,
 224         AST_SMP_MBOX_FIELD_GOSIGN,
 225     };
 226
 227     rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
 228                        sizeof(poll_mailbox_ready),
 229                        info->smp_loader_start);
 230 }
 231
 232 static void aspeed_reset_secondary(ARMCPU *cpu,
 233                                    const struct arm_boot_info *info)
 234 {
 235     AddressSpace *as = arm_boot_address_space(cpu, info);
 236     CPUState *cs = CPU(cpu);
 237
 238     /* info->smp_bootreg_addr */
 239     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 240                                MEMTXATTRS_UNSPECIFIED, NULL);
 241     cpu_set_pc(cs, info->smp_loader_start);
 242 }
 243
 244 #define FIRMWARE_ADDR 0x0
 245
 246 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
 247                            Error **errp)
 248 {
 249     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 250     g_autofree void *storage = NULL;
 251     int64_t size;
 252
 253     /* The block backend size should have already been 'validated' by
 254      * the creation of the m25p80 object.
 255      */
 256     size = blk_getlength(blk);
 257     if (size <= 0) {
 258         error_setg(errp, "failed to get flash size");
 259         return;
 260     }
 261
 262     if (rom_size > size) {
 263         rom_size = size;
 264     }
 265
 266     storage = g_malloc0(rom_size);
 267     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 268         error_setg(errp, "failed to read the initial flash content");
 269         return;
 270     }
 271
 272     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 273 }
 274
 275 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 276                                       unsigned int count, int unit0)
 277 {
 278     int i;
 279
 280     if (!flashtype) {
 281         return;
 282     }
 283
 284     for (i = 0; i < count; ++i) {
 285         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 286         qemu_irq cs_line;
 287         DeviceState *dev;
 288
 289         dev = qdev_new(flashtype);
 290         if (dinfo) {
 291             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 292         }
 293         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 294
 295         cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 296         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
 297     }
 298 }
 299
 300 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 301 {
 302         DeviceState *card;
 303
 304         if (!dinfo) {
 305             return;
 306         }
 307         card = qdev_new(TYPE_SD_CARD);
 308         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 309                                 &error_fatal);
 310         qdev_realize_and_unref(card,
 311                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 312                                &error_fatal);
 313 }
 314
 315 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 316 {
 317     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 318     AspeedSoCState *s = &bmc->soc;
 319     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 320
 321     aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
 322     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 323         if (uart == amc->uart_default) {
 324             continue;
 325         }
 326         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 327     }
 328 }
 329
 330 static void aspeed_machine_init(MachineState *machine)
 331 {
 332     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 333     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 334     AspeedSoCClass *sc;
 335     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
 336     int i;
 337     NICInfo *nd = &nd_table[0];
 338
 339     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 340
 341     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 342
 343     /*
 344      * This will error out if the RAM size is not supported by the
 345      * memory controller of the SoC.
 346      */
 347     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 348                              &error_fatal);
 349
 350     for (i = 0; i < sc->macs_num; i++) {
 351         if ((amc->macs_mask & (1 << i)) && nd->used) {
 352             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 353             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 354             nd++;
 355         }
 356     }
 357
 358     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 359                             &error_abort);
 360     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 361                             &error_abort);
 362     object_property_set_link(OBJECT(&bmc->soc), "memory",
 363                              OBJECT(get_system_memory()), &error_abort);
 364     object_property_set_link(OBJECT(&bmc->soc), "dram",
 365                              OBJECT(machine->ram), &error_abort);
 366     if (machine->kernel_filename) {
 367         /*
 368          * When booting with a -kernel command line there is no u-boot
 369          * that runs to unlock the SCU. In this case set the default to
 370          * be unlocked as the kernel expects
 371          */
 372         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 373                                 ASPEED_SCU_PROT_KEY, &error_abort);
 374     }
 375     connect_serial_hds_to_uarts(bmc);
 376     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 377
 378     aspeed_board_init_flashes(&bmc->soc.fmc,
 379                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 380                               amc->num_cs, 0);
 381     aspeed_board_init_flashes(&bmc->soc.spi[0],
 382                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 383                               1, amc->num_cs);
 384
 385     /* Install first FMC flash content as a boot rom. */
 386     if (drive0) {
 387         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
 388         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 389         uint64_t size = memory_region_size(&fl->mmio);
 390
 391         /*
 392          * create a ROM region using the default mapping window size of
 393          * the flash module. The window size is 64MB for the AST2400
 394          * SoC and 128MB for the AST2500 SoC, which is twice as big as
 395          * needed by the flash modules of the Aspeed machines.
 396          */
 397         if (ASPEED_MACHINE(machine)->mmio_exec) {
 398             memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
 399                                      &fl->mmio, 0, size);
 400             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 401                                         boot_rom);
 402         } else {
 403             memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
 404                                    size, &error_abort);
 405             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 406                                         boot_rom);
 407             write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
 408         }
 409     }
 410
 411     if (machine->kernel_filename && sc->num_cpus > 1) {
 412         /* With no u-boot we must set up a boot stub for the secondary CPU */
 413         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 414         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 415                                0x80, &error_abort);
 416         memory_region_add_subregion(get_system_memory(),
 417                                     AST_SMP_MAILBOX_BASE, smpboot);
 418
 419         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 420         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 421         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 422     }
 423
 424     aspeed_board_binfo.ram_size = machine->ram_size;
 425     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 426
 427     if (amc->i2c_init) {
 428         amc->i2c_init(bmc);
 429     }
 430
 431     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 432         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 433                            drive_get(IF_SD, 0, i));
 434     }
 435
 436     if (bmc->soc.emmc.num_slots) {
 437         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 438                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 439     }
 440
 441     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 442 }
 443
 444 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 445 {
 446     AspeedSoCState *soc = &bmc->soc;
 447     DeviceState *dev;
 448     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 449
 450     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 451      * enough to provide basic RTC features. Alarms will be missing */
 452     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 453
 454     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 455                           eeprom_buf);
 456
 457     /* add a TMP423 temperature sensor */
 458     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 459                                          "tmp423", 0x4c));
 460     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 461     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 462     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 463     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 464 }
 465
 466 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 467 {
 468     AspeedSoCState *soc = &bmc->soc;
 469
 470     /*
 471      * The quanta-q71l platform expects tmp75s which are compatible with
 472      * tmp105s.
 473      */
 474     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 475     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 476     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 477
 478     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 479     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 480     /* TODO: Add Memory Riser i2c mux and eeproms. */
 481
 482     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 483     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 484
 485     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 486
 487     /* i2c-7 */
 488     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 489     /*        - i2c@0: pmbus@59 */
 490     /*        - i2c@1: pmbus@58 */
 491     /*        - i2c@2: pmbus@58 */
 492     /*        - i2c@3: pmbus@59 */
 493
 494     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 495     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 496 }
 497
 498 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 499 {
 500     AspeedSoCState *soc = &bmc->soc;
 501     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 502
 503     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 504                           eeprom_buf);
 505
 506     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 507     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 508                      TYPE_TMP105, 0x4d);
 509 }
 510
 511 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 512 {
 513     AspeedSoCState *soc = &bmc->soc;
 514     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 515
 516     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 517                           eeprom_buf);
 518
 519     /* LM75 is compatible with TMP105 driver */
 520     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 521                      TYPE_TMP105, 0x4d);
 522 }
 523
 524 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 525 {
 526     AspeedSoCState *soc = &bmc->soc;
 527
 528     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 529      * good enough */
 530     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 531 }
 532
 533 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 534 {
 535     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 536                             TYPE_PCA9552, addr);
 537 }
 538
 539 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 540 {
 541     AspeedSoCState *soc = &bmc->soc;
 542
 543     /* bus 2 : */
 544     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 545     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 546     /* bus 2 : pca9546 @ 0x73 */
 547
 548     /* bus 3 : pca9548 @ 0x70 */
 549
 550     /* bus 4 : */
 551     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 552     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 553                           eeprom4_54);
 554     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 555     create_pca9552(soc, 4, 0x76);
 556     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 557     create_pca9552(soc, 4, 0x77);
 558
 559     /* bus 6 : */
 560     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 561     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 562     /* bus 6 : pca9546 @ 0x73 */
 563
 564     /* bus 8 : */
 565     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 566     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 567                           eeprom8_56);
 568     create_pca9552(soc, 8, 0x60);
 569     create_pca9552(soc, 8, 0x61);
 570     /* bus 8 : adc128d818 @ 0x1d */
 571     /* bus 8 : adc128d818 @ 0x1f */
 572
 573     /*
 574      * bus 13 : pca9548 @ 0x71
 575      *      - channel 3:
 576      *          - tmm421 @ 0x4c
 577      *          - tmp421 @ 0x4e
 578      *          - tmp421 @ 0x4f
 579      */
 580
 581 }
 582
 583 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 584 {
 585     static const struct {
 586         unsigned gpio_id;
 587         LEDColor color;
 588         const char *description;
 589         bool gpio_polarity;
 590     } pca1_leds[] = {
 591         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 592         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 593         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 594     };
 595     AspeedSoCState *soc = &bmc->soc;
 596     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 597     DeviceState *dev;
 598     LEDState *led;
 599
 600     /* Bus 3: TODO bmp280@77 */
 601     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 602     qdev_prop_set_string(dev, "description", "pca1");
 603     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 604                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 605                                 &error_fatal);
 606
 607     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 608         led = led_create_simple(OBJECT(bmc),
 609                                 pca1_leds[i].gpio_polarity,
 610                                 pca1_leds[i].color,
 611                                 pca1_leds[i].description);
 612         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 613                               qdev_get_gpio_in(DEVICE(led), 0));
 614     }
 615     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 616     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 617     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 618     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 619
 620     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 621     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 622                      0x4a);
 623
 624     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 625      * good enough */
 626     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 627
 628     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 629                           eeprom_buf);
 630     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 631     qdev_prop_set_string(dev, "description", "pca0");
 632     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 633                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 634                                 &error_fatal);
 635     /* Bus 11: TODO ucd90160@64 */
 636 }
 637
 638 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 639 {
 640     AspeedSoCState *soc = &bmc->soc;
 641     DeviceState *dev;
 642
 643     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 644                                          "emc1413", 0x4c));
 645     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 646     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 647     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 648
 649     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 650                                          "emc1413", 0x4c));
 651     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 652     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 653     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 654
 655     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 656                                          "emc1413", 0x4c));
 657     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 658     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 659     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 660
 661     static uint8_t eeprom_buf[2 * 1024] = {
 662             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 663             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 664             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 665             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 666             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 667             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 668             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 669     };
 670     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 671                           eeprom_buf);
 672 }
 673
 674 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 675 {
 676     AspeedSoCState *soc = &bmc->soc;
 677     I2CSlave *i2c_mux;
 678
 679     /* The at24c256 */
 680     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 681
 682     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 683     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 684                      0x48);
 685     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 686                      0x49);
 687
 688     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 689                      "pca9546", 0x70);
 690     /* It expects a TMP112 but a TMP105 is compatible */
 691     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 692                      0x4a);
 693
 694     /* It expects a ds3232 but a ds1338 is good enough */
 695     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 696
 697     /* It expects a pca9555 but a pca9552 is compatible */
 698     create_pca9552(soc, 8, 0x30);
 699 }
 700
 701 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 702 {
 703     AspeedSoCState *soc = &bmc->soc;
 704     I2CSlave *i2c_mux;
 705
 706     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 707
 708     create_pca9552(soc, 3, 0x61);
 709
 710     /* The rainier expects a TMP275 but a TMP105 is compatible */
 711     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 712                      0x48);
 713     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 714                      0x49);
 715     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 716                      0x4a);
 717     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 718                                       "pca9546", 0x70);
 719     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 720     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 721     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 722     create_pca9552(soc, 4, 0x60);
 723
 724     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 725                      0x48);
 726     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 727                      0x49);
 728     create_pca9552(soc, 5, 0x60);
 729     create_pca9552(soc, 5, 0x61);
 730     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 731                                       "pca9546", 0x70);
 732     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 733     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 734
 735     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 736                      0x48);
 737     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 738                      0x4a);
 739     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 740                      0x4b);
 741     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 742                                       "pca9546", 0x70);
 743     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 744     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 745     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 746     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 747
 748     create_pca9552(soc, 7, 0x30);
 749     create_pca9552(soc, 7, 0x31);
 750     create_pca9552(soc, 7, 0x32);
 751     create_pca9552(soc, 7, 0x33);
 752     create_pca9552(soc, 7, 0x60);
 753     create_pca9552(soc, 7, 0x61);
 754     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 755     /* Bus 7: TODO si7021-a20@20 */
 756     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 757                      0x48);
 758     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 759     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 760     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 761
 762     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 763                      0x48);
 764     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 765                      0x4a);
 766     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
 767     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 768     create_pca9552(soc, 8, 0x60);
 769     create_pca9552(soc, 8, 0x61);
 770     /* Bus 8: ucd90320@11 */
 771     /* Bus 8: ucd90320@b */
 772     /* Bus 8: ucd90320@c */
 773
 774     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 775     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 776     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 777
 778     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 779     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 780     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 781
 782     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 783                      0x48);
 784     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 785                      0x49);
 786     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 787                                       "pca9546", 0x70);
 788     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 789     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 790     create_pca9552(soc, 11, 0x60);
 791
 792
 793     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 794     create_pca9552(soc, 13, 0x60);
 795
 796     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 797     create_pca9552(soc, 14, 0x60);
 798
 799     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 800     create_pca9552(soc, 15, 0x60);
 801 }
 802
 803 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 804                                  I2CBus **channels)
 805 {
 806     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 807     for (int i = 0; i < 8; i++) {
 808         channels[i] = pca954x_i2c_get_bus(mux, i);
 809     }
 810 }
 811
 812 #define TYPE_LM75 TYPE_TMP105
 813 #define TYPE_TMP75 TYPE_TMP105
 814 #define TYPE_TMP422 "tmp422"
 815
 816 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 817 {
 818     AspeedSoCState *soc = &bmc->soc;
 819     I2CBus *i2c[144] = {};
 820
 821     for (int i = 0; i < 16; i++) {
 822         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 823     }
 824     I2CBus *i2c180 = i2c[2];
 825     I2CBus *i2c480 = i2c[8];
 826     I2CBus *i2c600 = i2c[11];
 827
 828     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 829     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 830     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 831     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 832     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 833     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 834     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 835     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 836     for (int i = 0; i < 8; i++) {
 837         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 838     }
 839
 840     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 841     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 842
 843     at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
 844     at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
 845     at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
 846
 847     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 848     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 849     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 850     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 851
 852     at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
 853     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 854
 855     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 856     at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
 857     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 858     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 859
 860     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 861     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 862
 863     at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
 864     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 865     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 866     at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
 867     at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
 868     at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
 869     at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
 870
 871     at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
 872     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 873     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 874     at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
 875     at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
 876     at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
 877     at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
 878     at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
 879
 880     for (int i = 0; i < 8; i++) {
 881         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 882         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 883         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 884         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 885     }
 886 }
 887
 888 #define TYPE_TMP421 "tmp421"
 889
 890 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 891 {
 892     AspeedSoCState *soc = &bmc->soc;
 893     I2CBus *i2c[13] = {};
 894     for (int i = 0; i < 13; i++) {
 895         if ((i == 8) || (i == 11)) {
 896             continue;
 897         }
 898         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 899     }
 900
 901     /* Bus 0 - 5 all have the same config. */
 902     for (int i = 0; i < 6; i++) {
 903         /* Missing model: ti,ina230 @ 0x45 */
 904         /* Missing model: mps,mp5023 @ 0x40 */
 905         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 906         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 907         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 908         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 909         /* Missing model: fsc,fusb302 @ 0x22 */
 910     }
 911
 912     /* Bus 6 */
 913     at24c_eeprom_init(i2c[6], 0x56, 65536);
 914     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 915     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 916
 917
 918     /* Bus 7 */
 919     at24c_eeprom_init(i2c[7], 0x54, 65536);
 920
 921     /* Bus 9 */
 922     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 923
 924     /* Bus 10 */
 925     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 926     /* Missing model: ti,hdc1080 @ 0x40 */
 927     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 928
 929     /* Bus 12 */
 930     /* Missing model: adi,adm1278 @ 0x11 */
 931     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 932     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 933     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 934 }
 935
 936 static void fby35_i2c_init(AspeedMachineState *bmc)
 937 {
 938     AspeedSoCState *soc = &bmc->soc;
 939     I2CBus *i2c[16];
 940
 941     for (int i = 0; i < 16; i++) {
 942         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 943     }
 944
 945     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 946     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 947     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 948     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 949     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 950     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 951
 952     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
 953     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
 954     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
 955                           fby35_nic_fruid_len);
 956     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
 957                           fby35_bb_fruid_len);
 958     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
 959                           fby35_bmc_fruid_len);
 960
 961     /*
 962      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
 963      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
 964      * each.
 965      */
 966 }
 967
 968 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 969 {
 970     AspeedSoCState *soc = &bmc->soc;
 971
 972     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 973 }
 974
 975 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 976 {
 977     AspeedSoCState *soc = &bmc->soc;
 978     I2CSlave *therm_mux, *cpuvr_mux;
 979
 980     /* Create the generic DC-SCM hardware */
 981     qcom_dc_scm_bmc_i2c_init(bmc);
 982
 983     /* Now create the Firework specific hardware */
 984
 985     /* I2C7 CPUVR MUX */
 986     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 987                                         "pca9546", 0x70);
 988     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
 989     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
 990     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
 991     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
 992
 993     /* I2C8 Thermal Diodes*/
 994     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 995                                         "pca9548", 0x70);
 996     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
 997     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
 998     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
 999     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1000     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1001
1002     /* I2C9 Fan Controller (MAX31785) */
1003     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1004     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1005 }
1006
1007 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1008 {
1009     return ASPEED_MACHINE(obj)->mmio_exec;
1010 }
1011
1012 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1013 {
1014     ASPEED_MACHINE(obj)->mmio_exec = value;
1015 }
1016
1017 static void aspeed_machine_instance_init(Object *obj)
1018 {
1019     ASPEED_MACHINE(obj)->mmio_exec = false;
1020 }
1021
1022 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1023 {
1024     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1025     return g_strdup(bmc->fmc_model);
1026 }
1027
1028 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1029 {
1030     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1031
1032     g_free(bmc->fmc_model);
1033     bmc->fmc_model = g_strdup(value);
1034 }
1035
1036 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1037 {
1038     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1039     return g_strdup(bmc->spi_model);
1040 }
1041
1042 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1043 {
1044     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1045
1046     g_free(bmc->spi_model);
1047     bmc->spi_model = g_strdup(value);
1048 }
1049
1050 static void aspeed_machine_class_props_init(ObjectClass *oc)
1051 {
1052     object_class_property_add_bool(oc, "execute-in-place",
1053                                    aspeed_get_mmio_exec,
1054                                    aspeed_set_mmio_exec);
1055     object_class_property_set_description(oc, "execute-in-place",
1056                            "boot directly from CE0 flash device");
1057
1058     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1059                                    aspeed_set_fmc_model);
1060     object_class_property_set_description(oc, "fmc-model",
1061                                           "Change the FMC Flash model");
1062     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1063                                    aspeed_set_spi_model);
1064     object_class_property_set_description(oc, "spi-model",
1065                                           "Change the SPI Flash model");
1066 }
1067
1068 static int aspeed_soc_num_cpus(const char *soc_name)
1069 {
1070    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1071    return sc->num_cpus;
1072 }
1073
1074 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1075 {
1076     MachineClass *mc = MACHINE_CLASS(oc);
1077     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1078
1079     mc->init = aspeed_machine_init;
1080     mc->no_floppy = 1;
1081     mc->no_cdrom = 1;
1082     mc->no_parallel = 1;
1083     mc->default_ram_id = "ram";
1084     amc->macs_mask = ASPEED_MAC0_ON;
1085     amc->uart_default = ASPEED_DEV_UART5;
1086
1087     aspeed_machine_class_props_init(oc);
1088 }
1089
1090 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1091 {
1092     MachineClass *mc = MACHINE_CLASS(oc);
1093     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1094
1095     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1096     amc->soc_name  = "ast2400-a1";
1097     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1098     amc->fmc_model = "n25q256a";
1099     amc->spi_model = "mx25l25635f";
1100     amc->num_cs    = 1;
1101     amc->i2c_init  = palmetto_bmc_i2c_init;
1102     mc->default_ram_size       = 256 * MiB;
1103     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1104         aspeed_soc_num_cpus(amc->soc_name);
1105 };
1106
1107 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1108 {
1109     MachineClass *mc = MACHINE_CLASS(oc);
1110     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1111
1112     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1113     amc->soc_name  = "ast2400-a1";
1114     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1115     amc->fmc_model = "n25q256a";
1116     amc->spi_model = "mx25l25635e";
1117     amc->num_cs    = 1;
1118     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1119     mc->default_ram_size       = 128 * MiB;
1120     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1121         aspeed_soc_num_cpus(amc->soc_name);
1122 }
1123
1124 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1125                                                         void *data)
1126 {
1127     MachineClass *mc = MACHINE_CLASS(oc);
1128     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1129
1130     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1131     amc->soc_name  = "ast2400-a1";
1132     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1133     amc->fmc_model = "mx25l25635e";
1134     amc->spi_model = "mx25l25635e";
1135     amc->num_cs    = 1;
1136     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1137     amc->i2c_init  = palmetto_bmc_i2c_init;
1138     mc->default_ram_size = 256 * MiB;
1139 }
1140
1141 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1142                                                             void *data)
1143 {
1144     MachineClass *mc = MACHINE_CLASS(oc);
1145     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1146
1147     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1148     amc->soc_name  = "ast2500-a1";
1149     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1150     amc->fmc_model = "mx25l25635e";
1151     amc->spi_model = "mx25l25635e";
1152     amc->num_cs    = 1;
1153     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1154     amc->i2c_init  = palmetto_bmc_i2c_init;
1155     mc->default_ram_size = 512 * MiB;
1156     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1157         aspeed_soc_num_cpus(amc->soc_name);
1158 }
1159
1160 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1161 {
1162     MachineClass *mc = MACHINE_CLASS(oc);
1163     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1164
1165     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1166     amc->soc_name  = "ast2500-a1";
1167     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1168     amc->fmc_model = "mx25l25635e";
1169     amc->spi_model = "mx25l25635f";
1170     amc->num_cs    = 1;
1171     amc->i2c_init  = ast2500_evb_i2c_init;
1172     mc->default_ram_size       = 512 * MiB;
1173     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1174         aspeed_soc_num_cpus(amc->soc_name);
1175 };
1176
1177 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1178 {
1179     MachineClass *mc = MACHINE_CLASS(oc);
1180     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1181
1182     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1183     amc->soc_name  = "ast2500-a1";
1184     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1185     amc->fmc_model = "n25q256a";
1186     amc->spi_model = "mx66l1g45g";
1187     amc->num_cs    = 2;
1188     amc->i2c_init  = romulus_bmc_i2c_init;
1189     mc->default_ram_size       = 512 * MiB;
1190     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1191         aspeed_soc_num_cpus(amc->soc_name);
1192 };
1193
1194 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1195 {
1196     MachineClass *mc = MACHINE_CLASS(oc);
1197     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1198
1199     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1200     amc->soc_name  = "ast2500-a1";
1201     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1202     amc->fmc_model = "mx66l1g45g";
1203     amc->spi_model = "mx66l1g45g";
1204     amc->num_cs    = 2;
1205     amc->i2c_init  = sonorapass_bmc_i2c_init;
1206     mc->default_ram_size       = 512 * MiB;
1207     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1208         aspeed_soc_num_cpus(amc->soc_name);
1209 };
1210
1211 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1212 {
1213     MachineClass *mc = MACHINE_CLASS(oc);
1214     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1215
1216     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1217     amc->soc_name  = "ast2500-a1";
1218     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1219     amc->fmc_model = "mx25l25635f";
1220     amc->spi_model = "mx66l1g45g";
1221     amc->num_cs    = 2;
1222     amc->i2c_init  = witherspoon_bmc_i2c_init;
1223     mc->default_ram_size = 512 * MiB;
1224     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1225         aspeed_soc_num_cpus(amc->soc_name);
1226 };
1227
1228 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1229 {
1230     MachineClass *mc = MACHINE_CLASS(oc);
1231     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1232
1233     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1234     amc->soc_name  = "ast2600-a3";
1235     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1236     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1237     amc->fmc_model = "mx66u51235f";
1238     amc->spi_model = "mx66u51235f";
1239     amc->num_cs    = 1;
1240     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1241                      ASPEED_MAC3_ON;
1242     amc->i2c_init  = ast2600_evb_i2c_init;
1243     mc->default_ram_size = 1 * GiB;
1244     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1245         aspeed_soc_num_cpus(amc->soc_name);
1246 };
1247
1248 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1249 {
1250     MachineClass *mc = MACHINE_CLASS(oc);
1251     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1252
1253     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1254     amc->soc_name  = "ast2600-a3";
1255     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1256     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1257     amc->fmc_model = "mx66l1g45g";
1258     amc->spi_model = "mx66l1g45g";
1259     amc->num_cs    = 2;
1260     amc->macs_mask  = ASPEED_MAC2_ON;
1261     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1262     mc->default_ram_size = 1 * GiB;
1263     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1264         aspeed_soc_num_cpus(amc->soc_name);
1265 };
1266
1267 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1268 {
1269     MachineClass *mc = MACHINE_CLASS(oc);
1270     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1271
1272     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1273     amc->soc_name  = "ast2500-a1";
1274     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1275     amc->fmc_model = "n25q512a";
1276     amc->spi_model = "mx25l25635e";
1277     amc->num_cs    = 2;
1278     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1279     amc->i2c_init  = g220a_bmc_i2c_init;
1280     mc->default_ram_size = 1024 * MiB;
1281     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1282         aspeed_soc_num_cpus(amc->soc_name);
1283 };
1284
1285 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1286 {
1287     MachineClass *mc = MACHINE_CLASS(oc);
1288     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1289
1290     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1291     amc->soc_name  = "ast2500-a1";
1292     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1293     amc->fmc_model = "n25q512a";
1294     amc->spi_model = "mx25l25635e";
1295     amc->num_cs    = 2;
1296     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1297     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1298     mc->default_ram_size = 512 * MiB;
1299     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1300         aspeed_soc_num_cpus(amc->soc_name);
1301 };
1302
1303 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1304 {
1305     MachineClass *mc = MACHINE_CLASS(oc);
1306     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1307
1308     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1309     amc->soc_name  = "ast2600-a3";
1310     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1311     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1312     amc->fmc_model = "mx66l1g45g";
1313     amc->spi_model = "mx66l1g45g";
1314     amc->num_cs    = 2;
1315     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1316     amc->i2c_init  = rainier_bmc_i2c_init;
1317     mc->default_ram_size = 1 * GiB;
1318     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1319         aspeed_soc_num_cpus(amc->soc_name);
1320 };
1321
1322 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1323 #if HOST_LONG_BITS == 32
1324 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1325 #else
1326 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1327 #endif
1328
1329 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1330 {
1331     MachineClass *mc = MACHINE_CLASS(oc);
1332     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1333
1334     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1335     amc->soc_name = "ast2600-a3";
1336     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1337     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1338     amc->fmc_model = "mx66l1g45g";
1339     amc->spi_model = "mx66l1g45g";
1340     amc->num_cs = 2;
1341     amc->macs_mask = ASPEED_MAC3_ON;
1342     amc->i2c_init = fuji_bmc_i2c_init;
1343     amc->uart_default = ASPEED_DEV_UART1;
1344     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1345     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1346         aspeed_soc_num_cpus(amc->soc_name);
1347 };
1348
1349 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1350 #if HOST_LONG_BITS == 32
1351 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1352 #else
1353 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1354 #endif
1355
1356 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1357 {
1358     MachineClass *mc = MACHINE_CLASS(oc);
1359     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1360
1361     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1362     amc->soc_name  = "ast2600-a3";
1363     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1364     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1365     amc->fmc_model = "w25q01jvq";
1366     amc->spi_model = NULL;
1367     amc->num_cs    = 2;
1368     amc->macs_mask = ASPEED_MAC2_ON;
1369     amc->i2c_init  = bletchley_bmc_i2c_init;
1370     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1371     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1372         aspeed_soc_num_cpus(amc->soc_name);
1373 }
1374
1375 static void fby35_reset(MachineState *state, ShutdownCause reason)
1376 {
1377     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1378     AspeedGPIOState *gpio = &bmc->soc.gpio;
1379
1380     qemu_devices_reset(reason);
1381
1382     /* Board ID: 7 (Class-1, 4 slots) */
1383     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1384     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1385     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1386     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1387
1388     /* Slot presence pins, inverse polarity. (False means present) */
1389     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1390     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1391     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1392     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1393
1394     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1395     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1396     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1397     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1398     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1399 }
1400
1401 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1402 {
1403     MachineClass *mc = MACHINE_CLASS(oc);
1404     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1405
1406     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1407     mc->reset      = fby35_reset;
1408     amc->fmc_model = "mx66l1g45g";
1409     amc->num_cs    = 2;
1410     amc->macs_mask = ASPEED_MAC3_ON;
1411     amc->i2c_init  = fby35_i2c_init;
1412     /* FIXME: Replace this macro with something more general */
1413     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1414 }
1415
1416 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1417 /* Main SYSCLK frequency in Hz (200MHz) */
1418 #define SYSCLK_FRQ 200000000ULL
1419
1420 static void aspeed_minibmc_machine_init(MachineState *machine)
1421 {
1422     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1423     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1424     Clock *sysclk;
1425
1426     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1427     clock_set_hz(sysclk, SYSCLK_FRQ);
1428
1429     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1430     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1431
1432     object_property_set_link(OBJECT(&bmc->soc), "memory",
1433                              OBJECT(get_system_memory()), &error_abort);
1434     connect_serial_hds_to_uarts(bmc);
1435     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1436
1437     aspeed_board_init_flashes(&bmc->soc.fmc,
1438                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1439                               amc->num_cs,
1440                               0);
1441
1442     aspeed_board_init_flashes(&bmc->soc.spi[0],
1443                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1444                               amc->num_cs, amc->num_cs);
1445
1446     aspeed_board_init_flashes(&bmc->soc.spi[1],
1447                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1448                               amc->num_cs, (amc->num_cs * 2));
1449
1450     if (amc->i2c_init) {
1451         amc->i2c_init(bmc);
1452     }
1453
1454     armv7m_load_kernel(ARM_CPU(first_cpu),
1455                        machine->kernel_filename,
1456                        0,
1457                        AST1030_INTERNAL_FLASH_SIZE);
1458 }
1459
1460 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1461 {
1462     AspeedSoCState *soc = &bmc->soc;
1463
1464     /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1465     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1466     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1467
1468     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1469     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1470 }
1471
1472 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1473                                                           void *data)
1474 {
1475     MachineClass *mc = MACHINE_CLASS(oc);
1476     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1477
1478     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1479     amc->soc_name = "ast1030-a1";
1480     amc->hw_strap1 = 0;
1481     amc->hw_strap2 = 0;
1482     mc->init = aspeed_minibmc_machine_init;
1483     amc->i2c_init = ast1030_evb_i2c_init;
1484     mc->default_ram_size = 0;
1485     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1486     amc->fmc_model = "sst25vf032b";
1487     amc->spi_model = "sst25vf032b";
1488     amc->num_cs = 2;
1489     amc->macs_mask = 0;
1490 }
1491
1492 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1493                                                      void *data)
1494 {
1495     MachineClass *mc = MACHINE_CLASS(oc);
1496     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1497
1498     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1499     amc->soc_name  = "ast2600-a3";
1500     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1501     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1502     amc->fmc_model = "n25q512a";
1503     amc->spi_model = "n25q512a";
1504     amc->num_cs    = 2;
1505     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1506     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1507     mc->default_ram_size = 1 * GiB;
1508     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1509         aspeed_soc_num_cpus(amc->soc_name);
1510 };
1511
1512 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1513                                                     void *data)
1514 {
1515     MachineClass *mc = MACHINE_CLASS(oc);
1516     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1517
1518     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1519     amc->soc_name  = "ast2600-a3";
1520     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1521     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1522     amc->fmc_model = "n25q512a";
1523     amc->spi_model = "n25q512a";
1524     amc->num_cs    = 2;
1525     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1526     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1527     mc->default_ram_size = 1 * GiB;
1528     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1529         aspeed_soc_num_cpus(amc->soc_name);
1530 };
1531
1532 static const TypeInfo aspeed_machine_types[] = {
1533     {
1534         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1535         .parent        = TYPE_ASPEED_MACHINE,
1536         .class_init    = aspeed_machine_palmetto_class_init,
1537     }, {
1538         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1539         .parent        = TYPE_ASPEED_MACHINE,
1540         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1541     }, {
1542         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1543         .parent        = TYPE_ASPEED_MACHINE,
1544         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1545     }, {
1546         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1547         .parent        = TYPE_ASPEED_MACHINE,
1548         .class_init    = aspeed_machine_ast2500_evb_class_init,
1549     }, {
1550         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1551         .parent        = TYPE_ASPEED_MACHINE,
1552         .class_init    = aspeed_machine_romulus_class_init,
1553     }, {
1554         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1555         .parent        = TYPE_ASPEED_MACHINE,
1556         .class_init    = aspeed_machine_sonorapass_class_init,
1557     }, {
1558         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1559         .parent        = TYPE_ASPEED_MACHINE,
1560         .class_init    = aspeed_machine_witherspoon_class_init,
1561     }, {
1562         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1563         .parent        = TYPE_ASPEED_MACHINE,
1564         .class_init    = aspeed_machine_ast2600_evb_class_init,
1565     }, {
1566         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1567         .parent        = TYPE_ASPEED_MACHINE,
1568         .class_init    = aspeed_machine_tacoma_class_init,
1569     }, {
1570         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1571         .parent        = TYPE_ASPEED_MACHINE,
1572         .class_init    = aspeed_machine_g220a_class_init,
1573     }, {
1574         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1575         .parent        = TYPE_ASPEED_MACHINE,
1576         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1577     }, {
1578         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1579         .parent        = TYPE_ASPEED_MACHINE,
1580         .class_init    = aspeed_machine_qcom_firework_class_init,
1581     }, {
1582         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1583         .parent        = TYPE_ASPEED_MACHINE,
1584         .class_init    = aspeed_machine_fp5280g2_class_init,
1585     }, {
1586         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1587         .parent        = TYPE_ASPEED_MACHINE,
1588         .class_init    = aspeed_machine_quanta_q71l_class_init,
1589     }, {
1590         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1591         .parent        = TYPE_ASPEED_MACHINE,
1592         .class_init    = aspeed_machine_rainier_class_init,
1593     }, {
1594         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1595         .parent        = TYPE_ASPEED_MACHINE,
1596         .class_init    = aspeed_machine_fuji_class_init,
1597     }, {
1598         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1599         .parent        = TYPE_ASPEED_MACHINE,
1600         .class_init    = aspeed_machine_bletchley_class_init,
1601     }, {
1602         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1603         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1604         .class_init    = aspeed_machine_fby35_class_init,
1605     }, {
1606         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1607         .parent         = TYPE_ASPEED_MACHINE,
1608         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1609     }, {
1610         .name          = TYPE_ASPEED_MACHINE,
1611         .parent        = TYPE_MACHINE,
1612         .instance_size = sizeof(AspeedMachineState),
1613         .instance_init = aspeed_machine_instance_init,
1614         .class_size    = sizeof(AspeedMachineClass),
1615         .class_init    = aspeed_machine_class_init,
1616         .abstract      = true,
1617     }
1618 };
1619
1620 DEFINE_TYPES(aspeed_machine_types)