hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/aspeed.h"
  16 #include "hw/arm/aspeed_soc.h"
  17 #include "hw/arm/aspeed_eeprom.h"
  18 #include "hw/i2c/i2c_mux_pca954x.h"
  19 #include "hw/i2c/smbus_eeprom.h"
  20 #include "hw/misc/pca9552.h"
  21 #include "hw/nvram/eeprom_at24c.h"
  22 #include "hw/sensor/tmp105.h"
  23 #include "hw/misc/led.h"
  24 #include "hw/qdev-properties.h"
  25 #include "sysemu/block-backend.h"
  26 #include "sysemu/reset.h"
  27 #include "hw/loader.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/units.h"
  30 #include "hw/qdev-clock.h"
  31 #include "sysemu/sysemu.h"
  32
  33 static struct arm_boot_info aspeed_board_binfo = {
  34     .board_id = -1, /* device-tree-only board */
  35 };
  36
  37 struct AspeedMachineState {
  38     /* Private */
  39     MachineState parent_obj;
  40     /* Public */
  41
  42     AspeedSoCState soc;
  43     bool mmio_exec;
  44     char *fmc_model;
  45     char *spi_model;
  46 };
  47
  48 /* Palmetto hardware value: 0x120CE416 */
  49 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  50         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  51         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  52         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  53         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  54         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  55         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  56         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  57         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  58         SCU_HW_STRAP_SPI_WIDTH |                                        \
  59         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  60         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  61
  62 /* TODO: Find the actual hardware value */
  63 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
  64         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
  65         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
  66         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  67         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  68         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  69         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  70         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  71         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  72         SCU_HW_STRAP_SPI_WIDTH |                                        \
  73         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  74         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  75
  76 /* TODO: Find the actual hardware value */
  77 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
  78         AST2500_HW_STRAP1_DEFAULTS |                                    \
  79         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  80         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  81         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  82         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  83         SCU_HW_STRAP_SPI_WIDTH |                                        \
  84         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
  85
  86 /* AST2500 evb hardware value: 0xF100C2E6 */
  87 #define AST2500_EVB_HW_STRAP1 ((                                        \
  88         AST2500_HW_STRAP1_DEFAULTS |                                    \
  89         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  90         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  91         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  92         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  93         SCU_HW_STRAP_MAC1_RGMII |                                       \
  94         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  95         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  96
  97 /* Romulus hardware value: 0xF10AD206 */
  98 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  99         AST2500_HW_STRAP1_DEFAULTS |                                    \
 100         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 101         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 102         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 103         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 104         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
 105         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
 106
 107 /* Sonorapass hardware value: 0xF100D216 */
 108 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
 109         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 110         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 111         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 112         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 113         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 114         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 115         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 116         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 117         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 118         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
 119         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 120         SCU_AST2500_HW_STRAP_RESERVED1)
 121
 122 #define G220A_BMC_HW_STRAP1 (                                      \
 123         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 124         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 125         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 126         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 127         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 128         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
 129         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 130         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 131         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 132         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 133         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
 134         SCU_AST2500_HW_STRAP_RESERVED1)
 135
 136 /* FP5280G2 hardware value: 0XF100D286 */
 137 #define FP5280G2_BMC_HW_STRAP1 (                                      \
 138         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
 139         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
 140         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
 141         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
 142         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
 143         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 144         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
 145         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
 146         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
 147         SCU_HW_STRAP_MAC1_RGMII |                                       \
 148         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
 149         SCU_AST2500_HW_STRAP_RESERVED1)
 150
 151 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
 152 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
 153
 154 /* Quanta-Q71l hardware value */
 155 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
 156         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
 157         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
 158         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
 159         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
 160         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
 161         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
 162         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
 163         SCU_HW_STRAP_SPI_WIDTH |                                        \
 164         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
 165         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 166
 167 /* AST2600 evb hardware value */
 168 #define AST2600_EVB_HW_STRAP1 0x000000C0
 169 #define AST2600_EVB_HW_STRAP2 0x00000003
 170
 171 /* Tacoma hardware value */
 172 #define TACOMA_BMC_HW_STRAP1  0x00000000
 173 #define TACOMA_BMC_HW_STRAP2  0x00000040
 174
 175 /* Rainier hardware value: (QEMU prototype) */
 176 #define RAINIER_BMC_HW_STRAP1 0x00422016
 177 #define RAINIER_BMC_HW_STRAP2 0x80000848
 178
 179 /* Fuji hardware value */
 180 #define FUJI_BMC_HW_STRAP1    0x00000000
 181 #define FUJI_BMC_HW_STRAP2    0x00000000
 182
 183 /* Bletchley hardware value */
 184 /* TODO: Leave same as EVB for now. */
 185 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 186 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 187
 188 /* Qualcomm DC-SCM hardware value */
 189 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 190 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
 191
 192 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
 193 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
 194 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
 195 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
 196 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
 197 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
 198 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
 199
 200 static void aspeed_write_smpboot(ARMCPU *cpu,
 201                                  const struct arm_boot_info *info)
 202 {
 203     static const uint32_t poll_mailbox_ready[] = {
 204         /*
 205          * r2 = per-cpu go sign value
 206          * r1 = AST_SMP_MBOX_FIELD_ENTRY
 207          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
 208          */
 209         0xee100fb0,  /* mrc     p15, 0, r0, c0, c0, 5 */
 210         0xe21000ff,  /* ands    r0, r0, #255          */
 211         0xe59f201c,  /* ldr     r2, [pc, #28]         */
 212         0xe1822000,  /* orr     r2, r2, r0            */
 213
 214         0xe59f1018,  /* ldr     r1, [pc, #24]         */
 215         0xe59f0018,  /* ldr     r0, [pc, #24]         */
 216
 217         0xe320f002,  /* wfe                           */
 218         0xe5904000,  /* ldr     r4, [r0]              */
 219         0xe1520004,  /* cmp     r2, r4                */
 220         0x1afffffb,  /* bne     <wfe>                 */
 221         0xe591f000,  /* ldr     pc, [r1]              */
 222         AST_SMP_MBOX_GOSIGN,
 223         AST_SMP_MBOX_FIELD_ENTRY,
 224         AST_SMP_MBOX_FIELD_GOSIGN,
 225     };
 226
 227     rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
 228                        sizeof(poll_mailbox_ready),
 229                        info->smp_loader_start);
 230 }
 231
 232 static void aspeed_reset_secondary(ARMCPU *cpu,
 233                                    const struct arm_boot_info *info)
 234 {
 235     AddressSpace *as = arm_boot_address_space(cpu, info);
 236     CPUState *cs = CPU(cpu);
 237
 238     /* info->smp_bootreg_addr */
 239     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
 240                                MEMTXATTRS_UNSPECIFIED, NULL);
 241     cpu_set_pc(cs, info->smp_loader_start);
 242 }
 243
 244 #define FIRMWARE_ADDR 0x0
 245
 246 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
 247                            Error **errp)
 248 {
 249     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 250     g_autofree void *storage = NULL;
 251     int64_t size;
 252
 253     /* The block backend size should have already been 'validated' by
 254      * the creation of the m25p80 object.
 255      */
 256     size = blk_getlength(blk);
 257     if (size <= 0) {
 258         error_setg(errp, "failed to get flash size");
 259         return;
 260     }
 261
 262     if (rom_size > size) {
 263         rom_size = size;
 264     }
 265
 266     storage = g_malloc0(rom_size);
 267     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
 268         error_setg(errp, "failed to read the initial flash content");
 269         return;
 270     }
 271
 272     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 273 }
 274
 275 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 276                                       unsigned int count, int unit0)
 277 {
 278     int i;
 279
 280     if (!flashtype) {
 281         return;
 282     }
 283
 284     for (i = 0; i < count; ++i) {
 285         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
 286         qemu_irq cs_line;
 287         DeviceState *dev;
 288
 289         dev = qdev_new(flashtype);
 290         if (dinfo) {
 291             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 292         }
 293         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
 294
 295         cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 296         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
 297     }
 298 }
 299
 300 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 301 {
 302         DeviceState *card;
 303
 304         if (!dinfo) {
 305             return;
 306         }
 307         card = qdev_new(TYPE_SD_CARD);
 308         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 309                                 &error_fatal);
 310         qdev_realize_and_unref(card,
 311                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
 312                                &error_fatal);
 313 }
 314
 315 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 316 {
 317     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 318     AspeedSoCState *s = &bmc->soc;
 319     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 320
 321     aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
 322     for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 323         if (uart == amc->uart_default) {
 324             continue;
 325         }
 326         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
 327     }
 328 }
 329
 330 static void aspeed_machine_init(MachineState *machine)
 331 {
 332     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
 333     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 334     AspeedSoCClass *sc;
 335     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
 336     int i;
 337     NICInfo *nd = &nd_table[0];
 338
 339     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 340
 341     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 342
 343     /*
 344      * This will error out if the RAM size is not supported by the
 345      * memory controller of the SoC.
 346      */
 347     object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 348                              &error_fatal);
 349
 350     for (i = 0; i < sc->macs_num; i++) {
 351         if ((amc->macs_mask & (1 << i)) && nd->used) {
 352             qemu_check_nic_model(nd, TYPE_FTGMAC100);
 353             qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 354             nd++;
 355         }
 356     }
 357
 358     object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 359                             &error_abort);
 360     object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 361                             &error_abort);
 362     object_property_set_link(OBJECT(&bmc->soc), "memory",
 363                              OBJECT(get_system_memory()), &error_abort);
 364     object_property_set_link(OBJECT(&bmc->soc), "dram",
 365                              OBJECT(machine->ram), &error_abort);
 366     if (machine->kernel_filename) {
 367         /*
 368          * When booting with a -kernel command line there is no u-boot
 369          * that runs to unlock the SCU. In this case set the default to
 370          * be unlocked as the kernel expects
 371          */
 372         object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 373                                 ASPEED_SCU_PROT_KEY, &error_abort);
 374     }
 375     connect_serial_hds_to_uarts(bmc);
 376     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 377
 378     aspeed_board_init_flashes(&bmc->soc.fmc,
 379                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
 380                               amc->num_cs, 0);
 381     aspeed_board_init_flashes(&bmc->soc.spi[0],
 382                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
 383                               1, amc->num_cs);
 384
 385     /* Install first FMC flash content as a boot rom. */
 386     if (drive0) {
 387         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
 388         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 389         uint64_t size = memory_region_size(&fl->mmio);
 390
 391         /*
 392          * create a ROM region using the default mapping window size of
 393          * the flash module. The window size is 64MB for the AST2400
 394          * SoC and 128MB for the AST2500 SoC, which is twice as big as
 395          * needed by the flash modules of the Aspeed machines.
 396          */
 397         if (ASPEED_MACHINE(machine)->mmio_exec) {
 398             memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
 399                                      &fl->mmio, 0, size);
 400             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 401                                         boot_rom);
 402         } else {
 403             memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
 404                                    size, &error_abort);
 405             memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 406                                         boot_rom);
 407             write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
 408         }
 409     }
 410
 411     if (machine->kernel_filename && sc->num_cpus > 1) {
 412         /* With no u-boot we must set up a boot stub for the secondary CPU */
 413         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
 414         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
 415                                0x80, &error_abort);
 416         memory_region_add_subregion(get_system_memory(),
 417                                     AST_SMP_MAILBOX_BASE, smpboot);
 418
 419         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
 420         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
 421         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
 422     }
 423
 424     aspeed_board_binfo.ram_size = machine->ram_size;
 425     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
 426
 427     if (amc->i2c_init) {
 428         amc->i2c_init(bmc);
 429     }
 430
 431     for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 432         sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 433                            drive_get(IF_SD, 0, i));
 434     }
 435
 436     if (bmc->soc.emmc.num_slots) {
 437         sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 438                            drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 439     }
 440
 441     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 442 }
 443
 444 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 445 {
 446     AspeedSoCState *soc = &bmc->soc;
 447     DeviceState *dev;
 448     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 449
 450     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 451      * enough to provide basic RTC features. Alarms will be missing */
 452     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
 453
 454     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
 455                           eeprom_buf);
 456
 457     /* add a TMP423 temperature sensor */
 458     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 459                                          "tmp423", 0x4c));
 460     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 461     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 462     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 463     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
 464 }
 465
 466 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 467 {
 468     AspeedSoCState *soc = &bmc->soc;
 469
 470     /*
 471      * The quanta-q71l platform expects tmp75s which are compatible with
 472      * tmp105s.
 473      */
 474     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
 475     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
 476     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
 477
 478     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
 479     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
 480     /* TODO: Add Memory Riser i2c mux and eeproms. */
 481
 482     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
 483     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
 484
 485     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
 486
 487     /* i2c-7 */
 488     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
 489     /*        - i2c@0: pmbus@59 */
 490     /*        - i2c@1: pmbus@58 */
 491     /*        - i2c@2: pmbus@58 */
 492     /*        - i2c@3: pmbus@59 */
 493
 494     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
 495     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
 496 }
 497
 498 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 499 {
 500     AspeedSoCState *soc = &bmc->soc;
 501     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 502
 503     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
 504                           eeprom_buf);
 505
 506     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 507     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
 508                      TYPE_TMP105, 0x4d);
 509 }
 510
 511 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 512 {
 513     AspeedSoCState *soc = &bmc->soc;
 514     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 515
 516     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
 517                           eeprom_buf);
 518
 519     /* LM75 is compatible with TMP105 driver */
 520     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
 521                      TYPE_TMP105, 0x4d);
 522 }
 523
 524 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 525 {
 526     AspeedSoCState *soc = &bmc->soc;
 527
 528     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
 529     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
 530                           yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
 531 }
 532
 533 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 534 {
 535     AspeedSoCState *soc = &bmc->soc;
 536
 537     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 538      * good enough */
 539     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 540 }
 541
 542 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 543 {
 544     AspeedSoCState *soc = &bmc->soc;
 545
 546     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
 547     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
 548                           tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
 549 }
 550
 551 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 552 {
 553     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
 554                             TYPE_PCA9552, addr);
 555 }
 556
 557 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 558 {
 559     AspeedSoCState *soc = &bmc->soc;
 560
 561     /* bus 2 : */
 562     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
 563     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
 564     /* bus 2 : pca9546 @ 0x73 */
 565
 566     /* bus 3 : pca9548 @ 0x70 */
 567
 568     /* bus 4 : */
 569     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
 570     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
 571                           eeprom4_54);
 572     /* PCA9539 @ 0x76, but PCA9552 is compatible */
 573     create_pca9552(soc, 4, 0x76);
 574     /* PCA9539 @ 0x77, but PCA9552 is compatible */
 575     create_pca9552(soc, 4, 0x77);
 576
 577     /* bus 6 : */
 578     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
 579     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
 580     /* bus 6 : pca9546 @ 0x73 */
 581
 582     /* bus 8 : */
 583     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
 584     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
 585                           eeprom8_56);
 586     create_pca9552(soc, 8, 0x60);
 587     create_pca9552(soc, 8, 0x61);
 588     /* bus 8 : adc128d818 @ 0x1d */
 589     /* bus 8 : adc128d818 @ 0x1f */
 590
 591     /*
 592      * bus 13 : pca9548 @ 0x71
 593      *      - channel 3:
 594      *          - tmm421 @ 0x4c
 595      *          - tmp421 @ 0x4e
 596      *          - tmp421 @ 0x4f
 597      */
 598
 599 }
 600
 601 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 602 {
 603     static const struct {
 604         unsigned gpio_id;
 605         LEDColor color;
 606         const char *description;
 607         bool gpio_polarity;
 608     } pca1_leds[] = {
 609         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
 610         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
 611         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
 612     };
 613     AspeedSoCState *soc = &bmc->soc;
 614     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 615     DeviceState *dev;
 616     LEDState *led;
 617
 618     /* Bus 3: TODO bmp280@77 */
 619     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 620     qdev_prop_set_string(dev, "description", "pca1");
 621     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 622                                 aspeed_i2c_get_bus(&soc->i2c, 3),
 623                                 &error_fatal);
 624
 625     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
 626         led = led_create_simple(OBJECT(bmc),
 627                                 pca1_leds[i].gpio_polarity,
 628                                 pca1_leds[i].color,
 629                                 pca1_leds[i].description);
 630         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
 631                               qdev_get_gpio_in(DEVICE(led), 0));
 632     }
 633     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
 634     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
 635     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
 636     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
 637
 638     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 639     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
 640                      0x4a);
 641
 642     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 643      * good enough */
 644     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
 645
 646     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
 647                           eeprom_buf);
 648     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
 649     qdev_prop_set_string(dev, "description", "pca0");
 650     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
 651                                 aspeed_i2c_get_bus(&soc->i2c, 11),
 652                                 &error_fatal);
 653     /* Bus 11: TODO ucd90160@64 */
 654 }
 655
 656 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 657 {
 658     AspeedSoCState *soc = &bmc->soc;
 659     DeviceState *dev;
 660
 661     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
 662                                          "emc1413", 0x4c));
 663     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 664     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 665     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 666
 667     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
 668                                          "emc1413", 0x4c));
 669     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 670     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 671     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 672
 673     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
 674                                          "emc1413", 0x4c));
 675     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
 676     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
 677     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
 678
 679     static uint8_t eeprom_buf[2 * 1024] = {
 680             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
 681             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
 682             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
 683             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
 684             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
 685             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
 686             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
 687     };
 688     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
 689                           eeprom_buf);
 690 }
 691
 692 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 693 {
 694     AspeedSoCState *soc = &bmc->soc;
 695     I2CSlave *i2c_mux;
 696
 697     /* The at24c256 */
 698     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
 699
 700     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
 701     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 702                      0x48);
 703     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
 704                      0x49);
 705
 706     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
 707                      "pca9546", 0x70);
 708     /* It expects a TMP112 but a TMP105 is compatible */
 709     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
 710                      0x4a);
 711
 712     /* It expects a ds3232 but a ds1338 is good enough */
 713     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
 714
 715     /* It expects a pca9555 but a pca9552 is compatible */
 716     create_pca9552(soc, 8, 0x30);
 717 }
 718
 719 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 720 {
 721     AspeedSoCState *soc = &bmc->soc;
 722     I2CSlave *i2c_mux;
 723
 724     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 725
 726     create_pca9552(soc, 3, 0x61);
 727
 728     /* The rainier expects a TMP275 but a TMP105 is compatible */
 729     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 730                      0x48);
 731     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 732                      0x49);
 733     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
 734                      0x4a);
 735     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
 736                                       "pca9546", 0x70);
 737     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 738     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 739     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
 740     create_pca9552(soc, 4, 0x60);
 741
 742     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 743                      0x48);
 744     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
 745                      0x49);
 746     create_pca9552(soc, 5, 0x60);
 747     create_pca9552(soc, 5, 0x61);
 748     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
 749                                       "pca9546", 0x70);
 750     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 751     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 752
 753     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 754                      0x48);
 755     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 756                      0x4a);
 757     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
 758                      0x4b);
 759     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
 760                                       "pca9546", 0x70);
 761     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 762     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 763     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
 764     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 765
 766     create_pca9552(soc, 7, 0x30);
 767     create_pca9552(soc, 7, 0x31);
 768     create_pca9552(soc, 7, 0x32);
 769     create_pca9552(soc, 7, 0x33);
 770     create_pca9552(soc, 7, 0x60);
 771     create_pca9552(soc, 7, 0x61);
 772     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
 773     /* Bus 7: TODO si7021-a20@20 */
 774     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
 775                      0x48);
 776     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
 777     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
 778     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 779
 780     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 781                      0x48);
 782     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
 783                      0x4a);
 784     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
 785     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
 786     create_pca9552(soc, 8, 0x60);
 787     create_pca9552(soc, 8, 0x61);
 788     /* Bus 8: ucd90320@11 */
 789     /* Bus 8: ucd90320@b */
 790     /* Bus 8: ucd90320@c */
 791
 792     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
 793     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
 794     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 795
 796     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
 797     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
 798     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 799
 800     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 801                      0x48);
 802     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
 803                      0x49);
 804     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
 805                                       "pca9546", 0x70);
 806     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
 807     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 808     create_pca9552(soc, 11, 0x60);
 809
 810
 811     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
 812     create_pca9552(soc, 13, 0x60);
 813
 814     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
 815     create_pca9552(soc, 14, 0x60);
 816
 817     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
 818     create_pca9552(soc, 15, 0x60);
 819 }
 820
 821 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 822                                  I2CBus **channels)
 823 {
 824     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
 825     for (int i = 0; i < 8; i++) {
 826         channels[i] = pca954x_i2c_get_bus(mux, i);
 827     }
 828 }
 829
 830 #define TYPE_LM75 TYPE_TMP105
 831 #define TYPE_TMP75 TYPE_TMP105
 832 #define TYPE_TMP422 "tmp422"
 833
 834 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 835 {
 836     AspeedSoCState *soc = &bmc->soc;
 837     I2CBus *i2c[144] = {};
 838
 839     for (int i = 0; i < 16; i++) {
 840         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 841     }
 842     I2CBus *i2c180 = i2c[2];
 843     I2CBus *i2c480 = i2c[8];
 844     I2CBus *i2c600 = i2c[11];
 845
 846     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
 847     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
 848     /* NOTE: The device tree skips [32, 40) in the alias numbering */
 849     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
 850     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
 851     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
 852     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
 853     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
 854     for (int i = 0; i < 8; i++) {
 855         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
 856     }
 857
 858     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
 859     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 860
 861     /*
 862      * EEPROM 24c64 size is 64Kbits or 8 Kbytes
 863      *        24c02 size is 2Kbits or 256 bytes
 864      */
 865     at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
 866     at24c_eeprom_init(i2c[20], 0x50, 256);
 867     at24c_eeprom_init(i2c[22], 0x52, 256);
 868
 869     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
 870     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
 871     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
 872     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 873
 874     at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
 875     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 876
 877     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
 878     at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
 879     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
 880     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 881
 882     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
 883     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 884
 885     at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
 886     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
 887     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
 888     at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
 889     at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
 890     at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
 891     at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
 892
 893     at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
 894     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
 895     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
 896     at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
 897     at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
 898     at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
 899     at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
 900     at24c_eeprom_init(i2c[28], 0x50, 256);
 901
 902     for (int i = 0; i < 8; i++) {
 903         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
 904         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
 905         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
 906         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
 907     }
 908 }
 909
 910 #define TYPE_TMP421 "tmp421"
 911
 912 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 913 {
 914     AspeedSoCState *soc = &bmc->soc;
 915     I2CBus *i2c[13] = {};
 916     for (int i = 0; i < 13; i++) {
 917         if ((i == 8) || (i == 11)) {
 918             continue;
 919         }
 920         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 921     }
 922
 923     /* Bus 0 - 5 all have the same config. */
 924     for (int i = 0; i < 6; i++) {
 925         /* Missing model: ti,ina230 @ 0x45 */
 926         /* Missing model: mps,mp5023 @ 0x40 */
 927         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
 928         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
 929         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
 930         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
 931         /* Missing model: fsc,fusb302 @ 0x22 */
 932     }
 933
 934     /* Bus 6 */
 935     at24c_eeprom_init(i2c[6], 0x56, 65536);
 936     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
 937     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
 938
 939
 940     /* Bus 7 */
 941     at24c_eeprom_init(i2c[7], 0x54, 65536);
 942
 943     /* Bus 9 */
 944     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
 945
 946     /* Bus 10 */
 947     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
 948     /* Missing model: ti,hdc1080 @ 0x40 */
 949     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
 950
 951     /* Bus 12 */
 952     /* Missing model: adi,adm1278 @ 0x11 */
 953     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
 954     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
 955     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 956 }
 957
 958 static void fby35_i2c_init(AspeedMachineState *bmc)
 959 {
 960     AspeedSoCState *soc = &bmc->soc;
 961     I2CBus *i2c[16];
 962
 963     for (int i = 0; i < 16; i++) {
 964         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
 965     }
 966
 967     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
 968     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
 969     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
 970     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
 971     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
 972     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 973
 974     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
 975     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
 976     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
 977                           fby35_nic_fruid_len);
 978     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
 979                           fby35_bb_fruid_len);
 980     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
 981                           fby35_bmc_fruid_len);
 982
 983     /*
 984      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
 985      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
 986      * each.
 987      */
 988 }
 989
 990 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 991 {
 992     AspeedSoCState *soc = &bmc->soc;
 993
 994     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 995 }
 996
 997 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 998 {
 999     AspeedSoCState *soc = &bmc->soc;
1000     I2CSlave *therm_mux, *cpuvr_mux;
1001
1002     /* Create the generic DC-SCM hardware */
1003     qcom_dc_scm_bmc_i2c_init(bmc);
1004
1005     /* Now create the Firework specific hardware */
1006
1007     /* I2C7 CPUVR MUX */
1008     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1009                                         "pca9546", 0x70);
1010     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1011     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1012     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1013     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1014
1015     /* I2C8 Thermal Diodes*/
1016     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1017                                         "pca9548", 0x70);
1018     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1019     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1020     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1021     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1022     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1023
1024     /* I2C9 Fan Controller (MAX31785) */
1025     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1026     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1027 }
1028
1029 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1030 {
1031     return ASPEED_MACHINE(obj)->mmio_exec;
1032 }
1033
1034 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1035 {
1036     ASPEED_MACHINE(obj)->mmio_exec = value;
1037 }
1038
1039 static void aspeed_machine_instance_init(Object *obj)
1040 {
1041     ASPEED_MACHINE(obj)->mmio_exec = false;
1042 }
1043
1044 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1045 {
1046     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1047     return g_strdup(bmc->fmc_model);
1048 }
1049
1050 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1051 {
1052     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1053
1054     g_free(bmc->fmc_model);
1055     bmc->fmc_model = g_strdup(value);
1056 }
1057
1058 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1059 {
1060     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1061     return g_strdup(bmc->spi_model);
1062 }
1063
1064 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1065 {
1066     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1067
1068     g_free(bmc->spi_model);
1069     bmc->spi_model = g_strdup(value);
1070 }
1071
1072 static void aspeed_machine_class_props_init(ObjectClass *oc)
1073 {
1074     object_class_property_add_bool(oc, "execute-in-place",
1075                                    aspeed_get_mmio_exec,
1076                                    aspeed_set_mmio_exec);
1077     object_class_property_set_description(oc, "execute-in-place",
1078                            "boot directly from CE0 flash device");
1079
1080     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1081                                    aspeed_set_fmc_model);
1082     object_class_property_set_description(oc, "fmc-model",
1083                                           "Change the FMC Flash model");
1084     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1085                                    aspeed_set_spi_model);
1086     object_class_property_set_description(oc, "spi-model",
1087                                           "Change the SPI Flash model");
1088 }
1089
1090 static int aspeed_soc_num_cpus(const char *soc_name)
1091 {
1092    AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1093    return sc->num_cpus;
1094 }
1095
1096 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1097 {
1098     MachineClass *mc = MACHINE_CLASS(oc);
1099     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1100
1101     mc->init = aspeed_machine_init;
1102     mc->no_floppy = 1;
1103     mc->no_cdrom = 1;
1104     mc->no_parallel = 1;
1105     mc->default_ram_id = "ram";
1106     amc->macs_mask = ASPEED_MAC0_ON;
1107     amc->uart_default = ASPEED_DEV_UART5;
1108
1109     aspeed_machine_class_props_init(oc);
1110 }
1111
1112 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1113 {
1114     MachineClass *mc = MACHINE_CLASS(oc);
1115     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1116
1117     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1118     amc->soc_name  = "ast2400-a1";
1119     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1120     amc->fmc_model = "n25q256a";
1121     amc->spi_model = "mx25l25635f";
1122     amc->num_cs    = 1;
1123     amc->i2c_init  = palmetto_bmc_i2c_init;
1124     mc->default_ram_size       = 256 * MiB;
1125     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1126         aspeed_soc_num_cpus(amc->soc_name);
1127 };
1128
1129 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1130 {
1131     MachineClass *mc = MACHINE_CLASS(oc);
1132     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1133
1134     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1135     amc->soc_name  = "ast2400-a1";
1136     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1137     amc->fmc_model = "n25q256a";
1138     amc->spi_model = "mx25l25635e";
1139     amc->num_cs    = 1;
1140     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1141     mc->default_ram_size       = 128 * MiB;
1142     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1143         aspeed_soc_num_cpus(amc->soc_name);
1144 }
1145
1146 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1147                                                         void *data)
1148 {
1149     MachineClass *mc = MACHINE_CLASS(oc);
1150     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1151
1152     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1153     amc->soc_name  = "ast2400-a1";
1154     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1155     amc->fmc_model = "mx25l25635e";
1156     amc->spi_model = "mx25l25635e";
1157     amc->num_cs    = 1;
1158     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1159     amc->i2c_init  = palmetto_bmc_i2c_init;
1160     mc->default_ram_size = 256 * MiB;
1161 }
1162
1163 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1164                                                             void *data)
1165 {
1166     MachineClass *mc = MACHINE_CLASS(oc);
1167     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1168
1169     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1170     amc->soc_name  = "ast2500-a1";
1171     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1172     amc->fmc_model = "mx25l25635e";
1173     amc->spi_model = "mx25l25635e";
1174     amc->num_cs    = 1;
1175     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1176     amc->i2c_init  = palmetto_bmc_i2c_init;
1177     mc->default_ram_size = 512 * MiB;
1178     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1179         aspeed_soc_num_cpus(amc->soc_name);
1180 }
1181
1182 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1183 {
1184     MachineClass *mc = MACHINE_CLASS(oc);
1185     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1186
1187     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1188     amc->soc_name  = "ast2500-a1";
1189     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1190     amc->fmc_model = "mx25l25635e";
1191     amc->spi_model = "mx25l25635f";
1192     amc->num_cs    = 1;
1193     amc->i2c_init  = ast2500_evb_i2c_init;
1194     mc->default_ram_size       = 512 * MiB;
1195     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1196         aspeed_soc_num_cpus(amc->soc_name);
1197 };
1198
1199 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1200 {
1201     MachineClass *mc = MACHINE_CLASS(oc);
1202     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1203
1204     mc->desc       = "Facebook YosemiteV2 BMC (ARM1176)";
1205     amc->soc_name  = "ast2500-a1";
1206     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1207     amc->hw_strap2 = 0;
1208     amc->fmc_model = "n25q256a";
1209     amc->spi_model = "mx25l25635e";
1210     amc->num_cs    = 2;
1211     amc->i2c_init  = yosemitev2_bmc_i2c_init;
1212     mc->default_ram_size       = 512 * MiB;
1213     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1214         aspeed_soc_num_cpus(amc->soc_name);
1215 };
1216
1217 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1218 {
1219     MachineClass *mc = MACHINE_CLASS(oc);
1220     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1221
1222     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1223     amc->soc_name  = "ast2500-a1";
1224     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1225     amc->fmc_model = "n25q256a";
1226     amc->spi_model = "mx66l1g45g";
1227     amc->num_cs    = 2;
1228     amc->i2c_init  = romulus_bmc_i2c_init;
1229     mc->default_ram_size       = 512 * MiB;
1230     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1231         aspeed_soc_num_cpus(amc->soc_name);
1232 };
1233
1234 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1235 {
1236     MachineClass *mc = MACHINE_CLASS(oc);
1237     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1238
1239     mc->desc       = "Facebook Tiogapass BMC (ARM1176)";
1240     amc->soc_name  = "ast2500-a1";
1241     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1242     amc->hw_strap2 = 0;
1243     amc->fmc_model = "n25q256a";
1244     amc->spi_model = "mx25l25635e";
1245     amc->num_cs    = 2;
1246     amc->i2c_init  = tiogapass_bmc_i2c_init;
1247     mc->default_ram_size       = 1 * GiB;
1248     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1249         aspeed_soc_num_cpus(amc->soc_name);
1250         aspeed_soc_num_cpus(amc->soc_name);
1251 };
1252
1253 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1254 {
1255     MachineClass *mc = MACHINE_CLASS(oc);
1256     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1257
1258     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1259     amc->soc_name  = "ast2500-a1";
1260     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1261     amc->fmc_model = "mx66l1g45g";
1262     amc->spi_model = "mx66l1g45g";
1263     amc->num_cs    = 2;
1264     amc->i2c_init  = sonorapass_bmc_i2c_init;
1265     mc->default_ram_size       = 512 * MiB;
1266     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1267         aspeed_soc_num_cpus(amc->soc_name);
1268 };
1269
1270 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1271 {
1272     MachineClass *mc = MACHINE_CLASS(oc);
1273     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1274
1275     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1276     amc->soc_name  = "ast2500-a1";
1277     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1278     amc->fmc_model = "mx25l25635f";
1279     amc->spi_model = "mx66l1g45g";
1280     amc->num_cs    = 2;
1281     amc->i2c_init  = witherspoon_bmc_i2c_init;
1282     mc->default_ram_size = 512 * MiB;
1283     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1284         aspeed_soc_num_cpus(amc->soc_name);
1285 };
1286
1287 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1288 {
1289     MachineClass *mc = MACHINE_CLASS(oc);
1290     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1291
1292     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1293     amc->soc_name  = "ast2600-a3";
1294     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1295     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1296     amc->fmc_model = "mx66u51235f";
1297     amc->spi_model = "mx66u51235f";
1298     amc->num_cs    = 1;
1299     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1300                      ASPEED_MAC3_ON;
1301     amc->i2c_init  = ast2600_evb_i2c_init;
1302     mc->default_ram_size = 1 * GiB;
1303     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1304         aspeed_soc_num_cpus(amc->soc_name);
1305 };
1306
1307 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1308 {
1309     MachineClass *mc = MACHINE_CLASS(oc);
1310     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1311
1312     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1313     amc->soc_name  = "ast2600-a3";
1314     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1315     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1316     amc->fmc_model = "mx66l1g45g";
1317     amc->spi_model = "mx66l1g45g";
1318     amc->num_cs    = 2;
1319     amc->macs_mask  = ASPEED_MAC2_ON;
1320     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1321     mc->default_ram_size = 1 * GiB;
1322     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1323         aspeed_soc_num_cpus(amc->soc_name);
1324 };
1325
1326 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1327 {
1328     MachineClass *mc = MACHINE_CLASS(oc);
1329     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1330
1331     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1332     amc->soc_name  = "ast2500-a1";
1333     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1334     amc->fmc_model = "n25q512a";
1335     amc->spi_model = "mx25l25635e";
1336     amc->num_cs    = 2;
1337     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1338     amc->i2c_init  = g220a_bmc_i2c_init;
1339     mc->default_ram_size = 1024 * MiB;
1340     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1341         aspeed_soc_num_cpus(amc->soc_name);
1342 };
1343
1344 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1345 {
1346     MachineClass *mc = MACHINE_CLASS(oc);
1347     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1348
1349     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1350     amc->soc_name  = "ast2500-a1";
1351     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1352     amc->fmc_model = "n25q512a";
1353     amc->spi_model = "mx25l25635e";
1354     amc->num_cs    = 2;
1355     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1356     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1357     mc->default_ram_size = 512 * MiB;
1358     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1359         aspeed_soc_num_cpus(amc->soc_name);
1360 };
1361
1362 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1363 {
1364     MachineClass *mc = MACHINE_CLASS(oc);
1365     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1366
1367     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1368     amc->soc_name  = "ast2600-a3";
1369     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1370     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1371     amc->fmc_model = "mx66l1g45g";
1372     amc->spi_model = "mx66l1g45g";
1373     amc->num_cs    = 2;
1374     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1375     amc->i2c_init  = rainier_bmc_i2c_init;
1376     mc->default_ram_size = 1 * GiB;
1377     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1378         aspeed_soc_num_cpus(amc->soc_name);
1379 };
1380
1381 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1382 #if HOST_LONG_BITS == 32
1383 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1384 #else
1385 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1386 #endif
1387
1388 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1389 {
1390     MachineClass *mc = MACHINE_CLASS(oc);
1391     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1392
1393     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1394     amc->soc_name = "ast2600-a3";
1395     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1396     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1397     amc->fmc_model = "mx66l1g45g";
1398     amc->spi_model = "mx66l1g45g";
1399     amc->num_cs = 2;
1400     amc->macs_mask = ASPEED_MAC3_ON;
1401     amc->i2c_init = fuji_bmc_i2c_init;
1402     amc->uart_default = ASPEED_DEV_UART1;
1403     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1404     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1405         aspeed_soc_num_cpus(amc->soc_name);
1406 };
1407
1408 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1409 #if HOST_LONG_BITS == 32
1410 #define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
1411 #else
1412 #define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
1413 #endif
1414
1415 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1416 {
1417     MachineClass *mc = MACHINE_CLASS(oc);
1418     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1419
1420     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1421     amc->soc_name  = "ast2600-a3";
1422     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1423     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1424     amc->fmc_model = "w25q01jvq";
1425     amc->spi_model = NULL;
1426     amc->num_cs    = 2;
1427     amc->macs_mask = ASPEED_MAC2_ON;
1428     amc->i2c_init  = bletchley_bmc_i2c_init;
1429     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1430     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1431         aspeed_soc_num_cpus(amc->soc_name);
1432 }
1433
1434 static void fby35_reset(MachineState *state, ShutdownCause reason)
1435 {
1436     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1437     AspeedGPIOState *gpio = &bmc->soc.gpio;
1438
1439     qemu_devices_reset(reason);
1440
1441     /* Board ID: 7 (Class-1, 4 slots) */
1442     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1443     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1444     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1445     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1446
1447     /* Slot presence pins, inverse polarity. (False means present) */
1448     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1449     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1450     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1451     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1452
1453     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1454     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1455     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1456     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1457     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1458 }
1459
1460 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1461 {
1462     MachineClass *mc = MACHINE_CLASS(oc);
1463     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1464
1465     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1466     mc->reset      = fby35_reset;
1467     amc->fmc_model = "mx66l1g45g";
1468     amc->num_cs    = 2;
1469     amc->macs_mask = ASPEED_MAC3_ON;
1470     amc->i2c_init  = fby35_i2c_init;
1471     /* FIXME: Replace this macro with something more general */
1472     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1473 }
1474
1475 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1476 /* Main SYSCLK frequency in Hz (200MHz) */
1477 #define SYSCLK_FRQ 200000000ULL
1478
1479 static void aspeed_minibmc_machine_init(MachineState *machine)
1480 {
1481     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1482     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1483     Clock *sysclk;
1484
1485     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1486     clock_set_hz(sysclk, SYSCLK_FRQ);
1487
1488     object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1489     qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1490
1491     object_property_set_link(OBJECT(&bmc->soc), "memory",
1492                              OBJECT(get_system_memory()), &error_abort);
1493     connect_serial_hds_to_uarts(bmc);
1494     qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1495
1496     aspeed_board_init_flashes(&bmc->soc.fmc,
1497                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1498                               amc->num_cs,
1499                               0);
1500
1501     aspeed_board_init_flashes(&bmc->soc.spi[0],
1502                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1503                               amc->num_cs, amc->num_cs);
1504
1505     aspeed_board_init_flashes(&bmc->soc.spi[1],
1506                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
1507                               amc->num_cs, (amc->num_cs * 2));
1508
1509     if (amc->i2c_init) {
1510         amc->i2c_init(bmc);
1511     }
1512
1513     armv7m_load_kernel(ARM_CPU(first_cpu),
1514                        machine->kernel_filename,
1515                        0,
1516                        AST1030_INTERNAL_FLASH_SIZE);
1517 }
1518
1519 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1520 {
1521     AspeedSoCState *soc = &bmc->soc;
1522
1523     /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1524     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1525     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1526
1527     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1528     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1529 }
1530
1531 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1532                                                           void *data)
1533 {
1534     MachineClass *mc = MACHINE_CLASS(oc);
1535     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1536
1537     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1538     amc->soc_name = "ast1030-a1";
1539     amc->hw_strap1 = 0;
1540     amc->hw_strap2 = 0;
1541     mc->init = aspeed_minibmc_machine_init;
1542     amc->i2c_init = ast1030_evb_i2c_init;
1543     mc->default_ram_size = 0;
1544     mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1545     amc->fmc_model = "sst25vf032b";
1546     amc->spi_model = "sst25vf032b";
1547     amc->num_cs = 2;
1548     amc->macs_mask = 0;
1549 }
1550
1551 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1552                                                      void *data)
1553 {
1554     MachineClass *mc = MACHINE_CLASS(oc);
1555     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1556
1557     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1558     amc->soc_name  = "ast2600-a3";
1559     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1560     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1561     amc->fmc_model = "n25q512a";
1562     amc->spi_model = "n25q512a";
1563     amc->num_cs    = 2;
1564     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1565     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1566     mc->default_ram_size = 1 * GiB;
1567     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1568         aspeed_soc_num_cpus(amc->soc_name);
1569 };
1570
1571 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1572                                                     void *data)
1573 {
1574     MachineClass *mc = MACHINE_CLASS(oc);
1575     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1576
1577     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1578     amc->soc_name  = "ast2600-a3";
1579     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1580     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1581     amc->fmc_model = "n25q512a";
1582     amc->spi_model = "n25q512a";
1583     amc->num_cs    = 2;
1584     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1585     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1586     mc->default_ram_size = 1 * GiB;
1587     mc->default_cpus = mc->min_cpus = mc->max_cpus =
1588         aspeed_soc_num_cpus(amc->soc_name);
1589 };
1590
1591 static const TypeInfo aspeed_machine_types[] = {
1592     {
1593         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1594         .parent        = TYPE_ASPEED_MACHINE,
1595         .class_init    = aspeed_machine_palmetto_class_init,
1596     }, {
1597         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1598         .parent        = TYPE_ASPEED_MACHINE,
1599         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1600     }, {
1601         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1602         .parent        = TYPE_ASPEED_MACHINE,
1603         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1604     }, {
1605         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1606         .parent        = TYPE_ASPEED_MACHINE,
1607         .class_init    = aspeed_machine_ast2500_evb_class_init,
1608     }, {
1609         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1610         .parent        = TYPE_ASPEED_MACHINE,
1611         .class_init    = aspeed_machine_romulus_class_init,
1612     }, {
1613         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1614         .parent        = TYPE_ASPEED_MACHINE,
1615         .class_init    = aspeed_machine_sonorapass_class_init,
1616     }, {
1617         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1618         .parent        = TYPE_ASPEED_MACHINE,
1619         .class_init    = aspeed_machine_witherspoon_class_init,
1620     }, {
1621         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1622         .parent        = TYPE_ASPEED_MACHINE,
1623         .class_init    = aspeed_machine_ast2600_evb_class_init,
1624     }, {
1625         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1626         .parent        = TYPE_ASPEED_MACHINE,
1627         .class_init    = aspeed_machine_yosemitev2_class_init,
1628     }, {
1629         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1630         .parent        = TYPE_ASPEED_MACHINE,
1631         .class_init    = aspeed_machine_tacoma_class_init,
1632     }, {
1633         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
1634         .parent        = TYPE_ASPEED_MACHINE,
1635         .class_init    = aspeed_machine_tiogapass_class_init,
1636     }, {
1637         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1638         .parent        = TYPE_ASPEED_MACHINE,
1639         .class_init    = aspeed_machine_g220a_class_init,
1640     }, {
1641         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1642         .parent        = TYPE_ASPEED_MACHINE,
1643         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1644     }, {
1645         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1646         .parent        = TYPE_ASPEED_MACHINE,
1647         .class_init    = aspeed_machine_qcom_firework_class_init,
1648     }, {
1649         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1650         .parent        = TYPE_ASPEED_MACHINE,
1651         .class_init    = aspeed_machine_fp5280g2_class_init,
1652     }, {
1653         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1654         .parent        = TYPE_ASPEED_MACHINE,
1655         .class_init    = aspeed_machine_quanta_q71l_class_init,
1656     }, {
1657         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1658         .parent        = TYPE_ASPEED_MACHINE,
1659         .class_init    = aspeed_machine_rainier_class_init,
1660     }, {
1661         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1662         .parent        = TYPE_ASPEED_MACHINE,
1663         .class_init    = aspeed_machine_fuji_class_init,
1664     }, {
1665         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1666         .parent        = TYPE_ASPEED_MACHINE,
1667         .class_init    = aspeed_machine_bletchley_class_init,
1668     }, {
1669         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1670         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1671         .class_init    = aspeed_machine_fby35_class_init,
1672     }, {
1673         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1674         .parent         = TYPE_ASPEED_MACHINE,
1675         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1676     }, {
1677         .name          = TYPE_ASPEED_MACHINE,
1678         .parent        = TYPE_MACHINE,
1679         .instance_size = sizeof(AspeedMachineState),
1680         .instance_init = aspeed_machine_instance_init,
1681         .class_size    = sizeof(AspeedMachineClass),
1682         .class_init    = aspeed_machine_class_init,
1683         .abstract      = true,
1684     }
1685 };
1686
1687 DEFINE_TYPES(aspeed_machine_types)